From 4dbedf43d26276f6d7c8c3146d0a5b2f0309d968 Mon Sep 17 00:00:00 2001 From: Nathan Williams Date: Wed, 25 Mar 2009 20:27:37 +1100 Subject: solos: support new FPGA RAM layout Buffer sizes have been changed to 2048 bytes. Flash upgrades use a dedicated RAM block. Add support for daughterboard. Signed-off-by: Nathan Williams Signed-off-by: David Woodhouse diff --git a/drivers/atm/solos-pci.c b/drivers/atm/solos-pci.c index bc3079d..bfef8d2 100644 --- a/drivers/atm/solos-pci.c +++ b/drivers/atm/solos-pci.c @@ -59,21 +59,29 @@ #define RX_DMA_ADDR(port) (0x30 + (4 * (port))) #define DATA_RAM_SIZE 32768 -#define BUF_SIZE 4096 +#define BUF_SIZE 2048 +#define OLD_BUF_SIZE 4096 /* For FPGA versions <= 2*/ #define FPGA_PAGE 528 /* FPGA flash page size*/ #define SOLOS_PAGE 512 /* Solos flash page size*/ #define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/ #define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/ -#define RX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2) -#define TX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2 + BUF_SIZE) +#define RX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2) +#define TX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2 + (card->buffer_size)) +#define FLASH_BUF ((card->buffers) + 4*(card->buffer_size)*2) #define RX_DMA_SIZE 2048 +#define FPGA_VERSION(a,b) (((a) << 8) + (b)) +#define LEGACY_BUFFERS 2 +#define DMA_SUPPORTED 4 + static int reset = 0; static int atmdebug = 0; static int firmware_upgrade = 0; static int fpga_upgrade = 0; +static int db_firmware_upgrade = 0; +static int db_fpga_upgrade = 0; struct pkt_hdr { __le16 size; @@ -116,6 +124,8 @@ struct solos_card { wait_queue_head_t param_wq; wait_queue_head_t fw_wq; int using_dma; + int fpga_version; + int buffer_size; }; @@ -136,10 +146,14 @@ MODULE_PARM_DESC(reset, "Reset Solos chips on startup"); MODULE_PARM_DESC(atmdebug, "Print ATM data"); MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade"); MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade"); +MODULE_PARM_DESC(db_firmware_upgrade, "Initiate daughter board Solos firmware upgrade"); +MODULE_PARM_DESC(db_fpga_upgrade, "Initiate daughter board FPGA upgrade"); module_param(reset, int, 0444); module_param(atmdebug, int, 0644); module_param(firmware_upgrade, int, 0444); module_param(fpga_upgrade, int, 0444); +module_param(db_firmware_upgrade, int, 0444); +module_param(db_fpga_upgrade, int, 0444); static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb, struct atm_vcc *vcc); @@ -517,10 +531,32 @@ static int flash_upgrade(struct solos_card *card, int chip) if (chip == 0) { fw_name = "solos-FPGA.bin"; blocksize = FPGA_BLOCK; - } else { + } + + if (chip == 1) { fw_name = "solos-Firmware.bin"; blocksize = SOLOS_BLOCK; } + + if (chip == 2){ + if (card->fpga_version > LEGACY_BUFFERS){ + fw_name = "solos-db-FPGA.bin"; + blocksize = FPGA_BLOCK; + } else { + dev_info(&card->dev->dev, "FPGA version doesn't support daughter board upgrades\n"); + return -EPERM; + } + } + + if (chip == 3){ + if (card->fpga_version > LEGACY_BUFFERS){ + fw_name = "solos-Firmware.bin"; + blocksize = SOLOS_BLOCK; + } else { + dev_info(&card->dev->dev, "FPGA version doesn't support daughter board upgrades\n"); + return -EPERM; + } + } if (request_firmware(&fw, fw_name, &card->dev->dev)) return -ENOENT; @@ -536,8 +572,10 @@ static int flash_upgrade(struct solos_card *card, int chip) data32 = ioread32(card->config_regs + FPGA_MODE); /* Set mode to Chip Erase */ - dev_info(&card->dev->dev, "Set FPGA Flash mode to %s Chip Erase\n", - chip?"Solos":"FPGA"); + if(chip == 0 || chip == 2) + dev_info(&card->dev->dev, "Set FPGA Flash mode to FPGA Chip Erase\n"); + if(chip == 1 || chip == 3) + dev_info(&card->dev->dev, "Set FPGA Flash mode to Solos Chip Erase\n"); iowrite32((chip * 2), card->config_regs + FLASH_MODE); @@ -557,7 +595,10 @@ static int flash_upgrade(struct solos_card *card, int chip) /* Copy block to buffer, swapping each 16 bits */ for(i = 0; i < blocksize; i += 4) { uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i)); - iowrite32(word, RX_BUF(card, 3) + i); + if(card->fpga_version > LEGACY_BUFFERS) + iowrite32(word, FLASH_BUF + i); + else + iowrite32(word, RX_BUF(card, 3) + i); } /* Specify block number and then trigger flash write */ @@ -1094,12 +1135,18 @@ static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id) fpga_ver = (data32 & 0x0000FFFF); major_ver = ((data32 & 0xFF000000) >> 24); minor_ver = ((data32 & 0x00FF0000) >> 16); + card->fpga_version = FPGA_VERSION(major_ver,minor_ver); + if (card->fpga_version > LEGACY_BUFFERS) + card->buffer_size = BUF_SIZE; + else + card->buffer_size = OLD_BUF_SIZE; dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n", major_ver, minor_ver, fpga_ver); - if (0 && fpga_ver > 27) + if (card->fpga_version >= DMA_SUPPORTED){ card->using_dma = 1; - else { + } else { + card->using_dma = 0; /* Set RX empty flag for all ports */ iowrite32(0xF0, card->config_regs + FLAGS_ADDR); } @@ -1131,6 +1178,12 @@ static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id) if (firmware_upgrade) flash_upgrade(card, 1); + if (db_fpga_upgrade) + flash_upgrade(card, 2); + + if (db_firmware_upgrade) + flash_upgrade(card, 3); + err = atm_init(card); if (err) goto out_free_irq; -- cgit v0.10.2 From 78f857f265241dfa6f343d75b45e8b30935f71df Mon Sep 17 00:00:00 2001 From: Nathan Williams Date: Wed, 25 Mar 2009 20:33:42 +1100 Subject: solos: Check for rogue received packets Sometimes there can be received packets with the size field set to 0xFFFF. This seems to only occur after an FPGA or firmware upgrade. This patch discards packets with an invalid size. Signed-off-by: Nathan Williams Signed-off-by: David Woodhouse diff --git a/drivers/atm/solos-pci.c b/drivers/atm/solos-pci.c index bfef8d2..6c82834 100644 --- a/drivers/atm/solos-pci.c +++ b/drivers/atm/solos-pci.c @@ -671,6 +671,10 @@ void solos_bh(unsigned long card_arg) memcpy_fromio(header, RX_BUF(card, port), sizeof(*header)); size = le16_to_cpu(header->size); + if (size > (card->buffer_size - sizeof(*header))){ + dev_warn(&card->dev->dev, "Invalid buffer size\n"); + continue; + } skb = alloc_skb(size + 1, GFP_ATOMIC); if (!skb) { -- cgit v0.10.2 From 099f53cb50e45ef617a9f1d63ceec799e489418b Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 8 Apr 2009 14:28:37 -0700 Subject: async_tx: rename zero_sum to val 'zero_sum' does not properly describe the operation of generating parity and checking that it validates against an existing buffer. Change the name of the operation to 'val' (for 'validate'). This is in anticipation of the p+q case where it is a requirement to identify the target parity buffers separately from the source buffers, because the target parity buffers will not have corresponding pq coefficients. Reviewed-by: Andre Noll Acked-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/Documentation/crypto/async-tx-api.txt b/Documentation/crypto/async-tx-api.txt index 9f59fcb..4af1218 100644 --- a/Documentation/crypto/async-tx-api.txt +++ b/Documentation/crypto/async-tx-api.txt @@ -61,13 +61,13 @@ async_(, void *callback_parameter); 3.2 Supported operations: -memcpy - memory copy between a source and a destination buffer -memset - fill a destination buffer with a byte value -xor - xor a series of source buffers and write the result to a - destination buffer -xor_zero_sum - xor a series of source buffers and set a flag if the - result is zero. The implementation attempts to prevent - writes to memory +memcpy - memory copy between a source and a destination buffer +memset - fill a destination buffer with a byte value +xor - xor a series of source buffers and write the result to a + destination buffer +xor_val - xor a series of source buffers and set a flag if the + result is zero. The implementation attempts to prevent + writes to memory 3.3 Descriptor management: The return value is non-NULL and points to a 'descriptor' when the operation diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c index cfd4d2e..9800228 100644 --- a/arch/arm/mach-iop13xx/setup.c +++ b/arch/arm/mach-iop13xx/setup.c @@ -478,7 +478,7 @@ void __init iop13xx_platform_init(void) dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); dma_cap_set(DMA_XOR, plat_data->cap_mask); dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); - dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask); + dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); dma_cap_set(DMA_MEMSET, plat_data->cap_mask); dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); @@ -490,7 +490,7 @@ void __init iop13xx_platform_init(void) dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); dma_cap_set(DMA_XOR, plat_data->cap_mask); dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); - dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask); + dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); dma_cap_set(DMA_MEMSET, plat_data->cap_mask); dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); @@ -502,13 +502,13 @@ void __init iop13xx_platform_init(void) dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); dma_cap_set(DMA_XOR, plat_data->cap_mask); dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); - dma_cap_set(DMA_ZERO_SUM, plat_data->cap_mask); + dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); dma_cap_set(DMA_MEMSET, plat_data->cap_mask); dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); dma_cap_set(DMA_PQ_XOR, plat_data->cap_mask); dma_cap_set(DMA_PQ_UPDATE, plat_data->cap_mask); - dma_cap_set(DMA_PQ_ZERO_SUM, plat_data->cap_mask); + dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask); break; } } diff --git a/arch/arm/plat-iop/adma.c b/arch/arm/plat-iop/adma.c index f724208..c040044 100644 --- a/arch/arm/plat-iop/adma.c +++ b/arch/arm/plat-iop/adma.c @@ -198,7 +198,7 @@ static int __init iop3xx_adma_cap_init(void) dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask); #else dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask); - dma_cap_set(DMA_ZERO_SUM, iop3xx_aau_data.cap_mask); + dma_cap_set(DMA_XOR_VAL, iop3xx_aau_data.cap_mask); dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask); dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask); #endif diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index 95fe2c8..e0580b0 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c @@ -222,7 +222,7 @@ static int page_is_zero(struct page *p, unsigned int offset, size_t len) } /** - * async_xor_zero_sum - attempt a xor parity check with a dma engine. + * async_xor_val - attempt a xor parity check with a dma engine. * @dest: destination page used if the xor is performed synchronously * @src_list: array of source pages. The dest page must be listed as a source * at index zero. The contents of this array may be overwritten. @@ -236,13 +236,13 @@ static int page_is_zero(struct page *p, unsigned int offset, size_t len) * @cb_param: parameter to pass to the callback routine */ struct dma_async_tx_descriptor * -async_xor_zero_sum(struct page *dest, struct page **src_list, +async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, int src_cnt, size_t len, u32 *result, enum async_tx_flags flags, struct dma_async_tx_descriptor *depend_tx, dma_async_tx_callback cb_fn, void *cb_param) { - struct dma_chan *chan = async_tx_find_channel(depend_tx, DMA_ZERO_SUM, + struct dma_chan *chan = async_tx_find_channel(depend_tx, DMA_XOR_VAL, &dest, 1, src_list, src_cnt, len); struct dma_device *device = chan ? chan->device : NULL; @@ -261,15 +261,15 @@ async_xor_zero_sum(struct page *dest, struct page **src_list, dma_src[i] = dma_map_page(device->dev, src_list[i], offset, len, DMA_TO_DEVICE); - tx = device->device_prep_dma_zero_sum(chan, dma_src, src_cnt, - len, result, - dma_prep_flags); + tx = device->device_prep_dma_xor_val(chan, dma_src, src_cnt, + len, result, + dma_prep_flags); if (unlikely(!tx)) { async_tx_quiesce(&depend_tx); while (!tx) { dma_async_issue_pending(chan); - tx = device->device_prep_dma_zero_sum(chan, + tx = device->device_prep_dma_xor_val(chan, dma_src, src_cnt, len, result, dma_prep_flags); } @@ -296,7 +296,7 @@ async_xor_zero_sum(struct page *dest, struct page **src_list, return tx; } -EXPORT_SYMBOL_GPL(async_xor_zero_sum); +EXPORT_SYMBOL_GPL(async_xor_val); static int __init async_xor_init(void) { diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 92438e9..6781e8f 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -644,8 +644,8 @@ int dma_async_device_register(struct dma_device *device) !device->device_prep_dma_memcpy); BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) && !device->device_prep_dma_xor); - BUG_ON(dma_has_cap(DMA_ZERO_SUM, device->cap_mask) && - !device->device_prep_dma_zero_sum); + BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) && + !device->device_prep_dma_xor_val); BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) && !device->device_prep_dma_memset); BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) && diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index 2f05226..6ff79a6 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c @@ -660,9 +660,9 @@ iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest, } static struct dma_async_tx_descriptor * -iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src, - unsigned int src_cnt, size_t len, u32 *result, - unsigned long flags) +iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src, + unsigned int src_cnt, size_t len, u32 *result, + unsigned long flags) { struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); struct iop_adma_desc_slot *sw_desc, *grp_start; @@ -906,7 +906,7 @@ out: #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */ static int __devinit -iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device) +iop_adma_xor_val_self_test(struct iop_adma_device *device) { int i, src_idx; struct page *dest; @@ -1002,7 +1002,7 @@ iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device) PAGE_SIZE, DMA_TO_DEVICE); /* skip zero sum if the capability is not present */ - if (!dma_has_cap(DMA_ZERO_SUM, dma_chan->device->cap_mask)) + if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) goto free_resources; /* zero sum the sources with the destintation page */ @@ -1016,10 +1016,10 @@ iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device) dma_srcs[i] = dma_map_page(dma_chan->device->dev, zero_sum_srcs[i], 0, PAGE_SIZE, DMA_TO_DEVICE); - tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs, - IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, - &zero_sum_result, - DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs, + IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, + &zero_sum_result, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); cookie = iop_adma_tx_submit(tx); iop_adma_issue_pending(dma_chan); @@ -1072,10 +1072,10 @@ iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device) dma_srcs[i] = dma_map_page(dma_chan->device->dev, zero_sum_srcs[i], 0, PAGE_SIZE, DMA_TO_DEVICE); - tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs, - IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, - &zero_sum_result, - DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs, + IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, + &zero_sum_result, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); cookie = iop_adma_tx_submit(tx); iop_adma_issue_pending(dma_chan); @@ -1192,9 +1192,9 @@ static int __devinit iop_adma_probe(struct platform_device *pdev) dma_dev->max_xor = iop_adma_get_max_xor(); dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor; } - if (dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask)) - dma_dev->device_prep_dma_zero_sum = - iop_adma_prep_dma_zero_sum; + if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask)) + dma_dev->device_prep_dma_xor_val = + iop_adma_prep_dma_xor_val; if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) dma_dev->device_prep_dma_interrupt = iop_adma_prep_dma_interrupt; @@ -1249,7 +1249,7 @@ static int __devinit iop_adma_probe(struct platform_device *pdev) if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) || dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) { - ret = iop_adma_xor_zero_sum_self_test(adev); + ret = iop_adma_xor_val_self_test(adev); dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); if (ret) goto err_free_iop_chan; @@ -1259,10 +1259,10 @@ static int __devinit iop_adma_probe(struct platform_device *pdev) "( %s%s%s%s%s%s%s%s%s%s)\n", dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "", dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "", - dma_has_cap(DMA_PQ_ZERO_SUM, dma_dev->cap_mask) ? "pq_zero_sum " : "", + dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "", dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "", - dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask) ? "xor_zero_sum " : "", + dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "", dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "", dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "", dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 3bbc6d6..f8d2d35 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -854,7 +854,7 @@ static void ops_run_check(struct stripe_head *sh) xor_srcs[count++] = dev->page; } - tx = async_xor_zero_sum(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, + tx = async_xor_val(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, &sh->ops.zero_sum_result, 0, NULL, NULL, NULL); atomic_inc(&sh->count); diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index 5fc2ef8..513150d 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h @@ -117,7 +117,7 @@ async_xor(struct page *dest, struct page **src_list, unsigned int offset, dma_async_tx_callback cb_fn, void *cb_fn_param); struct dma_async_tx_descriptor * -async_xor_zero_sum(struct page *dest, struct page **src_list, +async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, int src_cnt, size_t len, u32 *result, enum async_tx_flags flags, struct dma_async_tx_descriptor *depend_tx, diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 2e2aa3d..6768727 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -55,8 +55,8 @@ enum dma_transaction_type { DMA_PQ_XOR, DMA_DUAL_XOR, DMA_PQ_UPDATE, - DMA_ZERO_SUM, - DMA_PQ_ZERO_SUM, + DMA_XOR_VAL, + DMA_PQ_VAL, DMA_MEMSET, DMA_MEMCPY_CRC32C, DMA_INTERRUPT, @@ -214,7 +214,7 @@ struct dma_async_tx_descriptor { * @device_free_chan_resources: release DMA channel's resources * @device_prep_dma_memcpy: prepares a memcpy operation * @device_prep_dma_xor: prepares a xor operation - * @device_prep_dma_zero_sum: prepares a zero_sum operation + * @device_prep_dma_xor_val: prepares a xor validation operation * @device_prep_dma_memset: prepares a memset operation * @device_prep_dma_interrupt: prepares an end of chain interrupt operation * @device_prep_slave_sg: prepares a slave dma operation @@ -243,7 +243,7 @@ struct dma_device { struct dma_async_tx_descriptor *(*device_prep_dma_xor)( struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt, size_t len, unsigned long flags); - struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( + struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, size_t len, u32 *result, unsigned long flags); struct dma_async_tx_descriptor *(*device_prep_dma_memset)( -- cgit v0.10.2 From a3434660e5b47ab90387b017e311437bb3a88083 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Thu, 30 Apr 2009 15:38:01 +0100 Subject: solos: Add some margin-related parameters Signed-off-by: David Woodhouse diff --git a/drivers/atm/solos-attrlist.c b/drivers/atm/solos-attrlist.c index efa2808..9467263 100644 --- a/drivers/atm/solos-attrlist.c +++ b/drivers/atm/solos-attrlist.c @@ -62,6 +62,13 @@ SOLOS_ATTR_RW(Defaults) SOLOS_ATTR_RW(LineMode) SOLOS_ATTR_RW(Profile) SOLOS_ATTR_RW(DetectNoise) +SOLOS_ATTR_RW(BisAForceSNRMarginDn) +SOLOS_ATTR_RW(BisMForceSNRMarginDn) +SOLOS_ATTR_RW(BisAMaxMargin) +SOLOS_ATTR_RW(BisMMaxMargin) +SOLOS_ATTR_RW(AnnexAForceSNRMarginDn) +SOLOS_ATTR_RW(AnnexAMaxMargin) +SOLOS_ATTR_RW(AnnexMMaxMargin) SOLOS_ATTR_RO(SupportedAnnexes) SOLOS_ATTR_RO(Status) SOLOS_ATTR_RO(TotalStart) -- cgit v0.10.2 From 69a9ceab83928e743fafbba5b98bd09aed7c0e0d Mon Sep 17 00:00:00 2001 From: Simon Farnsworth Date: Thu, 7 May 2009 19:43:42 +0100 Subject: solos: Show Interleaving details for ADSL2 and 2+ InterleaveRDn and InterleaveRUp only apply to G.dmt. The equivalents for ADSL2 and 2+ are BisRDn and BisRUp. In addition, the INPdown and INPup statuses are useful when trying to track down instability on a line. Signed-off-by: Simon Farnsworth Signed-off-by: David Woodhouse diff --git a/drivers/atm/solos-attrlist.c b/drivers/atm/solos-attrlist.c index 9467263..1a9332e 100644 --- a/drivers/atm/solos-attrlist.c +++ b/drivers/atm/solos-attrlist.c @@ -25,6 +25,10 @@ SOLOS_ATTR_RO(RSCorrectedErrorsUp) SOLOS_ATTR_RO(RSUnCorrectedErrorsUp) SOLOS_ATTR_RO(InterleaveRDn) SOLOS_ATTR_RO(InterleaveRUp) +SOLOS_ATTR_RO(BisRDn) +SOLOS_ATTR_RO(BisRUp) +SOLOS_ATTR_RO(INPdown) +SOLOS_ATTR_RO(INPup) SOLOS_ATTR_RO(ShowtimeStart) SOLOS_ATTR_RO(ATURVendor) SOLOS_ATTR_RO(ATUCCountry) -- cgit v0.10.2 From 88ba2aa586c874681c072101287e15d40de7e6e2 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Thu, 9 Apr 2009 16:16:18 -0700 Subject: async_tx: kill ASYNC_TX_DEP_ACK flag In support of inter-channel chaining async_tx utilizes an ack flag to gate whether a dependent operation can be chained to another. While the flag is not set the chain can be considered open for appending. Setting the ack flag closes the chain and flags the descriptor for garbage collection. The ASYNC_TX_DEP_ACK flag essentially means "close the chain after adding this dependency". Since each operation can only have one child the api now implicitly sets the ack flag at dependency submission time. This removes an unnecessary management burden from clients of the api. [ Impact: clean up and enforce one dependency per operation ] Reviewed-by: Andre Noll Acked-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/Documentation/crypto/async-tx-api.txt b/Documentation/crypto/async-tx-api.txt index 4af1218..76feda8 100644 --- a/Documentation/crypto/async-tx-api.txt +++ b/Documentation/crypto/async-tx-api.txt @@ -80,8 +80,8 @@ acknowledged by the application before the offload engine driver is allowed to recycle (or free) the descriptor. A descriptor can be acked by one of the following methods: 1/ setting the ASYNC_TX_ACK flag if no child operations are to be submitted -2/ setting the ASYNC_TX_DEP_ACK flag to acknowledge the parent - descriptor of a new operation. +2/ submitting an unacknowledged descriptor as a dependency to another + async_tx call will implicitly set the acknowledged state. 3/ calling async_tx_ack() on the descriptor. 3.4 When does the operation execute? @@ -136,10 +136,9 @@ int run_xor_copy_xor(struct page **xor_srcs, tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, ASYNC_TX_XOR_DROP_DST, NULL, NULL, NULL); - tx = async_memcpy(copy_dest, copy_src, 0, 0, copy_len, - ASYNC_TX_DEP_ACK, tx, NULL, NULL); + tx = async_memcpy(copy_dest, copy_src, 0, 0, copy_len, tx, NULL, NULL); tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, - ASYNC_TX_XOR_DROP_DST | ASYNC_TX_DEP_ACK | ASYNC_TX_ACK, + ASYNC_TX_XOR_DROP_DST | ASYNC_TX_ACK, tx, complete_xor_copy_xor, NULL); async_tx_issue_pending_all(); diff --git a/crypto/async_tx/async_memcpy.c b/crypto/async_tx/async_memcpy.c index ddccfb0..7117ec6 100644 --- a/crypto/async_tx/async_memcpy.c +++ b/crypto/async_tx/async_memcpy.c @@ -35,7 +35,7 @@ * @src: src page * @offset: offset in pages to start transaction * @len: length in bytes - * @flags: ASYNC_TX_ACK, ASYNC_TX_DEP_ACK, + * @flags: ASYNC_TX_ACK * @depend_tx: memcpy depends on the result of this transaction * @cb_fn: function to call when the memcpy completes * @cb_param: parameter to pass to the callback routine diff --git a/crypto/async_tx/async_memset.c b/crypto/async_tx/async_memset.c index 5b5eb99..b2f1338 100644 --- a/crypto/async_tx/async_memset.c +++ b/crypto/async_tx/async_memset.c @@ -35,7 +35,7 @@ * @val: fill value * @offset: offset in pages to start transaction * @len: length in bytes - * @flags: ASYNC_TX_ACK, ASYNC_TX_DEP_ACK + * @flags: ASYNC_TX_ACK * @depend_tx: memset depends on the result of this transaction * @cb_fn: function to call when the memcpy completes * @cb_param: parameter to pass to the callback routine diff --git a/crypto/async_tx/async_tx.c b/crypto/async_tx/async_tx.c index 06eb6cc..3766bc3 100644 --- a/crypto/async_tx/async_tx.c +++ b/crypto/async_tx/async_tx.c @@ -223,7 +223,7 @@ async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, if (flags & ASYNC_TX_ACK) async_tx_ack(tx); - if (depend_tx && (flags & ASYNC_TX_DEP_ACK)) + if (depend_tx) async_tx_ack(depend_tx); } EXPORT_SYMBOL_GPL(async_tx_submit); @@ -231,7 +231,7 @@ EXPORT_SYMBOL_GPL(async_tx_submit); /** * async_trigger_callback - schedules the callback function to be run after * any dependent operations have been completed. - * @flags: ASYNC_TX_ACK, ASYNC_TX_DEP_ACK + * @flags: ASYNC_TX_ACK * @depend_tx: 'callback' requires the completion of this transaction * @cb_fn: function to call after depend_tx completes * @cb_param: parameter to pass to the callback routine diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index e0580b0..3cc5dc7 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c @@ -105,7 +105,6 @@ do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, _cb_param); depend_tx = tx; - flags |= ASYNC_TX_DEP_ACK; if (src_cnt > xor_src_cnt) { /* drop completed sources */ @@ -168,8 +167,7 @@ do_sync_xor(struct page *dest, struct page **src_list, unsigned int offset, * @offset: offset in pages to start transaction * @src_cnt: number of source pages * @len: length in bytes - * @flags: ASYNC_TX_XOR_ZERO_DST, ASYNC_TX_XOR_DROP_DEST, - * ASYNC_TX_ACK, ASYNC_TX_DEP_ACK + * @flags: ASYNC_TX_XOR_ZERO_DST, ASYNC_TX_XOR_DROP_DEST, ASYNC_TX_ACK * @depend_tx: xor depends on the result of this transaction. * @cb_fn: function to call when the xor completes * @cb_param: parameter to pass to the callback routine @@ -230,7 +228,7 @@ static int page_is_zero(struct page *p, unsigned int offset, size_t len) * @src_cnt: number of source pages * @len: length in bytes * @result: 0 if sum == 0 else non-zero - * @flags: ASYNC_TX_ACK, ASYNC_TX_DEP_ACK + * @flags: ASYNC_TX_ACK * @depend_tx: xor depends on the result of this transaction. * @cb_fn: function to call when the xor completes * @cb_param: parameter to pass to the callback routine diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index f8d2d35..0ef5362 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -525,14 +525,12 @@ async_copy_data(int frombio, struct bio *bio, struct page *page, bio_page = bio_iovec_idx(bio, i)->bv_page; if (frombio) tx = async_memcpy(page, bio_page, page_offset, - b_offset, clen, - ASYNC_TX_DEP_ACK, - tx, NULL, NULL); + b_offset, clen, 0, + tx, NULL, NULL); else tx = async_memcpy(bio_page, page, b_offset, - page_offset, clen, - ASYNC_TX_DEP_ACK, - tx, NULL, NULL); + page_offset, clen, 0, + tx, NULL, NULL); } if (clen < len) /* hit end of page */ break; @@ -615,8 +613,7 @@ static void ops_run_biofill(struct stripe_head *sh) } atomic_inc(&sh->count); - async_trigger_callback(ASYNC_TX_DEP_ACK | ASYNC_TX_ACK, tx, - ops_complete_biofill, sh); + async_trigger_callback(ASYNC_TX_ACK, tx, ops_complete_biofill, sh); } static void ops_complete_compute5(void *stripe_head_ref) @@ -701,8 +698,8 @@ ops_run_prexor(struct stripe_head *sh, struct dma_async_tx_descriptor *tx) } tx = async_xor(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, - ASYNC_TX_DEP_ACK | ASYNC_TX_XOR_DROP_DST, tx, - ops_complete_prexor, sh); + ASYNC_TX_XOR_DROP_DST, tx, + ops_complete_prexor, sh); return tx; } @@ -809,7 +806,7 @@ ops_run_postxor(struct stripe_head *sh, struct dma_async_tx_descriptor *tx) * set ASYNC_TX_XOR_DROP_DST and ASYNC_TX_XOR_ZERO_DST * for the synchronous xor case */ - flags = ASYNC_TX_DEP_ACK | ASYNC_TX_ACK | + flags = ASYNC_TX_ACK | (prexor ? ASYNC_TX_XOR_DROP_DST : ASYNC_TX_XOR_ZERO_DST); atomic_inc(&sh->count); @@ -858,7 +855,7 @@ static void ops_run_check(struct stripe_head *sh) &sh->ops.zero_sum_result, 0, NULL, NULL, NULL); atomic_inc(&sh->count); - tx = async_trigger_callback(ASYNC_TX_DEP_ACK | ASYNC_TX_ACK, tx, + tx = async_trigger_callback(ASYNC_TX_ACK, tx, ops_complete_check, sh); } @@ -2687,8 +2684,8 @@ static void handle_stripe_expansion(raid5_conf_t *conf, struct stripe_head *sh, /* place all the copies on one channel */ tx = async_memcpy(sh2->dev[dd_idx].page, - sh->dev[i].page, 0, 0, STRIPE_SIZE, - ASYNC_TX_DEP_ACK, tx, NULL, NULL); + sh->dev[i].page, 0, 0, STRIPE_SIZE, + 0, tx, NULL, NULL); set_bit(R5_Expanded, &sh2->dev[dd_idx].flags); set_bit(R5_UPTODATE, &sh2->dev[dd_idx].flags); diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index 513150d..9f14cd5 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h @@ -58,13 +58,11 @@ struct dma_chan_ref { * array. * @ASYNC_TX_ACK: immediately ack the descriptor, precludes setting up a * dependency chain - * @ASYNC_TX_DEP_ACK: ack the dependency descriptor. Useful for chaining. */ enum async_tx_flags { ASYNC_TX_XOR_ZERO_DST = (1 << 0), ASYNC_TX_XOR_DROP_DST = (1 << 1), - ASYNC_TX_ACK = (1 << 3), - ASYNC_TX_DEP_ACK = (1 << 4), + ASYNC_TX_ACK = (1 << 2), }; #ifdef CONFIG_DMA_ENGINE -- cgit v0.10.2 From a08abd8ca890a377521d65d493d174bebcaf694b Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 3 Jun 2009 11:43:59 -0700 Subject: async_tx: structify submission arguments, add scribble Prepare the api for the arrival of a new parameter, 'scribble'. This will allow callers to identify scratchpad memory for dma address or page address conversions. As this adds yet another parameter, take this opportunity to convert the common submission parameters (flags, dependency, callback, and callback argument) into an object that is passed by reference. Also, take this opportunity to fix up the kerneldoc and add notes about the relevant ASYNC_TX_* flags for each routine. [ Impact: moves api pass-by-value parameters to a pass-by-reference struct ] Signed-off-by: Andre Noll Acked-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/Documentation/crypto/async-tx-api.txt b/Documentation/crypto/async-tx-api.txt index 76feda8..dfe0475 100644 --- a/Documentation/crypto/async-tx-api.txt +++ b/Documentation/crypto/async-tx-api.txt @@ -54,11 +54,7 @@ features surfaced as a result: 3.1 General format of the API: struct dma_async_tx_descriptor * -async_(, - enum async_tx_flags flags, - struct dma_async_tx_descriptor *dependency, - dma_async_tx_callback callback_routine, - void *callback_parameter); +async_(, struct async_submit ctl *submit) 3.2 Supported operations: memcpy - memory copy between a source and a destination buffer diff --git a/crypto/async_tx/async_memcpy.c b/crypto/async_tx/async_memcpy.c index 7117ec6..89e0555 100644 --- a/crypto/async_tx/async_memcpy.c +++ b/crypto/async_tx/async_memcpy.c @@ -33,28 +33,28 @@ * async_memcpy - attempt to copy memory with a dma engine. * @dest: destination page * @src: src page - * @offset: offset in pages to start transaction + * @dest_offset: offset into 'dest' to start transaction + * @src_offset: offset into 'src' to start transaction * @len: length in bytes - * @flags: ASYNC_TX_ACK - * @depend_tx: memcpy depends on the result of this transaction - * @cb_fn: function to call when the memcpy completes - * @cb_param: parameter to pass to the callback routine + * @submit: submission / completion modifiers + * + * honored flags: ASYNC_TX_ACK */ struct dma_async_tx_descriptor * async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset, - unsigned int src_offset, size_t len, enum async_tx_flags flags, - struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_param) + unsigned int src_offset, size_t len, + struct async_submit_ctl *submit) { - struct dma_chan *chan = async_tx_find_channel(depend_tx, DMA_MEMCPY, + struct dma_chan *chan = async_tx_find_channel(submit, DMA_MEMCPY, &dest, 1, &src, 1, len); struct dma_device *device = chan ? chan->device : NULL; struct dma_async_tx_descriptor *tx = NULL; if (device) { dma_addr_t dma_dest, dma_src; - unsigned long dma_prep_flags = cb_fn ? DMA_PREP_INTERRUPT : 0; + unsigned long dma_prep_flags; + dma_prep_flags = submit->cb_fn ? DMA_PREP_INTERRUPT : 0; dma_dest = dma_map_page(device->dev, dest, dest_offset, len, DMA_FROM_DEVICE); @@ -67,13 +67,13 @@ async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset, if (tx) { pr_debug("%s: (async) len: %zu\n", __func__, len); - async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param); + async_tx_submit(chan, tx, submit); } else { void *dest_buf, *src_buf; pr_debug("%s: (sync) len: %zu\n", __func__, len); /* wait for any prerequisite operations */ - async_tx_quiesce(&depend_tx); + async_tx_quiesce(&submit->depend_tx); dest_buf = kmap_atomic(dest, KM_USER0) + dest_offset; src_buf = kmap_atomic(src, KM_USER1) + src_offset; @@ -83,7 +83,7 @@ async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset, kunmap_atomic(dest_buf, KM_USER0); kunmap_atomic(src_buf, KM_USER1); - async_tx_sync_epilog(cb_fn, cb_param); + async_tx_sync_epilog(submit); } return tx; diff --git a/crypto/async_tx/async_memset.c b/crypto/async_tx/async_memset.c index b2f1338..c144372 100644 --- a/crypto/async_tx/async_memset.c +++ b/crypto/async_tx/async_memset.c @@ -35,26 +35,23 @@ * @val: fill value * @offset: offset in pages to start transaction * @len: length in bytes - * @flags: ASYNC_TX_ACK - * @depend_tx: memset depends on the result of this transaction - * @cb_fn: function to call when the memcpy completes - * @cb_param: parameter to pass to the callback routine + * + * honored flags: ASYNC_TX_ACK */ struct dma_async_tx_descriptor * -async_memset(struct page *dest, int val, unsigned int offset, - size_t len, enum async_tx_flags flags, - struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_param) +async_memset(struct page *dest, int val, unsigned int offset, size_t len, + struct async_submit_ctl *submit) { - struct dma_chan *chan = async_tx_find_channel(depend_tx, DMA_MEMSET, + struct dma_chan *chan = async_tx_find_channel(submit, DMA_MEMSET, &dest, 1, NULL, 0, len); struct dma_device *device = chan ? chan->device : NULL; struct dma_async_tx_descriptor *tx = NULL; if (device) { dma_addr_t dma_dest; - unsigned long dma_prep_flags = cb_fn ? DMA_PREP_INTERRUPT : 0; + unsigned long dma_prep_flags; + dma_prep_flags = submit->cb_fn ? DMA_PREP_INTERRUPT : 0; dma_dest = dma_map_page(device->dev, dest, offset, len, DMA_FROM_DEVICE); @@ -64,19 +61,19 @@ async_memset(struct page *dest, int val, unsigned int offset, if (tx) { pr_debug("%s: (async) len: %zu\n", __func__, len); - async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param); + async_tx_submit(chan, tx, submit); } else { /* run the memset synchronously */ void *dest_buf; pr_debug("%s: (sync) len: %zu\n", __func__, len); - dest_buf = (void *) (((char *) page_address(dest)) + offset); + dest_buf = page_address(dest) + offset; /* wait for any prerequisite operations */ - async_tx_quiesce(&depend_tx); + async_tx_quiesce(&submit->depend_tx); memset(dest_buf, val, len); - async_tx_sync_epilog(cb_fn, cb_param); + async_tx_sync_epilog(submit); } return tx; diff --git a/crypto/async_tx/async_tx.c b/crypto/async_tx/async_tx.c index 3766bc3..802a5ce4 100644 --- a/crypto/async_tx/async_tx.c +++ b/crypto/async_tx/async_tx.c @@ -45,13 +45,15 @@ static void __exit async_tx_exit(void) /** * __async_tx_find_channel - find a channel to carry out the operation or let * the transaction execute synchronously - * @depend_tx: transaction dependency + * @submit: transaction dependency and submission modifiers * @tx_type: transaction type */ struct dma_chan * -__async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, - enum dma_transaction_type tx_type) +__async_tx_find_channel(struct async_submit_ctl *submit, + enum dma_transaction_type tx_type) { + struct dma_async_tx_descriptor *depend_tx = submit->depend_tx; + /* see if we can keep the chain on one channel */ if (depend_tx && dma_has_cap(tx_type, depend_tx->chan->device->cap_mask)) @@ -144,13 +146,14 @@ async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx, /** - * submit_disposition - while holding depend_tx->lock we must avoid submitting - * new operations to prevent a circular locking dependency with - * drivers that already hold a channel lock when calling - * async_tx_run_dependencies. + * submit_disposition - flags for routing an incoming operation * @ASYNC_TX_SUBMITTED: we were able to append the new operation under the lock * @ASYNC_TX_CHANNEL_SWITCH: when the lock is dropped schedule a channel switch * @ASYNC_TX_DIRECT_SUBMIT: when the lock is dropped submit directly + * + * while holding depend_tx->lock we must avoid submitting new operations + * to prevent a circular locking dependency with drivers that already + * hold a channel lock when calling async_tx_run_dependencies. */ enum submit_disposition { ASYNC_TX_SUBMITTED, @@ -160,11 +163,12 @@ enum submit_disposition { void async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, - enum async_tx_flags flags, struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_param) + struct async_submit_ctl *submit) { - tx->callback = cb_fn; - tx->callback_param = cb_param; + struct dma_async_tx_descriptor *depend_tx = submit->depend_tx; + + tx->callback = submit->cb_fn; + tx->callback_param = submit->cb_param; if (depend_tx) { enum submit_disposition s; @@ -220,7 +224,7 @@ async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, tx->tx_submit(tx); } - if (flags & ASYNC_TX_ACK) + if (submit->flags & ASYNC_TX_ACK) async_tx_ack(tx); if (depend_tx) @@ -229,21 +233,20 @@ async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, EXPORT_SYMBOL_GPL(async_tx_submit); /** - * async_trigger_callback - schedules the callback function to be run after - * any dependent operations have been completed. - * @flags: ASYNC_TX_ACK - * @depend_tx: 'callback' requires the completion of this transaction - * @cb_fn: function to call after depend_tx completes - * @cb_param: parameter to pass to the callback routine + * async_trigger_callback - schedules the callback function to be run + * @submit: submission and completion parameters + * + * honored flags: ASYNC_TX_ACK + * + * The callback is run after any dependent operations have completed. */ struct dma_async_tx_descriptor * -async_trigger_callback(enum async_tx_flags flags, - struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_param) +async_trigger_callback(struct async_submit_ctl *submit) { struct dma_chan *chan; struct dma_device *device; struct dma_async_tx_descriptor *tx; + struct dma_async_tx_descriptor *depend_tx = submit->depend_tx; if (depend_tx) { chan = depend_tx->chan; @@ -262,14 +265,14 @@ async_trigger_callback(enum async_tx_flags flags, if (tx) { pr_debug("%s: (async)\n", __func__); - async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param); + async_tx_submit(chan, tx, submit); } else { pr_debug("%s: (sync)\n", __func__); /* wait for any prerequisite operations */ - async_tx_quiesce(&depend_tx); + async_tx_quiesce(&submit->depend_tx); - async_tx_sync_epilog(cb_fn, cb_param); + async_tx_sync_epilog(submit); } return tx; diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index 3cc5dc7..691fa98 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c @@ -34,18 +34,16 @@ static __async_inline struct dma_async_tx_descriptor * do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, unsigned int offset, int src_cnt, size_t len, - enum async_tx_flags flags, - struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_param) + struct async_submit_ctl *submit) { struct dma_device *dma = chan->device; dma_addr_t *dma_src = (dma_addr_t *) src_list; struct dma_async_tx_descriptor *tx = NULL; int src_off = 0; int i; - dma_async_tx_callback _cb_fn; - void *_cb_param; - enum async_tx_flags async_flags; + dma_async_tx_callback cb_fn_orig = submit->cb_fn; + void *cb_param_orig = submit->cb_param; + enum async_tx_flags flags_orig = submit->flags; enum dma_ctrl_flags dma_flags; int xor_src_cnt; dma_addr_t dma_dest; @@ -63,7 +61,7 @@ do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, } while (src_cnt) { - async_flags = flags; + submit->flags = flags_orig; dma_flags = 0; xor_src_cnt = min(src_cnt, dma->max_xor); /* if we are submitting additional xors, leave the chain open, @@ -71,15 +69,15 @@ do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, * buffer mapped */ if (src_cnt > xor_src_cnt) { - async_flags &= ~ASYNC_TX_ACK; + submit->flags &= ~ASYNC_TX_ACK; dma_flags = DMA_COMPL_SKIP_DEST_UNMAP; - _cb_fn = NULL; - _cb_param = NULL; + submit->cb_fn = NULL; + submit->cb_param = NULL; } else { - _cb_fn = cb_fn; - _cb_param = cb_param; + submit->cb_fn = cb_fn_orig; + submit->cb_param = cb_param_orig; } - if (_cb_fn) + if (submit->cb_fn) dma_flags |= DMA_PREP_INTERRUPT; /* Since we have clobbered the src_list we are committed @@ -90,7 +88,7 @@ do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, xor_src_cnt, len, dma_flags); if (unlikely(!tx)) - async_tx_quiesce(&depend_tx); + async_tx_quiesce(&submit->depend_tx); /* spin wait for the preceeding transactions to complete */ while (unlikely(!tx)) { @@ -101,10 +99,8 @@ do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, dma_flags); } - async_tx_submit(chan, tx, async_flags, depend_tx, _cb_fn, - _cb_param); - - depend_tx = tx; + async_tx_submit(chan, tx, submit); + submit->depend_tx = tx; if (src_cnt > xor_src_cnt) { /* drop completed sources */ @@ -123,8 +119,7 @@ do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, static void do_sync_xor(struct page *dest, struct page **src_list, unsigned int offset, - int src_cnt, size_t len, enum async_tx_flags flags, - dma_async_tx_callback cb_fn, void *cb_param) + int src_cnt, size_t len, struct async_submit_ctl *submit) { int i; int xor_src_cnt; @@ -139,7 +134,7 @@ do_sync_xor(struct page *dest, struct page **src_list, unsigned int offset, /* set destination address */ dest_buf = page_address(dest) + offset; - if (flags & ASYNC_TX_XOR_ZERO_DST) + if (submit->flags & ASYNC_TX_XOR_ZERO_DST) memset(dest_buf, 0, len); while (src_cnt > 0) { @@ -152,33 +147,35 @@ do_sync_xor(struct page *dest, struct page **src_list, unsigned int offset, src_off += xor_src_cnt; } - async_tx_sync_epilog(cb_fn, cb_param); + async_tx_sync_epilog(submit); } /** * async_xor - attempt to xor a set of blocks with a dma engine. - * xor_blocks always uses the dest as a source so the ASYNC_TX_XOR_ZERO_DST - * flag must be set to not include dest data in the calculation. The - * assumption with dma eninges is that they only use the destination - * buffer as a source when it is explicity specified in the source list. * @dest: destination page - * @src_list: array of source pages (if the dest is also a source it must be - * at index zero). The contents of this array may be overwritten. - * @offset: offset in pages to start transaction + * @src_list: array of source pages + * @offset: common src/dst offset to start transaction * @src_cnt: number of source pages * @len: length in bytes - * @flags: ASYNC_TX_XOR_ZERO_DST, ASYNC_TX_XOR_DROP_DEST, ASYNC_TX_ACK - * @depend_tx: xor depends on the result of this transaction. - * @cb_fn: function to call when the xor completes - * @cb_param: parameter to pass to the callback routine + * @submit: submission / completion modifiers + * + * honored flags: ASYNC_TX_ACK, ASYNC_TX_XOR_ZERO_DST, ASYNC_TX_XOR_DROP_DST + * + * xor_blocks always uses the dest as a source so the + * ASYNC_TX_XOR_ZERO_DST flag must be set to not include dest data in + * the calculation. The assumption with dma eninges is that they only + * use the destination buffer as a source when it is explicity specified + * in the source list. + * + * src_list note: if the dest is also a source it must be at index zero. + * The contents of this array will be overwritten if a scribble region + * is not specified. */ struct dma_async_tx_descriptor * async_xor(struct page *dest, struct page **src_list, unsigned int offset, - int src_cnt, size_t len, enum async_tx_flags flags, - struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_param) + int src_cnt, size_t len, struct async_submit_ctl *submit) { - struct dma_chan *chan = async_tx_find_channel(depend_tx, DMA_XOR, + struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR, &dest, 1, src_list, src_cnt, len); BUG_ON(src_cnt <= 1); @@ -188,7 +185,7 @@ async_xor(struct page *dest, struct page **src_list, unsigned int offset, pr_debug("%s (async): len: %zu\n", __func__, len); return do_async_xor(chan, dest, src_list, offset, src_cnt, len, - flags, depend_tx, cb_fn, cb_param); + submit); } else { /* run the xor synchronously */ pr_debug("%s (sync): len: %zu\n", __func__, len); @@ -196,16 +193,15 @@ async_xor(struct page *dest, struct page **src_list, unsigned int offset, /* in the sync case the dest is an implied source * (assumes the dest is the first source) */ - if (flags & ASYNC_TX_XOR_DROP_DST) { + if (submit->flags & ASYNC_TX_XOR_DROP_DST) { src_cnt--; src_list++; } /* wait for any prerequisite operations */ - async_tx_quiesce(&depend_tx); + async_tx_quiesce(&submit->depend_tx); - do_sync_xor(dest, src_list, offset, src_cnt, len, - flags, cb_fn, cb_param); + do_sync_xor(dest, src_list, offset, src_cnt, len, submit); return NULL; } @@ -222,25 +218,25 @@ static int page_is_zero(struct page *p, unsigned int offset, size_t len) /** * async_xor_val - attempt a xor parity check with a dma engine. * @dest: destination page used if the xor is performed synchronously - * @src_list: array of source pages. The dest page must be listed as a source - * at index zero. The contents of this array may be overwritten. + * @src_list: array of source pages * @offset: offset in pages to start transaction * @src_cnt: number of source pages * @len: length in bytes * @result: 0 if sum == 0 else non-zero - * @flags: ASYNC_TX_ACK - * @depend_tx: xor depends on the result of this transaction. - * @cb_fn: function to call when the xor completes - * @cb_param: parameter to pass to the callback routine + * @submit: submission / completion modifiers + * + * honored flags: ASYNC_TX_ACK + * + * src_list note: if the dest is also a source it must be at index zero. + * The contents of this array will be overwritten if a scribble region + * is not specified. */ struct dma_async_tx_descriptor * -async_xor_val(struct page *dest, struct page **src_list, - unsigned int offset, int src_cnt, size_t len, - u32 *result, enum async_tx_flags flags, - struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_param) +async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, + int src_cnt, size_t len, u32 *result, + struct async_submit_ctl *submit) { - struct dma_chan *chan = async_tx_find_channel(depend_tx, DMA_XOR_VAL, + struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR_VAL, &dest, 1, src_list, src_cnt, len); struct dma_device *device = chan ? chan->device : NULL; @@ -250,11 +246,12 @@ async_xor_val(struct page *dest, struct page **src_list, if (device && src_cnt <= device->max_xor) { dma_addr_t *dma_src = (dma_addr_t *) src_list; - unsigned long dma_prep_flags = cb_fn ? DMA_PREP_INTERRUPT : 0; + unsigned long dma_prep_flags; int i; pr_debug("%s: (async) len: %zu\n", __func__, len); + dma_prep_flags = submit->cb_fn ? DMA_PREP_INTERRUPT : 0; for (i = 0; i < src_cnt; i++) dma_src[i] = dma_map_page(device->dev, src_list[i], offset, len, DMA_TO_DEVICE); @@ -263,7 +260,7 @@ async_xor_val(struct page *dest, struct page **src_list, len, result, dma_prep_flags); if (unlikely(!tx)) { - async_tx_quiesce(&depend_tx); + async_tx_quiesce(&submit->depend_tx); while (!tx) { dma_async_issue_pending(chan); @@ -273,23 +270,23 @@ async_xor_val(struct page *dest, struct page **src_list, } } - async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param); + async_tx_submit(chan, tx, submit); } else { - unsigned long xor_flags = flags; + enum async_tx_flags flags_orig = submit->flags; pr_debug("%s: (sync) len: %zu\n", __func__, len); - xor_flags |= ASYNC_TX_XOR_DROP_DST; - xor_flags &= ~ASYNC_TX_ACK; + submit->flags |= ASYNC_TX_XOR_DROP_DST; + submit->flags &= ~ASYNC_TX_ACK; - tx = async_xor(dest, src_list, offset, src_cnt, len, xor_flags, - depend_tx, NULL, NULL); + tx = async_xor(dest, src_list, offset, src_cnt, len, submit); async_tx_quiesce(&tx); *result = page_is_zero(dest, offset, len) ? 0 : 1; - async_tx_sync_epilog(cb_fn, cb_param); + async_tx_sync_epilog(submit); + submit->flags = flags_orig; } return tx; diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 0ef5362..e1920f2 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -499,11 +499,14 @@ async_copy_data(int frombio, struct bio *bio, struct page *page, struct page *bio_page; int i; int page_offset; + struct async_submit_ctl submit; if (bio->bi_sector >= sector) page_offset = (signed)(bio->bi_sector - sector) * 512; else page_offset = (signed)(sector - bio->bi_sector) * -512; + + init_async_submit(&submit, 0, tx, NULL, NULL, NULL); bio_for_each_segment(bvl, bio, i) { int len = bio_iovec_idx(bio, i)->bv_len; int clen; @@ -525,13 +528,14 @@ async_copy_data(int frombio, struct bio *bio, struct page *page, bio_page = bio_iovec_idx(bio, i)->bv_page; if (frombio) tx = async_memcpy(page, bio_page, page_offset, - b_offset, clen, 0, - tx, NULL, NULL); + b_offset, clen, &submit); else tx = async_memcpy(bio_page, page, b_offset, - page_offset, clen, 0, - tx, NULL, NULL); + page_offset, clen, &submit); } + /* chain the operations */ + submit.depend_tx = tx; + if (clen < len) /* hit end of page */ break; page_offset += len; @@ -590,6 +594,7 @@ static void ops_run_biofill(struct stripe_head *sh) { struct dma_async_tx_descriptor *tx = NULL; raid5_conf_t *conf = sh->raid_conf; + struct async_submit_ctl submit; int i; pr_debug("%s: stripe %llu\n", __func__, @@ -613,7 +618,8 @@ static void ops_run_biofill(struct stripe_head *sh) } atomic_inc(&sh->count); - async_trigger_callback(ASYNC_TX_ACK, tx, ops_complete_biofill, sh); + init_async_submit(&submit, ASYNC_TX_ACK, tx, ops_complete_biofill, sh, NULL); + async_trigger_callback(&submit); } static void ops_complete_compute5(void *stripe_head_ref) @@ -645,6 +651,7 @@ static struct dma_async_tx_descriptor *ops_run_compute5(struct stripe_head *sh) struct page *xor_dest = tgt->page; int count = 0; struct dma_async_tx_descriptor *tx; + struct async_submit_ctl submit; int i; pr_debug("%s: stripe %llu block: %d\n", @@ -657,13 +664,12 @@ static struct dma_async_tx_descriptor *ops_run_compute5(struct stripe_head *sh) atomic_inc(&sh->count); + init_async_submit(&submit, ASYNC_TX_XOR_ZERO_DST, NULL, + ops_complete_compute5, sh, NULL); if (unlikely(count == 1)) - tx = async_memcpy(xor_dest, xor_srcs[0], 0, 0, STRIPE_SIZE, - 0, NULL, ops_complete_compute5, sh); + tx = async_memcpy(xor_dest, xor_srcs[0], 0, 0, STRIPE_SIZE, &submit); else - tx = async_xor(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, - ASYNC_TX_XOR_ZERO_DST, NULL, - ops_complete_compute5, sh); + tx = async_xor(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, &submit); return tx; } @@ -683,6 +689,7 @@ ops_run_prexor(struct stripe_head *sh, struct dma_async_tx_descriptor *tx) int disks = sh->disks; struct page *xor_srcs[disks]; int count = 0, pd_idx = sh->pd_idx, i; + struct async_submit_ctl submit; /* existing parity data subtracted */ struct page *xor_dest = xor_srcs[count++] = sh->dev[pd_idx].page; @@ -697,9 +704,9 @@ ops_run_prexor(struct stripe_head *sh, struct dma_async_tx_descriptor *tx) xor_srcs[count++] = dev->page; } - tx = async_xor(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, - ASYNC_TX_XOR_DROP_DST, tx, - ops_complete_prexor, sh); + init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST, tx, + ops_complete_prexor, sh, NULL); + tx = async_xor(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, &submit); return tx; } @@ -772,7 +779,7 @@ ops_run_postxor(struct stripe_head *sh, struct dma_async_tx_descriptor *tx) /* kernel stack size limits the total number of disks */ int disks = sh->disks; struct page *xor_srcs[disks]; - + struct async_submit_ctl submit; int count = 0, pd_idx = sh->pd_idx, i; struct page *xor_dest; int prexor = 0; @@ -811,13 +818,11 @@ ops_run_postxor(struct stripe_head *sh, struct dma_async_tx_descriptor *tx) atomic_inc(&sh->count); - if (unlikely(count == 1)) { - flags &= ~(ASYNC_TX_XOR_DROP_DST | ASYNC_TX_XOR_ZERO_DST); - tx = async_memcpy(xor_dest, xor_srcs[0], 0, 0, STRIPE_SIZE, - flags, tx, ops_complete_postxor, sh); - } else - tx = async_xor(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, - flags, tx, ops_complete_postxor, sh); + init_async_submit(&submit, flags, tx, ops_complete_postxor, sh, NULL); + if (unlikely(count == 1)) + tx = async_memcpy(xor_dest, xor_srcs[0], 0, 0, STRIPE_SIZE, &submit); + else + tx = async_xor(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, &submit); } static void ops_complete_check(void *stripe_head_ref) @@ -838,6 +843,7 @@ static void ops_run_check(struct stripe_head *sh) int disks = sh->disks; struct page *xor_srcs[disks]; struct dma_async_tx_descriptor *tx; + struct async_submit_ctl submit; int count = 0, pd_idx = sh->pd_idx, i; struct page *xor_dest = xor_srcs[count++] = sh->dev[pd_idx].page; @@ -851,12 +857,13 @@ static void ops_run_check(struct stripe_head *sh) xor_srcs[count++] = dev->page; } + init_async_submit(&submit, 0, NULL, NULL, NULL, NULL); tx = async_xor_val(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, - &sh->ops.zero_sum_result, 0, NULL, NULL, NULL); + &sh->ops.zero_sum_result, &submit); atomic_inc(&sh->count); - tx = async_trigger_callback(ASYNC_TX_ACK, tx, - ops_complete_check, sh); + init_async_submit(&submit, ASYNC_TX_ACK, tx, ops_complete_check, sh, NULL); + tx = async_trigger_callback(&submit); } static void raid5_run_ops(struct stripe_head *sh, unsigned long ops_request) @@ -2664,6 +2671,7 @@ static void handle_stripe_expansion(raid5_conf_t *conf, struct stripe_head *sh, if (i != sh->pd_idx && i != sh->qd_idx) { int dd_idx, j; struct stripe_head *sh2; + struct async_submit_ctl submit; sector_t bn = compute_blocknr(sh, i, 1); sector_t s = raid5_compute_sector(conf, bn, 0, @@ -2683,9 +2691,10 @@ static void handle_stripe_expansion(raid5_conf_t *conf, struct stripe_head *sh, } /* place all the copies on one channel */ + init_async_submit(&submit, 0, tx, NULL, NULL, NULL); tx = async_memcpy(sh2->dev[dd_idx].page, sh->dev[i].page, 0, 0, STRIPE_SIZE, - 0, tx, NULL, NULL); + &submit); set_bit(R5_Expanded, &sh2->dev[dd_idx].flags); set_bit(R5_UPTODATE, &sh2->dev[dd_idx].flags); diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index 9f14cd5..00cfb63 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h @@ -65,6 +65,22 @@ enum async_tx_flags { ASYNC_TX_ACK = (1 << 2), }; +/** + * struct async_submit_ctl - async_tx submission/completion modifiers + * @flags: submission modifiers + * @depend_tx: parent dependency of the current operation being submitted + * @cb_fn: callback routine to run at operation completion + * @cb_param: parameter for the callback routine + * @scribble: caller provided space for dma/page address conversions + */ +struct async_submit_ctl { + enum async_tx_flags flags; + struct dma_async_tx_descriptor *depend_tx; + dma_async_tx_callback cb_fn; + void *cb_param; + void *scribble; +}; + #ifdef CONFIG_DMA_ENGINE #define async_tx_issue_pending_all dma_issue_pending_all #ifdef CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL @@ -73,8 +89,8 @@ enum async_tx_flags { #define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \ __async_tx_find_channel(dep, type) struct dma_chan * -__async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, - enum dma_transaction_type tx_type); +__async_tx_find_channel(struct async_submit_ctl *submit, + enum dma_transaction_type tx_type); #endif /* CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL */ #else static inline void async_tx_issue_pending_all(void) @@ -83,9 +99,10 @@ static inline void async_tx_issue_pending_all(void) } static inline struct dma_chan * -async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, - enum dma_transaction_type tx_type, struct page **dst, int dst_count, - struct page **src, int src_count, size_t len) +async_tx_find_channel(struct async_submit_ctl *submit, + enum dma_transaction_type tx_type, struct page **dst, + int dst_count, struct page **src, int src_count, + size_t len) { return NULL; } @@ -97,46 +114,53 @@ async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, * @cb_fn_param: parameter to pass to the callback routine */ static inline void -async_tx_sync_epilog(dma_async_tx_callback cb_fn, void *cb_fn_param) +async_tx_sync_epilog(struct async_submit_ctl *submit) +{ + if (submit->cb_fn) + submit->cb_fn(submit->cb_param); +} + +typedef union { + unsigned long addr; + struct page *page; + dma_addr_t dma; +} addr_conv_t; + +static inline void +init_async_submit(struct async_submit_ctl *args, enum async_tx_flags flags, + struct dma_async_tx_descriptor *tx, + dma_async_tx_callback cb_fn, void *cb_param, + addr_conv_t *scribble) { - if (cb_fn) - cb_fn(cb_fn_param); + args->flags = flags; + args->depend_tx = tx; + args->cb_fn = cb_fn; + args->cb_param = cb_param; + args->scribble = scribble; } -void -async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, - enum async_tx_flags flags, struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_fn_param); +void async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, + struct async_submit_ctl *submit); struct dma_async_tx_descriptor * async_xor(struct page *dest, struct page **src_list, unsigned int offset, - int src_cnt, size_t len, enum async_tx_flags flags, - struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_fn_param); + int src_cnt, size_t len, struct async_submit_ctl *submit); struct dma_async_tx_descriptor * -async_xor_val(struct page *dest, struct page **src_list, - unsigned int offset, int src_cnt, size_t len, - u32 *result, enum async_tx_flags flags, - struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_fn_param); +async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, + int src_cnt, size_t len, u32 *result, + struct async_submit_ctl *submit); struct dma_async_tx_descriptor * async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset, - unsigned int src_offset, size_t len, enum async_tx_flags flags, - struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_fn_param); + unsigned int src_offset, size_t len, + struct async_submit_ctl *submit); struct dma_async_tx_descriptor * async_memset(struct page *dest, int val, unsigned int offset, - size_t len, enum async_tx_flags flags, - struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_fn_param); + size_t len, struct async_submit_ctl *submit); -struct dma_async_tx_descriptor * -async_trigger_callback(enum async_tx_flags flags, - struct dma_async_tx_descriptor *depend_tx, - dma_async_tx_callback cb_fn, void *cb_fn_param); +struct dma_async_tx_descriptor *async_trigger_callback(struct async_submit_ctl *submit); void async_tx_quiesce(struct dma_async_tx_descriptor **tx); #endif /* _ASYNC_TX_H_ */ -- cgit v0.10.2 From 04ce9ab385dc97eb55299d533cd3af79b8fc7529 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 3 Jun 2009 14:22:28 -0700 Subject: async_xor: permit callers to pass in a 'dma/page scribble' region async_xor() needs space to perform dma and page address conversions. In most cases the code can simply reuse the struct page * array because the size of the native pointer matches the size of a dma/page address. In order to support archs where sizeof(dma_addr_t) is larger than sizeof(struct page *), or to preserve the input parameters, we utilize a memory region passed in by the caller. Since the code is now prepared to handle the case where it cannot perform address conversions on the stack, we no longer need the !HIGHMEM64G dependency in drivers/dma/Kconfig. [ Impact: don't clobber input buffers for address conversions ] Reviewed-by: Andre Noll Acked-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/Documentation/crypto/async-tx-api.txt b/Documentation/crypto/async-tx-api.txt index dfe0475..6b15e48 100644 --- a/Documentation/crypto/async-tx-api.txt +++ b/Documentation/crypto/async-tx-api.txt @@ -115,29 +115,42 @@ of an operation. Perform a xor->copy->xor operation where each operation depends on the result from the previous operation: -void complete_xor_copy_xor(void *param) +void callback(void *param) { - printk("complete\n"); + struct completion *cmp = param; + + complete(cmp); } -int run_xor_copy_xor(struct page **xor_srcs, - int xor_src_cnt, - struct page *xor_dest, - size_t xor_len, - struct page *copy_src, - struct page *copy_dest, - size_t copy_len) +void run_xor_copy_xor(struct page **xor_srcs, + int xor_src_cnt, + struct page *xor_dest, + size_t xor_len, + struct page *copy_src, + struct page *copy_dest, + size_t copy_len) { struct dma_async_tx_descriptor *tx; + addr_conv_t addr_conv[xor_src_cnt]; + struct async_submit_ctl submit; + addr_conv_t addr_conv[NDISKS]; + struct completion cmp; + + init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST, NULL, NULL, NULL, + addr_conv); + tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, &submit) - tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, - ASYNC_TX_XOR_DROP_DST, NULL, NULL, NULL); - tx = async_memcpy(copy_dest, copy_src, 0, 0, copy_len, tx, NULL, NULL); - tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, - ASYNC_TX_XOR_DROP_DST | ASYNC_TX_ACK, - tx, complete_xor_copy_xor, NULL); + submit->depend_tx = tx; + tx = async_memcpy(copy_dest, copy_src, 0, 0, copy_len, &submit); + + init_completion(&cmp); + init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST | ASYNC_TX_ACK, tx, + callback, &cmp, addr_conv); + tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, &submit); async_tx_issue_pending_all(); + + wait_for_completion(&cmp); } See include/linux/async_tx.h for more information on the flags. See the diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index 691fa98..1e96c4d 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c @@ -33,11 +33,10 @@ /* do_async_xor - dma map the pages and perform the xor with an engine */ static __async_inline struct dma_async_tx_descriptor * do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, - unsigned int offset, int src_cnt, size_t len, + unsigned int offset, int src_cnt, size_t len, dma_addr_t *dma_src, struct async_submit_ctl *submit) { struct dma_device *dma = chan->device; - dma_addr_t *dma_src = (dma_addr_t *) src_list; struct dma_async_tx_descriptor *tx = NULL; int src_off = 0; int i; @@ -125,9 +124,14 @@ do_sync_xor(struct page *dest, struct page **src_list, unsigned int offset, int xor_src_cnt; int src_off = 0; void *dest_buf; - void **srcs = (void **) src_list; + void **srcs; - /* reuse the 'src_list' array to convert to buffer pointers */ + if (submit->scribble) + srcs = submit->scribble; + else + srcs = (void **) src_list; + + /* convert to buffer pointers */ for (i = 0; i < src_cnt; i++) srcs[i] = page_address(src_list[i]) + offset; @@ -178,17 +182,26 @@ async_xor(struct page *dest, struct page **src_list, unsigned int offset, struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR, &dest, 1, src_list, src_cnt, len); + dma_addr_t *dma_src = NULL; + BUG_ON(src_cnt <= 1); - if (chan) { + if (submit->scribble) + dma_src = submit->scribble; + else if (sizeof(dma_addr_t) <= sizeof(struct page *)) + dma_src = (dma_addr_t *) src_list; + + if (dma_src && chan) { /* run the xor asynchronously */ pr_debug("%s (async): len: %zu\n", __func__, len); return do_async_xor(chan, dest, src_list, offset, src_cnt, len, - submit); + dma_src, submit); } else { /* run the xor synchronously */ pr_debug("%s (sync): len: %zu\n", __func__, len); + WARN_ONCE(chan, "%s: no space for dma address conversion\n", + __func__); /* in the sync case the dest is an implied source * (assumes the dest is the first source) @@ -241,11 +254,16 @@ async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, src_cnt, len); struct dma_device *device = chan ? chan->device : NULL; struct dma_async_tx_descriptor *tx = NULL; + dma_addr_t *dma_src = NULL; BUG_ON(src_cnt <= 1); - if (device && src_cnt <= device->max_xor) { - dma_addr_t *dma_src = (dma_addr_t *) src_list; + if (submit->scribble) + dma_src = submit->scribble; + else if (sizeof(dma_addr_t) <= sizeof(struct page *)) + dma_src = (dma_addr_t *) src_list; + + if (dma_src && device && src_cnt <= device->max_xor) { unsigned long dma_prep_flags; int i; @@ -275,6 +293,9 @@ async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, enum async_tx_flags flags_orig = submit->flags; pr_debug("%s: (sync) len: %zu\n", __func__, len); + WARN_ONCE(device && src_cnt <= device->max_xor, + "%s: no space for dma address conversion\n", + __func__); submit->flags |= ASYNC_TX_XOR_DROP_DST; submit->flags &= ~ASYNC_TX_ACK; @@ -293,29 +314,6 @@ async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, } EXPORT_SYMBOL_GPL(async_xor_val); -static int __init async_xor_init(void) -{ - #ifdef CONFIG_DMA_ENGINE - /* To conserve stack space the input src_list (array of page pointers) - * is reused to hold the array of dma addresses passed to the driver. - * This conversion is only possible when dma_addr_t is less than the - * the size of a pointer. HIGHMEM64G is known to violate this - * assumption. - */ - BUILD_BUG_ON(sizeof(dma_addr_t) > sizeof(struct page *)); - #endif - - return 0; -} - -static void __exit async_xor_exit(void) -{ - do { } while (0); -} - -module_init(async_xor_init); -module_exit(async_xor_exit); - MODULE_AUTHOR("Intel Corporation"); MODULE_DESCRIPTION("asynchronous xor/xor-zero-sum api"); MODULE_LICENSE("GPL"); diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 3b3c01b..912a51b 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -4,7 +4,7 @@ menuconfig DMADEVICES bool "DMA Engine support" - depends on !HIGHMEM64G && HAS_DMA + depends on HAS_DMA help DMA engines can do asynchronous data transfers without involving the host CPU. Currently, this framework can be -- cgit v0.10.2 From 74cad4ee9839669ad920257678ea0bf0a818cd3b Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Wed, 24 Jun 2009 11:49:49 +0800 Subject: ACPI: Make ACPI processor proc I/F depend on the ACPI_PROCFS Now whether the ACPI processor proc I/F is registered depends on the CONFIG_PROC. It had better depend on the CONFIG_ACPI_PROCFS. When the CONFIG_ACPI_PROCFS is unset in kernel configuration, the ACPI processor proc I/F won't be registered. Signed-off-by: Zhao Yakui Signed-off-by: Len Brown diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index 431f8b4..f26db48 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -60,7 +60,11 @@ config ACPI_PROCFS /proc/acpi/fadt (/sys/firmware/acpi/tables/FACP) /proc/acpi/debug_layer (/sys/module/acpi/parameters/debug_layer) /proc/acpi/debug_level (/sys/module/acpi/parameters/debug_level) - + /proc/acpi/processor/*/power (/sys/devices/system/cpu/*/cpuidle/*) + /proc/acpi/processor/*/performance (/sys/devices/system/cpu/*/ + cpufreq/*) + /proc/acpi/processor/*/throttling (/sys/class/thermal/ + cooling_device*/*) This option has no effect on /proc/acpi/ files and functions which do not yet exist in /sys. diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 23f0fb8..1b166c1 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -81,7 +81,9 @@ MODULE_LICENSE("GPL"); static int acpi_processor_add(struct acpi_device *device); static int acpi_processor_start(struct acpi_device *device); static int acpi_processor_remove(struct acpi_device *device, int type); +#ifdef CONFIG_ACPI_PROCFS static int acpi_processor_info_open_fs(struct inode *inode, struct file *file); +#endif static void acpi_processor_notify(struct acpi_device *device, u32 event); static acpi_status acpi_processor_hotadd_init(acpi_handle handle, int *p_cpu); static int acpi_processor_handle_eject(struct acpi_processor *pr); @@ -110,7 +112,7 @@ static struct acpi_driver acpi_processor_driver = { #define INSTALL_NOTIFY_HANDLER 1 #define UNINSTALL_NOTIFY_HANDLER 2 - +#ifdef CONFIG_ACPI_PROCFS static const struct file_operations acpi_processor_info_fops = { .owner = THIS_MODULE, .open = acpi_processor_info_open_fs, @@ -118,6 +120,7 @@ static const struct file_operations acpi_processor_info_fops = { .llseek = seq_lseek, .release = single_release, }; +#endif DEFINE_PER_CPU(struct acpi_processor *, processors); struct acpi_processor_errata errata __read_mostly; @@ -316,6 +319,7 @@ static int acpi_processor_set_pdc(struct acpi_processor *pr) FS Interface (/proc) -------------------------------------------------------------------------- */ +#ifdef CONFIG_ACPI_PROCFS static struct proc_dir_entry *acpi_processor_dir = NULL; static int acpi_processor_info_seq_show(struct seq_file *seq, void *offset) @@ -388,7 +392,6 @@ static int acpi_processor_add_fs(struct acpi_device *device) return -EIO; return 0; } - static int acpi_processor_remove_fs(struct acpi_device *device) { @@ -405,6 +408,16 @@ static int acpi_processor_remove_fs(struct acpi_device *device) return 0; } +#else +static inline int acpi_processor_add_fs(struct acpi_device *device) +{ + return 0; +} +static inline int acpi_processor_remove_fs(struct acpi_device *device) +{ + return 0; +} +#endif /* Use the acpiid in MADT to map cpus in case of SMP */ @@ -1147,11 +1160,11 @@ static int __init acpi_processor_init(void) (struct acpi_table_header **)&madt))) madt = NULL; #endif - +#ifdef CONFIG_ACPI_PROCFS acpi_processor_dir = proc_mkdir(ACPI_PROCESSOR_CLASS, acpi_root_dir); if (!acpi_processor_dir) return -ENOMEM; - +#endif /* * Check whether the system is DMI table. If yes, OSPM * should not use mwait for CPU-states. @@ -1179,7 +1192,9 @@ out_cpuidle: cpuidle_unregister_driver(&acpi_idle_driver); out_proc: +#ifdef CONFIG_ACPI_PROCFS remove_proc_entry(ACPI_PROCESSOR_CLASS, acpi_root_dir); +#endif return result; } @@ -1196,7 +1211,9 @@ static void __exit acpi_processor_exit(void) cpuidle_unregister_driver(&acpi_idle_driver); +#ifdef CONFIG_ACPI_PROCFS remove_proc_entry(ACPI_PROCESSOR_CLASS, acpi_root_dir); +#endif return; } diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 10a2d91..67b2fa1 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -679,6 +679,7 @@ static int acpi_processor_get_power_info(struct acpi_processor *pr) return 0; } +#ifdef CONFIG_ACPI_PROCFS static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) { struct acpi_processor *pr = seq->private; @@ -758,7 +759,7 @@ static const struct file_operations acpi_processor_power_fops = { .llseek = seq_lseek, .release = single_release, }; - +#endif /** * acpi_idle_bm_check - checks if bus master activity was detected @@ -1216,7 +1217,7 @@ int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, pr->power.states[i].type); printk(")\n"); } - +#ifdef CONFIG_ACPI_PROCFS /* 'power' [R] */ entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER, S_IRUGO, acpi_device_dir(device), @@ -1224,6 +1225,7 @@ int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, acpi_driver_data(device)); if (!entry) return -EIO; +#endif return 0; } @@ -1236,9 +1238,11 @@ int acpi_processor_power_exit(struct acpi_processor *pr, cpuidle_unregister_device(&pr->power.dev); pr->flags.power_setup_done = 0; +#ifdef CONFIG_ACPI_PROCFS if (acpi_device_dir(device)) remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, acpi_device_dir(device)); +#endif return 0; } diff --git a/drivers/acpi/processor_thermal.c b/drivers/acpi/processor_thermal.c index 39838c6..07e2614 100644 --- a/drivers/acpi/processor_thermal.c +++ b/drivers/acpi/processor_thermal.c @@ -438,7 +438,7 @@ struct thermal_cooling_device_ops processor_cooling_ops = { }; /* /proc interface */ - +#ifdef CONFIG_ACPI_PROCFS static int acpi_processor_limit_seq_show(struct seq_file *seq, void *offset) { struct acpi_processor *pr = (struct acpi_processor *)seq->private; @@ -517,3 +517,4 @@ const struct file_operations acpi_processor_limit_fops = { .llseek = seq_lseek, .release = single_release, }; +#endif diff --git a/drivers/acpi/processor_throttling.c b/drivers/acpi/processor_throttling.c index 2275437..1656001 100644 --- a/drivers/acpi/processor_throttling.c +++ b/drivers/acpi/processor_throttling.c @@ -1214,7 +1214,7 @@ int acpi_processor_get_throttling_info(struct acpi_processor *pr) } /* proc interface */ - +#ifdef CONFIG_ACPI_PROCFS static int acpi_processor_throttling_seq_show(struct seq_file *seq, void *offset) { @@ -1322,3 +1322,4 @@ const struct file_operations acpi_processor_throttling_fops = { .llseek = seq_lseek, .release = single_release, }; +#endif -- cgit v0.10.2 From b188e4ce3b7965ecc8d45191042cc9d25f6b90ee Mon Sep 17 00:00:00 2001 From: Len Brown Date: Wed, 24 Jun 2009 01:48:32 -0400 Subject: ACPI: fix CONFIG_ACPI_PROCFS=n build warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/acpi/processor_idle.c:1162: warning: unused variable ‘entry’ Signed-off-by: Len Brown diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 67b2fa1..b85d9f0 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -1160,7 +1160,9 @@ int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, { acpi_status status = 0; static int first_run; +#ifdef CONFIG_ACPI_PROCFS struct proc_dir_entry *entry = NULL; +#endif unsigned int i; if (boot_option_idle_override) -- cgit v0.10.2 From c1815e074079838d36d89e45e92b7ee317190700 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 22 Jun 2009 20:41:04 +0000 Subject: ACPI: processor: remove KOBJ_ONLINE/KOBJ_OFFLINE events This patch removes the KOBJ_ONLINE/KOBJ_OFFLINE events the driver used to generate for CPU hotplug. As far as I know, nobody consumes these. The driver core still generates KOBJ_ADD and KOBJ_REMOVE, of course. Signed-off-by: Bjorn Helgaas CC: Venkatesh Pallipadi CC: Zhao Yakui CC: Matthew Garrett CC: Thomas Renninger CC: Dave Jones CC: Kay Sievers CC: Greg Kroah-Hartman Signed-off-by: Len Brown diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 84e0f3c..c6ec68d 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -963,9 +963,6 @@ int acpi_processor_device_add(acpi_handle handle, struct acpi_device **device) if (!pr) return -ENODEV; - if ((pr->id >= 0) && (pr->id < nr_cpu_ids)) { - kobject_uevent(&(*device)->dev.kobj, KOBJ_ONLINE); - } return 0; } @@ -1002,18 +999,10 @@ static void __ref acpi_processor_hotplug_notify(acpi_handle handle, break; } - if (pr->id >= 0 && (pr->id < nr_cpu_ids)) { - kobject_uevent(&device->dev.kobj, KOBJ_OFFLINE); - break; - } - result = acpi_processor_start(device); - if ((!result) && ((pr->id >= 0) && (pr->id < nr_cpu_ids))) { - kobject_uevent(&device->dev.kobj, KOBJ_ONLINE); - } else { + if (result) printk(KERN_ERR PREFIX "Device [%s] failed to start\n", acpi_device_bid(device)); - } break; case ACPI_NOTIFY_EJECT_REQUEST: ACPI_DEBUG_PRINT((ACPI_DB_INFO, @@ -1030,9 +1019,6 @@ static void __ref acpi_processor_hotplug_notify(acpi_handle handle, "Driver data is NULL, dropping EJECT\n"); return; } - - if ((pr->id < nr_cpu_ids) && (cpu_present(pr->id))) - kobject_uevent(&device->dev.kobj, KOBJ_OFFLINE); break; default: ACPI_DEBUG_PRINT((ACPI_DB_INFO, -- cgit v0.10.2 From d4e0526184199e23ac1460fe59b8a3741b17a8b5 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 22 Jun 2009 20:41:09 +0000 Subject: ACPI: processor: clean up in acpi_processor_start() error exits We used to leave crud around if things failed in acpi_processor_start(). This patch cleans up as much as we can before returning. Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Chiang CC: Venkatesh Pallipadi CC: Zhao Yakui Signed-off-by: Len Brown diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index c6ec68d..a496a86 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -731,11 +731,13 @@ static int __cpuinit acpi_processor_start(struct acpi_device *device) result = acpi_processor_add_fs(device); if (result) - goto end; + return result; sysdev = get_cpu_sysdev(pr->id); - if (sysfs_create_link(&device->dev.kobj, &sysdev->kobj, "sysdev")) - return -EFAULT; + if (sysfs_create_link(&device->dev.kobj, &sysdev->kobj, "sysdev")) { + result = -EFAULT; + goto err_remove_fs; + } /* _PDC call should be done before doing anything else (if reqd.). */ arch_acpi_processor_init_pdc(pr); @@ -755,7 +757,7 @@ static int __cpuinit acpi_processor_start(struct acpi_device *device) &processor_cooling_ops); if (IS_ERR(pr->cdev)) { result = PTR_ERR(pr->cdev); - goto end; + goto err_power_exit; } dev_info(&device->dev, "registered as cooling_device%d\n", @@ -764,13 +766,17 @@ static int __cpuinit acpi_processor_start(struct acpi_device *device) result = sysfs_create_link(&device->dev.kobj, &pr->cdev->device.kobj, "thermal_cooling"); - if (result) + if (result) { printk(KERN_ERR PREFIX "Create sysfs link\n"); + goto err_thermal_unregister; + } result = sysfs_create_link(&pr->cdev->device.kobj, &device->dev.kobj, "device"); - if (result) + if (result) { printk(KERN_ERR PREFIX "Create sysfs link\n"); + goto err_remove_sysfs; + } if (pr->flags.throttling) { printk(KERN_INFO PREFIX "%s [%s] (supports", @@ -779,7 +785,16 @@ static int __cpuinit acpi_processor_start(struct acpi_device *device) printk(")\n"); } - end: + return 0; + +err_remove_sysfs: + sysfs_remove_link(&device->dev.kobj, "thermal_cooling"); +err_thermal_unregister: + thermal_cooling_device_unregister(pr->cdev); +err_power_exit: + acpi_processor_power_exit(pr, device); +err_remove_fs: + acpi_processor_remove_fs(device); return result; } -- cgit v0.10.2 From ddcd62d89e8c919cc75aeffd2ca37c986141b0f0 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 22 Jun 2009 20:41:14 +0000 Subject: ACPI: processor: move acpi_processor_start() after acpi_processor_add() Move acpi_processor_start() to just after acpi_processor_add(). A subsequent patch will merge them. Code movement only; no functional change. Signed-off-by: Bjorn Helgaas CC: Venkatesh Pallipadi CC: Zhao Yakui Signed-off-by: Len Brown diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index a496a86..53de55e 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -698,6 +698,90 @@ static int acpi_processor_get_info(struct acpi_device *device) static DEFINE_PER_CPU(void *, processor_device_array); +static void acpi_processor_notify(struct acpi_device *device, u32 event) +{ + struct acpi_processor *pr = acpi_driver_data(device); + int saved; + + if (!pr) + return; + + switch (event) { + case ACPI_PROCESSOR_NOTIFY_PERFORMANCE: + saved = pr->performance_platform_limit; + acpi_processor_ppc_has_changed(pr); + if (saved == pr->performance_platform_limit) + break; + acpi_bus_generate_proc_event(device, event, + pr->performance_platform_limit); + acpi_bus_generate_netlink_event(device->pnp.device_class, + dev_name(&device->dev), event, + pr->performance_platform_limit); + break; + case ACPI_PROCESSOR_NOTIFY_POWER: + acpi_processor_cst_has_changed(pr); + acpi_bus_generate_proc_event(device, event, 0); + acpi_bus_generate_netlink_event(device->pnp.device_class, + dev_name(&device->dev), event, 0); + break; + case ACPI_PROCESSOR_NOTIFY_THROTTLING: + acpi_processor_tstate_has_changed(pr); + acpi_bus_generate_proc_event(device, event, 0); + acpi_bus_generate_netlink_event(device->pnp.device_class, + dev_name(&device->dev), event, 0); + default: + ACPI_DEBUG_PRINT((ACPI_DB_INFO, + "Unsupported event [0x%x]\n", event)); + break; + } + + return; +} + +static int acpi_cpu_soft_notify(struct notifier_block *nfb, + unsigned long action, void *hcpu) +{ + unsigned int cpu = (unsigned long)hcpu; + struct acpi_processor *pr = per_cpu(processors, cpu); + + if (action == CPU_ONLINE && pr) { + acpi_processor_ppc_has_changed(pr); + acpi_processor_cst_has_changed(pr); + acpi_processor_tstate_has_changed(pr); + } + return NOTIFY_OK; +} + +static struct notifier_block acpi_cpu_notifier = +{ + .notifier_call = acpi_cpu_soft_notify, +}; + +static int acpi_processor_add(struct acpi_device *device) +{ + struct acpi_processor *pr = NULL; + + + if (!device) + return -EINVAL; + + pr = kzalloc(sizeof(struct acpi_processor), GFP_KERNEL); + if (!pr) + return -ENOMEM; + + if (!zalloc_cpumask_var(&pr->throttling.shared_cpu_map, GFP_KERNEL)) { + kfree(pr); + return -ENOMEM; + } + + pr->handle = device->handle; + strcpy(acpi_device_name(device), ACPI_PROCESSOR_DEVICE_NAME); + strcpy(acpi_device_class(device), ACPI_PROCESSOR_CLASS); + device->driver_data = pr; + + return 0; +} + static int __cpuinit acpi_processor_start(struct acpi_device *device) { int result = 0; @@ -799,90 +883,6 @@ err_remove_fs: return result; } -static void acpi_processor_notify(struct acpi_device *device, u32 event) -{ - struct acpi_processor *pr = acpi_driver_data(device); - int saved; - - if (!pr) - return; - - switch (event) { - case ACPI_PROCESSOR_NOTIFY_PERFORMANCE: - saved = pr->performance_platform_limit; - acpi_processor_ppc_has_changed(pr); - if (saved == pr->performance_platform_limit) - break; - acpi_bus_generate_proc_event(device, event, - pr->performance_platform_limit); - acpi_bus_generate_netlink_event(device->pnp.device_class, - dev_name(&device->dev), event, - pr->performance_platform_limit); - break; - case ACPI_PROCESSOR_NOTIFY_POWER: - acpi_processor_cst_has_changed(pr); - acpi_bus_generate_proc_event(device, event, 0); - acpi_bus_generate_netlink_event(device->pnp.device_class, - dev_name(&device->dev), event, 0); - break; - case ACPI_PROCESSOR_NOTIFY_THROTTLING: - acpi_processor_tstate_has_changed(pr); - acpi_bus_generate_proc_event(device, event, 0); - acpi_bus_generate_netlink_event(device->pnp.device_class, - dev_name(&device->dev), event, 0); - default: - ACPI_DEBUG_PRINT((ACPI_DB_INFO, - "Unsupported event [0x%x]\n", event)); - break; - } - - return; -} - -static int acpi_cpu_soft_notify(struct notifier_block *nfb, - unsigned long action, void *hcpu) -{ - unsigned int cpu = (unsigned long)hcpu; - struct acpi_processor *pr = per_cpu(processors, cpu); - - if (action == CPU_ONLINE && pr) { - acpi_processor_ppc_has_changed(pr); - acpi_processor_cst_has_changed(pr); - acpi_processor_tstate_has_changed(pr); - } - return NOTIFY_OK; -} - -static struct notifier_block acpi_cpu_notifier = -{ - .notifier_call = acpi_cpu_soft_notify, -}; - -static int acpi_processor_add(struct acpi_device *device) -{ - struct acpi_processor *pr = NULL; - - - if (!device) - return -EINVAL; - - pr = kzalloc(sizeof(struct acpi_processor), GFP_KERNEL); - if (!pr) - return -ENOMEM; - - if (!zalloc_cpumask_var(&pr->throttling.shared_cpu_map, GFP_KERNEL)) { - kfree(pr); - return -ENOMEM; - } - - pr->handle = device->handle; - strcpy(acpi_device_name(device), ACPI_PROCESSOR_DEVICE_NAME); - strcpy(acpi_device_class(device), ACPI_PROCESSOR_CLASS); - device->driver_data = pr; - - return 0; -} - static int acpi_processor_remove(struct acpi_device *device, int type) { struct acpi_processor *pr = NULL; -- cgit v0.10.2 From 970b04929a68134acca17878b1d93e115e58c12a Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 22 Jun 2009 20:41:19 +0000 Subject: ACPI: processor: remove .start() method This patch folds the .start() method into .add(). acpi_processor_start() is always called immediately after acpi_processor_add(), so there's really no point in having them be separate methods. Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Chiang CC: Venkatesh Pallipadi CC: Zhao Yakui Signed-off-by: Len Brown diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 53de55e..8014e2a 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -79,7 +79,6 @@ MODULE_DESCRIPTION("ACPI Processor Driver"); MODULE_LICENSE("GPL"); static int acpi_processor_add(struct acpi_device *device); -static int acpi_processor_start(struct acpi_device *device); static int acpi_processor_remove(struct acpi_device *device, int type); static int acpi_processor_info_open_fs(struct inode *inode, struct file *file); static void acpi_processor_notify(struct acpi_device *device, u32 event); @@ -101,7 +100,6 @@ static struct acpi_driver acpi_processor_driver = { .ops = { .add = acpi_processor_add, .remove = acpi_processor_remove, - .start = acpi_processor_start, .suspend = acpi_processor_suspend, .resume = acpi_processor_resume, .notify = acpi_processor_notify, @@ -760,10 +758,8 @@ static struct notifier_block acpi_cpu_notifier = static int acpi_processor_add(struct acpi_device *device) { struct acpi_processor *pr = NULL; - - - if (!device) - return -EINVAL; + int result = 0; + struct sys_device *sysdev; pr = kzalloc(sizeof(struct acpi_processor), GFP_KERNEL); if (!pr) @@ -779,17 +775,6 @@ static int acpi_processor_add(struct acpi_device *device) strcpy(acpi_device_class(device), ACPI_PROCESSOR_CLASS); device->driver_data = pr; - return 0; -} - -static int __cpuinit acpi_processor_start(struct acpi_device *device) -{ - int result = 0; - struct acpi_processor *pr; - struct sys_device *sysdev; - - pr = acpi_driver_data(device); - result = acpi_processor_get_info(device); if (result) { /* Processor is physically not present */ @@ -807,7 +792,8 @@ static int __cpuinit acpi_processor_start(struct acpi_device *device) per_cpu(processor_device_array, pr->id) != device) { printk(KERN_WARNING "BIOS reported wrong ACPI id " "for the processor\n"); - return -ENODEV; + result = -ENODEV; + goto err_free_cpumask; } per_cpu(processor_device_array, pr->id) = device; @@ -815,7 +801,7 @@ static int __cpuinit acpi_processor_start(struct acpi_device *device) result = acpi_processor_add_fs(device); if (result) - return result; + goto err_free_cpumask; sysdev = get_cpu_sysdev(pr->id); if (sysfs_create_link(&device->dev.kobj, &sysdev->kobj, "sysdev")) { @@ -879,6 +865,8 @@ err_power_exit: acpi_processor_power_exit(pr, device); err_remove_fs: acpi_processor_remove_fs(device); +err_free_cpumask: + free_cpumask_var(pr->throttling.shared_cpu_map); return result; } @@ -957,7 +945,6 @@ int acpi_processor_device_add(acpi_handle handle, struct acpi_device **device) { acpi_handle phandle; struct acpi_device *pdev; - struct acpi_processor *pr; if (acpi_get_parent(handle, &phandle)) { @@ -972,12 +959,6 @@ int acpi_processor_device_add(acpi_handle handle, struct acpi_device **device) return -ENODEV; } - acpi_bus_start(*device); - - pr = acpi_driver_data(*device); - if (!pr) - return -ENODEV; - return 0; } @@ -1007,17 +988,6 @@ static void __ref acpi_processor_hotplug_notify(acpi_handle handle, "Unable to add the device\n"); break; } - - pr = acpi_driver_data(device); - if (!pr) { - printk(KERN_ERR PREFIX "Driver data is NULL\n"); - break; - } - - result = acpi_processor_start(device); - if (result) - printk(KERN_ERR PREFIX "Device [%s] failed to start\n", - acpi_device_bid(device)); break; case ACPI_NOTIFY_EJECT_REQUEST: ACPI_DEBUG_PRINT((ACPI_DB_INFO, -- cgit v0.10.2 From 80f20fef6a2381402e59b169eb51b989cc175ab7 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 22 Jun 2009 20:41:25 +0000 Subject: ACPI: memory hotplug: remove .start() method This patch folds the .start() method into .add(). The .start() method is called in two paths: boot-time device enumeration and run-time node addition, currently via container_device_add(). In both cases, .start() is called immediately after .add(), so there's no reason to make them separate methods. Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Chiang CC: Yasunori Goto CC: Dave Hansen Signed-off-by: Len Brown diff --git a/drivers/acpi/acpi_memhotplug.c b/drivers/acpi/acpi_memhotplug.c index 7a0f4aa..a8d9d8f 100644 --- a/drivers/acpi/acpi_memhotplug.c +++ b/drivers/acpi/acpi_memhotplug.c @@ -50,7 +50,6 @@ MODULE_LICENSE("GPL"); static int acpi_memory_device_add(struct acpi_device *device); static int acpi_memory_device_remove(struct acpi_device *device, int type); -static int acpi_memory_device_start(struct acpi_device *device); static const struct acpi_device_id memory_device_ids[] = { {ACPI_MEMORY_DEVICE_HID, 0}, @@ -65,7 +64,6 @@ static struct acpi_driver acpi_memory_device_driver = { .ops = { .add = acpi_memory_device_add, .remove = acpi_memory_device_remove, - .start = acpi_memory_device_start, }, }; @@ -415,28 +413,6 @@ static int acpi_memory_device_add(struct acpi_device *device) printk(KERN_DEBUG "%s \n", acpi_device_name(device)); - return result; -} - -static int acpi_memory_device_remove(struct acpi_device *device, int type) -{ - struct acpi_memory_device *mem_device = NULL; - - - if (!device || !acpi_driver_data(device)) - return -EINVAL; - - mem_device = acpi_driver_data(device); - kfree(mem_device); - - return 0; -} - -static int acpi_memory_device_start (struct acpi_device *device) -{ - struct acpi_memory_device *mem_device; - int result = 0; - /* * Early boot code has recognized memory area by EFI/E820. * If DSDT shows these memory devices on boot, hotplug is not necessary @@ -446,8 +422,6 @@ static int acpi_memory_device_start (struct acpi_device *device) if (!acpi_hotmem_initialized) return 0; - mem_device = acpi_driver_data(device); - if (!acpi_memory_check_device(mem_device)) { /* call add_memory func */ result = acpi_memory_enable_device(mem_device); @@ -458,6 +432,20 @@ static int acpi_memory_device_start (struct acpi_device *device) return result; } +static int acpi_memory_device_remove(struct acpi_device *device, int type) +{ + struct acpi_memory_device *mem_device = NULL; + + + if (!device || !acpi_driver_data(device)) + return -EINVAL; + + mem_device = acpi_driver_data(device); + kfree(mem_device); + + return 0; +} + /* * Helper function to check for memory device */ -- cgit v0.10.2 From 5efc5476184173996dfcce780c2bb5e727df674e Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 22 Jun 2009 20:41:30 +0000 Subject: ACPI: EC: move acpi_ec_start() after acpi_ec_add() This patch rearranges ec_install_handlers() and acpi_ec_start() so acpi_ec_start() ends up just after acpi_ec_add(). A subsequent patch will merge them. Code movement only; no functional change. Signed-off-by: Bjorn Helgaas CC: Alexey Starikovskiy Signed-off-by: Len Brown diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index 391f331..8b387a4 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -788,6 +788,42 @@ ec_parse_device(acpi_handle handle, u32 Level, void *context, void **retval) return AE_CTRL_TERMINATE; } +static int ec_install_handlers(struct acpi_ec *ec) +{ + acpi_status status; + if (test_bit(EC_FLAGS_HANDLERS_INSTALLED, &ec->flags)) + return 0; + status = acpi_install_gpe_handler(NULL, ec->gpe, + ACPI_GPE_EDGE_TRIGGERED, + &acpi_ec_gpe_handler, ec); + if (ACPI_FAILURE(status)) + return -ENODEV; + acpi_set_gpe_type(NULL, ec->gpe, ACPI_GPE_TYPE_RUNTIME); + acpi_enable_gpe(NULL, ec->gpe); + status = acpi_install_address_space_handler(ec->handle, + ACPI_ADR_SPACE_EC, + &acpi_ec_space_handler, + NULL, ec); + if (ACPI_FAILURE(status)) { + if (status == AE_NOT_FOUND) { + /* + * Maybe OS fails in evaluating the _REG object. + * The AE_NOT_FOUND error will be ignored and OS + * continue to initialize EC. + */ + printk(KERN_ERR "Fail in evaluating the _REG object" + " of EC device. Broken bios is suspected.\n"); + } else { + acpi_remove_gpe_handler(NULL, ec->gpe, + &acpi_ec_gpe_handler); + return -ENODEV; + } + } + + set_bit(EC_FLAGS_HANDLERS_INSTALLED, &ec->flags); + return 0; +} + static void ec_remove_handlers(struct acpi_ec *ec) { if (ACPI_FAILURE(acpi_remove_address_space_handler(ec->handle, @@ -842,6 +878,26 @@ static int acpi_ec_add(struct acpi_device *device) return 0; } +static int acpi_ec_start(struct acpi_device *device) +{ + struct acpi_ec *ec; + int ret = 0; + + if (!device) + return -EINVAL; + + ec = acpi_driver_data(device); + + if (!ec) + return -EINVAL; + + ret = ec_install_handlers(ec); + + /* EC is fully operational, allow queries */ + clear_bit(EC_FLAGS_QUERY_PENDING, &ec->flags); + return ret; +} + static int acpi_ec_remove(struct acpi_device *device, int type) { struct acpi_ec *ec; @@ -888,62 +944,6 @@ ec_parse_io_ports(struct acpi_resource *resource, void *context) return AE_OK; } -static int ec_install_handlers(struct acpi_ec *ec) -{ - acpi_status status; - if (test_bit(EC_FLAGS_HANDLERS_INSTALLED, &ec->flags)) - return 0; - status = acpi_install_gpe_handler(NULL, ec->gpe, - ACPI_GPE_EDGE_TRIGGERED, - &acpi_ec_gpe_handler, ec); - if (ACPI_FAILURE(status)) - return -ENODEV; - acpi_set_gpe_type(NULL, ec->gpe, ACPI_GPE_TYPE_RUNTIME); - acpi_enable_gpe(NULL, ec->gpe); - status = acpi_install_address_space_handler(ec->handle, - ACPI_ADR_SPACE_EC, - &acpi_ec_space_handler, - NULL, ec); - if (ACPI_FAILURE(status)) { - if (status == AE_NOT_FOUND) { - /* - * Maybe OS fails in evaluating the _REG object. - * The AE_NOT_FOUND error will be ignored and OS - * continue to initialize EC. - */ - printk(KERN_ERR "Fail in evaluating the _REG object" - " of EC device. Broken bios is suspected.\n"); - } else { - acpi_remove_gpe_handler(NULL, ec->gpe, - &acpi_ec_gpe_handler); - return -ENODEV; - } - } - - set_bit(EC_FLAGS_HANDLERS_INSTALLED, &ec->flags); - return 0; -} - -static int acpi_ec_start(struct acpi_device *device) -{ - struct acpi_ec *ec; - int ret = 0; - - if (!device) - return -EINVAL; - - ec = acpi_driver_data(device); - - if (!ec) - return -EINVAL; - - ret = ec_install_handlers(ec); - - /* EC is fully operational, allow queries */ - clear_bit(EC_FLAGS_QUERY_PENDING, &ec->flags); - return ret; -} - static int acpi_ec_stop(struct acpi_device *device, int type) { struct acpi_ec *ec; -- cgit v0.10.2 From d02be04707b8ff5375a76c027327e8708877da39 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 22 Jun 2009 20:41:35 +0000 Subject: ACPI: EC: remove .start() method This patch folds the .start() method into .add(). acpi_ec_start() is always called immediately after acpi_ec_add(), so there's no need to have it be a separate method. Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Chiang CC: Alexey Starikovskiy Signed-off-by: Len Brown diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index 8b387a4..1feedce 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -838,9 +838,8 @@ static void ec_remove_handlers(struct acpi_ec *ec) static int acpi_ec_add(struct acpi_device *device) { struct acpi_ec *ec = NULL; + int ret; - if (!device) - return -EINVAL; strcpy(acpi_device_name(device), ACPI_EC_DEVICE_NAME); strcpy(acpi_device_class(device), ACPI_EC_CLASS); @@ -875,21 +874,6 @@ static int acpi_ec_add(struct acpi_device *device) ec->gpe, ec->command_addr, ec->data_addr); pr_info(PREFIX "driver started in %s mode\n", (test_bit(EC_FLAGS_GPE_MODE, &ec->flags))?"interrupt":"poll"); - return 0; -} - -static int acpi_ec_start(struct acpi_device *device) -{ - struct acpi_ec *ec; - int ret = 0; - - if (!device) - return -EINVAL; - - ec = acpi_driver_data(device); - - if (!ec) - return -EINVAL; ret = ec_install_handlers(ec); @@ -1077,7 +1061,6 @@ static struct acpi_driver acpi_ec_driver = { .ops = { .add = acpi_ec_add, .remove = acpi_ec_remove, - .start = acpi_ec_start, .stop = acpi_ec_stop, .suspend = acpi_ec_suspend, .resume = acpi_ec_resume, -- cgit v0.10.2 From cf745ec7a1222a661b2c5f0e8c2c4be81300d2a4 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 22 Jun 2009 20:41:40 +0000 Subject: ACPI: EC: remove .stop() method This patch folds the .stop() method into .remove(). acpi_ec_stop() is only called via acpi_device_probe() and acpi_device_remove(), and in both cases it is called immediately before acpi_ec_remove(), so there's no need to have it be a separate method. Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Chiang CC: Alexey Starikovskiy Signed-off-by: Len Brown diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index 1feedce..d6bf057 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -891,6 +891,7 @@ static int acpi_ec_remove(struct acpi_device *device, int type) return -EINVAL; ec = acpi_driver_data(device); + ec_remove_handlers(ec); mutex_lock(&ec->lock); list_for_each_entry_safe(handler, tmp, &ec->list, node) { list_del(&handler->node); @@ -928,19 +929,6 @@ ec_parse_io_ports(struct acpi_resource *resource, void *context) return AE_OK; } -static int acpi_ec_stop(struct acpi_device *device, int type) -{ - struct acpi_ec *ec; - if (!device) - return -EINVAL; - ec = acpi_driver_data(device); - if (!ec) - return -EINVAL; - ec_remove_handlers(ec); - - return 0; -} - int __init acpi_boot_ec_enable(void) { if (!boot_ec || test_bit(EC_FLAGS_HANDLERS_INSTALLED, &boot_ec->flags)) @@ -1061,7 +1049,6 @@ static struct acpi_driver acpi_ec_driver = { .ops = { .add = acpi_ec_add, .remove = acpi_ec_remove, - .stop = acpi_ec_stop, .suspend = acpi_ec_suspend, .resume = acpi_ec_resume, }, -- cgit v0.10.2 From dcf52fb71d988ba945054308f661bddf9b2455fb Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 22 Jun 2009 20:41:45 +0000 Subject: ACPI: remove unused acpi_device_ops .stop method No drivers use the .stop method, so remove it. Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Chiang Signed-off-by: Len Brown diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 781435d..4a89f08 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -426,9 +426,6 @@ static int acpi_device_probe(struct device * dev) if (acpi_drv->ops.notify) { ret = acpi_device_install_notify_handler(acpi_dev); if (ret) { - if (acpi_drv->ops.stop) - acpi_drv->ops.stop(acpi_dev, - acpi_dev->removal_type); if (acpi_drv->ops.remove) acpi_drv->ops.remove(acpi_dev, acpi_dev->removal_type); @@ -452,8 +449,6 @@ static int acpi_device_remove(struct device * dev) if (acpi_drv) { if (acpi_drv->ops.notify) acpi_device_remove_notify_handler(acpi_dev); - if (acpi_drv->ops.stop) - acpi_drv->ops.stop(acpi_dev, acpi_dev->removal_type); if (acpi_drv->ops.remove) acpi_drv->ops.remove(acpi_dev, acpi_dev->removal_type); } diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index c65e4ce..79a6c5e 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -89,7 +89,6 @@ struct acpi_device; typedef int (*acpi_op_add) (struct acpi_device * device); typedef int (*acpi_op_remove) (struct acpi_device * device, int type); typedef int (*acpi_op_start) (struct acpi_device * device); -typedef int (*acpi_op_stop) (struct acpi_device * device, int type); typedef int (*acpi_op_suspend) (struct acpi_device * device, pm_message_t state); typedef int (*acpi_op_resume) (struct acpi_device * device); @@ -106,7 +105,6 @@ struct acpi_device_ops { acpi_op_add add; acpi_op_remove remove; acpi_op_start start; - acpi_op_stop stop; acpi_op_suspend suspend; acpi_op_resume resume; acpi_op_bind bind; -- cgit v0.10.2 From b294a290d24d1196d68399cc3a9b8c50bfb55abd Mon Sep 17 00:00:00 2001 From: Andres Salomon Date: Tue, 30 Jun 2009 02:13:01 -0400 Subject: Revert "power: remove POWER_SUPPLY_PROP_CAPACITY_LEVEL" This reverts commit 8efe444038a205e79b38b7ad03878824901849a8 and 4cbc76eadf56399cd11fb736b33c53aec9caab8c. Richard@laptop.org was apparently using CAPACITY_LEVEL for debugging battery/EC problems, and was upset that it was removed. This readds it. Conflicts: Documentation/power_supply_class.txt Signed-off-by: Andres Salomon Signed-off-by: Anton Vorontsov diff --git a/Documentation/power/power_supply_class.txt b/Documentation/power/power_supply_class.txt index c6cd495..709d955 100644 --- a/Documentation/power/power_supply_class.txt +++ b/Documentation/power/power_supply_class.txt @@ -108,6 +108,8 @@ relative, time-based measurements. ENERGY_FULL, ENERGY_EMPTY - same as above but for energy. CAPACITY - capacity in percents. +CAPACITY_LEVEL - capacity level. This corresponds to +POWER_SUPPLY_CAPACITY_LEVEL_*. TEMP - temperature of the power supply. TEMP_AMBIENT - ambient temperature. diff --git a/drivers/power/olpc_battery.c b/drivers/power/olpc_battery.c index 58e4192..3a589df0 100644 --- a/drivers/power/olpc_battery.c +++ b/drivers/power/olpc_battery.c @@ -276,6 +276,14 @@ static int olpc_bat_get_property(struct power_supply *psy, return ret; val->intval = ec_byte; break; + case POWER_SUPPLY_PROP_CAPACITY_LEVEL: + if (ec_byte & BAT_STAT_FULL) + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_FULL; + else if (ec_byte & BAT_STAT_LOW) + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_LOW; + else + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; + break; case POWER_SUPPLY_PROP_TEMP: ret = olpc_ec_cmd(EC_BAT_TEMP, NULL, 0, (void *)&ec_word, 2); if (ret) @@ -321,6 +329,7 @@ static enum power_supply_property olpc_bat_props[] = { POWER_SUPPLY_PROP_VOLTAGE_AVG, POWER_SUPPLY_PROP_CURRENT_AVG, POWER_SUPPLY_PROP_CAPACITY, + POWER_SUPPLY_PROP_CAPACITY_LEVEL, POWER_SUPPLY_PROP_TEMP, POWER_SUPPLY_PROP_TEMP_AMBIENT, POWER_SUPPLY_PROP_MANUFACTURER, diff --git a/drivers/power/power_supply_sysfs.c b/drivers/power/power_supply_sysfs.c index da73591..9deabbd 100644 --- a/drivers/power/power_supply_sysfs.c +++ b/drivers/power/power_supply_sysfs.c @@ -51,6 +51,9 @@ static ssize_t power_supply_show_property(struct device *dev, "Unknown", "NiMH", "Li-ion", "Li-poly", "LiFe", "NiCd", "LiMn" }; + static char *capacity_level_text[] = { + "Unknown", "Critical", "Low", "Normal", "High", "Full" + }; ssize_t ret; struct power_supply *psy = dev_get_drvdata(dev); const ptrdiff_t off = attr - power_supply_attrs; @@ -71,6 +74,8 @@ static ssize_t power_supply_show_property(struct device *dev, return sprintf(buf, "%s\n", health_text[value.intval]); else if (off == POWER_SUPPLY_PROP_TECHNOLOGY) return sprintf(buf, "%s\n", technology_text[value.intval]); + else if (off == POWER_SUPPLY_PROP_CAPACITY_LEVEL) + return sprintf(buf, "%s\n", capacity_level_text[value.intval]); else if (off >= POWER_SUPPLY_PROP_MODEL_NAME) return sprintf(buf, "%s\n", value.strval); @@ -109,6 +114,7 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(energy_now), POWER_SUPPLY_ATTR(energy_avg), POWER_SUPPLY_ATTR(capacity), + POWER_SUPPLY_ATTR(capacity_level), POWER_SUPPLY_ATTR(temp), POWER_SUPPLY_ATTR(temp_ambient), POWER_SUPPLY_ATTR(time_to_empty_now), diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 594c494..0ab6aa1 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -58,6 +58,15 @@ enum { POWER_SUPPLY_TECHNOLOGY_LiMn, }; +enum { + POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN = 0, + POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL, + POWER_SUPPLY_CAPACITY_LEVEL_LOW, + POWER_SUPPLY_CAPACITY_LEVEL_NORMAL, + POWER_SUPPLY_CAPACITY_LEVEL_HIGH, + POWER_SUPPLY_CAPACITY_LEVEL_FULL, +}; + enum power_supply_property { /* Properties of type `int' */ POWER_SUPPLY_PROP_STATUS = 0, @@ -89,6 +98,7 @@ enum power_supply_property { POWER_SUPPLY_PROP_ENERGY_NOW, POWER_SUPPLY_PROP_ENERGY_AVG, POWER_SUPPLY_PROP_CAPACITY, /* in percents! */ + POWER_SUPPLY_PROP_CAPACITY_LEVEL, POWER_SUPPLY_PROP_TEMP, POWER_SUPPLY_PROP_TEMP_AMBIENT, POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW, -- cgit v0.10.2 From 144bbeaedc53290eab21da82ce1cb5faefd14374 Mon Sep 17 00:00:00 2001 From: Andres Salomon Date: Tue, 30 Jun 2009 02:15:26 -0400 Subject: olpc_battery: Add an 'error' sysfs device that displays raw errors Grab the error code from EC_BAT_ERRCODE and let the user see it (rather than attempting to decode it as we do with PROP_HEALTH) with a separate error sysfs file. Signed-off-by: Andres Salomon Signed-off-by: Anton Vorontsov diff --git a/drivers/power/olpc_battery.c b/drivers/power/olpc_battery.c index 3a589df0..602bbd0 100644 --- a/drivers/power/olpc_battery.c +++ b/drivers/power/olpc_battery.c @@ -10,7 +10,9 @@ #include #include +#include #include +#include #include #include #include @@ -379,6 +381,29 @@ static struct bin_attribute olpc_bat_eeprom = { .read = olpc_bat_eeprom_read, }; +/* Allow userspace to see the specific error value pulled from the EC */ + +static ssize_t olpc_bat_error_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + uint8_t ec_byte; + ssize_t ret; + + ret = olpc_ec_cmd(EC_BAT_ERRCODE, NULL, 0, &ec_byte, 1); + if (ret < 0) + return ret; + + return sprintf(buf, "%d\n", ec_byte); +} + +static struct device_attribute olpc_bat_error = { + .attr = { + .name = "error", + .mode = S_IRUGO, + }, + .show = olpc_bat_error_read, +}; + /********************************************************************* * Initialisation *********************************************************************/ @@ -442,8 +467,14 @@ static int __init olpc_bat_init(void) if (ret) goto eeprom_failed; + ret = device_create_file(olpc_bat.dev, &olpc_bat_error); + if (ret) + goto error_failed; + goto success; +error_failed: + device_remove_bin_file(olpc_bat.dev, &olpc_bat_eeprom); eeprom_failed: power_supply_unregister(&olpc_bat); battery_failed: @@ -456,6 +487,7 @@ success: static void __exit olpc_bat_exit(void) { + device_remove_file(olpc_bat.dev, &olpc_bat_error); device_remove_bin_file(olpc_bat.dev, &olpc_bat_eeprom); power_supply_unregister(&olpc_bat); power_supply_unregister(&olpc_ac); -- cgit v0.10.2 From a4a874a906ae69c35df4b712fadbc35b15665355 Mon Sep 17 00:00:00 2001 From: Huang Weiyi Date: Thu, 18 Jun 2009 07:05:46 +0800 Subject: kmemcheck: remove duplicated #include Remove duplicated #include in arch/x86/mm/kmemcheck/shadow.c. Signed-off-by: Huang Weiyi Acked-by: Pekka Enberg Signed-off-by: Vegard Nossum diff --git a/arch/x86/mm/kmemcheck/shadow.c b/arch/x86/mm/kmemcheck/shadow.c index e773b6b..3f66b82 100644 --- a/arch/x86/mm/kmemcheck/shadow.c +++ b/arch/x86/mm/kmemcheck/shadow.c @@ -1,7 +1,6 @@ #include #include #include -#include #include #include -- cgit v0.10.2 From 414f3251aa1b4cbd1e070866971eabc004a7dc20 Mon Sep 17 00:00:00 2001 From: Vegard Nossum Date: Mon, 22 Jun 2009 14:31:53 +0200 Subject: kmemcheck: remove useless check This check is a left-over from ancient times. We now have the equivalent check much earlier in both the page fault handler and the debug trap handler (the calls to kmemcheck_active()). Signed-off-by: Vegard Nossum diff --git a/arch/x86/mm/kmemcheck/kmemcheck.c b/arch/x86/mm/kmemcheck/kmemcheck.c index 2c55ed0..5b99004 100644 --- a/arch/x86/mm/kmemcheck/kmemcheck.c +++ b/arch/x86/mm/kmemcheck/kmemcheck.c @@ -225,9 +225,6 @@ void kmemcheck_hide(struct pt_regs *regs) BUG_ON(!irqs_disabled()); - if (data->balance == 0) - return; - if (unlikely(data->balance != 1)) { kmemcheck_show_all(); kmemcheck_error_save_bug(regs); -- cgit v0.10.2 From d33c9a491bc87fb87fd0298d0425f0ff320d20a2 Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Sun, 28 Jun 2009 13:10:19 +0200 Subject: kmemcheck: depend on HAVE_ARCH_KMEMCHECK to make it selectable if it is available. Signed-off-by: Sebastian Andrzej Siewior Acked-by: Pekka Enberg Signed-off-by: Vegard Nossum diff --git a/lib/Kconfig.kmemcheck b/lib/Kconfig.kmemcheck index 603c81b..846e039 100644 --- a/lib/Kconfig.kmemcheck +++ b/lib/Kconfig.kmemcheck @@ -1,6 +1,8 @@ config HAVE_ARCH_KMEMCHECK bool +if HAVE_ARCH_KMEMCHECK + menuconfig KMEMCHECK bool "kmemcheck: trap use of uninitialized memory" depends on DEBUG_KERNEL @@ -89,3 +91,4 @@ config KMEMCHECK_BITOPS_OK accesses where not all the bits are initialized at the same time. This may also hide some real bugs. +endif -- cgit v0.10.2 From e3c6c4a8af9e3c4588235444774e66b6483b10ad Mon Sep 17 00:00:00 2001 From: Vegard Nossum Date: Wed, 1 Jul 2009 22:36:22 +0200 Subject: kmemcheck: update documentation The download instructions are no longer needed since kmemcheck was included in mainline. Signed-off-by: Vegard Nossum diff --git a/Documentation/kmemcheck.txt b/Documentation/kmemcheck.txt index 36304460..c28f828 100644 --- a/Documentation/kmemcheck.txt +++ b/Documentation/kmemcheck.txt @@ -43,26 +43,7 @@ feature. 1. Downloading ============== -kmemcheck can only be downloaded using git. If you want to write patches -against the current code, you should use the kmemcheck development branch of -the tip tree. It is also possible to use the linux-next tree, which also -includes the latest version of kmemcheck. - -Assuming that you've already cloned the linux-2.6.git repository, all you -have to do is add the -tip tree as a remote, like this: - - $ git remote add tip git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip.git - -To actually download the tree, fetch the remote: - - $ git fetch tip - -And to check out a new local branch with the kmemcheck code: - - $ git checkout -b kmemcheck tip/kmemcheck - -General instructions for the -tip tree can be found here: -http://people.redhat.com/mingo/tip.git/readme.txt +As of version 2.6.31-rc1, kmemcheck is included in the mainline kernel. 2. Configuring and compiling -- cgit v0.10.2 From ee8076ed3e1cdd0cd1e61318386932669c90b92f Mon Sep 17 00:00:00 2001 From: Andres Salomon Date: Thu, 2 Jul 2009 09:45:18 -0400 Subject: power_supply: Add a charge_type property, and use it for olpc driver This adds a new sysfs file called 'charge_type' which displays the type of charging (unknown, n/a, trickle charge, or fast charging). This allows things like battery diagnostics to determine what the battery/EC is doing without resorting to changing the 'status' sysfs output. Signed-off-by: Andres Salomon Acked-by: Mark Brown Signed-off-by: Anton Vorontsov diff --git a/Documentation/power/power_supply_class.txt b/Documentation/power/power_supply_class.txt index 709d955..9f16c51 100644 --- a/Documentation/power/power_supply_class.txt +++ b/Documentation/power/power_supply_class.txt @@ -76,6 +76,11 @@ STATUS - this attribute represents operating status (charging, full, discharging (i.e. powering a load), etc.). This corresponds to BATTERY_STATUS_* values, as defined in battery.h. +CHARGE_TYPE - batteries can typically charge at different rates. +This defines trickle and fast charges. For batteries that +are already charged or discharging, 'n/a' can be displayed (or +'unknown', if the status is not known). + HEALTH - represents health of the battery, values corresponds to POWER_SUPPLY_HEALTH_*, defined in battery.h. diff --git a/drivers/power/olpc_battery.c b/drivers/power/olpc_battery.c index 602bbd0..8fefe5a 100644 --- a/drivers/power/olpc_battery.c +++ b/drivers/power/olpc_battery.c @@ -233,6 +233,14 @@ static int olpc_bat_get_property(struct power_supply *psy, if (ret) return ret; break; + case POWER_SUPPLY_PROP_CHARGE_TYPE: + if (ec_byte & BAT_STAT_TRICKLE) + val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; + else if (ec_byte & BAT_STAT_CHARGING) + val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST; + else + val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; + break; case POWER_SUPPLY_PROP_PRESENT: val->intval = !!(ec_byte & (BAT_STAT_PRESENT | BAT_STAT_TRICKLE)); @@ -325,6 +333,7 @@ static int olpc_bat_get_property(struct power_supply *psy, static enum power_supply_property olpc_bat_props[] = { POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_CHARGE_TYPE, POWER_SUPPLY_PROP_PRESENT, POWER_SUPPLY_PROP_HEALTH, POWER_SUPPLY_PROP_TECHNOLOGY, diff --git a/drivers/power/power_supply_sysfs.c b/drivers/power/power_supply_sysfs.c index 9deabbd..0814439 100644 --- a/drivers/power/power_supply_sysfs.c +++ b/drivers/power/power_supply_sysfs.c @@ -43,6 +43,9 @@ static ssize_t power_supply_show_property(struct device *dev, static char *status_text[] = { "Unknown", "Charging", "Discharging", "Not charging", "Full" }; + static char *charge_type[] = { + "Unknown", "N/A", "Trickle", "Fast" + }; static char *health_text[] = { "Unknown", "Good", "Overheat", "Dead", "Over voltage", "Unspecified failure", "Cold", @@ -70,6 +73,8 @@ static ssize_t power_supply_show_property(struct device *dev, if (off == POWER_SUPPLY_PROP_STATUS) return sprintf(buf, "%s\n", status_text[value.intval]); + else if (off == POWER_SUPPLY_PROP_CHARGE_TYPE) + return sprintf(buf, "%s\n", charge_type[value.intval]); else if (off == POWER_SUPPLY_PROP_HEALTH) return sprintf(buf, "%s\n", health_text[value.intval]); else if (off == POWER_SUPPLY_PROP_TECHNOLOGY) @@ -86,6 +91,7 @@ static ssize_t power_supply_show_property(struct device *dev, static struct device_attribute power_supply_attrs[] = { /* Properties of type `int' */ POWER_SUPPLY_ATTR(status), + POWER_SUPPLY_ATTR(charge_type), POWER_SUPPLY_ATTR(health), POWER_SUPPLY_ATTR(present), POWER_SUPPLY_ATTR(online), diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 0ab6aa1..4c7c6fc 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -39,6 +39,13 @@ enum { }; enum { + POWER_SUPPLY_CHARGE_TYPE_UNKNOWN = 0, + POWER_SUPPLY_CHARGE_TYPE_NONE, + POWER_SUPPLY_CHARGE_TYPE_TRICKLE, + POWER_SUPPLY_CHARGE_TYPE_FAST, +}; + +enum { POWER_SUPPLY_HEALTH_UNKNOWN = 0, POWER_SUPPLY_HEALTH_GOOD, POWER_SUPPLY_HEALTH_OVERHEAT, @@ -70,6 +77,7 @@ enum { enum power_supply_property { /* Properties of type `int' */ POWER_SUPPLY_PROP_STATUS = 0, + POWER_SUPPLY_PROP_CHARGE_TYPE, POWER_SUPPLY_PROP_HEALTH, POWER_SUPPLY_PROP_PRESENT, POWER_SUPPLY_PROP_ONLINE, -- cgit v0.10.2 From 846d8e7cc82a6205d5c0a905a4940abd0f565741 Mon Sep 17 00:00:00 2001 From: Wei Yongjun Date: Thu, 25 Jun 2009 16:35:44 +0800 Subject: svcrdma: fix error handling of rdma_alloc_frmr() ib_alloc_fast_reg_mr() and ib_alloc_fast_reg_page_list() returns ERR_PTR() and not NULL. Compile tested only. Signed-off-by: Wei Yongjun Signed-off-by: J. Bruce Fields diff --git a/net/sunrpc/xprtrdma/svc_rdma_transport.c b/net/sunrpc/xprtrdma/svc_rdma_transport.c index 5151f9f..0cf5e8c 100644 --- a/net/sunrpc/xprtrdma/svc_rdma_transport.c +++ b/net/sunrpc/xprtrdma/svc_rdma_transport.c @@ -730,12 +730,12 @@ static struct svc_rdma_fastreg_mr *rdma_alloc_frmr(struct svcxprt_rdma *xprt) goto err; mr = ib_alloc_fast_reg_mr(xprt->sc_pd, RPCSVC_MAXPAGES); - if (!mr) + if (IS_ERR(mr)) goto err_free_frmr; pl = ib_alloc_fast_reg_page_list(xprt->sc_cm_id->device, RPCSVC_MAXPAGES); - if (!pl) + if (IS_ERR(pl)) goto err_free_mr; frmr->mr = mr; -- cgit v0.10.2 From 147202aa772329a02c6e80bc2b7a6b8dd3deac0b Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Tue, 7 Jul 2009 19:43:20 +0100 Subject: intel-iommu: Speed up map routines by using cached domain ASAP We did before, in the end -- but it was at the bottom of a long stack of functions. Add an inline wrapper get_valid_domain_for_dev() which will use the cached one _first_ and only make the out-of-line call if it's not already set. This takes the average time taken for a 1-page intel_map_sg() from 5961 cycles to 4812 cycles on my Lenovo x200s test box -- a modest 20%. Signed-off-by: David Woodhouse diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index 360fb67..c5f7c73 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -2455,8 +2455,7 @@ static struct iova *intel_alloc_iova(struct device *dev, return iova; } -static struct dmar_domain * -get_valid_domain_for_dev(struct pci_dev *pdev) +static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev) { struct dmar_domain *domain; int ret; @@ -2484,6 +2483,18 @@ get_valid_domain_for_dev(struct pci_dev *pdev) return domain; } +static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev) +{ + struct device_domain_info *info; + + /* No lock here, assumes no domain exit in normal case */ + info = dev->dev.archdata.iommu; + if (likely(info)) + return info->domain; + + return __get_valid_domain_for_dev(dev); +} + static int iommu_dummy(struct pci_dev *pdev) { return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; -- cgit v0.10.2 From 5a421ce3c062a87db0a9e7f2a0a7ee0a5b869aab Mon Sep 17 00:00:00 2001 From: Benny Halevy Date: Fri, 10 Jul 2009 12:37:40 +0300 Subject: nfsd41: gather and report statistics also for v4.1 ops Signed-off-by: Benny Halevy Signed-off-by: J. Bruce Fields diff --git a/include/linux/nfs4.h b/include/linux/nfs4.h index bd2eba5..aff924a 100644 --- a/include/linux/nfs4.h +++ b/include/linux/nfs4.h @@ -234,7 +234,7 @@ enum nfs_opnum4 { Needs to be updated if more operations are defined in future.*/ #define FIRST_NFS4_OP OP_ACCESS -#define LAST_NFS4_OP OP_RELEASE_LOCKOWNER +#define LAST_NFS4_OP OP_RECLAIM_COMPLETE enum nfsstat4 { NFS4_OK = 0, -- cgit v0.10.2 From 4aed03ae58946c716c8e3f7060f8b500b8a8e30f Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 10 Jul 2009 16:28:33 +0100 Subject: wm8350_power: Implement charge type property Signed-off-by: Mark Brown Signed-off-by: Anton Vorontsov diff --git a/drivers/power/wm8350_power.c b/drivers/power/wm8350_power.c index 1b16bf3..28b0299 100644 --- a/drivers/power/wm8350_power.c +++ b/drivers/power/wm8350_power.c @@ -321,6 +321,24 @@ static int wm8350_bat_check_health(struct wm8350 *wm8350) return POWER_SUPPLY_HEALTH_GOOD; } +static int wm8350_bat_get_charge_type(struct wm8350 *wm8350) +{ + int state; + + state = wm8350_reg_read(wm8350, WM8350_BATTERY_CHARGER_CONTROL_2) & + WM8350_CHG_STS_MASK; + switch (state) { + case WM8350_CHG_STS_OFF: + return POWER_SUPPLY_CHARGE_TYPE_NONE; + case WM8350_CHG_STS_TRICKLE: + return POWER_SUPPLY_CHARGE_TYPE_TRICKLE; + case WM8350_CHG_STS_FAST: + return POWER_SUPPLY_CHARGE_TYPE_FAST; + default: + return POWER_SUPPLY_CHARGE_TYPE_UNKNOWN; + } +} + static int wm8350_bat_get_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) @@ -342,6 +360,9 @@ static int wm8350_bat_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_HEALTH: val->intval = wm8350_bat_check_health(wm8350); break; + case POWER_SUPPLY_PROP_CHARGE_TYPE: + val->intval = wm8350_bat_get_charge_type(wm8350); + break; default: ret = -EINVAL; break; @@ -355,6 +376,7 @@ static enum power_supply_property wm8350_bat_props[] = { POWER_SUPPLY_PROP_ONLINE, POWER_SUPPLY_PROP_VOLTAGE_NOW, POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_CHARGE_TYPE, }; /********************************************************************* -- cgit v0.10.2 From 9208faf297dddfa97a86d7224b6bf94f2e346dd9 Mon Sep 17 00:00:00 2001 From: Yu Zhiguo Date: Mon, 6 Jul 2009 17:24:16 +0800 Subject: NFSv4: ACL in operations 'open' and 'create' should be used ACL in operations 'open' and 'create' is decoded but never be used. It should be set as the initial ACL for the object according to RFC3530. If error occurs when setting the ACL, just clear the ACL bit in the returned attr bitmap. Signed-off-by: Yu Zhiguo Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c index 7c88017..d781658 100644 --- a/fs/nfsd/nfs4proc.c +++ b/fs/nfsd/nfs4proc.c @@ -123,6 +123,35 @@ nfsd4_check_open_attributes(struct svc_rqst *rqstp, return status; } +static int +is_create_with_attrs(struct nfsd4_open *open) +{ + return open->op_create == NFS4_OPEN_CREATE + && (open->op_createmode == NFS4_CREATE_UNCHECKED + || open->op_createmode == NFS4_CREATE_GUARDED + || open->op_createmode == NFS4_CREATE_EXCLUSIVE4_1); +} + +/* + * if error occurs when setting the acl, just clear the acl bit + * in the returned attr bitmap. + */ +static void +do_set_nfs4_acl(struct svc_rqst *rqstp, struct svc_fh *fhp, + struct nfs4_acl *acl, u32 *bmval) +{ + __be32 status; + + status = nfsd4_set_nfs4_acl(rqstp, fhp, acl); + if (status) + /* + * We should probably fail the whole open at this point, + * but we've already created the file, so it's too late; + * So this seems the least of evils: + */ + bmval[0] &= ~FATTR4_WORD0_ACL; +} + static inline void fh_dup2(struct svc_fh *dst, struct svc_fh *src) { @@ -206,6 +235,9 @@ do_open_lookup(struct svc_rqst *rqstp, struct svc_fh *current_fh, struct nfsd4_o if (status) goto out; + if (is_create_with_attrs(open) && open->op_acl != NULL) + do_set_nfs4_acl(rqstp, &resfh, open->op_acl, open->op_bmval); + set_change_info(&open->op_cinfo, current_fh); fh_dup2(current_fh, &resfh); @@ -536,12 +568,17 @@ nfsd4_create(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, status = nfserr_badtype; } - if (!status) { - fh_unlock(&cstate->current_fh); - set_change_info(&create->cr_cinfo, &cstate->current_fh); - fh_dup2(&cstate->current_fh, &resfh); - } + if (status) + goto out; + if (create->cr_acl != NULL) + do_set_nfs4_acl(rqstp, &resfh, create->cr_acl, + create->cr_bmval); + + fh_unlock(&cstate->current_fh); + set_change_info(&create->cr_cinfo, &cstate->current_fh); + fh_dup2(&cstate->current_fh, &resfh); +out: fh_put(&resfh); return status; } -- cgit v0.10.2 From a11034b4282515fd7d9f6fdc0a1380781da461c3 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 14 Jul 2009 11:48:16 -0700 Subject: md/raid6: release spare page at ->stop() Add missing call to safe_put_page from stop() by unifying open coded raid5_conf_t de-allocation under free_conf(). Signed-off-by: Dan Williams diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index e1920f2..9411466 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -4309,6 +4309,15 @@ raid5_size(mddev_t *mddev, sector_t sectors, int raid_disks) return sectors * (raid_disks - conf->max_degraded); } +static void free_conf(raid5_conf_t *conf) +{ + shrink_stripes(conf); + safe_put_page(conf->spare_page); + kfree(conf->disks); + kfree(conf->stripe_hashtbl); + kfree(conf); +} + static raid5_conf_t *setup_conf(mddev_t *mddev) { raid5_conf_t *conf; @@ -4438,11 +4447,7 @@ static raid5_conf_t *setup_conf(mddev_t *mddev) abort: if (conf) { - shrink_stripes(conf); - safe_put_page(conf->spare_page); - kfree(conf->disks); - kfree(conf->stripe_hashtbl); - kfree(conf); + free_conf(conf); return ERR_PTR(-EIO); } else return ERR_PTR(-ENOMEM); @@ -4608,12 +4613,8 @@ abort: md_unregister_thread(mddev->thread); mddev->thread = NULL; if (conf) { - shrink_stripes(conf); print_raid5_conf(conf); - safe_put_page(conf->spare_page); - kfree(conf->disks); - kfree(conf->stripe_hashtbl); - kfree(conf); + free_conf(conf); } mddev->private = NULL; printk(KERN_ALERT "raid5: failed to run raid set %s\n", mdname(mddev)); @@ -4628,13 +4629,10 @@ static int stop(mddev_t *mddev) md_unregister_thread(mddev->thread); mddev->thread = NULL; - shrink_stripes(conf); - kfree(conf->stripe_hashtbl); mddev->queue->backing_dev_info.congested_fn = NULL; blk_sync_queue(mddev->queue); /* the unplug fn references 'conf'*/ sysfs_remove_group(&mddev->kobj, &raid5_attrs_group); - kfree(conf->disks); - kfree(conf); + free_conf(conf); mddev->private = NULL; return 0; } -- cgit v0.10.2 From 7702ce40bc84a02e88aa20f95333df8cff5f9d37 Mon Sep 17 00:00:00 2001 From: Chuck Lever Date: Mon, 13 Jul 2009 10:54:26 -0400 Subject: SUNRPC: handle IPv6 PKTINFO when extracting destination address PKTINFO is needed to scrape the caller's IP address off the socket so RPC datagram replies are routed correctly. Fill in missing pieces in the kernel RPC server's UDP receive path to request IPv6 PKTINFO and correctly parse the IPv6 cmsg header. Without this patch, kernel RPC services drop all incoming requests on UDP on IPv6. Related commit: 7a37f5787e76bf1765c1add3a9a7163f841a28bb Signed-off-by: Chuck Lever Cc: Neil Brown Signed-off-by: J. Bruce Fields diff --git a/net/sunrpc/svcsock.c b/net/sunrpc/svcsock.c index 23128ee..99a826d 100644 --- a/net/sunrpc/svcsock.c +++ b/net/sunrpc/svcsock.c @@ -432,29 +432,49 @@ static void svc_tcp_write_space(struct sock *sk) } /* + * See net/ipv6/ip_sockglue.c : ip_cmsg_recv_pktinfo + */ +static int svc_udp_get_dest_address4(struct svc_rqst *rqstp, + struct cmsghdr *cmh) +{ + struct in_pktinfo *pki = CMSG_DATA(cmh); + if (cmh->cmsg_type != IP_PKTINFO) + return 0; + rqstp->rq_daddr.addr.s_addr = pki->ipi_spec_dst.s_addr; + return 1; +} + +/* + * See net/ipv6/datagram.c : datagram_recv_ctl + */ +static int svc_udp_get_dest_address6(struct svc_rqst *rqstp, + struct cmsghdr *cmh) +{ + struct in6_pktinfo *pki = CMSG_DATA(cmh); + if (cmh->cmsg_type != IPV6_PKTINFO) + return 0; + ipv6_addr_copy(&rqstp->rq_daddr.addr6, &pki->ipi6_addr); + return 1; +} + +/* * Copy the UDP datagram's destination address to the rqstp structure. * The 'destination' address in this case is the address to which the * peer sent the datagram, i.e. our local address. For multihomed * hosts, this can change from msg to msg. Note that only the IP * address changes, the port number should remain the same. */ -static void svc_udp_get_dest_address(struct svc_rqst *rqstp, - struct cmsghdr *cmh) +static int svc_udp_get_dest_address(struct svc_rqst *rqstp, + struct cmsghdr *cmh) { - struct svc_sock *svsk = - container_of(rqstp->rq_xprt, struct svc_sock, sk_xprt); - switch (svsk->sk_sk->sk_family) { - case AF_INET: { - struct in_pktinfo *pki = CMSG_DATA(cmh); - rqstp->rq_daddr.addr.s_addr = pki->ipi_spec_dst.s_addr; - break; - } - case AF_INET6: { - struct in6_pktinfo *pki = CMSG_DATA(cmh); - ipv6_addr_copy(&rqstp->rq_daddr.addr6, &pki->ipi6_addr); - break; - } + switch (cmh->cmsg_level) { + case SOL_IP: + return svc_udp_get_dest_address4(rqstp, cmh); + case SOL_IPV6: + return svc_udp_get_dest_address6(rqstp, cmh); } + + return 0; } /* @@ -531,16 +551,15 @@ static int svc_udp_recvfrom(struct svc_rqst *rqstp) rqstp->rq_prot = IPPROTO_UDP; - if (cmh->cmsg_level != IPPROTO_IP || - cmh->cmsg_type != IP_PKTINFO) { + if (!svc_udp_get_dest_address(rqstp, cmh)) { if (net_ratelimit()) - printk("rpcsvc: received unknown control message:" - "%d/%d\n", - cmh->cmsg_level, cmh->cmsg_type); + printk(KERN_WARNING + "svc: received unknown control message %d/%d; " + "dropping RPC reply datagram\n", + cmh->cmsg_level, cmh->cmsg_type); skb_free_datagram(svsk->sk_sk, skb); return 0; } - svc_udp_get_dest_address(rqstp, cmh); if (skb_is_nonlinear(skb)) { /* we have to copy */ @@ -651,8 +670,7 @@ static struct svc_xprt_class svc_udp_class = { static void svc_udp_init(struct svc_sock *svsk, struct svc_serv *serv) { - int one = 1; - mm_segment_t oldfs; + int err, level, optname, one = 1; svc_xprt_init(&svc_udp_class, &svsk->sk_xprt, serv); clear_bit(XPT_CACHE_AUTH, &svsk->sk_xprt.xpt_flags); @@ -671,12 +689,22 @@ static void svc_udp_init(struct svc_sock *svsk, struct svc_serv *serv) set_bit(XPT_DATA, &svsk->sk_xprt.xpt_flags); set_bit(XPT_CHNGBUF, &svsk->sk_xprt.xpt_flags); - oldfs = get_fs(); - set_fs(KERNEL_DS); /* make sure we get destination address info */ - svsk->sk_sock->ops->setsockopt(svsk->sk_sock, IPPROTO_IP, IP_PKTINFO, - (char __user *)&one, sizeof(one)); - set_fs(oldfs); + switch (svsk->sk_sk->sk_family) { + case AF_INET: + level = SOL_IP; + optname = IP_PKTINFO; + break; + case AF_INET6: + level = SOL_IPV6; + optname = IPV6_RECVPKTINFO; + break; + default: + BUG(); + } + err = kernel_setsockopt(svsk->sk_sock, level, optname, + (char *)&one, sizeof(one)); + dprintk("svc: kernel_setsockopt returned %d\n", err); } /* -- cgit v0.10.2 From 4bd9b0f4afc76cf972578c702e1bc1b6f2d10ba5 Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Wed, 24 Jun 2009 15:37:45 -0400 Subject: nfsd41: use globals for DRC limits The version 4.1 DRC memory limit and tracking variables are server wide and session specific. Replace struct svc_serv fields with globals. Stop using the svc_serv sv_lock. Add a spinlock to serialize access to the DRC limit management variables which change on session creation and deletion (usage counter) or (future) administrative action to adjust the total DRC memory limit. Signed-off-by: Andy Adamson Signed-off-by: Benny Halevy diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 980a216..2e6a44e 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -430,11 +430,11 @@ static int set_forechannel_maxreqs(struct nfsd4_channel_attrs *fchan) else if (fchan->maxreqs > NFSD_MAX_SLOTS_PER_SESSION) fchan->maxreqs = NFSD_MAX_SLOTS_PER_SESSION; - spin_lock(&nfsd_serv->sv_lock); - if (np + nfsd_serv->sv_drc_pages_used > nfsd_serv->sv_drc_max_pages) - np = nfsd_serv->sv_drc_max_pages - nfsd_serv->sv_drc_pages_used; - nfsd_serv->sv_drc_pages_used += np; - spin_unlock(&nfsd_serv->sv_lock); + spin_lock(&nfsd_drc_lock); + if (np + nfsd_drc_pages_used > nfsd_drc_max_pages) + np = nfsd_drc_max_pages - nfsd_drc_pages_used; + nfsd_drc_pages_used += np; + spin_unlock(&nfsd_drc_lock); if (np <= 0) { status = nfserr_resource; diff --git a/fs/nfsd/nfssvc.c b/fs/nfsd/nfssvc.c index d4c9884..78d8fcd 100644 --- a/fs/nfsd/nfssvc.c +++ b/fs/nfsd/nfssvc.c @@ -67,6 +67,16 @@ struct timeval nfssvc_boot; DEFINE_MUTEX(nfsd_mutex); struct svc_serv *nfsd_serv; +/* + * nfsd_drc_lock protects nfsd_drc_max_pages and nfsd_drc_pages_used. + * nfsd_drc_max_pages limits the total amount of memory available for + * version 4.1 DRC caches. + * nfsd_drc_pages_used tracks the current version 4.1 DRC memory usage. + */ +spinlock_t nfsd_drc_lock; +unsigned int nfsd_drc_max_pages; +unsigned int nfsd_drc_pages_used; + #if defined(CONFIG_NFSD_V2_ACL) || defined(CONFIG_NFSD_V3_ACL) static struct svc_stat nfsd_acl_svcstats; static struct svc_version * nfsd_acl_version[] = { @@ -238,11 +248,12 @@ static void set_max_drc(void) { /* The percent of nr_free_buffer_pages used by the V4.1 server DRC */ #define NFSD_DRC_SIZE_SHIFT 7 - nfsd_serv->sv_drc_max_pages = nr_free_buffer_pages() + nfsd_drc_max_pages = nr_free_buffer_pages() >> NFSD_DRC_SIZE_SHIFT; - nfsd_serv->sv_drc_pages_used = 0; - dprintk("%s svc_drc_max_pages %u\n", __func__, - nfsd_serv->sv_drc_max_pages); + nfsd_drc_pages_used = 0; + spin_lock_init(&nfsd_drc_lock); + dprintk("%s nfsd_drc_max_pages %u\n", __func__, + nfsd_drc_max_pages); } int nfsd_create_serv(void) diff --git a/include/linux/nfsd/nfsd.h b/include/linux/nfsd/nfsd.h index 2b49d67..2571f85 100644 --- a/include/linux/nfsd/nfsd.h +++ b/include/linux/nfsd/nfsd.h @@ -56,6 +56,9 @@ extern struct svc_version nfsd_version2, nfsd_version3, extern u32 nfsd_supported_minorversion; extern struct mutex nfsd_mutex; extern struct svc_serv *nfsd_serv; +extern spinlock_t nfsd_drc_lock; +extern unsigned int nfsd_drc_max_pages; +extern unsigned int nfsd_drc_pages_used; extern struct seq_operations nfs_exports_op; diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h index ea80096..52e8cb0 100644 --- a/include/linux/sunrpc/svc.h +++ b/include/linux/sunrpc/svc.h @@ -94,8 +94,6 @@ struct svc_serv { struct module * sv_module; /* optional module to count when * adding threads */ svc_thread_fn sv_function; /* main function for threads */ - unsigned int sv_drc_max_pages; /* Total pages for DRC */ - unsigned int sv_drc_pages_used;/* DRC pages used */ #if defined(CONFIG_NFS_V4_1) struct list_head sv_cb_list; /* queue for callback requests * that arrive over the same -- cgit v0.10.2 From d782c3f95c9263dc0b98e7115f75f1e18b9600b3 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Mon, 22 Jun 2009 13:17:08 +0800 Subject: drm/mode: add the CVT algorithm in kernel space Add the CVT algorithm in kernel space. And this function can be called to generate the required modeline. I copied it from the file of xserver/hw/xfree86/modes/xf86cvt.c. What I have done is to translate it by using integer calculation. This is to avoid the float-point calculation in kernel space. [airlied:- cleaned up some bits] Signed-off-by: Zhao Yakui Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 54f492a..0dbc7e4 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -8,6 +8,7 @@ * Copyright © 2007 Dave Airlie * Copyright © 2007-2008 Intel Corporation * Jesse Barnes + * Copyright 2005-2006 Luc Verhaegen * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -62,6 +63,224 @@ void drm_mode_debug_printmodeline(struct drm_display_mode *mode) EXPORT_SYMBOL(drm_mode_debug_printmodeline); /** + * drm_cvt_mode -create a modeline based on CVT algorithm + * @dev: DRM device + * @hdisplay: hdisplay size + * @vdisplay: vdisplay size + * @vrefresh : vrefresh rate + * @reduced : Whether the GTF calculation is simplified + * @interlaced:Whether the interlace is supported + * + * LOCKING: + * none. + * + * return the modeline based on CVT algorithm + * + * This function is called to generate the modeline based on CVT algorithm + * according to the hdisplay, vdisplay, vrefresh. + * It is based from the VESA(TM) Coordinated Video Timing Generator by + * Graham Loveridge April 9, 2003 available at + * http://www.vesa.org/public/CVT/CVTd6r1.xls + * + * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. + * What I have done is to translate it by using integer calculation. + */ +#define HV_FACTOR 1000 +struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, + int vdisplay, int vrefresh, + bool reduced, bool interlaced) +{ + /* 1) top/bottom margin size (% of height) - default: 1.8, */ +#define CVT_MARGIN_PERCENTAGE 18 + /* 2) character cell horizontal granularity (pixels) - default 8 */ +#define CVT_H_GRANULARITY 8 + /* 3) Minimum vertical porch (lines) - default 3 */ +#define CVT_MIN_V_PORCH 3 + /* 4) Minimum number of vertical back porch lines - default 6 */ +#define CVT_MIN_V_BPORCH 6 + /* Pixel Clock step (kHz) */ +#define CVT_CLOCK_STEP 250 + struct drm_display_mode *drm_mode; + bool margins = false; + unsigned int vfieldrate, hperiod; + int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; + int interlace; + + /* allocate the drm_display_mode structure. If failure, we will + * return directly + */ + drm_mode = drm_mode_create(dev); + if (!drm_mode) + return NULL; + + /* the CVT default refresh rate is 60Hz */ + if (!vrefresh) + vrefresh = 60; + + /* the required field fresh rate */ + if (interlaced) + vfieldrate = vrefresh * 2; + else + vfieldrate = vrefresh; + + /* horizontal pixels */ + hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); + + /* determine the left&right borders */ + hmargin = 0; + if (margins) { + hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; + hmargin -= hmargin % CVT_H_GRANULARITY; + } + /* find the total active pixels */ + drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; + + /* find the number of lines per field */ + if (interlaced) + vdisplay_rnd = vdisplay / 2; + else + vdisplay_rnd = vdisplay; + + /* find the top & bottom borders */ + vmargin = 0; + if (margins) + vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; + + drm_mode->vdisplay = vdisplay_rnd + 2 * vmargin; + + /* Interlaced */ + if (interlaced) + interlace = 1; + else + interlace = 0; + + /* Determine VSync Width from aspect ratio */ + if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) + vsync = 4; + else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) + vsync = 5; + else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) + vsync = 6; + else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) + vsync = 7; + else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) + vsync = 7; + else /* custom */ + vsync = 10; + + if (!reduced) { + /* simplify the GTF calculation */ + /* 4) Minimum time of vertical sync + back porch interval (µs) + * default 550.0 + */ + int tmp1, tmp2; +#define CVT_MIN_VSYNC_BP 550 + /* 3) Nominal HSync width (% of line period) - default 8 */ +#define CVT_HSYNC_PERCENTAGE 8 + unsigned int hblank_percentage; + int vsyncandback_porch, vback_porch, hblank; + + /* estimated the horizontal period */ + tmp1 = HV_FACTOR * 1000000 - + CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; + tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + + interlace; + hperiod = tmp1 * 2 / (tmp2 * vfieldrate); + + tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; + /* 9. Find number of lines in sync + backporch */ + if (tmp1 < (vsync + CVT_MIN_V_PORCH)) + vsyncandback_porch = vsync + CVT_MIN_V_PORCH; + else + vsyncandback_porch = tmp1; + /* 10. Find number of lines in back porch */ + vback_porch = vsyncandback_porch - vsync; + drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + + vsyncandback_porch + CVT_MIN_V_PORCH; + /* 5) Definition of Horizontal blanking time limitation */ + /* Gradient (%/kHz) - default 600 */ +#define CVT_M_FACTOR 600 + /* Offset (%) - default 40 */ +#define CVT_C_FACTOR 40 + /* Blanking time scaling factor - default 128 */ +#define CVT_K_FACTOR 128 + /* Scaling factor weighting - default 20 */ +#define CVT_J_FACTOR 20 +#define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) +#define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ + CVT_J_FACTOR) + /* 12. Find ideal blanking duty cycle from formula */ + hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * + hperiod / 1000; + /* 13. Blanking time */ + if (hblank_percentage < 20 * HV_FACTOR) + hblank_percentage = 20 * HV_FACTOR; + hblank = drm_mode->hdisplay * hblank_percentage / + (100 * HV_FACTOR - hblank_percentage); + hblank -= hblank % (2 * CVT_H_GRANULARITY); + /* 14. find the total pixes per line */ + drm_mode->htotal = drm_mode->hdisplay + hblank; + drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; + drm_mode->hsync_start = drm_mode->hsync_end - + (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; + drm_mode->hsync_start += CVT_H_GRANULARITY - + drm_mode->hsync_start % CVT_H_GRANULARITY; + /* fill the Vsync values */ + drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; + drm_mode->vsync_end = drm_mode->vsync_start + vsync; + } else { + /* Reduced blanking */ + /* Minimum vertical blanking interval time (µs)- default 460 */ +#define CVT_RB_MIN_VBLANK 460 + /* Fixed number of clocks for horizontal sync */ +#define CVT_RB_H_SYNC 32 + /* Fixed number of clocks for horizontal blanking */ +#define CVT_RB_H_BLANK 160 + /* Fixed number of lines for vertical front porch - default 3*/ +#define CVT_RB_VFPORCH 3 + int vbilines; + int tmp1, tmp2; + /* 8. Estimate Horizontal period. */ + tmp1 = HV_FACTOR * 1000000 - + CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; + tmp2 = vdisplay_rnd + 2 * vmargin; + hperiod = tmp1 / (tmp2 * vfieldrate); + /* 9. Find number of lines in vertical blanking */ + vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; + /* 10. Check if vertical blanking is sufficient */ + if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) + vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; + /* 11. Find total number of lines in vertical field */ + drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; + /* 12. Find total number of pixels in a line */ + drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; + /* Fill in HSync values */ + drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; + drm_mode->hsync_start = drm_mode->hsync_end = CVT_RB_H_SYNC; + } + /* 15/13. Find pixel clock frequency (kHz for xf86) */ + drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; + drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; + /* 18/16. Find actual vertical frame frequency */ + /* ignore - just set the mode flag for interlaced */ + if (interlaced) + drm_mode->vtotal *= 2; + /* Fill the mode line name */ + drm_mode_set_name(drm_mode); + if (reduced) + drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | + DRM_MODE_FLAG_NVSYNC); + else + drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | + DRM_MODE_FLAG_NHSYNC); + if (interlaced) + drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; + + return drm_mode; +} +EXPORT_SYMBOL(drm_cvt_mode); + +/** * drm_mode_set_name - set the name on a mode * @mode: name will be set in this mode * diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 7300fb8..820bc09 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -736,4 +736,7 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device *dev, extern int drm_mode_gamma_set_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); extern bool drm_detect_hdmi_monitor(struct edid *edid); +extern struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, + int hdisplay, int vdisplay, int vrefresh, + bool reduced, bool interlaced); #endif /* __DRM_CRTC_H__ */ -- cgit v0.10.2 From 26bbdadad356ec02d33657858d91675f3e9aca94 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Mon, 22 Jun 2009 13:17:09 +0800 Subject: drm/mode: add the GTF algorithm in kernel space Add the GTF algorithm in kernel space. And this function can be called to generate the required modeline. I copied it from the file of xserver/hw/xfree86/modes/xf86gtf.c. What I have done is to translate it by using integer calculation. This is to avoid the float-point calculation in kernel space. At the same tie I also refer to the function of fb_get_mode in drivers/video/fbmon.c Signed-off-by: Zhao Yakui Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 0dbc7e4..fd489d7 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -9,6 +9,7 @@ * Copyright © 2007-2008 Intel Corporation * Jesse Barnes * Copyright 2005-2006 Luc Verhaegen + * Copyright (c) 2001, Andy Ritger aritger@nvidia.com * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -281,6 +282,202 @@ struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, EXPORT_SYMBOL(drm_cvt_mode); /** + * drm_gtf_mode - create the modeline based on GTF algorithm + * + * @dev :drm device + * @hdisplay :hdisplay size + * @vdisplay :vdisplay size + * @vrefresh :vrefresh rate. + * @interlaced :whether the interlace is supported + * @margins :whether the margin is supported + * + * LOCKING. + * none. + * + * return the modeline based on GTF algorithm + * + * This function is to create the modeline based on the GTF algorithm. + * Generalized Timing Formula is derived from: + * GTF Spreadsheet by Andy Morrish (1/5/97) + * available at http://www.vesa.org + * + * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. + * What I have done is to translate it by using integer calculation. + * I also refer to the function of fb_get_mode in the file of + * drivers/video/fbmon.c + */ +struct drm_display_mode *drm_gtf_mode(struct drm_device *dev, int hdisplay, + int vdisplay, int vrefresh, + bool interlaced, int margins) +{ + /* 1) top/bottom margin size (% of height) - default: 1.8, */ +#define GTF_MARGIN_PERCENTAGE 18 + /* 2) character cell horizontal granularity (pixels) - default 8 */ +#define GTF_CELL_GRAN 8 + /* 3) Minimum vertical porch (lines) - default 3 */ +#define GTF_MIN_V_PORCH 1 + /* width of vsync in lines */ +#define V_SYNC_RQD 3 + /* width of hsync as % of total line */ +#define H_SYNC_PERCENT 8 + /* min time of vsync + back porch (microsec) */ +#define MIN_VSYNC_PLUS_BP 550 + /* blanking formula gradient */ +#define GTF_M 600 + /* blanking formula offset */ +#define GTF_C 40 + /* blanking formula scaling factor */ +#define GTF_K 128 + /* blanking formula scaling factor */ +#define GTF_J 20 + /* C' and M' are part of the Blanking Duty Cycle computation */ +#define GTF_C_PRIME (((GTF_C - GTF_J) * GTF_K / 256) + GTF_J) +#define GTF_M_PRIME (GTF_K * GTF_M / 256) + struct drm_display_mode *drm_mode; + unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; + int top_margin, bottom_margin; + int interlace; + unsigned int hfreq_est; + int vsync_plus_bp, vback_porch; + unsigned int vtotal_lines, vfieldrate_est, hperiod; + unsigned int vfield_rate, vframe_rate; + int left_margin, right_margin; + unsigned int total_active_pixels, ideal_duty_cycle; + unsigned int hblank, total_pixels, pixel_freq; + int hsync, hfront_porch, vodd_front_porch_lines; + unsigned int tmp1, tmp2; + + drm_mode = drm_mode_create(dev); + if (!drm_mode) + return NULL; + + /* 1. In order to give correct results, the number of horizontal + * pixels requested is first processed to ensure that it is divisible + * by the character size, by rounding it to the nearest character + * cell boundary: + */ + hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; + hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; + + /* 2. If interlace is requested, the number of vertical lines assumed + * by the calculation must be halved, as the computation calculates + * the number of vertical lines per field. + */ + if (interlaced) + vdisplay_rnd = vdisplay / 2; + else + vdisplay_rnd = vdisplay; + + /* 3. Find the frame rate required: */ + if (interlaced) + vfieldrate_rqd = vrefresh * 2; + else + vfieldrate_rqd = vrefresh; + + /* 4. Find number of lines in Top margin: */ + top_margin = 0; + if (margins) + top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / + 1000; + /* 5. Find number of lines in bottom margin: */ + bottom_margin = top_margin; + + /* 6. If interlace is required, then set variable interlace: */ + if (interlaced) + interlace = 1; + else + interlace = 0; + + /* 7. Estimate the Horizontal frequency */ + { + tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; + tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * + 2 + interlace; + hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; + } + + /* 8. Find the number of lines in V sync + back porch */ + /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ + vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; + vsync_plus_bp = (vsync_plus_bp + 500) / 1000; + /* 9. Find the number of lines in V back porch alone: */ + vback_porch = vsync_plus_bp - V_SYNC_RQD; + /* 10. Find the total number of lines in Vertical field period: */ + vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + + vsync_plus_bp + GTF_MIN_V_PORCH; + /* 11. Estimate the Vertical field frequency: */ + vfieldrate_est = hfreq_est / vtotal_lines; + /* 12. Find the actual horizontal period: */ + hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); + + /* 13. Find the actual Vertical field frequency: */ + vfield_rate = hfreq_est / vtotal_lines; + /* 14. Find the Vertical frame frequency: */ + if (interlaced) + vframe_rate = vfield_rate / 2; + else + vframe_rate = vfield_rate; + /* 15. Find number of pixels in left margin: */ + if (margins) + left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / + 1000; + else + left_margin = 0; + + /* 16.Find number of pixels in right margin: */ + right_margin = left_margin; + /* 17.Find total number of active pixels in image and left and right */ + total_active_pixels = hdisplay_rnd + left_margin + right_margin; + /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ + ideal_duty_cycle = GTF_C_PRIME * 1000 - + (GTF_M_PRIME * 1000000 / hfreq_est); + /* 19.Find the number of pixels in the blanking time to the nearest + * double character cell: */ + hblank = total_active_pixels * ideal_duty_cycle / + (100000 - ideal_duty_cycle); + hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); + hblank = hblank * 2 * GTF_CELL_GRAN; + /* 20.Find total number of pixels: */ + total_pixels = total_active_pixels + hblank; + /* 21.Find pixel clock frequency: */ + pixel_freq = total_pixels * hfreq_est / 1000; + /* Stage 1 computations are now complete; I should really pass + * the results to another function and do the Stage 2 computations, + * but I only need a few more values so I'll just append the + * computations here for now */ + /* 17. Find the number of pixels in the horizontal sync period: */ + hsync = H_SYNC_PERCENT * total_pixels / 100; + hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; + hsync = hsync * GTF_CELL_GRAN; + /* 18. Find the number of pixels in horizontal front porch period */ + hfront_porch = hblank / 2 - hsync; + /* 36. Find the number of lines in the odd front porch period: */ + vodd_front_porch_lines = GTF_MIN_V_PORCH ; + + /* finally, pack the results in the mode struct */ + drm_mode->hdisplay = hdisplay_rnd; + drm_mode->hsync_start = hdisplay_rnd + hfront_porch; + drm_mode->hsync_end = drm_mode->hsync_start + hsync; + drm_mode->htotal = total_pixels; + drm_mode->vdisplay = vdisplay_rnd; + drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; + drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; + drm_mode->vtotal = vtotal_lines; + + drm_mode->clock = pixel_freq; + + drm_mode_set_name(drm_mode); + drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; + + if (interlaced) { + drm_mode->vtotal *= 2; + drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; + } + + return drm_mode; +} +EXPORT_SYMBOL(drm_gtf_mode); +/** * drm_mode_set_name - set the name on a mode * @mode: name will be set in this mode * diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 820bc09..125994d 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -739,4 +739,7 @@ extern bool drm_detect_hdmi_monitor(struct edid *edid); extern struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, int vdisplay, int vrefresh, bool reduced, bool interlaced); +extern struct drm_display_mode *drm_gtf_mode(struct drm_device *dev, + int hdisplay, int vdisplay, int vrefresh, + bool interlaced, int margins); #endif /* __DRM_CRTC_H__ */ -- cgit v0.10.2 From 5c61259e6c7290082108e93815f7f72f27da14f4 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Mon, 22 Jun 2009 13:17:10 +0800 Subject: drm/mode: get the modeline for standard timing in EDID by using CVT/GTF Create the standard timing modeline by using CVT/GFT algorithm while interpreting the EDID. In course of interpreting the EDID, the timing level will be obtained, which is used to determine whether the CVT/GTF algorithm is selected to generate the modeline for the given hdisplay/vdisplay/vrefresh_rate. In the UMS mode firstly it will check whether it can be found in the DMT table. If it can be found, then the modeline is returned. Then the timing_level is used to choose CVT/GTF. As there is no DMT table, no modeline is returned when timing level is DMT. For the other two timing levels, the CVT/GTF will be called to generate the required standard timing modeline. [airlied: fixed up conflicts since EDID rework] Signed-off-by: Zhao Yakui Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 80cc6d0..bbcb2e2 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -61,6 +61,10 @@ /* use +hsync +vsync for detailed mode */ #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) +#define LEVEL_DMT 0 +#define LEVEL_GTF 1 +#define LEVEL_CVT 2 + static struct edid_quirk { char *vendor; int product_id; @@ -240,25 +244,31 @@ static void edid_fixup_preferred(struct drm_connector *connector, /** * drm_mode_std - convert standard mode info (width, height, refresh) into mode * @t: standard timing params + * @timing_level: standard timing level * * Take the standard timing params (in this case width, aspect, and refresh) - * and convert them into a real mode using CVT. + * and convert them into a real mode using CVT/GTF/DMT. * * Punts for now, but should eventually use the FB layer's CVT based mode * generation code. */ struct drm_display_mode *drm_mode_std(struct drm_device *dev, - struct std_timing *t) + struct std_timing *t, + int timing_level) { struct drm_display_mode *mode; - int hsize = t->hsize * 8 + 248, vsize; + int hsize, vsize; + int vrefresh_rate; unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) >> EDID_TIMING_ASPECT_SHIFT; - - mode = drm_mode_create(dev); - if (!mode) - return NULL; - + unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) + >> EDID_TIMING_VFREQ_SHIFT; + + /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ + hsize = t->hsize * 8 + 248; + /* vrefresh_rate = vfreq + 60 */ + vrefresh_rate = vfreq + 60; + /* the vdisplay is calculated based on the aspect ratio */ if (aspect_ratio == 0) vsize = (hsize * 10) / 16; else if (aspect_ratio == 1) @@ -268,8 +278,23 @@ struct drm_display_mode *drm_mode_std(struct drm_device *dev, else vsize = (hsize * 9) / 16; - drm_mode_set_name(mode); - + mode = NULL; + switch (timing_level) { + case LEVEL_DMT: + mode = drm_mode_create(dev); + if (mode) { + mode->hdisplay = hsize; + mode->vdisplay = vsize; + drm_mode_set_name(mode); + } + break; + case LEVEL_GTF: + mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); + break; + case LEVEL_CVT: + mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); + break; + } return mode; } @@ -451,6 +476,19 @@ static int add_established_modes(struct drm_connector *connector, struct edid *e return modes; } +/** + * stanard_timing_level - get std. timing level(CVT/GTF/DMT) + * @edid: EDID block to scan + */ +static int standard_timing_level(struct edid *edid) +{ + if (edid->revision >= 2) { + if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) + return LEVEL_CVT; + return LEVEL_GTF; + } + return LEVEL_DMT; +} /** * add_standard_modes - get std. modes from EDID and add them @@ -463,6 +501,9 @@ static int add_standard_modes(struct drm_connector *connector, struct edid *edid { struct drm_device *dev = connector->dev; int i, modes = 0; + int timing_level; + + timing_level = standard_timing_level(edid); for (i = 0; i < EDID_STD_TIMINGS; i++) { struct std_timing *t = &edid->standard_timings[i]; @@ -472,7 +513,8 @@ static int add_standard_modes(struct drm_connector *connector, struct edid *edid if (t->hsize == 1 && t->vfreq_aspect == 1) continue; - newmode = drm_mode_std(dev, &edid->standard_timings[i]); + newmode = drm_mode_std(dev, &edid->standard_timings[i], + timing_level); if (newmode) { drm_mode_probed_add(connector, newmode); modes++; @@ -496,6 +538,9 @@ static int add_detailed_info(struct drm_connector *connector, { struct drm_device *dev = connector->dev; int i, j, modes = 0; + int timing_level; + + timing_level = standard_timing_level(edid); for (i = 0; i < EDID_DETAILED_TIMINGS; i++) { struct detailed_timing *timing = &edid->detailed_timings[i]; @@ -541,7 +586,8 @@ static int add_detailed_info(struct drm_connector *connector, struct drm_display_mode *newmode; std = &data->data.timings[j]; - newmode = drm_mode_std(dev, std); + newmode = drm_mode_std(dev, std, + timing_level); if (newmode) { drm_mode_probed_add(connector, newmode); modes++; -- cgit v0.10.2 From 3d39cecc4841e8d4c4abdb401d10180f5faaded0 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Wed, 8 Jul 2009 15:23:30 +0100 Subject: intel-iommu: Remove superfluous iova_alloc_lock from IOVA code We only ever obtain this lock immediately before the iova_rbtree_lock, and release it immediately after the iova_rbtree_lock. So ditch it and just use iova_rbtree_lock. [v2: Remove the lockdep bits this time too] Signed-off-by: David Woodhouse diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index c5f7c73..d6a8573 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -1309,7 +1309,6 @@ static void iommu_detach_domain(struct dmar_domain *domain, } static struct iova_domain reserved_iova_list; -static struct lock_class_key reserved_alloc_key; static struct lock_class_key reserved_rbtree_key; static void dmar_init_reserved_ranges(void) @@ -1320,8 +1319,6 @@ static void dmar_init_reserved_ranges(void) init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN); - lockdep_set_class(&reserved_iova_list.iova_alloc_lock, - &reserved_alloc_key); lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, &reserved_rbtree_key); diff --git a/drivers/pci/iova.c b/drivers/pci/iova.c index 46dd440..7914951 100644 --- a/drivers/pci/iova.c +++ b/drivers/pci/iova.c @@ -22,7 +22,6 @@ void init_iova_domain(struct iova_domain *iovad, unsigned long pfn_32bit) { - spin_lock_init(&iovad->iova_alloc_lock); spin_lock_init(&iovad->iova_rbtree_lock); iovad->rbroot = RB_ROOT; iovad->cached32_node = NULL; @@ -205,7 +204,6 @@ alloc_iova(struct iova_domain *iovad, unsigned long size, unsigned long limit_pfn, bool size_aligned) { - unsigned long flags; struct iova *new_iova; int ret; @@ -219,11 +217,9 @@ alloc_iova(struct iova_domain *iovad, unsigned long size, if (size_aligned) size = __roundup_pow_of_two(size); - spin_lock_irqsave(&iovad->iova_alloc_lock, flags); ret = __alloc_and_insert_iova_range(iovad, size, limit_pfn, new_iova, size_aligned); - spin_unlock_irqrestore(&iovad->iova_alloc_lock, flags); if (ret) { free_iova_mem(new_iova); return NULL; @@ -381,8 +377,7 @@ reserve_iova(struct iova_domain *iovad, struct iova *iova; unsigned int overlap = 0; - spin_lock_irqsave(&iovad->iova_alloc_lock, flags); - spin_lock(&iovad->iova_rbtree_lock); + spin_lock_irqsave(&iovad->iova_rbtree_lock, flags); for (node = rb_first(&iovad->rbroot); node; node = rb_next(node)) { if (__is_range_overlap(node, pfn_lo, pfn_hi)) { iova = container_of(node, struct iova, node); @@ -402,8 +397,7 @@ reserve_iova(struct iova_domain *iovad, iova = __insert_new_range(iovad, pfn_lo, pfn_hi); finish: - spin_unlock(&iovad->iova_rbtree_lock); - spin_unlock_irqrestore(&iovad->iova_alloc_lock, flags); + spin_unlock_irqrestore(&iovad->iova_rbtree_lock, flags); return iova; } @@ -420,8 +414,7 @@ copy_reserved_iova(struct iova_domain *from, struct iova_domain *to) unsigned long flags; struct rb_node *node; - spin_lock_irqsave(&from->iova_alloc_lock, flags); - spin_lock(&from->iova_rbtree_lock); + spin_lock_irqsave(&from->iova_rbtree_lock, flags); for (node = rb_first(&from->rbroot); node; node = rb_next(node)) { struct iova *iova = container_of(node, struct iova, node); struct iova *new_iova; @@ -430,6 +423,5 @@ copy_reserved_iova(struct iova_domain *from, struct iova_domain *to) printk(KERN_ERR "Reserve iova range %lx@%lx failed\n", iova->pfn_lo, iova->pfn_lo); } - spin_unlock(&from->iova_rbtree_lock); - spin_unlock_irqrestore(&from->iova_alloc_lock, flags); + spin_unlock_irqrestore(&from->iova_rbtree_lock, flags); } diff --git a/include/linux/iova.h b/include/linux/iova.h index 228f6c9..76a0759 100644 --- a/include/linux/iova.h +++ b/include/linux/iova.h @@ -28,7 +28,6 @@ struct iova { /* holds all the iova translations for a domain */ struct iova_domain { - spinlock_t iova_alloc_lock;/* Lock to protect iova allocation */ spinlock_t iova_rbtree_lock; /* Lock to protect update of rbtree */ struct rb_root rbroot; /* iova domain rbtree root */ struct rb_node *cached32_node; /* Save last alloced node */ -- cgit v0.10.2 From acea0018a24b794e32afea4f3be4230c58f2f8e3 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Tue, 14 Jul 2009 01:55:11 +0100 Subject: intel-iommu: Defer the iotlb flush and iova free for intel_unmap_sg() too. I see no reason why we did this _only_ in intel_unmap_page(). Signed-off-by: David Woodhouse diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index d6a8573..ee48fd0 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -2815,11 +2815,18 @@ static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist, /* free page tables */ dma_pte_free_pagetable(domain, start_pfn, last_pfn); - iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, - (last_pfn - start_pfn + 1)); - - /* free iova */ - __free_iova(&domain->iovad, iova); + if (intel_iommu_strict) { + iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, + last_pfn - start_pfn + 1); + /* free iova */ + __free_iova(&domain->iovad, iova); + } else { + add_unmap(domain, iova); + /* + * queue up the release of the unmap to save the 1/6th of the + * cpu used up by the iotlb flush operation... + */ + } } static int intel_nontranslate_map_sg(struct device *hddev, -- cgit v0.10.2 From 0db9b7aebb6a1c2bba2d0636ae0b1f9ef729c827 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Tue, 14 Jul 2009 02:01:57 +0100 Subject: intel-iommu: Kill pointless intel_unmap_single() function Signed-off-by: David Woodhouse diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index ee48fd0..86a8394 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -2741,12 +2741,6 @@ static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, } } -static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size, - int dir) -{ - intel_unmap_page(dev, dev_addr, size, dir, NULL); -} - static void *intel_alloc_coherent(struct device *hwdev, size_t size, dma_addr_t *dma_handle, gfp_t flags) { @@ -2779,7 +2773,7 @@ static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr, size = PAGE_ALIGN(size); order = get_order(size); - intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL); + intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL); free_pages((unsigned long)vaddr, order); } -- cgit v0.10.2 From 86f4d0123b1fddb47d35b9a893f8c0b94bf89abe Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sun, 19 Jul 2009 14:47:45 +0300 Subject: intel-iommu: double kfree() g_iommus is freed after we "goto error;". Found by smatch (http://repo.or.cz/w/smatch.git). Signed-off-by: Dan Carpenter Signed-off-by: David Woodhouse diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index 86a8394..097d5da 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -2224,7 +2224,6 @@ int __init init_dmars(void) deferred_flush = kzalloc(g_num_of_iommus * sizeof(struct deferred_flush_tables), GFP_KERNEL); if (!deferred_flush) { - kfree(g_iommus); ret = -ENOMEM; goto error; } -- cgit v0.10.2 From 83ef2ecdbbd49cb0fbbfc7012b111b71664e386d Mon Sep 17 00:00:00 2001 From: Subrata Modak Date: Wed, 15 Jul 2009 07:49:03 +0530 Subject: UBIFS: suppress compilation warning Fix "using uninitialized variable" compilation warning by using the "unititialized_var()" helper. Signed-off-by: Subrata Modak Signed-off-by: Artem Bityutskiy diff --git a/fs/ubifs/commit.c b/fs/ubifs/commit.c index f3a7945..4775af4 100644 --- a/fs/ubifs/commit.c +++ b/fs/ubifs/commit.c @@ -510,7 +510,7 @@ int dbg_check_old_index(struct ubifs_info *c, struct ubifs_zbranch *zroot) int lnum, offs, len, err = 0, uninitialized_var(last_level), child_cnt; int first = 1, iip; struct ubifs_debug_info *d = c->dbg; - union ubifs_key lower_key, upper_key, l_key, u_key; + union ubifs_key uninitialized_var(lower_key), upper_key, l_key, u_key; unsigned long long uninitialized_var(last_sqnum); struct ubifs_idx_node *idx; struct list_head list; -- cgit v0.10.2 From b5148da40cb77ca84c4b0281e7049bb26d786592 Mon Sep 17 00:00:00 2001 From: Subrata Modak Date: Fri, 17 Jul 2009 18:28:12 +0300 Subject: UBIFS: remove unused functions Remove 'xent_key_init_hash()' and 'data_key_init_flash()' functions, as they are unot used anywhere. Signed-off-by: Subrata Modak Signed-off-by: Artem Bityutskiy diff --git a/fs/ubifs/key.h b/fs/ubifs/key.h index 5fa27ea..919af84 100644 --- a/fs/ubifs/key.h +++ b/fs/ubifs/key.h @@ -229,23 +229,6 @@ static inline void xent_key_init(const struct ubifs_info *c, } /** - * xent_key_init_hash - initialize extended attribute entry key without - * re-calculating hash function. - * @c: UBIFS file-system description object - * @key: key to initialize - * @inum: host inode number - * @hash: extended attribute entry name hash - */ -static inline void xent_key_init_hash(const struct ubifs_info *c, - union ubifs_key *key, ino_t inum, - uint32_t hash) -{ - ubifs_assert(!(hash & ~UBIFS_S_KEY_HASH_MASK)); - key->u32[0] = inum; - key->u32[1] = hash | (UBIFS_XENT_KEY << UBIFS_S_KEY_HASH_BITS); -} - -/** * xent_key_init_flash - initialize on-flash extended attribute entry key. * @c: UBIFS file-system description object * @k: key to initialize @@ -295,25 +278,6 @@ static inline void data_key_init(const struct ubifs_info *c, } /** - * data_key_init_flash - initialize on-flash data key. - * @c: UBIFS file-system description object - * @k: key to initialize - * @inum: inode number - * @block: block number - */ -static inline void data_key_init_flash(const struct ubifs_info *c, void *k, - ino_t inum, unsigned int block) -{ - union ubifs_key *key = k; - - ubifs_assert(!(block & ~UBIFS_S_KEY_BLOCK_MASK)); - key->j32[0] = cpu_to_le32(inum); - key->j32[1] = cpu_to_le32(block | - (UBIFS_DATA_KEY << UBIFS_S_KEY_BLOCK_BITS)); - memset(k + 8, 0, UBIFS_MAX_KEY_LEN - 8); -} - -/** * trun_key_init - initialize truncation node key. * @c: UBIFS file-system description object * @key: key to initialize -- cgit v0.10.2 From e9d6bbc428bdf0c08bbd0b3f28db2b7317cfff21 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Sun, 19 Jul 2009 13:51:04 +0300 Subject: UBIFS: kill BKL The BKL was pushed down from VFS to the file-systems. It used to serialize mount/unmount/remount and prevented more than one instance of the same file-system from doing mount/umount/remount at the same time. But it is OK for UBIFS and it does not need any additional locking for these cases. Thus, kick the BKL out of UBIFS. Signed-off-by: Artem Bityutskiy diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 26d2e0d..13e7ed4 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -36,7 +36,6 @@ #include #include #include -#include #include "ubifs.h" /* @@ -1726,8 +1725,6 @@ static void ubifs_put_super(struct super_block *sb) ubifs_msg("un-mount UBI device %d, volume %d", c->vi.ubi_num, c->vi.vol_id); - lock_kernel(); - /* * The following asserts are only valid if there has not been a failure * of the media. For example, there will be dirty inodes if we failed @@ -1792,8 +1789,6 @@ static void ubifs_put_super(struct super_block *sb) ubi_close_volume(c->ubi); mutex_unlock(&c->umount_mutex); kfree(c); - - unlock_kernel(); } static int ubifs_remount_fs(struct super_block *sb, int *flags, char *data) @@ -1809,22 +1804,17 @@ static int ubifs_remount_fs(struct super_block *sb, int *flags, char *data) return err; } - lock_kernel(); if ((sb->s_flags & MS_RDONLY) && !(*flags & MS_RDONLY)) { if (c->ro_media) { ubifs_msg("cannot re-mount due to prior errors"); - unlock_kernel(); return -EROFS; } err = ubifs_remount_rw(c); - if (err) { - unlock_kernel(); + if (err) return err; - } } else if (!(sb->s_flags & MS_RDONLY) && (*flags & MS_RDONLY)) { if (c->ro_media) { ubifs_msg("cannot re-mount due to prior errors"); - unlock_kernel(); return -EROFS; } ubifs_remount_ro(c); @@ -1839,7 +1829,6 @@ static int ubifs_remount_fs(struct super_block *sb, int *flags, char *data) } ubifs_assert(c->lst.taken_empty_lebs > 0); - unlock_kernel(); return 0; } -- cgit v0.10.2 From 887ee17117fd23e962332b353d250ac9e090b20f Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Mon, 20 Jul 2009 17:56:19 +0300 Subject: UBIFS: remove unneeded call from ubifs_sync_fs Nowadays VFS always synchronizes all dirty inodes and pages before calling '->sync_fs()', so remove unneeded 'generic_sync_sb_inodes()' from 'ubifs_sync_fs()'. It used to be needed, but not any longer. Pointed-out-by: Christoph Hellwig Signed-off-by: Artem Bityutskiy diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 13e7ed4..b541bd7 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -437,12 +437,6 @@ static int ubifs_sync_fs(struct super_block *sb, int wait) { int i, err; struct ubifs_info *c = sb->s_fs_info; - struct writeback_control wbc = { - .sync_mode = WB_SYNC_ALL, - .range_start = 0, - .range_end = LLONG_MAX, - .nr_to_write = LONG_MAX, - }; /* * Zero @wait is just an advisory thing to help the file system shove @@ -453,17 +447,6 @@ static int ubifs_sync_fs(struct super_block *sb, int wait) return 0; /* - * VFS calls '->sync_fs()' before synchronizing all dirty inodes and - * pages, so synchronize them first, then commit the journal. Strictly - * speaking, it is not necessary to commit the journal here, - * synchronizing write-buffers would be enough. But committing makes - * UBIFS free space predictions much more accurate, so we want to let - * the user be able to get more accurate results of 'statfs()' after - * they synchronize the file system. - */ - generic_sync_sb_inodes(sb, &wbc); - - /* * Synchronize write buffers, because 'ubifs_run_commit()' does not * do this if it waits for an already running commit. */ @@ -473,6 +456,13 @@ static int ubifs_sync_fs(struct super_block *sb, int wait) return err; } + /* + * Strictly speaking, it is not necessary to commit the journal here, + * synchronizing write-buffers would be enough. But committing makes + * UBIFS free space predictions much more accurate, so we want to let + * the user be able to get more accurate results of 'statfs()' after + * they synchronize the file system. + */ err = ubifs_run_commit(c); if (err) return err; -- cgit v0.10.2 From 2522a776c1b9b5c93383d07717f895cc1a56a87a Mon Sep 17 00:00:00 2001 From: Eric Sesterhenn Date: Tue, 28 Jul 2009 14:32:08 +0200 Subject: Fix memory leak in write_pool_threads kmemleak produces the following warning unreferenced object 0xc9ec02a0 (size 8): comm "cat", pid 19048, jiffies 730243 backtrace: [] create_object+0x100/0x240 [] kmemleak_alloc+0x2b/0x60 [] __kmalloc+0x14b/0x270 [] write_pool_threads+0x87/0x1d0 [] nfsctl_transaction_write+0x58/0x70 [] nfsctl_transaction_read+0x4f/0x60 [] vfs_read+0x94/0x150 [] sys_read+0x3d/0x70 [] sysenter_do_call+0x12/0x32 [] 0xffffffff write_pool_threads() only frees nthreads on error paths, in the success case we leak it. Signed-off-by: Eric Sesterhenn Reviewed-by: Catalin Marinas Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfsctl.c b/fs/nfsd/nfsctl.c index 1250fb9..48da164 100644 --- a/fs/nfsd/nfsctl.c +++ b/fs/nfsd/nfsctl.c @@ -785,6 +785,7 @@ static ssize_t write_pool_threads(struct file *file, char *buf, size_t size) mesg += len; } + kfree(nthreads); mutex_unlock(&nfsd_mutex); return (mesg-buf); -- cgit v0.10.2 From 413d63d7106b914a4a004ac08698f10c618e4616 Mon Sep 17 00:00:00 2001 From: "J. Bruce Fields" Date: Tue, 28 Jul 2009 11:37:25 -0400 Subject: nfsd: minor write_pool_threads exit cleanup Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfsctl.c b/fs/nfsd/nfsctl.c index 48da164..b51e7ae 100644 --- a/fs/nfsd/nfsctl.c +++ b/fs/nfsd/nfsctl.c @@ -784,11 +784,7 @@ static ssize_t write_pool_threads(struct file *file, char *buf, size_t size) size -= len; mesg += len; } - - kfree(nthreads); - mutex_unlock(&nfsd_mutex); - return (mesg-buf); - + rv = mesg - buf; out_free: kfree(nthreads); mutex_unlock(&nfsd_mutex); -- cgit v0.10.2 From be98d1bbd1b872a10d64cdef0af10b9afcc48092 Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Mon, 27 Jul 2009 18:49:05 -0400 Subject: nfsd41: reclaim DRC memory on session free This fixes a leak which would eventually lock out new clients. Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 2e6a44e..69bd37e 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -585,6 +585,9 @@ free_session(struct kref *kref) struct nfsd4_cache_entry *e = &ses->se_slots[i].sl_cache_entry; nfsd4_release_respages(e->ce_respages, e->ce_resused); } + spin_lock(&nfsd_drc_lock); + nfsd_drc_pages_used -= ses->se_fchannel.maxreqs * NFSD_PAGES_PER_SLOT; + spin_unlock(&nfsd_drc_lock); kfree(ses); } -- cgit v0.10.2 From b101ebbc39f50f8af4657e517954ca874b13b364 Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Mon, 27 Jul 2009 18:40:09 -0400 Subject: nfsd41: minor set_forechannel_maxreqs cleanup Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 69bd37e..70cba3f 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -423,26 +423,25 @@ gen_sessionid(struct nfsd4_session *ses) */ static int set_forechannel_maxreqs(struct nfsd4_channel_attrs *fchan) { - int status = 0, np = fchan->maxreqs * NFSD_PAGES_PER_SLOT; + int np; if (fchan->maxreqs < 1) return nfserr_inval; else if (fchan->maxreqs > NFSD_MAX_SLOTS_PER_SESSION) fchan->maxreqs = NFSD_MAX_SLOTS_PER_SESSION; + np = fchan->maxreqs * NFSD_PAGES_PER_SLOT; + spin_lock(&nfsd_drc_lock); if (np + nfsd_drc_pages_used > nfsd_drc_max_pages) np = nfsd_drc_max_pages - nfsd_drc_pages_used; nfsd_drc_pages_used += np; spin_unlock(&nfsd_drc_lock); - if (np <= 0) { - status = nfserr_resource; - fchan->maxreqs = 0; - } else - fchan->maxreqs = np / NFSD_PAGES_PER_SLOT; - - return status; + fchan->maxreqs = np / NFSD_PAGES_PER_SLOT; + if (fchan->maxreqs == 0) + return nfserr_resource; + return 0; } /* -- cgit v0.10.2 From 6a14dd1a4fe1bd00e02a96c97015cedfddda58ed Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Mon, 27 Jul 2009 19:06:45 -0400 Subject: nfsd41: reserve less memory for DRC Also remove a slightly misleading comment. Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfssvc.c b/fs/nfsd/nfssvc.c index 78d8fcd..9be2a19 100644 --- a/fs/nfsd/nfssvc.c +++ b/fs/nfsd/nfssvc.c @@ -246,8 +246,7 @@ void nfsd_reset_versions(void) */ static void set_max_drc(void) { - /* The percent of nr_free_buffer_pages used by the V4.1 server DRC */ - #define NFSD_DRC_SIZE_SHIFT 7 + #define NFSD_DRC_SIZE_SHIFT 10 nfsd_drc_max_pages = nr_free_buffer_pages() >> NFSD_DRC_SIZE_SHIFT; nfsd_drc_pages_used = 0; -- cgit v0.10.2 From 0c193054a4c1cf190d2f23e5e91bd14402e43912 Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Mon, 27 Jul 2009 19:09:19 -0400 Subject: nfsd41: hange from page to memory based drc limits NFSD_SLOT_CACHE_SIZE is the size of all encoded operation responses (excluding the sequence operation) that we want to cache. For now, keep NFSD_SLOT_CACHE_SIZE at PAGE_SIZE. It will be reduced when the DRC is changed from page based to memory based. Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 70cba3f..e2b11b1 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -414,31 +414,31 @@ gen_sessionid(struct nfsd4_session *ses) /* * Give the client the number of slots it requests bound by - * NFSD_MAX_SLOTS_PER_SESSION and by sv_drc_max_pages. + * NFSD_MAX_SLOTS_PER_SESSION and by nfsd_drc_max_mem. * - * If we run out of pages (sv_drc_pages_used == sv_drc_max_pages) we - * should (up to a point) re-negotiate active sessions and reduce their - * slot usage to make rooom for new connections. For now we just fail the - * create session. + * If we run out of reserved DRC memory we should (up to a point) re-negotiate + * active sessions and reduce their slot usage to make rooom for new + * connections. For now we just fail the create session. */ static int set_forechannel_maxreqs(struct nfsd4_channel_attrs *fchan) { - int np; + int mem; if (fchan->maxreqs < 1) return nfserr_inval; else if (fchan->maxreqs > NFSD_MAX_SLOTS_PER_SESSION) fchan->maxreqs = NFSD_MAX_SLOTS_PER_SESSION; - np = fchan->maxreqs * NFSD_PAGES_PER_SLOT; + mem = fchan->maxreqs * NFSD_SLOT_CACHE_SIZE; spin_lock(&nfsd_drc_lock); - if (np + nfsd_drc_pages_used > nfsd_drc_max_pages) - np = nfsd_drc_max_pages - nfsd_drc_pages_used; - nfsd_drc_pages_used += np; + if (mem + nfsd_drc_mem_used > nfsd_drc_max_mem) + mem = ((nfsd_drc_max_mem - nfsd_drc_mem_used) / + NFSD_SLOT_CACHE_SIZE) * NFSD_SLOT_CACHE_SIZE; + nfsd_drc_mem_used += mem; spin_unlock(&nfsd_drc_lock); - fchan->maxreqs = np / NFSD_PAGES_PER_SLOT; + fchan->maxreqs = mem / NFSD_SLOT_CACHE_SIZE; if (fchan->maxreqs == 0) return nfserr_resource; return 0; @@ -465,9 +465,7 @@ static int init_forechannel_attrs(struct svc_rqst *rqstp, fchan->maxresp_sz = maxcount; session_fchan->maxresp_sz = fchan->maxresp_sz; - /* Set the max response cached size our default which is - * a multiple of PAGE_SIZE and small */ - session_fchan->maxresp_cached = NFSD_PAGES_PER_SLOT * PAGE_SIZE; + session_fchan->maxresp_cached = NFSD_SLOT_CACHE_SIZE; fchan->maxresp_cached = session_fchan->maxresp_cached; /* Use the client's maxops if possible */ @@ -585,7 +583,7 @@ free_session(struct kref *kref) nfsd4_release_respages(e->ce_respages, e->ce_resused); } spin_lock(&nfsd_drc_lock); - nfsd_drc_pages_used -= ses->se_fchannel.maxreqs * NFSD_PAGES_PER_SLOT; + nfsd_drc_mem_used -= ses->se_fchannel.maxreqs * NFSD_SLOT_CACHE_SIZE; spin_unlock(&nfsd_drc_lock); kfree(ses); } diff --git a/fs/nfsd/nfssvc.c b/fs/nfsd/nfssvc.c index 9be2a19..5a280a9 100644 --- a/fs/nfsd/nfssvc.c +++ b/fs/nfsd/nfssvc.c @@ -74,8 +74,8 @@ struct svc_serv *nfsd_serv; * nfsd_drc_pages_used tracks the current version 4.1 DRC memory usage. */ spinlock_t nfsd_drc_lock; -unsigned int nfsd_drc_max_pages; -unsigned int nfsd_drc_pages_used; +unsigned int nfsd_drc_max_mem; +unsigned int nfsd_drc_mem_used; #if defined(CONFIG_NFSD_V2_ACL) || defined(CONFIG_NFSD_V3_ACL) static struct svc_stat nfsd_acl_svcstats; @@ -247,12 +247,11 @@ void nfsd_reset_versions(void) static void set_max_drc(void) { #define NFSD_DRC_SIZE_SHIFT 10 - nfsd_drc_max_pages = nr_free_buffer_pages() - >> NFSD_DRC_SIZE_SHIFT; - nfsd_drc_pages_used = 0; + nfsd_drc_max_mem = (nr_free_buffer_pages() + >> NFSD_DRC_SIZE_SHIFT) * PAGE_SIZE; + nfsd_drc_mem_used = 0; spin_lock_init(&nfsd_drc_lock); - dprintk("%s nfsd_drc_max_pages %u\n", __func__, - nfsd_drc_max_pages); + dprintk("%s nfsd_drc_max_mem %u \n", __func__, nfsd_drc_max_mem); } int nfsd_create_serv(void) diff --git a/include/linux/nfsd/nfsd.h b/include/linux/nfsd/nfsd.h index 2571f85..2812ed5 100644 --- a/include/linux/nfsd/nfsd.h +++ b/include/linux/nfsd/nfsd.h @@ -57,8 +57,8 @@ extern u32 nfsd_supported_minorversion; extern struct mutex nfsd_mutex; extern struct svc_serv *nfsd_serv; extern spinlock_t nfsd_drc_lock; -extern unsigned int nfsd_drc_max_pages; -extern unsigned int nfsd_drc_pages_used; +extern unsigned int nfsd_drc_max_mem; +extern unsigned int nfsd_drc_mem_used; extern struct seq_operations nfs_exports_op; diff --git a/include/linux/nfsd/state.h b/include/linux/nfsd/state.h index 57ab2ed..a6c87d6 100644 --- a/include/linux/nfsd/state.h +++ b/include/linux/nfsd/state.h @@ -96,6 +96,7 @@ struct nfs4_cb_conn { #define NFSD_MAX_SLOTS_PER_SESSION 128 /* Maximum number of pages per slot cache entry */ #define NFSD_PAGES_PER_SLOT 1 +#define NFSD_SLOT_CACHE_SIZE PAGE_SIZE /* Maximum number of operations per session compound */ #define NFSD_MAX_OPS_PER_COMPOUND 16 -- cgit v0.10.2 From 5261dcf8eb3d098545a676030910cf2c05a00e6c Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Thu, 23 Jul 2009 19:02:14 -0400 Subject: nfsd41: remove redundant forechannel max requests check This check is done in set_forechannel_maxreqs. Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index e2b11b1..0be417e 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -473,10 +473,6 @@ static int init_forechannel_attrs(struct svc_rqst *rqstp, fchan->maxops = NFSD_MAX_OPS_PER_COMPOUND; session_fchan->maxops = fchan->maxops; - /* try to use the client requested number of slots */ - if (fchan->maxreqs > NFSD_MAX_SLOTS_PER_SESSION) - fchan->maxreqs = NFSD_MAX_SLOTS_PER_SESSION; - /* FIXME: Error means no more DRC pages so the server should * recover pages from existing sessions. For now fail session * creation. -- cgit v0.10.2 From 88e588d56a2f0226a34386b94a03fda97d2b8e67 Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Thu, 23 Jul 2009 19:02:15 -0400 Subject: nfsd41: change check_slot_seqid parameters For separation of session slot and clientid slot processing. Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 0be417e..99df8e7 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -1309,26 +1309,26 @@ error: } static int -check_slot_seqid(u32 seqid, struct nfsd4_slot *slot) +check_slot_seqid(u32 seqid, u32 slot_seqid, int slot_inuse) { - dprintk("%s enter. seqid %d slot->sl_seqid %d\n", __func__, seqid, - slot->sl_seqid); + dprintk("%s enter. seqid %d slot_seqid %d\n", __func__, seqid, + slot_seqid); /* The slot is in use, and no response has been sent. */ - if (slot->sl_inuse) { - if (seqid == slot->sl_seqid) + if (slot_inuse) { + if (seqid == slot_seqid) return nfserr_jukebox; else return nfserr_seq_misordered; } /* Normal */ - if (likely(seqid == slot->sl_seqid + 1)) + if (likely(seqid == slot_seqid + 1)) return nfs_ok; /* Replay */ - if (seqid == slot->sl_seqid) + if (seqid == slot_seqid) return nfserr_replay_cache; /* Wraparound */ - if (seqid == 1 && (slot->sl_seqid + 1) == 0) + if (seqid == 1 && (slot_seqid + 1) == 0) return nfs_ok; /* Misordered replay or misordered new request */ return nfserr_seq_misordered; @@ -1351,7 +1351,8 @@ nfsd4_create_session(struct svc_rqst *rqstp, if (conf) { slot = &conf->cl_slot; - status = check_slot_seqid(cr_ses->seqid, slot); + status = check_slot_seqid(cr_ses->seqid, slot->sl_seqid, + slot->sl_inuse); if (status == nfserr_replay_cache) { dprintk("Got a create_session replay! seqid= %d\n", slot->sl_seqid); @@ -1376,7 +1377,8 @@ nfsd4_create_session(struct svc_rqst *rqstp, } slot = &unconf->cl_slot; - status = check_slot_seqid(cr_ses->seqid, slot); + status = check_slot_seqid(cr_ses->seqid, slot->sl_seqid, + slot->sl_inuse); if (status) { /* an unconfirmed replay returns misordered */ status = nfserr_seq_misordered; @@ -1477,7 +1479,7 @@ nfsd4_sequence(struct svc_rqst *rqstp, slot = &session->se_slots[seq->slotid]; dprintk("%s: slotid %d\n", __func__, seq->slotid); - status = check_slot_seqid(seq->seqid, slot); + status = check_slot_seqid(seq->seqid, slot->sl_seqid, slot->sl_inuse); if (status == nfserr_replay_cache) { cstate->slot = slot; cstate->session = session; -- cgit v0.10.2 From 49557cc74c7bdf6a984be227ead9a84b3a26f053 Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Thu, 23 Jul 2009 19:02:16 -0400 Subject: nfsd41: Use separate DRC for setclientid Instead of trying to share the generic 4.1 reply cache code for the CREATE_SESSION reply cache, it's simpler to handle CREATE_SESSION separately. The nfs41 single slot clientid DRC holds the results of create session processing. CREATE_SESSION can be preceeded by a SEQUENCE operation (an embedded CREATE_SESSION) and the create session single slot cache must be maintained. nfsd4_replay_cache_entry() and nfsd4_store_cache_entry() do not implement the replay of an embedded CREATE_SESSION. The clientid DRC slot does not need the inuse, cachethis or other fields that the multiple slot session cache uses. Replace the clientid DRC cache struct nfs4_slot cache with a new nfsd4_clid_slot cache. Save the xdr struct nfsd4_create_session into the cache at the end of processing, and on a replay, replace the struct for the replay request with the cached version all while under the state lock. nfsd4_proc_compound will handle both the solo and embedded CREATE_SESSION case via the normal use of encode_operation. Errors that do not change the create session cache: A create session NFS4ERR_STALE_CLIENTID error means that a client record (and associated create session slot) could not be found and therefore can't be changed. NFSERR_SEQ_MISORDERED errors do not change the slot cache. All other errors get cached. Remove the clientid DRC specific check in nfs4svc_encode_compoundres to put the session only if cstate.session is set which will now always be true. Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c index d781658..d606c6a 100644 --- a/fs/nfsd/nfs4proc.c +++ b/fs/nfsd/nfs4proc.c @@ -1120,7 +1120,7 @@ nfsd4_proc_compound(struct svc_rqst *rqstp, BUG_ON(op->status == nfs_ok); encode_op: - /* Only from SEQUENCE or CREATE_SESSION */ + /* Only from SEQUENCE */ if (resp->cstate.status == nfserr_replay_cache) { dprintk("%s NFS4.1 replay from cache\n", __func__); if (nfsd4_not_cached(resp)) diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 99df8e7..7729d09 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -653,8 +653,6 @@ static inline void free_client(struct nfs4_client *clp) { shutdown_callback_client(clp); - nfsd4_release_respages(clp->cl_slot.sl_cache_entry.ce_respages, - clp->cl_slot.sl_cache_entry.ce_resused); if (clp->cl_cred.cr_group_info) put_group_info(clp->cl_cred.cr_group_info); kfree(clp->cl_principal); @@ -1293,12 +1291,11 @@ out_copy: exid->clientid.cl_boot = new->cl_clientid.cl_boot; exid->clientid.cl_id = new->cl_clientid.cl_id; - new->cl_slot.sl_seqid = 0; exid->seqid = 1; nfsd4_set_ex_flags(new, exid); dprintk("nfsd4_exchange_id seqid %d flags %x\n", - new->cl_slot.sl_seqid, new->cl_exchange_flags); + new->cl_cs_slot.sl_seqid, new->cl_exchange_flags); status = nfs_ok; out: @@ -1334,15 +1331,35 @@ check_slot_seqid(u32 seqid, u32 slot_seqid, int slot_inuse) return nfserr_seq_misordered; } +/* + * Cache the create session result into the create session single DRC + * slot cache by saving the xdr structure. sl_seqid has been set. + * Do this for solo or embedded create session operations. + */ +static void +nfsd4_cache_create_session(struct nfsd4_create_session *cr_ses, + struct nfsd4_clid_slot *slot, int nfserr) +{ + slot->sl_status = nfserr; + memcpy(&slot->sl_cr_ses, cr_ses, sizeof(*cr_ses)); +} + +static __be32 +nfsd4_replay_create_session(struct nfsd4_create_session *cr_ses, + struct nfsd4_clid_slot *slot) +{ + memcpy(cr_ses, &slot->sl_cr_ses, sizeof(*cr_ses)); + return slot->sl_status; +} + __be32 nfsd4_create_session(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, struct nfsd4_create_session *cr_ses) { u32 ip_addr = svc_addr_in(rqstp)->sin_addr.s_addr; - struct nfsd4_compoundres *resp = rqstp->rq_resp; struct nfs4_client *conf, *unconf; - struct nfsd4_slot *slot = NULL; + struct nfsd4_clid_slot *cs_slot = NULL; int status = 0; nfs4_lock_state(); @@ -1350,25 +1367,22 @@ nfsd4_create_session(struct svc_rqst *rqstp, conf = find_confirmed_client(&cr_ses->clientid); if (conf) { - slot = &conf->cl_slot; - status = check_slot_seqid(cr_ses->seqid, slot->sl_seqid, - slot->sl_inuse); + cs_slot = &conf->cl_cs_slot; + status = check_slot_seqid(cr_ses->seqid, cs_slot->sl_seqid, 0); if (status == nfserr_replay_cache) { dprintk("Got a create_session replay! seqid= %d\n", - slot->sl_seqid); - cstate->slot = slot; - cstate->status = status; + cs_slot->sl_seqid); /* Return the cached reply status */ - status = nfsd4_replay_cache_entry(resp, NULL); + status = nfsd4_replay_create_session(cr_ses, cs_slot); goto out; - } else if (cr_ses->seqid != conf->cl_slot.sl_seqid + 1) { + } else if (cr_ses->seqid != cs_slot->sl_seqid + 1) { status = nfserr_seq_misordered; dprintk("Sequence misordered!\n"); dprintk("Expected seqid= %d but got seqid= %d\n", - slot->sl_seqid, cr_ses->seqid); + cs_slot->sl_seqid, cr_ses->seqid); goto out; } - conf->cl_slot.sl_seqid++; + cs_slot->sl_seqid++; } else if (unconf) { if (!same_creds(&unconf->cl_cred, &rqstp->rq_cred) || (ip_addr != unconf->cl_addr)) { @@ -1376,16 +1390,15 @@ nfsd4_create_session(struct svc_rqst *rqstp, goto out; } - slot = &unconf->cl_slot; - status = check_slot_seqid(cr_ses->seqid, slot->sl_seqid, - slot->sl_inuse); + cs_slot = &unconf->cl_cs_slot; + status = check_slot_seqid(cr_ses->seqid, cs_slot->sl_seqid, 0); if (status) { /* an unconfirmed replay returns misordered */ status = nfserr_seq_misordered; - goto out; + goto out_cache; } - slot->sl_seqid++; /* from 0 to 1 */ + cs_slot->sl_seqid++; /* from 0 to 1 */ move_to_confirmed(unconf); /* @@ -1406,12 +1419,11 @@ nfsd4_create_session(struct svc_rqst *rqstp, memcpy(cr_ses->sessionid.data, conf->cl_sessionid.data, NFS4_MAX_SESSIONID_LEN); - cr_ses->seqid = slot->sl_seqid; + cr_ses->seqid = cs_slot->sl_seqid; - slot->sl_inuse = true; - cstate->slot = slot; - /* Ensure a page is used for the cache */ - slot->sl_cache_entry.ce_cachethis = 1; +out_cache: + /* cache solo and embedded create sessions under the state lock */ + nfsd4_cache_create_session(cr_ses, cs_slot, status); out: nfs4_unlock_state(); dprintk("%s returns %d\n", __func__, ntohl(status)); diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c index 2dcc7fe..fdf632b 100644 --- a/fs/nfsd/nfs4xdr.c +++ b/fs/nfsd/nfs4xdr.c @@ -3313,8 +3313,7 @@ nfs4svc_encode_compoundres(struct svc_rqst *rqstp, __be32 *p, struct nfsd4_compo dprintk("%s: SET SLOT STATE TO AVAILABLE\n", __func__); resp->cstate.slot->sl_inuse = 0; } - if (resp->cstate.session) - nfsd4_put_session(resp->cstate.session); + nfsd4_put_session(resp->cstate.session); } return 1; } diff --git a/include/linux/nfsd/state.h b/include/linux/nfsd/state.h index a6c87d6..58bb197 100644 --- a/include/linux/nfsd/state.h +++ b/include/linux/nfsd/state.h @@ -127,6 +127,25 @@ struct nfsd4_channel_attrs { u32 rdma_attrs; }; +struct nfsd4_create_session { + clientid_t clientid; + struct nfs4_sessionid sessionid; + u32 seqid; + u32 flags; + struct nfsd4_channel_attrs fore_channel; + struct nfsd4_channel_attrs back_channel; + u32 callback_prog; + u32 uid; + u32 gid; +}; + +/* The single slot clientid cache structure */ +struct nfsd4_clid_slot { + u32 sl_seqid; + __be32 sl_status; + struct nfsd4_create_session sl_cr_ses; +}; + struct nfsd4_session { struct kref se_ref; struct list_head se_hash; /* hash by sessionid */ @@ -193,7 +212,7 @@ struct nfs4_client { /* for nfs41 */ struct list_head cl_sessions; - struct nfsd4_slot cl_slot; /* create_session slot */ + struct nfsd4_clid_slot cl_cs_slot; /* create_session slot */ u32 cl_exchange_flags; struct nfs4_sessionid cl_sessionid; }; diff --git a/include/linux/nfsd/xdr4.h b/include/linux/nfsd/xdr4.h index 2bacf75..5e4beb0 100644 --- a/include/linux/nfsd/xdr4.h +++ b/include/linux/nfsd/xdr4.h @@ -366,18 +366,6 @@ struct nfsd4_exchange_id { int spa_how; }; -struct nfsd4_create_session { - clientid_t clientid; - struct nfs4_sessionid sessionid; - u32 seqid; - u32 flags; - struct nfsd4_channel_attrs fore_channel; - struct nfsd4_channel_attrs back_channel; - u32 callback_prog; - u32 uid; - u32 gid; -}; - struct nfsd4_sequence { struct nfs4_sessionid sessionid; /* request/response */ u32 seqid; /* request/response */ -- cgit v0.10.2 From c8647947f8c13ee2647505debae284ab1c859e65 Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Thu, 23 Jul 2009 19:02:17 -0400 Subject: nfsd41: rename nfsd4_enc_uncached_replay This function is only used for SEQUENCE replay. Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c index d606c6a..23cd738 100644 --- a/fs/nfsd/nfs4proc.c +++ b/fs/nfsd/nfs4proc.c @@ -989,7 +989,7 @@ static const char *nfsd4_op_name(unsigned opnum); * encode the uncache rep error on the next operation. */ static __be32 -nfsd4_enc_uncached_replay(struct nfsd4_compoundargs *args, +nfsd4_enc_sequence_replay(struct nfsd4_compoundargs *args, struct nfsd4_compoundres *resp) { struct nfsd4_op *op; @@ -1124,7 +1124,7 @@ encode_op: if (resp->cstate.status == nfserr_replay_cache) { dprintk("%s NFS4.1 replay from cache\n", __func__); if (nfsd4_not_cached(resp)) - status = nfsd4_enc_uncached_replay(args, resp); + status = nfsd4_enc_sequence_replay(args, resp); else status = op->status; goto out; -- cgit v0.10.2 From abfabf8cafa60e7876a7193fb344f739f690071d Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Thu, 23 Jul 2009 19:02:18 -0400 Subject: nfsd41: encode replay sequence from the slot values The sequence operation is not cached; always encode the sequence operation on a replay from the slot table and session values. This simplifies the sessions replay logic in nfsd4_proc_compound. If this is a replay of a compound that was specified not to be cached, return NFS4ERR_RETRY_UNCACHED_REP. Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c index 23cd738..6fde431 100644 --- a/fs/nfsd/nfs4proc.c +++ b/fs/nfsd/nfs4proc.c @@ -984,34 +984,6 @@ static struct nfsd4_operation nfsd4_ops[]; static const char *nfsd4_op_name(unsigned opnum); /* - * This is a replay of a compound for which no cache entry pages - * were used. Encode the sequence operation, and if cachethis is FALSE - * encode the uncache rep error on the next operation. - */ -static __be32 -nfsd4_enc_sequence_replay(struct nfsd4_compoundargs *args, - struct nfsd4_compoundres *resp) -{ - struct nfsd4_op *op; - - dprintk("--> %s resp->opcnt %d ce_cachethis %u \n", __func__, - resp->opcnt, resp->cstate.slot->sl_cache_entry.ce_cachethis); - - /* Encode the replayed sequence operation */ - BUG_ON(resp->opcnt != 1); - op = &args->ops[resp->opcnt - 1]; - nfsd4_encode_operation(resp, op); - - /*return nfserr_retry_uncached_rep in next operation. */ - if (resp->cstate.slot->sl_cache_entry.ce_cachethis == 0) { - op = &args->ops[resp->opcnt++]; - op->status = nfserr_retry_uncached_rep; - nfsd4_encode_operation(resp, op); - } - return op->status; -} - -/* * Enforce NFSv4.1 COMPOUND ordering rules. * * TODO: @@ -1123,10 +1095,7 @@ encode_op: /* Only from SEQUENCE */ if (resp->cstate.status == nfserr_replay_cache) { dprintk("%s NFS4.1 replay from cache\n", __func__); - if (nfsd4_not_cached(resp)) - status = nfsd4_enc_sequence_replay(args, resp); - else - status = op->status; + status = op->status; goto out; } if (op->status == nfserr_replay_me) { diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 7729d09..9295c4b 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -1109,6 +1109,36 @@ nfsd41_copy_replay_data(struct nfsd4_compoundres *resp, } /* + * Encode the replay sequence operation from the slot values. + * If cachethis is FALSE encode the uncached rep error on the next + * operation which sets resp->p and increments resp->opcnt for + * nfs4svc_encode_compoundres. + * + */ +static __be32 +nfsd4_enc_sequence_replay(struct nfsd4_compoundargs *args, + struct nfsd4_compoundres *resp) +{ + struct nfsd4_op *op; + struct nfsd4_slot *slot = resp->cstate.slot; + + dprintk("--> %s resp->opcnt %d cachethis %u \n", __func__, + resp->opcnt, resp->cstate.slot->sl_cache_entry.ce_cachethis); + + /* Encode the replayed sequence operation */ + op = &args->ops[resp->opcnt - 1]; + nfsd4_encode_operation(resp, op); + + /* Return nfserr_retry_uncached_rep in next operation. */ + if (args->opcnt > 1 && slot->sl_cache_entry.ce_cachethis == 0) { + op = &args->ops[resp->opcnt++]; + op->status = nfserr_retry_uncached_rep; + nfsd4_encode_operation(resp, op); + } + return op->status; +} + +/* * Keep the first page of the replay. Copy the NFSv4.1 data from the first * cached page. Replace any futher replay pages from the cache. */ @@ -1131,10 +1161,12 @@ nfsd4_replay_cache_entry(struct nfsd4_compoundres *resp, * session inactivity timer fires and a solo sequence operation * is sent (lease renewal). */ - if (seq && nfsd4_not_cached(resp)) { - seq->maxslots = resp->cstate.session->se_fchannel.maxreqs; - return nfs_ok; - } + seq->maxslots = resp->cstate.session->se_fchannel.maxreqs; + + /* Either returns 0 or nfserr_retry_uncached */ + status = nfsd4_enc_sequence_replay(resp->rqstp->rq_argp, resp); + if (status == nfserr_retry_uncached_rep) + return status; if (!nfsd41_copy_replay_data(resp, entry)) { /* -- cgit v0.10.2 From 584ec22759c06cdfc189c03a727f20038526245b Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 28 Jul 2009 14:32:12 -0700 Subject: ioat: move to drivers/dma/ioat/ When first created the ioat driver was the only inhabitant of drivers/dma/. Now, it is the only multi-file (more than a .c and a .h) driver in the directory. Moving it to an ioat/ subdirectory allows the naming convention to be cleaned up, and allows for future splitting of the source files by hardware version (v1, v2, and v3). Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 2e5dc96..a1cb285 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -1,8 +1,7 @@ obj-$(CONFIG_DMA_ENGINE) += dmaengine.o obj-$(CONFIG_NET_DMA) += iovlock.o obj-$(CONFIG_DMATEST) += dmatest.o -obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o -ioatdma-objs := ioat.o ioat_dma.o ioat_dca.o +obj-$(CONFIG_INTEL_IOATDMA) += ioat/ obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o obj-$(CONFIG_FSL_DMA) += fsldma.o obj-$(CONFIG_MV_XOR) += mv_xor.o diff --git a/drivers/dma/ioat.c b/drivers/dma/ioat.c deleted file mode 100644 index 2225bb6..0000000 --- a/drivers/dma/ioat.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Intel I/OAT DMA Linux driver - * Copyright(c) 2007 - 2009 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - */ - -/* - * This driver supports an Intel I/OAT DMA engine, which does asynchronous - * copy operations. - */ - -#include -#include -#include -#include -#include -#include "ioatdma.h" -#include "ioatdma_registers.h" -#include "ioatdma_hw.h" - -MODULE_VERSION(IOAT_DMA_VERSION); -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Intel Corporation"); - -static struct pci_device_id ioat_pci_tbl[] = { - /* I/OAT v1 platforms */ - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_CNB) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SCNB) }, - { PCI_DEVICE(PCI_VENDOR_ID_UNISYS, PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR) }, - - /* I/OAT v2 platforms */ - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB) }, - - /* I/OAT v3 platforms */ - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, - { 0, } -}; - -struct ioat_device { - struct pci_dev *pdev; - void __iomem *iobase; - struct ioatdma_device *dma; - struct dca_provider *dca; -}; - -static int __devinit ioat_probe(struct pci_dev *pdev, - const struct pci_device_id *id); -static void __devexit ioat_remove(struct pci_dev *pdev); - -static int ioat_dca_enabled = 1; -module_param(ioat_dca_enabled, int, 0644); -MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); - -static struct pci_driver ioat_pci_driver = { - .name = "ioatdma", - .id_table = ioat_pci_tbl, - .probe = ioat_probe, - .remove = __devexit_p(ioat_remove), -}; - -static int __devinit ioat_probe(struct pci_dev *pdev, - const struct pci_device_id *id) -{ - void __iomem *iobase; - struct ioat_device *device; - unsigned long mmio_start, mmio_len; - int err; - - err = pci_enable_device(pdev); - if (err) - goto err_enable_device; - - err = pci_request_regions(pdev, ioat_pci_driver.name); - if (err) - goto err_request_regions; - - err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); - if (err) - err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); - if (err) - goto err_set_dma_mask; - - err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); - if (err) - err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); - if (err) - goto err_set_dma_mask; - - mmio_start = pci_resource_start(pdev, 0); - mmio_len = pci_resource_len(pdev, 0); - iobase = ioremap(mmio_start, mmio_len); - if (!iobase) { - err = -ENOMEM; - goto err_ioremap; - } - - device = kzalloc(sizeof(*device), GFP_KERNEL); - if (!device) { - err = -ENOMEM; - goto err_kzalloc; - } - device->pdev = pdev; - pci_set_drvdata(pdev, device); - device->iobase = iobase; - - pci_set_master(pdev); - - switch (readb(iobase + IOAT_VER_OFFSET)) { - case IOAT_VER_1_2: - device->dma = ioat_dma_probe(pdev, iobase); - if (device->dma && ioat_dca_enabled) - device->dca = ioat_dca_init(pdev, iobase); - break; - case IOAT_VER_2_0: - device->dma = ioat_dma_probe(pdev, iobase); - if (device->dma && ioat_dca_enabled) - device->dca = ioat2_dca_init(pdev, iobase); - break; - case IOAT_VER_3_0: - device->dma = ioat_dma_probe(pdev, iobase); - if (device->dma && ioat_dca_enabled) - device->dca = ioat3_dca_init(pdev, iobase); - break; - default: - err = -ENODEV; - break; - } - if (!device->dma) - err = -ENODEV; - - if (err) - goto err_version; - - return 0; - -err_version: - kfree(device); -err_kzalloc: - iounmap(iobase); -err_ioremap: -err_set_dma_mask: - pci_release_regions(pdev); - pci_disable_device(pdev); -err_request_regions: -err_enable_device: - return err; -} - -static void __devexit ioat_remove(struct pci_dev *pdev) -{ - struct ioat_device *device = pci_get_drvdata(pdev); - - dev_err(&pdev->dev, "Removing dma and dca services\n"); - if (device->dca) { - unregister_dca_provider(device->dca); - free_dca_provider(device->dca); - device->dca = NULL; - } - - if (device->dma) { - ioat_dma_remove(device->dma); - device->dma = NULL; - } - - kfree(device); -} - -static int __init ioat_init_module(void) -{ - return pci_register_driver(&ioat_pci_driver); -} -module_init(ioat_init_module); - -static void __exit ioat_exit_module(void) -{ - pci_unregister_driver(&ioat_pci_driver); -} -module_exit(ioat_exit_module); diff --git a/drivers/dma/ioat/Makefile b/drivers/dma/ioat/Makefile new file mode 100644 index 0000000..2ce3d3a --- /dev/null +++ b/drivers/dma/ioat/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o +ioatdma-objs := pci.o dma.o dca.o diff --git a/drivers/dma/ioat/dca.c b/drivers/dma/ioat/dca.c new file mode 100644 index 0000000..af1c762 --- /dev/null +++ b/drivers/dma/ioat/dca.c @@ -0,0 +1,681 @@ +/* + * Intel I/OAT DMA Linux driver + * Copyright(c) 2007 - 2009 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + */ + +#include +#include +#include +#include +#include + +/* either a kernel change is needed, or we need something like this in kernel */ +#ifndef CONFIG_SMP +#include +#undef cpu_physical_id +#define cpu_physical_id(cpu) (cpuid_ebx(1) >> 24) +#endif + +#include "dma.h" +#include "registers.h" + +/* + * Bit 7 of a tag map entry is the "valid" bit, if it is set then bits 0:6 + * contain the bit number of the APIC ID to map into the DCA tag. If the valid + * bit is not set, then the value must be 0 or 1 and defines the bit in the tag. + */ +#define DCA_TAG_MAP_VALID 0x80 + +#define DCA3_TAG_MAP_BIT_TO_INV 0x80 +#define DCA3_TAG_MAP_BIT_TO_SEL 0x40 +#define DCA3_TAG_MAP_LITERAL_VAL 0x1 + +#define DCA_TAG_MAP_MASK 0xDF + +/* expected tag map bytes for I/OAT ver.2 */ +#define DCA2_TAG_MAP_BYTE0 0x80 +#define DCA2_TAG_MAP_BYTE1 0x0 +#define DCA2_TAG_MAP_BYTE2 0x81 +#define DCA2_TAG_MAP_BYTE3 0x82 +#define DCA2_TAG_MAP_BYTE4 0x82 + +/* verify if tag map matches expected values */ +static inline int dca2_tag_map_valid(u8 *tag_map) +{ + return ((tag_map[0] == DCA2_TAG_MAP_BYTE0) && + (tag_map[1] == DCA2_TAG_MAP_BYTE1) && + (tag_map[2] == DCA2_TAG_MAP_BYTE2) && + (tag_map[3] == DCA2_TAG_MAP_BYTE3) && + (tag_map[4] == DCA2_TAG_MAP_BYTE4)); +} + +/* + * "Legacy" DCA systems do not implement the DCA register set in the + * I/OAT device. Software needs direct support for their tag mappings. + */ + +#define APICID_BIT(x) (DCA_TAG_MAP_VALID | (x)) +#define IOAT_TAG_MAP_LEN 8 + +static u8 ioat_tag_map_BNB[IOAT_TAG_MAP_LEN] = { + 1, APICID_BIT(1), APICID_BIT(2), APICID_BIT(2), }; +static u8 ioat_tag_map_SCNB[IOAT_TAG_MAP_LEN] = { + 1, APICID_BIT(1), APICID_BIT(2), APICID_BIT(2), }; +static u8 ioat_tag_map_CNB[IOAT_TAG_MAP_LEN] = { + 1, APICID_BIT(1), APICID_BIT(3), APICID_BIT(4), APICID_BIT(2), }; +static u8 ioat_tag_map_UNISYS[IOAT_TAG_MAP_LEN] = { 0 }; + +/* pack PCI B/D/F into a u16 */ +static inline u16 dcaid_from_pcidev(struct pci_dev *pci) +{ + return (pci->bus->number << 8) | pci->devfn; +} + +static int dca_enabled_in_bios(struct pci_dev *pdev) +{ + /* CPUID level 9 returns DCA configuration */ + /* Bit 0 indicates DCA enabled by the BIOS */ + unsigned long cpuid_level_9; + int res; + + cpuid_level_9 = cpuid_eax(9); + res = test_bit(0, &cpuid_level_9); + if (!res) + dev_err(&pdev->dev, "DCA is disabled in BIOS\n"); + + return res; +} + +static int system_has_dca_enabled(struct pci_dev *pdev) +{ + if (boot_cpu_has(X86_FEATURE_DCA)) + return dca_enabled_in_bios(pdev); + + dev_err(&pdev->dev, "boot cpu doesn't have X86_FEATURE_DCA\n"); + return 0; +} + +struct ioat_dca_slot { + struct pci_dev *pdev; /* requester device */ + u16 rid; /* requester id, as used by IOAT */ +}; + +#define IOAT_DCA_MAX_REQ 6 +#define IOAT3_DCA_MAX_REQ 2 + +struct ioat_dca_priv { + void __iomem *iobase; + void __iomem *dca_base; + int max_requesters; + int requester_count; + u8 tag_map[IOAT_TAG_MAP_LEN]; + struct ioat_dca_slot req_slots[0]; +}; + +/* 5000 series chipset DCA Port Requester ID Table Entry Format + * [15:8] PCI-Express Bus Number + * [7:3] PCI-Express Device Number + * [2:0] PCI-Express Function Number + * + * 5000 series chipset DCA control register format + * [7:1] Reserved (0) + * [0] Ignore Function Number + */ + +static int ioat_dca_add_requester(struct dca_provider *dca, struct device *dev) +{ + struct ioat_dca_priv *ioatdca = dca_priv(dca); + struct pci_dev *pdev; + int i; + u16 id; + + /* This implementation only supports PCI-Express */ + if (dev->bus != &pci_bus_type) + return -ENODEV; + pdev = to_pci_dev(dev); + id = dcaid_from_pcidev(pdev); + + if (ioatdca->requester_count == ioatdca->max_requesters) + return -ENODEV; + + for (i = 0; i < ioatdca->max_requesters; i++) { + if (ioatdca->req_slots[i].pdev == NULL) { + /* found an empty slot */ + ioatdca->requester_count++; + ioatdca->req_slots[i].pdev = pdev; + ioatdca->req_slots[i].rid = id; + writew(id, ioatdca->dca_base + (i * 4)); + /* make sure the ignore function bit is off */ + writeb(0, ioatdca->dca_base + (i * 4) + 2); + return i; + } + } + /* Error, ioatdma->requester_count is out of whack */ + return -EFAULT; +} + +static int ioat_dca_remove_requester(struct dca_provider *dca, + struct device *dev) +{ + struct ioat_dca_priv *ioatdca = dca_priv(dca); + struct pci_dev *pdev; + int i; + + /* This implementation only supports PCI-Express */ + if (dev->bus != &pci_bus_type) + return -ENODEV; + pdev = to_pci_dev(dev); + + for (i = 0; i < ioatdca->max_requesters; i++) { + if (ioatdca->req_slots[i].pdev == pdev) { + writew(0, ioatdca->dca_base + (i * 4)); + ioatdca->req_slots[i].pdev = NULL; + ioatdca->req_slots[i].rid = 0; + ioatdca->requester_count--; + return i; + } + } + return -ENODEV; +} + +static u8 ioat_dca_get_tag(struct dca_provider *dca, + struct device *dev, + int cpu) +{ + struct ioat_dca_priv *ioatdca = dca_priv(dca); + int i, apic_id, bit, value; + u8 entry, tag; + + tag = 0; + apic_id = cpu_physical_id(cpu); + + for (i = 0; i < IOAT_TAG_MAP_LEN; i++) { + entry = ioatdca->tag_map[i]; + if (entry & DCA_TAG_MAP_VALID) { + bit = entry & ~DCA_TAG_MAP_VALID; + value = (apic_id & (1 << bit)) ? 1 : 0; + } else { + value = entry ? 1 : 0; + } + tag |= (value << i); + } + return tag; +} + +static int ioat_dca_dev_managed(struct dca_provider *dca, + struct device *dev) +{ + struct ioat_dca_priv *ioatdca = dca_priv(dca); + struct pci_dev *pdev; + int i; + + pdev = to_pci_dev(dev); + for (i = 0; i < ioatdca->max_requesters; i++) { + if (ioatdca->req_slots[i].pdev == pdev) + return 1; + } + return 0; +} + +static struct dca_ops ioat_dca_ops = { + .add_requester = ioat_dca_add_requester, + .remove_requester = ioat_dca_remove_requester, + .get_tag = ioat_dca_get_tag, + .dev_managed = ioat_dca_dev_managed, +}; + + +struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase) +{ + struct dca_provider *dca; + struct ioat_dca_priv *ioatdca; + u8 *tag_map = NULL; + int i; + int err; + u8 version; + u8 max_requesters; + + if (!system_has_dca_enabled(pdev)) + return NULL; + + /* I/OAT v1 systems must have a known tag_map to support DCA */ + switch (pdev->vendor) { + case PCI_VENDOR_ID_INTEL: + switch (pdev->device) { + case PCI_DEVICE_ID_INTEL_IOAT: + tag_map = ioat_tag_map_BNB; + break; + case PCI_DEVICE_ID_INTEL_IOAT_CNB: + tag_map = ioat_tag_map_CNB; + break; + case PCI_DEVICE_ID_INTEL_IOAT_SCNB: + tag_map = ioat_tag_map_SCNB; + break; + } + break; + case PCI_VENDOR_ID_UNISYS: + switch (pdev->device) { + case PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR: + tag_map = ioat_tag_map_UNISYS; + break; + } + break; + } + if (tag_map == NULL) + return NULL; + + version = readb(iobase + IOAT_VER_OFFSET); + if (version == IOAT_VER_3_0) + max_requesters = IOAT3_DCA_MAX_REQ; + else + max_requesters = IOAT_DCA_MAX_REQ; + + dca = alloc_dca_provider(&ioat_dca_ops, + sizeof(*ioatdca) + + (sizeof(struct ioat_dca_slot) * max_requesters)); + if (!dca) + return NULL; + + ioatdca = dca_priv(dca); + ioatdca->max_requesters = max_requesters; + ioatdca->dca_base = iobase + 0x54; + + /* copy over the APIC ID to DCA tag mapping */ + for (i = 0; i < IOAT_TAG_MAP_LEN; i++) + ioatdca->tag_map[i] = tag_map[i]; + + err = register_dca_provider(dca, &pdev->dev); + if (err) { + free_dca_provider(dca); + return NULL; + } + + return dca; +} + + +static int ioat2_dca_add_requester(struct dca_provider *dca, struct device *dev) +{ + struct ioat_dca_priv *ioatdca = dca_priv(dca); + struct pci_dev *pdev; + int i; + u16 id; + u16 global_req_table; + + /* This implementation only supports PCI-Express */ + if (dev->bus != &pci_bus_type) + return -ENODEV; + pdev = to_pci_dev(dev); + id = dcaid_from_pcidev(pdev); + + if (ioatdca->requester_count == ioatdca->max_requesters) + return -ENODEV; + + for (i = 0; i < ioatdca->max_requesters; i++) { + if (ioatdca->req_slots[i].pdev == NULL) { + /* found an empty slot */ + ioatdca->requester_count++; + ioatdca->req_slots[i].pdev = pdev; + ioatdca->req_slots[i].rid = id; + global_req_table = + readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET); + writel(id | IOAT_DCA_GREQID_VALID, + ioatdca->iobase + global_req_table + (i * 4)); + return i; + } + } + /* Error, ioatdma->requester_count is out of whack */ + return -EFAULT; +} + +static int ioat2_dca_remove_requester(struct dca_provider *dca, + struct device *dev) +{ + struct ioat_dca_priv *ioatdca = dca_priv(dca); + struct pci_dev *pdev; + int i; + u16 global_req_table; + + /* This implementation only supports PCI-Express */ + if (dev->bus != &pci_bus_type) + return -ENODEV; + pdev = to_pci_dev(dev); + + for (i = 0; i < ioatdca->max_requesters; i++) { + if (ioatdca->req_slots[i].pdev == pdev) { + global_req_table = + readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET); + writel(0, ioatdca->iobase + global_req_table + (i * 4)); + ioatdca->req_slots[i].pdev = NULL; + ioatdca->req_slots[i].rid = 0; + ioatdca->requester_count--; + return i; + } + } + return -ENODEV; +} + +static u8 ioat2_dca_get_tag(struct dca_provider *dca, + struct device *dev, + int cpu) +{ + u8 tag; + + tag = ioat_dca_get_tag(dca, dev, cpu); + tag = (~tag) & 0x1F; + return tag; +} + +static struct dca_ops ioat2_dca_ops = { + .add_requester = ioat2_dca_add_requester, + .remove_requester = ioat2_dca_remove_requester, + .get_tag = ioat2_dca_get_tag, + .dev_managed = ioat_dca_dev_managed, +}; + +static int ioat2_dca_count_dca_slots(void __iomem *iobase, u16 dca_offset) +{ + int slots = 0; + u32 req; + u16 global_req_table; + + global_req_table = readw(iobase + dca_offset + IOAT_DCA_GREQID_OFFSET); + if (global_req_table == 0) + return 0; + do { + req = readl(iobase + global_req_table + (slots * sizeof(u32))); + slots++; + } while ((req & IOAT_DCA_GREQID_LASTID) == 0); + + return slots; +} + +struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase) +{ + struct dca_provider *dca; + struct ioat_dca_priv *ioatdca; + int slots; + int i; + int err; + u32 tag_map; + u16 dca_offset; + u16 csi_fsb_control; + u16 pcie_control; + u8 bit; + + if (!system_has_dca_enabled(pdev)) + return NULL; + + dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET); + if (dca_offset == 0) + return NULL; + + slots = ioat2_dca_count_dca_slots(iobase, dca_offset); + if (slots == 0) + return NULL; + + dca = alloc_dca_provider(&ioat2_dca_ops, + sizeof(*ioatdca) + + (sizeof(struct ioat_dca_slot) * slots)); + if (!dca) + return NULL; + + ioatdca = dca_priv(dca); + ioatdca->iobase = iobase; + ioatdca->dca_base = iobase + dca_offset; + ioatdca->max_requesters = slots; + + /* some bios might not know to turn these on */ + csi_fsb_control = readw(ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET); + if ((csi_fsb_control & IOAT_FSB_CAP_ENABLE_PREFETCH) == 0) { + csi_fsb_control |= IOAT_FSB_CAP_ENABLE_PREFETCH; + writew(csi_fsb_control, + ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET); + } + pcie_control = readw(ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET); + if ((pcie_control & IOAT_PCI_CAP_ENABLE_MEMWR) == 0) { + pcie_control |= IOAT_PCI_CAP_ENABLE_MEMWR; + writew(pcie_control, + ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET); + } + + + /* TODO version, compatibility and configuration checks */ + + /* copy out the APIC to DCA tag map */ + tag_map = readl(ioatdca->dca_base + IOAT_APICID_TAG_MAP_OFFSET); + for (i = 0; i < 5; i++) { + bit = (tag_map >> (4 * i)) & 0x0f; + if (bit < 8) + ioatdca->tag_map[i] = bit | DCA_TAG_MAP_VALID; + else + ioatdca->tag_map[i] = 0; + } + + if (!dca2_tag_map_valid(ioatdca->tag_map)) { + dev_err(&pdev->dev, "APICID_TAG_MAP set incorrectly by BIOS, " + "disabling DCA\n"); + free_dca_provider(dca); + return NULL; + } + + err = register_dca_provider(dca, &pdev->dev); + if (err) { + free_dca_provider(dca); + return NULL; + } + + return dca; +} + +static int ioat3_dca_add_requester(struct dca_provider *dca, struct device *dev) +{ + struct ioat_dca_priv *ioatdca = dca_priv(dca); + struct pci_dev *pdev; + int i; + u16 id; + u16 global_req_table; + + /* This implementation only supports PCI-Express */ + if (dev->bus != &pci_bus_type) + return -ENODEV; + pdev = to_pci_dev(dev); + id = dcaid_from_pcidev(pdev); + + if (ioatdca->requester_count == ioatdca->max_requesters) + return -ENODEV; + + for (i = 0; i < ioatdca->max_requesters; i++) { + if (ioatdca->req_slots[i].pdev == NULL) { + /* found an empty slot */ + ioatdca->requester_count++; + ioatdca->req_slots[i].pdev = pdev; + ioatdca->req_slots[i].rid = id; + global_req_table = + readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); + writel(id | IOAT_DCA_GREQID_VALID, + ioatdca->iobase + global_req_table + (i * 4)); + return i; + } + } + /* Error, ioatdma->requester_count is out of whack */ + return -EFAULT; +} + +static int ioat3_dca_remove_requester(struct dca_provider *dca, + struct device *dev) +{ + struct ioat_dca_priv *ioatdca = dca_priv(dca); + struct pci_dev *pdev; + int i; + u16 global_req_table; + + /* This implementation only supports PCI-Express */ + if (dev->bus != &pci_bus_type) + return -ENODEV; + pdev = to_pci_dev(dev); + + for (i = 0; i < ioatdca->max_requesters; i++) { + if (ioatdca->req_slots[i].pdev == pdev) { + global_req_table = + readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); + writel(0, ioatdca->iobase + global_req_table + (i * 4)); + ioatdca->req_slots[i].pdev = NULL; + ioatdca->req_slots[i].rid = 0; + ioatdca->requester_count--; + return i; + } + } + return -ENODEV; +} + +static u8 ioat3_dca_get_tag(struct dca_provider *dca, + struct device *dev, + int cpu) +{ + u8 tag; + + struct ioat_dca_priv *ioatdca = dca_priv(dca); + int i, apic_id, bit, value; + u8 entry; + + tag = 0; + apic_id = cpu_physical_id(cpu); + + for (i = 0; i < IOAT_TAG_MAP_LEN; i++) { + entry = ioatdca->tag_map[i]; + if (entry & DCA3_TAG_MAP_BIT_TO_SEL) { + bit = entry & + ~(DCA3_TAG_MAP_BIT_TO_SEL | DCA3_TAG_MAP_BIT_TO_INV); + value = (apic_id & (1 << bit)) ? 1 : 0; + } else if (entry & DCA3_TAG_MAP_BIT_TO_INV) { + bit = entry & ~DCA3_TAG_MAP_BIT_TO_INV; + value = (apic_id & (1 << bit)) ? 0 : 1; + } else { + value = (entry & DCA3_TAG_MAP_LITERAL_VAL) ? 1 : 0; + } + tag |= (value << i); + } + + return tag; +} + +static struct dca_ops ioat3_dca_ops = { + .add_requester = ioat3_dca_add_requester, + .remove_requester = ioat3_dca_remove_requester, + .get_tag = ioat3_dca_get_tag, + .dev_managed = ioat_dca_dev_managed, +}; + +static int ioat3_dca_count_dca_slots(void *iobase, u16 dca_offset) +{ + int slots = 0; + u32 req; + u16 global_req_table; + + global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET); + if (global_req_table == 0) + return 0; + + do { + req = readl(iobase + global_req_table + (slots * sizeof(u32))); + slots++; + } while ((req & IOAT_DCA_GREQID_LASTID) == 0); + + return slots; +} + +struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase) +{ + struct dca_provider *dca; + struct ioat_dca_priv *ioatdca; + int slots; + int i; + int err; + u16 dca_offset; + u16 csi_fsb_control; + u16 pcie_control; + u8 bit; + + union { + u64 full; + struct { + u32 low; + u32 high; + }; + } tag_map; + + if (!system_has_dca_enabled(pdev)) + return NULL; + + dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET); + if (dca_offset == 0) + return NULL; + + slots = ioat3_dca_count_dca_slots(iobase, dca_offset); + if (slots == 0) + return NULL; + + dca = alloc_dca_provider(&ioat3_dca_ops, + sizeof(*ioatdca) + + (sizeof(struct ioat_dca_slot) * slots)); + if (!dca) + return NULL; + + ioatdca = dca_priv(dca); + ioatdca->iobase = iobase; + ioatdca->dca_base = iobase + dca_offset; + ioatdca->max_requesters = slots; + + /* some bios might not know to turn these on */ + csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET); + if ((csi_fsb_control & IOAT3_CSI_CONTROL_PREFETCH) == 0) { + csi_fsb_control |= IOAT3_CSI_CONTROL_PREFETCH; + writew(csi_fsb_control, + ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET); + } + pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET); + if ((pcie_control & IOAT3_PCI_CONTROL_MEMWR) == 0) { + pcie_control |= IOAT3_PCI_CONTROL_MEMWR; + writew(pcie_control, + ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET); + } + + + /* TODO version, compatibility and configuration checks */ + + /* copy out the APIC to DCA tag map */ + tag_map.low = + readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_LOW); + tag_map.high = + readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_HIGH); + for (i = 0; i < 8; i++) { + bit = tag_map.full >> (8 * i); + ioatdca->tag_map[i] = bit & DCA_TAG_MAP_MASK; + } + + err = register_dca_provider(dca, &pdev->dev); + if (err) { + free_dca_provider(dca); + return NULL; + } + + return dca; +} diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c new file mode 100644 index 0000000..648797e --- /dev/null +++ b/drivers/dma/ioat/dma.c @@ -0,0 +1,1741 @@ +/* + * Intel I/OAT DMA Linux driver + * Copyright(c) 2004 - 2009 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + */ + +/* + * This driver supports an Intel I/OAT DMA engine, which does asynchronous + * copy operations. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dma.h" +#include "registers.h" +#include "hw.h" + +#define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common) +#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) +#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) +#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx) + +#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) +static int ioat_pending_level = 4; +module_param(ioat_pending_level, int, 0644); +MODULE_PARM_DESC(ioat_pending_level, + "high-water mark for pushing ioat descriptors (default: 4)"); + +#define RESET_DELAY msecs_to_jiffies(100) +#define WATCHDOG_DELAY round_jiffies(msecs_to_jiffies(2000)) +static void ioat_dma_chan_reset_part2(struct work_struct *work); +static void ioat_dma_chan_watchdog(struct work_struct *work); + +/* + * workaround for IOAT ver.3.0 null descriptor issue + * (channel returns error when size is 0) + */ +#define NULL_DESC_BUFFER_SIZE 1 + +/* internal functions */ +static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan); +static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan); + +static struct ioat_desc_sw * +ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan); +static struct ioat_desc_sw * +ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan); + +static inline struct ioat_dma_chan *ioat_lookup_chan_by_index( + struct ioatdma_device *device, + int index) +{ + return device->idx[index]; +} + +/** + * ioat_dma_do_interrupt - handler used for single vector interrupt mode + * @irq: interrupt id + * @data: interrupt data + */ +static irqreturn_t ioat_dma_do_interrupt(int irq, void *data) +{ + struct ioatdma_device *instance = data; + struct ioat_dma_chan *ioat_chan; + unsigned long attnstatus; + int bit; + u8 intrctrl; + + intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); + + if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) + return IRQ_NONE; + + if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { + writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); + return IRQ_NONE; + } + + attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); + for_each_bit(bit, &attnstatus, BITS_PER_LONG) { + ioat_chan = ioat_lookup_chan_by_index(instance, bit); + tasklet_schedule(&ioat_chan->cleanup_task); + } + + writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); + return IRQ_HANDLED; +} + +/** + * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode + * @irq: interrupt id + * @data: interrupt data + */ +static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) +{ + struct ioat_dma_chan *ioat_chan = data; + + tasklet_schedule(&ioat_chan->cleanup_task); + + return IRQ_HANDLED; +} + +static void ioat_dma_cleanup_tasklet(unsigned long data); + +/** + * ioat_dma_enumerate_channels - find and initialize the device's channels + * @device: the device to be enumerated + */ +static int ioat_dma_enumerate_channels(struct ioatdma_device *device) +{ + u8 xfercap_scale; + u32 xfercap; + int i; + struct ioat_dma_chan *ioat_chan; + + /* + * IOAT ver.3 workarounds + */ + if (device->version == IOAT_VER_3_0) { + u32 chan_err_mask; + u16 dev_id; + u32 dmauncerrsts; + + /* + * Write CHANERRMSK_INT with 3E07h to mask out the errors + * that can cause stability issues for IOAT ver.3 + */ + chan_err_mask = 0x3E07; + pci_write_config_dword(device->pdev, + IOAT_PCI_CHANERRMASK_INT_OFFSET, + chan_err_mask); + + /* + * Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit + * (workaround for spurious config parity error after restart) + */ + pci_read_config_word(device->pdev, + IOAT_PCI_DEVICE_ID_OFFSET, + &dev_id); + if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) { + dmauncerrsts = 0x10; + pci_write_config_dword(device->pdev, + IOAT_PCI_DMAUNCERRSTS_OFFSET, + dmauncerrsts); + } + } + + device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); + xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); + xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); + +#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL + if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) { + device->common.chancnt--; + } +#endif + for (i = 0; i < device->common.chancnt; i++) { + ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL); + if (!ioat_chan) { + device->common.chancnt = i; + break; + } + + ioat_chan->device = device; + ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1)); + ioat_chan->xfercap = xfercap; + ioat_chan->desccount = 0; + INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2); + if (ioat_chan->device->version == IOAT_VER_2_0) + writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | + IOAT_DMA_DCA_ANY_CPU, + ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); + else if (ioat_chan->device->version == IOAT_VER_3_0) + writel(IOAT_DMA_DCA_ANY_CPU, + ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); + spin_lock_init(&ioat_chan->cleanup_lock); + spin_lock_init(&ioat_chan->desc_lock); + INIT_LIST_HEAD(&ioat_chan->free_desc); + INIT_LIST_HEAD(&ioat_chan->used_desc); + /* This should be made common somewhere in dmaengine.c */ + ioat_chan->common.device = &device->common; + list_add_tail(&ioat_chan->common.device_node, + &device->common.channels); + device->idx[i] = ioat_chan; + tasklet_init(&ioat_chan->cleanup_task, + ioat_dma_cleanup_tasklet, + (unsigned long) ioat_chan); + tasklet_disable(&ioat_chan->cleanup_task); + } + return device->common.chancnt; +} + +/** + * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended + * descriptors to hw + * @chan: DMA channel handle + */ +static inline void __ioat1_dma_memcpy_issue_pending( + struct ioat_dma_chan *ioat_chan) +{ + ioat_chan->pending = 0; + writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET); +} + +static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan) +{ + struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + + if (ioat_chan->pending > 0) { + spin_lock_bh(&ioat_chan->desc_lock); + __ioat1_dma_memcpy_issue_pending(ioat_chan); + spin_unlock_bh(&ioat_chan->desc_lock); + } +} + +static inline void __ioat2_dma_memcpy_issue_pending( + struct ioat_dma_chan *ioat_chan) +{ + ioat_chan->pending = 0; + writew(ioat_chan->dmacount, + ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); +} + +static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan) +{ + struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + + if (ioat_chan->pending > 0) { + spin_lock_bh(&ioat_chan->desc_lock); + __ioat2_dma_memcpy_issue_pending(ioat_chan); + spin_unlock_bh(&ioat_chan->desc_lock); + } +} + + +/** + * ioat_dma_chan_reset_part2 - reinit the channel after a reset + */ +static void ioat_dma_chan_reset_part2(struct work_struct *work) +{ + struct ioat_dma_chan *ioat_chan = + container_of(work, struct ioat_dma_chan, work.work); + struct ioat_desc_sw *desc; + + spin_lock_bh(&ioat_chan->cleanup_lock); + spin_lock_bh(&ioat_chan->desc_lock); + + ioat_chan->completion_virt->low = 0; + ioat_chan->completion_virt->high = 0; + ioat_chan->pending = 0; + + /* + * count the descriptors waiting, and be sure to do it + * right for both the CB1 line and the CB2 ring + */ + ioat_chan->dmacount = 0; + if (ioat_chan->used_desc.prev) { + desc = to_ioat_desc(ioat_chan->used_desc.prev); + do { + ioat_chan->dmacount++; + desc = to_ioat_desc(desc->node.next); + } while (&desc->node != ioat_chan->used_desc.next); + } + + /* + * write the new starting descriptor address + * this puts channel engine into ARMED state + */ + desc = to_ioat_desc(ioat_chan->used_desc.prev); + switch (ioat_chan->device->version) { + case IOAT_VER_1_2: + writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF, + ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); + writel(((u64) desc->async_tx.phys) >> 32, + ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); + + writeb(IOAT_CHANCMD_START, ioat_chan->reg_base + + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); + break; + case IOAT_VER_2_0: + writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF, + ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); + writel(((u64) desc->async_tx.phys) >> 32, + ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); + + /* tell the engine to go with what's left to be done */ + writew(ioat_chan->dmacount, + ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); + + break; + } + dev_err(&ioat_chan->device->pdev->dev, + "chan%d reset - %d descs waiting, %d total desc\n", + chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); + + spin_unlock_bh(&ioat_chan->desc_lock); + spin_unlock_bh(&ioat_chan->cleanup_lock); +} + +/** + * ioat_dma_reset_channel - restart a channel + * @ioat_chan: IOAT DMA channel handle + */ +static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan) +{ + u32 chansts, chanerr; + + if (!ioat_chan->used_desc.prev) + return; + + chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); + chansts = (ioat_chan->completion_virt->low + & IOAT_CHANSTS_DMA_TRANSFER_STATUS); + if (chanerr) { + dev_err(&ioat_chan->device->pdev->dev, + "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", + chan_num(ioat_chan), chansts, chanerr); + writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); + } + + /* + * whack it upside the head with a reset + * and wait for things to settle out. + * force the pending count to a really big negative + * to make sure no one forces an issue_pending + * while we're waiting. + */ + + spin_lock_bh(&ioat_chan->desc_lock); + ioat_chan->pending = INT_MIN; + writeb(IOAT_CHANCMD_RESET, + ioat_chan->reg_base + + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); + spin_unlock_bh(&ioat_chan->desc_lock); + + /* schedule the 2nd half instead of sleeping a long time */ + schedule_delayed_work(&ioat_chan->work, RESET_DELAY); +} + +/** + * ioat_dma_chan_watchdog - watch for stuck channels + */ +static void ioat_dma_chan_watchdog(struct work_struct *work) +{ + struct ioatdma_device *device = + container_of(work, struct ioatdma_device, work.work); + struct ioat_dma_chan *ioat_chan; + int i; + + union { + u64 full; + struct { + u32 low; + u32 high; + }; + } completion_hw; + unsigned long compl_desc_addr_hw; + + for (i = 0; i < device->common.chancnt; i++) { + ioat_chan = ioat_lookup_chan_by_index(device, i); + + if (ioat_chan->device->version == IOAT_VER_1_2 + /* have we started processing anything yet */ + && ioat_chan->last_completion + /* have we completed any since last watchdog cycle? */ + && (ioat_chan->last_completion == + ioat_chan->watchdog_completion) + /* has TCP stuck on one cookie since last watchdog? */ + && (ioat_chan->watchdog_tcp_cookie == + ioat_chan->watchdog_last_tcp_cookie) + && (ioat_chan->watchdog_tcp_cookie != + ioat_chan->completed_cookie) + /* is there something in the chain to be processed? */ + /* CB1 chain always has at least the last one processed */ + && (ioat_chan->used_desc.prev != ioat_chan->used_desc.next) + && ioat_chan->pending == 0) { + + /* + * check CHANSTS register for completed + * descriptor address. + * if it is different than completion writeback, + * it is not zero + * and it has changed since the last watchdog + * we can assume that channel + * is still working correctly + * and the problem is in completion writeback. + * update completion writeback + * with actual CHANSTS value + * else + * try resetting the channel + */ + + completion_hw.low = readl(ioat_chan->reg_base + + IOAT_CHANSTS_OFFSET_LOW(ioat_chan->device->version)); + completion_hw.high = readl(ioat_chan->reg_base + + IOAT_CHANSTS_OFFSET_HIGH(ioat_chan->device->version)); +#if (BITS_PER_LONG == 64) + compl_desc_addr_hw = + completion_hw.full + & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; +#else + compl_desc_addr_hw = + completion_hw.low & IOAT_LOW_COMPLETION_MASK; +#endif + + if ((compl_desc_addr_hw != 0) + && (compl_desc_addr_hw != ioat_chan->watchdog_completion) + && (compl_desc_addr_hw != ioat_chan->last_compl_desc_addr_hw)) { + ioat_chan->last_compl_desc_addr_hw = compl_desc_addr_hw; + ioat_chan->completion_virt->low = completion_hw.low; + ioat_chan->completion_virt->high = completion_hw.high; + } else { + ioat_dma_reset_channel(ioat_chan); + ioat_chan->watchdog_completion = 0; + ioat_chan->last_compl_desc_addr_hw = 0; + } + + /* + * for version 2.0 if there are descriptors yet to be processed + * and the last completed hasn't changed since the last watchdog + * if they haven't hit the pending level + * issue the pending to push them through + * else + * try resetting the channel + */ + } else if (ioat_chan->device->version == IOAT_VER_2_0 + && ioat_chan->used_desc.prev + && ioat_chan->last_completion + && ioat_chan->last_completion == ioat_chan->watchdog_completion) { + + if (ioat_chan->pending < ioat_pending_level) + ioat2_dma_memcpy_issue_pending(&ioat_chan->common); + else { + ioat_dma_reset_channel(ioat_chan); + ioat_chan->watchdog_completion = 0; + } + } else { + ioat_chan->last_compl_desc_addr_hw = 0; + ioat_chan->watchdog_completion + = ioat_chan->last_completion; + } + + ioat_chan->watchdog_last_tcp_cookie = + ioat_chan->watchdog_tcp_cookie; + } + + schedule_delayed_work(&device->work, WATCHDOG_DELAY); +} + +static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan); + struct ioat_desc_sw *first = tx_to_ioat_desc(tx); + struct ioat_desc_sw *prev, *new; + struct ioat_dma_descriptor *hw; + dma_cookie_t cookie; + LIST_HEAD(new_chain); + u32 copy; + size_t len; + dma_addr_t src, dst; + unsigned long orig_flags; + unsigned int desc_count = 0; + + /* src and dest and len are stored in the initial descriptor */ + len = first->len; + src = first->src; + dst = first->dst; + orig_flags = first->async_tx.flags; + new = first; + + spin_lock_bh(&ioat_chan->desc_lock); + prev = to_ioat_desc(ioat_chan->used_desc.prev); + prefetch(prev->hw); + do { + copy = min_t(size_t, len, ioat_chan->xfercap); + + async_tx_ack(&new->async_tx); + + hw = new->hw; + hw->size = copy; + hw->ctl = 0; + hw->src_addr = src; + hw->dst_addr = dst; + hw->next = 0; + + /* chain together the physical address list for the HW */ + wmb(); + prev->hw->next = (u64) new->async_tx.phys; + + len -= copy; + dst += copy; + src += copy; + + list_add_tail(&new->node, &new_chain); + desc_count++; + prev = new; + } while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan))); + + if (!new) { + dev_err(&ioat_chan->device->pdev->dev, + "tx submit failed\n"); + spin_unlock_bh(&ioat_chan->desc_lock); + return -ENOMEM; + } + + hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS; + if (first->async_tx.callback) { + hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN; + if (first != new) { + /* move callback into to last desc */ + new->async_tx.callback = first->async_tx.callback; + new->async_tx.callback_param + = first->async_tx.callback_param; + first->async_tx.callback = NULL; + first->async_tx.callback_param = NULL; + } + } + + new->tx_cnt = desc_count; + new->async_tx.flags = orig_flags; /* client is in control of this ack */ + + /* store the original values for use in later cleanup */ + if (new != first) { + new->src = first->src; + new->dst = first->dst; + new->len = first->len; + } + + /* cookie incr and addition to used_list must be atomic */ + cookie = ioat_chan->common.cookie; + cookie++; + if (cookie < 0) + cookie = 1; + ioat_chan->common.cookie = new->async_tx.cookie = cookie; + + /* write address into NextDescriptor field of last desc in chain */ + to_ioat_desc(ioat_chan->used_desc.prev)->hw->next = + first->async_tx.phys; + list_splice_tail(&new_chain, &ioat_chan->used_desc); + + ioat_chan->dmacount += desc_count; + ioat_chan->pending += desc_count; + if (ioat_chan->pending >= ioat_pending_level) + __ioat1_dma_memcpy_issue_pending(ioat_chan); + spin_unlock_bh(&ioat_chan->desc_lock); + + return cookie; +} + +static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan); + struct ioat_desc_sw *first = tx_to_ioat_desc(tx); + struct ioat_desc_sw *new; + struct ioat_dma_descriptor *hw; + dma_cookie_t cookie; + u32 copy; + size_t len; + dma_addr_t src, dst; + unsigned long orig_flags; + unsigned int desc_count = 0; + + /* src and dest and len are stored in the initial descriptor */ + len = first->len; + src = first->src; + dst = first->dst; + orig_flags = first->async_tx.flags; + new = first; + + /* + * ioat_chan->desc_lock is still in force in version 2 path + * it gets unlocked at end of this function + */ + do { + copy = min_t(size_t, len, ioat_chan->xfercap); + + async_tx_ack(&new->async_tx); + + hw = new->hw; + hw->size = copy; + hw->ctl = 0; + hw->src_addr = src; + hw->dst_addr = dst; + + len -= copy; + dst += copy; + src += copy; + desc_count++; + } while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan))); + + if (!new) { + dev_err(&ioat_chan->device->pdev->dev, + "tx submit failed\n"); + spin_unlock_bh(&ioat_chan->desc_lock); + return -ENOMEM; + } + + hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS; + if (first->async_tx.callback) { + hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN; + if (first != new) { + /* move callback into to last desc */ + new->async_tx.callback = first->async_tx.callback; + new->async_tx.callback_param + = first->async_tx.callback_param; + first->async_tx.callback = NULL; + first->async_tx.callback_param = NULL; + } + } + + new->tx_cnt = desc_count; + new->async_tx.flags = orig_flags; /* client is in control of this ack */ + + /* store the original values for use in later cleanup */ + if (new != first) { + new->src = first->src; + new->dst = first->dst; + new->len = first->len; + } + + /* cookie incr and addition to used_list must be atomic */ + cookie = ioat_chan->common.cookie; + cookie++; + if (cookie < 0) + cookie = 1; + ioat_chan->common.cookie = new->async_tx.cookie = cookie; + + ioat_chan->dmacount += desc_count; + ioat_chan->pending += desc_count; + if (ioat_chan->pending >= ioat_pending_level) + __ioat2_dma_memcpy_issue_pending(ioat_chan); + spin_unlock_bh(&ioat_chan->desc_lock); + + return cookie; +} + +/** + * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair + * @ioat_chan: the channel supplying the memory pool for the descriptors + * @flags: allocation flags + */ +static struct ioat_desc_sw *ioat_dma_alloc_descriptor( + struct ioat_dma_chan *ioat_chan, + gfp_t flags) +{ + struct ioat_dma_descriptor *desc; + struct ioat_desc_sw *desc_sw; + struct ioatdma_device *ioatdma_device; + dma_addr_t phys; + + ioatdma_device = to_ioatdma_device(ioat_chan->common.device); + desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys); + if (unlikely(!desc)) + return NULL; + + desc_sw = kzalloc(sizeof(*desc_sw), flags); + if (unlikely(!desc_sw)) { + pci_pool_free(ioatdma_device->dma_pool, desc, phys); + return NULL; + } + + memset(desc, 0, sizeof(*desc)); + dma_async_tx_descriptor_init(&desc_sw->async_tx, &ioat_chan->common); + switch (ioat_chan->device->version) { + case IOAT_VER_1_2: + desc_sw->async_tx.tx_submit = ioat1_tx_submit; + break; + case IOAT_VER_2_0: + case IOAT_VER_3_0: + desc_sw->async_tx.tx_submit = ioat2_tx_submit; + break; + } + + desc_sw->hw = desc; + desc_sw->async_tx.phys = phys; + + return desc_sw; +} + +static int ioat_initial_desc_count = 256; +module_param(ioat_initial_desc_count, int, 0644); +MODULE_PARM_DESC(ioat_initial_desc_count, + "initial descriptors per channel (default: 256)"); + +/** + * ioat2_dma_massage_chan_desc - link the descriptors into a circle + * @ioat_chan: the channel to be massaged + */ +static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan) +{ + struct ioat_desc_sw *desc, *_desc; + + /* setup used_desc */ + ioat_chan->used_desc.next = ioat_chan->free_desc.next; + ioat_chan->used_desc.prev = NULL; + + /* pull free_desc out of the circle so that every node is a hw + * descriptor, but leave it pointing to the list + */ + ioat_chan->free_desc.prev->next = ioat_chan->free_desc.next; + ioat_chan->free_desc.next->prev = ioat_chan->free_desc.prev; + + /* circle link the hw descriptors */ + desc = to_ioat_desc(ioat_chan->free_desc.next); + desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys; + list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) { + desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys; + } +} + +/** + * ioat_dma_alloc_chan_resources - returns the number of allocated descriptors + * @chan: the channel to be filled out + */ +static int ioat_dma_alloc_chan_resources(struct dma_chan *chan) +{ + struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + struct ioat_desc_sw *desc; + u16 chanctrl; + u32 chanerr; + int i; + LIST_HEAD(tmp_list); + + /* have we already been set up? */ + if (!list_empty(&ioat_chan->free_desc)) + return ioat_chan->desccount; + + /* Setup register to interrupt and write completion status on error */ + chanctrl = IOAT_CHANCTRL_ERR_INT_EN | + IOAT_CHANCTRL_ANY_ERR_ABORT_EN | + IOAT_CHANCTRL_ERR_COMPLETION_EN; + writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); + + chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); + if (chanerr) { + dev_err(&ioat_chan->device->pdev->dev, + "CHANERR = %x, clearing\n", chanerr); + writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); + } + + /* Allocate descriptors */ + for (i = 0; i < ioat_initial_desc_count; i++) { + desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL); + if (!desc) { + dev_err(&ioat_chan->device->pdev->dev, + "Only %d initial descriptors\n", i); + break; + } + list_add_tail(&desc->node, &tmp_list); + } + spin_lock_bh(&ioat_chan->desc_lock); + ioat_chan->desccount = i; + list_splice(&tmp_list, &ioat_chan->free_desc); + if (ioat_chan->device->version != IOAT_VER_1_2) + ioat2_dma_massage_chan_desc(ioat_chan); + spin_unlock_bh(&ioat_chan->desc_lock); + + /* allocate a completion writeback area */ + /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ + ioat_chan->completion_virt = + pci_pool_alloc(ioat_chan->device->completion_pool, + GFP_KERNEL, + &ioat_chan->completion_addr); + memset(ioat_chan->completion_virt, 0, + sizeof(*ioat_chan->completion_virt)); + writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF, + ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); + writel(((u64) ioat_chan->completion_addr) >> 32, + ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); + + tasklet_enable(&ioat_chan->cleanup_task); + ioat_dma_start_null_desc(ioat_chan); /* give chain to dma device */ + return ioat_chan->desccount; +} + +/** + * ioat_dma_free_chan_resources - release all the descriptors + * @chan: the channel to be cleaned + */ +static void ioat_dma_free_chan_resources(struct dma_chan *chan) +{ + struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + struct ioatdma_device *ioatdma_device = to_ioatdma_device(chan->device); + struct ioat_desc_sw *desc, *_desc; + int in_use_descs = 0; + + /* Before freeing channel resources first check + * if they have been previously allocated for this channel. + */ + if (ioat_chan->desccount == 0) + return; + + tasklet_disable(&ioat_chan->cleanup_task); + ioat_dma_memcpy_cleanup(ioat_chan); + + /* Delay 100ms after reset to allow internal DMA logic to quiesce + * before removing DMA descriptor resources. + */ + writeb(IOAT_CHANCMD_RESET, + ioat_chan->reg_base + + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); + mdelay(100); + + spin_lock_bh(&ioat_chan->desc_lock); + switch (ioat_chan->device->version) { + case IOAT_VER_1_2: + list_for_each_entry_safe(desc, _desc, + &ioat_chan->used_desc, node) { + in_use_descs++; + list_del(&desc->node); + pci_pool_free(ioatdma_device->dma_pool, desc->hw, + desc->async_tx.phys); + kfree(desc); + } + list_for_each_entry_safe(desc, _desc, + &ioat_chan->free_desc, node) { + list_del(&desc->node); + pci_pool_free(ioatdma_device->dma_pool, desc->hw, + desc->async_tx.phys); + kfree(desc); + } + break; + case IOAT_VER_2_0: + case IOAT_VER_3_0: + list_for_each_entry_safe(desc, _desc, + ioat_chan->free_desc.next, node) { + list_del(&desc->node); + pci_pool_free(ioatdma_device->dma_pool, desc->hw, + desc->async_tx.phys); + kfree(desc); + } + desc = to_ioat_desc(ioat_chan->free_desc.next); + pci_pool_free(ioatdma_device->dma_pool, desc->hw, + desc->async_tx.phys); + kfree(desc); + INIT_LIST_HEAD(&ioat_chan->free_desc); + INIT_LIST_HEAD(&ioat_chan->used_desc); + break; + } + spin_unlock_bh(&ioat_chan->desc_lock); + + pci_pool_free(ioatdma_device->completion_pool, + ioat_chan->completion_virt, + ioat_chan->completion_addr); + + /* one is ok since we left it on there on purpose */ + if (in_use_descs > 1) + dev_err(&ioat_chan->device->pdev->dev, + "Freeing %d in use descriptors!\n", + in_use_descs - 1); + + ioat_chan->last_completion = ioat_chan->completion_addr = 0; + ioat_chan->pending = 0; + ioat_chan->dmacount = 0; + ioat_chan->desccount = 0; + ioat_chan->watchdog_completion = 0; + ioat_chan->last_compl_desc_addr_hw = 0; + ioat_chan->watchdog_tcp_cookie = + ioat_chan->watchdog_last_tcp_cookie = 0; +} + +/** + * ioat_dma_get_next_descriptor - return the next available descriptor + * @ioat_chan: IOAT DMA channel handle + * + * Gets the next descriptor from the chain, and must be called with the + * channel's desc_lock held. Allocates more descriptors if the channel + * has run out. + */ +static struct ioat_desc_sw * +ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) +{ + struct ioat_desc_sw *new; + + if (!list_empty(&ioat_chan->free_desc)) { + new = to_ioat_desc(ioat_chan->free_desc.next); + list_del(&new->node); + } else { + /* try to get another desc */ + new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC); + if (!new) { + dev_err(&ioat_chan->device->pdev->dev, + "alloc failed\n"); + return NULL; + } + } + + prefetch(new->hw); + return new; +} + +static struct ioat_desc_sw * +ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) +{ + struct ioat_desc_sw *new; + + /* + * used.prev points to where to start processing + * used.next points to next free descriptor + * if used.prev == NULL, there are none waiting to be processed + * if used.next == used.prev.prev, there is only one free descriptor, + * and we need to use it to as a noop descriptor before + * linking in a new set of descriptors, since the device + * has probably already read the pointer to it + */ + if (ioat_chan->used_desc.prev && + ioat_chan->used_desc.next == ioat_chan->used_desc.prev->prev) { + + struct ioat_desc_sw *desc; + struct ioat_desc_sw *noop_desc; + int i; + + /* set up the noop descriptor */ + noop_desc = to_ioat_desc(ioat_chan->used_desc.next); + /* set size to non-zero value (channel returns error when size is 0) */ + noop_desc->hw->size = NULL_DESC_BUFFER_SIZE; + noop_desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL; + noop_desc->hw->src_addr = 0; + noop_desc->hw->dst_addr = 0; + + ioat_chan->used_desc.next = ioat_chan->used_desc.next->next; + ioat_chan->pending++; + ioat_chan->dmacount++; + + /* try to get a few more descriptors */ + for (i = 16; i; i--) { + desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC); + if (!desc) { + dev_err(&ioat_chan->device->pdev->dev, + "alloc failed\n"); + break; + } + list_add_tail(&desc->node, ioat_chan->used_desc.next); + + desc->hw->next + = to_ioat_desc(desc->node.next)->async_tx.phys; + to_ioat_desc(desc->node.prev)->hw->next + = desc->async_tx.phys; + ioat_chan->desccount++; + } + + ioat_chan->used_desc.next = noop_desc->node.next; + } + new = to_ioat_desc(ioat_chan->used_desc.next); + prefetch(new); + ioat_chan->used_desc.next = new->node.next; + + if (ioat_chan->used_desc.prev == NULL) + ioat_chan->used_desc.prev = &new->node; + + prefetch(new->hw); + return new; +} + +static struct ioat_desc_sw *ioat_dma_get_next_descriptor( + struct ioat_dma_chan *ioat_chan) +{ + if (!ioat_chan) + return NULL; + + switch (ioat_chan->device->version) { + case IOAT_VER_1_2: + return ioat1_dma_get_next_descriptor(ioat_chan); + case IOAT_VER_2_0: + case IOAT_VER_3_0: + return ioat2_dma_get_next_descriptor(ioat_chan); + } + return NULL; +} + +static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy( + struct dma_chan *chan, + dma_addr_t dma_dest, + dma_addr_t dma_src, + size_t len, + unsigned long flags) +{ + struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + struct ioat_desc_sw *new; + + spin_lock_bh(&ioat_chan->desc_lock); + new = ioat_dma_get_next_descriptor(ioat_chan); + spin_unlock_bh(&ioat_chan->desc_lock); + + if (new) { + new->len = len; + new->dst = dma_dest; + new->src = dma_src; + new->async_tx.flags = flags; + return &new->async_tx; + } else { + dev_err(&ioat_chan->device->pdev->dev, + "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n", + chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); + return NULL; + } +} + +static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy( + struct dma_chan *chan, + dma_addr_t dma_dest, + dma_addr_t dma_src, + size_t len, + unsigned long flags) +{ + struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + struct ioat_desc_sw *new; + + spin_lock_bh(&ioat_chan->desc_lock); + new = ioat2_dma_get_next_descriptor(ioat_chan); + + /* + * leave ioat_chan->desc_lock set in ioat 2 path + * it will get unlocked at end of tx_submit + */ + + if (new) { + new->len = len; + new->dst = dma_dest; + new->src = dma_src; + new->async_tx.flags = flags; + return &new->async_tx; + } else { + spin_unlock_bh(&ioat_chan->desc_lock); + dev_err(&ioat_chan->device->pdev->dev, + "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n", + chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); + return NULL; + } +} + +static void ioat_dma_cleanup_tasklet(unsigned long data) +{ + struct ioat_dma_chan *chan = (void *)data; + ioat_dma_memcpy_cleanup(chan); + writew(IOAT_CHANCTRL_INT_DISABLE, + chan->reg_base + IOAT_CHANCTRL_OFFSET); +} + +static void +ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc) +{ + if (!(desc->async_tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { + if (desc->async_tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) + pci_unmap_single(ioat_chan->device->pdev, + pci_unmap_addr(desc, dst), + pci_unmap_len(desc, len), + PCI_DMA_FROMDEVICE); + else + pci_unmap_page(ioat_chan->device->pdev, + pci_unmap_addr(desc, dst), + pci_unmap_len(desc, len), + PCI_DMA_FROMDEVICE); + } + + if (!(desc->async_tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { + if (desc->async_tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) + pci_unmap_single(ioat_chan->device->pdev, + pci_unmap_addr(desc, src), + pci_unmap_len(desc, len), + PCI_DMA_TODEVICE); + else + pci_unmap_page(ioat_chan->device->pdev, + pci_unmap_addr(desc, src), + pci_unmap_len(desc, len), + PCI_DMA_TODEVICE); + } +} + +/** + * ioat_dma_memcpy_cleanup - cleanup up finished descriptors + * @chan: ioat channel to be cleaned up + */ +static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) +{ + unsigned long phys_complete; + struct ioat_desc_sw *desc, *_desc; + dma_cookie_t cookie = 0; + unsigned long desc_phys; + struct ioat_desc_sw *latest_desc; + + prefetch(ioat_chan->completion_virt); + + if (!spin_trylock_bh(&ioat_chan->cleanup_lock)) + return; + + /* The completion writeback can happen at any time, + so reads by the driver need to be atomic operations + The descriptor physical addresses are limited to 32-bits + when the CPU can only do a 32-bit mov */ + +#if (BITS_PER_LONG == 64) + phys_complete = + ioat_chan->completion_virt->full + & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; +#else + phys_complete = + ioat_chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK; +#endif + + if ((ioat_chan->completion_virt->full + & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == + IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) { + dev_err(&ioat_chan->device->pdev->dev, + "Channel halted, chanerr = %x\n", + readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET)); + + /* TODO do something to salvage the situation */ + } + + if (phys_complete == ioat_chan->last_completion) { + spin_unlock_bh(&ioat_chan->cleanup_lock); + /* + * perhaps we're stuck so hard that the watchdog can't go off? + * try to catch it after 2 seconds + */ + if (ioat_chan->device->version != IOAT_VER_3_0) { + if (time_after(jiffies, + ioat_chan->last_completion_time + HZ*WATCHDOG_DELAY)) { + ioat_dma_chan_watchdog(&(ioat_chan->device->work.work)); + ioat_chan->last_completion_time = jiffies; + } + } + return; + } + ioat_chan->last_completion_time = jiffies; + + cookie = 0; + if (!spin_trylock_bh(&ioat_chan->desc_lock)) { + spin_unlock_bh(&ioat_chan->cleanup_lock); + return; + } + + switch (ioat_chan->device->version) { + case IOAT_VER_1_2: + list_for_each_entry_safe(desc, _desc, + &ioat_chan->used_desc, node) { + + /* + * Incoming DMA requests may use multiple descriptors, + * due to exceeding xfercap, perhaps. If so, only the + * last one will have a cookie, and require unmapping. + */ + if (desc->async_tx.cookie) { + cookie = desc->async_tx.cookie; + ioat_dma_unmap(ioat_chan, desc); + if (desc->async_tx.callback) { + desc->async_tx.callback(desc->async_tx.callback_param); + desc->async_tx.callback = NULL; + } + } + + if (desc->async_tx.phys != phys_complete) { + /* + * a completed entry, but not the last, so clean + * up if the client is done with the descriptor + */ + if (async_tx_test_ack(&desc->async_tx)) { + list_move_tail(&desc->node, + &ioat_chan->free_desc); + } else + desc->async_tx.cookie = 0; + } else { + /* + * last used desc. Do not remove, so we can + * append from it, but don't look at it next + * time, either + */ + desc->async_tx.cookie = 0; + + /* TODO check status bits? */ + break; + } + } + break; + case IOAT_VER_2_0: + case IOAT_VER_3_0: + /* has some other thread has already cleaned up? */ + if (ioat_chan->used_desc.prev == NULL) + break; + + /* work backwards to find latest finished desc */ + desc = to_ioat_desc(ioat_chan->used_desc.next); + latest_desc = NULL; + do { + desc = to_ioat_desc(desc->node.prev); + desc_phys = (unsigned long)desc->async_tx.phys + & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; + if (desc_phys == phys_complete) { + latest_desc = desc; + break; + } + } while (&desc->node != ioat_chan->used_desc.prev); + + if (latest_desc != NULL) { + + /* work forwards to clear finished descriptors */ + for (desc = to_ioat_desc(ioat_chan->used_desc.prev); + &desc->node != latest_desc->node.next && + &desc->node != ioat_chan->used_desc.next; + desc = to_ioat_desc(desc->node.next)) { + if (desc->async_tx.cookie) { + cookie = desc->async_tx.cookie; + desc->async_tx.cookie = 0; + ioat_dma_unmap(ioat_chan, desc); + if (desc->async_tx.callback) { + desc->async_tx.callback(desc->async_tx.callback_param); + desc->async_tx.callback = NULL; + } + } + } + + /* move used.prev up beyond those that are finished */ + if (&desc->node == ioat_chan->used_desc.next) + ioat_chan->used_desc.prev = NULL; + else + ioat_chan->used_desc.prev = &desc->node; + } + break; + } + + spin_unlock_bh(&ioat_chan->desc_lock); + + ioat_chan->last_completion = phys_complete; + if (cookie != 0) + ioat_chan->completed_cookie = cookie; + + spin_unlock_bh(&ioat_chan->cleanup_lock); +} + +/** + * ioat_dma_is_complete - poll the status of a IOAT DMA transaction + * @chan: IOAT DMA channel handle + * @cookie: DMA transaction identifier + * @done: if not %NULL, updated with last completed transaction + * @used: if not %NULL, updated with last used transaction + */ +static enum dma_status ioat_dma_is_complete(struct dma_chan *chan, + dma_cookie_t cookie, + dma_cookie_t *done, + dma_cookie_t *used) +{ + struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + dma_cookie_t last_used; + dma_cookie_t last_complete; + enum dma_status ret; + + last_used = chan->cookie; + last_complete = ioat_chan->completed_cookie; + ioat_chan->watchdog_tcp_cookie = cookie; + + if (done) + *done = last_complete; + if (used) + *used = last_used; + + ret = dma_async_is_complete(cookie, last_complete, last_used); + if (ret == DMA_SUCCESS) + return ret; + + ioat_dma_memcpy_cleanup(ioat_chan); + + last_used = chan->cookie; + last_complete = ioat_chan->completed_cookie; + + if (done) + *done = last_complete; + if (used) + *used = last_used; + + return dma_async_is_complete(cookie, last_complete, last_used); +} + +static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan) +{ + struct ioat_desc_sw *desc; + + spin_lock_bh(&ioat_chan->desc_lock); + + desc = ioat_dma_get_next_descriptor(ioat_chan); + + if (!desc) { + dev_err(&ioat_chan->device->pdev->dev, + "Unable to start null desc - get next desc failed\n"); + spin_unlock_bh(&ioat_chan->desc_lock); + return; + } + + desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL + | IOAT_DMA_DESCRIPTOR_CTL_INT_GN + | IOAT_DMA_DESCRIPTOR_CTL_CP_STS; + /* set size to non-zero value (channel returns error when size is 0) */ + desc->hw->size = NULL_DESC_BUFFER_SIZE; + desc->hw->src_addr = 0; + desc->hw->dst_addr = 0; + async_tx_ack(&desc->async_tx); + switch (ioat_chan->device->version) { + case IOAT_VER_1_2: + desc->hw->next = 0; + list_add_tail(&desc->node, &ioat_chan->used_desc); + + writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF, + ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); + writel(((u64) desc->async_tx.phys) >> 32, + ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); + + writeb(IOAT_CHANCMD_START, ioat_chan->reg_base + + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); + break; + case IOAT_VER_2_0: + case IOAT_VER_3_0: + writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF, + ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); + writel(((u64) desc->async_tx.phys) >> 32, + ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); + + ioat_chan->dmacount++; + __ioat2_dma_memcpy_issue_pending(ioat_chan); + break; + } + spin_unlock_bh(&ioat_chan->desc_lock); +} + +/* + * Perform a IOAT transaction to verify the HW works. + */ +#define IOAT_TEST_SIZE 2000 + +static void ioat_dma_test_callback(void *dma_async_param) +{ + struct completion *cmp = dma_async_param; + + complete(cmp); +} + +/** + * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. + * @device: device to be tested + */ +static int ioat_dma_self_test(struct ioatdma_device *device) +{ + int i; + u8 *src; + u8 *dest; + struct dma_chan *dma_chan; + struct dma_async_tx_descriptor *tx; + dma_addr_t dma_dest, dma_src; + dma_cookie_t cookie; + int err = 0; + struct completion cmp; + unsigned long tmo; + unsigned long flags; + + src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); + if (!src) + return -ENOMEM; + dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); + if (!dest) { + kfree(src); + return -ENOMEM; + } + + /* Fill in src buffer */ + for (i = 0; i < IOAT_TEST_SIZE; i++) + src[i] = (u8)i; + + /* Start copy, using first DMA channel */ + dma_chan = container_of(device->common.channels.next, + struct dma_chan, + device_node); + if (device->common.device_alloc_chan_resources(dma_chan) < 1) { + dev_err(&device->pdev->dev, + "selftest cannot allocate chan resource\n"); + err = -ENODEV; + goto out; + } + + dma_src = dma_map_single(dma_chan->device->dev, src, IOAT_TEST_SIZE, + DMA_TO_DEVICE); + dma_dest = dma_map_single(dma_chan->device->dev, dest, IOAT_TEST_SIZE, + DMA_FROM_DEVICE); + flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE; + tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src, + IOAT_TEST_SIZE, flags); + if (!tx) { + dev_err(&device->pdev->dev, + "Self-test prep failed, disabling\n"); + err = -ENODEV; + goto free_resources; + } + + async_tx_ack(tx); + init_completion(&cmp); + tx->callback = ioat_dma_test_callback; + tx->callback_param = &cmp; + cookie = tx->tx_submit(tx); + if (cookie < 0) { + dev_err(&device->pdev->dev, + "Self-test setup failed, disabling\n"); + err = -ENODEV; + goto free_resources; + } + device->common.device_issue_pending(dma_chan); + + tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); + + if (tmo == 0 || + device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL) + != DMA_SUCCESS) { + dev_err(&device->pdev->dev, + "Self-test copy timed out, disabling\n"); + err = -ENODEV; + goto free_resources; + } + if (memcmp(src, dest, IOAT_TEST_SIZE)) { + dev_err(&device->pdev->dev, + "Self-test copy failed compare, disabling\n"); + err = -ENODEV; + goto free_resources; + } + +free_resources: + device->common.device_free_chan_resources(dma_chan); +out: + kfree(src); + kfree(dest); + return err; +} + +static char ioat_interrupt_style[32] = "msix"; +module_param_string(ioat_interrupt_style, ioat_interrupt_style, + sizeof(ioat_interrupt_style), 0644); +MODULE_PARM_DESC(ioat_interrupt_style, + "set ioat interrupt style: msix (default), " + "msix-single-vector, msi, intx)"); + +/** + * ioat_dma_setup_interrupts - setup interrupt handler + * @device: ioat device + */ +static int ioat_dma_setup_interrupts(struct ioatdma_device *device) +{ + struct ioat_dma_chan *ioat_chan; + int err, i, j, msixcnt; + u8 intrctrl = 0; + + if (!strcmp(ioat_interrupt_style, "msix")) + goto msix; + if (!strcmp(ioat_interrupt_style, "msix-single-vector")) + goto msix_single_vector; + if (!strcmp(ioat_interrupt_style, "msi")) + goto msi; + if (!strcmp(ioat_interrupt_style, "intx")) + goto intx; + dev_err(&device->pdev->dev, "invalid ioat_interrupt_style %s\n", + ioat_interrupt_style); + goto err_no_irq; + +msix: + /* The number of MSI-X vectors should equal the number of channels */ + msixcnt = device->common.chancnt; + for (i = 0; i < msixcnt; i++) + device->msix_entries[i].entry = i; + + err = pci_enable_msix(device->pdev, device->msix_entries, msixcnt); + if (err < 0) + goto msi; + if (err > 0) + goto msix_single_vector; + + for (i = 0; i < msixcnt; i++) { + ioat_chan = ioat_lookup_chan_by_index(device, i); + err = request_irq(device->msix_entries[i].vector, + ioat_dma_do_interrupt_msix, + 0, "ioat-msix", ioat_chan); + if (err) { + for (j = 0; j < i; j++) { + ioat_chan = + ioat_lookup_chan_by_index(device, j); + free_irq(device->msix_entries[j].vector, + ioat_chan); + } + goto msix_single_vector; + } + } + intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; + device->irq_mode = msix_multi_vector; + goto done; + +msix_single_vector: + device->msix_entries[0].entry = 0; + err = pci_enable_msix(device->pdev, device->msix_entries, 1); + if (err) + goto msi; + + err = request_irq(device->msix_entries[0].vector, ioat_dma_do_interrupt, + 0, "ioat-msix", device); + if (err) { + pci_disable_msix(device->pdev); + goto msi; + } + device->irq_mode = msix_single_vector; + goto done; + +msi: + err = pci_enable_msi(device->pdev); + if (err) + goto intx; + + err = request_irq(device->pdev->irq, ioat_dma_do_interrupt, + 0, "ioat-msi", device); + if (err) { + pci_disable_msi(device->pdev); + goto intx; + } + /* + * CB 1.2 devices need a bit set in configuration space to enable MSI + */ + if (device->version == IOAT_VER_1_2) { + u32 dmactrl; + pci_read_config_dword(device->pdev, + IOAT_PCI_DMACTRL_OFFSET, &dmactrl); + dmactrl |= IOAT_PCI_DMACTRL_MSI_EN; + pci_write_config_dword(device->pdev, + IOAT_PCI_DMACTRL_OFFSET, dmactrl); + } + device->irq_mode = msi; + goto done; + +intx: + err = request_irq(device->pdev->irq, ioat_dma_do_interrupt, + IRQF_SHARED, "ioat-intx", device); + if (err) + goto err_no_irq; + device->irq_mode = intx; + +done: + intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; + writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET); + return 0; + +err_no_irq: + /* Disable all interrupt generation */ + writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); + dev_err(&device->pdev->dev, "no usable interrupts\n"); + device->irq_mode = none; + return -1; +} + +/** + * ioat_dma_remove_interrupts - remove whatever interrupts were set + * @device: ioat device + */ +static void ioat_dma_remove_interrupts(struct ioatdma_device *device) +{ + struct ioat_dma_chan *ioat_chan; + int i; + + /* Disable all interrupt generation */ + writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); + + switch (device->irq_mode) { + case msix_multi_vector: + for (i = 0; i < device->common.chancnt; i++) { + ioat_chan = ioat_lookup_chan_by_index(device, i); + free_irq(device->msix_entries[i].vector, ioat_chan); + } + pci_disable_msix(device->pdev); + break; + case msix_single_vector: + free_irq(device->msix_entries[0].vector, device); + pci_disable_msix(device->pdev); + break; + case msi: + free_irq(device->pdev->irq, device); + pci_disable_msi(device->pdev); + break; + case intx: + free_irq(device->pdev->irq, device); + break; + case none: + dev_warn(&device->pdev->dev, + "call to %s without interrupts setup\n", __func__); + } + device->irq_mode = none; +} + +struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, + void __iomem *iobase) +{ + int err; + struct ioatdma_device *device; + + device = kzalloc(sizeof(*device), GFP_KERNEL); + if (!device) { + err = -ENOMEM; + goto err_kzalloc; + } + device->pdev = pdev; + device->reg_base = iobase; + device->version = readb(device->reg_base + IOAT_VER_OFFSET); + + /* DMA coherent memory pool for DMA descriptor allocations */ + device->dma_pool = pci_pool_create("dma_desc_pool", pdev, + sizeof(struct ioat_dma_descriptor), + 64, 0); + if (!device->dma_pool) { + err = -ENOMEM; + goto err_dma_pool; + } + + device->completion_pool = pci_pool_create("completion_pool", pdev, + sizeof(u64), SMP_CACHE_BYTES, + SMP_CACHE_BYTES); + if (!device->completion_pool) { + err = -ENOMEM; + goto err_completion_pool; + } + + INIT_LIST_HEAD(&device->common.channels); + ioat_dma_enumerate_channels(device); + + device->common.device_alloc_chan_resources = + ioat_dma_alloc_chan_resources; + device->common.device_free_chan_resources = + ioat_dma_free_chan_resources; + device->common.dev = &pdev->dev; + + dma_cap_set(DMA_MEMCPY, device->common.cap_mask); + device->common.device_is_tx_complete = ioat_dma_is_complete; + switch (device->version) { + case IOAT_VER_1_2: + device->common.device_prep_dma_memcpy = ioat1_dma_prep_memcpy; + device->common.device_issue_pending = + ioat1_dma_memcpy_issue_pending; + break; + case IOAT_VER_2_0: + case IOAT_VER_3_0: + device->common.device_prep_dma_memcpy = ioat2_dma_prep_memcpy; + device->common.device_issue_pending = + ioat2_dma_memcpy_issue_pending; + break; + } + + dev_err(&device->pdev->dev, + "Intel(R) I/OAT DMA Engine found," + " %d channels, device version 0x%02x, driver version %s\n", + device->common.chancnt, device->version, IOAT_DMA_VERSION); + + if (!device->common.chancnt) { + dev_err(&device->pdev->dev, + "Intel(R) I/OAT DMA Engine problem found: " + "zero channels detected\n"); + goto err_setup_interrupts; + } + + err = ioat_dma_setup_interrupts(device); + if (err) + goto err_setup_interrupts; + + err = ioat_dma_self_test(device); + if (err) + goto err_self_test; + + ioat_set_tcp_copy_break(device); + + dma_async_device_register(&device->common); + + if (device->version != IOAT_VER_3_0) { + INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog); + schedule_delayed_work(&device->work, + WATCHDOG_DELAY); + } + + return device; + +err_self_test: + ioat_dma_remove_interrupts(device); +err_setup_interrupts: + pci_pool_destroy(device->completion_pool); +err_completion_pool: + pci_pool_destroy(device->dma_pool); +err_dma_pool: + kfree(device); +err_kzalloc: + dev_err(&pdev->dev, + "Intel(R) I/OAT DMA Engine initialization failed\n"); + return NULL; +} + +void ioat_dma_remove(struct ioatdma_device *device) +{ + struct dma_chan *chan, *_chan; + struct ioat_dma_chan *ioat_chan; + + if (device->version != IOAT_VER_3_0) + cancel_delayed_work(&device->work); + + ioat_dma_remove_interrupts(device); + + dma_async_device_unregister(&device->common); + + pci_pool_destroy(device->dma_pool); + pci_pool_destroy(device->completion_pool); + + iounmap(device->reg_base); + pci_release_regions(device->pdev); + pci_disable_device(device->pdev); + + list_for_each_entry_safe(chan, _chan, + &device->common.channels, device_node) { + ioat_chan = to_ioat_chan(chan); + list_del(&chan->device_node); + kfree(ioat_chan); + } + kfree(device); +} + diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h new file mode 100644 index 0000000..e80e787 --- /dev/null +++ b/drivers/dma/ioat/dma.h @@ -0,0 +1,165 @@ +/* + * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * The full GNU General Public License is included in this distribution in the + * file called COPYING. + */ +#ifndef IOATDMA_H +#define IOATDMA_H + +#include +#include "hw.h" +#include +#include +#include +#include +#include + +#define IOAT_DMA_VERSION "3.64" + +enum ioat_interrupt { + none = 0, + msix_multi_vector = 1, + msix_single_vector = 2, + msi = 3, + intx = 4, +}; + +#define IOAT_LOW_COMPLETION_MASK 0xffffffc0 +#define IOAT_DMA_DCA_ANY_CPU ~0 +#define IOAT_WATCHDOG_PERIOD (2 * HZ) + + +/** + * struct ioatdma_device - internal representation of a IOAT device + * @pdev: PCI-Express device + * @reg_base: MMIO register space base address + * @dma_pool: for allocating DMA descriptors + * @common: embedded struct dma_device + * @version: version of ioatdma device + * @irq_mode: which style irq to use + * @msix_entries: irq handlers + * @idx: per channel data + */ + +struct ioatdma_device { + struct pci_dev *pdev; + void __iomem *reg_base; + struct pci_pool *dma_pool; + struct pci_pool *completion_pool; + struct dma_device common; + u8 version; + enum ioat_interrupt irq_mode; + struct delayed_work work; + struct msix_entry msix_entries[4]; + struct ioat_dma_chan *idx[4]; +}; + +/** + * struct ioat_dma_chan - internal representation of a DMA channel + */ +struct ioat_dma_chan { + + void __iomem *reg_base; + + dma_cookie_t completed_cookie; + unsigned long last_completion; + unsigned long last_completion_time; + + size_t xfercap; /* XFERCAP register value expanded out */ + + spinlock_t cleanup_lock; + spinlock_t desc_lock; + struct list_head free_desc; + struct list_head used_desc; + unsigned long watchdog_completion; + int watchdog_tcp_cookie; + u32 watchdog_last_tcp_cookie; + struct delayed_work work; + + int pending; + int dmacount; + int desccount; + + struct ioatdma_device *device; + struct dma_chan common; + + dma_addr_t completion_addr; + union { + u64 full; /* HW completion writeback */ + struct { + u32 low; + u32 high; + }; + } *completion_virt; + unsigned long last_compl_desc_addr_hw; + struct tasklet_struct cleanup_task; +}; + +/* wrapper around hardware descriptor format + additional software fields */ + +/** + * struct ioat_desc_sw - wrapper around hardware descriptor + * @hw: hardware DMA descriptor + * @node: this descriptor will either be on the free list, + * or attached to a transaction list (async_tx.tx_list) + * @tx_cnt: number of descriptors required to complete the transaction + * @async_tx: the generic software descriptor for all engines + */ +struct ioat_desc_sw { + struct ioat_dma_descriptor *hw; + struct list_head node; + int tx_cnt; + size_t len; + dma_addr_t src; + dma_addr_t dst; + struct dma_async_tx_descriptor async_tx; +}; + +static inline void ioat_set_tcp_copy_break(struct ioatdma_device *dev) +{ + #ifdef CONFIG_NET_DMA + switch (dev->version) { + case IOAT_VER_1_2: + sysctl_tcp_dma_copybreak = 4096; + break; + case IOAT_VER_2_0: + sysctl_tcp_dma_copybreak = 2048; + break; + case IOAT_VER_3_0: + sysctl_tcp_dma_copybreak = 262144; + break; + } + #endif +} + +#if defined(CONFIG_INTEL_IOATDMA) || defined(CONFIG_INTEL_IOATDMA_MODULE) +struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, + void __iomem *iobase); +void ioat_dma_remove(struct ioatdma_device *device); +struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); +struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); +struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase); +#else +#define ioat_dma_probe(pdev, iobase) NULL +#define ioat_dma_remove(device) do { } while (0) +#define ioat_dca_init(pdev, iobase) NULL +#define ioat2_dca_init(pdev, iobase) NULL +#define ioat3_dca_init(pdev, iobase) NULL +#endif + +#endif /* IOATDMA_H */ diff --git a/drivers/dma/ioat/hw.h b/drivers/dma/ioat/hw.h new file mode 100644 index 0000000..afa57ee --- /dev/null +++ b/drivers/dma/ioat/hw.h @@ -0,0 +1,70 @@ +/* + * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * The full GNU General Public License is included in this distribution in the + * file called COPYING. + */ +#ifndef _IOAT_HW_H_ +#define _IOAT_HW_H_ + +/* PCI Configuration Space Values */ +#define IOAT_PCI_VID 0x8086 + +/* CB device ID's */ +#define IOAT_PCI_DID_5000 0x1A38 +#define IOAT_PCI_DID_CNB 0x360B +#define IOAT_PCI_DID_SCNB 0x65FF +#define IOAT_PCI_DID_SNB 0x402F + +#define IOAT_PCI_RID 0x00 +#define IOAT_PCI_SVID 0x8086 +#define IOAT_PCI_SID 0x8086 +#define IOAT_VER_1_2 0x12 /* Version 1.2 */ +#define IOAT_VER_2_0 0x20 /* Version 2.0 */ +#define IOAT_VER_3_0 0x30 /* Version 3.0 */ + +struct ioat_dma_descriptor { + uint32_t size; + uint32_t ctl; + uint64_t src_addr; + uint64_t dst_addr; + uint64_t next; + uint64_t rsv1; + uint64_t rsv2; + uint64_t user1; + uint64_t user2; +}; + +#define IOAT_DMA_DESCRIPTOR_CTL_INT_GN 0x00000001 +#define IOAT_DMA_DESCRIPTOR_CTL_SRC_SN 0x00000002 +#define IOAT_DMA_DESCRIPTOR_CTL_DST_SN 0x00000004 +#define IOAT_DMA_DESCRIPTOR_CTL_CP_STS 0x00000008 +#define IOAT_DMA_DESCRIPTOR_CTL_FRAME 0x00000010 +#define IOAT_DMA_DESCRIPTOR_NUL 0x00000020 +#define IOAT_DMA_DESCRIPTOR_CTL_SP_BRK 0x00000040 +#define IOAT_DMA_DESCRIPTOR_CTL_DP_BRK 0x00000080 +#define IOAT_DMA_DESCRIPTOR_CTL_BNDL 0x00000100 +#define IOAT_DMA_DESCRIPTOR_CTL_DCA 0x00000200 +#define IOAT_DMA_DESCRIPTOR_CTL_BUFHINT 0x00000400 + +#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_CONTEXT 0xFF000000 +#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_DMA 0x00000000 + +#define IOAT_DMA_DESCRIPTOR_CTL_CONTEXT_DCA 0x00000001 +#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_MASK 0xFF000000 + +#endif diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c new file mode 100644 index 0000000..d7948bf --- /dev/null +++ b/drivers/dma/ioat/pci.c @@ -0,0 +1,202 @@ +/* + * Intel I/OAT DMA Linux driver + * Copyright(c) 2007 - 2009 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + */ + +/* + * This driver supports an Intel I/OAT DMA engine, which does asynchronous + * copy operations. + */ + +#include +#include +#include +#include +#include +#include "dma.h" +#include "registers.h" +#include "hw.h" + +MODULE_VERSION(IOAT_DMA_VERSION); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Intel Corporation"); + +static struct pci_device_id ioat_pci_tbl[] = { + /* I/OAT v1 platforms */ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_CNB) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SCNB) }, + { PCI_DEVICE(PCI_VENDOR_ID_UNISYS, PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR) }, + + /* I/OAT v2 platforms */ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB) }, + + /* I/OAT v3 platforms */ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, + { 0, } +}; + +struct ioat_device { + struct pci_dev *pdev; + void __iomem *iobase; + struct ioatdma_device *dma; + struct dca_provider *dca; +}; + +static int __devinit ioat_probe(struct pci_dev *pdev, + const struct pci_device_id *id); +static void __devexit ioat_remove(struct pci_dev *pdev); + +static int ioat_dca_enabled = 1; +module_param(ioat_dca_enabled, int, 0644); +MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); + +static struct pci_driver ioat_pci_driver = { + .name = "ioatdma", + .id_table = ioat_pci_tbl, + .probe = ioat_probe, + .remove = __devexit_p(ioat_remove), +}; + +static int __devinit ioat_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + void __iomem *iobase; + struct ioat_device *device; + unsigned long mmio_start, mmio_len; + int err; + + err = pci_enable_device(pdev); + if (err) + goto err_enable_device; + + err = pci_request_regions(pdev, ioat_pci_driver.name); + if (err) + goto err_request_regions; + + err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); + if (err) + err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + if (err) + goto err_set_dma_mask; + + err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); + if (err) + err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + if (err) + goto err_set_dma_mask; + + mmio_start = pci_resource_start(pdev, 0); + mmio_len = pci_resource_len(pdev, 0); + iobase = ioremap(mmio_start, mmio_len); + if (!iobase) { + err = -ENOMEM; + goto err_ioremap; + } + + device = kzalloc(sizeof(*device), GFP_KERNEL); + if (!device) { + err = -ENOMEM; + goto err_kzalloc; + } + device->pdev = pdev; + pci_set_drvdata(pdev, device); + device->iobase = iobase; + + pci_set_master(pdev); + + switch (readb(iobase + IOAT_VER_OFFSET)) { + case IOAT_VER_1_2: + device->dma = ioat_dma_probe(pdev, iobase); + if (device->dma && ioat_dca_enabled) + device->dca = ioat_dca_init(pdev, iobase); + break; + case IOAT_VER_2_0: + device->dma = ioat_dma_probe(pdev, iobase); + if (device->dma && ioat_dca_enabled) + device->dca = ioat2_dca_init(pdev, iobase); + break; + case IOAT_VER_3_0: + device->dma = ioat_dma_probe(pdev, iobase); + if (device->dma && ioat_dca_enabled) + device->dca = ioat3_dca_init(pdev, iobase); + break; + default: + err = -ENODEV; + break; + } + if (!device->dma) + err = -ENODEV; + + if (err) + goto err_version; + + return 0; + +err_version: + kfree(device); +err_kzalloc: + iounmap(iobase); +err_ioremap: +err_set_dma_mask: + pci_release_regions(pdev); + pci_disable_device(pdev); +err_request_regions: +err_enable_device: + return err; +} + +static void __devexit ioat_remove(struct pci_dev *pdev) +{ + struct ioat_device *device = pci_get_drvdata(pdev); + + dev_err(&pdev->dev, "Removing dma and dca services\n"); + if (device->dca) { + unregister_dca_provider(device->dca); + free_dca_provider(device->dca); + device->dca = NULL; + } + + if (device->dma) { + ioat_dma_remove(device->dma); + device->dma = NULL; + } + + kfree(device); +} + +static int __init ioat_init_module(void) +{ + return pci_register_driver(&ioat_pci_driver); +} +module_init(ioat_init_module); + +static void __exit ioat_exit_module(void) +{ + pci_unregister_driver(&ioat_pci_driver); +} +module_exit(ioat_exit_module); diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h new file mode 100644 index 0000000..49bc277 --- /dev/null +++ b/drivers/dma/ioat/registers.h @@ -0,0 +1,226 @@ +/* + * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * The full GNU General Public License is included in this distribution in the + * file called COPYING. + */ +#ifndef _IOAT_REGISTERS_H_ +#define _IOAT_REGISTERS_H_ + +#define IOAT_PCI_DMACTRL_OFFSET 0x48 +#define IOAT_PCI_DMACTRL_DMA_EN 0x00000001 +#define IOAT_PCI_DMACTRL_MSI_EN 0x00000002 + +#define IOAT_PCI_DEVICE_ID_OFFSET 0x02 +#define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148 +#define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184 + +/* MMIO Device Registers */ +#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */ + +#define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */ +#define IOAT_XFERCAP_4KB 12 +#define IOAT_XFERCAP_8KB 13 +#define IOAT_XFERCAP_16KB 14 +#define IOAT_XFERCAP_32KB 15 +#define IOAT_XFERCAP_32GB 0 + +#define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */ +#define IOAT_GENCTRL_DEBUG_EN 0x01 + +#define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */ +#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */ +#define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */ +#define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */ +#define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */ + +#define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */ + +#define IOAT_VER_OFFSET 0x08 /* 8-bit */ +#define IOAT_VER_MAJOR_MASK 0xF0 +#define IOAT_VER_MINOR_MASK 0x0F +#define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4) +#define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK) + +#define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */ + +#define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */ +#define IOAT_INTRDELAY_INT_DELAY_MASK 0x3FFF /* Interrupt Delay Time */ +#define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */ + +#define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ +#define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001 + +#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ + +/* DMA Channel Registers */ +#define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */ +#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 +#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 +#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 +#define IOAT_CHANCTRL_ERR_INT_EN 0x0010 +#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 +#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 +#define IOAT_CHANCTRL_INT_DISABLE 0x0001 + +#define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */ +#define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ +#define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ + + +#define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */ +#define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ +#define IOAT_CHANSTS_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ + ? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET) +#define IOAT1_CHANSTS_OFFSET_LOW 0x04 +#define IOAT2_CHANSTS_OFFSET_LOW 0x08 +#define IOAT_CHANSTS_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ + ? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW) +#define IOAT1_CHANSTS_OFFSET_HIGH 0x08 +#define IOAT2_CHANSTS_OFFSET_HIGH 0x0C +#define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ + ? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH) +#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR ~0x3F +#define IOAT_CHANSTS_SOFT_ERR 0x0000000000000010 +#define IOAT_CHANSTS_UNAFFILIATED_ERR 0x0000000000000008 +#define IOAT_CHANSTS_DMA_TRANSFER_STATUS 0x0000000000000007 +#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE 0x0 +#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE 0x1 +#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_SUSPENDED 0x2 +#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED 0x3 + + + +#define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */ + +#define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */ +#define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000 +#define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */ + +/* CB DCA Memory Space Registers */ +#define IOAT_DCAOFFSET_OFFSET 0x14 +/* CB_BAR + IOAT_DCAOFFSET value */ +#define IOAT_DCA_VER_OFFSET 0x00 +#define IOAT_DCA_VER_MAJOR_MASK 0xF0 +#define IOAT_DCA_VER_MINOR_MASK 0x0F + +#define IOAT_DCA_COMP_OFFSET 0x02 +#define IOAT_DCA_COMP_V1 0x1 + +#define IOAT_FSB_CAPABILITY_OFFSET 0x04 +#define IOAT_FSB_CAPABILITY_PREFETCH 0x1 + +#define IOAT_PCI_CAPABILITY_OFFSET 0x06 +#define IOAT_PCI_CAPABILITY_MEMWR 0x1 + +#define IOAT_FSB_CAP_ENABLE_OFFSET 0x08 +#define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1 + +#define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A +#define IOAT_PCI_CAP_ENABLE_MEMWR 0x1 + +#define IOAT_APICID_TAG_MAP_OFFSET 0x0C +#define IOAT_APICID_TAG_MAP_TAG0 0x0000000F +#define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0 +#define IOAT_APICID_TAG_MAP_TAG1 0x000000F0 +#define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4 +#define IOAT_APICID_TAG_MAP_TAG2 0x00000F00 +#define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8 +#define IOAT_APICID_TAG_MAP_TAG3 0x0000F000 +#define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12 +#define IOAT_APICID_TAG_MAP_TAG4 0x000F0000 +#define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16 +#define IOAT_APICID_TAG_CB2_VALID 0x8080808080 + +#define IOAT_DCA_GREQID_OFFSET 0x10 +#define IOAT_DCA_GREQID_SIZE 0x04 +#define IOAT_DCA_GREQID_MASK 0xFFFF +#define IOAT_DCA_GREQID_IGNOREFUN 0x10000000 +#define IOAT_DCA_GREQID_VALID 0x20000000 +#define IOAT_DCA_GREQID_LASTID 0x80000000 + +#define IOAT3_CSI_CAPABILITY_OFFSET 0x08 +#define IOAT3_CSI_CAPABILITY_PREFETCH 0x1 + +#define IOAT3_PCI_CAPABILITY_OFFSET 0x0A +#define IOAT3_PCI_CAPABILITY_MEMWR 0x1 + +#define IOAT3_CSI_CONTROL_OFFSET 0x0C +#define IOAT3_CSI_CONTROL_PREFETCH 0x1 + +#define IOAT3_PCI_CONTROL_OFFSET 0x0E +#define IOAT3_PCI_CONTROL_MEMWR 0x1 + +#define IOAT3_APICID_TAG_MAP_OFFSET 0x10 +#define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10 +#define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14 + +#define IOAT3_DCA_GREQID_OFFSET 0x02 + +#define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */ +#define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */ +#define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ + ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET) +#define IOAT1_CHAINADDR_OFFSET_LOW 0x0C +#define IOAT2_CHAINADDR_OFFSET_LOW 0x10 +#define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ + ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW) +#define IOAT1_CHAINADDR_OFFSET_HIGH 0x10 +#define IOAT2_CHAINADDR_OFFSET_HIGH 0x14 +#define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ + ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH) + +#define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */ +#define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */ +#define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ + ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET) +#define IOAT_CHANCMD_RESET 0x20 +#define IOAT_CHANCMD_RESUME 0x10 +#define IOAT_CHANCMD_ABORT 0x08 +#define IOAT_CHANCMD_SUSPEND 0x04 +#define IOAT_CHANCMD_APPEND 0x02 +#define IOAT_CHANCMD_START 0x01 + +#define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */ +#define IOAT_CHANCMP_OFFSET_LOW 0x18 +#define IOAT_CHANCMP_OFFSET_HIGH 0x1C + +#define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */ +#define IOAT_CDAR_OFFSET_LOW 0x20 +#define IOAT_CDAR_OFFSET_HIGH 0x24 + +#define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */ +#define IOAT_CHANERR_DMA_TRANSFER_SRC_ADDR_ERR 0x0001 +#define IOAT_CHANERR_DMA_TRANSFER_DEST_ADDR_ERR 0x0002 +#define IOAT_CHANERR_NEXT_DESCRIPTOR_ADDR_ERR 0x0004 +#define IOAT_CHANERR_NEXT_DESCRIPTOR_ALIGNMENT_ERR 0x0008 +#define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010 +#define IOAT_CHANERR_CHANCMD_ERR 0x0020 +#define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040 +#define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080 +#define IOAT_CHANERR_READ_DATA_ERR 0x0100 +#define IOAT_CHANERR_WRITE_DATA_ERR 0x0200 +#define IOAT_CHANERR_DESCRIPTOR_CONTROL_ERR 0x0400 +#define IOAT_CHANERR_DESCRIPTOR_LENGTH_ERR 0x0800 +#define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000 +#define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000 +#define IOAT_CHANERR_SOFT_ERR 0x4000 +#define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000 + +#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ + +#endif /* _IOAT_REGISTERS_H_ */ diff --git a/drivers/dma/ioat_dca.c b/drivers/dma/ioat_dca.c deleted file mode 100644 index c012a1e..0000000 --- a/drivers/dma/ioat_dca.c +++ /dev/null @@ -1,681 +0,0 @@ -/* - * Intel I/OAT DMA Linux driver - * Copyright(c) 2007 - 2009 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - */ - -#include -#include -#include -#include -#include - -/* either a kernel change is needed, or we need something like this in kernel */ -#ifndef CONFIG_SMP -#include -#undef cpu_physical_id -#define cpu_physical_id(cpu) (cpuid_ebx(1) >> 24) -#endif - -#include "ioatdma.h" -#include "ioatdma_registers.h" - -/* - * Bit 7 of a tag map entry is the "valid" bit, if it is set then bits 0:6 - * contain the bit number of the APIC ID to map into the DCA tag. If the valid - * bit is not set, then the value must be 0 or 1 and defines the bit in the tag. - */ -#define DCA_TAG_MAP_VALID 0x80 - -#define DCA3_TAG_MAP_BIT_TO_INV 0x80 -#define DCA3_TAG_MAP_BIT_TO_SEL 0x40 -#define DCA3_TAG_MAP_LITERAL_VAL 0x1 - -#define DCA_TAG_MAP_MASK 0xDF - -/* expected tag map bytes for I/OAT ver.2 */ -#define DCA2_TAG_MAP_BYTE0 0x80 -#define DCA2_TAG_MAP_BYTE1 0x0 -#define DCA2_TAG_MAP_BYTE2 0x81 -#define DCA2_TAG_MAP_BYTE3 0x82 -#define DCA2_TAG_MAP_BYTE4 0x82 - -/* verify if tag map matches expected values */ -static inline int dca2_tag_map_valid(u8 *tag_map) -{ - return ((tag_map[0] == DCA2_TAG_MAP_BYTE0) && - (tag_map[1] == DCA2_TAG_MAP_BYTE1) && - (tag_map[2] == DCA2_TAG_MAP_BYTE2) && - (tag_map[3] == DCA2_TAG_MAP_BYTE3) && - (tag_map[4] == DCA2_TAG_MAP_BYTE4)); -} - -/* - * "Legacy" DCA systems do not implement the DCA register set in the - * I/OAT device. Software needs direct support for their tag mappings. - */ - -#define APICID_BIT(x) (DCA_TAG_MAP_VALID | (x)) -#define IOAT_TAG_MAP_LEN 8 - -static u8 ioat_tag_map_BNB[IOAT_TAG_MAP_LEN] = { - 1, APICID_BIT(1), APICID_BIT(2), APICID_BIT(2), }; -static u8 ioat_tag_map_SCNB[IOAT_TAG_MAP_LEN] = { - 1, APICID_BIT(1), APICID_BIT(2), APICID_BIT(2), }; -static u8 ioat_tag_map_CNB[IOAT_TAG_MAP_LEN] = { - 1, APICID_BIT(1), APICID_BIT(3), APICID_BIT(4), APICID_BIT(2), }; -static u8 ioat_tag_map_UNISYS[IOAT_TAG_MAP_LEN] = { 0 }; - -/* pack PCI B/D/F into a u16 */ -static inline u16 dcaid_from_pcidev(struct pci_dev *pci) -{ - return (pci->bus->number << 8) | pci->devfn; -} - -static int dca_enabled_in_bios(struct pci_dev *pdev) -{ - /* CPUID level 9 returns DCA configuration */ - /* Bit 0 indicates DCA enabled by the BIOS */ - unsigned long cpuid_level_9; - int res; - - cpuid_level_9 = cpuid_eax(9); - res = test_bit(0, &cpuid_level_9); - if (!res) - dev_err(&pdev->dev, "DCA is disabled in BIOS\n"); - - return res; -} - -static int system_has_dca_enabled(struct pci_dev *pdev) -{ - if (boot_cpu_has(X86_FEATURE_DCA)) - return dca_enabled_in_bios(pdev); - - dev_err(&pdev->dev, "boot cpu doesn't have X86_FEATURE_DCA\n"); - return 0; -} - -struct ioat_dca_slot { - struct pci_dev *pdev; /* requester device */ - u16 rid; /* requester id, as used by IOAT */ -}; - -#define IOAT_DCA_MAX_REQ 6 -#define IOAT3_DCA_MAX_REQ 2 - -struct ioat_dca_priv { - void __iomem *iobase; - void __iomem *dca_base; - int max_requesters; - int requester_count; - u8 tag_map[IOAT_TAG_MAP_LEN]; - struct ioat_dca_slot req_slots[0]; -}; - -/* 5000 series chipset DCA Port Requester ID Table Entry Format - * [15:8] PCI-Express Bus Number - * [7:3] PCI-Express Device Number - * [2:0] PCI-Express Function Number - * - * 5000 series chipset DCA control register format - * [7:1] Reserved (0) - * [0] Ignore Function Number - */ - -static int ioat_dca_add_requester(struct dca_provider *dca, struct device *dev) -{ - struct ioat_dca_priv *ioatdca = dca_priv(dca); - struct pci_dev *pdev; - int i; - u16 id; - - /* This implementation only supports PCI-Express */ - if (dev->bus != &pci_bus_type) - return -ENODEV; - pdev = to_pci_dev(dev); - id = dcaid_from_pcidev(pdev); - - if (ioatdca->requester_count == ioatdca->max_requesters) - return -ENODEV; - - for (i = 0; i < ioatdca->max_requesters; i++) { - if (ioatdca->req_slots[i].pdev == NULL) { - /* found an empty slot */ - ioatdca->requester_count++; - ioatdca->req_slots[i].pdev = pdev; - ioatdca->req_slots[i].rid = id; - writew(id, ioatdca->dca_base + (i * 4)); - /* make sure the ignore function bit is off */ - writeb(0, ioatdca->dca_base + (i * 4) + 2); - return i; - } - } - /* Error, ioatdma->requester_count is out of whack */ - return -EFAULT; -} - -static int ioat_dca_remove_requester(struct dca_provider *dca, - struct device *dev) -{ - struct ioat_dca_priv *ioatdca = dca_priv(dca); - struct pci_dev *pdev; - int i; - - /* This implementation only supports PCI-Express */ - if (dev->bus != &pci_bus_type) - return -ENODEV; - pdev = to_pci_dev(dev); - - for (i = 0; i < ioatdca->max_requesters; i++) { - if (ioatdca->req_slots[i].pdev == pdev) { - writew(0, ioatdca->dca_base + (i * 4)); - ioatdca->req_slots[i].pdev = NULL; - ioatdca->req_slots[i].rid = 0; - ioatdca->requester_count--; - return i; - } - } - return -ENODEV; -} - -static u8 ioat_dca_get_tag(struct dca_provider *dca, - struct device *dev, - int cpu) -{ - struct ioat_dca_priv *ioatdca = dca_priv(dca); - int i, apic_id, bit, value; - u8 entry, tag; - - tag = 0; - apic_id = cpu_physical_id(cpu); - - for (i = 0; i < IOAT_TAG_MAP_LEN; i++) { - entry = ioatdca->tag_map[i]; - if (entry & DCA_TAG_MAP_VALID) { - bit = entry & ~DCA_TAG_MAP_VALID; - value = (apic_id & (1 << bit)) ? 1 : 0; - } else { - value = entry ? 1 : 0; - } - tag |= (value << i); - } - return tag; -} - -static int ioat_dca_dev_managed(struct dca_provider *dca, - struct device *dev) -{ - struct ioat_dca_priv *ioatdca = dca_priv(dca); - struct pci_dev *pdev; - int i; - - pdev = to_pci_dev(dev); - for (i = 0; i < ioatdca->max_requesters; i++) { - if (ioatdca->req_slots[i].pdev == pdev) - return 1; - } - return 0; -} - -static struct dca_ops ioat_dca_ops = { - .add_requester = ioat_dca_add_requester, - .remove_requester = ioat_dca_remove_requester, - .get_tag = ioat_dca_get_tag, - .dev_managed = ioat_dca_dev_managed, -}; - - -struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase) -{ - struct dca_provider *dca; - struct ioat_dca_priv *ioatdca; - u8 *tag_map = NULL; - int i; - int err; - u8 version; - u8 max_requesters; - - if (!system_has_dca_enabled(pdev)) - return NULL; - - /* I/OAT v1 systems must have a known tag_map to support DCA */ - switch (pdev->vendor) { - case PCI_VENDOR_ID_INTEL: - switch (pdev->device) { - case PCI_DEVICE_ID_INTEL_IOAT: - tag_map = ioat_tag_map_BNB; - break; - case PCI_DEVICE_ID_INTEL_IOAT_CNB: - tag_map = ioat_tag_map_CNB; - break; - case PCI_DEVICE_ID_INTEL_IOAT_SCNB: - tag_map = ioat_tag_map_SCNB; - break; - } - break; - case PCI_VENDOR_ID_UNISYS: - switch (pdev->device) { - case PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR: - tag_map = ioat_tag_map_UNISYS; - break; - } - break; - } - if (tag_map == NULL) - return NULL; - - version = readb(iobase + IOAT_VER_OFFSET); - if (version == IOAT_VER_3_0) - max_requesters = IOAT3_DCA_MAX_REQ; - else - max_requesters = IOAT_DCA_MAX_REQ; - - dca = alloc_dca_provider(&ioat_dca_ops, - sizeof(*ioatdca) + - (sizeof(struct ioat_dca_slot) * max_requesters)); - if (!dca) - return NULL; - - ioatdca = dca_priv(dca); - ioatdca->max_requesters = max_requesters; - ioatdca->dca_base = iobase + 0x54; - - /* copy over the APIC ID to DCA tag mapping */ - for (i = 0; i < IOAT_TAG_MAP_LEN; i++) - ioatdca->tag_map[i] = tag_map[i]; - - err = register_dca_provider(dca, &pdev->dev); - if (err) { - free_dca_provider(dca); - return NULL; - } - - return dca; -} - - -static int ioat2_dca_add_requester(struct dca_provider *dca, struct device *dev) -{ - struct ioat_dca_priv *ioatdca = dca_priv(dca); - struct pci_dev *pdev; - int i; - u16 id; - u16 global_req_table; - - /* This implementation only supports PCI-Express */ - if (dev->bus != &pci_bus_type) - return -ENODEV; - pdev = to_pci_dev(dev); - id = dcaid_from_pcidev(pdev); - - if (ioatdca->requester_count == ioatdca->max_requesters) - return -ENODEV; - - for (i = 0; i < ioatdca->max_requesters; i++) { - if (ioatdca->req_slots[i].pdev == NULL) { - /* found an empty slot */ - ioatdca->requester_count++; - ioatdca->req_slots[i].pdev = pdev; - ioatdca->req_slots[i].rid = id; - global_req_table = - readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET); - writel(id | IOAT_DCA_GREQID_VALID, - ioatdca->iobase + global_req_table + (i * 4)); - return i; - } - } - /* Error, ioatdma->requester_count is out of whack */ - return -EFAULT; -} - -static int ioat2_dca_remove_requester(struct dca_provider *dca, - struct device *dev) -{ - struct ioat_dca_priv *ioatdca = dca_priv(dca); - struct pci_dev *pdev; - int i; - u16 global_req_table; - - /* This implementation only supports PCI-Express */ - if (dev->bus != &pci_bus_type) - return -ENODEV; - pdev = to_pci_dev(dev); - - for (i = 0; i < ioatdca->max_requesters; i++) { - if (ioatdca->req_slots[i].pdev == pdev) { - global_req_table = - readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET); - writel(0, ioatdca->iobase + global_req_table + (i * 4)); - ioatdca->req_slots[i].pdev = NULL; - ioatdca->req_slots[i].rid = 0; - ioatdca->requester_count--; - return i; - } - } - return -ENODEV; -} - -static u8 ioat2_dca_get_tag(struct dca_provider *dca, - struct device *dev, - int cpu) -{ - u8 tag; - - tag = ioat_dca_get_tag(dca, dev, cpu); - tag = (~tag) & 0x1F; - return tag; -} - -static struct dca_ops ioat2_dca_ops = { - .add_requester = ioat2_dca_add_requester, - .remove_requester = ioat2_dca_remove_requester, - .get_tag = ioat2_dca_get_tag, - .dev_managed = ioat_dca_dev_managed, -}; - -static int ioat2_dca_count_dca_slots(void __iomem *iobase, u16 dca_offset) -{ - int slots = 0; - u32 req; - u16 global_req_table; - - global_req_table = readw(iobase + dca_offset + IOAT_DCA_GREQID_OFFSET); - if (global_req_table == 0) - return 0; - do { - req = readl(iobase + global_req_table + (slots * sizeof(u32))); - slots++; - } while ((req & IOAT_DCA_GREQID_LASTID) == 0); - - return slots; -} - -struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase) -{ - struct dca_provider *dca; - struct ioat_dca_priv *ioatdca; - int slots; - int i; - int err; - u32 tag_map; - u16 dca_offset; - u16 csi_fsb_control; - u16 pcie_control; - u8 bit; - - if (!system_has_dca_enabled(pdev)) - return NULL; - - dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET); - if (dca_offset == 0) - return NULL; - - slots = ioat2_dca_count_dca_slots(iobase, dca_offset); - if (slots == 0) - return NULL; - - dca = alloc_dca_provider(&ioat2_dca_ops, - sizeof(*ioatdca) - + (sizeof(struct ioat_dca_slot) * slots)); - if (!dca) - return NULL; - - ioatdca = dca_priv(dca); - ioatdca->iobase = iobase; - ioatdca->dca_base = iobase + dca_offset; - ioatdca->max_requesters = slots; - - /* some bios might not know to turn these on */ - csi_fsb_control = readw(ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET); - if ((csi_fsb_control & IOAT_FSB_CAP_ENABLE_PREFETCH) == 0) { - csi_fsb_control |= IOAT_FSB_CAP_ENABLE_PREFETCH; - writew(csi_fsb_control, - ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET); - } - pcie_control = readw(ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET); - if ((pcie_control & IOAT_PCI_CAP_ENABLE_MEMWR) == 0) { - pcie_control |= IOAT_PCI_CAP_ENABLE_MEMWR; - writew(pcie_control, - ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET); - } - - - /* TODO version, compatibility and configuration checks */ - - /* copy out the APIC to DCA tag map */ - tag_map = readl(ioatdca->dca_base + IOAT_APICID_TAG_MAP_OFFSET); - for (i = 0; i < 5; i++) { - bit = (tag_map >> (4 * i)) & 0x0f; - if (bit < 8) - ioatdca->tag_map[i] = bit | DCA_TAG_MAP_VALID; - else - ioatdca->tag_map[i] = 0; - } - - if (!dca2_tag_map_valid(ioatdca->tag_map)) { - dev_err(&pdev->dev, "APICID_TAG_MAP set incorrectly by BIOS, " - "disabling DCA\n"); - free_dca_provider(dca); - return NULL; - } - - err = register_dca_provider(dca, &pdev->dev); - if (err) { - free_dca_provider(dca); - return NULL; - } - - return dca; -} - -static int ioat3_dca_add_requester(struct dca_provider *dca, struct device *dev) -{ - struct ioat_dca_priv *ioatdca = dca_priv(dca); - struct pci_dev *pdev; - int i; - u16 id; - u16 global_req_table; - - /* This implementation only supports PCI-Express */ - if (dev->bus != &pci_bus_type) - return -ENODEV; - pdev = to_pci_dev(dev); - id = dcaid_from_pcidev(pdev); - - if (ioatdca->requester_count == ioatdca->max_requesters) - return -ENODEV; - - for (i = 0; i < ioatdca->max_requesters; i++) { - if (ioatdca->req_slots[i].pdev == NULL) { - /* found an empty slot */ - ioatdca->requester_count++; - ioatdca->req_slots[i].pdev = pdev; - ioatdca->req_slots[i].rid = id; - global_req_table = - readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); - writel(id | IOAT_DCA_GREQID_VALID, - ioatdca->iobase + global_req_table + (i * 4)); - return i; - } - } - /* Error, ioatdma->requester_count is out of whack */ - return -EFAULT; -} - -static int ioat3_dca_remove_requester(struct dca_provider *dca, - struct device *dev) -{ - struct ioat_dca_priv *ioatdca = dca_priv(dca); - struct pci_dev *pdev; - int i; - u16 global_req_table; - - /* This implementation only supports PCI-Express */ - if (dev->bus != &pci_bus_type) - return -ENODEV; - pdev = to_pci_dev(dev); - - for (i = 0; i < ioatdca->max_requesters; i++) { - if (ioatdca->req_slots[i].pdev == pdev) { - global_req_table = - readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); - writel(0, ioatdca->iobase + global_req_table + (i * 4)); - ioatdca->req_slots[i].pdev = NULL; - ioatdca->req_slots[i].rid = 0; - ioatdca->requester_count--; - return i; - } - } - return -ENODEV; -} - -static u8 ioat3_dca_get_tag(struct dca_provider *dca, - struct device *dev, - int cpu) -{ - u8 tag; - - struct ioat_dca_priv *ioatdca = dca_priv(dca); - int i, apic_id, bit, value; - u8 entry; - - tag = 0; - apic_id = cpu_physical_id(cpu); - - for (i = 0; i < IOAT_TAG_MAP_LEN; i++) { - entry = ioatdca->tag_map[i]; - if (entry & DCA3_TAG_MAP_BIT_TO_SEL) { - bit = entry & - ~(DCA3_TAG_MAP_BIT_TO_SEL | DCA3_TAG_MAP_BIT_TO_INV); - value = (apic_id & (1 << bit)) ? 1 : 0; - } else if (entry & DCA3_TAG_MAP_BIT_TO_INV) { - bit = entry & ~DCA3_TAG_MAP_BIT_TO_INV; - value = (apic_id & (1 << bit)) ? 0 : 1; - } else { - value = (entry & DCA3_TAG_MAP_LITERAL_VAL) ? 1 : 0; - } - tag |= (value << i); - } - - return tag; -} - -static struct dca_ops ioat3_dca_ops = { - .add_requester = ioat3_dca_add_requester, - .remove_requester = ioat3_dca_remove_requester, - .get_tag = ioat3_dca_get_tag, - .dev_managed = ioat_dca_dev_managed, -}; - -static int ioat3_dca_count_dca_slots(void *iobase, u16 dca_offset) -{ - int slots = 0; - u32 req; - u16 global_req_table; - - global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET); - if (global_req_table == 0) - return 0; - - do { - req = readl(iobase + global_req_table + (slots * sizeof(u32))); - slots++; - } while ((req & IOAT_DCA_GREQID_LASTID) == 0); - - return slots; -} - -struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase) -{ - struct dca_provider *dca; - struct ioat_dca_priv *ioatdca; - int slots; - int i; - int err; - u16 dca_offset; - u16 csi_fsb_control; - u16 pcie_control; - u8 bit; - - union { - u64 full; - struct { - u32 low; - u32 high; - }; - } tag_map; - - if (!system_has_dca_enabled(pdev)) - return NULL; - - dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET); - if (dca_offset == 0) - return NULL; - - slots = ioat3_dca_count_dca_slots(iobase, dca_offset); - if (slots == 0) - return NULL; - - dca = alloc_dca_provider(&ioat3_dca_ops, - sizeof(*ioatdca) - + (sizeof(struct ioat_dca_slot) * slots)); - if (!dca) - return NULL; - - ioatdca = dca_priv(dca); - ioatdca->iobase = iobase; - ioatdca->dca_base = iobase + dca_offset; - ioatdca->max_requesters = slots; - - /* some bios might not know to turn these on */ - csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET); - if ((csi_fsb_control & IOAT3_CSI_CONTROL_PREFETCH) == 0) { - csi_fsb_control |= IOAT3_CSI_CONTROL_PREFETCH; - writew(csi_fsb_control, - ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET); - } - pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET); - if ((pcie_control & IOAT3_PCI_CONTROL_MEMWR) == 0) { - pcie_control |= IOAT3_PCI_CONTROL_MEMWR; - writew(pcie_control, - ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET); - } - - - /* TODO version, compatibility and configuration checks */ - - /* copy out the APIC to DCA tag map */ - tag_map.low = - readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_LOW); - tag_map.high = - readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_HIGH); - for (i = 0; i < 8; i++) { - bit = tag_map.full >> (8 * i); - ioatdca->tag_map[i] = bit & DCA_TAG_MAP_MASK; - } - - err = register_dca_provider(dca, &pdev->dev); - if (err) { - free_dca_provider(dca); - return NULL; - } - - return dca; -} diff --git a/drivers/dma/ioat_dma.c b/drivers/dma/ioat_dma.c deleted file mode 100644 index a600fc0..0000000 --- a/drivers/dma/ioat_dma.c +++ /dev/null @@ -1,1741 +0,0 @@ -/* - * Intel I/OAT DMA Linux driver - * Copyright(c) 2004 - 2009 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - * - */ - -/* - * This driver supports an Intel I/OAT DMA engine, which does asynchronous - * copy operations. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ioatdma.h" -#include "ioatdma_registers.h" -#include "ioatdma_hw.h" - -#define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common) -#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) -#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) -#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx) - -#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) -static int ioat_pending_level = 4; -module_param(ioat_pending_level, int, 0644); -MODULE_PARM_DESC(ioat_pending_level, - "high-water mark for pushing ioat descriptors (default: 4)"); - -#define RESET_DELAY msecs_to_jiffies(100) -#define WATCHDOG_DELAY round_jiffies(msecs_to_jiffies(2000)) -static void ioat_dma_chan_reset_part2(struct work_struct *work); -static void ioat_dma_chan_watchdog(struct work_struct *work); - -/* - * workaround for IOAT ver.3.0 null descriptor issue - * (channel returns error when size is 0) - */ -#define NULL_DESC_BUFFER_SIZE 1 - -/* internal functions */ -static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan); -static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan); - -static struct ioat_desc_sw * -ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan); -static struct ioat_desc_sw * -ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan); - -static inline struct ioat_dma_chan *ioat_lookup_chan_by_index( - struct ioatdma_device *device, - int index) -{ - return device->idx[index]; -} - -/** - * ioat_dma_do_interrupt - handler used for single vector interrupt mode - * @irq: interrupt id - * @data: interrupt data - */ -static irqreturn_t ioat_dma_do_interrupt(int irq, void *data) -{ - struct ioatdma_device *instance = data; - struct ioat_dma_chan *ioat_chan; - unsigned long attnstatus; - int bit; - u8 intrctrl; - - intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); - - if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) - return IRQ_NONE; - - if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { - writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); - return IRQ_NONE; - } - - attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); - for_each_bit(bit, &attnstatus, BITS_PER_LONG) { - ioat_chan = ioat_lookup_chan_by_index(instance, bit); - tasklet_schedule(&ioat_chan->cleanup_task); - } - - writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); - return IRQ_HANDLED; -} - -/** - * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode - * @irq: interrupt id - * @data: interrupt data - */ -static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) -{ - struct ioat_dma_chan *ioat_chan = data; - - tasklet_schedule(&ioat_chan->cleanup_task); - - return IRQ_HANDLED; -} - -static void ioat_dma_cleanup_tasklet(unsigned long data); - -/** - * ioat_dma_enumerate_channels - find and initialize the device's channels - * @device: the device to be enumerated - */ -static int ioat_dma_enumerate_channels(struct ioatdma_device *device) -{ - u8 xfercap_scale; - u32 xfercap; - int i; - struct ioat_dma_chan *ioat_chan; - - /* - * IOAT ver.3 workarounds - */ - if (device->version == IOAT_VER_3_0) { - u32 chan_err_mask; - u16 dev_id; - u32 dmauncerrsts; - - /* - * Write CHANERRMSK_INT with 3E07h to mask out the errors - * that can cause stability issues for IOAT ver.3 - */ - chan_err_mask = 0x3E07; - pci_write_config_dword(device->pdev, - IOAT_PCI_CHANERRMASK_INT_OFFSET, - chan_err_mask); - - /* - * Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit - * (workaround for spurious config parity error after restart) - */ - pci_read_config_word(device->pdev, - IOAT_PCI_DEVICE_ID_OFFSET, - &dev_id); - if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) { - dmauncerrsts = 0x10; - pci_write_config_dword(device->pdev, - IOAT_PCI_DMAUNCERRSTS_OFFSET, - dmauncerrsts); - } - } - - device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); - xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); - xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); - -#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL - if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) { - device->common.chancnt--; - } -#endif - for (i = 0; i < device->common.chancnt; i++) { - ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL); - if (!ioat_chan) { - device->common.chancnt = i; - break; - } - - ioat_chan->device = device; - ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1)); - ioat_chan->xfercap = xfercap; - ioat_chan->desccount = 0; - INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2); - if (ioat_chan->device->version == IOAT_VER_2_0) - writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | - IOAT_DMA_DCA_ANY_CPU, - ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); - else if (ioat_chan->device->version == IOAT_VER_3_0) - writel(IOAT_DMA_DCA_ANY_CPU, - ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); - spin_lock_init(&ioat_chan->cleanup_lock); - spin_lock_init(&ioat_chan->desc_lock); - INIT_LIST_HEAD(&ioat_chan->free_desc); - INIT_LIST_HEAD(&ioat_chan->used_desc); - /* This should be made common somewhere in dmaengine.c */ - ioat_chan->common.device = &device->common; - list_add_tail(&ioat_chan->common.device_node, - &device->common.channels); - device->idx[i] = ioat_chan; - tasklet_init(&ioat_chan->cleanup_task, - ioat_dma_cleanup_tasklet, - (unsigned long) ioat_chan); - tasklet_disable(&ioat_chan->cleanup_task); - } - return device->common.chancnt; -} - -/** - * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended - * descriptors to hw - * @chan: DMA channel handle - */ -static inline void __ioat1_dma_memcpy_issue_pending( - struct ioat_dma_chan *ioat_chan) -{ - ioat_chan->pending = 0; - writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET); -} - -static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan) -{ - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); - - if (ioat_chan->pending > 0) { - spin_lock_bh(&ioat_chan->desc_lock); - __ioat1_dma_memcpy_issue_pending(ioat_chan); - spin_unlock_bh(&ioat_chan->desc_lock); - } -} - -static inline void __ioat2_dma_memcpy_issue_pending( - struct ioat_dma_chan *ioat_chan) -{ - ioat_chan->pending = 0; - writew(ioat_chan->dmacount, - ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); -} - -static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan) -{ - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); - - if (ioat_chan->pending > 0) { - spin_lock_bh(&ioat_chan->desc_lock); - __ioat2_dma_memcpy_issue_pending(ioat_chan); - spin_unlock_bh(&ioat_chan->desc_lock); - } -} - - -/** - * ioat_dma_chan_reset_part2 - reinit the channel after a reset - */ -static void ioat_dma_chan_reset_part2(struct work_struct *work) -{ - struct ioat_dma_chan *ioat_chan = - container_of(work, struct ioat_dma_chan, work.work); - struct ioat_desc_sw *desc; - - spin_lock_bh(&ioat_chan->cleanup_lock); - spin_lock_bh(&ioat_chan->desc_lock); - - ioat_chan->completion_virt->low = 0; - ioat_chan->completion_virt->high = 0; - ioat_chan->pending = 0; - - /* - * count the descriptors waiting, and be sure to do it - * right for both the CB1 line and the CB2 ring - */ - ioat_chan->dmacount = 0; - if (ioat_chan->used_desc.prev) { - desc = to_ioat_desc(ioat_chan->used_desc.prev); - do { - ioat_chan->dmacount++; - desc = to_ioat_desc(desc->node.next); - } while (&desc->node != ioat_chan->used_desc.next); - } - - /* - * write the new starting descriptor address - * this puts channel engine into ARMED state - */ - desc = to_ioat_desc(ioat_chan->used_desc.prev); - switch (ioat_chan->device->version) { - case IOAT_VER_1_2: - writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF, - ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->async_tx.phys) >> 32, - ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); - - writeb(IOAT_CHANCMD_START, ioat_chan->reg_base - + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); - break; - case IOAT_VER_2_0: - writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF, - ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->async_tx.phys) >> 32, - ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); - - /* tell the engine to go with what's left to be done */ - writew(ioat_chan->dmacount, - ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); - - break; - } - dev_err(&ioat_chan->device->pdev->dev, - "chan%d reset - %d descs waiting, %d total desc\n", - chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); - - spin_unlock_bh(&ioat_chan->desc_lock); - spin_unlock_bh(&ioat_chan->cleanup_lock); -} - -/** - * ioat_dma_reset_channel - restart a channel - * @ioat_chan: IOAT DMA channel handle - */ -static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan) -{ - u32 chansts, chanerr; - - if (!ioat_chan->used_desc.prev) - return; - - chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); - chansts = (ioat_chan->completion_virt->low - & IOAT_CHANSTS_DMA_TRANSFER_STATUS); - if (chanerr) { - dev_err(&ioat_chan->device->pdev->dev, - "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", - chan_num(ioat_chan), chansts, chanerr); - writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); - } - - /* - * whack it upside the head with a reset - * and wait for things to settle out. - * force the pending count to a really big negative - * to make sure no one forces an issue_pending - * while we're waiting. - */ - - spin_lock_bh(&ioat_chan->desc_lock); - ioat_chan->pending = INT_MIN; - writeb(IOAT_CHANCMD_RESET, - ioat_chan->reg_base - + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); - spin_unlock_bh(&ioat_chan->desc_lock); - - /* schedule the 2nd half instead of sleeping a long time */ - schedule_delayed_work(&ioat_chan->work, RESET_DELAY); -} - -/** - * ioat_dma_chan_watchdog - watch for stuck channels - */ -static void ioat_dma_chan_watchdog(struct work_struct *work) -{ - struct ioatdma_device *device = - container_of(work, struct ioatdma_device, work.work); - struct ioat_dma_chan *ioat_chan; - int i; - - union { - u64 full; - struct { - u32 low; - u32 high; - }; - } completion_hw; - unsigned long compl_desc_addr_hw; - - for (i = 0; i < device->common.chancnt; i++) { - ioat_chan = ioat_lookup_chan_by_index(device, i); - - if (ioat_chan->device->version == IOAT_VER_1_2 - /* have we started processing anything yet */ - && ioat_chan->last_completion - /* have we completed any since last watchdog cycle? */ - && (ioat_chan->last_completion == - ioat_chan->watchdog_completion) - /* has TCP stuck on one cookie since last watchdog? */ - && (ioat_chan->watchdog_tcp_cookie == - ioat_chan->watchdog_last_tcp_cookie) - && (ioat_chan->watchdog_tcp_cookie != - ioat_chan->completed_cookie) - /* is there something in the chain to be processed? */ - /* CB1 chain always has at least the last one processed */ - && (ioat_chan->used_desc.prev != ioat_chan->used_desc.next) - && ioat_chan->pending == 0) { - - /* - * check CHANSTS register for completed - * descriptor address. - * if it is different than completion writeback, - * it is not zero - * and it has changed since the last watchdog - * we can assume that channel - * is still working correctly - * and the problem is in completion writeback. - * update completion writeback - * with actual CHANSTS value - * else - * try resetting the channel - */ - - completion_hw.low = readl(ioat_chan->reg_base + - IOAT_CHANSTS_OFFSET_LOW(ioat_chan->device->version)); - completion_hw.high = readl(ioat_chan->reg_base + - IOAT_CHANSTS_OFFSET_HIGH(ioat_chan->device->version)); -#if (BITS_PER_LONG == 64) - compl_desc_addr_hw = - completion_hw.full - & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; -#else - compl_desc_addr_hw = - completion_hw.low & IOAT_LOW_COMPLETION_MASK; -#endif - - if ((compl_desc_addr_hw != 0) - && (compl_desc_addr_hw != ioat_chan->watchdog_completion) - && (compl_desc_addr_hw != ioat_chan->last_compl_desc_addr_hw)) { - ioat_chan->last_compl_desc_addr_hw = compl_desc_addr_hw; - ioat_chan->completion_virt->low = completion_hw.low; - ioat_chan->completion_virt->high = completion_hw.high; - } else { - ioat_dma_reset_channel(ioat_chan); - ioat_chan->watchdog_completion = 0; - ioat_chan->last_compl_desc_addr_hw = 0; - } - - /* - * for version 2.0 if there are descriptors yet to be processed - * and the last completed hasn't changed since the last watchdog - * if they haven't hit the pending level - * issue the pending to push them through - * else - * try resetting the channel - */ - } else if (ioat_chan->device->version == IOAT_VER_2_0 - && ioat_chan->used_desc.prev - && ioat_chan->last_completion - && ioat_chan->last_completion == ioat_chan->watchdog_completion) { - - if (ioat_chan->pending < ioat_pending_level) - ioat2_dma_memcpy_issue_pending(&ioat_chan->common); - else { - ioat_dma_reset_channel(ioat_chan); - ioat_chan->watchdog_completion = 0; - } - } else { - ioat_chan->last_compl_desc_addr_hw = 0; - ioat_chan->watchdog_completion - = ioat_chan->last_completion; - } - - ioat_chan->watchdog_last_tcp_cookie = - ioat_chan->watchdog_tcp_cookie; - } - - schedule_delayed_work(&device->work, WATCHDOG_DELAY); -} - -static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) -{ - struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan); - struct ioat_desc_sw *first = tx_to_ioat_desc(tx); - struct ioat_desc_sw *prev, *new; - struct ioat_dma_descriptor *hw; - dma_cookie_t cookie; - LIST_HEAD(new_chain); - u32 copy; - size_t len; - dma_addr_t src, dst; - unsigned long orig_flags; - unsigned int desc_count = 0; - - /* src and dest and len are stored in the initial descriptor */ - len = first->len; - src = first->src; - dst = first->dst; - orig_flags = first->async_tx.flags; - new = first; - - spin_lock_bh(&ioat_chan->desc_lock); - prev = to_ioat_desc(ioat_chan->used_desc.prev); - prefetch(prev->hw); - do { - copy = min_t(size_t, len, ioat_chan->xfercap); - - async_tx_ack(&new->async_tx); - - hw = new->hw; - hw->size = copy; - hw->ctl = 0; - hw->src_addr = src; - hw->dst_addr = dst; - hw->next = 0; - - /* chain together the physical address list for the HW */ - wmb(); - prev->hw->next = (u64) new->async_tx.phys; - - len -= copy; - dst += copy; - src += copy; - - list_add_tail(&new->node, &new_chain); - desc_count++; - prev = new; - } while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan))); - - if (!new) { - dev_err(&ioat_chan->device->pdev->dev, - "tx submit failed\n"); - spin_unlock_bh(&ioat_chan->desc_lock); - return -ENOMEM; - } - - hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS; - if (first->async_tx.callback) { - hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN; - if (first != new) { - /* move callback into to last desc */ - new->async_tx.callback = first->async_tx.callback; - new->async_tx.callback_param - = first->async_tx.callback_param; - first->async_tx.callback = NULL; - first->async_tx.callback_param = NULL; - } - } - - new->tx_cnt = desc_count; - new->async_tx.flags = orig_flags; /* client is in control of this ack */ - - /* store the original values for use in later cleanup */ - if (new != first) { - new->src = first->src; - new->dst = first->dst; - new->len = first->len; - } - - /* cookie incr and addition to used_list must be atomic */ - cookie = ioat_chan->common.cookie; - cookie++; - if (cookie < 0) - cookie = 1; - ioat_chan->common.cookie = new->async_tx.cookie = cookie; - - /* write address into NextDescriptor field of last desc in chain */ - to_ioat_desc(ioat_chan->used_desc.prev)->hw->next = - first->async_tx.phys; - list_splice_tail(&new_chain, &ioat_chan->used_desc); - - ioat_chan->dmacount += desc_count; - ioat_chan->pending += desc_count; - if (ioat_chan->pending >= ioat_pending_level) - __ioat1_dma_memcpy_issue_pending(ioat_chan); - spin_unlock_bh(&ioat_chan->desc_lock); - - return cookie; -} - -static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) -{ - struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan); - struct ioat_desc_sw *first = tx_to_ioat_desc(tx); - struct ioat_desc_sw *new; - struct ioat_dma_descriptor *hw; - dma_cookie_t cookie; - u32 copy; - size_t len; - dma_addr_t src, dst; - unsigned long orig_flags; - unsigned int desc_count = 0; - - /* src and dest and len are stored in the initial descriptor */ - len = first->len; - src = first->src; - dst = first->dst; - orig_flags = first->async_tx.flags; - new = first; - - /* - * ioat_chan->desc_lock is still in force in version 2 path - * it gets unlocked at end of this function - */ - do { - copy = min_t(size_t, len, ioat_chan->xfercap); - - async_tx_ack(&new->async_tx); - - hw = new->hw; - hw->size = copy; - hw->ctl = 0; - hw->src_addr = src; - hw->dst_addr = dst; - - len -= copy; - dst += copy; - src += copy; - desc_count++; - } while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan))); - - if (!new) { - dev_err(&ioat_chan->device->pdev->dev, - "tx submit failed\n"); - spin_unlock_bh(&ioat_chan->desc_lock); - return -ENOMEM; - } - - hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS; - if (first->async_tx.callback) { - hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN; - if (first != new) { - /* move callback into to last desc */ - new->async_tx.callback = first->async_tx.callback; - new->async_tx.callback_param - = first->async_tx.callback_param; - first->async_tx.callback = NULL; - first->async_tx.callback_param = NULL; - } - } - - new->tx_cnt = desc_count; - new->async_tx.flags = orig_flags; /* client is in control of this ack */ - - /* store the original values for use in later cleanup */ - if (new != first) { - new->src = first->src; - new->dst = first->dst; - new->len = first->len; - } - - /* cookie incr and addition to used_list must be atomic */ - cookie = ioat_chan->common.cookie; - cookie++; - if (cookie < 0) - cookie = 1; - ioat_chan->common.cookie = new->async_tx.cookie = cookie; - - ioat_chan->dmacount += desc_count; - ioat_chan->pending += desc_count; - if (ioat_chan->pending >= ioat_pending_level) - __ioat2_dma_memcpy_issue_pending(ioat_chan); - spin_unlock_bh(&ioat_chan->desc_lock); - - return cookie; -} - -/** - * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair - * @ioat_chan: the channel supplying the memory pool for the descriptors - * @flags: allocation flags - */ -static struct ioat_desc_sw *ioat_dma_alloc_descriptor( - struct ioat_dma_chan *ioat_chan, - gfp_t flags) -{ - struct ioat_dma_descriptor *desc; - struct ioat_desc_sw *desc_sw; - struct ioatdma_device *ioatdma_device; - dma_addr_t phys; - - ioatdma_device = to_ioatdma_device(ioat_chan->common.device); - desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys); - if (unlikely(!desc)) - return NULL; - - desc_sw = kzalloc(sizeof(*desc_sw), flags); - if (unlikely(!desc_sw)) { - pci_pool_free(ioatdma_device->dma_pool, desc, phys); - return NULL; - } - - memset(desc, 0, sizeof(*desc)); - dma_async_tx_descriptor_init(&desc_sw->async_tx, &ioat_chan->common); - switch (ioat_chan->device->version) { - case IOAT_VER_1_2: - desc_sw->async_tx.tx_submit = ioat1_tx_submit; - break; - case IOAT_VER_2_0: - case IOAT_VER_3_0: - desc_sw->async_tx.tx_submit = ioat2_tx_submit; - break; - } - - desc_sw->hw = desc; - desc_sw->async_tx.phys = phys; - - return desc_sw; -} - -static int ioat_initial_desc_count = 256; -module_param(ioat_initial_desc_count, int, 0644); -MODULE_PARM_DESC(ioat_initial_desc_count, - "initial descriptors per channel (default: 256)"); - -/** - * ioat2_dma_massage_chan_desc - link the descriptors into a circle - * @ioat_chan: the channel to be massaged - */ -static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan) -{ - struct ioat_desc_sw *desc, *_desc; - - /* setup used_desc */ - ioat_chan->used_desc.next = ioat_chan->free_desc.next; - ioat_chan->used_desc.prev = NULL; - - /* pull free_desc out of the circle so that every node is a hw - * descriptor, but leave it pointing to the list - */ - ioat_chan->free_desc.prev->next = ioat_chan->free_desc.next; - ioat_chan->free_desc.next->prev = ioat_chan->free_desc.prev; - - /* circle link the hw descriptors */ - desc = to_ioat_desc(ioat_chan->free_desc.next); - desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys; - list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) { - desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys; - } -} - -/** - * ioat_dma_alloc_chan_resources - returns the number of allocated descriptors - * @chan: the channel to be filled out - */ -static int ioat_dma_alloc_chan_resources(struct dma_chan *chan) -{ - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); - struct ioat_desc_sw *desc; - u16 chanctrl; - u32 chanerr; - int i; - LIST_HEAD(tmp_list); - - /* have we already been set up? */ - if (!list_empty(&ioat_chan->free_desc)) - return ioat_chan->desccount; - - /* Setup register to interrupt and write completion status on error */ - chanctrl = IOAT_CHANCTRL_ERR_INT_EN | - IOAT_CHANCTRL_ANY_ERR_ABORT_EN | - IOAT_CHANCTRL_ERR_COMPLETION_EN; - writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); - - chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); - if (chanerr) { - dev_err(&ioat_chan->device->pdev->dev, - "CHANERR = %x, clearing\n", chanerr); - writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); - } - - /* Allocate descriptors */ - for (i = 0; i < ioat_initial_desc_count; i++) { - desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL); - if (!desc) { - dev_err(&ioat_chan->device->pdev->dev, - "Only %d initial descriptors\n", i); - break; - } - list_add_tail(&desc->node, &tmp_list); - } - spin_lock_bh(&ioat_chan->desc_lock); - ioat_chan->desccount = i; - list_splice(&tmp_list, &ioat_chan->free_desc); - if (ioat_chan->device->version != IOAT_VER_1_2) - ioat2_dma_massage_chan_desc(ioat_chan); - spin_unlock_bh(&ioat_chan->desc_lock); - - /* allocate a completion writeback area */ - /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ - ioat_chan->completion_virt = - pci_pool_alloc(ioat_chan->device->completion_pool, - GFP_KERNEL, - &ioat_chan->completion_addr); - memset(ioat_chan->completion_virt, 0, - sizeof(*ioat_chan->completion_virt)); - writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF, - ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); - writel(((u64) ioat_chan->completion_addr) >> 32, - ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); - - tasklet_enable(&ioat_chan->cleanup_task); - ioat_dma_start_null_desc(ioat_chan); /* give chain to dma device */ - return ioat_chan->desccount; -} - -/** - * ioat_dma_free_chan_resources - release all the descriptors - * @chan: the channel to be cleaned - */ -static void ioat_dma_free_chan_resources(struct dma_chan *chan) -{ - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); - struct ioatdma_device *ioatdma_device = to_ioatdma_device(chan->device); - struct ioat_desc_sw *desc, *_desc; - int in_use_descs = 0; - - /* Before freeing channel resources first check - * if they have been previously allocated for this channel. - */ - if (ioat_chan->desccount == 0) - return; - - tasklet_disable(&ioat_chan->cleanup_task); - ioat_dma_memcpy_cleanup(ioat_chan); - - /* Delay 100ms after reset to allow internal DMA logic to quiesce - * before removing DMA descriptor resources. - */ - writeb(IOAT_CHANCMD_RESET, - ioat_chan->reg_base - + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); - mdelay(100); - - spin_lock_bh(&ioat_chan->desc_lock); - switch (ioat_chan->device->version) { - case IOAT_VER_1_2: - list_for_each_entry_safe(desc, _desc, - &ioat_chan->used_desc, node) { - in_use_descs++; - list_del(&desc->node); - pci_pool_free(ioatdma_device->dma_pool, desc->hw, - desc->async_tx.phys); - kfree(desc); - } - list_for_each_entry_safe(desc, _desc, - &ioat_chan->free_desc, node) { - list_del(&desc->node); - pci_pool_free(ioatdma_device->dma_pool, desc->hw, - desc->async_tx.phys); - kfree(desc); - } - break; - case IOAT_VER_2_0: - case IOAT_VER_3_0: - list_for_each_entry_safe(desc, _desc, - ioat_chan->free_desc.next, node) { - list_del(&desc->node); - pci_pool_free(ioatdma_device->dma_pool, desc->hw, - desc->async_tx.phys); - kfree(desc); - } - desc = to_ioat_desc(ioat_chan->free_desc.next); - pci_pool_free(ioatdma_device->dma_pool, desc->hw, - desc->async_tx.phys); - kfree(desc); - INIT_LIST_HEAD(&ioat_chan->free_desc); - INIT_LIST_HEAD(&ioat_chan->used_desc); - break; - } - spin_unlock_bh(&ioat_chan->desc_lock); - - pci_pool_free(ioatdma_device->completion_pool, - ioat_chan->completion_virt, - ioat_chan->completion_addr); - - /* one is ok since we left it on there on purpose */ - if (in_use_descs > 1) - dev_err(&ioat_chan->device->pdev->dev, - "Freeing %d in use descriptors!\n", - in_use_descs - 1); - - ioat_chan->last_completion = ioat_chan->completion_addr = 0; - ioat_chan->pending = 0; - ioat_chan->dmacount = 0; - ioat_chan->desccount = 0; - ioat_chan->watchdog_completion = 0; - ioat_chan->last_compl_desc_addr_hw = 0; - ioat_chan->watchdog_tcp_cookie = - ioat_chan->watchdog_last_tcp_cookie = 0; -} - -/** - * ioat_dma_get_next_descriptor - return the next available descriptor - * @ioat_chan: IOAT DMA channel handle - * - * Gets the next descriptor from the chain, and must be called with the - * channel's desc_lock held. Allocates more descriptors if the channel - * has run out. - */ -static struct ioat_desc_sw * -ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) -{ - struct ioat_desc_sw *new; - - if (!list_empty(&ioat_chan->free_desc)) { - new = to_ioat_desc(ioat_chan->free_desc.next); - list_del(&new->node); - } else { - /* try to get another desc */ - new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC); - if (!new) { - dev_err(&ioat_chan->device->pdev->dev, - "alloc failed\n"); - return NULL; - } - } - - prefetch(new->hw); - return new; -} - -static struct ioat_desc_sw * -ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) -{ - struct ioat_desc_sw *new; - - /* - * used.prev points to where to start processing - * used.next points to next free descriptor - * if used.prev == NULL, there are none waiting to be processed - * if used.next == used.prev.prev, there is only one free descriptor, - * and we need to use it to as a noop descriptor before - * linking in a new set of descriptors, since the device - * has probably already read the pointer to it - */ - if (ioat_chan->used_desc.prev && - ioat_chan->used_desc.next == ioat_chan->used_desc.prev->prev) { - - struct ioat_desc_sw *desc; - struct ioat_desc_sw *noop_desc; - int i; - - /* set up the noop descriptor */ - noop_desc = to_ioat_desc(ioat_chan->used_desc.next); - /* set size to non-zero value (channel returns error when size is 0) */ - noop_desc->hw->size = NULL_DESC_BUFFER_SIZE; - noop_desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL; - noop_desc->hw->src_addr = 0; - noop_desc->hw->dst_addr = 0; - - ioat_chan->used_desc.next = ioat_chan->used_desc.next->next; - ioat_chan->pending++; - ioat_chan->dmacount++; - - /* try to get a few more descriptors */ - for (i = 16; i; i--) { - desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC); - if (!desc) { - dev_err(&ioat_chan->device->pdev->dev, - "alloc failed\n"); - break; - } - list_add_tail(&desc->node, ioat_chan->used_desc.next); - - desc->hw->next - = to_ioat_desc(desc->node.next)->async_tx.phys; - to_ioat_desc(desc->node.prev)->hw->next - = desc->async_tx.phys; - ioat_chan->desccount++; - } - - ioat_chan->used_desc.next = noop_desc->node.next; - } - new = to_ioat_desc(ioat_chan->used_desc.next); - prefetch(new); - ioat_chan->used_desc.next = new->node.next; - - if (ioat_chan->used_desc.prev == NULL) - ioat_chan->used_desc.prev = &new->node; - - prefetch(new->hw); - return new; -} - -static struct ioat_desc_sw *ioat_dma_get_next_descriptor( - struct ioat_dma_chan *ioat_chan) -{ - if (!ioat_chan) - return NULL; - - switch (ioat_chan->device->version) { - case IOAT_VER_1_2: - return ioat1_dma_get_next_descriptor(ioat_chan); - case IOAT_VER_2_0: - case IOAT_VER_3_0: - return ioat2_dma_get_next_descriptor(ioat_chan); - } - return NULL; -} - -static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy( - struct dma_chan *chan, - dma_addr_t dma_dest, - dma_addr_t dma_src, - size_t len, - unsigned long flags) -{ - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); - struct ioat_desc_sw *new; - - spin_lock_bh(&ioat_chan->desc_lock); - new = ioat_dma_get_next_descriptor(ioat_chan); - spin_unlock_bh(&ioat_chan->desc_lock); - - if (new) { - new->len = len; - new->dst = dma_dest; - new->src = dma_src; - new->async_tx.flags = flags; - return &new->async_tx; - } else { - dev_err(&ioat_chan->device->pdev->dev, - "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n", - chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); - return NULL; - } -} - -static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy( - struct dma_chan *chan, - dma_addr_t dma_dest, - dma_addr_t dma_src, - size_t len, - unsigned long flags) -{ - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); - struct ioat_desc_sw *new; - - spin_lock_bh(&ioat_chan->desc_lock); - new = ioat2_dma_get_next_descriptor(ioat_chan); - - /* - * leave ioat_chan->desc_lock set in ioat 2 path - * it will get unlocked at end of tx_submit - */ - - if (new) { - new->len = len; - new->dst = dma_dest; - new->src = dma_src; - new->async_tx.flags = flags; - return &new->async_tx; - } else { - spin_unlock_bh(&ioat_chan->desc_lock); - dev_err(&ioat_chan->device->pdev->dev, - "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n", - chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); - return NULL; - } -} - -static void ioat_dma_cleanup_tasklet(unsigned long data) -{ - struct ioat_dma_chan *chan = (void *)data; - ioat_dma_memcpy_cleanup(chan); - writew(IOAT_CHANCTRL_INT_DISABLE, - chan->reg_base + IOAT_CHANCTRL_OFFSET); -} - -static void -ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc) -{ - if (!(desc->async_tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { - if (desc->async_tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) - pci_unmap_single(ioat_chan->device->pdev, - pci_unmap_addr(desc, dst), - pci_unmap_len(desc, len), - PCI_DMA_FROMDEVICE); - else - pci_unmap_page(ioat_chan->device->pdev, - pci_unmap_addr(desc, dst), - pci_unmap_len(desc, len), - PCI_DMA_FROMDEVICE); - } - - if (!(desc->async_tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { - if (desc->async_tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) - pci_unmap_single(ioat_chan->device->pdev, - pci_unmap_addr(desc, src), - pci_unmap_len(desc, len), - PCI_DMA_TODEVICE); - else - pci_unmap_page(ioat_chan->device->pdev, - pci_unmap_addr(desc, src), - pci_unmap_len(desc, len), - PCI_DMA_TODEVICE); - } -} - -/** - * ioat_dma_memcpy_cleanup - cleanup up finished descriptors - * @chan: ioat channel to be cleaned up - */ -static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) -{ - unsigned long phys_complete; - struct ioat_desc_sw *desc, *_desc; - dma_cookie_t cookie = 0; - unsigned long desc_phys; - struct ioat_desc_sw *latest_desc; - - prefetch(ioat_chan->completion_virt); - - if (!spin_trylock_bh(&ioat_chan->cleanup_lock)) - return; - - /* The completion writeback can happen at any time, - so reads by the driver need to be atomic operations - The descriptor physical addresses are limited to 32-bits - when the CPU can only do a 32-bit mov */ - -#if (BITS_PER_LONG == 64) - phys_complete = - ioat_chan->completion_virt->full - & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; -#else - phys_complete = - ioat_chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK; -#endif - - if ((ioat_chan->completion_virt->full - & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == - IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) { - dev_err(&ioat_chan->device->pdev->dev, - "Channel halted, chanerr = %x\n", - readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET)); - - /* TODO do something to salvage the situation */ - } - - if (phys_complete == ioat_chan->last_completion) { - spin_unlock_bh(&ioat_chan->cleanup_lock); - /* - * perhaps we're stuck so hard that the watchdog can't go off? - * try to catch it after 2 seconds - */ - if (ioat_chan->device->version != IOAT_VER_3_0) { - if (time_after(jiffies, - ioat_chan->last_completion_time + HZ*WATCHDOG_DELAY)) { - ioat_dma_chan_watchdog(&(ioat_chan->device->work.work)); - ioat_chan->last_completion_time = jiffies; - } - } - return; - } - ioat_chan->last_completion_time = jiffies; - - cookie = 0; - if (!spin_trylock_bh(&ioat_chan->desc_lock)) { - spin_unlock_bh(&ioat_chan->cleanup_lock); - return; - } - - switch (ioat_chan->device->version) { - case IOAT_VER_1_2: - list_for_each_entry_safe(desc, _desc, - &ioat_chan->used_desc, node) { - - /* - * Incoming DMA requests may use multiple descriptors, - * due to exceeding xfercap, perhaps. If so, only the - * last one will have a cookie, and require unmapping. - */ - if (desc->async_tx.cookie) { - cookie = desc->async_tx.cookie; - ioat_dma_unmap(ioat_chan, desc); - if (desc->async_tx.callback) { - desc->async_tx.callback(desc->async_tx.callback_param); - desc->async_tx.callback = NULL; - } - } - - if (desc->async_tx.phys != phys_complete) { - /* - * a completed entry, but not the last, so clean - * up if the client is done with the descriptor - */ - if (async_tx_test_ack(&desc->async_tx)) { - list_move_tail(&desc->node, - &ioat_chan->free_desc); - } else - desc->async_tx.cookie = 0; - } else { - /* - * last used desc. Do not remove, so we can - * append from it, but don't look at it next - * time, either - */ - desc->async_tx.cookie = 0; - - /* TODO check status bits? */ - break; - } - } - break; - case IOAT_VER_2_0: - case IOAT_VER_3_0: - /* has some other thread has already cleaned up? */ - if (ioat_chan->used_desc.prev == NULL) - break; - - /* work backwards to find latest finished desc */ - desc = to_ioat_desc(ioat_chan->used_desc.next); - latest_desc = NULL; - do { - desc = to_ioat_desc(desc->node.prev); - desc_phys = (unsigned long)desc->async_tx.phys - & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; - if (desc_phys == phys_complete) { - latest_desc = desc; - break; - } - } while (&desc->node != ioat_chan->used_desc.prev); - - if (latest_desc != NULL) { - - /* work forwards to clear finished descriptors */ - for (desc = to_ioat_desc(ioat_chan->used_desc.prev); - &desc->node != latest_desc->node.next && - &desc->node != ioat_chan->used_desc.next; - desc = to_ioat_desc(desc->node.next)) { - if (desc->async_tx.cookie) { - cookie = desc->async_tx.cookie; - desc->async_tx.cookie = 0; - ioat_dma_unmap(ioat_chan, desc); - if (desc->async_tx.callback) { - desc->async_tx.callback(desc->async_tx.callback_param); - desc->async_tx.callback = NULL; - } - } - } - - /* move used.prev up beyond those that are finished */ - if (&desc->node == ioat_chan->used_desc.next) - ioat_chan->used_desc.prev = NULL; - else - ioat_chan->used_desc.prev = &desc->node; - } - break; - } - - spin_unlock_bh(&ioat_chan->desc_lock); - - ioat_chan->last_completion = phys_complete; - if (cookie != 0) - ioat_chan->completed_cookie = cookie; - - spin_unlock_bh(&ioat_chan->cleanup_lock); -} - -/** - * ioat_dma_is_complete - poll the status of a IOAT DMA transaction - * @chan: IOAT DMA channel handle - * @cookie: DMA transaction identifier - * @done: if not %NULL, updated with last completed transaction - * @used: if not %NULL, updated with last used transaction - */ -static enum dma_status ioat_dma_is_complete(struct dma_chan *chan, - dma_cookie_t cookie, - dma_cookie_t *done, - dma_cookie_t *used) -{ - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); - dma_cookie_t last_used; - dma_cookie_t last_complete; - enum dma_status ret; - - last_used = chan->cookie; - last_complete = ioat_chan->completed_cookie; - ioat_chan->watchdog_tcp_cookie = cookie; - - if (done) - *done = last_complete; - if (used) - *used = last_used; - - ret = dma_async_is_complete(cookie, last_complete, last_used); - if (ret == DMA_SUCCESS) - return ret; - - ioat_dma_memcpy_cleanup(ioat_chan); - - last_used = chan->cookie; - last_complete = ioat_chan->completed_cookie; - - if (done) - *done = last_complete; - if (used) - *used = last_used; - - return dma_async_is_complete(cookie, last_complete, last_used); -} - -static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan) -{ - struct ioat_desc_sw *desc; - - spin_lock_bh(&ioat_chan->desc_lock); - - desc = ioat_dma_get_next_descriptor(ioat_chan); - - if (!desc) { - dev_err(&ioat_chan->device->pdev->dev, - "Unable to start null desc - get next desc failed\n"); - spin_unlock_bh(&ioat_chan->desc_lock); - return; - } - - desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL - | IOAT_DMA_DESCRIPTOR_CTL_INT_GN - | IOAT_DMA_DESCRIPTOR_CTL_CP_STS; - /* set size to non-zero value (channel returns error when size is 0) */ - desc->hw->size = NULL_DESC_BUFFER_SIZE; - desc->hw->src_addr = 0; - desc->hw->dst_addr = 0; - async_tx_ack(&desc->async_tx); - switch (ioat_chan->device->version) { - case IOAT_VER_1_2: - desc->hw->next = 0; - list_add_tail(&desc->node, &ioat_chan->used_desc); - - writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF, - ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->async_tx.phys) >> 32, - ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); - - writeb(IOAT_CHANCMD_START, ioat_chan->reg_base - + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); - break; - case IOAT_VER_2_0: - case IOAT_VER_3_0: - writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF, - ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->async_tx.phys) >> 32, - ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); - - ioat_chan->dmacount++; - __ioat2_dma_memcpy_issue_pending(ioat_chan); - break; - } - spin_unlock_bh(&ioat_chan->desc_lock); -} - -/* - * Perform a IOAT transaction to verify the HW works. - */ -#define IOAT_TEST_SIZE 2000 - -static void ioat_dma_test_callback(void *dma_async_param) -{ - struct completion *cmp = dma_async_param; - - complete(cmp); -} - -/** - * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. - * @device: device to be tested - */ -static int ioat_dma_self_test(struct ioatdma_device *device) -{ - int i; - u8 *src; - u8 *dest; - struct dma_chan *dma_chan; - struct dma_async_tx_descriptor *tx; - dma_addr_t dma_dest, dma_src; - dma_cookie_t cookie; - int err = 0; - struct completion cmp; - unsigned long tmo; - unsigned long flags; - - src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); - if (!src) - return -ENOMEM; - dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); - if (!dest) { - kfree(src); - return -ENOMEM; - } - - /* Fill in src buffer */ - for (i = 0; i < IOAT_TEST_SIZE; i++) - src[i] = (u8)i; - - /* Start copy, using first DMA channel */ - dma_chan = container_of(device->common.channels.next, - struct dma_chan, - device_node); - if (device->common.device_alloc_chan_resources(dma_chan) < 1) { - dev_err(&device->pdev->dev, - "selftest cannot allocate chan resource\n"); - err = -ENODEV; - goto out; - } - - dma_src = dma_map_single(dma_chan->device->dev, src, IOAT_TEST_SIZE, - DMA_TO_DEVICE); - dma_dest = dma_map_single(dma_chan->device->dev, dest, IOAT_TEST_SIZE, - DMA_FROM_DEVICE); - flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE; - tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src, - IOAT_TEST_SIZE, flags); - if (!tx) { - dev_err(&device->pdev->dev, - "Self-test prep failed, disabling\n"); - err = -ENODEV; - goto free_resources; - } - - async_tx_ack(tx); - init_completion(&cmp); - tx->callback = ioat_dma_test_callback; - tx->callback_param = &cmp; - cookie = tx->tx_submit(tx); - if (cookie < 0) { - dev_err(&device->pdev->dev, - "Self-test setup failed, disabling\n"); - err = -ENODEV; - goto free_resources; - } - device->common.device_issue_pending(dma_chan); - - tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); - - if (tmo == 0 || - device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL) - != DMA_SUCCESS) { - dev_err(&device->pdev->dev, - "Self-test copy timed out, disabling\n"); - err = -ENODEV; - goto free_resources; - } - if (memcmp(src, dest, IOAT_TEST_SIZE)) { - dev_err(&device->pdev->dev, - "Self-test copy failed compare, disabling\n"); - err = -ENODEV; - goto free_resources; - } - -free_resources: - device->common.device_free_chan_resources(dma_chan); -out: - kfree(src); - kfree(dest); - return err; -} - -static char ioat_interrupt_style[32] = "msix"; -module_param_string(ioat_interrupt_style, ioat_interrupt_style, - sizeof(ioat_interrupt_style), 0644); -MODULE_PARM_DESC(ioat_interrupt_style, - "set ioat interrupt style: msix (default), " - "msix-single-vector, msi, intx)"); - -/** - * ioat_dma_setup_interrupts - setup interrupt handler - * @device: ioat device - */ -static int ioat_dma_setup_interrupts(struct ioatdma_device *device) -{ - struct ioat_dma_chan *ioat_chan; - int err, i, j, msixcnt; - u8 intrctrl = 0; - - if (!strcmp(ioat_interrupt_style, "msix")) - goto msix; - if (!strcmp(ioat_interrupt_style, "msix-single-vector")) - goto msix_single_vector; - if (!strcmp(ioat_interrupt_style, "msi")) - goto msi; - if (!strcmp(ioat_interrupt_style, "intx")) - goto intx; - dev_err(&device->pdev->dev, "invalid ioat_interrupt_style %s\n", - ioat_interrupt_style); - goto err_no_irq; - -msix: - /* The number of MSI-X vectors should equal the number of channels */ - msixcnt = device->common.chancnt; - for (i = 0; i < msixcnt; i++) - device->msix_entries[i].entry = i; - - err = pci_enable_msix(device->pdev, device->msix_entries, msixcnt); - if (err < 0) - goto msi; - if (err > 0) - goto msix_single_vector; - - for (i = 0; i < msixcnt; i++) { - ioat_chan = ioat_lookup_chan_by_index(device, i); - err = request_irq(device->msix_entries[i].vector, - ioat_dma_do_interrupt_msix, - 0, "ioat-msix", ioat_chan); - if (err) { - for (j = 0; j < i; j++) { - ioat_chan = - ioat_lookup_chan_by_index(device, j); - free_irq(device->msix_entries[j].vector, - ioat_chan); - } - goto msix_single_vector; - } - } - intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; - device->irq_mode = msix_multi_vector; - goto done; - -msix_single_vector: - device->msix_entries[0].entry = 0; - err = pci_enable_msix(device->pdev, device->msix_entries, 1); - if (err) - goto msi; - - err = request_irq(device->msix_entries[0].vector, ioat_dma_do_interrupt, - 0, "ioat-msix", device); - if (err) { - pci_disable_msix(device->pdev); - goto msi; - } - device->irq_mode = msix_single_vector; - goto done; - -msi: - err = pci_enable_msi(device->pdev); - if (err) - goto intx; - - err = request_irq(device->pdev->irq, ioat_dma_do_interrupt, - 0, "ioat-msi", device); - if (err) { - pci_disable_msi(device->pdev); - goto intx; - } - /* - * CB 1.2 devices need a bit set in configuration space to enable MSI - */ - if (device->version == IOAT_VER_1_2) { - u32 dmactrl; - pci_read_config_dword(device->pdev, - IOAT_PCI_DMACTRL_OFFSET, &dmactrl); - dmactrl |= IOAT_PCI_DMACTRL_MSI_EN; - pci_write_config_dword(device->pdev, - IOAT_PCI_DMACTRL_OFFSET, dmactrl); - } - device->irq_mode = msi; - goto done; - -intx: - err = request_irq(device->pdev->irq, ioat_dma_do_interrupt, - IRQF_SHARED, "ioat-intx", device); - if (err) - goto err_no_irq; - device->irq_mode = intx; - -done: - intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; - writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET); - return 0; - -err_no_irq: - /* Disable all interrupt generation */ - writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); - dev_err(&device->pdev->dev, "no usable interrupts\n"); - device->irq_mode = none; - return -1; -} - -/** - * ioat_dma_remove_interrupts - remove whatever interrupts were set - * @device: ioat device - */ -static void ioat_dma_remove_interrupts(struct ioatdma_device *device) -{ - struct ioat_dma_chan *ioat_chan; - int i; - - /* Disable all interrupt generation */ - writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); - - switch (device->irq_mode) { - case msix_multi_vector: - for (i = 0; i < device->common.chancnt; i++) { - ioat_chan = ioat_lookup_chan_by_index(device, i); - free_irq(device->msix_entries[i].vector, ioat_chan); - } - pci_disable_msix(device->pdev); - break; - case msix_single_vector: - free_irq(device->msix_entries[0].vector, device); - pci_disable_msix(device->pdev); - break; - case msi: - free_irq(device->pdev->irq, device); - pci_disable_msi(device->pdev); - break; - case intx: - free_irq(device->pdev->irq, device); - break; - case none: - dev_warn(&device->pdev->dev, - "call to %s without interrupts setup\n", __func__); - } - device->irq_mode = none; -} - -struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, - void __iomem *iobase) -{ - int err; - struct ioatdma_device *device; - - device = kzalloc(sizeof(*device), GFP_KERNEL); - if (!device) { - err = -ENOMEM; - goto err_kzalloc; - } - device->pdev = pdev; - device->reg_base = iobase; - device->version = readb(device->reg_base + IOAT_VER_OFFSET); - - /* DMA coherent memory pool for DMA descriptor allocations */ - device->dma_pool = pci_pool_create("dma_desc_pool", pdev, - sizeof(struct ioat_dma_descriptor), - 64, 0); - if (!device->dma_pool) { - err = -ENOMEM; - goto err_dma_pool; - } - - device->completion_pool = pci_pool_create("completion_pool", pdev, - sizeof(u64), SMP_CACHE_BYTES, - SMP_CACHE_BYTES); - if (!device->completion_pool) { - err = -ENOMEM; - goto err_completion_pool; - } - - INIT_LIST_HEAD(&device->common.channels); - ioat_dma_enumerate_channels(device); - - device->common.device_alloc_chan_resources = - ioat_dma_alloc_chan_resources; - device->common.device_free_chan_resources = - ioat_dma_free_chan_resources; - device->common.dev = &pdev->dev; - - dma_cap_set(DMA_MEMCPY, device->common.cap_mask); - device->common.device_is_tx_complete = ioat_dma_is_complete; - switch (device->version) { - case IOAT_VER_1_2: - device->common.device_prep_dma_memcpy = ioat1_dma_prep_memcpy; - device->common.device_issue_pending = - ioat1_dma_memcpy_issue_pending; - break; - case IOAT_VER_2_0: - case IOAT_VER_3_0: - device->common.device_prep_dma_memcpy = ioat2_dma_prep_memcpy; - device->common.device_issue_pending = - ioat2_dma_memcpy_issue_pending; - break; - } - - dev_err(&device->pdev->dev, - "Intel(R) I/OAT DMA Engine found," - " %d channels, device version 0x%02x, driver version %s\n", - device->common.chancnt, device->version, IOAT_DMA_VERSION); - - if (!device->common.chancnt) { - dev_err(&device->pdev->dev, - "Intel(R) I/OAT DMA Engine problem found: " - "zero channels detected\n"); - goto err_setup_interrupts; - } - - err = ioat_dma_setup_interrupts(device); - if (err) - goto err_setup_interrupts; - - err = ioat_dma_self_test(device); - if (err) - goto err_self_test; - - ioat_set_tcp_copy_break(device); - - dma_async_device_register(&device->common); - - if (device->version != IOAT_VER_3_0) { - INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog); - schedule_delayed_work(&device->work, - WATCHDOG_DELAY); - } - - return device; - -err_self_test: - ioat_dma_remove_interrupts(device); -err_setup_interrupts: - pci_pool_destroy(device->completion_pool); -err_completion_pool: - pci_pool_destroy(device->dma_pool); -err_dma_pool: - kfree(device); -err_kzalloc: - dev_err(&pdev->dev, - "Intel(R) I/OAT DMA Engine initialization failed\n"); - return NULL; -} - -void ioat_dma_remove(struct ioatdma_device *device) -{ - struct dma_chan *chan, *_chan; - struct ioat_dma_chan *ioat_chan; - - if (device->version != IOAT_VER_3_0) - cancel_delayed_work(&device->work); - - ioat_dma_remove_interrupts(device); - - dma_async_device_unregister(&device->common); - - pci_pool_destroy(device->dma_pool); - pci_pool_destroy(device->completion_pool); - - iounmap(device->reg_base); - pci_release_regions(device->pdev); - pci_disable_device(device->pdev); - - list_for_each_entry_safe(chan, _chan, - &device->common.channels, device_node) { - ioat_chan = to_ioat_chan(chan); - list_del(&chan->device_node); - kfree(ioat_chan); - } - kfree(device); -} - diff --git a/drivers/dma/ioatdma.h b/drivers/dma/ioatdma.h deleted file mode 100644 index a52ff4b..0000000 --- a/drivers/dma/ioatdma.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 - * Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - * The full GNU General Public License is included in this distribution in the - * file called COPYING. - */ -#ifndef IOATDMA_H -#define IOATDMA_H - -#include -#include "ioatdma_hw.h" -#include -#include -#include -#include -#include - -#define IOAT_DMA_VERSION "3.64" - -enum ioat_interrupt { - none = 0, - msix_multi_vector = 1, - msix_single_vector = 2, - msi = 3, - intx = 4, -}; - -#define IOAT_LOW_COMPLETION_MASK 0xffffffc0 -#define IOAT_DMA_DCA_ANY_CPU ~0 -#define IOAT_WATCHDOG_PERIOD (2 * HZ) - - -/** - * struct ioatdma_device - internal representation of a IOAT device - * @pdev: PCI-Express device - * @reg_base: MMIO register space base address - * @dma_pool: for allocating DMA descriptors - * @common: embedded struct dma_device - * @version: version of ioatdma device - * @irq_mode: which style irq to use - * @msix_entries: irq handlers - * @idx: per channel data - */ - -struct ioatdma_device { - struct pci_dev *pdev; - void __iomem *reg_base; - struct pci_pool *dma_pool; - struct pci_pool *completion_pool; - struct dma_device common; - u8 version; - enum ioat_interrupt irq_mode; - struct delayed_work work; - struct msix_entry msix_entries[4]; - struct ioat_dma_chan *idx[4]; -}; - -/** - * struct ioat_dma_chan - internal representation of a DMA channel - */ -struct ioat_dma_chan { - - void __iomem *reg_base; - - dma_cookie_t completed_cookie; - unsigned long last_completion; - unsigned long last_completion_time; - - size_t xfercap; /* XFERCAP register value expanded out */ - - spinlock_t cleanup_lock; - spinlock_t desc_lock; - struct list_head free_desc; - struct list_head used_desc; - unsigned long watchdog_completion; - int watchdog_tcp_cookie; - u32 watchdog_last_tcp_cookie; - struct delayed_work work; - - int pending; - int dmacount; - int desccount; - - struct ioatdma_device *device; - struct dma_chan common; - - dma_addr_t completion_addr; - union { - u64 full; /* HW completion writeback */ - struct { - u32 low; - u32 high; - }; - } *completion_virt; - unsigned long last_compl_desc_addr_hw; - struct tasklet_struct cleanup_task; -}; - -/* wrapper around hardware descriptor format + additional software fields */ - -/** - * struct ioat_desc_sw - wrapper around hardware descriptor - * @hw: hardware DMA descriptor - * @node: this descriptor will either be on the free list, - * or attached to a transaction list (async_tx.tx_list) - * @tx_cnt: number of descriptors required to complete the transaction - * @async_tx: the generic software descriptor for all engines - */ -struct ioat_desc_sw { - struct ioat_dma_descriptor *hw; - struct list_head node; - int tx_cnt; - size_t len; - dma_addr_t src; - dma_addr_t dst; - struct dma_async_tx_descriptor async_tx; -}; - -static inline void ioat_set_tcp_copy_break(struct ioatdma_device *dev) -{ - #ifdef CONFIG_NET_DMA - switch (dev->version) { - case IOAT_VER_1_2: - sysctl_tcp_dma_copybreak = 4096; - break; - case IOAT_VER_2_0: - sysctl_tcp_dma_copybreak = 2048; - break; - case IOAT_VER_3_0: - sysctl_tcp_dma_copybreak = 262144; - break; - } - #endif -} - -#if defined(CONFIG_INTEL_IOATDMA) || defined(CONFIG_INTEL_IOATDMA_MODULE) -struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, - void __iomem *iobase); -void ioat_dma_remove(struct ioatdma_device *device); -struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); -struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); -struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase); -#else -#define ioat_dma_probe(pdev, iobase) NULL -#define ioat_dma_remove(device) do { } while (0) -#define ioat_dca_init(pdev, iobase) NULL -#define ioat2_dca_init(pdev, iobase) NULL -#define ioat3_dca_init(pdev, iobase) NULL -#endif - -#endif /* IOATDMA_H */ diff --git a/drivers/dma/ioatdma_hw.h b/drivers/dma/ioatdma_hw.h deleted file mode 100644 index afa57ee..0000000 --- a/drivers/dma/ioatdma_hw.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 - * Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - * The full GNU General Public License is included in this distribution in the - * file called COPYING. - */ -#ifndef _IOAT_HW_H_ -#define _IOAT_HW_H_ - -/* PCI Configuration Space Values */ -#define IOAT_PCI_VID 0x8086 - -/* CB device ID's */ -#define IOAT_PCI_DID_5000 0x1A38 -#define IOAT_PCI_DID_CNB 0x360B -#define IOAT_PCI_DID_SCNB 0x65FF -#define IOAT_PCI_DID_SNB 0x402F - -#define IOAT_PCI_RID 0x00 -#define IOAT_PCI_SVID 0x8086 -#define IOAT_PCI_SID 0x8086 -#define IOAT_VER_1_2 0x12 /* Version 1.2 */ -#define IOAT_VER_2_0 0x20 /* Version 2.0 */ -#define IOAT_VER_3_0 0x30 /* Version 3.0 */ - -struct ioat_dma_descriptor { - uint32_t size; - uint32_t ctl; - uint64_t src_addr; - uint64_t dst_addr; - uint64_t next; - uint64_t rsv1; - uint64_t rsv2; - uint64_t user1; - uint64_t user2; -}; - -#define IOAT_DMA_DESCRIPTOR_CTL_INT_GN 0x00000001 -#define IOAT_DMA_DESCRIPTOR_CTL_SRC_SN 0x00000002 -#define IOAT_DMA_DESCRIPTOR_CTL_DST_SN 0x00000004 -#define IOAT_DMA_DESCRIPTOR_CTL_CP_STS 0x00000008 -#define IOAT_DMA_DESCRIPTOR_CTL_FRAME 0x00000010 -#define IOAT_DMA_DESCRIPTOR_NUL 0x00000020 -#define IOAT_DMA_DESCRIPTOR_CTL_SP_BRK 0x00000040 -#define IOAT_DMA_DESCRIPTOR_CTL_DP_BRK 0x00000080 -#define IOAT_DMA_DESCRIPTOR_CTL_BNDL 0x00000100 -#define IOAT_DMA_DESCRIPTOR_CTL_DCA 0x00000200 -#define IOAT_DMA_DESCRIPTOR_CTL_BUFHINT 0x00000400 - -#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_CONTEXT 0xFF000000 -#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_DMA 0x00000000 - -#define IOAT_DMA_DESCRIPTOR_CTL_CONTEXT_DCA 0x00000001 -#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_MASK 0xFF000000 - -#endif diff --git a/drivers/dma/ioatdma_registers.h b/drivers/dma/ioatdma_registers.h deleted file mode 100644 index 49bc277..0000000 --- a/drivers/dma/ioatdma_registers.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 - * Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - * The full GNU General Public License is included in this distribution in the - * file called COPYING. - */ -#ifndef _IOAT_REGISTERS_H_ -#define _IOAT_REGISTERS_H_ - -#define IOAT_PCI_DMACTRL_OFFSET 0x48 -#define IOAT_PCI_DMACTRL_DMA_EN 0x00000001 -#define IOAT_PCI_DMACTRL_MSI_EN 0x00000002 - -#define IOAT_PCI_DEVICE_ID_OFFSET 0x02 -#define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148 -#define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184 - -/* MMIO Device Registers */ -#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */ - -#define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */ -#define IOAT_XFERCAP_4KB 12 -#define IOAT_XFERCAP_8KB 13 -#define IOAT_XFERCAP_16KB 14 -#define IOAT_XFERCAP_32KB 15 -#define IOAT_XFERCAP_32GB 0 - -#define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */ -#define IOAT_GENCTRL_DEBUG_EN 0x01 - -#define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */ -#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */ -#define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */ -#define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */ -#define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */ - -#define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */ - -#define IOAT_VER_OFFSET 0x08 /* 8-bit */ -#define IOAT_VER_MAJOR_MASK 0xF0 -#define IOAT_VER_MINOR_MASK 0x0F -#define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4) -#define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK) - -#define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */ - -#define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */ -#define IOAT_INTRDELAY_INT_DELAY_MASK 0x3FFF /* Interrupt Delay Time */ -#define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */ - -#define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ -#define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001 - -#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ - -/* DMA Channel Registers */ -#define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */ -#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 -#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 -#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 -#define IOAT_CHANCTRL_ERR_INT_EN 0x0010 -#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 -#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 -#define IOAT_CHANCTRL_INT_DISABLE 0x0001 - -#define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */ -#define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ -#define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ - - -#define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */ -#define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ -#define IOAT_CHANSTS_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ - ? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET) -#define IOAT1_CHANSTS_OFFSET_LOW 0x04 -#define IOAT2_CHANSTS_OFFSET_LOW 0x08 -#define IOAT_CHANSTS_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ - ? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW) -#define IOAT1_CHANSTS_OFFSET_HIGH 0x08 -#define IOAT2_CHANSTS_OFFSET_HIGH 0x0C -#define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ - ? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH) -#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR ~0x3F -#define IOAT_CHANSTS_SOFT_ERR 0x0000000000000010 -#define IOAT_CHANSTS_UNAFFILIATED_ERR 0x0000000000000008 -#define IOAT_CHANSTS_DMA_TRANSFER_STATUS 0x0000000000000007 -#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE 0x0 -#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE 0x1 -#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_SUSPENDED 0x2 -#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED 0x3 - - - -#define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */ - -#define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */ -#define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000 -#define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */ - -/* CB DCA Memory Space Registers */ -#define IOAT_DCAOFFSET_OFFSET 0x14 -/* CB_BAR + IOAT_DCAOFFSET value */ -#define IOAT_DCA_VER_OFFSET 0x00 -#define IOAT_DCA_VER_MAJOR_MASK 0xF0 -#define IOAT_DCA_VER_MINOR_MASK 0x0F - -#define IOAT_DCA_COMP_OFFSET 0x02 -#define IOAT_DCA_COMP_V1 0x1 - -#define IOAT_FSB_CAPABILITY_OFFSET 0x04 -#define IOAT_FSB_CAPABILITY_PREFETCH 0x1 - -#define IOAT_PCI_CAPABILITY_OFFSET 0x06 -#define IOAT_PCI_CAPABILITY_MEMWR 0x1 - -#define IOAT_FSB_CAP_ENABLE_OFFSET 0x08 -#define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1 - -#define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A -#define IOAT_PCI_CAP_ENABLE_MEMWR 0x1 - -#define IOAT_APICID_TAG_MAP_OFFSET 0x0C -#define IOAT_APICID_TAG_MAP_TAG0 0x0000000F -#define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0 -#define IOAT_APICID_TAG_MAP_TAG1 0x000000F0 -#define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4 -#define IOAT_APICID_TAG_MAP_TAG2 0x00000F00 -#define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8 -#define IOAT_APICID_TAG_MAP_TAG3 0x0000F000 -#define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12 -#define IOAT_APICID_TAG_MAP_TAG4 0x000F0000 -#define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16 -#define IOAT_APICID_TAG_CB2_VALID 0x8080808080 - -#define IOAT_DCA_GREQID_OFFSET 0x10 -#define IOAT_DCA_GREQID_SIZE 0x04 -#define IOAT_DCA_GREQID_MASK 0xFFFF -#define IOAT_DCA_GREQID_IGNOREFUN 0x10000000 -#define IOAT_DCA_GREQID_VALID 0x20000000 -#define IOAT_DCA_GREQID_LASTID 0x80000000 - -#define IOAT3_CSI_CAPABILITY_OFFSET 0x08 -#define IOAT3_CSI_CAPABILITY_PREFETCH 0x1 - -#define IOAT3_PCI_CAPABILITY_OFFSET 0x0A -#define IOAT3_PCI_CAPABILITY_MEMWR 0x1 - -#define IOAT3_CSI_CONTROL_OFFSET 0x0C -#define IOAT3_CSI_CONTROL_PREFETCH 0x1 - -#define IOAT3_PCI_CONTROL_OFFSET 0x0E -#define IOAT3_PCI_CONTROL_MEMWR 0x1 - -#define IOAT3_APICID_TAG_MAP_OFFSET 0x10 -#define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10 -#define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14 - -#define IOAT3_DCA_GREQID_OFFSET 0x02 - -#define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */ -#define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */ -#define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ - ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET) -#define IOAT1_CHAINADDR_OFFSET_LOW 0x0C -#define IOAT2_CHAINADDR_OFFSET_LOW 0x10 -#define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ - ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW) -#define IOAT1_CHAINADDR_OFFSET_HIGH 0x10 -#define IOAT2_CHAINADDR_OFFSET_HIGH 0x14 -#define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ - ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH) - -#define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */ -#define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */ -#define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ - ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET) -#define IOAT_CHANCMD_RESET 0x20 -#define IOAT_CHANCMD_RESUME 0x10 -#define IOAT_CHANCMD_ABORT 0x08 -#define IOAT_CHANCMD_SUSPEND 0x04 -#define IOAT_CHANCMD_APPEND 0x02 -#define IOAT_CHANCMD_START 0x01 - -#define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */ -#define IOAT_CHANCMP_OFFSET_LOW 0x18 -#define IOAT_CHANCMP_OFFSET_HIGH 0x1C - -#define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */ -#define IOAT_CDAR_OFFSET_LOW 0x20 -#define IOAT_CDAR_OFFSET_HIGH 0x24 - -#define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */ -#define IOAT_CHANERR_DMA_TRANSFER_SRC_ADDR_ERR 0x0001 -#define IOAT_CHANERR_DMA_TRANSFER_DEST_ADDR_ERR 0x0002 -#define IOAT_CHANERR_NEXT_DESCRIPTOR_ADDR_ERR 0x0004 -#define IOAT_CHANERR_NEXT_DESCRIPTOR_ALIGNMENT_ERR 0x0008 -#define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010 -#define IOAT_CHANERR_CHANCMD_ERR 0x0020 -#define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040 -#define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080 -#define IOAT_CHANERR_READ_DATA_ERR 0x0100 -#define IOAT_CHANERR_WRITE_DATA_ERR 0x0200 -#define IOAT_CHANERR_DESCRIPTOR_CONTROL_ERR 0x0400 -#define IOAT_CHANERR_DESCRIPTOR_LENGTH_ERR 0x0800 -#define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000 -#define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000 -#define IOAT_CHANERR_SOFT_ERR 0x4000 -#define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000 - -#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ - -#endif /* _IOAT_REGISTERS_H_ */ diff --git a/drivers/idle/i7300_idle.c b/drivers/idle/i7300_idle.c index 949c97f..f2ec724 100644 --- a/drivers/idle/i7300_idle.c +++ b/drivers/idle/i7300_idle.c @@ -29,8 +29,8 @@ #include -#include "../dma/ioatdma_hw.h" -#include "../dma/ioatdma_registers.h" +#include "../dma/ioat/hw.h" +#include "../dma/ioat/registers.h" #define I7300_IDLE_DRIVER_VERSION "1.55" #define I7300_PRINT "i7300_idle:" -- cgit v0.10.2 From 2e83a5c5d2317c386de2880eb43ef0bef8eb1fa9 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Wed, 15 Jul 2009 18:20:38 +0200 Subject: ds2760_battery: delay power supply registration This fixes a race condition I recently introduced with the PMOD feature addition (cef437e3: "w1: ds2760_battery: add support for sleep mode feature"). Postpone the call to power_supply_register() to fix it. Signed-off-by: Daniel Mack Cc: Szabolcs Gyurko Acked-by: Matt Reimer Signed-off-by: Anton Vorontsov diff --git a/drivers/power/ds2760_battery.c b/drivers/power/ds2760_battery.c index 520b5c4..cf07c43 100644 --- a/drivers/power/ds2760_battery.c +++ b/drivers/power/ds2760_battery.c @@ -381,12 +381,6 @@ static int ds2760_battery_probe(struct platform_device *pdev) di->charge_status = POWER_SUPPLY_STATUS_UNKNOWN; - retval = power_supply_register(&pdev->dev, &di->bat); - if (retval) { - dev_err(di->dev, "failed to register battery\n"); - goto batt_failed; - } - /* enable sleep mode feature */ ds2760_battery_read_status(di); status = di->raw[DS2760_STATUS_REG]; @@ -397,6 +391,12 @@ static int ds2760_battery_probe(struct platform_device *pdev) ds2760_battery_write_status(di, status); + retval = power_supply_register(&pdev->dev, &di->bat); + if (retval) { + dev_err(di->dev, "failed to register battery\n"); + goto batt_failed; + } + INIT_DELAYED_WORK(&di->monitor_work, ds2760_battery_work); di->monitor_wqueue = create_singlethread_workqueue(dev_name(&pdev->dev)); if (!di->monitor_wqueue) { -- cgit v0.10.2 From 5c6e9bf2c96e746237516bc8897add67682ee452 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Wed, 15 Jul 2009 18:20:39 +0200 Subject: ds2760_battery: export more features Export POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW and POWER_SUPPLY_PROP_CAPACITY features to the power supply core. Signed-off-by: Daniel Mack Cc: Szabolcs Gyurko Acked-by: Matt Reimer Signed-off-by: Anton Vorontsov diff --git a/drivers/power/ds2760_battery.c b/drivers/power/ds2760_battery.c index cf07c43..f439071 100644 --- a/drivers/power/ds2760_battery.c +++ b/drivers/power/ds2760_battery.c @@ -337,6 +337,12 @@ static int ds2760_battery_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_TEMP: val->intval = di->temp_C; break; + case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW: + val->intval = di->life_sec; + break; + case POWER_SUPPLY_PROP_CAPACITY: + val->intval = di->rem_capacity; + break; default: return -EINVAL; } @@ -353,6 +359,8 @@ static enum power_supply_property ds2760_battery_props[] = { POWER_SUPPLY_PROP_CHARGE_EMPTY, POWER_SUPPLY_PROP_CHARGE_NOW, POWER_SUPPLY_PROP_TEMP, + POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW, + POWER_SUPPLY_PROP_CAPACITY, }; static int ds2760_battery_probe(struct platform_device *pdev) -- cgit v0.10.2 From c1e72193ea3fa02e96bf3aa66006e18d107d0266 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Wed, 15 Jul 2009 18:20:40 +0200 Subject: ds2760_battery: add rated_capacity module parameter For systems where the ds2760 is soldered directly on the PCB, the 'rated capacity' register is not set to anything useful. In order to allow users to bootstrap this value, introduce a new module parameter 'rated_capacity' and use it to write the internal EEPROM in case the value differes from what's been given. Signed-off-by: Daniel Mack Cc: Szabolcs Gyurko Acked-by: Matt Reimer Signed-off-by: Anton Vorontsov diff --git a/drivers/power/ds2760_battery.c b/drivers/power/ds2760_battery.c index f439071..ed0ea5e 100644 --- a/drivers/power/ds2760_battery.c +++ b/drivers/power/ds2760_battery.c @@ -66,6 +66,10 @@ static unsigned int pmod_enabled; module_param(pmod_enabled, bool, 0644); MODULE_PARM_DESC(pmod_enabled, "PMOD enable bit"); +static unsigned int rated_capacity; +module_param(rated_capacity, uint, 0644); +MODULE_PARM_DESC(rated_capacity, "rated battery capacity, 10*mAh or index"); + /* Some batteries have their rated capacity stored a N * 10 mAh, while * others use an index into this table. */ static int rated_capacities[] = { @@ -274,6 +278,17 @@ static void ds2760_battery_write_status(struct ds2760_device_info *di, w1_ds2760_recall_eeprom(di->w1_dev, DS2760_EEPROM_BLOCK1); } +static void ds2760_battery_write_rated_capacity(struct ds2760_device_info *di, + unsigned char rated_capacity) +{ + if (rated_capacity == di->raw[DS2760_RATED_CAPACITY]) + return; + + w1_ds2760_write(di->w1_dev, &rated_capacity, DS2760_RATED_CAPACITY, 1); + w1_ds2760_store_eeprom(di->w1_dev, DS2760_EEPROM_BLOCK1); + w1_ds2760_recall_eeprom(di->w1_dev, DS2760_EEPROM_BLOCK1); +} + static void ds2760_battery_work(struct work_struct *work) { struct ds2760_device_info *di = container_of(work, @@ -399,6 +414,10 @@ static int ds2760_battery_probe(struct platform_device *pdev) ds2760_battery_write_status(di, status); + /* set rated capacity from module param */ + if (rated_capacity) + ds2760_battery_write_rated_capacity(di, rated_capacity); + retval = power_supply_register(&pdev->dev, &di->bat); if (retval) { dev_err(di->dev, "failed to register battery\n"); -- cgit v0.10.2 From 25f2bfa62ae77820a8185734c4a2ab7f3971a2fc Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Wed, 15 Jul 2009 18:20:41 +0200 Subject: ds2760_battery: handle full_active_uAh == 0 case correctly In systems where the battery monitor is not part of the battery pack and is hence not bootstrapped with sane values, the full_active_uAh is likely to be zero. Handle that case by defaulting to the rated_capacity information which can be passed to the driver using the new module parameter. Signed-off-by: Daniel Mack Cc: Szabolcs Gyurko Acked-by: Matt Reimer Signed-off-by: Anton Vorontsov diff --git a/drivers/power/ds2760_battery.c b/drivers/power/ds2760_battery.c index ed0ea5e..2d0e5ed 100644 --- a/drivers/power/ds2760_battery.c +++ b/drivers/power/ds2760_battery.c @@ -172,8 +172,13 @@ static int ds2760_battery_read_status(struct ds2760_device_info *di) di->full_active_uAh = di->raw[DS2760_ACTIVE_FULL] << 8 | di->raw[DS2760_ACTIVE_FULL + 1]; - scale[0] = di->raw[DS2760_ACTIVE_FULL] << 8 | - di->raw[DS2760_ACTIVE_FULL + 1]; + /* If the full_active_uAh value is not given, fall back to the rated + * capacity. This is likely to happen when chips are not part of the + * battery pack and is therefore not bootstrapped. */ + if (di->full_active_uAh == 0) + di->full_active_uAh = di->rated_capacity / 1000L; + + scale[0] = di->full_active_uAh; for (i = 1; i < 5; i++) scale[i] = scale[i - 1] + di->raw[DS2760_ACTIVE_FULL + 2 + i]; -- cgit v0.10.2 From 02d0d2758821c38b2601d34dac544140af09e651 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Wed, 15 Jul 2009 22:57:16 +0200 Subject: ds2760_battery: add current_accum module parameter When connecting a ds2760 to a partly loaded battery the first time, there must be a way to bootstrap the current_accum value. Without that, the current capactity value is bogus until the battery is fully charged for the first time. Signed-off-by: Daniel Mack Cc: Szabolcs Gyurko Cc: Matt Reimer Signed-off-by: Anton Vorontsov diff --git a/drivers/power/ds2760_battery.c b/drivers/power/ds2760_battery.c index 2d0e5ed..f4a9258 100644 --- a/drivers/power/ds2760_battery.c +++ b/drivers/power/ds2760_battery.c @@ -70,6 +70,10 @@ static unsigned int rated_capacity; module_param(rated_capacity, uint, 0644); MODULE_PARM_DESC(rated_capacity, "rated battery capacity, 10*mAh or index"); +static unsigned int current_accum; +module_param(current_accum, uint, 0644); +MODULE_PARM_DESC(current_accum, "current accumulator value"); + /* Some batteries have their rated capacity stored a N * 10 mAh, while * others use an index into this table. */ static int rated_capacities[] = { @@ -215,6 +219,22 @@ static int ds2760_battery_read_status(struct ds2760_device_info *di) return 0; } +static void ds2760_battery_set_current_accum(struct ds2760_device_info *di, + unsigned int acr_val) +{ + unsigned char acr[2]; + + /* acr is in units of 0.25 mAh */ + acr_val *= 4L; + acr_val /= 1000; + + acr[0] = acr_val >> 8; + acr[1] = acr_val & 0xff; + + if (w1_ds2760_write(di->w1_dev, acr, DS2760_CURRENT_ACCUM_MSB, 2) < 2) + dev_warn(di->dev, "ACR write failed\n"); +} + static void ds2760_battery_update_status(struct ds2760_device_info *di) { int old_charge_status = di->charge_status; @@ -246,21 +266,9 @@ static void ds2760_battery_update_status(struct ds2760_device_info *di) if (di->full_counter < 2) { di->charge_status = POWER_SUPPLY_STATUS_CHARGING; } else { - unsigned char acr[2]; - int acr_val; - - /* acr is in units of 0.25 mAh */ - acr_val = di->full_active_uAh * 4L / 1000; - - acr[0] = acr_val >> 8; - acr[1] = acr_val & 0xff; - - if (w1_ds2760_write(di->w1_dev, acr, - DS2760_CURRENT_ACCUM_MSB, 2) < 2) - dev_warn(di->dev, - "ACR reset failed\n"); - di->charge_status = POWER_SUPPLY_STATUS_FULL; + ds2760_battery_set_current_accum(di, + di->full_active_uAh); } } } else { @@ -423,6 +431,11 @@ static int ds2760_battery_probe(struct platform_device *pdev) if (rated_capacity) ds2760_battery_write_rated_capacity(di, rated_capacity); + /* set current accumulator if given as parameter. + * this should only be done for bootstrapping the value */ + if (current_accum) + ds2760_battery_set_current_accum(di, current_accum); + retval = power_supply_register(&pdev->dev, &di->bat); if (retval) { dev_err(di->dev, "failed to register battery\n"); -- cgit v0.10.2 From ff3417e7effe57cc002a8882a48bcb8e1a7e7267 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 30 Jul 2009 17:42:31 +0400 Subject: power_supply: EXPORT_SYMBOL cleanups While I'm at it, cleanup the power supply code so that EXPORT_SYMBOL_GPL appears directly after the symbole declaration. checkpatch.pl wants it that way. Signed-off-by: Daniel Mack Cc: Ian Molton Cc: Matt Reimer Signed-off-by: Anton Vorontsov diff --git a/drivers/power/power_supply_core.c b/drivers/power/power_supply_core.c index 55200404..12cd6e3 100644 --- a/drivers/power/power_supply_core.c +++ b/drivers/power/power_supply_core.c @@ -18,7 +18,9 @@ #include #include "power_supply.h" +/* exported for the APM Power driver, APM emulation */ struct class *power_supply_class; +EXPORT_SYMBOL_GPL(power_supply_class); static int __power_supply_changed_work(struct device *dev, void *data) { @@ -55,6 +57,7 @@ void power_supply_changed(struct power_supply *psy) schedule_work(&psy->changed_work); } +EXPORT_SYMBOL_GPL(power_supply_changed); static int __power_supply_am_i_supplied(struct device *dev, void *data) { @@ -86,6 +89,7 @@ int power_supply_am_i_supplied(struct power_supply *psy) return error; } +EXPORT_SYMBOL_GPL(power_supply_am_i_supplied); static int __power_supply_is_system_supplied(struct device *dev, void *data) { @@ -110,6 +114,7 @@ int power_supply_is_system_supplied(void) return error; } +EXPORT_SYMBOL_GPL(power_supply_is_system_supplied); int power_supply_register(struct device *parent, struct power_supply *psy) { @@ -144,6 +149,7 @@ dev_create_failed: success: return rc; } +EXPORT_SYMBOL_GPL(power_supply_register); void power_supply_unregister(struct power_supply *psy) { @@ -152,6 +158,7 @@ void power_supply_unregister(struct power_supply *psy) power_supply_remove_attrs(psy); device_unregister(psy->dev); } +EXPORT_SYMBOL_GPL(power_supply_unregister); static int __init power_supply_class_init(void) { @@ -170,15 +177,6 @@ static void __exit power_supply_class_exit(void) class_destroy(power_supply_class); } -EXPORT_SYMBOL_GPL(power_supply_changed); -EXPORT_SYMBOL_GPL(power_supply_am_i_supplied); -EXPORT_SYMBOL_GPL(power_supply_is_system_supplied); -EXPORT_SYMBOL_GPL(power_supply_register); -EXPORT_SYMBOL_GPL(power_supply_unregister); - -/* exported for the APM Power driver, APM emulation */ -EXPORT_SYMBOL_GPL(power_supply_class); - subsys_initcall(power_supply_class_init); module_exit(power_supply_class_exit); -- cgit v0.10.2 From e5f5ccb646bc6009572b5c23201b5e81638ff150 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 23 Jul 2009 20:35:53 +0200 Subject: power_supply: get_by_name and set_charged functionality This adds a function that indicates that a battery is fully charged. It also includes functions to get a power_supply device from the class of registered devices by name reference. These can be used to find a specific battery to call power_supply_set_battery_charged() on. Some battery drivers might need this information to calibrate themselves. Signed-off-by: Daniel Mack Cc: Ian Molton Cc: Anton Vorontsov Cc: Matt Reimer Signed-off-by: Anton Vorontsov diff --git a/drivers/power/power_supply_core.c b/drivers/power/power_supply_core.c index 12cd6e3..cce75b4 100644 --- a/drivers/power/power_supply_core.c +++ b/drivers/power/power_supply_core.c @@ -116,6 +116,34 @@ int power_supply_is_system_supplied(void) } EXPORT_SYMBOL_GPL(power_supply_is_system_supplied); +int power_supply_set_battery_charged(struct power_supply *psy) +{ + if (psy->type == POWER_SUPPLY_TYPE_BATTERY && psy->set_charged) { + psy->set_charged(psy); + return 0; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(power_supply_set_battery_charged); + +static int power_supply_match_device_by_name(struct device *dev, void *data) +{ + const char *name = data; + struct power_supply *psy = dev_get_drvdata(dev); + + return strcmp(psy->name, name) == 0; +} + +struct power_supply *power_supply_get_by_name(char *name) +{ + struct device *dev = class_find_device(power_supply_class, NULL, name, + power_supply_match_device_by_name); + + return dev ? dev_get_drvdata(dev) : NULL; +} +EXPORT_SYMBOL_GPL(power_supply_get_by_name); + int power_supply_register(struct device *parent, struct power_supply *psy) { int rc = 0; diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 4c7c6fc..b5d096d 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -144,6 +144,7 @@ struct power_supply { enum power_supply_property psp, union power_supply_propval *val); void (*external_power_changed)(struct power_supply *psy); + void (*set_charged)(struct power_supply *psy); /* For APM emulation, think legacy userspace. */ int use_for_apm; @@ -183,8 +184,10 @@ struct power_supply_info { int use_for_apm; }; +extern struct power_supply *power_supply_get_by_name(char *name); extern void power_supply_changed(struct power_supply *psy); extern int power_supply_am_i_supplied(struct power_supply *psy); +extern int power_supply_set_battery_charged(struct power_supply *psy); #if defined(CONFIG_POWER_SUPPLY) || defined(CONFIG_POWER_SUPPLY_MODULE) extern int power_supply_is_system_supplied(void); -- cgit v0.10.2 From 8d631ccff8d90fce77b42f01b3872595c599cbf9 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 23 Jul 2009 20:35:54 +0200 Subject: ds2760_battery: implement set_charged() feature The ds2760's internal current meter is not reliable enough as it has an inacurracy of around ~15%. Without any correction for that error, the current accumulator is couting up all the time, even though the battery is already fully charged and hence destroys the static information. The longer it is connected, the worse is the aberration. Fortunately, this can be corrected by the DS2760_CURRENT_OFFSET_BIAS register. Using the external power_supply_set_battery_charged() function, this register is now gauging the measurement. A delayed work is used to debounce flaky GPIO signals and to let the current value settle. Also see Maxim's application note AN4188. Signed-off-by: Daniel Mack Cc: Szabolcs Gyurko Cc: Matt Reimer Cc: Anton Vorontsov Signed-off-by: Anton Vorontsov diff --git a/drivers/power/ds2760_battery.c b/drivers/power/ds2760_battery.c index f4a9258..1bb8498 100644 --- a/drivers/power/ds2760_battery.c +++ b/drivers/power/ds2760_battery.c @@ -56,6 +56,7 @@ struct ds2760_device_info { struct device *w1_dev; struct workqueue_struct *monitor_wqueue; struct delayed_work monitor_work; + struct delayed_work set_charged_work; }; static unsigned int cache_time = 1000; @@ -327,6 +328,52 @@ static void ds2760_battery_external_power_changed(struct power_supply *psy) queue_delayed_work(di->monitor_wqueue, &di->monitor_work, HZ/10); } + +static void ds2760_battery_set_charged_work(struct work_struct *work) +{ + char bias; + struct ds2760_device_info *di = container_of(work, + struct ds2760_device_info, set_charged_work.work); + + dev_dbg(di->dev, "%s\n", __func__); + + ds2760_battery_read_status(di); + + /* When we get notified by external circuitry that the battery is + * considered fully charged now, we know that there is no current + * flow any more. However, the ds2760's internal current meter is + * too inaccurate to rely on - spec say something ~15% failure. + * Hence, we use the current offset bias register to compensate + * that error. + */ + + if (!power_supply_am_i_supplied(&di->bat)) + return; + + bias = (signed char) di->current_raw + + (signed char) di->raw[DS2760_CURRENT_OFFSET_BIAS]; + + dev_dbg(di->dev, "%s: bias = %d\n", __func__, bias); + + w1_ds2760_write(di->w1_dev, &bias, DS2760_CURRENT_OFFSET_BIAS, 1); + w1_ds2760_store_eeprom(di->w1_dev, DS2760_EEPROM_BLOCK1); + w1_ds2760_recall_eeprom(di->w1_dev, DS2760_EEPROM_BLOCK1); + + /* Write to the di->raw[] buffer directly - the CURRENT_OFFSET_BIAS + * value won't be read back by ds2760_battery_read_status() */ + di->raw[DS2760_CURRENT_OFFSET_BIAS] = bias; +} + +static void ds2760_battery_set_charged(struct power_supply *psy) +{ + struct ds2760_device_info *di = to_ds2760_device_info(psy); + + /* postpone the actual work by 20 secs. This is for debouncing GPIO + * signals and to let the current value settle. See AN4188. */ + cancel_delayed_work(&di->set_charged_work); + queue_delayed_work(di->monitor_wqueue, &di->set_charged_work, HZ * 20); +} + static int ds2760_battery_get_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) @@ -412,6 +459,7 @@ static int ds2760_battery_probe(struct platform_device *pdev) di->bat.properties = ds2760_battery_props; di->bat.num_properties = ARRAY_SIZE(ds2760_battery_props); di->bat.get_property = ds2760_battery_get_property; + di->bat.set_charged = ds2760_battery_set_charged; di->bat.external_power_changed = ds2760_battery_external_power_changed; @@ -443,6 +491,8 @@ static int ds2760_battery_probe(struct platform_device *pdev) } INIT_DELAYED_WORK(&di->monitor_work, ds2760_battery_work); + INIT_DELAYED_WORK(&di->set_charged_work, + ds2760_battery_set_charged_work); di->monitor_wqueue = create_singlethread_workqueue(dev_name(&pdev->dev)); if (!di->monitor_wqueue) { retval = -ESRCH; @@ -467,6 +517,8 @@ static int ds2760_battery_remove(struct platform_device *pdev) cancel_rearming_delayed_workqueue(di->monitor_wqueue, &di->monitor_work); + cancel_rearming_delayed_workqueue(di->monitor_wqueue, + &di->set_charged_work); destroy_workqueue(di->monitor_wqueue); power_supply_unregister(&di->bat); -- cgit v0.10.2 From 8e0af5141ab950b78b3ebbfaded5439dcf8b3a8d Mon Sep 17 00:00:00 2001 From: Shaohua Li Date: Mon, 27 Jul 2009 18:11:02 -0400 Subject: ACPI: create Processor Aggregator Device driver ACPI 4.0 created the logical "processor aggregator device" as a mechinism for platforms to ask the OS to force otherwise busy processors to enter (power saving) idle. The intent is to lower power consumption to ride-out transient electrical and thermal emergencies, rather than powering off the server. On platforms that can save more power/performance via P-states, the platform will first exhaust P-states before forcing idle. However, the relative benefit of P-states vs. idle states is platform dependent, and thus this driver need not know or care about it. This driver does not use the kernel's CPU hot-plug mechanism because after the transient emergency is over, the system must be returned to its normal state, and hotplug would permanently break both cpusets and binding. So to force idle, the driver creates a power saving thread. The scheduler will migrate the thread to the preferred CPU. The thread has max priority and has SCHED_RR policy, so it can occupy one CPU. To save power, the thread will invoke the deep C-state entry instructions. To avoid starvation, the thread will sleep 5% of the time time for every second (current RT scheduler has threshold to avoid starvation, but if other CPUs are idle, the CPU can borrow CPU timer from other, which makes the mechanism not work here) Vaidyanathan Srinivasan has proposed scheduler enhancements to allow injecting idle time into the system. This driver doesn't depend on those enhancements, but could cut over to them when they are available. Peter Z. does not favor upstreaming this driver until the those scheduler enhancements are in place. However, we favor upstreaming this driver now because it is useful now, and can be enhanced over time. Signed-off-by: Shaohua Li NACKed-by: Peter Zijlstra Cc: Vaidyanathan Srinivasan Signed-off-by: Len Brown diff --git a/MAINTAINERS b/MAINTAINERS index ebc2691..082df56 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -288,6 +288,14 @@ L: linux-pci@vger.kernel.org S: Supported F: drivers/pci/hotplug/acpi* +ACPI PROCESSOR AGGREGATOR DRIVER +P: Shaohua Li +M: shaohua.li@intel.com +L: linux-acpi@vger.kernel.org +W: http://www.lesswatts.org/projects/acpi/ +S: Supported +F: drivers/acpi/acpi_pad.c + ACPI THERMAL DRIVER P: Zhang Rui M: rui.zhang@intel.com diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index 7ec7d88..13531ed 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -196,6 +196,17 @@ config ACPI_HOTPLUG_CPU select ACPI_CONTAINER default y +config ACPI_PROCESSOR_AGGREGATOR + tristate "Processor Aggregator" + depends on ACPI_PROCESSOR + depends on EXPERIMENTAL + help + ACPI 4.0 defines processor Aggregator, which enables OS to perform + specfic processor configuration and control that applies to all + processors in the platform. Currently only logical processor idling + is defined, which is to reduce power consumption. This driver + support the new device. + config ACPI_THERMAL tristate "Thermal Zone" depends on ACPI_PROCESSOR diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index 03a985b..8dae61c 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -61,3 +61,5 @@ obj-$(CONFIG_ACPI_SBS) += sbs.o processor-y := processor_core.o processor_throttling.o processor-y += processor_idle.o processor_thermal.o processor-$(CONFIG_CPU_FREQ) += processor_perflib.o + +obj-$(CONFIG_ACPI_PROCESSOR_AGGREGATOR) += acpi_pad.o diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c new file mode 100644 index 0000000..0d2cdb8 --- /dev/null +++ b/drivers/acpi/acpi_pad.c @@ -0,0 +1,514 @@ +/* + * acpi_pad.c ACPI Processor Aggregator Driver + * + * Copyright (c) 2009, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ACPI_PROCESSOR_AGGREGATOR_CLASS "processor_aggregator" +#define ACPI_PROCESSOR_AGGREGATOR_DEVICE_NAME "Processor Aggregator" +#define ACPI_PROCESSOR_AGGREGATOR_NOTIFY 0x80 +static DEFINE_MUTEX(isolated_cpus_lock); + +#define MWAIT_SUBSTATE_MASK (0xf) +#define MWAIT_CSTATE_MASK (0xf) +#define MWAIT_SUBSTATE_SIZE (4) +#define CPUID_MWAIT_LEAF (5) +#define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1) +#define CPUID5_ECX_INTERRUPT_BREAK (0x2) +static unsigned long power_saving_mwait_eax; +static void power_saving_mwait_init(void) +{ + unsigned int eax, ebx, ecx, edx; + unsigned int highest_cstate = 0; + unsigned int highest_subcstate = 0; + int i; + + if (!boot_cpu_has(X86_FEATURE_MWAIT)) + return; + if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) + return; + + cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); + + if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || + !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) + return; + + edx >>= MWAIT_SUBSTATE_SIZE; + for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { + if (edx & MWAIT_SUBSTATE_MASK) { + highest_cstate = i; + highest_subcstate = edx & MWAIT_SUBSTATE_MASK; + } + } + power_saving_mwait_eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | + (highest_subcstate - 1); + + for_each_online_cpu(i) + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &i); + +#if defined(CONFIG_GENERIC_TIME) && defined(CONFIG_X86) + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_AMD: + case X86_VENDOR_INTEL: + /* + * AMD Fam10h TSC will tick in all + * C/P/S0/S1 states when this bit is set. + */ + if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) + return; + + /*FALL THROUGH*/ + default: + /* TSC could halt in idle, so notify users */ + mark_tsc_unstable("TSC halts in idle"); + } +#endif +} + +static unsigned long cpu_weight[NR_CPUS]; +static int tsk_in_cpu[NR_CPUS] = {[0 ... NR_CPUS-1] = -1}; +static DECLARE_BITMAP(pad_busy_cpus_bits, NR_CPUS); +static void round_robin_cpu(unsigned int tsk_index) +{ + struct cpumask *pad_busy_cpus = to_cpumask(pad_busy_cpus_bits); + cpumask_var_t tmp; + int cpu; + unsigned long min_weight = -1, preferred_cpu; + + if (!alloc_cpumask_var(&tmp, GFP_KERNEL)) + return; + + mutex_lock(&isolated_cpus_lock); + cpumask_clear(tmp); + for_each_cpu(cpu, pad_busy_cpus) + cpumask_or(tmp, tmp, topology_thread_cpumask(cpu)); + cpumask_andnot(tmp, cpu_online_mask, tmp); + /* avoid HT sibilings if possible */ + if (cpumask_empty(tmp)) + cpumask_andnot(tmp, cpu_online_mask, pad_busy_cpus); + if (cpumask_empty(tmp)) { + mutex_unlock(&isolated_cpus_lock); + return; + } + for_each_cpu(cpu, tmp) { + if (cpu_weight[cpu] < min_weight) { + min_weight = cpu_weight[cpu]; + preferred_cpu = cpu; + } + } + + if (tsk_in_cpu[tsk_index] != -1) + cpumask_clear_cpu(tsk_in_cpu[tsk_index], pad_busy_cpus); + tsk_in_cpu[tsk_index] = preferred_cpu; + cpumask_set_cpu(preferred_cpu, pad_busy_cpus); + cpu_weight[preferred_cpu]++; + mutex_unlock(&isolated_cpus_lock); + + set_cpus_allowed_ptr(current, cpumask_of(preferred_cpu)); +} + +static void exit_round_robin(unsigned int tsk_index) +{ + struct cpumask *pad_busy_cpus = to_cpumask(pad_busy_cpus_bits); + cpumask_clear_cpu(tsk_in_cpu[tsk_index], pad_busy_cpus); + tsk_in_cpu[tsk_index] = -1; +} + +static unsigned int idle_pct = 5; /* percentage */ +static unsigned int round_robin_time = 10; /* second */ +static int power_saving_thread(void *data) +{ + struct sched_param param = {.sched_priority = 1}; + int do_sleep; + unsigned int tsk_index = (unsigned long)data; + u64 last_jiffies = 0; + + sched_setscheduler(current, SCHED_RR, ¶m); + + while (!kthread_should_stop()) { + int cpu; + u64 expire_time; + + try_to_freeze(); + + /* round robin to cpus */ + if (last_jiffies + round_robin_time * HZ < jiffies) { + last_jiffies = jiffies; + round_robin_cpu(tsk_index); + } + + do_sleep = 0; + + current_thread_info()->status &= ~TS_POLLING; + /* + * TS_POLLING-cleared state must be visible before we test + * NEED_RESCHED: + */ + smp_mb(); + + expire_time = jiffies + HZ * (100 - idle_pct) / 100; + + while (!need_resched()) { + local_irq_disable(); + cpu = smp_processor_id(); + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, + &cpu); + stop_critical_timings(); + + __monitor((void *)¤t_thread_info()->flags, 0, 0); + smp_mb(); + if (!need_resched()) + __mwait(power_saving_mwait_eax, 1); + + start_critical_timings(); + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, + &cpu); + local_irq_enable(); + + if (jiffies > expire_time) { + do_sleep = 1; + break; + } + } + + current_thread_info()->status |= TS_POLLING; + + /* + * current sched_rt has threshold for rt task running time. + * When a rt task uses 95% CPU time, the rt thread will be + * scheduled out for 5% CPU time to not starve other tasks. But + * the mechanism only works when all CPUs have RT task running, + * as if one CPU hasn't RT task, RT task from other CPUs will + * borrow CPU time from this CPU and cause RT task use > 95% + * CPU time. To make 'avoid staration' work, takes a nap here. + */ + if (do_sleep) + schedule_timeout_killable(HZ * idle_pct / 100); + } + + exit_round_robin(tsk_index); + return 0; +} + +static struct task_struct *ps_tsks[NR_CPUS]; +static unsigned int ps_tsk_num; +static int create_power_saving_task(void) +{ + ps_tsks[ps_tsk_num] = kthread_run(power_saving_thread, + (void *)(unsigned long)ps_tsk_num, + "power_saving/%d", ps_tsk_num); + if (ps_tsks[ps_tsk_num]) { + ps_tsk_num++; + return 0; + } + return -EINVAL; +} + +static void destroy_power_saving_task(void) +{ + if (ps_tsk_num > 0) { + ps_tsk_num--; + kthread_stop(ps_tsks[ps_tsk_num]); + } +} + +static void set_power_saving_task_num(unsigned int num) +{ + if (num > ps_tsk_num) { + while (ps_tsk_num < num) { + if (create_power_saving_task()) + return; + } + } else if (num < ps_tsk_num) { + while (ps_tsk_num > num) + destroy_power_saving_task(); + } +} + +static int acpi_pad_idle_cpus(unsigned int num_cpus) +{ + get_online_cpus(); + + num_cpus = min_t(unsigned int, num_cpus, num_online_cpus()); + set_power_saving_task_num(num_cpus); + + put_online_cpus(); + return 0; +} + +static uint32_t acpi_pad_idle_cpus_num(void) +{ + return ps_tsk_num; +} + +static ssize_t acpi_pad_rrtime_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + unsigned long num; + if (strict_strtoul(buf, 0, &num)) + return -EINVAL; + if (num < 1 || num >= 100) + return -EINVAL; + mutex_lock(&isolated_cpus_lock); + round_robin_time = num; + mutex_unlock(&isolated_cpus_lock); + return count; +} + +static ssize_t acpi_pad_rrtime_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%d", round_robin_time); +} +static DEVICE_ATTR(rrtime, S_IRUGO|S_IWUSR, + acpi_pad_rrtime_show, + acpi_pad_rrtime_store); + +static ssize_t acpi_pad_idlepct_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + unsigned long num; + if (strict_strtoul(buf, 0, &num)) + return -EINVAL; + if (num < 1 || num >= 100) + return -EINVAL; + mutex_lock(&isolated_cpus_lock); + idle_pct = num; + mutex_unlock(&isolated_cpus_lock); + return count; +} + +static ssize_t acpi_pad_idlepct_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%d", idle_pct); +} +static DEVICE_ATTR(idlepct, S_IRUGO|S_IWUSR, + acpi_pad_idlepct_show, + acpi_pad_idlepct_store); + +static ssize_t acpi_pad_idlecpus_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + unsigned long num; + if (strict_strtoul(buf, 0, &num)) + return -EINVAL; + mutex_lock(&isolated_cpus_lock); + acpi_pad_idle_cpus(num); + mutex_unlock(&isolated_cpus_lock); + return count; +} + +static ssize_t acpi_pad_idlecpus_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return cpumask_scnprintf(buf, PAGE_SIZE, + to_cpumask(pad_busy_cpus_bits)); +} +static DEVICE_ATTR(idlecpus, S_IRUGO|S_IWUSR, + acpi_pad_idlecpus_show, + acpi_pad_idlecpus_store); + +static int acpi_pad_add_sysfs(struct acpi_device *device) +{ + int result; + + result = device_create_file(&device->dev, &dev_attr_idlecpus); + if (result) + return -ENODEV; + result = device_create_file(&device->dev, &dev_attr_idlepct); + if (result) { + device_remove_file(&device->dev, &dev_attr_idlecpus); + return -ENODEV; + } + result = device_create_file(&device->dev, &dev_attr_rrtime); + if (result) { + device_remove_file(&device->dev, &dev_attr_idlecpus); + device_remove_file(&device->dev, &dev_attr_idlepct); + return -ENODEV; + } + return 0; +} + +static void acpi_pad_remove_sysfs(struct acpi_device *device) +{ + device_remove_file(&device->dev, &dev_attr_idlecpus); + device_remove_file(&device->dev, &dev_attr_idlepct); + device_remove_file(&device->dev, &dev_attr_rrtime); +} + +/* Query firmware how many CPUs should be idle */ +static int acpi_pad_pur(acpi_handle handle, int *num_cpus) +{ + struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; + acpi_status status; + union acpi_object *package; + int rev, num, ret = -EINVAL; + + status = acpi_evaluate_object(handle, "_PUR", NULL, &buffer); + if (ACPI_FAILURE(status)) + return -EINVAL; + package = buffer.pointer; + if (package->type != ACPI_TYPE_PACKAGE || package->package.count != 2) + goto out; + rev = package->package.elements[0].integer.value; + num = package->package.elements[1].integer.value; + if (rev != 1) + goto out; + *num_cpus = num; + ret = 0; +out: + kfree(buffer.pointer); + return ret; +} + +/* Notify firmware how many CPUs are idle */ +static void acpi_pad_ost(acpi_handle handle, int stat, + uint32_t idle_cpus) +{ + union acpi_object params[3] = { + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_BUFFER,}, + }; + struct acpi_object_list arg_list = {3, params}; + + params[0].integer.value = ACPI_PROCESSOR_AGGREGATOR_NOTIFY; + params[1].integer.value = stat; + params[2].buffer.length = 4; + params[2].buffer.pointer = (void *)&idle_cpus; + acpi_evaluate_object(handle, "_OST", &arg_list, NULL); +} + +static void acpi_pad_handle_notify(acpi_handle handle) +{ + int num_cpus, ret; + uint32_t idle_cpus; + + mutex_lock(&isolated_cpus_lock); + if (acpi_pad_pur(handle, &num_cpus)) { + mutex_unlock(&isolated_cpus_lock); + return; + } + ret = acpi_pad_idle_cpus(num_cpus); + idle_cpus = acpi_pad_idle_cpus_num(); + if (!ret) + acpi_pad_ost(handle, 0, idle_cpus); + else + acpi_pad_ost(handle, 1, 0); + mutex_unlock(&isolated_cpus_lock); +} + +static void acpi_pad_notify(acpi_handle handle, u32 event, + void *data) +{ + struct acpi_device *device = data; + + switch (event) { + case ACPI_PROCESSOR_AGGREGATOR_NOTIFY: + acpi_pad_handle_notify(handle); + acpi_bus_generate_proc_event(device, event, 0); + acpi_bus_generate_netlink_event(device->pnp.device_class, + dev_name(&device->dev), event, 0); + break; + default: + printk(KERN_WARNING"Unsupported event [0x%x]\n", event); + break; + } +} + +static int acpi_pad_add(struct acpi_device *device) +{ + acpi_status status; + + strcpy(acpi_device_name(device), ACPI_PROCESSOR_AGGREGATOR_DEVICE_NAME); + strcpy(acpi_device_class(device), ACPI_PROCESSOR_AGGREGATOR_CLASS); + + if (acpi_pad_add_sysfs(device)) + return -ENODEV; + + status = acpi_install_notify_handler(device->handle, + ACPI_DEVICE_NOTIFY, acpi_pad_notify, device); + if (ACPI_FAILURE(status)) { + acpi_pad_remove_sysfs(device); + return -ENODEV; + } + + return 0; +} + +static int acpi_pad_remove(struct acpi_device *device, + int type) +{ + mutex_lock(&isolated_cpus_lock); + acpi_pad_idle_cpus(0); + mutex_unlock(&isolated_cpus_lock); + + acpi_remove_notify_handler(device->handle, + ACPI_DEVICE_NOTIFY, acpi_pad_notify); + acpi_pad_remove_sysfs(device); + return 0; +} + +static const struct acpi_device_id pad_device_ids[] = { + {"ACPI000C", 0}, + {"", 0}, +}; +MODULE_DEVICE_TABLE(acpi, pad_device_ids); + +static struct acpi_driver acpi_pad_driver = { + .name = "processor_aggregator", + .class = ACPI_PROCESSOR_AGGREGATOR_CLASS, + .ids = pad_device_ids, + .ops = { + .add = acpi_pad_add, + .remove = acpi_pad_remove, + }, +}; + +static int __init acpi_pad_init(void) +{ + power_saving_mwait_init(); + if (power_saving_mwait_eax == 0) + return -EINVAL; + + return acpi_bus_register_driver(&acpi_pad_driver); +} + +static void __exit acpi_pad_exit(void) +{ + acpi_bus_unregister_driver(&acpi_pad_driver); +} + +module_init(acpi_pad_init); +module_exit(acpi_pad_exit); +MODULE_AUTHOR("Shaohua Li"); +MODULE_DESCRIPTION("ACPI Processor Aggregator Driver"); +MODULE_LICENSE("GPL"); -- cgit v0.10.2 From 67638e4043083cdc6f10386a75fef87ba46eecb3 Mon Sep 17 00:00:00 2001 From: OGAWA Hirofumi Date: Sat, 1 Aug 2009 21:30:31 +0900 Subject: fat/nls: Fix handling of utf8 invalid char With utf8 option, vfat allowed the duplicated filenames. Normal nls returns -EINVAL for invalid char. But utf8s_to_utf16s() skipped the invalid char historically. So, this changes the utf8s_to_utf16s() directly to return -EINVAL for invalid char, because vfat is only user of it. mkdir /mnt/fatfs FILENAME=`echo -ne "invalidutf8char_\\0341_endofchar"` echo "Using filename: $FILENAME" dd if=/dev/zero of=fatfs bs=512 count=128 mkdosfs -F 32 fatfs mount -o loop,utf8 fatfs /mnt/fatfs touch "/mnt/fatfs/$FILENAME" umount /mnt/fatfs mount -o loop,utf8 fatfs /mnt/fatfs touch "/mnt/fatfs/$FILENAME" ls -l /mnt/fatfs umount /mnt/fatfs ---- And the output is: Using filename: invalidutf8char_\0341_endofchar 128+0 records in 128+0 records out 65536 bytes (66 kB) copied, 0.000388118 s, 169 MB/s mkdosfs 2.11 (12 Mar 2005) total 0 -rwxr-xr-x 1 root root 0 Jun 28 19:46 invalidutf8char__endofchar -rwxr-xr-x 1 root root 0 Jun 28 19:46 invalidutf8char__endofchar Tested-by: Marton Balint Signed-off-by: OGAWA Hirofumi diff --git a/fs/fat/namei_vfat.c b/fs/fat/namei_vfat.c index cb6e835..f565f24 100644 --- a/fs/fat/namei_vfat.c +++ b/fs/fat/namei_vfat.c @@ -499,17 +499,10 @@ xlate_to_uni(const unsigned char *name, int len, unsigned char *outname, int charlen; if (utf8) { - int name_len = strlen(name); - - *outlen = utf8s_to_utf16s(name, PATH_MAX, (wchar_t *) outname); - - /* - * We stripped '.'s before and set len appropriately, - * but utf8s_to_utf16s doesn't care about len - */ - *outlen -= (name_len - len); - - if (*outlen > 255) + *outlen = utf8s_to_utf16s(name, len, (wchar_t *)outname); + if (*outlen < 0) + return *outlen; + else if (*outlen > 255) return -ENAMETOOLONG; op = &outname[*outlen * sizeof(wchar_t)]; diff --git a/fs/nls/nls_base.c b/fs/nls/nls_base.c index 477d37d..b25c218 100644 --- a/fs/nls/nls_base.c +++ b/fs/nls/nls_base.c @@ -124,10 +124,10 @@ int utf8s_to_utf16s(const u8 *s, int len, wchar_t *pwcs) while (*s && len > 0) { if (*s & 0x80) { size = utf8_to_utf32(s, len, &u); - if (size < 0) { - /* Ignore character and move on */ - size = 1; - } else if (u >= PLANE_SIZE) { + if (size < 0) + return -EINVAL; + + if (u >= PLANE_SIZE) { u -= PLANE_SIZE; *op++ = (wchar_t) (SURROGATE_PAIR | ((u >> 10) & SURROGATE_BITS)); -- cgit v0.10.2 From 955234755ce4a2c33cfc558912aa8f2148cc1fc6 Mon Sep 17 00:00:00 2001 From: Paul Wise Date: Sat, 1 Aug 2009 21:30:31 +0900 Subject: vfat: change the default from shortname=lower to shortname=mixed Because, with "shortname=lower", copying one FAT filesystem tree to another FAT filesystem tree using Linux results in semantically different filesystems. (E.g.: Filenames which were once "all uppercase" are now "all lowercase"). So, this changes the default of "shortname=lower" to "shortname=mixed". Signed-off-by: Paul Wise [change fat_show_options()] Signed-off-by: OGAWA Hirofumi diff --git a/Documentation/filesystems/vfat.txt b/Documentation/filesystems/vfat.txt index b58b84b..eed520f 100644 --- a/Documentation/filesystems/vfat.txt +++ b/Documentation/filesystems/vfat.txt @@ -102,7 +102,7 @@ shortname=lower|win95|winnt|mixed winnt: emulate the Windows NT rule for display/create. mixed: emulate the Windows NT rule for display, emulate the Windows 95 rule for create. - Default setting is `lower'. + Default setting is `mixed'. tz=UTC -- Interpret timestamps as UTC rather than local time. This option disables the conversion of timestamps diff --git a/fs/fat/inode.c b/fs/fat/inode.c index 8970d8c..63a5c1a 100644 --- a/fs/fat/inode.c +++ b/fs/fat/inode.c @@ -820,7 +820,7 @@ static int fat_show_options(struct seq_file *m, struct vfsmount *mnt) seq_puts(m, ",shortname=mixed"); break; case VFAT_SFN_DISPLAY_LOWER | VFAT_SFN_CREATE_WIN95: - /* seq_puts(m, ",shortname=lower"); */ + seq_puts(m, ",shortname=lower"); break; default: seq_puts(m, ",shortname=unknown"); @@ -971,7 +971,7 @@ static int parse_options(char *options, int is_vfat, int silent, int *debug, opts->codepage = fat_default_codepage; opts->iocharset = fat_default_iocharset; if (is_vfat) { - opts->shortname = VFAT_SFN_DISPLAY_LOWER|VFAT_SFN_CREATE_WIN95; + opts->shortname = VFAT_SFN_DISPLAY_WINNT|VFAT_SFN_CREATE_WIN95; opts->rodir = 0; } else { opts->shortname = 0; -- cgit v0.10.2 From cfc65dd57967f2e0c7b3a8b73e6d12470b1cf1c1 Mon Sep 17 00:00:00 2001 From: Alex Williamson Date: Thu, 30 Jul 2009 16:15:18 -0600 Subject: iommu=pt is a valid early param This avoids a "Malformed early option 'iommu'" warning on boot when trying to use pass-through mode. Signed-off-by: Alex Williamson Signed-off-by: David Woodhouse diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c index 1a041bc..ae13e34 100644 --- a/arch/x86/kernel/pci-dma.c +++ b/arch/x86/kernel/pci-dma.c @@ -212,10 +212,8 @@ static __init int iommu_setup(char *p) if (!strncmp(p, "soft", 4)) swiotlb = 1; #endif - if (!strncmp(p, "pt", 2)) { + if (!strncmp(p, "pt", 2)) iommu_pass_through = 1; - return 1; - } gart_parse_options(p); -- cgit v0.10.2 From 42c4ab41a176ee784c0f28c0b29025a8fc34f05a Mon Sep 17 00:00:00 2001 From: Stanislaw Gruszka Date: Wed, 29 Jul 2009 12:15:26 +0200 Subject: itimers: Merge ITIMER_VIRT and ITIMER_PROF Both cpu itimers have same data flow in the few places, this patch make unification of code related with VIRT and PROF itimers. Signed-off-by: Stanislaw Gruszka Acked-by: Peter Zijlstra Acked-by: Thomas Gleixner Cc: Oleg Nesterov Cc: Andrew Morton Cc: Paul Mackerras Cc: Benjamin Herrenschmidt LKML-Reference: <1248862529-6063-2-git-send-email-sgruszka@redhat.com> Signed-off-by: Ingo Molnar diff --git a/include/linux/sched.h b/include/linux/sched.h index 3ab08e4..3b3efad 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -470,6 +470,11 @@ struct pacct_struct { unsigned long ac_minflt, ac_majflt; }; +struct cpu_itimer { + cputime_t expires; + cputime_t incr; +}; + /** * struct task_cputime - collected CPU time counts * @utime: time spent in user mode, in &cputime_t units @@ -564,9 +569,12 @@ struct signal_struct { struct pid *leader_pid; ktime_t it_real_incr; - /* ITIMER_PROF and ITIMER_VIRTUAL timers for the process */ - cputime_t it_prof_expires, it_virt_expires; - cputime_t it_prof_incr, it_virt_incr; + /* + * ITIMER_PROF and ITIMER_VIRTUAL timers for the process, we use + * CPUCLOCK_PROF and CPUCLOCK_VIRT for indexing array as these + * values are defined to 0 and 1 respectively + */ + struct cpu_itimer it[2]; /* * Thread group totals for process CPU timers. diff --git a/kernel/fork.c b/kernel/fork.c index 29b532e..893ab0b 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -62,6 +62,7 @@ #include #include #include +#include #include #include @@ -790,10 +791,10 @@ static void posix_cpu_timers_init_group(struct signal_struct *sig) thread_group_cputime_init(sig); /* Expiration times and increments. */ - sig->it_virt_expires = cputime_zero; - sig->it_virt_incr = cputime_zero; - sig->it_prof_expires = cputime_zero; - sig->it_prof_incr = cputime_zero; + sig->it[CPUCLOCK_PROF].expires = cputime_zero; + sig->it[CPUCLOCK_PROF].incr = cputime_zero; + sig->it[CPUCLOCK_VIRT].expires = cputime_zero; + sig->it[CPUCLOCK_VIRT].incr = cputime_zero; /* Cached expiration times. */ sig->cputime_expires.prof_exp = cputime_zero; diff --git a/kernel/itimer.c b/kernel/itimer.c index 58762f7..852c88d 100644 --- a/kernel/itimer.c +++ b/kernel/itimer.c @@ -41,10 +41,43 @@ static struct timeval itimer_get_remtime(struct hrtimer *timer) return ktime_to_timeval(rem); } +static void get_cpu_itimer(struct task_struct *tsk, unsigned int clock_id, + struct itimerval *value) +{ + cputime_t cval, cinterval; + struct cpu_itimer *it = &tsk->signal->it[clock_id]; + + spin_lock_irq(&tsk->sighand->siglock); + + cval = it->expires; + cinterval = it->incr; + if (!cputime_eq(cval, cputime_zero)) { + struct task_cputime cputime; + cputime_t t; + + thread_group_cputimer(tsk, &cputime); + if (clock_id == CPUCLOCK_PROF) + t = cputime_add(cputime.utime, cputime.stime); + else + /* CPUCLOCK_VIRT */ + t = cputime.utime; + + if (cputime_le(cval, t)) + /* about to fire */ + cval = jiffies_to_cputime(1); + else + cval = cputime_sub(cval, t); + } + + spin_unlock_irq(&tsk->sighand->siglock); + + cputime_to_timeval(cval, &value->it_value); + cputime_to_timeval(cinterval, &value->it_interval); +} + int do_getitimer(int which, struct itimerval *value) { struct task_struct *tsk = current; - cputime_t cinterval, cval; switch (which) { case ITIMER_REAL: @@ -55,44 +88,10 @@ int do_getitimer(int which, struct itimerval *value) spin_unlock_irq(&tsk->sighand->siglock); break; case ITIMER_VIRTUAL: - spin_lock_irq(&tsk->sighand->siglock); - cval = tsk->signal->it_virt_expires; - cinterval = tsk->signal->it_virt_incr; - if (!cputime_eq(cval, cputime_zero)) { - struct task_cputime cputime; - cputime_t utime; - - thread_group_cputimer(tsk, &cputime); - utime = cputime.utime; - if (cputime_le(cval, utime)) { /* about to fire */ - cval = jiffies_to_cputime(1); - } else { - cval = cputime_sub(cval, utime); - } - } - spin_unlock_irq(&tsk->sighand->siglock); - cputime_to_timeval(cval, &value->it_value); - cputime_to_timeval(cinterval, &value->it_interval); + get_cpu_itimer(tsk, CPUCLOCK_VIRT, value); break; case ITIMER_PROF: - spin_lock_irq(&tsk->sighand->siglock); - cval = tsk->signal->it_prof_expires; - cinterval = tsk->signal->it_prof_incr; - if (!cputime_eq(cval, cputime_zero)) { - struct task_cputime times; - cputime_t ptime; - - thread_group_cputimer(tsk, ×); - ptime = cputime_add(times.utime, times.stime); - if (cputime_le(cval, ptime)) { /* about to fire */ - cval = jiffies_to_cputime(1); - } else { - cval = cputime_sub(cval, ptime); - } - } - spin_unlock_irq(&tsk->sighand->siglock); - cputime_to_timeval(cval, &value->it_value); - cputime_to_timeval(cinterval, &value->it_interval); + get_cpu_itimer(tsk, CPUCLOCK_PROF, value); break; default: return(-EINVAL); @@ -128,6 +127,36 @@ enum hrtimer_restart it_real_fn(struct hrtimer *timer) return HRTIMER_NORESTART; } +static void set_cpu_itimer(struct task_struct *tsk, unsigned int clock_id, + struct itimerval *value, struct itimerval *ovalue) +{ + cputime_t cval, cinterval, nval, ninterval; + struct cpu_itimer *it = &tsk->signal->it[clock_id]; + + nval = timeval_to_cputime(&value->it_value); + ninterval = timeval_to_cputime(&value->it_interval); + + spin_lock_irq(&tsk->sighand->siglock); + + cval = it->expires; + cinterval = it->incr; + if (!cputime_eq(cval, cputime_zero) || + !cputime_eq(nval, cputime_zero)) { + if (cputime_gt(nval, cputime_zero)) + nval = cputime_add(nval, jiffies_to_cputime(1)); + set_process_cpu_timer(tsk, clock_id, &nval, &cval); + } + it->expires = nval; + it->incr = ninterval; + + spin_unlock_irq(&tsk->sighand->siglock); + + if (ovalue) { + cputime_to_timeval(cval, &ovalue->it_value); + cputime_to_timeval(cinterval, &ovalue->it_interval); + } +} + /* * Returns true if the timeval is in canonical form */ @@ -139,7 +168,6 @@ int do_setitimer(int which, struct itimerval *value, struct itimerval *ovalue) struct task_struct *tsk = current; struct hrtimer *timer; ktime_t expires; - cputime_t cval, cinterval, nval, ninterval; /* * Validate the timevals in value. @@ -174,48 +202,10 @@ again: spin_unlock_irq(&tsk->sighand->siglock); break; case ITIMER_VIRTUAL: - nval = timeval_to_cputime(&value->it_value); - ninterval = timeval_to_cputime(&value->it_interval); - spin_lock_irq(&tsk->sighand->siglock); - cval = tsk->signal->it_virt_expires; - cinterval = tsk->signal->it_virt_incr; - if (!cputime_eq(cval, cputime_zero) || - !cputime_eq(nval, cputime_zero)) { - if (cputime_gt(nval, cputime_zero)) - nval = cputime_add(nval, - jiffies_to_cputime(1)); - set_process_cpu_timer(tsk, CPUCLOCK_VIRT, - &nval, &cval); - } - tsk->signal->it_virt_expires = nval; - tsk->signal->it_virt_incr = ninterval; - spin_unlock_irq(&tsk->sighand->siglock); - if (ovalue) { - cputime_to_timeval(cval, &ovalue->it_value); - cputime_to_timeval(cinterval, &ovalue->it_interval); - } + set_cpu_itimer(tsk, CPUCLOCK_VIRT, value, ovalue); break; case ITIMER_PROF: - nval = timeval_to_cputime(&value->it_value); - ninterval = timeval_to_cputime(&value->it_interval); - spin_lock_irq(&tsk->sighand->siglock); - cval = tsk->signal->it_prof_expires; - cinterval = tsk->signal->it_prof_incr; - if (!cputime_eq(cval, cputime_zero) || - !cputime_eq(nval, cputime_zero)) { - if (cputime_gt(nval, cputime_zero)) - nval = cputime_add(nval, - jiffies_to_cputime(1)); - set_process_cpu_timer(tsk, CPUCLOCK_PROF, - &nval, &cval); - } - tsk->signal->it_prof_expires = nval; - tsk->signal->it_prof_incr = ninterval; - spin_unlock_irq(&tsk->sighand->siglock); - if (ovalue) { - cputime_to_timeval(cval, &ovalue->it_value); - cputime_to_timeval(cinterval, &ovalue->it_interval); - } + set_cpu_itimer(tsk, CPUCLOCK_PROF, value, ovalue); break; default: return -EINVAL; diff --git a/kernel/posix-cpu-timers.c b/kernel/posix-cpu-timers.c index bece7c0..9b2d5e4 100644 --- a/kernel/posix-cpu-timers.c +++ b/kernel/posix-cpu-timers.c @@ -14,11 +14,11 @@ */ void update_rlimit_cpu(unsigned long rlim_new) { - cputime_t cputime; + cputime_t cputime = secs_to_cputime(rlim_new); + struct signal_struct *const sig = current->signal; - cputime = secs_to_cputime(rlim_new); - if (cputime_eq(current->signal->it_prof_expires, cputime_zero) || - cputime_gt(current->signal->it_prof_expires, cputime)) { + if (cputime_eq(sig->it[CPUCLOCK_PROF].expires, cputime_zero) || + cputime_gt(sig->it[CPUCLOCK_PROF].expires, cputime)) { spin_lock_irq(¤t->sighand->siglock); set_process_cpu_timer(current, CPUCLOCK_PROF, &cputime, NULL); spin_unlock_irq(¤t->sighand->siglock); @@ -613,6 +613,9 @@ static void arm_timer(struct k_itimer *timer, union cpu_time_count now) break; } } else { + struct signal_struct *const sig = p->signal; + union cpu_time_count *exp = &timer->it.cpu.expires; + /* * For a process timer, set the cached expiration time. */ @@ -620,30 +623,27 @@ static void arm_timer(struct k_itimer *timer, union cpu_time_count now) default: BUG(); case CPUCLOCK_VIRT: - if (!cputime_eq(p->signal->it_virt_expires, + if (!cputime_eq(sig->it[CPUCLOCK_VIRT].expires, cputime_zero) && - cputime_lt(p->signal->it_virt_expires, - timer->it.cpu.expires.cpu)) + cputime_lt(sig->it[CPUCLOCK_VIRT].expires, + exp->cpu)) break; - p->signal->cputime_expires.virt_exp = - timer->it.cpu.expires.cpu; + sig->cputime_expires.virt_exp = exp->cpu; break; case CPUCLOCK_PROF: - if (!cputime_eq(p->signal->it_prof_expires, + if (!cputime_eq(sig->it[CPUCLOCK_PROF].expires, cputime_zero) && - cputime_lt(p->signal->it_prof_expires, - timer->it.cpu.expires.cpu)) + cputime_lt(sig->it[CPUCLOCK_PROF].expires, + exp->cpu)) break; - i = p->signal->rlim[RLIMIT_CPU].rlim_cur; + i = sig->rlim[RLIMIT_CPU].rlim_cur; if (i != RLIM_INFINITY && - i <= cputime_to_secs(timer->it.cpu.expires.cpu)) + i <= cputime_to_secs(exp->cpu)) break; - p->signal->cputime_expires.prof_exp = - timer->it.cpu.expires.cpu; + sig->cputime_expires.prof_exp = exp->cpu; break; case CPUCLOCK_SCHED: - p->signal->cputime_expires.sched_exp = - timer->it.cpu.expires.sched; + sig->cputime_expires.sched_exp = exp->sched; break; } } @@ -1070,6 +1070,27 @@ static void stop_process_timers(struct task_struct *tsk) spin_unlock_irqrestore(&cputimer->lock, flags); } +static void check_cpu_itimer(struct task_struct *tsk, struct cpu_itimer *it, + cputime_t *expires, cputime_t cur_time, int signo) +{ + if (cputime_eq(it->expires, cputime_zero)) + return; + + if (cputime_ge(cur_time, it->expires)) { + it->expires = it->incr; + if (!cputime_eq(it->expires, cputime_zero)) + it->expires = cputime_add(it->expires, cur_time); + + __group_send_sig_info(signo, SEND_SIG_PRIV, tsk); + } + + if (!cputime_eq(it->expires, cputime_zero) && + (cputime_eq(*expires, cputime_zero) || + cputime_lt(it->expires, *expires))) { + *expires = it->expires; + } +} + /* * Check for any per-thread CPU timers that have fired and move them * off the tsk->*_timers list onto the firing list. Per-thread timers @@ -1089,10 +1110,10 @@ static void check_process_timers(struct task_struct *tsk, * Don't sample the current process CPU clocks if there are no timers. */ if (list_empty(&timers[CPUCLOCK_PROF]) && - cputime_eq(sig->it_prof_expires, cputime_zero) && + cputime_eq(sig->it[CPUCLOCK_PROF].expires, cputime_zero) && sig->rlim[RLIMIT_CPU].rlim_cur == RLIM_INFINITY && list_empty(&timers[CPUCLOCK_VIRT]) && - cputime_eq(sig->it_virt_expires, cputime_zero) && + cputime_eq(sig->it[CPUCLOCK_VIRT].expires, cputime_zero) && list_empty(&timers[CPUCLOCK_SCHED])) { stop_process_timers(tsk); return; @@ -1152,38 +1173,11 @@ static void check_process_timers(struct task_struct *tsk, /* * Check for the special case process timers. */ - if (!cputime_eq(sig->it_prof_expires, cputime_zero)) { - if (cputime_ge(ptime, sig->it_prof_expires)) { - /* ITIMER_PROF fires and reloads. */ - sig->it_prof_expires = sig->it_prof_incr; - if (!cputime_eq(sig->it_prof_expires, cputime_zero)) { - sig->it_prof_expires = cputime_add( - sig->it_prof_expires, ptime); - } - __group_send_sig_info(SIGPROF, SEND_SIG_PRIV, tsk); - } - if (!cputime_eq(sig->it_prof_expires, cputime_zero) && - (cputime_eq(prof_expires, cputime_zero) || - cputime_lt(sig->it_prof_expires, prof_expires))) { - prof_expires = sig->it_prof_expires; - } - } - if (!cputime_eq(sig->it_virt_expires, cputime_zero)) { - if (cputime_ge(utime, sig->it_virt_expires)) { - /* ITIMER_VIRTUAL fires and reloads. */ - sig->it_virt_expires = sig->it_virt_incr; - if (!cputime_eq(sig->it_virt_expires, cputime_zero)) { - sig->it_virt_expires = cputime_add( - sig->it_virt_expires, utime); - } - __group_send_sig_info(SIGVTALRM, SEND_SIG_PRIV, tsk); - } - if (!cputime_eq(sig->it_virt_expires, cputime_zero) && - (cputime_eq(virt_expires, cputime_zero) || - cputime_lt(sig->it_virt_expires, virt_expires))) { - virt_expires = sig->it_virt_expires; - } - } + check_cpu_itimer(tsk, &sig->it[CPUCLOCK_PROF], &prof_expires, ptime, + SIGPROF); + check_cpu_itimer(tsk, &sig->it[CPUCLOCK_VIRT], &virt_expires, utime, + SIGVTALRM); + if (sig->rlim[RLIMIT_CPU].rlim_cur != RLIM_INFINITY) { unsigned long psecs = cputime_to_secs(ptime); cputime_t x; -- cgit v0.10.2 From 8356b5f9c424e5831715abbce747197c30d1fd71 Mon Sep 17 00:00:00 2001 From: Stanislaw Gruszka Date: Wed, 29 Jul 2009 12:15:27 +0200 Subject: itimers: Fix periodic tics precision Measure ITIMER_PROF and ITIMER_VIRT timers interval error between real ticks and requested by user. Take it into account when scheduling next tick. This patch introduce possibility where time between two consecutive tics is smaller then requested interval, it preserve however dependency that n tick is generated not earlier than n*interval time - counting from the beginning of periodic signal generation. Signed-off-by: Stanislaw Gruszka Acked-by: Peter Zijlstra Acked-by: Thomas Gleixner Cc: Oleg Nesterov Cc: Andrew Morton Cc: Paul Mackerras Cc: Benjamin Herrenschmidt LKML-Reference: <1248862529-6063-3-git-send-email-sgruszka@redhat.com> Signed-off-by: Ingo Molnar diff --git a/include/linux/sched.h b/include/linux/sched.h index 3b3efad..a069e65 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -473,6 +473,8 @@ struct pacct_struct { struct cpu_itimer { cputime_t expires; cputime_t incr; + u32 error; + u32 incr_error; }; /** diff --git a/kernel/itimer.c b/kernel/itimer.c index 852c88d..21adff7 100644 --- a/kernel/itimer.c +++ b/kernel/itimer.c @@ -42,7 +42,7 @@ static struct timeval itimer_get_remtime(struct hrtimer *timer) } static void get_cpu_itimer(struct task_struct *tsk, unsigned int clock_id, - struct itimerval *value) + struct itimerval *const value) { cputime_t cval, cinterval; struct cpu_itimer *it = &tsk->signal->it[clock_id]; @@ -127,14 +127,32 @@ enum hrtimer_restart it_real_fn(struct hrtimer *timer) return HRTIMER_NORESTART; } +static inline u32 cputime_sub_ns(cputime_t ct, s64 real_ns) +{ + struct timespec ts; + s64 cpu_ns; + + cputime_to_timespec(ct, &ts); + cpu_ns = timespec_to_ns(&ts); + + return (cpu_ns <= real_ns) ? 0 : cpu_ns - real_ns; +} + static void set_cpu_itimer(struct task_struct *tsk, unsigned int clock_id, - struct itimerval *value, struct itimerval *ovalue) + const struct itimerval *const value, + struct itimerval *const ovalue) { - cputime_t cval, cinterval, nval, ninterval; + cputime_t cval, nval, cinterval, ninterval; + s64 ns_ninterval, ns_nval; struct cpu_itimer *it = &tsk->signal->it[clock_id]; nval = timeval_to_cputime(&value->it_value); + ns_nval = timeval_to_ns(&value->it_value); ninterval = timeval_to_cputime(&value->it_interval); + ns_ninterval = timeval_to_ns(&value->it_interval); + + it->incr_error = cputime_sub_ns(ninterval, ns_ninterval); + it->error = cputime_sub_ns(nval, ns_nval); spin_lock_irq(&tsk->sighand->siglock); diff --git a/kernel/posix-cpu-timers.c b/kernel/posix-cpu-timers.c index 9b2d5e4..b60d644 100644 --- a/kernel/posix-cpu-timers.c +++ b/kernel/posix-cpu-timers.c @@ -1070,6 +1070,8 @@ static void stop_process_timers(struct task_struct *tsk) spin_unlock_irqrestore(&cputimer->lock, flags); } +static u32 onecputick; + static void check_cpu_itimer(struct task_struct *tsk, struct cpu_itimer *it, cputime_t *expires, cputime_t cur_time, int signo) { @@ -1077,9 +1079,16 @@ static void check_cpu_itimer(struct task_struct *tsk, struct cpu_itimer *it, return; if (cputime_ge(cur_time, it->expires)) { - it->expires = it->incr; - if (!cputime_eq(it->expires, cputime_zero)) - it->expires = cputime_add(it->expires, cur_time); + if (!cputime_eq(it->incr, cputime_zero)) { + it->expires = cputime_add(it->expires, it->incr); + it->error += it->incr_error; + if (it->error >= onecputick) { + it->expires = cputime_sub(it->expires, + jiffies_to_cputime(1)); + it->error -= onecputick; + } + } else + it->expires = cputime_zero; __group_send_sig_info(signo, SEND_SIG_PRIV, tsk); } @@ -1696,10 +1705,15 @@ static __init int init_posix_cpu_timers(void) .nsleep = thread_cpu_nsleep, .nsleep_restart = thread_cpu_nsleep_restart, }; + struct timespec ts; register_posix_clock(CLOCK_PROCESS_CPUTIME_ID, &process); register_posix_clock(CLOCK_THREAD_CPUTIME_ID, &thread); + cputime_to_timespec(jiffies_to_cputime(1), &ts); + onecputick = ts.tv_nsec; + WARN_ON(ts.tv_sec != 0); + return 0; } __initcall(init_posix_cpu_timers); -- cgit v0.10.2 From d1e3b6d195770bd422e3229b88edfc154b6a27dd Mon Sep 17 00:00:00 2001 From: Stanislaw Gruszka Date: Wed, 29 Jul 2009 12:15:28 +0200 Subject: itimers: Simplify arm_timer() code a bit Don't update values in expiration cache when new ones are equal. Add expire_le() and expire_gt() helpers to simplify the code. Signed-off-by: Stanislaw Gruszka Acked-by: Peter Zijlstra Acked-by: Thomas Gleixner Cc: Oleg Nesterov Cc: Andrew Morton Cc: Paul Mackerras Cc: Benjamin Herrenschmidt LKML-Reference: <1248862529-6063-4-git-send-email-sgruszka@redhat.com> Signed-off-by: Ingo Molnar diff --git a/kernel/posix-cpu-timers.c b/kernel/posix-cpu-timers.c index b60d644..69c9237435 100644 --- a/kernel/posix-cpu-timers.c +++ b/kernel/posix-cpu-timers.c @@ -541,6 +541,17 @@ static void clear_dead_task(struct k_itimer *timer, union cpu_time_count now) now); } +static inline int expires_gt(cputime_t expires, cputime_t new_exp) +{ + return cputime_eq(expires, cputime_zero) || + cputime_gt(expires, new_exp); +} + +static inline int expires_le(cputime_t expires, cputime_t new_exp) +{ + return !cputime_eq(expires, cputime_zero) && + cputime_le(expires, new_exp); +} /* * Insert the timer on the appropriate list before any timers that * expire later. This must be called with the tasklist_lock held @@ -585,31 +596,26 @@ static void arm_timer(struct k_itimer *timer, union cpu_time_count now) */ if (CPUCLOCK_PERTHREAD(timer->it_clock)) { + union cpu_time_count *exp = &nt->expires; + switch (CPUCLOCK_WHICH(timer->it_clock)) { default: BUG(); case CPUCLOCK_PROF: - if (cputime_eq(p->cputime_expires.prof_exp, - cputime_zero) || - cputime_gt(p->cputime_expires.prof_exp, - nt->expires.cpu)) - p->cputime_expires.prof_exp = - nt->expires.cpu; + if (expires_gt(p->cputime_expires.prof_exp, + exp->cpu)) + p->cputime_expires.prof_exp = exp->cpu; break; case CPUCLOCK_VIRT: - if (cputime_eq(p->cputime_expires.virt_exp, - cputime_zero) || - cputime_gt(p->cputime_expires.virt_exp, - nt->expires.cpu)) - p->cputime_expires.virt_exp = - nt->expires.cpu; + if (expires_gt(p->cputime_expires.virt_exp, + exp->cpu)) + p->cputime_expires.virt_exp = exp->cpu; break; case CPUCLOCK_SCHED: if (p->cputime_expires.sched_exp == 0 || - p->cputime_expires.sched_exp > - nt->expires.sched) + p->cputime_expires.sched_exp > exp->sched) p->cputime_expires.sched_exp = - nt->expires.sched; + exp->sched; break; } } else { @@ -623,17 +629,13 @@ static void arm_timer(struct k_itimer *timer, union cpu_time_count now) default: BUG(); case CPUCLOCK_VIRT: - if (!cputime_eq(sig->it[CPUCLOCK_VIRT].expires, - cputime_zero) && - cputime_lt(sig->it[CPUCLOCK_VIRT].expires, + if (expires_le(sig->it[CPUCLOCK_VIRT].expires, exp->cpu)) break; sig->cputime_expires.virt_exp = exp->cpu; break; case CPUCLOCK_PROF: - if (!cputime_eq(sig->it[CPUCLOCK_PROF].expires, - cputime_zero) && - cputime_lt(sig->it[CPUCLOCK_PROF].expires, + if (expires_le(sig->it[CPUCLOCK_PROF].expires, exp->cpu)) break; i = sig->rlim[RLIMIT_CPU].rlim_cur; -- cgit v0.10.2 From a42548a18866e87092db93b771e6c5b060d78401 Mon Sep 17 00:00:00 2001 From: Stanislaw Gruszka Date: Wed, 29 Jul 2009 12:15:29 +0200 Subject: cputime: Optimize jiffies_to_cputime(1) For powerpc with CONFIG_VIRT_CPU_ACCOUNTING jiffies_to_cputime(1) is not compile time constant and run time calculations are quite expensive. To optimize we use precomputed value. For all other architectures is is preprocessor definition. Signed-off-by: Stanislaw Gruszka Acked-by: Peter Zijlstra Acked-by: Thomas Gleixner Cc: Oleg Nesterov Cc: Andrew Morton Cc: Paul Mackerras Cc: Benjamin Herrenschmidt LKML-Reference: <1248862529-6063-5-git-send-email-sgruszka@redhat.com> Signed-off-by: Ingo Molnar diff --git a/arch/ia64/include/asm/cputime.h b/arch/ia64/include/asm/cputime.h index d20b998..7fa8a85 100644 --- a/arch/ia64/include/asm/cputime.h +++ b/arch/ia64/include/asm/cputime.h @@ -30,6 +30,7 @@ typedef u64 cputime_t; typedef u64 cputime64_t; #define cputime_zero ((cputime_t)0) +#define cputime_one_jiffy jiffies_to_cputime(1) #define cputime_max ((~((cputime_t)0) >> 1) - 1) #define cputime_add(__a, __b) ((__a) + (__b)) #define cputime_sub(__a, __b) ((__a) - (__b)) diff --git a/arch/powerpc/include/asm/cputime.h b/arch/powerpc/include/asm/cputime.h index f42e623..fa19f3f 100644 --- a/arch/powerpc/include/asm/cputime.h +++ b/arch/powerpc/include/asm/cputime.h @@ -18,6 +18,9 @@ #ifndef CONFIG_VIRT_CPU_ACCOUNTING #include +#ifdef __KERNEL__ +static inline void setup_cputime_one_jiffy(void) { } +#endif #else #include @@ -49,6 +52,11 @@ typedef u64 cputime64_t; #ifdef __KERNEL__ /* + * One jiffy in timebase units computed during initialization + */ +extern cputime_t cputime_one_jiffy; + +/* * Convert cputime <-> jiffies */ extern u64 __cputime_jiffies_factor; @@ -89,6 +97,11 @@ static inline cputime_t jiffies_to_cputime(const unsigned long jif) return ct; } +static inline void setup_cputime_one_jiffy(void) +{ + cputime_one_jiffy = jiffies_to_cputime(1); +} + static inline cputime64_t jiffies64_to_cputime64(const u64 jif) { cputime_t ct; diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index eae4511..211d7b0 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -193,6 +193,8 @@ EXPORT_SYMBOL(__cputime_clockt_factor); DEFINE_PER_CPU(unsigned long, cputime_last_delta); DEFINE_PER_CPU(unsigned long, cputime_scaled_last_delta); +cputime_t cputime_one_jiffy; + static void calc_cputime_factors(void) { struct div_result res; @@ -500,6 +502,7 @@ static int __init iSeries_tb_recal(void) tb_to_xs = divres.result_low; vdso_data->tb_ticks_per_sec = tb_ticks_per_sec; vdso_data->tb_to_xs = tb_to_xs; + setup_cputime_one_jiffy(); } else { printk( "Titan recalibrate: FAILED (difference > 4 percent)\n" @@ -945,6 +948,7 @@ void __init time_init(void) tb_ticks_per_usec = ppc_tb_freq / 1000000; tb_to_us = mulhwu_scale_factor(ppc_tb_freq, 1000000); calc_cputime_factors(); + setup_cputime_one_jiffy(); /* * Calculate the length of each tick in ns. It will not be diff --git a/arch/s390/include/asm/cputime.h b/arch/s390/include/asm/cputime.h index 7a3817a..24b1244 100644 --- a/arch/s390/include/asm/cputime.h +++ b/arch/s390/include/asm/cputime.h @@ -42,6 +42,7 @@ __div(unsigned long long n, unsigned int base) #endif /* __s390x__ */ #define cputime_zero (0ULL) +#define cputime_one_jiffy jiffies_to_cputime(1) #define cputime_max ((~0UL >> 1) - 1) #define cputime_add(__a, __b) ((__a) + (__b)) #define cputime_sub(__a, __b) ((__a) - (__b)) diff --git a/include/asm-generic/cputime.h b/include/asm-generic/cputime.h index 1c1fa42..ca0f239 100644 --- a/include/asm-generic/cputime.h +++ b/include/asm-generic/cputime.h @@ -7,6 +7,7 @@ typedef unsigned long cputime_t; #define cputime_zero (0UL) +#define cputime_one_jiffy jiffies_to_cputime(1) #define cputime_max ((~0UL >> 1) - 1) #define cputime_add(__a, __b) ((__a) + (__b)) #define cputime_sub(__a, __b) ((__a) - (__b)) diff --git a/kernel/itimer.c b/kernel/itimer.c index 21adff7..8078a32 100644 --- a/kernel/itimer.c +++ b/kernel/itimer.c @@ -64,7 +64,7 @@ static void get_cpu_itimer(struct task_struct *tsk, unsigned int clock_id, if (cputime_le(cval, t)) /* about to fire */ - cval = jiffies_to_cputime(1); + cval = cputime_one_jiffy; else cval = cputime_sub(cval, t); } @@ -161,7 +161,7 @@ static void set_cpu_itimer(struct task_struct *tsk, unsigned int clock_id, if (!cputime_eq(cval, cputime_zero) || !cputime_eq(nval, cputime_zero)) { if (cputime_gt(nval, cputime_zero)) - nval = cputime_add(nval, jiffies_to_cputime(1)); + nval = cputime_add(nval, cputime_one_jiffy); set_process_cpu_timer(tsk, clock_id, &nval, &cval); } it->expires = nval; diff --git a/kernel/posix-cpu-timers.c b/kernel/posix-cpu-timers.c index 69c9237435..18bdde6 100644 --- a/kernel/posix-cpu-timers.c +++ b/kernel/posix-cpu-timers.c @@ -1086,7 +1086,7 @@ static void check_cpu_itimer(struct task_struct *tsk, struct cpu_itimer *it, it->error += it->incr_error; if (it->error >= onecputick) { it->expires = cputime_sub(it->expires, - jiffies_to_cputime(1)); + cputime_one_jiffy); it->error -= onecputick; } } else @@ -1461,7 +1461,7 @@ void set_process_cpu_timer(struct task_struct *tsk, unsigned int clock_idx, if (!cputime_eq(*oldval, cputime_zero)) { if (cputime_le(*oldval, now.cpu)) { /* Just about to fire. */ - *oldval = jiffies_to_cputime(1); + *oldval = cputime_one_jiffy; } else { *oldval = cputime_sub(*oldval, now.cpu); } @@ -1712,7 +1712,7 @@ static __init int init_posix_cpu_timers(void) register_posix_clock(CLOCK_PROCESS_CPUTIME_ID, &process); register_posix_clock(CLOCK_THREAD_CPUTIME_ID, &thread); - cputime_to_timespec(jiffies_to_cputime(1), &ts); + cputime_to_timespec(cputime_one_jiffy, &ts); onecputick = ts.tv_nsec; WARN_ON(ts.tv_sec != 0); diff --git a/kernel/sched.c b/kernel/sched.c index 1b59e26..8f977d5 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -5031,17 +5031,16 @@ void account_idle_time(cputime_t cputime) */ void account_process_tick(struct task_struct *p, int user_tick) { - cputime_t one_jiffy = jiffies_to_cputime(1); - cputime_t one_jiffy_scaled = cputime_to_scaled(one_jiffy); + cputime_t one_jiffy_scaled = cputime_to_scaled(cputime_one_jiffy); struct rq *rq = this_rq(); if (user_tick) - account_user_time(p, one_jiffy, one_jiffy_scaled); + account_user_time(p, cputime_one_jiffy, one_jiffy_scaled); else if ((p != rq->idle) || (irq_count() != HARDIRQ_OFFSET)) - account_system_time(p, HARDIRQ_OFFSET, one_jiffy, + account_system_time(p, HARDIRQ_OFFSET, cputime_one_jiffy, one_jiffy_scaled); else - account_idle_time(one_jiffy); + account_idle_time(cputime_one_jiffy); } /* -- cgit v0.10.2 From 8a4c47f346cc7a12d0897c05eb3cc1add26b487f Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Mon, 20 Jul 2009 13:48:04 +0800 Subject: drm: Remove the unused prefix in DRM_DEBUG_KMS/DRIVER/MODE We will have to add a prefix when using the macro defintion of DRM_DEBUG_KMS /DRM_DEBUG_DRIVER/MODE. It is not convenient. We should use the DRM_NAME as default prefix. So remove the prefix in the macro definition of DRM_DEBUG_KMS/DRIVER/MODE. Signed-off-by: Zhao Yakui Acked-by: Ian Romanick Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index fd489d7..5eca2d5 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -40,7 +40,6 @@ #include "drm.h" #include "drm_crtc.h" -#define DRM_MODESET_DEBUG "drm_mode" /** * drm_mode_debug_printmodeline - debug print a mode * @dev: DRM device @@ -53,8 +52,8 @@ */ void drm_mode_debug_printmodeline(struct drm_display_mode *mode) { - DRM_DEBUG_MODE(DRM_MODESET_DEBUG, - "Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x\n", + DRM_DEBUG_MODE("Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d " + "0x%x 0x%x\n", mode->base.id, mode->name, mode->vrefresh, mode->clock, mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, @@ -819,8 +818,7 @@ void drm_mode_prune_invalid(struct drm_device *dev, list_del(&mode->head); if (verbose) { drm_mode_debug_printmodeline(mode); - DRM_DEBUG_MODE(DRM_MODESET_DEBUG, - "Not using %s mode %d\n", + DRM_DEBUG_MODE("Not using %s mode %d\n", mode->name, mode->status); } drm_mode_destroy(dev, mode); diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 8c47831..14625e1 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -33,8 +33,6 @@ #include "i915_drm.h" #include "i915_drv.h" -#define I915_DRV "i915_drv" - /* Really want an OS-independent resettable timer. Would like to have * this loop run for (eg) 3 sec, but have the timer reset every time * the head pointer changes, so that EBUSY only happens if the ring @@ -101,7 +99,7 @@ static int i915_init_phys_hws(struct drm_device *dev) memset(dev_priv->hw_status_page, 0, PAGE_SIZE); I915_WRITE(HWS_PGA, dev_priv->dma_status_page); - DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n"); + DRM_DEBUG_DRIVER("Enabled hardware status page\n"); return 0; } @@ -187,8 +185,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) master_priv->sarea_priv = (drm_i915_sarea_t *) ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); } else { - DRM_DEBUG_DRIVER(I915_DRV, - "sarea not found assuming DRI2 userspace\n"); + DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); } if (init->ring_size != 0) { @@ -238,7 +235,7 @@ static int i915_dma_resume(struct drm_device * dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__); + DRM_DEBUG_DRIVER("%s\n", __func__); if (dev_priv->ring.map.handle == NULL) { DRM_ERROR("can not ioremap virtual address for" @@ -251,14 +248,14 @@ static int i915_dma_resume(struct drm_device * dev) DRM_ERROR("Can not find hardware status page\n"); return -EINVAL; } - DRM_DEBUG_DRIVER(I915_DRV, "hw status page @ %p\n", + DRM_DEBUG_DRIVER("hw status page @ %p\n", dev_priv->hw_status_page); if (dev_priv->status_gfx_addr != 0) I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); else I915_WRITE(HWS_PGA, dev_priv->dma_status_page); - DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n"); + DRM_DEBUG_DRIVER("Enabled hardware status page\n"); return 0; } @@ -552,7 +549,7 @@ static int i915_dispatch_flip(struct drm_device * dev) if (!master_priv->sarea_priv) return -EINVAL; - DRM_DEBUG_DRIVER(I915_DRV, "%s: page=%d pfCurrentPage=%d\n", + DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", __func__, dev_priv->current_page, master_priv->sarea_priv->pf_current_page); @@ -633,8 +630,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data, return -EINVAL; } - DRM_DEBUG_DRIVER(I915_DRV, - "i915 batchbuffer, start %x used %d cliprects %d\n", + DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", batch->start, batch->used, batch->num_cliprects); RING_LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -681,8 +677,7 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data, void *batch_data; int ret; - DRM_DEBUG_DRIVER(I915_DRV, - "i915 cmdbuffer, buf %p sz %d cliprects %d\n", + DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); RING_LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -735,7 +730,7 @@ static int i915_flip_bufs(struct drm_device *dev, void *data, { int ret; - DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__); + DRM_DEBUG_DRIVER("%s\n", __func__); RING_LOCK_TEST_WITH_RETURN(dev, file_priv); @@ -778,7 +773,7 @@ static int i915_getparam(struct drm_device *dev, void *data, value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; break; default: - DRM_DEBUG_DRIVER(I915_DRV, "Unknown parameter %d\n", + DRM_DEBUG_DRIVER("Unknown parameter %d\n", param->param); return -EINVAL; } @@ -819,7 +814,7 @@ static int i915_setparam(struct drm_device *dev, void *data, dev_priv->fence_reg_start = param->value; break; default: - DRM_DEBUG_DRIVER(I915_DRV, "unknown parameter %d\n", + DRM_DEBUG_DRIVER("unknown parameter %d\n", param->param); return -EINVAL; } @@ -846,7 +841,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data, return 0; } - DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr); + DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); @@ -868,9 +863,9 @@ static int i915_set_status_page(struct drm_device *dev, void *data, memset(dev_priv->hw_status_page, 0, PAGE_SIZE); I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); - DRM_DEBUG_DRIVER(I915_DRV, "load hws HWS_PGA with gfx mem 0x%x\n", + DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", dev_priv->status_gfx_addr); - DRM_DEBUG_DRIVER(I915_DRV, "load hws at %p\n", + DRM_DEBUG_DRIVER("load hws at %p\n", dev_priv->hw_status_page); return 0; } @@ -1310,7 +1305,7 @@ int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) { struct drm_i915_file_private *i915_file_priv; - DRM_DEBUG_DRIVER(I915_DRV, "\n"); + DRM_DEBUG_DRIVER("\n"); i915_file_priv = (struct drm_i915_file_private *) kmalloc(sizeof(*i915_file_priv), GFP_KERNEL); diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 9ab38ef..b59c65d 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -38,8 +38,6 @@ #include "i915_drv.h" #include -#define I915_LVDS "i915_lvds" - /* * the following four scaling options are defined. * #define DRM_MODE_SCALE_NON_GPU 0 @@ -673,8 +671,7 @@ static int intel_lvds_set_property(struct drm_connector *connector, struct drm_crtc *crtc = connector->encoder->crtc; struct intel_lvds_priv *lvds_priv = intel_output->dev_priv; if (value == DRM_MODE_SCALE_NON_GPU) { - DRM_DEBUG_KMS(I915_LVDS, - "non_GPU property is unsupported\n"); + DRM_DEBUG_KMS("non_GPU property is unsupported\n"); return 0; } if (lvds_priv->fitting_mode == value) { @@ -731,8 +728,7 @@ static const struct drm_encoder_funcs intel_lvds_enc_funcs = { static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) { - DRM_DEBUG_KMS(I915_LVDS, - "Skipping LVDS initialization for %s\n", id->ident); + DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); return 1; } @@ -1013,7 +1009,7 @@ out: return; failed: - DRM_DEBUG_KMS(I915_LVDS, "No LVDS modes found, disabling.\n"); + DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); if (intel_output->ddc_bus) intel_i2c_destroy(intel_output->ddc_bus); drm_connector_cleanup(connector); diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 4f0c309..abef69c 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -36,7 +36,6 @@ #include "intel_sdvo_regs.h" #undef SDVO_DEBUG -#define I915_SDVO "i915_sdvo" struct intel_sdvo_priv { u8 slave_addr; @@ -178,7 +177,7 @@ static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr, return true; } - DRM_DEBUG("i2c transfer returned %d\n", ret); + DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); return false; } @@ -288,7 +287,7 @@ static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd, struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; int i; - DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ", + DRM_DEBUG_KMS("%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd); for (i = 0; i < args_len; i++) DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); @@ -341,7 +340,7 @@ static void intel_sdvo_debug_response(struct intel_output *intel_output, struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; int i; - DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv)); + DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv)); for (i = 0; i < response_len; i++) DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); for (; i < 8; i++) @@ -658,10 +657,10 @@ static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output) status = intel_sdvo_read_response(intel_output, &response, 1); if (status != SDVO_CMD_STATUS_SUCCESS) { - DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n"); + DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n"); return SDVO_CLOCK_RATE_MULT_1X; } else { - DRM_DEBUG("Current clock rate multiplier: %d\n", response); + DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response); } return response; @@ -942,14 +941,14 @@ static void intel_sdvo_set_tv_format(struct intel_output *output) format = &sdvo_priv->tv_format; memset(&unset, 0, sizeof(unset)); if (memcmp(format, &unset, sizeof(*format))) { - DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n", + DRM_DEBUG_KMS("%s: Choosing default TV format of NTSC-M\n", SDVO_NAME(sdvo_priv)); format->ntsc_m = 1; intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format, sizeof(*format)); status = intel_sdvo_read_response(output, NULL, 0); if (status != SDVO_CMD_STATUS_SUCCESS) - DRM_DEBUG("%s: Failed to set TV format\n", + DRM_DEBUG_KMS("%s: Failed to set TV format\n", SDVO_NAME(sdvo_priv)); } } @@ -1220,8 +1219,8 @@ static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) * a given it the status is a success, we succeeded. */ if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { - DRM_DEBUG("First %s output reported failure to sync\n", - SDVO_NAME(sdvo_priv)); + DRM_DEBUG_KMS("First %s output reported failure to " + "sync\n", SDVO_NAME(sdvo_priv)); } if (0) @@ -1316,8 +1315,8 @@ static void intel_sdvo_restore(struct drm_connector *connector) intel_wait_for_vblank(dev); status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2); if (status == SDVO_CMD_STATUS_SUCCESS && !input1) - DRM_DEBUG("First %s output reported failure to sync\n", - SDVO_NAME(sdvo_priv)); + DRM_DEBUG_KMS("First %s output reported failure to " + "sync\n", SDVO_NAME(sdvo_priv)); } intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs); @@ -1395,7 +1394,7 @@ int intel_sdvo_supports_hotplug(struct drm_connector *connector) u8 response[2]; u8 status; struct intel_output *intel_output; - DRM_DEBUG("\n"); + DRM_DEBUG_KMS("\n"); if (!connector) return 0; @@ -1460,7 +1459,7 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); status = intel_sdvo_read_response(intel_output, &response, 2); - DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]); + DRM_DEBUG_KMS("SDVO response %d %d\n", response[0], response[1]); if (status != SDVO_CMD_STATUS_SUCCESS) return connector_status_unknown; @@ -1905,8 +1904,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) /* Read the regs to test if we can talk to the device */ for (i = 0; i < 0x40; i++) { if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) { - DRM_DEBUG_KMS(I915_SDVO, - "No SDVO device found on SDVO%c\n", + DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", output_device == SDVOB ? 'B' : 'C'); goto err_i2c; } @@ -1989,8 +1987,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) sdvo_priv->controlled_output = 0; memcpy (bytes, &sdvo_priv->caps.output_flags, 2); - DRM_DEBUG_KMS(I915_SDVO, - "%s: Unknown SDVO output type (0x%02x%02x)\n", + DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", SDVO_NAME(sdvo_priv), bytes[0], bytes[1]); encoder_type = DRM_MODE_ENCODER_NONE; @@ -2022,7 +2019,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) &sdvo_priv->pixel_clock_max); - DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, " + DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n", diff --git a/include/drm/drmP.h b/include/drm/drmP.h index 45b67d9..edbdb02 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -174,19 +174,19 @@ extern void drm_ut_debug_printk(unsigned int request_level, __func__, fmt, ##args); \ } while (0) -#define DRM_DEBUG_DRIVER(prefix, fmt, args...) \ +#define DRM_DEBUG_DRIVER(fmt, args...) \ do { \ - drm_ut_debug_printk(DRM_UT_DRIVER, prefix, \ + drm_ut_debug_printk(DRM_UT_DRIVER, DRM_NAME, \ __func__, fmt, ##args); \ } while (0) -#define DRM_DEBUG_KMS(prefix, fmt, args...) \ +#define DRM_DEBUG_KMS(fmt, args...) \ do { \ - drm_ut_debug_printk(DRM_UT_KMS, prefix, \ + drm_ut_debug_printk(DRM_UT_KMS, DRM_NAME, \ __func__, fmt, ##args); \ } while (0) -#define DRM_DEBUG_MODE(prefix, fmt, args...) \ +#define DRM_DEBUG_MODE(fmt, args...) \ do { \ - drm_ut_debug_printk(DRM_UT_MODE, prefix, \ + drm_ut_debug_printk(DRM_UT_MODE, DRM_NAME, \ __func__, fmt, ##args); \ } while (0) #define DRM_LOG(fmt, args...) \ @@ -210,9 +210,9 @@ extern void drm_ut_debug_printk(unsigned int request_level, NULL, fmt, ##args); \ } while (0) #else -#define DRM_DEBUG_DRIVER(prefix, fmt, args...) do { } while (0) -#define DRM_DEBUG_KMS(prefix, fmt, args...) do { } while (0) -#define DRM_DEBUG_MODE(prefix, fmt, args...) do { } while (0) +#define DRM_DEBUG_DRIVER(fmt, args...) do { } while (0) +#define DRM_DEBUG_KMS(fmt, args...) do { } while (0) +#define DRM_DEBUG_MODE(fmt, args...) do { } while (0) #define DRM_DEBUG(fmt, arg...) do { } while (0) #define DRM_LOG(fmt, arg...) do { } while (0) #define DRM_LOG_KMS(fmt, args...) do { } while (0) -- cgit v0.10.2 From f940f37f022f7392ab81a35516222cbd46110b42 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Mon, 20 Jul 2009 13:48:05 +0800 Subject: drm: Remove the macro defintion of DRM_DEBUG_MODE Two macro definitions of DRM_DEBUG_KMS/MODE can be used to add the debug info related with KMS. It is confusing. So remove the macro definition of DRM_DEBUG_MODE. Instead it can be replaced by the DRM_DEBUG_KMS. Signed-off-by: Zhao Yakui Acked-by: Ian Romanick Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 5eca2d5..6b4d2dc 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -52,7 +52,7 @@ */ void drm_mode_debug_printmodeline(struct drm_display_mode *mode) { - DRM_DEBUG_MODE("Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d " + DRM_DEBUG_KMS("Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d " "0x%x 0x%x\n", mode->base.id, mode->name, mode->vrefresh, mode->clock, mode->hdisplay, mode->hsync_start, @@ -818,7 +818,7 @@ void drm_mode_prune_invalid(struct drm_device *dev, list_del(&mode->head); if (verbose) { drm_mode_debug_printmodeline(mode); - DRM_DEBUG_MODE("Not using %s mode %d\n", + DRM_DEBUG_KMS("Not using %s mode %d\n", mode->name, mode->status); } drm_mode_destroy(dev, mode); diff --git a/include/drm/drmP.h b/include/drm/drmP.h index edbdb02..6513d16 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -88,7 +88,6 @@ struct drm_device; #define DRM_UT_CORE 0x01 #define DRM_UT_DRIVER 0x02 #define DRM_UT_KMS 0x04 -#define DRM_UT_MODE 0x08 extern void drm_ut_debug_printk(unsigned int request_level, const char *prefix, @@ -184,11 +183,6 @@ extern void drm_ut_debug_printk(unsigned int request_level, drm_ut_debug_printk(DRM_UT_KMS, DRM_NAME, \ __func__, fmt, ##args); \ } while (0) -#define DRM_DEBUG_MODE(fmt, args...) \ - do { \ - drm_ut_debug_printk(DRM_UT_MODE, DRM_NAME, \ - __func__, fmt, ##args); \ - } while (0) #define DRM_LOG(fmt, args...) \ do { \ drm_ut_debug_printk(DRM_UT_CORE, NULL, \ @@ -212,7 +206,6 @@ extern void drm_ut_debug_printk(unsigned int request_level, #else #define DRM_DEBUG_DRIVER(fmt, args...) do { } while (0) #define DRM_DEBUG_KMS(fmt, args...) do { } while (0) -#define DRM_DEBUG_MODE(fmt, args...) do { } while (0) #define DRM_DEBUG(fmt, arg...) do { } while (0) #define DRM_LOG(fmt, arg...) do { } while (0) #define DRM_LOG_KMS(fmt, args...) do { } while (0) -- cgit v0.10.2 From 87fdff81cd2d770f0adc742e21eb5e062ad20def Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Mon, 20 Jul 2009 13:48:06 +0800 Subject: DRM: Add the explanation about DRM debug level Add the explanation about DRM debug level in the drmP header file. This is to explain how/where to use the different DRM debug level. Signed-off-by: Zhao Yakui Signed-off-by: Dave Airlie diff --git a/include/drm/drmP.h b/include/drm/drmP.h index 6513d16..e0f1c1f 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -88,6 +88,37 @@ struct drm_device; #define DRM_UT_CORE 0x01 #define DRM_UT_DRIVER 0x02 #define DRM_UT_KMS 0x04 +/* + * Three debug levels are defined. + * drm_core, drm_driver, drm_kms + * drm_core level can be used in the generic drm code. For example: + * drm_ioctl, drm_mm, drm_memory + * The macro definiton of DRM_DEBUG is used. + * DRM_DEBUG(fmt, args...) + * The debug info by using the DRM_DEBUG can be obtained by adding + * the boot option of "drm.debug=1". + * + * drm_driver level can be used in the specific drm driver. It is used + * to add the debug info related with the drm driver. For example: + * i915_drv, i915_dma, i915_gem, radeon_drv, + * The macro definition of DRM_DEBUG_DRIVER can be used. + * DRM_DEBUG_DRIVER(fmt, args...) + * The debug info by using the DRM_DEBUG_DRIVER can be obtained by + * adding the boot option of "drm.debug=0x02" + * + * drm_kms level can be used in the KMS code related with specific drm driver. + * It is used to add the debug info related with KMS mode. For example: + * the connector/crtc , + * The macro definition of DRM_DEBUG_KMS can be used. + * DRM_DEBUG_KMS(fmt, args...) + * The debug info by using the DRM_DEBUG_KMS can be obtained by + * adding the boot option of "drm.debug=0x04" + * + * If we add the boot option of "drm.debug=0x06", we can get the debug info by + * using the DRM_DEBUG_KMS and DRM_DEBUG_DRIVER. + * If we add the boot option of "drm.debug=0x05", we can get the debug info by + * using the DRM_DEBUG_KMS and DRM_DEBUG. + */ extern void drm_ut_debug_printk(unsigned int request_level, const char *prefix, -- cgit v0.10.2 From 58367ed65f30128d8b763bf4c1fb942da49ade15 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Mon, 20 Jul 2009 13:48:07 +0800 Subject: drm: Add the debug info in generic drm mode by using DRM_DEBUG_KMS Add the debug info in generic drm mode by using DRM_DEBUG_KMS Signed-off-by: Zhao Yakui Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 8fab789..9c75830 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -1060,7 +1060,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data, if (file_priv->master->minor->type == DRM_MINOR_CONTROL) { list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - DRM_DEBUG("CRTC ID is %d\n", crtc->base.id); + DRM_DEBUG_KMS("CRTC ID is %d\n", crtc->base.id); if (put_user(crtc->base.id, crtc_id + copied)) { ret = -EFAULT; goto out; @@ -1088,7 +1088,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data, list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - DRM_DEBUG("ENCODER ID is %d\n", + DRM_DEBUG_KMS("ENCODER ID is %d\n", encoder->base.id); if (put_user(encoder->base.id, encoder_id + copied)) { @@ -1119,7 +1119,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data, list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - DRM_DEBUG("CONNECTOR ID is %d\n", + DRM_DEBUG_KMS("CONNECTOR ID is %d\n", connector->base.id); if (put_user(connector->base.id, connector_id + copied)) { @@ -1143,7 +1143,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data, } card_res->count_connectors = connector_count; - DRM_DEBUG("Counted %d %d %d\n", card_res->count_crtcs, + DRM_DEBUG_KMS("Counted %d %d %d\n", card_res->count_crtcs, card_res->count_connectors, card_res->count_encoders); out: @@ -1246,7 +1246,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data, memset(&u_mode, 0, sizeof(struct drm_mode_modeinfo)); - DRM_DEBUG("connector id %d:\n", out_resp->connector_id); + DRM_DEBUG_KMS("connector id %d:\n", out_resp->connector_id); mutex_lock(&dev->mode_config.mutex); @@ -1422,7 +1422,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, obj = drm_mode_object_find(dev, crtc_req->crtc_id, DRM_MODE_OBJECT_CRTC); if (!obj) { - DRM_DEBUG("Unknown CRTC ID %d\n", crtc_req->crtc_id); + DRM_DEBUG_KMS("Unknown CRTC ID %d\n", crtc_req->crtc_id); ret = -EINVAL; goto out; } @@ -1435,7 +1435,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, list_for_each_entry(crtcfb, &dev->mode_config.crtc_list, head) { if (crtcfb == crtc) { - DRM_DEBUG("Using current fb for setmode\n"); + DRM_DEBUG_KMS("Using current fb for " + "setmode\n"); fb = crtc->fb; } } @@ -1443,7 +1444,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, obj = drm_mode_object_find(dev, crtc_req->fb_id, DRM_MODE_OBJECT_FB); if (!obj) { - DRM_DEBUG("Unknown FB ID%d\n", crtc_req->fb_id); + DRM_DEBUG_KMS("Unknown FB ID%d\n", + crtc_req->fb_id); ret = -EINVAL; goto out; } @@ -1456,13 +1458,13 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, } if (crtc_req->count_connectors == 0 && mode) { - DRM_DEBUG("Count connectors is 0 but mode set\n"); + DRM_DEBUG_KMS("Count connectors is 0 but mode set\n"); ret = -EINVAL; goto out; } if (crtc_req->count_connectors > 0 && !mode && !fb) { - DRM_DEBUG("Count connectors is %d but no mode or fb set\n", + DRM_DEBUG_KMS("Count connectors is %d but no mode or fb set\n", crtc_req->count_connectors); ret = -EINVAL; goto out; @@ -1495,7 +1497,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, obj = drm_mode_object_find(dev, out_id, DRM_MODE_OBJECT_CONNECTOR); if (!obj) { - DRM_DEBUG("Connector id %d unknown\n", out_id); + DRM_DEBUG_KMS("Connector id %d unknown\n", + out_id); ret = -EINVAL; goto out; } @@ -1528,7 +1531,7 @@ int drm_mode_cursor_ioctl(struct drm_device *dev, struct drm_crtc *crtc; int ret = 0; - DRM_DEBUG("\n"); + DRM_DEBUG_KMS("\n"); if (!req->flags) { DRM_ERROR("no operation set\n"); @@ -1538,7 +1541,7 @@ int drm_mode_cursor_ioctl(struct drm_device *dev, mutex_lock(&dev->mode_config.mutex); obj = drm_mode_object_find(dev, req->crtc_id, DRM_MODE_OBJECT_CRTC); if (!obj) { - DRM_DEBUG("Unknown CRTC ID %d\n", req->crtc_id); + DRM_DEBUG_KMS("Unknown CRTC ID %d\n", req->crtc_id); ret = -EINVAL; goto out; } diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index 3da9cfa..9cd8451 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -94,7 +94,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, int count = 0; int mode_flags = 0; - DRM_DEBUG("%s\n", drm_get_connector_name(connector)); + DRM_DEBUG_KMS("%s\n", drm_get_connector_name(connector)); /* set all modes to the unverified state */ list_for_each_entry_safe(mode, t, &connector->modes, head) mode->status = MODE_UNVERIFIED; @@ -102,7 +102,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, connector->status = connector->funcs->detect(connector); if (connector->status == connector_status_disconnected) { - DRM_DEBUG("%s is disconnected\n", + DRM_DEBUG_KMS("%s is disconnected\n", drm_get_connector_name(connector)); /* TODO set EDID to NULL */ return 0; @@ -138,7 +138,8 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, drm_mode_sort(&connector->modes); - DRM_DEBUG("Probed modes for %s\n", drm_get_connector_name(connector)); + DRM_DEBUG_KMS("Probed modes for %s\n", + drm_get_connector_name(connector)); list_for_each_entry_safe(mode, t, &connector->modes, head) { mode->vrefresh = drm_mode_vrefresh(mode); @@ -184,12 +185,13 @@ static void drm_helper_add_std_modes(struct drm_device *dev, drm_mode_list_concat(&connector->probed_modes, &connector->modes); - DRM_DEBUG("Adding mode %s to %s\n", stdmode->name, + DRM_DEBUG_KMS("Adding mode %s to %s\n", stdmode->name, drm_get_connector_name(connector)); } drm_mode_sort(&connector->modes); - DRM_DEBUG("Added std modes on %s\n", drm_get_connector_name(connector)); + DRM_DEBUG_KMS("Added std modes on %s\n", + drm_get_connector_name(connector)); list_for_each_entry_safe(mode, t, &connector->modes, head) { mode->vrefresh = drm_mode_vrefresh(mode); @@ -312,7 +314,7 @@ static void drm_enable_connectors(struct drm_device *dev, bool *enabled) list_for_each_entry(connector, &dev->mode_config.connector_list, head) { enabled[i] = drm_connector_enabled(connector, true); - DRM_DEBUG("connector %d enabled? %s\n", connector->base.id, + DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id, enabled[i] ? "yes" : "no"); any_enabled |= enabled[i]; i++; @@ -342,7 +344,7 @@ static bool drm_target_preferred(struct drm_device *dev, continue; } - DRM_DEBUG("looking for preferred mode on connector %d\n", + DRM_DEBUG_KMS("looking for preferred mode on connector %d\n", connector->base.id); modes[i] = drm_has_preferred_mode(connector, width, height); @@ -351,7 +353,7 @@ static bool drm_target_preferred(struct drm_device *dev, list_for_each_entry(modes[i], &connector->modes, head) break; } - DRM_DEBUG("found mode %s\n", modes[i] ? modes[i]->name : + DRM_DEBUG_KMS("found mode %s\n", modes[i] ? modes[i]->name : "none"); i++; } @@ -452,7 +454,7 @@ static void drm_setup_crtcs(struct drm_device *dev) int width, height; int i, ret; - DRM_DEBUG("\n"); + DRM_DEBUG_KMS("\n"); width = dev->mode_config.max_width; height = dev->mode_config.max_height; @@ -475,7 +477,7 @@ static void drm_setup_crtcs(struct drm_device *dev) if (!ret) DRM_ERROR("Unable to find initial modes\n"); - DRM_DEBUG("picking CRTCs for %dx%d config\n", width, height); + DRM_DEBUG_KMS("picking CRTCs for %dx%d config\n", width, height); drm_pick_crtcs(dev, crtcs, modes, 0, width, height); @@ -490,7 +492,7 @@ static void drm_setup_crtcs(struct drm_device *dev) } if (mode && crtc) { - DRM_DEBUG("desired mode %s set on crtc %d\n", + DRM_DEBUG_KMS("desired mode %s set on crtc %d\n", mode->name, crtc->base.id); crtc->desired_mode = mode; connector->encoder->crtc = crtc; @@ -713,7 +715,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) struct drm_crtc_helper_funcs *crtc_funcs; int ret = 0; - DRM_DEBUG("\n"); + DRM_DEBUG_KMS("\n"); if (!set) return -EINVAL; @@ -726,7 +728,8 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) crtc_funcs = set->crtc->helper_private; - DRM_DEBUG("crtc: %p %d fb: %p connectors: %p num_connectors: %d (x, y) (%i, %i)\n", + DRM_DEBUG_KMS("crtc: %p %d fb: %p connectors: %p num_connectors:" + " %d (x, y) (%i, %i)\n", set->crtc, set->crtc->base.id, set->fb, set->connectors, (int)set->num_connectors, set->x, set->y); @@ -756,7 +759,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) if (set->crtc->fb != set->fb) { /* If we have no fb then treat it as a full mode set */ if (set->crtc->fb == NULL) { - DRM_DEBUG("crtc has no fb, full mode set\n"); + DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); mode_changed = true; } else if ((set->fb->bits_per_pixel != set->crtc->fb->bits_per_pixel) || @@ -770,7 +773,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) fb_changed = true; if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { - DRM_DEBUG("modes are different, full mode set\n"); + DRM_DEBUG_KMS("modes are different, full mode set\n"); drm_mode_debug_printmodeline(&set->crtc->mode); drm_mode_debug_printmodeline(set->mode); mode_changed = true; @@ -796,7 +799,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) } if (new_encoder != connector->encoder) { - DRM_DEBUG("encoder changed, full mode switch\n"); + DRM_DEBUG_KMS("encoder changed, full mode switch\n"); mode_changed = true; connector->encoder = new_encoder; } @@ -831,11 +834,11 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) goto fail_set_mode; } if (new_crtc != connector->encoder->crtc) { - DRM_DEBUG("crtc changed, full mode switch\n"); + DRM_DEBUG_KMS("crtc changed, full mode switch\n"); mode_changed = true; connector->encoder->crtc = new_crtc; } - DRM_DEBUG("setting connector %d crtc to %p\n", + DRM_DEBUG_KMS("setting connector %d crtc to %p\n", connector->base.id, new_crtc); } @@ -848,7 +851,8 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) set->crtc->fb = set->fb; set->crtc->enabled = (set->mode != NULL); if (set->mode != NULL) { - DRM_DEBUG("attempting to set mode from userspace\n"); + DRM_DEBUG_KMS("attempting to set mode from" + " userspace\n"); drm_mode_debug_printmodeline(set->mode); if (!drm_crtc_helper_set_mode(set->crtc, set->mode, set->x, set->y, @@ -901,7 +905,7 @@ EXPORT_SYMBOL(drm_crtc_helper_set_config); bool drm_helper_plugged_event(struct drm_device *dev) { - DRM_DEBUG("\n"); + DRM_DEBUG_KMS("\n"); drm_helper_probe_connector_modes(dev, dev->mode_config.max_width, dev->mode_config.max_height); -- cgit v0.10.2 From 2066facca4c7dfe9f5068ece0200a4dbf10f49e1 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Sun, 2 Aug 2009 04:19:17 +0200 Subject: drm/kms: slave encoder interface. Define some helper functions to make easier to detach a KMS encoder implementation from the drm module of the GPU it's used in. This is mainly useful for some external I2C encoders known to be present on cards with GPUs from several different manufacturers. Signed-off-by: Francisco Jerez Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index fe23f29..5f0aec4 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -11,7 +11,7 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \ drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \ drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \ drm_crtc.o drm_crtc_helper.o drm_modes.o drm_edid.o \ - drm_info.o drm_debugfs.o + drm_info.o drm_debugfs.o drm_encoder_slave.o drm-$(CONFIG_COMPAT) += drm_ioc32.o diff --git a/drivers/gpu/drm/drm_encoder_slave.c b/drivers/gpu/drm/drm_encoder_slave.c new file mode 100644 index 0000000..6ffd600 --- /dev/null +++ b/drivers/gpu/drm/drm_encoder_slave.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2009 Francisco Jerez. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include + +/** + * drm_i2c_encoder_init - Initialize an I2C slave encoder + * @dev: DRM device. + * @encoder: Encoder to be attached to the I2C device. You aren't + * required to have called drm_encoder_init() before. + * @adap: I2C adapter that will be used to communicate with + * the device. + * @info: Information that will be used to create the I2C device. + * Required fields are @addr and @type. + * + * Create an I2C device on the specified bus (the module containing its + * driver is transparently loaded) and attach it to the specified + * &drm_encoder_slave. The @slave_funcs field will be initialized with + * the hooks provided by the slave driver. + * + * Returns 0 on success or a negative errno on failure, in particular, + * -ENODEV is returned when no matching driver is found. + */ +int drm_i2c_encoder_init(struct drm_device *dev, + struct drm_encoder_slave *encoder, + struct i2c_adapter *adap, + const struct i2c_board_info *info) +{ + char modalias[sizeof(I2C_MODULE_PREFIX) + + I2C_NAME_SIZE]; + struct module *module = NULL; + struct i2c_client *client; + struct drm_i2c_encoder_driver *encoder_drv; + int err = 0; + + snprintf(modalias, sizeof(modalias), + "%s%s", I2C_MODULE_PREFIX, info->type); + request_module(modalias); + + client = i2c_new_device(adap, info); + if (!client) { + err = -ENOMEM; + goto fail; + } + + if (!client->driver) { + err = -ENODEV; + goto fail_unregister; + } + + module = client->driver->driver.owner; + if (!try_module_get(module)) { + err = -ENODEV; + goto fail_unregister; + } + + encoder->bus_priv = client; + + encoder_drv = to_drm_i2c_encoder_driver(client->driver); + + err = encoder_drv->encoder_init(client, dev, encoder); + if (err) + goto fail_unregister; + + return 0; + +fail_unregister: + i2c_unregister_device(client); + module_put(module); +fail: + return err; +} +EXPORT_SYMBOL(drm_i2c_encoder_init); + +/** + * drm_i2c_encoder_destroy - Unregister the I2C device backing an encoder + * @drm_encoder: Encoder to be unregistered. + * + * This should be called from the @destroy method of an I2C slave + * encoder driver once I2C access is no longer needed. + */ +void drm_i2c_encoder_destroy(struct drm_encoder *drm_encoder) +{ + struct drm_encoder_slave *encoder = to_encoder_slave(drm_encoder); + struct i2c_client *client = drm_i2c_encoder_get_client(drm_encoder); + struct module *module = client->driver->driver.owner; + + i2c_unregister_device(client); + encoder->bus_priv = NULL; + + module_put(module); +} +EXPORT_SYMBOL(drm_i2c_encoder_destroy); diff --git a/include/drm/drm_encoder_slave.h b/include/drm/drm_encoder_slave.h new file mode 100644 index 0000000..821ec40 --- /dev/null +++ b/include/drm/drm_encoder_slave.h @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2009 Francisco Jerez. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DRM_ENCODER_SLAVE_H__ +#define __DRM_ENCODER_SLAVE_H__ + +#include +#include + +/** + * struct drm_encoder_slave_funcs - Entry points exposed by a slave encoder driver + * @set_config: Initialize any encoder-specific modesetting parameters. + * The meaning of the @params parameter is implementation + * dependent. It will usually be a structure with DVO port + * data format settings or timings. It's not required for + * the new parameters to take effect until the next mode + * is set. + * + * Most of its members are analogous to the function pointers in + * &drm_encoder_helper_funcs and they can optionally be used to + * initialize the latter. Connector-like methods (e.g. @get_modes and + * @set_property) will typically be wrapped around and only be called + * if the encoder is the currently selected one for the connector. + */ +struct drm_encoder_slave_funcs { + void (*set_config)(struct drm_encoder *encoder, + void *params); + + void (*destroy)(struct drm_encoder *encoder); + void (*dpms)(struct drm_encoder *encoder, int mode); + void (*save)(struct drm_encoder *encoder); + void (*restore)(struct drm_encoder *encoder); + bool (*mode_fixup)(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); + int (*mode_valid)(struct drm_encoder *encoder, + struct drm_display_mode *mode); + void (*mode_set)(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); + + enum drm_connector_status (*detect)(struct drm_encoder *encoder, + struct drm_connector *connector); + int (*get_modes)(struct drm_encoder *encoder, + struct drm_connector *connector); + int (*create_resources)(struct drm_encoder *encoder, + struct drm_connector *connector); + int (*set_property)(struct drm_encoder *encoder, + struct drm_connector *connector, + struct drm_property *property, + uint64_t val); + +}; + +/** + * struct drm_encoder_slave - Slave encoder struct + * @base: DRM encoder object. + * @slave_funcs: Slave encoder callbacks. + * @slave_priv: Slave encoder private data. + * @bus_priv: Bus specific data. + * + * A &drm_encoder_slave has two sets of callbacks, @slave_funcs and the + * ones in @base. The former are never actually called by the common + * CRTC code, it's just a convenience for splitting the encoder + * functions in an upper, GPU-specific layer and a (hopefully) + * GPU-agnostic lower layer: It's the GPU driver responsibility to + * call the slave methods when appropriate. + * + * drm_i2c_encoder_init() provides a way to get an implementation of + * this. + */ +struct drm_encoder_slave { + struct drm_encoder base; + + struct drm_encoder_slave_funcs *slave_funcs; + void *slave_priv; + void *bus_priv; +}; +#define to_encoder_slave(x) container_of((x), struct drm_encoder_slave, base) + +int drm_i2c_encoder_init(struct drm_device *dev, + struct drm_encoder_slave *encoder, + struct i2c_adapter *adap, + const struct i2c_board_info *info); + + +/** + * struct drm_i2c_encoder_driver + * + * Describes a device driver for an encoder connected to the GPU + * through an I2C bus. In addition to the entry points in @i2c_driver + * an @encoder_init function should be provided. It will be called to + * give the driver an opportunity to allocate any per-encoder data + * structures and to initialize the @slave_funcs and (optionally) + * @slave_priv members of @encoder. + */ +struct drm_i2c_encoder_driver { + struct i2c_driver i2c_driver; + + int (*encoder_init)(struct i2c_client *client, + struct drm_device *dev, + struct drm_encoder_slave *encoder); + +}; +#define to_drm_i2c_encoder_driver(x) container_of((x), \ + struct drm_i2c_encoder_driver, \ + i2c_driver) + +/** + * drm_i2c_encoder_get_client - Get the I2C client corresponding to an encoder + */ +static inline struct i2c_client *drm_i2c_encoder_get_client(struct drm_encoder *encoder) +{ + return (struct i2c_client *)to_encoder_slave(encoder)->bus_priv; +} + +/** + * drm_i2c_encoder_register - Register an I2C encoder driver + * @owner: Module containing the driver. + * @driver: Driver to be registered. + */ +static inline int drm_i2c_encoder_register(struct module *owner, + struct drm_i2c_encoder_driver *driver) +{ + return i2c_register_driver(owner, &driver->i2c_driver); +} + +/** + * drm_i2c_encoder_unregister - Unregister an I2C encoder driver + * @driver: Driver to be unregistered. + */ +static inline void drm_i2c_encoder_unregister(struct drm_i2c_encoder_driver *driver) +{ + return i2c_del_driver(&driver->i2c_driver); +} + +void drm_i2c_encoder_destroy(struct drm_encoder *encoder); + +#endif -- cgit v0.10.2 From 74bd3c26b90f39b9dcc05c471333da8998572b5d Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Sun, 2 Aug 2009 04:19:18 +0200 Subject: drm: Define DRM_MODE_CONNECTOR_TV The existing TV connector types are often unsuitable either because there is no way to probe them until they're actually plugged in or because they can change during run time (e.g. 7-pin DIN connectors that behave as S-Video, Component, Composite or SCART depending on the adaptor plugged in). Signed-off-by: Francisco Jerez Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 9c75830..c7ab80b 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -146,6 +146,7 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] = { DRM_MODE_CONNECTOR_DisplayPort, "DisplayPort", 0 }, { DRM_MODE_CONNECTOR_HDMIA, "HDMI Type A", 0 }, { DRM_MODE_CONNECTOR_HDMIB, "HDMI Type B", 0 }, + { DRM_MODE_CONNECTOR_TV, "TV", 0 }, }; static struct drm_prop_enum_list drm_encoder_enum_list[] = diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index 85ec31b..adc1794 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -247,6 +247,7 @@ static ssize_t subconnector_show(struct device *device, case DRM_MODE_CONNECTOR_Composite: case DRM_MODE_CONNECTOR_SVIDEO: case DRM_MODE_CONNECTOR_Component: + case DRM_MODE_CONNECTOR_TV: prop = dev->mode_config.tv_subconnector_property; is_tv = 1; break; @@ -287,6 +288,7 @@ static ssize_t select_subconnector_show(struct device *device, case DRM_MODE_CONNECTOR_Composite: case DRM_MODE_CONNECTOR_SVIDEO: case DRM_MODE_CONNECTOR_Component: + case DRM_MODE_CONNECTOR_TV: prop = dev->mode_config.tv_select_subconnector_property; is_tv = 1; break; @@ -385,6 +387,7 @@ int drm_sysfs_connector_add(struct drm_connector *connector) case DRM_MODE_CONNECTOR_Composite: case DRM_MODE_CONNECTOR_SVIDEO: case DRM_MODE_CONNECTOR_Component: + case DRM_MODE_CONNECTOR_TV: for (i = 0; i < ARRAY_SIZE(connector_attrs_opt1); i++) { ret = device_create_file(&connector->kdev, &connector_attrs_opt1[i]); if (ret) diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index ae304cc..c51e9f5 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h @@ -155,6 +155,7 @@ struct drm_mode_get_encoder { #define DRM_MODE_CONNECTOR_DisplayPort 10 #define DRM_MODE_CONNECTOR_HDMIA 11 #define DRM_MODE_CONNECTOR_HDMIB 12 +#define DRM_MODE_CONNECTOR_TV 13 struct drm_mode_get_connector { -- cgit v0.10.2 From aeaa1ad3ff32be833680e484d99ec29d892da1ff Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Sun, 2 Aug 2009 04:19:19 +0200 Subject: drm: Define DRM_MODE_SUBCONNECTOR_SCART Signed-off-by: Francisco Jerez Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index c7ab80b..ed53c5c 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -108,6 +108,7 @@ static struct drm_prop_enum_list drm_tv_select_enum_list[] = { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */ { DRM_MODE_SUBCONNECTOR_SVIDEO, "SVIDEO" }, /* TV-out */ { DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */ + { DRM_MODE_SUBCONNECTOR_SCART, "SCART" }, /* TV-out */ }; DRM_ENUM_NAME_FN(drm_get_tv_select_name, drm_tv_select_enum_list) @@ -118,6 +119,7 @@ static struct drm_prop_enum_list drm_tv_subconnector_enum_list[] = { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */ { DRM_MODE_SUBCONNECTOR_SVIDEO, "SVIDEO" }, /* TV-out */ { DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */ + { DRM_MODE_SUBCONNECTOR_SCART, "SCART" }, /* TV-out */ }; DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name, diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index c51e9f5..616aeb4 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h @@ -141,6 +141,7 @@ struct drm_mode_get_encoder { #define DRM_MODE_SUBCONNECTOR_Composite 5 #define DRM_MODE_SUBCONNECTOR_SVIDEO 6 #define DRM_MODE_SUBCONNECTOR_Component 8 +#define DRM_MODE_SUBCONNECTOR_SCART 9 #define DRM_MODE_CONNECTOR_Unknown 0 #define DRM_MODE_CONNECTOR_VGA 1 -- cgit v0.10.2 From b6b7902e54c7e8abbc213d8bdc290350c00ccfe5 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Sun, 2 Aug 2009 04:19:20 +0200 Subject: drm: Define some new standard TV properties. Namely "brightness", "contrast" and "flicker reduction". Signed-off-by: Francisco Jerez Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index ed53c5c..a8c8311 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -718,6 +718,24 @@ int drm_mode_create_tv_properties(struct drm_device *dev, int num_modes, drm_property_add_enum(dev->mode_config.tv_mode_property, i, i, modes[i]); + dev->mode_config.tv_brightness_property = + drm_property_create(dev, DRM_MODE_PROP_RANGE, + "brightness", 2); + dev->mode_config.tv_brightness_property->values[0] = 0; + dev->mode_config.tv_brightness_property->values[1] = 100; + + dev->mode_config.tv_contrast_property = + drm_property_create(dev, DRM_MODE_PROP_RANGE, + "contrast", 2); + dev->mode_config.tv_contrast_property->values[0] = 0; + dev->mode_config.tv_contrast_property->values[1] = 100; + + dev->mode_config.tv_flicker_reduction_property = + drm_property_create(dev, DRM_MODE_PROP_RANGE, + "flicker reduction", 2); + dev->mode_config.tv_flicker_reduction_property->values[0] = 0; + dev->mode_config.tv_flicker_reduction_property->values[1] = 100; + return 0; } EXPORT_SYMBOL(drm_mode_create_tv_properties); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 125994d..5f2cc0c 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -572,6 +572,9 @@ struct drm_mode_config { struct drm_property *tv_right_margin_property; struct drm_property *tv_top_margin_property; struct drm_property *tv_bottom_margin_property; + struct drm_property *tv_brightness_property; + struct drm_property *tv_contrast_property; + struct drm_property *tv_flicker_reduction_property; /* Optional properties */ struct drm_property *scaling_mode_property; -- cgit v0.10.2 From 0815565adfe3f4c369110c57d8ffe83caefeed68 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Tue, 4 Aug 2009 09:17:20 +0100 Subject: intel-iommu: Cope with broken HP DC7900 BIOS Yet another reason why trusting this stuff to the BIOS was a bad idea. The HP DC7900 BIOS reports an iommu at an address which just returns all ones, when VT-d is disabled in the BIOS. Fix up the missing iounmap in the error paths while we're at it. Signed-off-by: David Woodhouse diff --git a/drivers/pci/dmar.c b/drivers/pci/dmar.c index 7b287cb..380b60e 100644 --- a/drivers/pci/dmar.c +++ b/drivers/pci/dmar.c @@ -632,20 +632,31 @@ int alloc_iommu(struct dmar_drhd_unit *drhd) iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); + if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { + /* Promote an attitude of violence to a BIOS engineer today */ + WARN(1, "Your BIOS is broken; DMAR reported at address %llx returns all ones!\n" + "BIOS vendor: %s; Ver: %s; Product Version: %s\n", + drhd->reg_base_addr, + dmi_get_system_info(DMI_BIOS_VENDOR), + dmi_get_system_info(DMI_BIOS_VERSION), + dmi_get_system_info(DMI_PRODUCT_VERSION)); + goto err_unmap; + } + #ifdef CONFIG_DMAR agaw = iommu_calculate_agaw(iommu); if (agaw < 0) { printk(KERN_ERR "Cannot get a valid agaw for iommu (seq_id = %d)\n", iommu->seq_id); - goto error; + goto err_unmap; } msagaw = iommu_calculate_max_sagaw(iommu); if (msagaw < 0) { printk(KERN_ERR "Cannot get a valid max agaw for iommu (seq_id = %d)\n", iommu->seq_id); - goto error; + goto err_unmap; } #endif iommu->agaw = agaw; @@ -665,7 +676,7 @@ int alloc_iommu(struct dmar_drhd_unit *drhd) } ver = readl(iommu->reg + DMAR_VER_REG); - pr_debug("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n", + pr_info("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n", (unsigned long long)drhd->reg_base_addr, DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver), (unsigned long long)iommu->cap, @@ -675,7 +686,10 @@ int alloc_iommu(struct dmar_drhd_unit *drhd) drhd->iommu = iommu; return 0; -error: + + err_unmap: + iounmap(iommu->reg); + error: kfree(iommu); return -1; } -- cgit v0.10.2 From f866a8194f7cbabb9135b98b9ac7d26237b88367 Mon Sep 17 00:00:00 2001 From: NeilBrown Date: Tue, 4 Aug 2009 15:22:38 +1000 Subject: sunrpc/cache: rename queue_loose to cache_dequeue 'loose' was a mis-spelling of 'lose', and even that wasn't a good word choice. So give this function a more useful name. Signed-off-by: NeilBrown Signed-off-by: J. Bruce Fields diff --git a/net/sunrpc/cache.c b/net/sunrpc/cache.c index ff0c230..d19c075 100644 --- a/net/sunrpc/cache.c +++ b/net/sunrpc/cache.c @@ -101,7 +101,7 @@ struct cache_head *sunrpc_cache_lookup(struct cache_detail *detail, EXPORT_SYMBOL_GPL(sunrpc_cache_lookup); -static void queue_loose(struct cache_detail *detail, struct cache_head *ch); +static void cache_dequeue(struct cache_detail *detail, struct cache_head *ch); static int cache_fresh_locked(struct cache_head *head, time_t expiry) { @@ -117,7 +117,7 @@ static void cache_fresh_unlocked(struct cache_head *head, cache_revisit_request(head); if (test_and_clear_bit(CACHE_PENDING, &head->flags)) { cache_revisit_request(head); - queue_loose(detail, head); + cache_dequeue(detail, head); } } @@ -457,7 +457,7 @@ static int cache_clean(void) ) continue; if (test_and_clear_bit(CACHE_PENDING, &ch->flags)) - queue_loose(current_detail, ch); + cache_dequeue(current_detail, ch); if (atomic_read(&ch->ref.refcount) == 1) break; @@ -920,7 +920,7 @@ static const struct file_operations cache_file_operations = { }; -static void queue_loose(struct cache_detail *detail, struct cache_head *ch) +static void cache_dequeue(struct cache_detail *detail, struct cache_head *ch) { struct cache_queue *cq; spin_lock(&queue_lock); -- cgit v0.10.2 From 5c4d26390341732a8d614141a4cf4663610a1698 Mon Sep 17 00:00:00 2001 From: NeilBrown Date: Tue, 4 Aug 2009 15:22:38 +1000 Subject: sunrpc/cache: make sure deferred requests eventually get revisited. While deferred requests normally get revisited quite quickly, it is possible for a request to remain in the deferral queue when the cache item is discarded. We can easily make sure that doesn't happen by calling cache_revisit_request just before the final 'put'. Also there is a small chance that a race would cause one thread to defer a request against a cache item while another thread is failing to queue an upcall for that item. So when the upcall fails, make sure to revisit all deferred requests. Signed-off-by: NeilBrown Signed-off-by: J. Bruce Fields diff --git a/net/sunrpc/cache.c b/net/sunrpc/cache.c index d19c075..44f4516 100644 --- a/net/sunrpc/cache.c +++ b/net/sunrpc/cache.c @@ -221,6 +221,7 @@ int cache_check(struct cache_detail *detail, switch (cache_make_upcall(detail, h)) { case -EINVAL: clear_bit(CACHE_PENDING, &h->flags); + cache_revisit_request(h); if (rv == -EAGAIN) { set_bit(CACHE_NEGATIVE, &h->flags); cache_fresh_unlocked(h, detail, @@ -473,8 +474,10 @@ static int cache_clean(void) if (!ch) current_index ++; spin_unlock(&cache_list_lock); - if (ch) + if (ch) { + cache_revisit_request(ch); cache_put(ch, d); + } } else spin_unlock(&cache_list_lock); -- cgit v0.10.2 From 19943b0e30b05d42e494ae6fef78156ebc8c637e Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Tue, 4 Aug 2009 16:19:20 +0100 Subject: intel-iommu: Unify hardware and software passthrough support This makes the hardware passthrough mode work a lot more like the software version, so that the behaviour of a kernel with 'iommu=pt' is the same whether the hardware supports passthrough or not. In particular: - We use a single si_domain for the pass-through devices. - 32-bit devices can be taken out of the pass-through domain so that they don't have to use swiotlb. - Devices will work again after being removed from a KVM guest. - A potential oops on OOM (in init_context_pass_through()) is fixed. Signed-off-by: David Woodhouse diff --git a/arch/x86/kernel/pci-swiotlb.c b/arch/x86/kernel/pci-swiotlb.c index 6af96ee..1e66b18 100644 --- a/arch/x86/kernel/pci-swiotlb.c +++ b/arch/x86/kernel/pci-swiotlb.c @@ -71,9 +71,8 @@ void __init pci_swiotlb_init(void) { /* don't initialize swiotlb if iommu=off (no_iommu=1) */ #ifdef CONFIG_X86_64 - if ((!iommu_detected && !no_iommu && max_pfn > MAX_DMA32_PFN) || - iommu_pass_through) - swiotlb = 1; + if ((!iommu_detected && !no_iommu && max_pfn > MAX_DMA32_PFN)) + swiotlb = 1; #endif if (swiotlb_force) swiotlb = 1; diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index 097d5da..147b3b9 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -251,7 +251,8 @@ static inline int first_pte_in_page(struct dma_pte *pte) * 2. It maps to each iommu if successful. * 3. Each iommu mapps to this domain if successful. */ -struct dmar_domain *si_domain; +static struct dmar_domain *si_domain; +static int hw_pass_through = 1; /* devices under the same p2p bridge are owned in one domain */ #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0) @@ -1948,14 +1949,24 @@ static int iommu_prepare_identity_map(struct pci_dev *pdev, struct dmar_domain *domain; int ret; - printk(KERN_INFO - "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n", - pci_name(pdev), start, end); - domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH); if (!domain) return -ENOMEM; + /* For _hardware_ passthrough, don't bother. But for software + passthrough, we do it anyway -- it may indicate a memory + range which is reserved in E820, so which didn't get set + up to start with in si_domain */ + if (domain == si_domain && hw_pass_through) { + printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n", + pci_name(pdev), start, end); + return 0; + } + + printk(KERN_INFO + "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n", + pci_name(pdev), start, end); + ret = iommu_domain_identity_map(domain, start, end); if (ret) goto error; @@ -2006,23 +2017,6 @@ static inline void iommu_prepare_isa(void) } #endif /* !CONFIG_DMAR_FLPY_WA */ -/* Initialize each context entry as pass through.*/ -static int __init init_context_pass_through(void) -{ - struct pci_dev *pdev = NULL; - struct dmar_domain *domain; - int ret; - - for_each_pci_dev(pdev) { - domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH); - ret = domain_context_mapping(domain, pdev, - CONTEXT_TT_PASS_THROUGH); - if (ret) - return ret; - } - return 0; -} - static int md_domain_init(struct dmar_domain *domain, int guest_width); static int __init si_domain_work_fn(unsigned long start_pfn, @@ -2037,7 +2031,7 @@ static int __init si_domain_work_fn(unsigned long start_pfn, } -static int si_domain_init(void) +static int si_domain_init(int hw) { struct dmar_drhd_unit *drhd; struct intel_iommu *iommu; @@ -2064,6 +2058,9 @@ static int si_domain_init(void) si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY; + if (hw) + return 0; + for_each_online_node(nid) { work_with_active_regions(nid, si_domain_work_fn, &ret); if (ret) @@ -2155,24 +2152,26 @@ static int iommu_should_identity_map(struct pci_dev *pdev, int startup) return 1; } -static int iommu_prepare_static_identity_mapping(void) +static int iommu_prepare_static_identity_mapping(int hw) { struct pci_dev *pdev = NULL; int ret; - ret = si_domain_init(); + ret = si_domain_init(hw); if (ret) return -EFAULT; for_each_pci_dev(pdev) { if (iommu_should_identity_map(pdev, 1)) { - printk(KERN_INFO "IOMMU: identity mapping for device %s\n", - pci_name(pdev)); + printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n", + hw ? "hardware" : "software", pci_name(pdev)); ret = domain_context_mapping(si_domain, pdev, + hw ? CONTEXT_TT_PASS_THROUGH : CONTEXT_TT_MULTI_LEVEL); if (ret) return ret; + ret = domain_add_dev_info(si_domain, pdev); if (ret) return ret; @@ -2189,14 +2188,6 @@ int __init init_dmars(void) struct pci_dev *pdev; struct intel_iommu *iommu; int i, ret; - int pass_through = 1; - - /* - * In case pass through can not be enabled, iommu tries to use identity - * mapping. - */ - if (iommu_pass_through) - iommu_identity_mapping = 1; /* * for each drhd @@ -2250,14 +2241,8 @@ int __init init_dmars(void) goto error; } if (!ecap_pass_through(iommu->ecap)) - pass_through = 0; + hw_pass_through = 0; } - if (iommu_pass_through) - if (!pass_through) { - printk(KERN_INFO - "Pass Through is not supported by hardware.\n"); - iommu_pass_through = 0; - } /* * Start from the sane iommu hardware state. @@ -2312,64 +2297,57 @@ int __init init_dmars(void) } } + if (iommu_pass_through) + iommu_identity_mapping = 1; +#ifdef CONFIG_DMAR_BROKEN_GFX_WA + else + iommu_identity_mapping = 2; +#endif /* - * If pass through is set and enabled, context entries of all pci - * devices are intialized by pass through translation type. + * If pass through is not set or not enabled, setup context entries for + * identity mappings for rmrr, gfx, and isa and may fall back to static + * identity mapping if iommu_identity_mapping is set. */ - if (iommu_pass_through) { - ret = init_context_pass_through(); + if (iommu_identity_mapping) { + ret = iommu_prepare_static_identity_mapping(hw_pass_through); if (ret) { - printk(KERN_ERR "IOMMU: Pass through init failed.\n"); - iommu_pass_through = 0; + printk(KERN_CRIT "Failed to setup IOMMU pass-through\n"); + goto error; } } - /* - * If pass through is not set or not enabled, setup context entries for - * identity mappings for rmrr, gfx, and isa and may fall back to static - * identity mapping if iommu_identity_mapping is set. + * For each rmrr + * for each dev attached to rmrr + * do + * locate drhd for dev, alloc domain for dev + * allocate free domain + * allocate page table entries for rmrr + * if context not allocated for bus + * allocate and init context + * set present in root table for this bus + * init context with domain, translation etc + * endfor + * endfor */ - if (!iommu_pass_through) { -#ifdef CONFIG_DMAR_BROKEN_GFX_WA - if (!iommu_identity_mapping) - iommu_identity_mapping = 2; -#endif - if (iommu_identity_mapping) - iommu_prepare_static_identity_mapping(); - /* - * For each rmrr - * for each dev attached to rmrr - * do - * locate drhd for dev, alloc domain for dev - * allocate free domain - * allocate page table entries for rmrr - * if context not allocated for bus - * allocate and init context - * set present in root table for this bus - * init context with domain, translation etc - * endfor - * endfor - */ - printk(KERN_INFO "IOMMU: Setting RMRR:\n"); - for_each_rmrr_units(rmrr) { - for (i = 0; i < rmrr->devices_cnt; i++) { - pdev = rmrr->devices[i]; - /* - * some BIOS lists non-exist devices in DMAR - * table. - */ - if (!pdev) - continue; - ret = iommu_prepare_rmrr_dev(rmrr, pdev); - if (ret) - printk(KERN_ERR - "IOMMU: mapping reserved region failed\n"); - } + printk(KERN_INFO "IOMMU: Setting RMRR:\n"); + for_each_rmrr_units(rmrr) { + for (i = 0; i < rmrr->devices_cnt; i++) { + pdev = rmrr->devices[i]; + /* + * some BIOS lists non-exist devices in DMAR + * table. + */ + if (!pdev) + continue; + ret = iommu_prepare_rmrr_dev(rmrr, pdev); + if (ret) + printk(KERN_ERR + "IOMMU: mapping reserved region failed\n"); } - - iommu_prepare_isa(); } + iommu_prepare_isa(); + /* * for each drhd * enable fault log @@ -2536,7 +2514,10 @@ static int iommu_no_mapping(struct device *dev) ret = domain_add_dev_info(si_domain, pdev); if (ret) return 0; - ret = domain_context_mapping(si_domain, pdev, CONTEXT_TT_MULTI_LEVEL); + ret = domain_context_mapping(si_domain, pdev, + hw_pass_through ? + CONTEXT_TT_PASS_THROUGH : + CONTEXT_TT_MULTI_LEVEL); if (!ret) { printk(KERN_INFO "64bit %s uses identity mapping\n", pci_name(pdev)); @@ -3202,7 +3183,7 @@ int __init intel_iommu_init(void) * Check the need for DMA-remapping initialization now. * Above initialization will also be used by Interrupt-remapping. */ - if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled) + if (no_iommu || swiotlb || dmar_disabled) return -ENODEV; iommu_init_mempool(); @@ -3222,14 +3203,7 @@ int __init intel_iommu_init(void) init_timer(&unmap_timer); force_iommu = 1; - - if (!iommu_pass_through) { - printk(KERN_INFO - "Multi-level page-table translation for DMAR.\n"); - dma_ops = &intel_dma_ops; - } else - printk(KERN_INFO - "DMAR: Pass through translation for DMAR.\n"); + dma_ops = &intel_dma_ops; init_iommu_sysfs(); -- cgit v0.10.2 From 989a19b9b10635eeb91c08cefe6cf82986bd4ee2 Mon Sep 17 00:00:00 2001 From: NeilBrown Date: Tue, 4 Aug 2009 15:22:38 +1000 Subject: sunrpc/cache: recheck cache validity after cache_defer_req If cache_defer_req did not leave the request on a queue, then it could possibly have waited long enough that the cache became valid. So check the status after the call. Signed-off-by: NeilBrown Signed-off-by: J. Bruce Fields diff --git a/net/sunrpc/cache.c b/net/sunrpc/cache.c index 44f4516..bbd31f1 100644 --- a/net/sunrpc/cache.c +++ b/net/sunrpc/cache.c @@ -176,6 +176,22 @@ struct cache_head *sunrpc_cache_update(struct cache_detail *detail, EXPORT_SYMBOL_GPL(sunrpc_cache_update); static int cache_make_upcall(struct cache_detail *detail, struct cache_head *h); + +static inline int cache_is_valid(struct cache_detail *detail, struct cache_head *h) +{ + if (!test_bit(CACHE_VALID, &h->flags) || + h->expiry_time < get_seconds()) + return -EAGAIN; + else if (detail->flush_time > h->last_refresh) + return -EAGAIN; + else { + /* entry is valid */ + if (test_bit(CACHE_NEGATIVE, &h->flags)) + return -ENOENT; + else + return 0; + } +} /* * This is the generic cache management routine for all * the authentication caches. @@ -184,8 +200,10 @@ static int cache_make_upcall(struct cache_detail *detail, struct cache_head *h); * * * Returns 0 if the cache_head can be used, or cache_puts it and returns - * -EAGAIN if upcall is pending, - * -ETIMEDOUT if upcall failed and should be retried, + * -EAGAIN if upcall is pending and request has been queued + * -ETIMEDOUT if upcall failed or request could not be queue or + * upcall completed but item is still invalid (implying that + * the cache item has been replaced with a newer one). * -ENOENT if cache entry was negative */ int cache_check(struct cache_detail *detail, @@ -195,17 +213,7 @@ int cache_check(struct cache_detail *detail, long refresh_age, age; /* First decide return status as best we can */ - if (!test_bit(CACHE_VALID, &h->flags) || - h->expiry_time < get_seconds()) - rv = -EAGAIN; - else if (detail->flush_time > h->last_refresh) - rv = -EAGAIN; - else { - /* entry is valid */ - if (test_bit(CACHE_NEGATIVE, &h->flags)) - rv = -ENOENT; - else rv = 0; - } + rv = cache_is_valid(detail, h); /* now see if we want to start an upcall */ refresh_age = (h->expiry_time - h->last_refresh); @@ -238,10 +246,14 @@ int cache_check(struct cache_detail *detail, } } - if (rv == -EAGAIN) - if (cache_defer_req(rqstp, h) != 0) - rv = -ETIMEDOUT; - + if (rv == -EAGAIN) { + if (cache_defer_req(rqstp, h) == 0) { + /* Request is not deferred */ + rv = cache_is_valid(detail, h); + if (rv == -EAGAIN) + rv = -ETIMEDOUT; + } + } if (rv) cache_put(h, detail); return rv; @@ -560,11 +572,11 @@ static int cache_defer_req(struct cache_req *req, struct cache_head *item) * or continue and drop the oldest below */ if (net_random()&1) - return -ETIMEDOUT; + return 0; } dreq = req->defer(req); if (dreq == NULL) - return -ETIMEDOUT; + return 0; dreq->item = item; @@ -594,8 +606,9 @@ static int cache_defer_req(struct cache_req *req, struct cache_head *item) if (!test_bit(CACHE_PENDING, &item->flags)) { /* must have just been validated... */ cache_revisit_request(item); + return 0; } - return 0; + return 1; } static void cache_revisit_request(struct cache_head *item) -- cgit v0.10.2 From 560ab42ef923aaf2e4347315bdfcc74b2708972c Mon Sep 17 00:00:00 2001 From: NeilBrown Date: Tue, 4 Aug 2009 15:22:39 +1000 Subject: sunrpc: fix memory leak in unix_gid cache. When we look up an entry in the uid->gidlist cache, we take a reference to the content but don't drop the reference to the cache entry. So it never gets freed. Signed-off-by: NeilBrown Signed-off-by: J. Bruce Fields diff --git a/net/sunrpc/svcauth_unix.c b/net/sunrpc/svcauth_unix.c index 5c865e2..799ff6e 100644 --- a/net/sunrpc/svcauth_unix.c +++ b/net/sunrpc/svcauth_unix.c @@ -658,6 +658,7 @@ static int unix_gid_find(uid_t uid, struct group_info **gip, case 0: *gip = ug->gi; get_group_info(*gip); + cache_put(&ug->h, &unix_gid_cache); return 0; default: return -EAGAIN; -- cgit v0.10.2 From 5fe60f4e5871b64e687229199fafd4ef13cd0886 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Sun, 9 Aug 2009 10:53:41 +0100 Subject: intel-iommu: make domain_add_dev_info() call domain_context_mapping() All callers of the former were also calling the latter, in one order or the other, and failing to correctly clean up if the second returned failure. Signed-off-by: David Woodhouse diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index 3f256b8..09606e9 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -2094,15 +2094,23 @@ static int identity_mapping(struct pci_dev *pdev) } static int domain_add_dev_info(struct dmar_domain *domain, - struct pci_dev *pdev) + struct pci_dev *pdev, + int translation) { struct device_domain_info *info; unsigned long flags; + int ret; info = alloc_devinfo_mem(); if (!info) return -ENOMEM; + ret = domain_context_mapping(domain, pdev, translation); + if (ret) { + free_devinfo_mem(info); + return ret; + } + info->segment = pci_domain_nr(pdev->bus); info->bus = pdev->bus->number; info->devfn = pdev->devfn; @@ -2173,15 +2181,11 @@ static int iommu_prepare_static_identity_mapping(int hw) printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n", hw ? "hardware" : "software", pci_name(pdev)); - ret = domain_context_mapping(si_domain, pdev, + ret = domain_add_dev_info(si_domain, pdev, hw ? CONTEXT_TT_PASS_THROUGH : CONTEXT_TT_MULTI_LEVEL); if (ret) return ret; - - ret = domain_add_dev_info(si_domain, pdev); - if (ret) - return ret; } } @@ -2510,13 +2514,10 @@ static int iommu_no_mapping(struct device *dev) */ if (iommu_should_identity_map(pdev, 0)) { int ret; - ret = domain_add_dev_info(si_domain, pdev); - if (ret) - return 0; - ret = domain_context_mapping(si_domain, pdev, - hw_pass_through ? - CONTEXT_TT_PASS_THROUGH : - CONTEXT_TT_MULTI_LEVEL); + ret = domain_add_dev_info(si_domain, pdev, + hw_pass_through ? + CONTEXT_TT_PASS_THROUGH : + CONTEXT_TT_MULTI_LEVEL); if (!ret) { printk(KERN_INFO "64bit %s uses identity mapping\n", pci_name(pdev)); @@ -3486,7 +3487,6 @@ static int intel_iommu_attach_device(struct iommu_domain *domain, struct intel_iommu *iommu; int addr_width; u64 end; - int ret; /* normally pdev is not mapped */ if (unlikely(domain_context_mapped(pdev))) { @@ -3518,12 +3518,7 @@ static int intel_iommu_attach_device(struct iommu_domain *domain, return -EFAULT; } - ret = domain_add_dev_info(dmar_domain, pdev); - if (ret) - return ret; - - ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL); - return ret; + return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL); } static void intel_iommu_detach_device(struct iommu_domain *domain, -- cgit v0.10.2 From 841b4117b30d544690fceb952037b1cddf14783f Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Wed, 12 Aug 2009 02:30:09 +0200 Subject: drm: Fix drm_cvt_mode() for interlaced modes. The calculated vdisplay was half the right value. Signed-off-by: Francisco Jerez Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 6b4d2dc..9e54925 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -146,7 +146,7 @@ struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, if (margins) vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; - drm_mode->vdisplay = vdisplay_rnd + 2 * vmargin; + drm_mode->vdisplay = vdisplay + 2 * vmargin; /* Interlaced */ if (interlaced) -- cgit v0.10.2 From a75f0236292a5fca65f26efedca48bd07db1834d Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Wed, 12 Aug 2009 02:30:10 +0200 Subject: drm: Add more standard TV properties. Overscan, saturation, hue. Used in the nouveau driver for GPUs with integrated TV encoders. Signed-off-by: Francisco Jerez Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index a8c8311..362a538 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -736,6 +736,24 @@ int drm_mode_create_tv_properties(struct drm_device *dev, int num_modes, dev->mode_config.tv_flicker_reduction_property->values[0] = 0; dev->mode_config.tv_flicker_reduction_property->values[1] = 100; + dev->mode_config.tv_overscan_property = + drm_property_create(dev, DRM_MODE_PROP_RANGE, + "overscan", 2); + dev->mode_config.tv_overscan_property->values[0] = 0; + dev->mode_config.tv_overscan_property->values[1] = 100; + + dev->mode_config.tv_saturation_property = + drm_property_create(dev, DRM_MODE_PROP_RANGE, + "saturation", 2); + dev->mode_config.tv_saturation_property->values[0] = 0; + dev->mode_config.tv_saturation_property->values[1] = 100; + + dev->mode_config.tv_hue_property = + drm_property_create(dev, DRM_MODE_PROP_RANGE, + "hue", 2); + dev->mode_config.tv_hue_property->values[0] = 0; + dev->mode_config.tv_hue_property->values[1] = 100; + return 0; } EXPORT_SYMBOL(drm_mode_create_tv_properties); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 5f2cc0c..db92a83 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -575,6 +575,9 @@ struct drm_mode_config { struct drm_property *tv_brightness_property; struct drm_property *tv_contrast_property; struct drm_property *tv_flicker_reduction_property; + struct drm_property *tv_overscan_property; + struct drm_property *tv_saturation_property; + struct drm_property *tv_hue_property; /* Optional properties */ struct drm_property *scaling_mode_property; -- cgit v0.10.2 From cfcf4738cd6b5d7bed1473acad76d6430cf1fb0a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 13 Aug 2009 13:31:54 +1000 Subject: drm: fixup include file in drm_encoder_slave Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_encoder_slave.c b/drivers/gpu/drm/drm_encoder_slave.c index 6ffd600..f018469 100644 --- a/drivers/gpu/drm/drm_encoder_slave.c +++ b/drivers/gpu/drm/drm_encoder_slave.c @@ -24,7 +24,7 @@ * */ -#include +#include "drm_encoder_slave.h" /** * drm_i2c_encoder_init - Initialize an I2C slave encoder -- cgit v0.10.2 From ba6c548701ef7a93b9ea05d1506d2b62f1628333 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Thu, 13 Aug 2009 18:18:00 +0100 Subject: ia64: IOMMU passthrough mode shouldn't trigger swiotlb init Since commit 19943b0e30b05d42e494ae6fef78156ebc8c637e ('intel-iommu: Unify hardware and software passthrough support'), hardware passthrough mode will do the same as software passthrough mode was doing -- it'll still use the IOMMU normally for devices which can't address all of memory. This means that we don't need to bother with swiotlb. Signed-off-by: David Woodhouse diff --git a/arch/ia64/kernel/pci-swiotlb.c b/arch/ia64/kernel/pci-swiotlb.c index 223abb1..285aae8 100644 --- a/arch/ia64/kernel/pci-swiotlb.c +++ b/arch/ia64/kernel/pci-swiotlb.c @@ -46,7 +46,7 @@ void __init swiotlb_dma_init(void) void __init pci_swiotlb_init(void) { - if (!iommu_detected || iommu_pass_through) { + if (!iommu_detected) { #ifdef CONFIG_IA64_GENERIC swiotlb = 1; printk(KERN_INFO "PCI-DMA: Re-initialize machine vector.\n"); -- cgit v0.10.2 From 29a88c99d29834fb3314e0144900b187ede83106 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Sun, 19 Jul 2009 14:03:16 +0300 Subject: UBI: print a message if ECH is corrupted and VIDH is ok If the EC header is corrupted, but the VID header is OK, UBI accepts the PEB and treats it as "used". However, generally this should not happen. Print a warning if this happens. Signed-off-by: Artem Bityutskiy diff --git a/drivers/mtd/ubi/scan.c b/drivers/mtd/ubi/scan.c index b847745..93361ea 100644 --- a/drivers/mtd/ubi/scan.c +++ b/drivers/mtd/ubi/scan.c @@ -864,7 +864,9 @@ static int process_eb(struct ubi_device *ubi, struct ubi_scan_info *si, } } - /* Both UBI headers seem to be fine */ + if (ec_corr) + ubi_warn("valid VID header but corrupted EC header at PEB %d", + pnum); err = ubi_scan_add_used(ubi, si, pnum, ec, vidh, bitflips); if (err) return err; -- cgit v0.10.2 From 5b289b562f6d236108569a880cb38cc03d17a50d Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Sun, 19 Jul 2009 14:09:46 +0300 Subject: UBI: amend NOR flash pre-erase quirk In case of NOR flash, UBI zeroes EC and VID headers' magic, in order to detect interrupted erasures. It first zeroes out the EC magic, then VID magic. However, if a power cut happens in between, we'll end up with a corrupted EC header and a valid VID header, in which case UBI accepts the PEB, but prints a warning. This patch makes sure we first zero out the VID magic, then the EC magic, not vice versa. This is just a small amendment to prevent warning messages. Signed-off-by: Artem Bityutskiy diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index 4cb6992..4e7bcb2 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -480,20 +480,20 @@ static int nor_erase_prepare(struct ubi_device *ubi, int pnum) loff_t addr; uint32_t data = 0; - addr = (loff_t)pnum * ubi->peb_size; + addr = (loff_t)pnum * ubi->peb_size + ubi->vid_hdr_aloffset; err = ubi->mtd->write(ubi->mtd, addr, 4, &written, (void *)&data); if (err) { ubi_err("error %d while writing 4 bytes to PEB %d:%d, written " - "%zd bytes", err, pnum, 0, written); + "%zd bytes", err, pnum, ubi->vid_hdr_aloffset, written); ubi_dbg_dump_stack(); return err; } - addr += ubi->vid_hdr_aloffset; + addr -= ubi->vid_hdr_aloffset; err = ubi->mtd->write(ubi->mtd, addr, 4, &written, (void *)&data); if (err) { ubi_err("error %d while writing 4 bytes to PEB %d:%d, written " - "%zd bytes", err, pnum, ubi->vid_hdr_aloffset, written); + "%zd bytes", err, pnum, 0, written); ubi_dbg_dump_stack(); return err; } -- cgit v0.10.2 From 4a406856ea6830d8b8dba6a27d9f9331c5f4c13a Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Sun, 19 Jul 2009 14:33:14 +0300 Subject: UBI: print a warning if too many PEBs are corrupted There was a bug report recently where UBI prints: UBI error: ubi_attach_mtd_dev: failed to attach by scanning, error -22 error messages and refuses to attach a PEB. It turned out to be a buggy flash driver which returned garbage to almost every UBI read. This patch makes UBI print a better message in such cases. Namely, if UBI finds 8 or more corrupted PEBs, it prints a warning and lists the corrupted PEBs. Signed-off-by: Artem Bityutskiy diff --git a/drivers/mtd/ubi/scan.c b/drivers/mtd/ubi/scan.c index 93361ea..e7161ad 100644 --- a/drivers/mtd/ubi/scan.c +++ b/drivers/mtd/ubi/scan.c @@ -75,9 +75,10 @@ static int add_to_list(struct ubi_scan_info *si, int pnum, int ec, dbg_bld("add to free: PEB %d, EC %d", pnum, ec); else if (list == &si->erase) dbg_bld("add to erase: PEB %d, EC %d", pnum, ec); - else if (list == &si->corr) + else if (list == &si->corr) { dbg_bld("add to corrupted: PEB %d, EC %d", pnum, ec); - else if (list == &si->alien) + si->corr_count += 1; + } else if (list == &si->alien) dbg_bld("add to alien: PEB %d, EC %d", pnum, ec); else BUG(); @@ -938,6 +939,19 @@ struct ubi_scan_info *ubi_scan(struct ubi_device *ubi) ubi_msg("empty MTD device detected"); /* + * Few corrupted PEBs are not a problem and may be just a result of + * unclean reboots. However, many of them may indicate some problems + * with the flash HW or driver. Print a warning in this case. + */ + if (si->corr_count >= 8 || si->corr_count >= ubi->peb_count / 4) { + ubi_warn("%d PEBs are corrupted", si->corr_count); + printk(KERN_WARNING "corrupted PEBs are:"); + list_for_each_entry(seb, &si->corr, u.list) + printk(KERN_CONT " %d", seb->pnum); + printk(KERN_CONT "\n"); + } + + /* * In case of unknown erase counter we use the mean erase counter * value. */ diff --git a/drivers/mtd/ubi/scan.h b/drivers/mtd/ubi/scan.h index 1017cf1..bab3169 100644 --- a/drivers/mtd/ubi/scan.h +++ b/drivers/mtd/ubi/scan.h @@ -102,6 +102,7 @@ struct ubi_scan_volume { * @mean_ec: mean erase counter value * @ec_sum: a temporary variable used when calculating @mean_ec * @ec_count: a temporary variable used when calculating @mean_ec + * @corr_count: count of corrupted PEBs * @image_seq_set: indicates @ubi->image_seq is known * * This data structure contains the result of scanning and may be used by other @@ -125,6 +126,7 @@ struct ubi_scan_info { int mean_ec; uint64_t ec_sum; int ec_count; + int corr_count; int image_seq_set; }; -- cgit v0.10.2 From 758d8e46347aee199e7025b8c571bab75d2de63f Mon Sep 17 00:00:00 2001 From: Phil Carmody Date: Thu, 23 Jul 2009 15:29:10 +0200 Subject: UBI: eliminate possible undefined behaviour The assignment to pos when rb is finally NULL is undefined behaviour. Upon seeing that assignment, GCC may assume that rb is not NULL, and the loop condition ``rb'' may be optimised away. Signed-off-by: Phil Carmody Signed-off-by: Artem Bityutskiy diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h index 6a5fe96..c290f51 100644 --- a/drivers/mtd/ubi/ubi.h +++ b/drivers/mtd/ubi/ubi.h @@ -579,7 +579,8 @@ void ubi_do_get_volume_info(struct ubi_device *ubi, struct ubi_volume *vol, for (rb = rb_first(root), \ pos = (rb ? container_of(rb, typeof(*pos), member) : NULL); \ rb; \ - rb = rb_next(rb), pos = container_of(rb, typeof(*pos), member)) + rb = rb_next(rb), \ + pos = (rb ? container_of(rb, typeof(*pos), member) : NULL)) /** * ubi_zalloc_vid_hdr - allocate a volume identifier header object. -- cgit v0.10.2 From 867996b15c1f0a98d2c405bada907e97499ba8c2 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Fri, 24 Jul 2009 15:31:33 +0300 Subject: UBI: introduce flash dump helper Useful for debugging problems, compiled in only if UBI debugging is enabled. This patch also makes the UBI writing function dump the flash if it fails to write. Signed-off-by: Artem Bityutskiy diff --git a/drivers/mtd/ubi/debug.c b/drivers/mtd/ubi/debug.c index 54b0186..4876977 100644 --- a/drivers/mtd/ubi/debug.c +++ b/drivers/mtd/ubi/debug.c @@ -196,4 +196,36 @@ void ubi_dbg_dump_mkvol_req(const struct ubi_mkvol_req *req) printk(KERN_DEBUG "\t1st 16 characters of name: %s\n", nm); } +/** + * ubi_dbg_dump_flash - dump a region of flash. + * @ubi: UBI device description object + * @pnum: the physical eraseblock number to dump + * @offset: the starting offset within the physical eraseblock to dump + * @len: the length of the region to dump + */ +void ubi_dbg_dump_flash(struct ubi_device *ubi, int pnum, int offset, int len) +{ + int err; + size_t read; + void *buf; + loff_t addr = (loff_t)pnum * ubi->peb_size + offset; + + buf = vmalloc(len); + if (!buf) + return; + err = ubi->mtd->read(ubi->mtd, addr, len, &read, buf); + if (err && err != -EUCLEAN) { + ubi_err("error %d while reading %d bytes from PEB %d:%d, " + "read %zd bytes", err, len, pnum, offset, read); + goto out; + } + + dbg_msg("dumping %d bytes of data from PEB %d, offset %d", + len, pnum, offset); + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, buf, len, 1); +out: + vfree(buf); + return; +} + #endif /* CONFIG_MTD_UBI_DEBUG */ diff --git a/drivers/mtd/ubi/debug.h b/drivers/mtd/ubi/debug.h index a4da7a0..f30bcb3 100644 --- a/drivers/mtd/ubi/debug.h +++ b/drivers/mtd/ubi/debug.h @@ -55,6 +55,7 @@ void ubi_dbg_dump_vtbl_record(const struct ubi_vtbl_record *r, int idx); void ubi_dbg_dump_sv(const struct ubi_scan_volume *sv); void ubi_dbg_dump_seb(const struct ubi_scan_leb *seb, int type); void ubi_dbg_dump_mkvol_req(const struct ubi_mkvol_req *req); +void ubi_dbg_dump_flash(struct ubi_device *ubi, int pnum, int offset, int len); #ifdef CONFIG_MTD_UBI_DEBUG_MSG /* General debugging messages */ @@ -167,6 +168,7 @@ static inline int ubi_dbg_is_erase_failure(void) #define ubi_dbg_dump_sv(sv) ({}) #define ubi_dbg_dump_seb(seb, type) ({}) #define ubi_dbg_dump_mkvol_req(req) ({}) +#define ubi_dbg_dump_flash(ubi, pnum, offset, len) ({}) #define UBI_IO_DEBUG 0 #define DBG_DISABLE_BGT 0 diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index 4e7bcb2..b693138 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -269,6 +269,7 @@ int ubi_io_write(struct ubi_device *ubi, const void *buf, int pnum, int offset, ubi_err("error %d while writing %d bytes to PEB %d:%d, written " "%zd bytes", err, len, pnum, offset, written); ubi_dbg_dump_stack(); + ubi_dbg_dump_flash(ubi, pnum, offset, len); } else ubi_assert(written == len); -- cgit v0.10.2 From de75c771b4cc4da963164a538a8448128301bc35 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Fri, 24 Jul 2009 16:18:04 +0300 Subject: UBI: improve NOR flash erasure quirk More testing of NOR flash against power cuts showed that sometimes eraseblocks may be unwritable, and we cannot really invalidate them before erasure. But in this case the eraseblock probably contains garbage anyway, and we do not have to invalidate the headers. This assumption might be not true, but this is at least what I have observed. So if we cannot invalidate the headers, we make sure that the PEB does not contain valid VID header. If this is true, everything is fine, otherwise we panic. diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index b693138..8aa51e7 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -476,30 +476,46 @@ out: */ static int nor_erase_prepare(struct ubi_device *ubi, int pnum) { - int err; + int err, err1; size_t written; loff_t addr; uint32_t data = 0; + struct ubi_vid_hdr vid_hdr; addr = (loff_t)pnum * ubi->peb_size + ubi->vid_hdr_aloffset; err = ubi->mtd->write(ubi->mtd, addr, 4, &written, (void *)&data); - if (err) { - ubi_err("error %d while writing 4 bytes to PEB %d:%d, written " - "%zd bytes", err, pnum, ubi->vid_hdr_aloffset, written); - ubi_dbg_dump_stack(); - return err; + if (!err) { + addr -= ubi->vid_hdr_aloffset; + err = ubi->mtd->write(ubi->mtd, addr, 4, &written, + (void *)&data); + if (!err) + return 0; } - addr -= ubi->vid_hdr_aloffset; - err = ubi->mtd->write(ubi->mtd, addr, 4, &written, (void *)&data); - if (err) { - ubi_err("error %d while writing 4 bytes to PEB %d:%d, written " - "%zd bytes", err, pnum, 0, written); - ubi_dbg_dump_stack(); - return err; - } + /* + * We failed to write to the media. This was observed with Spansion + * S29GL512N NOR flash. Most probably the eraseblock erasure was + * interrupted at a very inappropriate moment, so it became unwritable. + * In this case we probably anyway have garbage in this PEB. + */ + err1 = ubi_io_read_vid_hdr(ubi, pnum, &vid_hdr, 0); + if (err1 == UBI_IO_BAD_VID_HDR) + /* + * The VID header is corrupted, so we can safely erase this + * PEB and not afraid that it will be treated as a valid PEB in + * case of an unclean reboot. + */ + return 0; - return 0; + /* + * The PEB contains a valid VID header, but we cannot invalidate it. + * Supposedly the flash media or the driver is screwed up, so return an + * error. + */ + ubi_err("cannot invalidate PEB %d, write returned %d read returned %d", + pnum, err, err1); + ubi_dbg_dump_flash(ubi, pnum, 0, ubi->peb_size); + return -EIO; } /** -- cgit v0.10.2 From 5ad73d07173e7b76c16bcb8b6cf64d8386019689 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 10 Aug 2009 12:51:56 +0100 Subject: ARM: 5665/1: U300 syscon register updates This adds in a few new register and defines for improved padmux support and some figures that were plain wrong on the targeted U300 platforms. Signed-off-by: Linus Walleij Signed-off-by: Russell King diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h index 1c90d1b..7444f5c 100644 --- a/arch/arm/mach-u300/include/mach/syscon.h +++ b/arch/arm/mach-u300/include/mach/syscon.h @@ -240,8 +240,13 @@ #define U300_SYSCON_PMC1LR_CDI_MASK (0xC000) #define U300_SYSCON_PMC1LR_CDI_CDI (0x0000) #define U300_SYSCON_PMC1LR_CDI_EMIF (0x4000) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_PMC1LR_CDI_CDI2 (0x8000) +#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO (0xC000) +#elif CONFIG_MACH_U300_BS365 #define U300_SYSCON_PMC1LR_CDI_GPIO (0x8000) #define U300_SYSCON_PMC1LR_CDI_WCDMA (0xC000) +#endif #define U300_SYSCON_PMC1LR_PDI_MASK (0x3000) #define U300_SYSCON_PMC1LR_PDI_PDI (0x0000) #define U300_SYSCON_PMC1LR_PDI_EGG (0x1000) @@ -345,19 +350,69 @@ #define U300_SYSCON_MMCR_MASK (0x0003) #define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002) #define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001) - +/* Pull up/down control (R/W) */ +#define U300_SYSCON_PUCR (0x104) +#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE (0x0200) +#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE (0x0100) +#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080) +#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040) +#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F) +/* Padmux 2 control */ +#define U300_SYSCON_PMC2R (0x100) +#define U300_SYSCON_PMC2R_APP_MISC_0_MASK (0x00C0) +#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM (0x0040) +#define U300_SYSCON_PMC2R_APP_MISC_0_MMC (0x0080) +#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 (0x00C0) +#define U300_SYSCON_PMC2R_APP_MISC_1_MASK (0x0300) +#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM (0x0100) +#define U300_SYSCON_PMC2R_APP_MISC_1_MMC (0x0200) +#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 (0x0300) +#define U300_SYSCON_PMC2R_APP_MISC_2_MASK (0x0C00) +#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM (0x0400) +#define U300_SYSCON_PMC2R_APP_MISC_2_MMC (0x0800) +#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 (0x0C00) +#define U300_SYSCON_PMC2R_APP_MISC_3_MASK (0x3000) +#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM (0x1000) +#define U300_SYSCON_PMC2R_APP_MISC_3_MMC (0x2000) +#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 (0x3000) +#define U300_SYSCON_PMC2R_APP_MISC_4_MASK (0xC000) +#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM (0x4000) +#define U300_SYSCON_PMC2R_APP_MISC_4_MMC (0x8000) +#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO (0xC000) /* TODO: More SYSCON registers missing */ #define U300_SYSCON_PMC3R (0x10c) #define U300_SYSCON_PMC3R_APP_MISC_11_MASK (0xc000) #define U300_SYSCON_PMC3R_APP_MISC_11_SPI (0x4000) #define U300_SYSCON_PMC3R_APP_MISC_10_MASK (0x3000) #define U300_SYSCON_PMC3R_APP_MISC_10_SPI (0x1000) -/* TODO: Missing other configs, I just added the SPI stuff */ - +/* TODO: Missing other configs */ +#define U300_SYSCON_PMC4R (0x168) +#define U300_SYSCON_PMC4R_APP_MISC_12_MASK (0x0003) +#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_13_MASK (0x000C) +#define U300_SYSCON_PMC4R_APP_MISC_13_CDI (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA (0x0004) +#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 (0x0008) +#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO (0x000C) +#define U300_SYSCON_PMC4R_APP_MISC_14_MASK (0x0030) +#define U300_SYSCON_PMC4R_APP_MISC_14_CDI (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA (0x0010) +#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 (0x0020) +#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO (0x0030) +#define U300_SYSCON_PMC4R_APP_MISC_16_MASK (0x0300) +#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS (0x0100) +#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N (0x0200) /* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ #define U300_SYSCON_S0CCR (0x120) #define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) #define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000) +#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000) #define U300_SYSCON_S0CCR_CLOCK_INV (0x0200) #define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0) #define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E) @@ -375,6 +430,7 @@ #define U300_SYSCON_S1CCR (0x124) #define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF) #define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000) +#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000) #define U300_SYSCON_S1CCR_CLOCK_INV (0x0200) #define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0) #define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E) @@ -393,6 +449,7 @@ #define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF) #define U300_SYSCON_S2CCR_CLK_STEAL (0x8000) #define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000) +#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000) #define U300_SYSCON_S2CCR_CLOCK_INV (0x0200) #define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0) #define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E) @@ -425,6 +482,44 @@ #define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C) #define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002) #define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001) +/* SC_PLL_IRQ_CONTROL 16bit (R/W) */ +#define U300_SYSCON_PICR (0x0130) +#define U300_SYSCON_PICR_MASK (0x00FF) +#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080) +#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040) +#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020) +#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010) +#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008) +#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004) +#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002) +#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001) +/* SC_PLL_IRQ_STATUS 16 bit (R/-) */ +#define U300_SYSCON_PISR (0x0134) +#define U300_SYSCON_PISR_MASK (0x000F) +#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008) +#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004) +#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002) +#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001) +/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */ +#define U300_SYSCON_PICLR (0x0138) +#define U300_SYSCON_PICLR_MASK (0x000F) +#define U300_SYSCON_PICLR_RWMASK (0x0000) +#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008) +#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004) +#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002) +#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001) +/* CAMIF_CONTROL 16 bit (-/W) */ +#define U300_SYSCON_CICR (0x013C) +#define U300_SYSCON_CICR_MASK (0x0FFF) +#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK (0x0F00) +#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1 (0x0C00) +#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0 (0x0300) +#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK (0x00F0) +#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1 (0x00C0) +#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0 (0x0030) +#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK (0x000F) +#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1 (0x000C) +#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0 (0x0003) /* Clock activity observability register 0 */ #define U300_SYSCON_C0OAR (0x140) #define U300_SYSCON_C0OAR_MASK (0xFFFF) @@ -513,7 +608,7 @@ /** * CPU medium frequency in MHz */ -#define SYSCON_CPU_CLOCK_MEDIUM 104 +#define SYSCON_CPU_CLOCK_MEDIUM 52 /** * CPU low frequency in MHz */ @@ -527,7 +622,7 @@ /** * EMIF medium frequency in MHz */ -#define SYSCON_EMIF_CLOCK_MEDIUM 104 +#define SYSCON_EMIF_CLOCK_MEDIUM 52 /** * EMIF low frequency in MHz */ @@ -541,7 +636,7 @@ /** * AHB medium frequency in MHz */ -#define SYSCON_AHB_CLOCK_MEDIUM 52 +#define SYSCON_AHB_CLOCK_MEDIUM 26 /** * AHB low frequency in MHz */ @@ -553,6 +648,15 @@ enum syscon_busmaster { SYSCON_BM_VIDEO_ENC }; +/* Selectr a resistor or a set of resistors */ +enum syscon_pull_up_down { + SYSCON_PU_KEY_IN_EN, + SYSCON_PU_EMIF_1_8_BIT_EN, + SYSCON_PU_EMIF_1_16_BIT_EN, + SYSCON_PU_EMIF_1_NFIF_READY_EN, + SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN, +}; + /* * Note that this array must match the order of the array "clk_reg" * in syscon.c @@ -575,6 +679,7 @@ enum syscon_clk { SYSCON_CLKCONTROL_SPI, SYSCON_CLKCONTROL_I2S0_CORE, SYSCON_CLKCONTROL_I2S1_CORE, + SYSCON_CLKCONTROL_UART1, SYSCON_CLKCONTROL_AAIF, SYSCON_CLKCONTROL_AHB, SYSCON_CLKCONTROL_APEX, @@ -604,7 +709,8 @@ enum syscon_sysclk_mode { enum syscon_sysclk_req { SYSCON_SYSCLKREQ_DISABLED, - SYSCON_SYSCLKREQ_ACTIVE_LOW + SYSCON_SYSCLKREQ_ACTIVE_LOW, + SYSCON_SYSCLKREQ_MONITOR }; enum syscon_clk_mode { -- cgit v0.10.2 From df1e0520f9434b5b771c854a13dd928727d8673a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 10 Aug 2009 12:52:40 +0100 Subject: ARM: 5666/1: Revamped U300 padmux API This abstracts the hackish padmux API on the U300 platform into something more manageable. It provides a way for drivers to activate/deactivate a certain padmux setting. It will also switch the users of the old API over to using the new style, pushing muxing into the apropriate setup files. Signed-off-by: Linus Walleij Signed-off-by: Russell King diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c index 308cdb1..63c8f27 100644 --- a/arch/arm/mach-u300/gpio.c +++ b/arch/arm/mach-u300/gpio.c @@ -25,11 +25,6 @@ #include #include -/* Need access to SYSCON registers for PADmuxing */ -#include - -#include "padmux.h" - /* Reference to GPIO block clock */ static struct clk *clk; @@ -606,14 +601,6 @@ static int __init gpio_probe(struct platform_device *pdev) writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR); #endif - /* Set up some padmuxing here */ -#ifdef CONFIG_MMC - pmx_set_mission_mode_mmc(); -#endif -#ifdef CONFIG_SPI_PL022 - pmx_set_mission_mode_spi(); -#endif - gpio_set_initial_values(); for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) { diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c index 3138d39..e66284d 100644 --- a/arch/arm/mach-u300/mmc.c +++ b/arch/arm/mach-u300/mmc.c @@ -22,6 +22,7 @@ #include #include "mmc.h" +#include "padmux.h" struct mmci_card_event { struct input_dev *mmc_input; @@ -146,6 +147,7 @@ int __devinit mmc_init(struct amba_device *adev) { struct mmci_card_event *mmci_card; struct device *mmcsd_device = &adev->dev; + struct pmx *pmx; int ret = 0; mmci_card = kzalloc(sizeof(struct mmci_card_event), GFP_KERNEL); @@ -205,6 +207,20 @@ int __devinit mmc_init(struct amba_device *adev) input_set_drvdata(mmci_card->mmc_input, mmci_card); + /* + * Setup padmuxing for MMC. Since this must always be + * compiled into the kernel, pmx is never released. + */ + pmx = pmx_get(mmcsd_device, U300_APP_PMX_MMC_SETTING); + + if (IS_ERR(pmx)) + pr_warning("Could not get padmux handle\n"); + else { + ret = pmx_activate(mmcsd_device, pmx); + if (IS_ERR_VALUE(ret)) + pr_warning("Could not activate padmuxing\n"); + } + ret = gpio_register_callback(U300_GPIO_PIN_MMC_CD, mmci_callback, mmci_card); diff --git a/arch/arm/mach-u300/padmux.c b/arch/arm/mach-u300/padmux.c index f366456..4c93c6c 100644 --- a/arch/arm/mach-u300/padmux.c +++ b/arch/arm/mach-u300/padmux.c @@ -6,53 +6,362 @@ * Copyright (C) 2009 ST-Ericsson AB * License terms: GNU General Public License (GPL) version 2 * U300 PADMUX functions - * Author: Linus Walleij - * + * Author: Martin Persson */ -#include + +#include +#include +#include #include +#include +#include +#include +#include +#include +#include +#include #include #include - #include "padmux.h" -/* Set the PAD MUX to route the MMC reader correctly to GPIO0. */ -void pmx_set_mission_mode_mmc(void) -{ - u16 val; - - val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1LR); - val &= ~U300_SYSCON_PMC1LR_MMCSD_MASK; - writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1LR); - val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1HR); - val &= ~U300_SYSCON_PMC1HR_APP_GPIO_1_MASK; - val |= U300_SYSCON_PMC1HR_APP_GPIO_1_MMC; - writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1HR); -} - -void pmx_set_mission_mode_spi(void) -{ - u16 val; - - /* Set up padmuxing so the SPI port and its chipselects are active */ - val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1HR); - /* - * Activate the SPI port (disable the use of these pins for generic - * GPIO, DSP, AAIF - */ - val &= ~U300_SYSCON_PMC1HR_APP_SPI_2_MASK; - val |= U300_SYSCON_PMC1HR_APP_SPI_2_SPI; - /* - * Use GPIO pin SPI CS1 for CS1 actually (it can be used for other - * things also) - */ - val &= ~U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK; - val |= U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI; - /* - * Use GPIO pin SPI CS2 for CS2 actually (it can be used for other - * things also) - */ - val &= ~U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK; - val |= U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI; - writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1HR); +static DEFINE_MUTEX(pmx_mutex); + +const u32 pmx_registers[] = { + (U300_SYSCON_VBASE + U300_SYSCON_PMC1LR), + (U300_SYSCON_VBASE + U300_SYSCON_PMC1HR), + (U300_SYSCON_VBASE + U300_SYSCON_PMC2R), + (U300_SYSCON_VBASE + U300_SYSCON_PMC3R), + (U300_SYSCON_VBASE + U300_SYSCON_PMC4R) +}; + +/* High level functionality */ + +/* Lazy dog: + * onmask = { + * {"PMC1LR" mask, "PMC1LR" value}, + * {"PMC1HR" mask, "PMC1HR" value}, + * {"PMC2R" mask, "PMC2R" value}, + * {"PMC3R" mask, "PMC3R" value}, + * {"PMC4R" mask, "PMC4R" value} + * } + */ +static struct pmx mmc_setting = { + .setting = U300_APP_PMX_MMC_SETTING, + .default_on = false, + .activated = false, + .name = "MMC", + .onmask = { + {U300_SYSCON_PMC1LR_MMCSD_MASK, + U300_SYSCON_PMC1LR_MMCSD_MMCSD}, + {0, 0}, + {0, 0}, + {0, 0}, + {U300_SYSCON_PMC4R_APP_MISC_12_MASK, + U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO} + }, +}; + +static struct pmx spi_setting = { + .setting = U300_APP_PMX_SPI_SETTING, + .default_on = false, + .activated = false, + .name = "SPI", + .onmask = {{0, 0}, + {U300_SYSCON_PMC1HR_APP_SPI_2_MASK | + U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK | + U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK, + U300_SYSCON_PMC1HR_APP_SPI_2_SPI | + U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI | + U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI}, + {0, 0}, + {0, 0}, + {0, 0} + }, +}; + +/* Available padmux settings */ +static struct pmx *pmx_settings[] = { + &mmc_setting, + &spi_setting, +}; + +static void update_registers(struct pmx *pmx, bool activate) +{ + u16 regval, val, mask; + int i; + + for (i = 0; i < ARRAY_SIZE(pmx_registers); i++) { + if (activate) + val = pmx->onmask[i].val; + else + val = 0; + + mask = pmx->onmask[i].mask; + if (mask != 0) { + regval = readw(pmx_registers[i]); + regval &= ~mask; + regval |= val; + writew(regval, pmx_registers[i]); + } + } +} + +struct pmx *pmx_get(struct device *dev, enum pmx_settings setting) +{ + int i; + struct pmx *pmx = ERR_PTR(-ENOENT); + + if (dev == NULL) + return ERR_PTR(-EINVAL); + + mutex_lock(&pmx_mutex); + for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { + + if (setting == pmx_settings[i]->setting) { + + if (pmx_settings[i]->dev != NULL) { + WARN(1, "padmux: required setting " + "in use by another consumer\n"); + } else { + pmx = pmx_settings[i]; + pmx->dev = dev; + dev_dbg(dev, "padmux: setting nr %d is now " + "bound to %s and ready to use\n", + setting, dev_name(dev)); + break; + } + } + } + mutex_unlock(&pmx_mutex); + + return pmx; +} +EXPORT_SYMBOL(pmx_get); + +int pmx_put(struct device *dev, struct pmx *pmx) +{ + int i; + int ret = -ENOENT; + + if (pmx == NULL || dev == NULL) + return -EINVAL; + + mutex_lock(&pmx_mutex); + for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { + + if (pmx->setting == pmx_settings[i]->setting) { + + if (dev != pmx->dev) { + WARN(1, "padmux: cannot release handle as " + "it is bound to another consumer\n"); + ret = -EINVAL; + break; + } else { + pmx_settings[i]->dev = NULL; + ret = 0; + break; + } + } + } + mutex_unlock(&pmx_mutex); + + return ret; +} +EXPORT_SYMBOL(pmx_put); + +int pmx_activate(struct device *dev, struct pmx *pmx) +{ + int i, j, ret; + ret = 0; + + if (pmx == NULL || dev == NULL) + return -EINVAL; + + mutex_lock(&pmx_mutex); + + /* Make sure the required bits are not used */ + for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { + + if (pmx_settings[i]->dev == NULL || pmx_settings[i] == pmx) + continue; + + for (j = 0; j < ARRAY_SIZE(pmx_registers); j++) { + + if (pmx_settings[i]->onmask[j].mask & pmx-> + onmask[j].mask) { + /* More than one entry on the same bits */ + WARN(1, "padmux: cannot activate " + "setting. Bit conflict with " + "an active setting\n"); + + ret = -EUSERS; + goto exit; + } + } + } + update_registers(pmx, true); + pmx->activated = true; + dev_dbg(dev, "padmux: setting nr %d is activated\n", + pmx->setting); + +exit: + mutex_unlock(&pmx_mutex); + return ret; +} +EXPORT_SYMBOL(pmx_activate); + +int pmx_deactivate(struct device *dev, struct pmx *pmx) +{ + int i; + int ret = -ENOENT; + + if (pmx == NULL || dev == NULL) + return -EINVAL; + + mutex_lock(&pmx_mutex); + for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { + + if (pmx_settings[i]->dev == NULL) + continue; + + if (pmx->setting == pmx_settings[i]->setting) { + + if (dev != pmx->dev) { + WARN(1, "padmux: cannot deactivate " + "pmx setting as it was activated " + "by another consumer\n"); + + ret = -EBUSY; + continue; + } else { + update_registers(pmx, false); + pmx_settings[i]->dev = NULL; + pmx->activated = false; + ret = 0; + dev_dbg(dev, "padmux: setting nr %d is deactivated", + pmx->setting); + break; + } + } + } + mutex_unlock(&pmx_mutex); + + return ret; +} +EXPORT_SYMBOL(pmx_deactivate); + +/* + * For internal use only. If it is to be exported, + * it should be reentrant. Notice that pmx_activate + * (i.e. runtime settings) always override default settings. + */ +static int pmx_set_default(void) +{ + /* Used to identify several entries on the same bits */ + u16 modbits[ARRAY_SIZE(pmx_registers)]; + + int i, j; + + memset(modbits, 0, ARRAY_SIZE(pmx_registers) * sizeof(u16)); + + for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { + + if (!pmx_settings[i]->default_on) + continue; + + for (j = 0; j < ARRAY_SIZE(pmx_registers); j++) { + + /* Make sure there is only one entry on the same bits */ + if (modbits[j] & pmx_settings[i]->onmask[j].mask) { + BUG(); + return -EUSERS; + } + modbits[j] |= pmx_settings[i]->onmask[j].mask; + } + update_registers(pmx_settings[i], true); + } + return 0; } + +#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG)) +static int pmx_show(struct seq_file *s, void *data) +{ + int i; + seq_printf(s, "-------------------------------------------------\n"); + seq_printf(s, "SETTING BOUND TO DEVICE STATE\n"); + seq_printf(s, "-------------------------------------------------\n"); + mutex_lock(&pmx_mutex); + for (i = 0; i < ARRAY_SIZE(pmx_settings); i++) { + /* Format pmx and device name nicely */ + char cdp[33]; + int chars; + + chars = snprintf(&cdp[0], 17, "%s", pmx_settings[i]->name); + while (chars < 16) { + cdp[chars] = ' '; + chars++; + } + chars = snprintf(&cdp[16], 17, "%s", pmx_settings[i]->dev ? + dev_name(pmx_settings[i]->dev) : "N/A"); + while (chars < 16) { + cdp[chars+16] = ' '; + chars++; + } + cdp[32] = '\0'; + + seq_printf(s, + "%s\t%s\n", + &cdp[0], + pmx_settings[i]->activated ? + "ACTIVATED" : "DEACTIVATED" + ); + + } + mutex_unlock(&pmx_mutex); + return 0; +} + +static int pmx_open(struct inode *inode, struct file *file) +{ + return single_open(file, pmx_show, NULL); +} + +static const struct file_operations pmx_operations = { + .owner = THIS_MODULE, + .open = pmx_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init init_pmx_read_debugfs(void) +{ + /* Expose a simple debugfs interface to view pmx settings */ + (void) debugfs_create_file("padmux", S_IFREG | S_IRUGO, + NULL, NULL, + &pmx_operations); + return 0; +} + +/* + * This needs to come in after the core_initcall(), + * because debugfs is not available until + * the subsystems come up. + */ +module_init(init_pmx_read_debugfs); +#endif + +static int __init pmx_init(void) +{ + int ret; + + ret = pmx_set_default(); + + if (IS_ERR_VALUE(ret)) + pr_crit("padmux: default settings could not be set\n"); + + return 0; +} + +/* Should be initialized before consumers */ +core_initcall(pmx_init); diff --git a/arch/arm/mach-u300/padmux.h b/arch/arm/mach-u300/padmux.h index 8c2099a..6e8b860 100644 --- a/arch/arm/mach-u300/padmux.h +++ b/arch/arm/mach-u300/padmux.h @@ -6,14 +6,34 @@ * Copyright (C) 2009 ST-Ericsson AB * License terms: GNU General Public License (GPL) version 2 * U300 PADMUX API - * Author: Linus Walleij - * + * Author: Martin Persson */ #ifndef __MACH_U300_PADMUX_H #define __MACH_U300_PADMUX_H -void pmx_set_mission_mode_mmc(void); -void pmx_set_mission_mode_spi(void); +enum pmx_settings { + U300_APP_PMX_MMC_SETTING, + U300_APP_PMX_SPI_SETTING +}; + +struct pmx_onmask { + u16 mask; /* Mask bits */ + u16 val; /* Value when active */ +}; + +struct pmx { + struct device *dev; + enum pmx_settings setting; + char *name; + bool activated; + bool default_on; + struct pmx_onmask onmask[]; +}; + +struct pmx *pmx_get(struct device *dev, enum pmx_settings setting); +int pmx_put(struct device *dev, struct pmx *pmx); +int pmx_activate(struct device *dev, struct pmx *pmx); +int pmx_deactivate(struct device *dev, struct pmx *pmx); #endif -- cgit v0.10.2 From c7c8c78fdf6e9bd65d8ee879115dc2cd5d9fd0dc Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 14 Aug 2009 10:59:05 +0100 Subject: ARM: 5667/3: U300 SSP/SPI board setup and test This adds a U300 board configuration for the PL022 SSP/SPI PrimeCell driver recently merged to the 2.6.31-rc series. Further it adds a dummy loopback SPI chip that can be used for testing the SPI functionality on a running system using the loopback mode of PL022. Signed-off-by: Linus Walleij Signed-off-by: Russell King diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index 337b9aa..801b21e 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -81,6 +81,18 @@ config MACH_U300_SEMI_IS_SHARED Memory Interface) from both from access and application side. +config MACH_U300_SPIDUMMY + bool "SSP/SPI dummy chip" + select SPI + select SPI_MASTER + select SPI_PL022 + help + This creates a small kernel module that creates a dummy + SPI device to be used for loopback tests. Regularly used + to test reference designs. If you're not testing SPI, + you don't need it. Selecting this will activate the + SPI framework and ARM PL022 support. + comment "All the settings below must match the bootloader's settings" config MACH_U300_ACCESS_MEM_SIZE diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile index 24950e0..4941f89 100644 --- a/arch/arm/mach-u300/Makefile +++ b/arch/arm/mach-u300/Makefile @@ -9,3 +9,5 @@ obj- := obj-$(CONFIG_ARCH_U300) += u300.o obj-$(CONFIG_MMC) += mmc.o +obj-$(CONFIG_SPI_PL022) += spi.o +obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 89b3ccf..38d08a1 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -32,6 +32,7 @@ #include "clock.h" #include "mmc.h" +#include "spi.h" /* * Static I/O mappings that are needed for booting the U300 platforms. The @@ -611,6 +612,8 @@ void __init u300_init_devices(void) /* Wait for the PLL208 to lock if not locked in yet */ while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) & U300_SYSCON_CSR_PLL208_LOCK_IND)); + /* Initialize SPI device with some board specifics */ + u300_spi_init(&pl022_device); /* Register the AMBA devices in the AMBA bus abstraction layer */ u300_clock_primecells(); @@ -622,6 +625,9 @@ void __init u300_init_devices(void) u300_assign_physmem(); + /* Register subdevices on the SPI bus */ + u300_spi_register_board_devices(); + /* Register the platform devices */ platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c new file mode 100644 index 0000000..962f9de --- /dev/null +++ b/arch/arm/mach-u300/dummyspichip.c @@ -0,0 +1,290 @@ +/* + * arch/arm/mach-u300/dummyspichip.c + * + * Copyright (C) 2007-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * This is a dummy loopback SPI "chip" used for testing SPI. + * Author: Linus Walleij + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +/* + * WARNING! Do not include this pl022-specific controller header + * for any generic driver. It is only done in this dummy chip + * because we alter the chip configuration in order to test some + * different settings on the loopback device. Normal chip configs + * shall be STATIC and not altered by the driver! + */ +#include + +struct dummy { + struct device *dev; + struct mutex lock; +}; + +#define DMA_TEST_SIZE 2048 + +/* When we cat /sys/bus/spi/devices/spi0.0/looptest this will be triggered */ +static ssize_t dummy_looptest(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct spi_device *spi = to_spi_device(dev); + struct dummy *p_dummy = dev_get_drvdata(&spi->dev); + + /* + * WARNING! Do not dereference the chip-specific data in any normal + * driver for a chip. It is usually STATIC and shall not be read + * or written to. Your chip driver should NOT depend on fields in this + * struct, this is just used here to alter the behaviour of the chip + * in order to perform tests. + */ + struct pl022_config_chip *chip_info = spi->controller_data; + int status; + u8 txbuf[14] = {0xDE, 0xAD, 0xBE, 0xEF, 0x2B, 0xAD, + 0xCA, 0xFE, 0xBA, 0xBE, 0xB1, 0x05, + 0xF0, 0x0D}; + u8 rxbuf[14]; + u8 *bigtxbuf_virtual; + u8 *bigrxbuf_virtual; + + if (mutex_lock_interruptible(&p_dummy->lock)) + return -ERESTARTSYS; + + bigtxbuf_virtual = kmalloc(DMA_TEST_SIZE, GFP_KERNEL); + if (bigtxbuf_virtual == NULL) { + status = -ENOMEM; + goto out; + } + bigrxbuf_virtual = kmalloc(DMA_TEST_SIZE, GFP_KERNEL); + + /* Fill TXBUF with some happy pattern */ + memset(bigtxbuf_virtual, 0xAA, DMA_TEST_SIZE); + + /* + * Force chip to 8 bit mode + * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC! + */ + chip_info->data_size = SSP_DATA_BITS_8; + /* You should NOT DO THIS EITHER */ + spi->master->setup(spi); + + /* Now run the tests for 8bit mode */ + pr_info("Simple test 1: write 0xAA byte, read back garbage byte " + "in 8bit mode\n"); + status = spi_w8r8(spi, 0xAA); + if (status < 0) + pr_warning("Siple test 1: FAILURE: spi_write_then_read " + "failed with status %d\n", status); + else + pr_info("Simple test 1: SUCCESS!\n"); + + pr_info("Simple test 2: write 8 bytes, read back 8 bytes garbage " + "in 8bit mode (full FIFO)\n"); + status = spi_write_then_read(spi, &txbuf[0], 8, &rxbuf[0], 8); + if (status < 0) + pr_warning("Simple test 2: FAILURE: spi_write_then_read() " + "failed with status %d\n", status); + else + pr_info("Simple test 2: SUCCESS!\n"); + + pr_info("Simple test 3: write 14 bytes, read back 14 bytes garbage " + "in 8bit mode (see if we overflow FIFO)\n"); + status = spi_write_then_read(spi, &txbuf[0], 14, &rxbuf[0], 14); + if (status < 0) + pr_warning("Simple test 3: FAILURE: failed with status %d " + "(probably FIFO overrun)\n", status); + else + pr_info("Simple test 3: SUCCESS!\n"); + + pr_info("Simple test 4: write 8 bytes with spi_write(), read 8 " + "bytes garbage with spi_read() in 8bit mode\n"); + status = spi_write(spi, &txbuf[0], 8); + if (status < 0) + pr_warning("Simple test 4 step 1: FAILURE: spi_write() " + "failed with status %d\n", status); + else + pr_info("Simple test 4 step 1: SUCCESS!\n"); + status = spi_read(spi, &rxbuf[0], 8); + if (status < 0) + pr_warning("Simple test 4 step 2: FAILURE: spi_read() " + "failed with status %d\n", status); + else + pr_info("Simple test 4 step 2: SUCCESS!\n"); + + pr_info("Simple test 5: write 14 bytes with spi_write(), read " + "14 bytes garbage with spi_read() in 8bit mode\n"); + status = spi_write(spi, &txbuf[0], 14); + if (status < 0) + pr_warning("Simple test 5 step 1: FAILURE: spi_write() " + "failed with status %d (probably FIFO overrun)\n", + status); + else + pr_info("Simple test 5 step 1: SUCCESS!\n"); + status = spi_read(spi, &rxbuf[0], 14); + if (status < 0) + pr_warning("Simple test 5 step 2: FAILURE: spi_read() " + "failed with status %d (probably FIFO overrun)\n", + status); + else + pr_info("Simple test 5: SUCCESS!\n"); + + pr_info("Simple test 6: write %d bytes with spi_write(), " + "read %d bytes garbage with spi_read() in 8bit mode\n", + DMA_TEST_SIZE, DMA_TEST_SIZE); + status = spi_write(spi, &bigtxbuf_virtual[0], DMA_TEST_SIZE); + if (status < 0) + pr_warning("Simple test 6 step 1: FAILURE: spi_write() " + "failed with status %d (probably FIFO overrun)\n", + status); + else + pr_info("Simple test 6 step 1: SUCCESS!\n"); + status = spi_read(spi, &bigrxbuf_virtual[0], DMA_TEST_SIZE); + if (status < 0) + pr_warning("Simple test 6 step 2: FAILURE: spi_read() " + "failed with status %d (probably FIFO overrun)\n", + status); + else + pr_info("Simple test 6: SUCCESS!\n"); + + + /* + * Force chip to 16 bit mode + * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC! + */ + chip_info->data_size = SSP_DATA_BITS_16; + /* You should NOT DO THIS EITHER */ + spi->master->setup(spi); + + pr_info("Simple test 7: write 0xAA byte, read back garbage byte " + "in 16bit bus mode\n"); + status = spi_w8r8(spi, 0xAA); + if (status == -EIO) + pr_info("Simple test 7: SUCCESS! (expected failure with " + "status EIO)\n"); + else if (status < 0) + pr_warning("Siple test 7: FAILURE: spi_write_then_read " + "failed with status %d\n", status); + else + pr_warning("Siple test 7: FAILURE: spi_write_then_read " + "succeeded but it was expected to fail!\n"); + + pr_info("Simple test 8: write 8 bytes, read back 8 bytes garbage " + "in 16bit mode (full FIFO)\n"); + status = spi_write_then_read(spi, &txbuf[0], 8, &rxbuf[0], 8); + if (status < 0) + pr_warning("Simple test 8: FAILURE: spi_write_then_read() " + "failed with status %d\n", status); + else + pr_info("Simple test 8: SUCCESS!\n"); + + pr_info("Simple test 9: write 14 bytes, read back 14 bytes garbage " + "in 16bit mode (see if we overflow FIFO)\n"); + status = spi_write_then_read(spi, &txbuf[0], 14, &rxbuf[0], 14); + if (status < 0) + pr_warning("Simple test 9: FAILURE: failed with status %d " + "(probably FIFO overrun)\n", status); + else + pr_info("Simple test 9: SUCCESS!\n"); + + pr_info("Simple test 10: write %d bytes with spi_write(), " + "read %d bytes garbage with spi_read() in 16bit mode\n", + DMA_TEST_SIZE, DMA_TEST_SIZE); + status = spi_write(spi, &bigtxbuf_virtual[0], DMA_TEST_SIZE); + if (status < 0) + pr_warning("Simple test 10 step 1: FAILURE: spi_write() " + "failed with status %d (probably FIFO overrun)\n", + status); + else + pr_info("Simple test 10 step 1: SUCCESS!\n"); + + status = spi_read(spi, &bigrxbuf_virtual[0], DMA_TEST_SIZE); + if (status < 0) + pr_warning("Simple test 10 step 2: FAILURE: spi_read() " + "failed with status %d (probably FIFO overrun)\n", + status); + else + pr_info("Simple test 10: SUCCESS!\n"); + + status = sprintf(buf, "loop test complete\n"); + kfree(bigrxbuf_virtual); + kfree(bigtxbuf_virtual); + out: + mutex_unlock(&p_dummy->lock); + return status; +} + +static DEVICE_ATTR(looptest, S_IRUGO, dummy_looptest, NULL); + +static int __devinit pl022_dummy_probe(struct spi_device *spi) +{ + struct dummy *p_dummy; + int status; + + dev_info(&spi->dev, "probing dummy SPI device\n"); + + p_dummy = kzalloc(sizeof *p_dummy, GFP_KERNEL); + if (!p_dummy) + return -ENOMEM; + + dev_set_drvdata(&spi->dev, p_dummy); + mutex_init(&p_dummy->lock); + + /* sysfs hook */ + status = device_create_file(&spi->dev, &dev_attr_looptest); + if (status) { + dev_dbg(&spi->dev, "device_create_file looptest failure.\n"); + goto out_dev_create_looptest_failed; + } + + return 0; + +out_dev_create_looptest_failed: + dev_set_drvdata(&spi->dev, NULL); + kfree(p_dummy); + return status; +} + +static int __devexit pl022_dummy_remove(struct spi_device *spi) +{ + struct dummy *p_dummy = dev_get_drvdata(&spi->dev); + + dev_info(&spi->dev, "removing dummy SPI device\n"); + device_remove_file(&spi->dev, &dev_attr_looptest); + dev_set_drvdata(&spi->dev, NULL); + kfree(p_dummy); + + return 0; +} + +static struct spi_driver pl022_dummy_driver = { + .driver = { + .name = "spi-dummy", + .owner = THIS_MODULE, + }, + .probe = pl022_dummy_probe, + .remove = __devexit_p(pl022_dummy_remove), +}; + +static int __init pl022_init_dummy(void) +{ + return spi_register_driver(&pl022_dummy_driver); +} + +static void __exit pl022_exit_dummy(void) +{ + spi_unregister_driver(&pl022_dummy_driver); +} + +module_init(pl022_init_dummy); +module_exit(pl022_exit_dummy); + +MODULE_AUTHOR("Linus Walleij "); +MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c new file mode 100644 index 0000000..307d007 --- /dev/null +++ b/arch/arm/mach-u300/spi.c @@ -0,0 +1,124 @@ +/* + * arch/arm/mach-u300/spi.c + * + * Copyright (C) 2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * + * Author: Linus Walleij + */ +#include +#include +#include +#include +#include +#include "padmux.h" + +/* + * The following is for the actual devices on the SSP/SPI bus + */ +#ifdef CONFIG_MACH_U300_SPIDUMMY +static void select_dummy_chip(u32 chipselect) +{ + pr_debug("CORE: %s called with CS=0x%x (%s)\n", + __func__, + chipselect, + chipselect ? "unselect chip" : "select chip"); + /* + * Here you would write the chip select value to the GPIO pins if + * this was a real chip (but this is a loopback dummy). + */ +} + +struct pl022_config_chip dummy_chip_info = { + /* Nominally this is LOOPBACK_DISABLED, but this is our dummy chip! */ + .lbm = LOOPBACK_ENABLED, + /* + * available POLLING_TRANSFER and INTERRUPT_TRANSFER, + * DMA_TRANSFER does not work + */ + .com_mode = INTERRUPT_TRANSFER, + .iface = SSP_INTERFACE_MOTOROLA_SPI, + /* We can only act as master but SSP_SLAVE is possible in theory */ + .hierarchy = SSP_MASTER, + /* 0 = drive TX even as slave, 1 = do not drive TX as slave */ + .slave_tx_disable = 0, + /* LSB first */ + .endian_tx = SSP_TX_LSB, + .endian_rx = SSP_RX_LSB, + .data_size = SSP_DATA_BITS_8, /* used to be 12 in some default */ + .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, + .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, + .clk_phase = SSP_CLK_FALLING_EDGE, + .clk_pol = SSP_CLK_POL_IDLE_LOW, + .ctrl_len = SSP_BITS_12, + .wait_state = SSP_MWIRE_WAIT_ZERO, + .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, + /* + * This is where you insert a call to a function to enable CS + * (usually GPIO) for a certain chip. + */ + .cs_control = select_dummy_chip, +}; +#endif + +static struct spi_board_info u300_spi_devices[] = { +#ifdef CONFIG_MACH_U300_SPIDUMMY + { + /* A dummy chip used for loopback tests */ + .modalias = "spi-dummy", + /* Really dummy, pass in additional chip config here */ + .platform_data = NULL, + /* This defines how the controller shall handle the device */ + .controller_data = &dummy_chip_info, + /* .irq - no external IRQ routed from this device */ + .max_speed_hz = 1000000, + .bus_num = 0, /* Only one bus on this chip */ + .chip_select = 0, + /* Means SPI_CS_HIGH, change if e.g low CS */ + .mode = 0, + }, +#endif +}; + +static struct pl022_ssp_controller ssp_platform_data = { + /* If you have several SPI buses this varies, we have only bus 0 */ + .bus_id = 0, + /* Set this to 1 when we think we got DMA working */ + .enable_dma = 0, + /* + * On the APP CPU GPIO 4, 5 and 6 are connected as generic + * chip selects for SPI. (Same on U330, U335 and U365.) + * TODO: make sure the GPIO driver can select these properly + * and do padmuxing accordingly too. + */ + .num_chipselect = 3, +}; + + +void __init u300_spi_init(struct amba_device *adev) +{ + struct pmx *pmx; + + adev->dev.platform_data = &ssp_platform_data; + /* + * Setup padmuxing for SPI. Since this must always be + * compiled into the kernel, pmx is never released. + */ + pmx = pmx_get(&adev->dev, U300_APP_PMX_SPI_SETTING); + + if (IS_ERR(pmx)) + dev_warn(&adev->dev, "Could not get padmux handle\n"); + else { + int ret; + + ret = pmx_activate(&adev->dev, pmx); + if (IS_ERR_VALUE(ret)) + dev_warn(&adev->dev, "Could not activate padmuxing\n"); + } + +} +void __init u300_spi_register_board_devices(void) +{ + /* Register any SPI devices */ + spi_register_board_info(u300_spi_devices, ARRAY_SIZE(u300_spi_devices)); +} diff --git a/arch/arm/mach-u300/spi.h b/arch/arm/mach-u300/spi.h new file mode 100644 index 0000000..bd3d867 --- /dev/null +++ b/arch/arm/mach-u300/spi.h @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-u300/spi.h + * + * Copyright (C) 2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * + * Author: Linus Walleij + */ +#ifndef SPI_H +#define SPI_H +#include + +#ifdef CONFIG_SPI_PL022 +void __init u300_spi_init(struct amba_device *adev); +void __init u300_spi_register_board_devices(void); +#else +/* Compile out SPI support if PL022 is not selected */ +static inline void __init u300_spi_init(struct amba_device *adev) +{ +} +static inline void __init u300_spi_register_board_devices(void) +{ +} +#endif + +#endif -- cgit v0.10.2 From 6be2a0cacc1ed6899a53172e2e9b7a3587be0bea Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 13 Aug 2009 21:42:01 +0100 Subject: ARM: 5668/2: U300 I2C board setup This sets up the U300 I2C subdevices so that the AB3100 analog baseband ASIC is properly detected and also the camera devices in the U335 reference design get properly registered. Signed-off-by: Linus Walleij Signed-off-by: Russell King diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile index 4941f89..885b5c0 100644 --- a/arch/arm/mach-u300/Makefile +++ b/arch/arm/mach-u300/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_ARCH_U300) += u300.o obj-$(CONFIG_MMC) += mmc.o obj-$(CONFIG_SPI_PL022) += spi.o obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o +obj-$(CONFIG_I2C_STU300) += i2c.o diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 38d08a1..bad1ba2 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -33,6 +33,7 @@ #include "clock.h" #include "mmc.h" #include "spi.h" +#include "i2c.h" /* * Static I/O mappings that are needed for booting the U300 platforms. The @@ -379,14 +380,14 @@ static struct platform_device wdog_device = { }; static struct platform_device i2c0_device = { - .name = "stddci2c", + .name = "stu300", .id = 0, .num_resources = ARRAY_SIZE(i2c0_resources), .resource = i2c0_resources, }; static struct platform_device i2c1_device = { - .name = "stddci2c", + .name = "stu300", .id = 1, .num_resources = ARRAY_SIZE(i2c1_resources), .resource = i2c1_resources, @@ -625,6 +626,9 @@ void __init u300_init_devices(void) u300_assign_physmem(); + /* Register subdevices on the I2C buses */ + u300_i2c_register_board_devices(); + /* Register subdevices on the SPI bus */ u300_spi_register_board_devices(); diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c new file mode 100644 index 0000000..10be1f8 --- /dev/null +++ b/arch/arm/mach-u300/i2c.c @@ -0,0 +1,43 @@ +/* + * arch/arm/mach-u300/i2c.c + * + * Copyright (C) 2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * + * Register board i2c devices + * Author: Linus Walleij + */ +#include +#include +#include + +static struct i2c_board_info __initdata bus0_i2c_board_info[] = { + { + .type = "ab3100", + .addr = 0x48, + .irq = IRQ_U300_IRQ0_EXT, + }, +}; + +static struct i2c_board_info __initdata bus1_i2c_board_info[] = { +#ifdef CONFIG_MACH_U300_BS335 + { + .type = "fwcam", + .addr = 0x10, + }, + { + .type = "fwcam", + .addr = 0x5d, + }, +#else + { }, +#endif +}; + +void __init u300_i2c_register_board_devices(void) +{ + i2c_register_board_info(0, bus0_i2c_board_info, + ARRAY_SIZE(bus0_i2c_board_info)); + i2c_register_board_info(1, bus1_i2c_board_info, + ARRAY_SIZE(bus1_i2c_board_info)); +} diff --git a/arch/arm/mach-u300/i2c.h b/arch/arm/mach-u300/i2c.h new file mode 100644 index 0000000..485c02e --- /dev/null +++ b/arch/arm/mach-u300/i2c.h @@ -0,0 +1,23 @@ +/* + * arch/arm/mach-u300/i2c.h + * + * Copyright (C) 2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * + * Register board i2c devices + * Author: Linus Walleij + */ + +#ifndef MACH_U300_I2C_H +#define MACH_U300_I2C_H + +#ifdef CONFIG_I2C_STU300 +void __init u300_i2c_register_board_devices(void); +#else +/* Compile out this stuff if no I2C adapter is available */ +static inline void __init u300_i2c_register_board_devices(void) +{ +} +#endif + +#endif -- cgit v0.10.2 From 9e2a7e6f5f1091965c78e01e87af05607bbf937f Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 18 Aug 2009 13:47:30 -0700 Subject: iop33x: update defconfig (default atu to on) By default the iop3xx configurations are set to boot the platforms over an nfs root configuration. Since commit c34002c1 "iop: unconditionally initialize the ATU on platforms known to be 'hosts'" this configuration also requires iop3xx_init_atu=y to be specified on the kernel command line. Signed-off-by: Dan Williams diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig index eec4882..ed2d59d 100644 --- a/arch/arm/configs/iop33x_defconfig +++ b/arch/arm/configs/iop33x_defconfig @@ -1,29 +1,26 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.24-rc5 -# Wed Dec 12 16:11:27 2007 +# Linux kernel version: 2.6.31-rc6 +# Tue Aug 18 13:41:41 2009 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_GENERIC_GPIO is not set -# CONFIG_GENERIC_TIME is not set -# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_GENERIC_GPIO=y CONFIG_MMU=y -# CONFIG_NO_IOPORT is not set CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -40,21 +37,39 @@ CONFIG_SYSVIPC_SYSCTL=y CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set # CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +# CONFIG_CLASSIC_RCU is not set +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_FAIR_USER_SCHED=y -# CONFIG_FAIR_CGROUP_SCHED is not set -CONFIG_SYSFS_DEPRECATED=y +# CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y # CONFIG_EMBEDDED is not set CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y @@ -67,29 +82,48 @@ CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y -CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -103,6 +137,7 @@ CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set # # System Type @@ -112,15 +147,15 @@ CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set CONFIG_ARCH_IOP33X=y @@ -128,19 +163,26 @@ CONFIG_ARCH_IOP33X=y # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_W90X900 is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -CONFIG_IOP3XX_ATU=y # # IOP33x Implementation Options @@ -151,14 +193,6 @@ CONFIG_IOP3XX_ATU=y # CONFIG_ARCH_IQ80331=y CONFIG_MACH_IQ80332=y - -# -# Boot options -# - -# -# Power management -# CONFIG_PLAT_IOP=y # @@ -168,6 +202,7 @@ CONFIG_CPU_32=y CONFIG_CPU_XSCALE=y CONFIG_CPU_32v5=y CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_NOIFAR=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_TLB_V4WBI=y CONFIG_CPU_CP15=y @@ -178,7 +213,6 @@ CONFIG_CPU_CP15_MMU=y # # CONFIG_ARM_THUMB is not set # CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_OUTER_CACHE is not set # CONFIG_IWMMXT is not set CONFIG_XSCALE_PMU=y @@ -190,41 +224,55 @@ CONFIG_PCI_SYSCALL=y # CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_PCI_LEGACY=y # CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set # CONFIG_PCCARD is not set # # Kernel Features # -# CONFIG_TICK_ONESHOT is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 # CONFIG_PREEMPT is not set CONFIG_HZ=100 # CONFIG_AEABI is not set -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set # # Boot options # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp cachepolicy=writealloc" +CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp cachepolicy=writealloc iop3xx_init_atu=y" # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set # +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# # Floating point emulation # @@ -239,6 +287,8 @@ CONFIG_FPE_NWFPE=y # Userspace binary formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=y # CONFIG_BINFMT_MISC is not set # CONFIG_ARTHUR is not set @@ -247,11 +297,7 @@ CONFIG_BINFMT_AOUT=y # Power management options # # CONFIG_PM is not set -CONFIG_SUSPEND_UP_POSSIBLE=y - -# -# Networking -# +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y # @@ -264,6 +310,7 @@ CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y @@ -310,6 +357,7 @@ CONFIG_IPV6=y # CONFIG_IPV6_SIT is not set # CONFIG_IPV6_TUNNEL is not set # CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set @@ -317,6 +365,7 @@ CONFIG_IPV6=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -326,24 +375,31 @@ CONFIG_IPV6=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_OLD_REGULATORY is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_LIB80211 is not set # -# Wireless +# CFG80211 needs to be enabled for MAC80211 # -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 +# CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -357,7 +413,9 @@ CONFIG_IPV6=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set @@ -366,12 +424,14 @@ CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y # CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -421,9 +481,7 @@ CONFIG_MTD_CFI_UTIL=y # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0x0 -CONFIG_MTD_PHYSMAP_LEN=0x0 -CONFIG_MTD_PHYSMAP_BANKWIDTH=1 +# CONFIG_MTD_PHYSMAP_COMPAT is not set # CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set @@ -447,6 +505,11 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=1 # CONFIG_MTD_ONENAND is not set # +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# # UBI - Unsorted block images # # CONFIG_MTD_UBI is not set @@ -463,14 +526,29 @@ CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set -# CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # @@ -492,10 +570,6 @@ CONFIG_BLK_DEV_SD=y # CONFIG_BLK_DEV_SR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -512,6 +586,8 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_3W_9XXX is not set # CONFIG_SCSI_ACARD is not set @@ -520,13 +596,18 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_AIC7XXX_OLD is not set # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT2SAS is not set # CONFIG_SCSI_HPTIOP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_IPS is not set @@ -543,15 +624,18 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set # CONFIG_ATA is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=y CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y # CONFIG_MD_RAID10 is not set CONFIG_MD_RAID456=y -# CONFIG_MD_RAID5_RESHAPE is not set +CONFIG_MD_RAID6_PQ=y # CONFIG_MD_MULTIPATH is not set # CONFIG_MD_FAULTY is not set CONFIG_BLK_DEV_DM=y @@ -568,27 +652,34 @@ CONFIG_BLK_DEV_DM=y # # IEEE 1394 (FireWire) support # + +# +# You can enable one or both FireWire driver stacks. +# + +# +# See the help texts for more information. +# # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set -# CONFIG_IP1000 is not set # CONFIG_ARCNET is not set # CONFIG_NET_ETHERNET is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set CONFIG_E1000=y -CONFIG_E1000_NAPI=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -596,23 +687,34 @@ CONFIG_E1000_NAPI=y # CONFIG_SIS190 is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set +# CONFIG_CNIC is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set +CONFIG_CHELSIO_T3_DEPENDS=y # CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set +# CONFIG_VXGE is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set +# CONFIG_BNX2X is not set +# CONFIG_QLGE is not set +# CONFIG_SFC is not set +# CONFIG_BE2NET is not set # CONFIG_TR is not set # @@ -620,13 +722,16 @@ CONFIG_NETDEV_10000=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -670,10 +775,13 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set # # Serial drivers @@ -692,11 +800,12 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y -# CONFIG_NVRAM is not set +# CONFIG_HW_RANDOM_TIMERIOMEM is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set @@ -705,16 +814,14 @@ CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y # -# I2C Algorithms +# I2C Hardware Bus support # -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set # -# I2C Hardware Bus support +# PC SMBus host controller drivers # # CONFIG_I2C_ALI1535 is not set # CONFIG_I2C_ALI1563 is not set @@ -722,50 +829,82 @@ CONFIG_I2C_CHARDEV=y # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set +# CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set -CONFIG_I2C_IOP3XX=y # CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_STUB is not set # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_IOP3XX=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Graphics adapter I2C/DDC channel drivers +# # CONFIG_I2C_VOODOO3 is not set # +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# # Miscellaneous I2C Chip support # -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set # CONFIG_DS1682 is not set -# CONFIG_EEPROM_LEGACY is not set # CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set # -# SPI support +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# +# SPI GPIO expanders: # -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set @@ -773,13 +912,17 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set @@ -794,16 +937,23 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_VT8231 is not set @@ -812,28 +962,38 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -CONFIG_DAB=y +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support @@ -854,15 +1014,16 @@ CONFIG_DAB=y # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -870,14 +1031,21 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# Enable Host or Gadget support to see Inventra options # # -# USB Gadget Support +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_UWB is not set # CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set # CONFIG_NEW_LEDS is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set @@ -893,6 +1061,12 @@ CONFIG_DMA_ENGINE=y # DMA Clients # CONFIG_NET_DMA=y +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems @@ -901,10 +1075,11 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set @@ -913,17 +1088,23 @@ CONFIG_FS_MBCACHE=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set # +# Caches +# +# CONFIG_FSCACHE is not set + +# # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set @@ -941,15 +1122,13 @@ CONFIG_DNOTIFY=y # CONFIG_PROC_FS=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# +CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -959,29 +1138,31 @@ CONFIG_TMPFS=y # CONFIG_EFS_FS is not set # CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set +CONFIG_ROOT_NFS=y CONFIG_NFSD=y CONFIG_NFSD_V3=y # CONFIG_NFSD_V3_ACL is not set # CONFIG_NFSD_V4 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y -# CONFIG_SUNRPC_BIND34 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1013,9 +1194,6 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_SYSV68_PARTITION is not set # CONFIG_NLS is not set # CONFIG_DLM is not set -CONFIG_INSTRUMENTATION=y -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set # # Kernel hacking @@ -1023,6 +1201,7 @@ CONFIG_INSTRUMENTATION=y # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set @@ -1030,10 +1209,17 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set # CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set @@ -1047,16 +1233,41 @@ CONFIG_SCHED_DEBUG=y CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set CONFIG_FRAME_POINTER=y -# CONFIG_FORCED_INLINING is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set CONFIG_DEBUG_USER=y # CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y # CONFIG_DEBUG_ICEDCC is not set @@ -1065,24 +1276,117 @@ CONFIG_DEBUG_LL=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_XOR_BLOCKS=y CONFIG_ASYNC_CORE=y CONFIG_ASYNC_MEMCPY=y CONFIG_ASYNC_XOR=y -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set # # Library routines # +CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set # CONFIG_CRC32 is not set # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_PLIST=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- cgit v0.10.2 From 5b9eda3313b678f20f2bec08e8173f93e85f6c14 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Fri, 31 Jul 2009 12:16:21 +0300 Subject: iop3xx: ATU and PCI memory configuration corrected There are two 64 MB outbound memory windows at bus addresses 0x80000000..0x83ffffff and 0x84000000..0x87ffffff for PCI memory. Currently, on iop32x, only the lower window is available for allocations, limiting the available space to 64 MB. On iop33x the full 128 MB can be allocated, but the translation value is wrong for the upper window. The patch enables the full 128 MB space on iop32x and corrects the initialization of OMWTVR1. Redundant definitions are deleted. Tested using a Thecus N2100 board with a graphics adapter in the expansion slot. Both windows are in use: 00:05.0 VGA compatible controller: XGI Technology Inc. (eXtreme Graphics Innovation) Volari Z7 (prog-if 00 [VGA controller]) [...] Region 0: Memory at 80000000 (32-bit, prefetchable) [size=64M] Region 1: Memory at 84080000 (32-bit, non-prefetchable) [size=256K] Signed-off-by: Aaro Koskinen Cc: Lennert Buytenhek Signed-off-by: Dan Williams diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 4b8e7f5..8d60ad2 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h @@ -215,6 +215,7 @@ extern int iop3xx_get_init_atu(void); * IOP3XX I/O and Mem space regions for PCI autoconfiguration */ #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 +#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000 #define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 #define IOP3XX_PCI_LOWER_IO_PA 0x90000000 diff --git a/arch/arm/mach-iop32x/include/mach/iop32x.h b/arch/arm/mach-iop32x/include/mach/iop32x.h index abd9eb4..941f363 100644 --- a/arch/arm/mach-iop32x/include/mach/iop32x.h +++ b/arch/arm/mach-iop32x/include/mach/iop32x.h @@ -31,7 +31,5 @@ #define IOP32X_MAX_RAM_SIZE 0x40000000UL #define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE #define IOP3XX_PCI_LOWER_MEM_BA 0x80000000 -#define IOP32X_PCI_MEM_WINDOW_SIZE 0x04000000 -#define IOP3XX_PCI_MEM_WINDOW_SIZE IOP32X_PCI_MEM_WINDOW_SIZE #endif diff --git a/arch/arm/mach-iop33x/include/mach/iop33x.h b/arch/arm/mach-iop33x/include/mach/iop33x.h index 2456731..a89c0a2 100644 --- a/arch/arm/mach-iop33x/include/mach/iop33x.h +++ b/arch/arm/mach-iop33x/include/mach/iop33x.h @@ -36,8 +36,6 @@ #define IOP33X_MAX_RAM_SIZE 0x80000000UL #define IOP3XX_MAX_RAM_SIZE IOP33X_MAX_RAM_SIZE #define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE) -#define IOP33X_PCI_MEM_WINDOW_SIZE 0x08000000 -#define IOP3XX_PCI_MEM_WINDOW_SIZE IOP33X_PCI_MEM_WINDOW_SIZE #endif diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 77fa7cc..ce31f31 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -257,7 +257,8 @@ void __init iop3xx_atu_setup(void) *IOP3XX_OUMWTVR0 = 0; /* Outbound window 1 */ - *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + IOP3XX_PCI_MEM_WINDOW_SIZE; + *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + + IOP3XX_PCI_MEM_WINDOW_SIZE / 2; *IOP3XX_OUMWTVR1 = 0; /* BAR 3 ( Disabled ) */ -- cgit v0.10.2 From a692838dcaacb5f6f05fac73abb99d92dd7b1021 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Sun, 2 Aug 2009 10:46:45 +0200 Subject: arch/arm/plat-iop: Use DIV_ROUND_CLOSEST The kernel.h macro DIV_ROUND_CLOSEST performs the computation (x + d/2)/d but is perhaps more readable. The semantic patch that makes this change is as follows: (http://www.emn.fr/x-info/coccinelle/) // @haskernel@ @@ #include @depends on haskernel@ expression x,__divisor; @@ - (((x) + ((__divisor) / 2)) / (__divisor)) + DIV_ROUND_CLOSEST(x,__divisor) // Signed-off-by: Julia Lawall Signed-off-by: Dan Williams diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 3695bbe..8da95d5 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -85,7 +85,7 @@ void __init iop_init_time(unsigned long tick_rate) { u32 timer_ctl; - ticks_per_jiffy = (tick_rate + HZ/2) / HZ; + ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); ticks_per_usec = tick_rate / 1000000; next_jiffy_time = 0xffffffff; iop_tick_rate = tick_rate; -- cgit v0.10.2 From f00f510ab33f3e689e35ccdbb8dc264168aa5250 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 18 Aug 2009 15:21:50 -0700 Subject: iop: downgrade maintenance status iop support is in maintenance-only mode. Cc: Lennert Buytenhek Signed-off-by: Dan Williams diff --git a/MAINTAINERS b/MAINTAINERS index 2c4326c..e2f7199 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -631,24 +631,24 @@ ARM/INTEL IOP32X ARM ARCHITECTURE M: Lennert Buytenhek M: Dan Williams L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) -S: Supported +S: Maintained ARM/INTEL IOP33X ARM ARCHITECTURE M: Dan Williams L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) -S: Supported +S: Maintained ARM/INTEL IOP13XX ARM ARCHITECTURE M: Lennert Buytenhek M: Dan Williams L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) -S: Supported +S: Maintained ARM/INTEL IQ81342EX MACHINE SUPPORT M: Lennert Buytenhek M: Dan Williams L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) -S: Supported +S: Maintained ARM/INTEL IXP2000 ARM ARCHITECTURE M: Lennert Buytenhek @@ -669,7 +669,7 @@ ARM/INTEL XSC3 (MANZANO) ARM CORE M: Lennert Buytenhek M: Dan Williams L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) -S: Supported +S: Maintained ARM/IP FABRICS DOUBLE ESPRESSO MACHINE SUPPORT M: Lennert Buytenhek @@ -2619,7 +2619,7 @@ F: include/linux/intel-iommu.h INTEL IOP-ADMA DMA DRIVER M: Dan Williams -S: Supported +S: Maintained F: drivers/dma/iop-adma.c INTEL IXP4XX QMGR, NPE, ETHERNET and HSS SUPPORT -- cgit v0.10.2 From 453a7d46dca88704ed88b364c445ff55680a8557 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Wed, 19 Aug 2009 15:51:55 +1000 Subject: drm: remove root requirement from DRM_IOCTL_SET_VERSION (+ DRM_IOCTL_AUTH_MAGIC) Just a DRM_MASTER flag is sufficient here, though maybe this call is totally deprecated anyway (xf86-video-intel still calls it though). (airlied: drop ioctl auth_magic as discussed on mailing list also) Signed-off-by: Jesse Barnes Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index b39d7bf..a75ca63 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -63,12 +63,12 @@ static struct drm_ioctl_desc drm_ioctls[] = { DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_getmap, 0), DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, 0), DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, 0), - DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER), DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_setunique, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_IOCTL_BLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_IOCTL_UNBLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER), DRM_IOCTL_DEF(DRM_IOCTL_ADD_MAP, drm_addmap_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_IOCTL_RM_MAP, drm_rmmap_ioctl, DRM_AUTH), -- cgit v0.10.2 From 776f3360de6ed246e973577828f725681120fd7a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 19 Aug 2009 15:56:37 +1000 Subject: drm: fixup includes in encoder slave header files. Signed-off-by: Dave Airlie diff --git a/include/drm/drm_encoder_slave.h b/include/drm/drm_encoder_slave.h index 821ec40..e5e5c94 100644 --- a/include/drm/drm_encoder_slave.h +++ b/include/drm/drm_encoder_slave.h @@ -27,8 +27,8 @@ #ifndef __DRM_ENCODER_SLAVE_H__ #define __DRM_ENCODER_SLAVE_H__ -#include -#include +#include "drmP.h" +#include "drm_crtc.h" /** * struct drm_encoder_slave_funcs - Entry points exposed by a slave encoder driver -- cgit v0.10.2 From 53bd83899f5ba6b0da8f5ef976129273854a72d4 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Wed, 1 Jul 2009 10:04:40 -0700 Subject: drm: clarify scaling property names Now that we're using the scaling property in the Intel driver I noticed that the names were a bit confusing. I've corrected them according to our discussion on IRC and the mailing list, though I've left out potential new additions for a new scaling property with an integer (or two) for the scaling factor. None of the drivers implement that today, but if someone wants to do it, I think it could be done with the addition of a single new type and a new property to describe the scaling factor in the X and Y directions. Signed-off-by: Jesse Barnes Acked-by: Alex Deucher Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 362a538..39a6bc6 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -68,10 +68,10 @@ DRM_ENUM_NAME_FN(drm_get_dpms_name, drm_dpms_enum_list) */ static struct drm_prop_enum_list drm_scaling_mode_enum_list[] = { - { DRM_MODE_SCALE_NON_GPU, "Non-GPU" }, - { DRM_MODE_SCALE_FULLSCREEN, "Fullscreen" }, - { DRM_MODE_SCALE_NO_SCALE, "No scale" }, - { DRM_MODE_SCALE_ASPECT, "Aspect" }, + { DRM_MODE_SCALE_NONE, "None" }, + { DRM_MODE_SCALE_FULLSCREEN, "Full" }, + { DRM_MODE_SCALE_CENTER, "Center" }, + { DRM_MODE_SCALE_ASPECT, "Full aspect" }, }; static struct drm_prop_enum_list drm_dithering_mode_enum_list[] = diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index b59c65d..5df486f 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -38,14 +38,6 @@ #include "i915_drv.h" #include -/* - * the following four scaling options are defined. - * #define DRM_MODE_SCALE_NON_GPU 0 - * #define DRM_MODE_SCALE_FULLSCREEN 1 - * #define DRM_MODE_SCALE_NO_SCALE 2 - * #define DRM_MODE_SCALE_ASPECT 3 - */ - /* Private structure for the integrated LVDS support */ struct intel_lvds_priv { int fitting_mode; @@ -334,7 +326,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, I915_WRITE(BCLRPAT_B, 0); switch (lvds_priv->fitting_mode) { - case DRM_MODE_SCALE_NO_SCALE: + case DRM_MODE_SCALE_CENTER: /* * For centered modes, we have to calculate border widths & * heights and modify the values programmed into the CRTC. @@ -670,8 +662,8 @@ static int intel_lvds_set_property(struct drm_connector *connector, connector->encoder) { struct drm_crtc *crtc = connector->encoder->crtc; struct intel_lvds_priv *lvds_priv = intel_output->dev_priv; - if (value == DRM_MODE_SCALE_NON_GPU) { - DRM_DEBUG_KMS("non_GPU property is unsupported\n"); + if (value == DRM_MODE_SCALE_NONE) { + DRM_DEBUG_KMS("no scaling not supported\n"); return 0; } if (lvds_priv->fitting_mode == value) { diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index 616aeb4..1f90841 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h @@ -68,10 +68,11 @@ #define DRM_MODE_DPMS_OFF 3 /* Scaling mode options */ -#define DRM_MODE_SCALE_NON_GPU 0 -#define DRM_MODE_SCALE_FULLSCREEN 1 -#define DRM_MODE_SCALE_NO_SCALE 2 -#define DRM_MODE_SCALE_ASPECT 3 +#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or + software can still scale) */ +#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ +#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ +#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ /* Dithering mode options */ #define DRM_MODE_DITHERING_OFF 0 -- cgit v0.10.2 From 949ef70e2d1a5c12178875f513df34fc85d91a38 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Mon, 17 Aug 2009 19:49:19 +0300 Subject: drm/kms: no need to return void value (encoder) Cc: Francisco Jerez Signed-off-by: Pekka Paalanen Signed-off-by: Dave Airlie diff --git a/include/drm/drm_encoder_slave.h b/include/drm/drm_encoder_slave.h index e5e5c94..2f65633 100644 --- a/include/drm/drm_encoder_slave.h +++ b/include/drm/drm_encoder_slave.h @@ -154,7 +154,7 @@ static inline int drm_i2c_encoder_register(struct module *owner, */ static inline void drm_i2c_encoder_unregister(struct drm_i2c_encoder_driver *driver) { - return i2c_del_driver(&driver->i2c_driver); + i2c_del_driver(&driver->i2c_driver); } void drm_i2c_encoder_destroy(struct drm_encoder *encoder); -- cgit v0.10.2 From a0724fcf829e5afb66159ef68cb16a805ea11b42 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Mon, 17 Aug 2009 01:18:38 +0300 Subject: drm/ttm: optimize bo_kmap_type values A micro-optimization on the function ttm_kmap_obj_virtual(). By defining the values of enum ttm_bo_kmap_obj::bo_kmap_type to have a bit indicating iomem, size of the function ttm_kmap_obj_virtual() will be reduced by 16 bytes on x86_64 (gcc 4.1.2). ttm_kmap_obj_virtual() may be heavily used, when buffer objects are accessed via wrappers, that work for both kinds of memory addresses: iomem cookies and kernel virtual. Signed-off-by: Pekka Paalanen Signed-off-by: Dave Airlie diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index cd22ab4..99dc521 100644 --- a/include/drm/ttm/ttm_bo_api.h +++ b/include/drm/ttm/ttm_bo_api.h @@ -245,14 +245,15 @@ struct ttm_buffer_object { * premapped region. */ +#define TTM_BO_MAP_IOMEM_MASK 0x80 struct ttm_bo_kmap_obj { void *virtual; struct page *page; enum { - ttm_bo_map_iomap, - ttm_bo_map_vmap, - ttm_bo_map_kmap, - ttm_bo_map_premapped, + ttm_bo_map_iomap = 1 | TTM_BO_MAP_IOMEM_MASK, + ttm_bo_map_vmap = 2, + ttm_bo_map_kmap = 3, + ttm_bo_map_premapped = 4 | TTM_BO_MAP_IOMEM_MASK, } bo_kmap_type; }; @@ -522,8 +523,7 @@ extern int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type); static inline void *ttm_kmap_obj_virtual(struct ttm_bo_kmap_obj *map, bool *is_iomem) { - *is_iomem = (map->bo_kmap_type == ttm_bo_map_iomap || - map->bo_kmap_type == ttm_bo_map_premapped); + *is_iomem = !!(map->bo_kmap_type & TTM_BO_MAP_IOMEM_MASK); return map->virtual; } -- cgit v0.10.2 From 327c225bd548bf7871f116a0baa5ebdac884e452 Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Mon, 17 Aug 2009 16:28:37 +0200 Subject: drm: Enable drm drivers to add drm sysfs devices. Export utility functions for drivers to add specialized devices in the sysfs drm class subdirectory. Initially this will be needed form TTM to add a virtual device that handles power management. Signed-off-by: Thomas Hellstrom Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index adc1794..de15455 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -16,6 +16,7 @@ #include #include +#include "drm_sysfs.h" #include "drm_core.h" #include "drmP.h" @@ -515,3 +516,27 @@ void drm_sysfs_device_remove(struct drm_minor *minor) { device_unregister(&minor->kdev); } + + +/** + * drm_class_device_register - Register a struct device in the drm class. + * + * @dev: pointer to struct device to register. + * + * @dev should have all relevant members pre-filled with the exception + * of the class member. In particular, the device_type member must + * be set. + */ + +int drm_class_device_register(struct device *dev) +{ + dev->class = drm_class; + return device_register(dev); +} +EXPORT_SYMBOL_GPL(drm_class_device_register); + +void drm_class_device_unregister(struct device *dev) +{ + return device_unregister(dev); +} +EXPORT_SYMBOL_GPL(drm_class_device_unregister); diff --git a/include/drm/drm_sysfs.h b/include/drm/drm_sysfs.h new file mode 100644 index 0000000..1d8e033 --- /dev/null +++ b/include/drm/drm_sysfs.h @@ -0,0 +1,12 @@ +#ifndef _DRM_SYSFS_H_ +#define _DRM_SYSFS_H_ + +/** + * This minimalistic include file is intended for users (read TTM) that + * don't want to include the full drmP.h file. + */ + +extern int drm_class_device_register(struct device *dev); +extern void drm_class_device_unregister(struct device *dev); + +#endif -- cgit v0.10.2 From e9840be8c23601285a70520b4898818f28ce8c2b Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Tue, 18 Aug 2009 10:27:57 +0200 Subject: drm/ttm: Add a virtual ttm sysfs device. The device directory will be the base directory of the sysfs representation of other ttm subsystems. Signed-off-by: Thomas Hellstrom Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c index 59ce819..9a6edbf 100644 --- a/drivers/gpu/drm/ttm/ttm_module.c +++ b/drivers/gpu/drm/ttm/ttm_module.c @@ -29,16 +29,72 @@ * Jerome Glisse */ #include -#include +#include +#include +#include "ttm/ttm_module.h" +#include "drm_sysfs.h" + +static DECLARE_WAIT_QUEUE_HEAD(exit_q); +atomic_t device_released; + +static struct device_type ttm_drm_class_type = { + .name = "ttm", + /** + * Add pm ops here. + */ +}; + +static void ttm_drm_class_device_release(struct device *dev) +{ + atomic_set(&device_released, 1); + wake_up_all(&exit_q); +} + +static struct device ttm_drm_class_device = { + .type = &ttm_drm_class_type, + .release = &ttm_drm_class_device_release +}; + +struct kobject *ttm_get_kobj(void) +{ + struct kobject *kobj = &ttm_drm_class_device.kobj; + BUG_ON(kobj == NULL); + return kobj; +} static int __init ttm_init(void) { + int ret; + + ret = dev_set_name(&ttm_drm_class_device, "ttm"); + if (unlikely(ret != 0)) + return ret; + ttm_global_init(); + + atomic_set(&device_released, 0); + ret = drm_class_device_register(&ttm_drm_class_device); + if (unlikely(ret != 0)) + goto out_no_dev_reg; + return 0; +out_no_dev_reg: + atomic_set(&device_released, 1); + wake_up_all(&exit_q); + ttm_global_release(); + return ret; } static void __exit ttm_exit(void) { + drm_class_device_unregister(&ttm_drm_class_device); + + /** + * Refuse to unload until the TTM device is released. + * Not sure this is 100% needed. + */ + + wait_event(exit_q, atomic_read(&device_released) == 1); ttm_global_release(); } -- cgit v0.10.2 From 5fd9cbad3a4ae82c83c55b9c621d156c326724ef Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Mon, 17 Aug 2009 16:28:39 +0200 Subject: drm/ttm: Memory accounting rework. Use inclusive zones to simplify accounting and its sysfs representation. Use DMA32 accounting where applicable. Add a sysfs interface to make the heuristically determined limits readable and configurable. Signed-off-by: Thomas Hellstrom Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index c1c407f..f16909c 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -70,7 +70,7 @@ static void ttm_bo_release_list(struct kref *list_kref) if (bo->destroy) bo->destroy(bo); else { - ttm_mem_global_free(bdev->mem_glob, bo->acc_size, false); + ttm_mem_global_free(bdev->mem_glob, bo->acc_size); kfree(bo); } } @@ -1065,14 +1065,14 @@ int ttm_buffer_object_create(struct ttm_bo_device *bdev, size_t acc_size = ttm_bo_size(bdev, (size + PAGE_SIZE - 1) >> PAGE_SHIFT); - ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false, false); + ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false); if (unlikely(ret != 0)) return ret; bo = kzalloc(sizeof(*bo), GFP_KERNEL); if (unlikely(bo == NULL)) { - ttm_mem_global_free(mem_glob, acc_size, false); + ttm_mem_global_free(mem_glob, acc_size); return -ENOMEM; } diff --git a/drivers/gpu/drm/ttm/ttm_global.c b/drivers/gpu/drm/ttm/ttm_global.c index 0b14eb1..541744d 100644 --- a/drivers/gpu/drm/ttm/ttm_global.c +++ b/drivers/gpu/drm/ttm/ttm_global.c @@ -71,7 +71,7 @@ int ttm_global_item_ref(struct ttm_global_reference *ref) mutex_lock(&item->mutex); if (item->refcount == 0) { - item->object = kmalloc(ref->size, GFP_KERNEL); + item->object = kzalloc(ref->size, GFP_KERNEL); if (unlikely(item->object == NULL)) { ret = -ENOMEM; goto out_err; @@ -89,7 +89,6 @@ int ttm_global_item_ref(struct ttm_global_reference *ref) mutex_unlock(&item->mutex); return 0; out_err: - kfree(item->object); mutex_unlock(&item->mutex); item->object = NULL; return ret; @@ -105,7 +104,6 @@ void ttm_global_item_unref(struct ttm_global_reference *ref) BUG_ON(ref->object != item->object); if (--item->refcount == 0) { ref->release(ref); - kfree(item->object); item->object = NULL; } mutex_unlock(&item->mutex); diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c index 87323d4..62fb5cf 100644 --- a/drivers/gpu/drm/ttm/ttm_memory.c +++ b/drivers/gpu/drm/ttm/ttm_memory.c @@ -26,15 +26,180 @@ **************************************************************************/ #include "ttm/ttm_memory.h" +#include "ttm/ttm_module.h" #include #include #include #include #include -#define TTM_PFX "[TTM] " #define TTM_MEMORY_ALLOC_RETRIES 4 +struct ttm_mem_zone { + struct kobject kobj; + struct ttm_mem_global *glob; + const char *name; + uint64_t zone_mem; + uint64_t emer_mem; + uint64_t max_mem; + uint64_t swap_limit; + uint64_t used_mem; +}; + +static struct attribute ttm_mem_sys = { + .name = "zone_memory", + .mode = S_IRUGO +}; +static struct attribute ttm_mem_emer = { + .name = "emergency_memory", + .mode = S_IRUGO | S_IWUSR +}; +static struct attribute ttm_mem_max = { + .name = "available_memory", + .mode = S_IRUGO | S_IWUSR +}; +static struct attribute ttm_mem_swap = { + .name = "swap_limit", + .mode = S_IRUGO | S_IWUSR +}; +static struct attribute ttm_mem_used = { + .name = "used_memory", + .mode = S_IRUGO +}; + +static void ttm_mem_zone_kobj_release(struct kobject *kobj) +{ + struct ttm_mem_zone *zone = + container_of(kobj, struct ttm_mem_zone, kobj); + + printk(KERN_INFO TTM_PFX + "Zone %7s: Used memory at exit: %llu kiB.\n", + zone->name, (unsigned long long) zone->used_mem >> 10); + kfree(zone); +} + +static ssize_t ttm_mem_zone_show(struct kobject *kobj, + struct attribute *attr, + char *buffer) +{ + struct ttm_mem_zone *zone = + container_of(kobj, struct ttm_mem_zone, kobj); + uint64_t val = 0; + + spin_lock(&zone->glob->lock); + if (attr == &ttm_mem_sys) + val = zone->zone_mem; + else if (attr == &ttm_mem_emer) + val = zone->emer_mem; + else if (attr == &ttm_mem_max) + val = zone->max_mem; + else if (attr == &ttm_mem_swap) + val = zone->swap_limit; + else if (attr == &ttm_mem_used) + val = zone->used_mem; + spin_unlock(&zone->glob->lock); + + return snprintf(buffer, PAGE_SIZE, "%llu\n", + (unsigned long long) val >> 10); +} + +static void ttm_check_swapping(struct ttm_mem_global *glob); + +static ssize_t ttm_mem_zone_store(struct kobject *kobj, + struct attribute *attr, + const char *buffer, + size_t size) +{ + struct ttm_mem_zone *zone = + container_of(kobj, struct ttm_mem_zone, kobj); + int chars; + unsigned long val; + uint64_t val64; + + chars = sscanf(buffer, "%lu", &val); + if (chars == 0) + return size; + + val64 = val; + val64 <<= 10; + + spin_lock(&zone->glob->lock); + if (val64 > zone->zone_mem) + val64 = zone->zone_mem; + if (attr == &ttm_mem_emer) { + zone->emer_mem = val64; + if (zone->max_mem > val64) + zone->max_mem = val64; + } else if (attr == &ttm_mem_max) { + zone->max_mem = val64; + if (zone->emer_mem < val64) + zone->emer_mem = val64; + } else if (attr == &ttm_mem_swap) + zone->swap_limit = val64; + spin_unlock(&zone->glob->lock); + + ttm_check_swapping(zone->glob); + + return size; +} + +static struct attribute *ttm_mem_zone_attrs[] = { + &ttm_mem_sys, + &ttm_mem_emer, + &ttm_mem_max, + &ttm_mem_swap, + &ttm_mem_used, + NULL +}; + +static struct sysfs_ops ttm_mem_zone_ops = { + .show = &ttm_mem_zone_show, + .store = &ttm_mem_zone_store +}; + +static struct kobj_type ttm_mem_zone_kobj_type = { + .release = &ttm_mem_zone_kobj_release, + .sysfs_ops = &ttm_mem_zone_ops, + .default_attrs = ttm_mem_zone_attrs, +}; + +static void ttm_mem_global_kobj_release(struct kobject *kobj) +{ + struct ttm_mem_global *glob = + container_of(kobj, struct ttm_mem_global, kobj); + + kfree(glob); +} + +static struct kobj_type ttm_mem_glob_kobj_type = { + .release = &ttm_mem_global_kobj_release, +}; + +static bool ttm_zones_above_swap_target(struct ttm_mem_global *glob, + bool from_wq, uint64_t extra) +{ + unsigned int i; + struct ttm_mem_zone *zone; + uint64_t target; + + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + + if (from_wq) + target = zone->swap_limit; + else if (capable(CAP_SYS_ADMIN)) + target = zone->emer_mem; + else + target = zone->max_mem; + + target = (extra > target) ? 0ULL : target; + + if (zone->used_mem > target) + return true; + } + return false; +} + /** * At this point we only support a single shrink callback. * Extend this if needed, perhaps using a linked list of callbacks. @@ -42,34 +207,17 @@ * many threads may try to swap out at any given time. */ -static void ttm_shrink(struct ttm_mem_global *glob, bool from_workqueue, +static void ttm_shrink(struct ttm_mem_global *glob, bool from_wq, uint64_t extra) { int ret; struct ttm_mem_shrink *shrink; - uint64_t target; - uint64_t total_target; spin_lock(&glob->lock); if (glob->shrink == NULL) goto out; - if (from_workqueue) { - target = glob->swap_limit; - total_target = glob->total_memory_swap_limit; - } else if (capable(CAP_SYS_ADMIN)) { - total_target = glob->emer_total_memory; - target = glob->emer_memory; - } else { - total_target = glob->max_total_memory; - target = glob->max_memory; - } - - total_target = (extra >= total_target) ? 0 : total_target - extra; - target = (extra >= target) ? 0 : target - extra; - - while (glob->used_memory > target || - glob->used_total_memory > total_target) { + while (ttm_zones_above_swap_target(glob, from_wq, extra)) { shrink = glob->shrink; spin_unlock(&glob->lock); ret = shrink->do_shrink(shrink); @@ -81,6 +229,8 @@ out: spin_unlock(&glob->lock); } + + static void ttm_shrink_work(struct work_struct *work) { struct ttm_mem_global *glob = @@ -89,63 +239,178 @@ static void ttm_shrink_work(struct work_struct *work) ttm_shrink(glob, true, 0ULL); } +static int ttm_mem_init_kernel_zone(struct ttm_mem_global *glob, + const struct sysinfo *si) +{ + struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL); + uint64_t mem; + + if (unlikely(!zone)) + return -ENOMEM; + + mem = si->totalram - si->totalhigh; + mem *= si->mem_unit; + + zone->name = "kernel"; + zone->zone_mem = mem; + zone->max_mem = mem >> 1; + zone->emer_mem = (mem >> 1) + (mem >> 2); + zone->swap_limit = zone->max_mem - (mem >> 3); + zone->used_mem = 0; + zone->glob = glob; + glob->zone_kernel = zone; + glob->zones[glob->num_zones++] = zone; + kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type); + return kobject_add(&zone->kobj, &glob->kobj, zone->name); +} + +#ifdef CONFIG_HIGHMEM +static int ttm_mem_init_highmem_zone(struct ttm_mem_global *glob, + const struct sysinfo *si) +{ + struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL); + uint64_t mem; + + if (unlikely(!zone)) + return -ENOMEM; + + if (si->totalhigh == 0) + return 0; + + mem = si->totalram; + mem *= si->mem_unit; + + zone->name = "highmem"; + zone->zone_mem = mem; + zone->max_mem = mem >> 1; + zone->emer_mem = (mem >> 1) + (mem >> 2); + zone->swap_limit = zone->max_mem - (mem >> 3); + zone->used_mem = 0; + zone->glob = glob; + glob->zone_highmem = zone; + glob->zones[glob->num_zones++] = zone; + kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type); + return kobject_add(&zone->kobj, &glob->kobj, zone->name); +} +#else +static int ttm_mem_init_dma32_zone(struct ttm_mem_global *glob, + const struct sysinfo *si) +{ + struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL); + uint64_t mem; + + if (unlikely(!zone)) + return -ENOMEM; + + mem = si->totalram; + mem *= si->mem_unit; + + /** + * No special dma32 zone needed. + */ + + if (mem <= ((uint64_t) 1ULL << 32)) + return 0; + + /* + * Limit max dma32 memory to 4GB for now + * until we can figure out how big this + * zone really is. + */ + + mem = ((uint64_t) 1ULL << 32); + zone->name = "dma32"; + zone->zone_mem = mem; + zone->max_mem = mem >> 1; + zone->emer_mem = (mem >> 1) + (mem >> 2); + zone->swap_limit = zone->max_mem - (mem >> 3); + zone->used_mem = 0; + zone->glob = glob; + glob->zone_dma32 = zone; + glob->zones[glob->num_zones++] = zone; + kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type); + return kobject_add(&zone->kobj, &glob->kobj, zone->name); +} +#endif + int ttm_mem_global_init(struct ttm_mem_global *glob) { struct sysinfo si; - uint64_t mem; + int ret; + int i; + struct ttm_mem_zone *zone; spin_lock_init(&glob->lock); glob->swap_queue = create_singlethread_workqueue("ttm_swap"); INIT_WORK(&glob->work, ttm_shrink_work); init_waitqueue_head(&glob->queue); + kobject_init(&glob->kobj, &ttm_mem_glob_kobj_type); + ret = kobject_add(&glob->kobj, + ttm_get_kobj(), + "memory_accounting"); + if (unlikely(ret != 0)) + goto out_no_zone; si_meminfo(&si); - mem = si.totalram - si.totalhigh; - mem *= si.mem_unit; - - glob->max_memory = mem >> 1; - glob->emer_memory = (mem >> 1) + (mem >> 2); - glob->swap_limit = glob->max_memory - (mem >> 3); - glob->used_memory = 0; - glob->used_total_memory = 0; - glob->shrink = NULL; - - mem = si.totalram; - mem *= si.mem_unit; - - glob->max_total_memory = mem >> 1; - glob->emer_total_memory = (mem >> 1) + (mem >> 2); - - glob->total_memory_swap_limit = glob->max_total_memory - (mem >> 3); - - printk(KERN_INFO TTM_PFX "TTM available graphics memory: %llu MiB\n", - glob->max_total_memory >> 20); - printk(KERN_INFO TTM_PFX "TTM available object memory: %llu MiB\n", - glob->max_memory >> 20); - + ret = ttm_mem_init_kernel_zone(glob, &si); + if (unlikely(ret != 0)) + goto out_no_zone; +#ifdef CONFIG_HIGHMEM + ret = ttm_mem_init_highmem_zone(glob, &si); + if (unlikely(ret != 0)) + goto out_no_zone; +#else + ret = ttm_mem_init_dma32_zone(glob, &si); + if (unlikely(ret != 0)) + goto out_no_zone; +#endif + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + printk(KERN_INFO TTM_PFX + "Zone %7s: Available graphics memory: %llu kiB.\n", + zone->name, (unsigned long long) zone->max_mem >> 10); + } return 0; +out_no_zone: + ttm_mem_global_release(glob); + return ret; } EXPORT_SYMBOL(ttm_mem_global_init); void ttm_mem_global_release(struct ttm_mem_global *glob) { - printk(KERN_INFO TTM_PFX "Used total memory is %llu bytes.\n", - (unsigned long long)glob->used_total_memory); + unsigned int i; + struct ttm_mem_zone *zone; + flush_workqueue(glob->swap_queue); destroy_workqueue(glob->swap_queue); glob->swap_queue = NULL; + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + kobject_del(&zone->kobj); + kobject_put(&zone->kobj); + } + kobject_del(&glob->kobj); + kobject_put(&glob->kobj); } EXPORT_SYMBOL(ttm_mem_global_release); -static inline void ttm_check_swapping(struct ttm_mem_global *glob) +static void ttm_check_swapping(struct ttm_mem_global *glob) { - bool needs_swapping; + bool needs_swapping = false; + unsigned int i; + struct ttm_mem_zone *zone; spin_lock(&glob->lock); - needs_swapping = (glob->used_memory > glob->swap_limit || - glob->used_total_memory > - glob->total_memory_swap_limit); + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + if (zone->used_mem > zone->swap_limit) { + needs_swapping = true; + break; + } + } + spin_unlock(&glob->lock); if (unlikely(needs_swapping)) @@ -153,44 +418,60 @@ static inline void ttm_check_swapping(struct ttm_mem_global *glob) } -void ttm_mem_global_free(struct ttm_mem_global *glob, - uint64_t amount, bool himem) +static void ttm_mem_global_free_zone(struct ttm_mem_global *glob, + struct ttm_mem_zone *single_zone, + uint64_t amount) { + unsigned int i; + struct ttm_mem_zone *zone; + spin_lock(&glob->lock); - glob->used_total_memory -= amount; - if (!himem) - glob->used_memory -= amount; - wake_up_all(&glob->queue); + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + if (single_zone && zone != single_zone) + continue; + zone->used_mem -= amount; + } spin_unlock(&glob->lock); } +void ttm_mem_global_free(struct ttm_mem_global *glob, + uint64_t amount) +{ + return ttm_mem_global_free_zone(glob, NULL, amount); +} + static int ttm_mem_global_reserve(struct ttm_mem_global *glob, - uint64_t amount, bool himem, bool reserve) + struct ttm_mem_zone *single_zone, + uint64_t amount, bool reserve) { uint64_t limit; - uint64_t lomem_limit; int ret = -ENOMEM; + unsigned int i; + struct ttm_mem_zone *zone; spin_lock(&glob->lock); + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + if (single_zone && zone != single_zone) + continue; - if (capable(CAP_SYS_ADMIN)) { - limit = glob->emer_total_memory; - lomem_limit = glob->emer_memory; - } else { - limit = glob->max_total_memory; - lomem_limit = glob->max_memory; - } + limit = (capable(CAP_SYS_ADMIN)) ? + zone->emer_mem : zone->max_mem; - if (unlikely(glob->used_total_memory + amount > limit)) - goto out_unlock; - if (unlikely(!himem && glob->used_memory + amount > lomem_limit)) - goto out_unlock; + if (zone->used_mem > limit) + goto out_unlock; + } if (reserve) { - glob->used_total_memory += amount; - if (!himem) - glob->used_memory += amount; + for (i = 0; i < glob->num_zones; ++i) { + zone = glob->zones[i]; + if (single_zone && zone != single_zone) + continue; + zone->used_mem += amount; + } } + ret = 0; out_unlock: spin_unlock(&glob->lock); @@ -199,12 +480,17 @@ out_unlock: return ret; } -int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, - bool no_wait, bool interruptible, bool himem) + +static int ttm_mem_global_alloc_zone(struct ttm_mem_global *glob, + struct ttm_mem_zone *single_zone, + uint64_t memory, + bool no_wait, bool interruptible) { int count = TTM_MEMORY_ALLOC_RETRIES; - while (unlikely(ttm_mem_global_reserve(glob, memory, himem, true) + while (unlikely(ttm_mem_global_reserve(glob, + single_zone, + memory, true) != 0)) { if (no_wait) return -ENOMEM; @@ -216,6 +502,56 @@ int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, return 0; } +int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, + bool no_wait, bool interruptible) +{ + /** + * Normal allocations of kernel memory are registered in + * all zones. + */ + + return ttm_mem_global_alloc_zone(glob, NULL, memory, no_wait, + interruptible); +} + +int ttm_mem_global_alloc_page(struct ttm_mem_global *glob, + struct page *page, + bool no_wait, bool interruptible) +{ + + struct ttm_mem_zone *zone = NULL; + + /** + * Page allocations may be registed in a single zone + * only if highmem or !dma32. + */ + +#ifdef CONFIG_HIGHMEM + if (PageHighMem(page) && glob->zone_highmem != NULL) + zone = glob->zone_highmem; +#else + if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL) + zone = glob->zone_kernel; +#endif + return ttm_mem_global_alloc_zone(glob, zone, PAGE_SIZE, no_wait, + interruptible); +} + +void ttm_mem_global_free_page(struct ttm_mem_global *glob, struct page *page) +{ + struct ttm_mem_zone *zone = NULL; + +#ifdef CONFIG_HIGHMEM + if (PageHighMem(page) && glob->zone_highmem != NULL) + zone = glob->zone_highmem; +#else + if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL) + zone = glob->zone_kernel; +#endif + ttm_mem_global_free_zone(glob, zone, PAGE_SIZE); +} + + size_t ttm_round_pot(size_t size) { if ((size & (size - 1)) == 0) diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 75dc8bd..4e1e256 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -166,7 +166,7 @@ static void ttm_tt_free_user_pages(struct ttm_tt *ttm) set_page_dirty_lock(page); ttm->pages[i] = NULL; - ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE, false); + ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE); put_page(page); } ttm->state = tt_unpopulated; @@ -187,21 +187,14 @@ static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index) if (!p) return NULL; - if (PageHighMem(p)) { - ret = - ttm_mem_global_alloc(mem_glob, PAGE_SIZE, - false, false, true); - if (unlikely(ret != 0)) - goto out_err; + ret = ttm_mem_global_alloc_page(mem_glob, p, false, false); + if (unlikely(ret != 0)) + goto out_err; + + if (PageHighMem(p)) ttm->pages[--ttm->first_himem_page] = p; - } else { - ret = - ttm_mem_global_alloc(mem_glob, PAGE_SIZE, - false, false, false); - if (unlikely(ret != 0)) - goto out_err; + else ttm->pages[++ttm->last_lomem_page] = p; - } } return p; out_err: @@ -355,8 +348,8 @@ static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm) printk(KERN_ERR TTM_PFX "Erroneous page count. " "Leaking pages.\n"); - ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE, - PageHighMem(cur_page)); + ttm_mem_global_free_page(ttm->bdev->mem_glob, + cur_page); __free_page(cur_page); } } @@ -411,7 +404,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm, */ ret = ttm_mem_global_alloc(mem_glob, num_pages * PAGE_SIZE, - false, false, false); + false, false); if (unlikely(ret != 0)) return ret; @@ -422,7 +415,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm, if (ret != num_pages && write) { ttm_tt_free_user_pages(ttm); - ttm_mem_global_free(mem_glob, num_pages * PAGE_SIZE, false); + ttm_mem_global_free(mem_glob, num_pages * PAGE_SIZE); return -ENOMEM; } diff --git a/include/drm/ttm/ttm_memory.h b/include/drm/ttm/ttm_memory.h index d8b8f04..6983a7c 100644 --- a/include/drm/ttm/ttm_memory.h +++ b/include/drm/ttm/ttm_memory.h @@ -32,6 +32,7 @@ #include #include #include +#include /** * struct ttm_mem_shrink - callback to shrink TTM memory usage. @@ -60,34 +61,33 @@ struct ttm_mem_shrink { * @queue: Wait queue for processes suspended waiting for memory. * @lock: Lock to protect the @shrink - and the memory accounting members, * that is, essentially the whole structure with some exceptions. - * @emer_memory: Lowmem memory limit available for root. - * @max_memory: Lowmem memory limit available for non-root. - * @swap_limit: Lowmem memory limit where the shrink workqueue kicks in. - * @used_memory: Currently used lowmem memory. - * @used_total_memory: Currently used total (lowmem + highmem) memory. - * @total_memory_swap_limit: Total memory limit where the shrink workqueue - * kicks in. - * @max_total_memory: Total memory available to non-root processes. - * @emer_total_memory: Total memory available to root processes. + * @zones: Array of pointers to accounting zones. + * @num_zones: Number of populated entries in the @zones array. + * @zone_kernel: Pointer to the kernel zone. + * @zone_highmem: Pointer to the highmem zone if there is one. + * @zone_dma32: Pointer to the dma32 zone if there is one. * * Note that this structure is not per device. It should be global for all * graphics devices. */ +#define TTM_MEM_MAX_ZONES 2 +struct ttm_mem_zone; struct ttm_mem_global { + struct kobject kobj; struct ttm_mem_shrink *shrink; struct workqueue_struct *swap_queue; struct work_struct work; wait_queue_head_t queue; spinlock_t lock; - uint64_t emer_memory; - uint64_t max_memory; - uint64_t swap_limit; - uint64_t used_memory; - uint64_t used_total_memory; - uint64_t total_memory_swap_limit; - uint64_t max_total_memory; - uint64_t emer_total_memory; + struct ttm_mem_zone *zones[TTM_MEM_MAX_ZONES]; + unsigned int num_zones; + struct ttm_mem_zone *zone_kernel; +#ifdef CONFIG_HIGHMEM + struct ttm_mem_zone *zone_highmem; +#else + struct ttm_mem_zone *zone_dma32; +#endif }; /** @@ -146,8 +146,13 @@ static inline void ttm_mem_unregister_shrink(struct ttm_mem_global *glob, extern int ttm_mem_global_init(struct ttm_mem_global *glob); extern void ttm_mem_global_release(struct ttm_mem_global *glob); extern int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory, - bool no_wait, bool interruptible, bool himem); + bool no_wait, bool interruptible); extern void ttm_mem_global_free(struct ttm_mem_global *glob, - uint64_t amount, bool himem); + uint64_t amount); +extern int ttm_mem_global_alloc_page(struct ttm_mem_global *glob, + struct page *page, + bool no_wait, bool interruptible); +extern void ttm_mem_global_free_page(struct ttm_mem_global *glob, + struct page *page); extern size_t ttm_round_pot(size_t size); #endif diff --git a/include/drm/ttm/ttm_module.h b/include/drm/ttm/ttm_module.h index 889a4c79..0a72ac7 100644 --- a/include/drm/ttm/ttm_module.h +++ b/include/drm/ttm/ttm_module.h @@ -32,6 +32,7 @@ #define _TTM_MODULE_H_ #include +struct kobject; #define TTM_PFX "[TTM]" @@ -54,5 +55,6 @@ extern void ttm_global_init(void); extern void ttm_global_release(void); extern int ttm_global_item_ref(struct ttm_global_reference *ref); extern void ttm_global_item_unref(struct ttm_global_reference *ref); +extern struct kobject *ttm_get_kobj(void); #endif /* _TTM_MODULE_H_ */ -- cgit v0.10.2 From a987fcaa805fcb24ba885c2e29fd4fdb6816f08f Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Tue, 18 Aug 2009 16:51:56 +0200 Subject: ttm: Make parts of a struct ttm_bo_device global. Common resources, like memory accounting and swap lists should be global and not per device. Introduce a struct ttm_bo_global to accomodate this, and register it with sysfs. Add a small sysfs interface to return the number of active buffer objects. Signed-off-by: Thomas Hellstrom Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h index 473e477..10e8af6 100644 --- a/drivers/gpu/drm/radeon/radeon_object.h +++ b/drivers/gpu/drm/radeon/radeon_object.h @@ -37,6 +37,7 @@ * TTM. */ struct radeon_mman { + struct ttm_bo_global_ref bo_global_ref; struct ttm_global_reference mem_global_ref; bool mem_global_referenced; struct ttm_bo_device bdev; diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 1227a97..343b6d6 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -77,9 +77,25 @@ static int radeon_ttm_global_init(struct radeon_device *rdev) global_ref->release = &radeon_ttm_mem_global_release; r = ttm_global_item_ref(global_ref); if (r != 0) { - DRM_ERROR("Failed referencing a global TTM memory object.\n"); + DRM_ERROR("Failed setting up TTM memory accounting " + "subsystem.\n"); return r; } + + rdev->mman.bo_global_ref.mem_glob = + rdev->mman.mem_global_ref.object; + global_ref = &rdev->mman.bo_global_ref.ref; + global_ref->global_type = TTM_GLOBAL_TTM_BO; + global_ref->size = sizeof(struct ttm_mem_global); + global_ref->init = &ttm_bo_global_init; + global_ref->release = &ttm_bo_global_release; + r = ttm_global_item_ref(global_ref); + if (r != 0) { + DRM_ERROR("Failed setting up TTM BO subsystem.\n"); + ttm_global_item_unref(&rdev->mman.mem_global_ref); + return r; + } + rdev->mman.mem_global_referenced = true; return 0; } @@ -87,6 +103,7 @@ static int radeon_ttm_global_init(struct radeon_device *rdev) static void radeon_ttm_global_fini(struct radeon_device *rdev) { if (rdev->mman.mem_global_referenced) { + ttm_global_item_unref(&rdev->mman.bo_global_ref.ref); ttm_global_item_unref(&rdev->mman.mem_global_ref); rdev->mman.mem_global_referenced = false; } @@ -286,9 +303,11 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo, r = ttm_bo_move_ttm(bo, true, no_wait, new_mem); out_cleanup: if (tmp_mem.mm_node) { - spin_lock(&rdev->mman.bdev.lru_lock); + struct ttm_bo_global *glob = rdev->mman.bdev.glob; + + spin_lock(&glob->lru_lock); drm_mm_put_block(tmp_mem.mm_node); - spin_unlock(&rdev->mman.bdev.lru_lock); + spin_unlock(&glob->lru_lock); return r; } return r; @@ -323,9 +342,11 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo, } out_cleanup: if (tmp_mem.mm_node) { - spin_lock(&rdev->mman.bdev.lru_lock); + struct ttm_bo_global *glob = rdev->mman.bdev.glob; + + spin_lock(&glob->lru_lock); drm_mm_put_block(tmp_mem.mm_node); - spin_unlock(&rdev->mman.bdev.lru_lock); + spin_unlock(&glob->lru_lock); return r; } return r; @@ -441,7 +462,7 @@ int radeon_ttm_init(struct radeon_device *rdev) } /* No others user of address space so set it to 0 */ r = ttm_bo_device_init(&rdev->mman.bdev, - rdev->mman.mem_global_ref.object, + rdev->mman.bo_global_ref.ref.object, &radeon_bo_driver, DRM_FILE_PAGE_OFFSET); if (r) { DRM_ERROR("failed initializing buffer object driver(%d).\n", r); diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index f16909c..0d0b1b7 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -45,6 +45,39 @@ static int ttm_bo_setup_vm(struct ttm_buffer_object *bo); static void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo); static int ttm_bo_swapout(struct ttm_mem_shrink *shrink); +static void ttm_bo_global_kobj_release(struct kobject *kobj); + +static struct attribute ttm_bo_count = { + .name = "bo_count", + .mode = S_IRUGO +}; + +static ssize_t ttm_bo_global_show(struct kobject *kobj, + struct attribute *attr, + char *buffer) +{ + struct ttm_bo_global *glob = + container_of(kobj, struct ttm_bo_global, kobj); + + return snprintf(buffer, PAGE_SIZE, "%lu\n", + (unsigned long) atomic_read(&glob->bo_count)); +} + +static struct attribute *ttm_bo_global_attrs[] = { + &ttm_bo_count, + NULL +}; + +static struct sysfs_ops ttm_bo_global_ops = { + .show = &ttm_bo_global_show +}; + +static struct kobj_type ttm_bo_glob_kobj_type = { + .release = &ttm_bo_global_kobj_release, + .sysfs_ops = &ttm_bo_global_ops, + .default_attrs = ttm_bo_global_attrs +}; + static inline uint32_t ttm_bo_type_flags(unsigned type) { @@ -67,10 +100,11 @@ static void ttm_bo_release_list(struct kref *list_kref) if (bo->ttm) ttm_tt_destroy(bo->ttm); + atomic_dec(&bo->glob->bo_count); if (bo->destroy) bo->destroy(bo); else { - ttm_mem_global_free(bdev->mem_glob, bo->acc_size); + ttm_mem_global_free(bdev->glob->mem_glob, bo->acc_size); kfree(bo); } } @@ -107,7 +141,7 @@ static void ttm_bo_add_to_lru(struct ttm_buffer_object *bo) kref_get(&bo->list_kref); if (bo->ttm != NULL) { - list_add_tail(&bo->swap, &bdev->swap_lru); + list_add_tail(&bo->swap, &bo->glob->swap_lru); kref_get(&bo->list_kref); } } @@ -142,7 +176,7 @@ int ttm_bo_reserve_locked(struct ttm_buffer_object *bo, bool interruptible, bool no_wait, bool use_sequence, uint32_t sequence) { - struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; int ret; while (unlikely(atomic_cmpxchg(&bo->reserved, 0, 1) != 0)) { @@ -154,9 +188,9 @@ int ttm_bo_reserve_locked(struct ttm_buffer_object *bo, if (no_wait) return -EBUSY; - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); ret = ttm_bo_wait_unreserved(bo, interruptible); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); if (unlikely(ret)) return ret; @@ -182,16 +216,16 @@ int ttm_bo_reserve(struct ttm_buffer_object *bo, bool interruptible, bool no_wait, bool use_sequence, uint32_t sequence) { - struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; int put_count = 0; int ret; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); ret = ttm_bo_reserve_locked(bo, interruptible, no_wait, use_sequence, sequence); if (likely(ret == 0)) put_count = ttm_bo_del_from_lru(bo); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); while (put_count--) kref_put(&bo->list_kref, ttm_bo_ref_bug); @@ -201,13 +235,13 @@ int ttm_bo_reserve(struct ttm_buffer_object *bo, void ttm_bo_unreserve(struct ttm_buffer_object *bo) { - struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); ttm_bo_add_to_lru(bo); atomic_set(&bo->reserved, 0); wake_up_all(&bo->event_queue); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); } EXPORT_SYMBOL(ttm_bo_unreserve); @@ -218,6 +252,7 @@ EXPORT_SYMBOL(ttm_bo_unreserve); static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc) { struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; int ret = 0; uint32_t page_flags = 0; @@ -230,14 +265,14 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc) page_flags |= TTM_PAGE_FLAG_ZERO_ALLOC; case ttm_bo_type_kernel: bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT, - page_flags, bdev->dummy_read_page); + page_flags, glob->dummy_read_page); if (unlikely(bo->ttm == NULL)) ret = -ENOMEM; break; case ttm_bo_type_user: bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT, page_flags | TTM_PAGE_FLAG_USER, - bdev->dummy_read_page); + glob->dummy_read_page); if (unlikely(bo->ttm == NULL)) ret = -ENOMEM; break; @@ -355,6 +390,7 @@ out_err: static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) { struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; struct ttm_bo_driver *driver = bdev->driver; int ret; @@ -366,7 +402,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) spin_unlock(&bo->lock); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); ret = ttm_bo_reserve_locked(bo, false, false, false, 0); BUG_ON(ret); if (bo->ttm) @@ -381,7 +417,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) bo->mem.mm_node = NULL; } put_count = ttm_bo_del_from_lru(bo); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); atomic_set(&bo->reserved, 0); @@ -391,14 +427,14 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) return 0; } - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); if (list_empty(&bo->ddestroy)) { void *sync_obj = bo->sync_obj; void *sync_obj_arg = bo->sync_obj_arg; kref_get(&bo->list_kref); list_add_tail(&bo->ddestroy, &bdev->ddestroy); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); spin_unlock(&bo->lock); if (sync_obj) @@ -408,7 +444,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) ret = 0; } else { - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); spin_unlock(&bo->lock); ret = -EBUSY; } @@ -423,11 +459,12 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all) static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) { + struct ttm_bo_global *glob = bdev->glob; struct ttm_buffer_object *entry, *nentry; struct list_head *list, *next; int ret; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); list_for_each_safe(list, next, &bdev->ddestroy) { entry = list_entry(list, struct ttm_buffer_object, ddestroy); nentry = NULL; @@ -444,16 +481,16 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) } kref_get(&entry->list_kref); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); ret = ttm_bo_cleanup_refs(entry, remove_all); kref_put(&entry->list_kref, ttm_bo_release_list); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); if (nentry) { bool next_onlist = !list_empty(next); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); kref_put(&nentry->list_kref, ttm_bo_release_list); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); /* * Someone might have raced us and removed the * next entry from the list. We don't bother restarting @@ -467,7 +504,7 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) break; } ret = !list_empty(&bdev->ddestroy); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); return ret; } @@ -517,6 +554,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, unsigned mem_type, { int ret = 0; struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; struct ttm_mem_reg evict_mem; uint32_t proposed_placement; @@ -565,12 +603,12 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, unsigned mem_type, goto out; } - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); if (evict_mem.mm_node) { drm_mm_put_block(evict_mem.mm_node); evict_mem.mm_node = NULL; } - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); bo->evicted = true; out: return ret; @@ -585,6 +623,7 @@ static int ttm_bo_mem_force_space(struct ttm_bo_device *bdev, uint32_t mem_type, bool interruptible, bool no_wait) { + struct ttm_bo_global *glob = bdev->glob; struct drm_mm_node *node; struct ttm_buffer_object *entry; struct ttm_mem_type_manager *man = &bdev->man[mem_type]; @@ -598,7 +637,7 @@ retry_pre_get: if (unlikely(ret != 0)) return ret; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); do { node = drm_mm_search_free(&man->manager, num_pages, mem->page_alignment, 1); @@ -619,7 +658,7 @@ retry_pre_get: if (likely(ret == 0)) put_count = ttm_bo_del_from_lru(entry); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); if (unlikely(ret != 0)) return ret; @@ -635,21 +674,21 @@ retry_pre_get: if (ret) return ret; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); } while (1); if (!node) { - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); return -ENOMEM; } node = drm_mm_get_block_atomic(node, num_pages, mem->page_alignment); if (unlikely(!node)) { - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); goto retry_pre_get; } - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); mem->mm_node = node; mem->mem_type = mem_type; return 0; @@ -697,6 +736,7 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, bool interruptible, bool no_wait) { struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; struct ttm_mem_type_manager *man; uint32_t num_prios = bdev->driver->num_mem_type_prio; @@ -733,20 +773,20 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, if (unlikely(ret)) return ret; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); node = drm_mm_search_free(&man->manager, mem->num_pages, mem->page_alignment, 1); if (unlikely(!node)) { - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); break; } node = drm_mm_get_block_atomic(node, mem->num_pages, mem-> page_alignment); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); } while (!node); } if (node) @@ -816,7 +856,7 @@ int ttm_bo_move_buffer(struct ttm_buffer_object *bo, uint32_t proposed_placement, bool interruptible, bool no_wait) { - struct ttm_bo_device *bdev = bo->bdev; + struct ttm_bo_global *glob = bo->glob; int ret = 0; struct ttm_mem_reg mem; @@ -852,9 +892,9 @@ int ttm_bo_move_buffer(struct ttm_buffer_object *bo, out_unlock: if (ret && mem.mm_node) { - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); drm_mm_put_block(mem.mm_node); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); } return ret; } @@ -990,6 +1030,7 @@ int ttm_buffer_object_init(struct ttm_bo_device *bdev, INIT_LIST_HEAD(&bo->ddestroy); INIT_LIST_HEAD(&bo->swap); bo->bdev = bdev; + bo->glob = bdev->glob; bo->type = type; bo->num_pages = num_pages; bo->mem.mem_type = TTM_PL_SYSTEM; @@ -1002,6 +1043,7 @@ int ttm_buffer_object_init(struct ttm_bo_device *bdev, bo->seq_valid = false; bo->persistant_swap_storage = persistant_swap_storage; bo->acc_size = acc_size; + atomic_inc(&bo->glob->bo_count); ret = ttm_bo_check_placement(bo, flags, 0ULL); if (unlikely(ret != 0)) @@ -1040,13 +1082,13 @@ out_err: } EXPORT_SYMBOL(ttm_buffer_object_init); -static inline size_t ttm_bo_size(struct ttm_bo_device *bdev, +static inline size_t ttm_bo_size(struct ttm_bo_global *glob, unsigned long num_pages) { size_t page_array_size = (num_pages * sizeof(void *) + PAGE_SIZE - 1) & PAGE_MASK; - return bdev->ttm_bo_size + 2 * page_array_size; + return glob->ttm_bo_size + 2 * page_array_size; } int ttm_buffer_object_create(struct ttm_bo_device *bdev, @@ -1061,10 +1103,10 @@ int ttm_buffer_object_create(struct ttm_bo_device *bdev, { struct ttm_buffer_object *bo; int ret; - struct ttm_mem_global *mem_glob = bdev->mem_glob; + struct ttm_mem_global *mem_glob = bdev->glob->mem_glob; size_t acc_size = - ttm_bo_size(bdev, (size + PAGE_SIZE - 1) >> PAGE_SHIFT); + ttm_bo_size(bdev->glob, (size + PAGE_SIZE - 1) >> PAGE_SHIFT); ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false); if (unlikely(ret != 0)) return ret; @@ -1118,6 +1160,7 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, struct list_head *head, unsigned mem_type, bool allow_errors) { + struct ttm_bo_global *glob = bdev->glob; struct ttm_buffer_object *entry; int ret; int put_count; @@ -1126,30 +1169,31 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, * Can't use standard list traversal since we're unlocking. */ - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); while (!list_empty(head)) { entry = list_first_entry(head, struct ttm_buffer_object, lru); kref_get(&entry->list_kref); ret = ttm_bo_reserve_locked(entry, false, false, false, 0); put_count = ttm_bo_del_from_lru(entry); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); while (put_count--) kref_put(&entry->list_kref, ttm_bo_ref_bug); BUG_ON(ret); ret = ttm_bo_leave_list(entry, mem_type, allow_errors); ttm_bo_unreserve(entry); kref_put(&entry->list_kref, ttm_bo_release_list); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); } - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); return 0; } int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type) { + struct ttm_bo_global *glob = bdev->glob; struct ttm_mem_type_manager *man = &bdev->man[mem_type]; int ret = -EINVAL; @@ -1171,13 +1215,13 @@ int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type) if (mem_type > 0) { ttm_bo_force_list_clean(bdev, &man->lru, mem_type, false); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); if (drm_mm_clean(&man->manager)) drm_mm_takedown(&man->manager); else ret = -EBUSY; - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); } return ret; @@ -1251,11 +1295,83 @@ int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type, } EXPORT_SYMBOL(ttm_bo_init_mm); +static void ttm_bo_global_kobj_release(struct kobject *kobj) +{ + struct ttm_bo_global *glob = + container_of(kobj, struct ttm_bo_global, kobj); + + printk(KERN_INFO TTM_PFX "Freeing bo global.\n"); + ttm_mem_unregister_shrink(glob->mem_glob, &glob->shrink); + __free_page(glob->dummy_read_page); + kfree(glob); +} + +void ttm_bo_global_release(struct ttm_global_reference *ref) +{ + struct ttm_bo_global *glob = ref->object; + + kobject_del(&glob->kobj); + kobject_put(&glob->kobj); +} +EXPORT_SYMBOL(ttm_bo_global_release); + +int ttm_bo_global_init(struct ttm_global_reference *ref) +{ + struct ttm_bo_global_ref *bo_ref = + container_of(ref, struct ttm_bo_global_ref, ref); + struct ttm_bo_global *glob = ref->object; + int ret; + + mutex_init(&glob->device_list_mutex); + spin_lock_init(&glob->lru_lock); + glob->mem_glob = bo_ref->mem_glob; + glob->dummy_read_page = alloc_page(__GFP_ZERO | GFP_DMA32); + + if (unlikely(glob->dummy_read_page == NULL)) { + ret = -ENOMEM; + goto out_no_drp; + } + + INIT_LIST_HEAD(&glob->swap_lru); + INIT_LIST_HEAD(&glob->device_list); + + ttm_mem_init_shrink(&glob->shrink, ttm_bo_swapout); + ret = ttm_mem_register_shrink(glob->mem_glob, &glob->shrink); + if (unlikely(ret != 0)) { + printk(KERN_ERR TTM_PFX + "Could not register buffer object swapout.\n"); + goto out_no_shrink; + } + + glob->ttm_bo_extra_size = + ttm_round_pot(sizeof(struct ttm_tt)) + + ttm_round_pot(sizeof(struct ttm_backend)); + + glob->ttm_bo_size = glob->ttm_bo_extra_size + + ttm_round_pot(sizeof(struct ttm_buffer_object)); + + atomic_set(&glob->bo_count, 0); + + kobject_init(&glob->kobj, &ttm_bo_glob_kobj_type); + ret = kobject_add(&glob->kobj, ttm_get_kobj(), "buffer_objects"); + if (unlikely(ret != 0)) + kobject_put(&glob->kobj); + return ret; +out_no_shrink: + __free_page(glob->dummy_read_page); +out_no_drp: + kfree(glob); + return ret; +} +EXPORT_SYMBOL(ttm_bo_global_init); + + int ttm_bo_device_release(struct ttm_bo_device *bdev) { int ret = 0; unsigned i = TTM_NUM_MEM_TYPES; struct ttm_mem_type_manager *man; + struct ttm_bo_global *glob = bdev->glob; while (i--) { man = &bdev->man[i]; @@ -1271,98 +1387,74 @@ int ttm_bo_device_release(struct ttm_bo_device *bdev) } } + mutex_lock(&glob->device_list_mutex); + list_del(&bdev->device_list); + mutex_unlock(&glob->device_list_mutex); + if (!cancel_delayed_work(&bdev->wq)) flush_scheduled_work(); while (ttm_bo_delayed_delete(bdev, true)) ; - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); if (list_empty(&bdev->ddestroy)) TTM_DEBUG("Delayed destroy list was clean\n"); if (list_empty(&bdev->man[0].lru)) TTM_DEBUG("Swap list was clean\n"); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); - ttm_mem_unregister_shrink(bdev->mem_glob, &bdev->shrink); BUG_ON(!drm_mm_clean(&bdev->addr_space_mm)); write_lock(&bdev->vm_lock); drm_mm_takedown(&bdev->addr_space_mm); write_unlock(&bdev->vm_lock); - __free_page(bdev->dummy_read_page); return ret; } EXPORT_SYMBOL(ttm_bo_device_release); -/* - * This function is intended to be called on drm driver load. - * If you decide to call it from firstopen, you must protect the call - * from a potentially racing ttm_bo_driver_finish in lastclose. - * (This may happen on X server restart). - */ - int ttm_bo_device_init(struct ttm_bo_device *bdev, - struct ttm_mem_global *mem_glob, - struct ttm_bo_driver *driver, uint64_t file_page_offset) + struct ttm_bo_global *glob, + struct ttm_bo_driver *driver, + uint64_t file_page_offset) { int ret = -EINVAL; - bdev->dummy_read_page = NULL; rwlock_init(&bdev->vm_lock); - spin_lock_init(&bdev->lru_lock); + spin_lock_init(&glob->lru_lock); bdev->driver = driver; - bdev->mem_glob = mem_glob; memset(bdev->man, 0, sizeof(bdev->man)); - bdev->dummy_read_page = alloc_page(__GFP_ZERO | GFP_DMA32); - if (unlikely(bdev->dummy_read_page == NULL)) { - ret = -ENOMEM; - goto out_err0; - } - /* * Initialize the system memory buffer type. * Other types need to be driver / IOCTL initialized. */ ret = ttm_bo_init_mm(bdev, TTM_PL_SYSTEM, 0, 0); if (unlikely(ret != 0)) - goto out_err1; + goto out_no_sys; bdev->addr_space_rb = RB_ROOT; ret = drm_mm_init(&bdev->addr_space_mm, file_page_offset, 0x10000000); if (unlikely(ret != 0)) - goto out_err2; + goto out_no_addr_mm; INIT_DELAYED_WORK(&bdev->wq, ttm_bo_delayed_workqueue); bdev->nice_mode = true; INIT_LIST_HEAD(&bdev->ddestroy); - INIT_LIST_HEAD(&bdev->swap_lru); bdev->dev_mapping = NULL; - ttm_mem_init_shrink(&bdev->shrink, ttm_bo_swapout); - ret = ttm_mem_register_shrink(mem_glob, &bdev->shrink); - if (unlikely(ret != 0)) { - printk(KERN_ERR TTM_PFX - "Could not register buffer object swapout.\n"); - goto out_err2; - } + bdev->glob = glob; - bdev->ttm_bo_extra_size = - ttm_round_pot(sizeof(struct ttm_tt)) + - ttm_round_pot(sizeof(struct ttm_backend)); - - bdev->ttm_bo_size = bdev->ttm_bo_extra_size + - ttm_round_pot(sizeof(struct ttm_buffer_object)); + mutex_lock(&glob->device_list_mutex); + list_add_tail(&bdev->device_list, &glob->device_list); + mutex_unlock(&glob->device_list_mutex); return 0; -out_err2: +out_no_addr_mm: ttm_bo_clean_mm(bdev, 0); -out_err1: - __free_page(bdev->dummy_read_page); -out_err0: +out_no_sys: return ret; } EXPORT_SYMBOL(ttm_bo_device_init); @@ -1607,21 +1699,21 @@ void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo) static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) { - struct ttm_bo_device *bdev = - container_of(shrink, struct ttm_bo_device, shrink); + struct ttm_bo_global *glob = + container_of(shrink, struct ttm_bo_global, shrink); struct ttm_buffer_object *bo; int ret = -EBUSY; int put_count; uint32_t swap_placement = (TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); while (ret == -EBUSY) { - if (unlikely(list_empty(&bdev->swap_lru))) { - spin_unlock(&bdev->lru_lock); + if (unlikely(list_empty(&glob->swap_lru))) { + spin_unlock(&glob->lru_lock); return -EBUSY; } - bo = list_first_entry(&bdev->swap_lru, + bo = list_first_entry(&glob->swap_lru, struct ttm_buffer_object, swap); kref_get(&bo->list_kref); @@ -1633,16 +1725,16 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) ret = ttm_bo_reserve_locked(bo, false, true, false, 0); if (unlikely(ret == -EBUSY)) { - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); ttm_bo_wait_unreserved(bo, false); kref_put(&bo->list_kref, ttm_bo_release_list); - spin_lock(&bdev->lru_lock); + spin_lock(&glob->lru_lock); } } BUG_ON(ret != 0); put_count = ttm_bo_del_from_lru(bo); - spin_unlock(&bdev->lru_lock); + spin_unlock(&glob->lru_lock); while (put_count--) kref_put(&bo->list_kref, ttm_bo_ref_bug); @@ -1696,6 +1788,6 @@ out: void ttm_bo_swapout_all(struct ttm_bo_device *bdev) { - while (ttm_bo_swapout(&bdev->shrink) == 0) + while (ttm_bo_swapout(&bdev->glob->shrink) == 0) ; } diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index bdec583..12cd47a 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -41,9 +41,9 @@ void ttm_bo_free_old_node(struct ttm_buffer_object *bo) struct ttm_mem_reg *old_mem = &bo->mem; if (old_mem->mm_node) { - spin_lock(&bo->bdev->lru_lock); + spin_lock(&bo->glob->lru_lock); drm_mm_put_block(old_mem->mm_node); - spin_unlock(&bo->bdev->lru_lock); + spin_unlock(&bo->glob->lru_lock); } old_mem->mm_node = NULL; } diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 4e1e256..b0f7309 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -166,7 +166,7 @@ static void ttm_tt_free_user_pages(struct ttm_tt *ttm) set_page_dirty_lock(page); ttm->pages[i] = NULL; - ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE); + ttm_mem_global_free(ttm->glob->mem_glob, PAGE_SIZE); put_page(page); } ttm->state = tt_unpopulated; @@ -177,8 +177,7 @@ static void ttm_tt_free_user_pages(struct ttm_tt *ttm) static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index) { struct page *p; - struct ttm_bo_device *bdev = ttm->bdev; - struct ttm_mem_global *mem_glob = bdev->mem_glob; + struct ttm_mem_global *mem_glob = ttm->glob->mem_glob; int ret; while (NULL == (p = ttm->pages[index])) { @@ -348,7 +347,7 @@ static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm) printk(KERN_ERR TTM_PFX "Erroneous page count. " "Leaking pages.\n"); - ttm_mem_global_free_page(ttm->bdev->mem_glob, + ttm_mem_global_free_page(ttm->glob->mem_glob, cur_page); __free_page(cur_page); } @@ -394,7 +393,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm, struct mm_struct *mm = tsk->mm; int ret; int write = (ttm->page_flags & TTM_PAGE_FLAG_WRITE) != 0; - struct ttm_mem_global *mem_glob = ttm->bdev->mem_glob; + struct ttm_mem_global *mem_glob = ttm->glob->mem_glob; BUG_ON(num_pages != ttm->num_pages); BUG_ON((ttm->page_flags & TTM_PAGE_FLAG_USER) == 0); @@ -439,8 +438,7 @@ struct ttm_tt *ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size, if (!ttm) return NULL; - ttm->bdev = bdev; - + ttm->glob = bdev->glob; ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; ttm->first_himem_page = ttm->num_pages; ttm->last_lomem_page = -1; diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index 99dc521..4911461 100644 --- a/include/drm/ttm/ttm_bo_api.h +++ b/include/drm/ttm/ttm_bo_api.h @@ -155,6 +155,7 @@ struct ttm_buffer_object { * Members constant at init. */ + struct ttm_bo_global *glob; struct ttm_bo_device *bdev; unsigned long buffer_start; enum ttm_bo_type type; diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h index 62ed733..9dc32f7 100644 --- a/include/drm/ttm/ttm_bo_driver.h +++ b/include/drm/ttm/ttm_bo_driver.h @@ -32,6 +32,7 @@ #include "ttm/ttm_bo_api.h" #include "ttm/ttm_memory.h" +#include "ttm/ttm_module.h" #include "drm_mm.h" #include "linux/workqueue.h" #include "linux/fs.h" @@ -160,7 +161,7 @@ struct ttm_tt { long last_lomem_page; uint32_t page_flags; unsigned long num_pages; - struct ttm_bo_device *bdev; + struct ttm_bo_global *glob; struct ttm_backend *be; struct task_struct *tsk; unsigned long start; @@ -355,24 +356,73 @@ struct ttm_bo_driver { void *(*sync_obj_ref) (void *sync_obj); }; -#define TTM_NUM_MEM_TYPES 8 +/** + * struct ttm_bo_global_ref - Argument to initialize a struct ttm_bo_global. + */ + +struct ttm_bo_global_ref { + struct ttm_global_reference ref; + struct ttm_mem_global *mem_glob; +}; -#define TTM_BO_PRIV_FLAG_MOVING 0 /* Buffer object is moving and needs - idling before CPU mapping */ -#define TTM_BO_PRIV_FLAG_MAX 1 /** - * struct ttm_bo_device - Buffer object driver device-specific data. + * struct ttm_bo_global - Buffer object driver global data. * * @mem_glob: Pointer to a struct ttm_mem_global object for accounting. - * @driver: Pointer to a struct ttm_bo_driver struct setup by the driver. - * @count: Current number of buffer object. - * @pages: Current number of pinned pages. * @dummy_read_page: Pointer to a dummy page used for mapping requests * of unpopulated pages. - * @shrink: A shrink callback object used for buffre object swap. + * @shrink: A shrink callback object used for buffer object swap. * @ttm_bo_extra_size: Extra size (sizeof(struct ttm_buffer_object) excluded) * used by a buffer object. This is excluding page arrays and backing pages. * @ttm_bo_size: This is @ttm_bo_extra_size + sizeof(struct ttm_buffer_object). + * @device_list_mutex: Mutex protecting the device list. + * This mutex is held while traversing the device list for pm options. + * @lru_lock: Spinlock protecting the bo subsystem lru lists. + * @device_list: List of buffer object devices. + * @swap_lru: Lru list of buffer objects used for swapping. + */ + +struct ttm_bo_global { + + /** + * Constant after init. + */ + + struct kobject kobj; + struct ttm_mem_global *mem_glob; + struct page *dummy_read_page; + struct ttm_mem_shrink shrink; + size_t ttm_bo_extra_size; + size_t ttm_bo_size; + struct mutex device_list_mutex; + spinlock_t lru_lock; + + /** + * Protected by device_list_mutex. + */ + struct list_head device_list; + + /** + * Protected by the lru_lock. + */ + struct list_head swap_lru; + + /** + * Internal protection. + */ + atomic_t bo_count; +}; + + +#define TTM_NUM_MEM_TYPES 8 + +#define TTM_BO_PRIV_FLAG_MOVING 0 /* Buffer object is moving and needs + idling before CPU mapping */ +#define TTM_BO_PRIV_FLAG_MAX 1 +/** + * struct ttm_bo_device - Buffer object driver device-specific data. + * + * @driver: Pointer to a struct ttm_bo_driver struct setup by the driver. * @man: An array of mem_type_managers. * @addr_space_mm: Range manager for the device address space. * lru_lock: Spinlock that protects the buffer+device lru lists and @@ -390,32 +440,21 @@ struct ttm_bo_device { /* * Constant after bo device init / atomic. */ - - struct ttm_mem_global *mem_glob; + struct list_head device_list; + struct ttm_bo_global *glob; struct ttm_bo_driver *driver; - struct page *dummy_read_page; - struct ttm_mem_shrink shrink; - - size_t ttm_bo_extra_size; - size_t ttm_bo_size; - rwlock_t vm_lock; + struct ttm_mem_type_manager man[TTM_NUM_MEM_TYPES]; /* * Protected by the vm lock. */ - struct ttm_mem_type_manager man[TTM_NUM_MEM_TYPES]; struct rb_root addr_space_rb; struct drm_mm addr_space_mm; /* - * Might want to change this to one lock per manager. - */ - spinlock_t lru_lock; - /* - * Protected by the lru lock. + * Protected by the global:lru lock. */ struct list_head ddestroy; - struct list_head swap_lru; /* * Protected by load / firstopen / lastclose /unload sync. @@ -629,6 +668,9 @@ extern int ttm_bo_pci_offset(struct ttm_bo_device *bdev, unsigned long *bus_offset, unsigned long *bus_size); +extern void ttm_bo_global_release(struct ttm_global_reference *ref); +extern int ttm_bo_global_init(struct ttm_global_reference *ref); + extern int ttm_bo_device_release(struct ttm_bo_device *bdev); /** @@ -646,7 +688,7 @@ extern int ttm_bo_device_release(struct ttm_bo_device *bdev); * !0: Failure. */ extern int ttm_bo_device_init(struct ttm_bo_device *bdev, - struct ttm_mem_global *mem_glob, + struct ttm_bo_global *glob, struct ttm_bo_driver *driver, uint64_t file_page_offset); -- cgit v0.10.2 From 7f5f4db2d50ea1af8f160686d2e97bbfa5102b4f Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Thu, 20 Aug 2009 10:29:08 +0200 Subject: drm/ttm: Fixes for "Make parts of a struct ttm_bo_device global" ttm: Remove a stray debug printout. Remove a re-init of the lru spinlock at device init. radeon: Fix the size of the bo_global allocation. Signed-off-by: Thomas Hellstrom Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 6f5ad08..0a85e7b 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -86,7 +86,7 @@ static int radeon_ttm_global_init(struct radeon_device *rdev) rdev->mman.mem_global_ref.object; global_ref = &rdev->mman.bo_global_ref.ref; global_ref->global_type = TTM_GLOBAL_TTM_BO; - global_ref->size = sizeof(struct ttm_mem_global); + global_ref->size = sizeof(struct ttm_bo_global); global_ref->init = &ttm_bo_global_init; global_ref->release = &ttm_bo_global_release; r = ttm_global_item_ref(global_ref); diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index fa87ccb..87c0625 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1333,7 +1333,6 @@ static void ttm_bo_global_kobj_release(struct kobject *kobj) struct ttm_bo_global *glob = container_of(kobj, struct ttm_bo_global, kobj); - printk(KERN_INFO TTM_PFX "Freeing bo global.\n"); ttm_mem_unregister_shrink(glob->mem_glob, &glob->shrink); __free_page(glob->dummy_read_page); kfree(glob); @@ -1456,8 +1455,6 @@ int ttm_bo_device_init(struct ttm_bo_device *bdev, int ret = -EINVAL; rwlock_init(&bdev->vm_lock); - spin_lock_init(&glob->lru_lock); - bdev->driver = driver; memset(bdev->man, 0, sizeof(bdev->man)); -- cgit v0.10.2 From 759e4f83f418f4001e724042b4c0e408d615d9ec Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Thu, 20 Aug 2009 10:29:09 +0200 Subject: drm/ttm: Fixes for "Memory accounting rework." ttm: Fix error paths when kobject_add returns an error. Signed-off-by: Thomas Hellstrom Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c index 62fb5cf..072c281a 100644 --- a/drivers/gpu/drm/ttm/ttm_memory.c +++ b/drivers/gpu/drm/ttm/ttm_memory.c @@ -244,6 +244,7 @@ static int ttm_mem_init_kernel_zone(struct ttm_mem_global *glob, { struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL); uint64_t mem; + int ret; if (unlikely(!zone)) return -ENOMEM; @@ -259,9 +260,14 @@ static int ttm_mem_init_kernel_zone(struct ttm_mem_global *glob, zone->used_mem = 0; zone->glob = glob; glob->zone_kernel = zone; - glob->zones[glob->num_zones++] = zone; kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type); - return kobject_add(&zone->kobj, &glob->kobj, zone->name); + ret = kobject_add(&zone->kobj, &glob->kobj, zone->name); + if (unlikely(ret != 0)) { + kobject_put(&zone->kobj); + return ret; + } + glob->zones[glob->num_zones++] = zone; + return 0; } #ifdef CONFIG_HIGHMEM @@ -270,6 +276,7 @@ static int ttm_mem_init_highmem_zone(struct ttm_mem_global *glob, { struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL); uint64_t mem; + int ret; if (unlikely(!zone)) return -ENOMEM; @@ -288,9 +295,14 @@ static int ttm_mem_init_highmem_zone(struct ttm_mem_global *glob, zone->used_mem = 0; zone->glob = glob; glob->zone_highmem = zone; - glob->zones[glob->num_zones++] = zone; kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type); - return kobject_add(&zone->kobj, &glob->kobj, zone->name); + ret = kobject_add(&zone->kobj, &glob->kobj, zone->name); + if (unlikely(ret != 0)) { + kobject_put(&zone->kobj); + return ret; + } + glob->zones[glob->num_zones++] = zone; + return 0; } #else static int ttm_mem_init_dma32_zone(struct ttm_mem_global *glob, @@ -298,6 +310,7 @@ static int ttm_mem_init_dma32_zone(struct ttm_mem_global *glob, { struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL); uint64_t mem; + int ret; if (unlikely(!zone)) return -ENOMEM; @@ -327,9 +340,14 @@ static int ttm_mem_init_dma32_zone(struct ttm_mem_global *glob, zone->used_mem = 0; zone->glob = glob; glob->zone_dma32 = zone; - glob->zones[glob->num_zones++] = zone; kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type); - return kobject_add(&zone->kobj, &glob->kobj, zone->name); + ret = kobject_add(&zone->kobj, &glob->kobj, zone->name); + if (unlikely(ret != 0)) { + kobject_put(&zone->kobj); + return ret; + } + glob->zones[glob->num_zones++] = zone; + return 0; } #endif @@ -348,8 +366,10 @@ int ttm_mem_global_init(struct ttm_mem_global *glob) ret = kobject_add(&glob->kobj, ttm_get_kobj(), "memory_accounting"); - if (unlikely(ret != 0)) - goto out_no_zone; + if (unlikely(ret != 0)) { + kobject_put(&glob->kobj); + return ret; + } si_meminfo(&si); -- cgit v0.10.2 From 132032274a594ee9ffb6b9c9e2e9698149a09ea9 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Mon, 3 Aug 2009 12:40:27 +0100 Subject: USB: Work around BIOS bugs by quiescing USB controllers earlier We are seeing a number of crashes in SMM, when VT-d is enabled while 'Legacy USB support' is enabled in various BIOSes. The BIOS is supposed to indicate which addresses it uses for DMA in a special ACPI table ("RMRR"), so that we can punch a hole for it when we set up the IOMMU. The problem is, as usual, that BIOS engineers are totally incompetent. They write code which will crash if the DMA goes AWOL, and then they either neglect to provide an RMRR table at all, or they put the wrong addresses in it. And of course they don't do _any_ QA, since that would take too much time away from their crack-smoking habit. The real fix, of course, is for consumers to refuse to buy motherboards which only have closed-source firmware available. If we had _open_ firmware, bugs like this would be easy to fix. Since that's something I can only dream about, this patch implements an alternative -- ensuring that the USB controllers are handed off from the BIOS and quiesced _before_ the IOMMU is initialised. That would have been a much better design than this RMRR nonsense in the first place, of course. The bootloader has no business doing DMA after the OS has booted anyway. Signed-off-by: David Woodhouse Signed-off-by: Greg Kroah-Hartman diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c index 83b5f9c..23cf3bd 100644 --- a/drivers/usb/host/pci-quirks.c +++ b/drivers/usb/host/pci-quirks.c @@ -475,4 +475,4 @@ static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev) else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI) quirk_usb_handoff_xhci(pdev); } -DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff); +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff); -- cgit v0.10.2 From 50f153036c9d9e4ae1768d5ca9c2ad4184f7a0b7 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 21 Aug 2009 13:21:01 +1000 Subject: drm/radeon/kms: generate the safe register tables. Previously we just made these offline and included them, but no reason we can't generate them at build time. TODO: add rs690 + r100/r200 when done. should we do rs480/rs690 no tcl version? Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 013d380..8e17718 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -6,6 +6,21 @@ ccflags-y := -Iinclude/drm radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ radeon_irq.o r300_cmdbuf.o r600_cp.o +hostprogs-y := mkregtable + +quiet_cmd_mkregtable = MKREGTABLE $@ + cmd_mkregtable = $(obj)/mkregtable $< > $@ + +$(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable + $(call if_changed,mkregtable) + +$(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable + $(call if_changed,mkregtable) + +$(obj)/rv515.o: $(obj)/rv515_reg_safe.h + +$(obj)/r300.o: $(obj)/r300_reg_safe.h + radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \ radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \ atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \ diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c new file mode 100644 index 0000000..0acd1cf --- /dev/null +++ b/drivers/gpu/drm/radeon/mkregtable.c @@ -0,0 +1,726 @@ +/* utility to create the register check tables + * this includes inlined list.h safe for userspace. + * + * Copyright 2009 Jerome Glisse + * Copyright 2009 Red Hat Inc. + * + * Authors: + * Jerome Glisse + * Dave Airlie + */ + +#include +#include +#include +#include +#include +#include + +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + + + +/* + * Simple doubly linked list implementation. + * + * Some of the internal functions ("__xxx") are useful when + * manipulating whole lists rather than single entries, as + * sometimes we already know the next/prev entries and we can + * generate better code by using them directly rather than + * using the generic single-entry routines. + */ + +struct list_head { + struct list_head *next, *prev; +}; + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +static inline void INIT_LIST_HEAD(struct list_head *list) +{ + list->next = list; + list->prev = list; +} + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +#ifndef CONFIG_DEBUG_LIST +static inline void __list_add(struct list_head *new, + struct list_head *prev, + struct list_head *next) +{ + next->prev = new; + new->next = next; + new->prev = prev; + prev->next = new; +} +#else +extern void __list_add(struct list_head *new, + struct list_head *prev, + struct list_head *next); +#endif + +/** + * list_add - add a new entry + * @new: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +static inline void list_add(struct list_head *new, struct list_head *head) +{ + __list_add(new, head, head->next); +} + + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static inline void list_add_tail(struct list_head *new, struct list_head *head) +{ + __list_add(new, head->prev, head); +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_del(struct list_head * prev, struct list_head * next) +{ + next->prev = prev; + prev->next = next; +} + +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty() on entry does not return true after this, the entry is + * in an undefined state. + */ +#ifndef CONFIG_DEBUG_LIST +static inline void list_del(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + entry->next = (void*)0xDEADBEEF; + entry->prev = (void*)0xBEEFDEAD; +} +#else +extern void list_del(struct list_head *entry); +#endif + +/** + * list_replace - replace old entry by new one + * @old : the element to be replaced + * @new : the new element to insert + * + * If @old was empty, it will be overwritten. + */ +static inline void list_replace(struct list_head *old, + struct list_head *new) +{ + new->next = old->next; + new->next->prev = new; + new->prev = old->prev; + new->prev->next = new; +} + +static inline void list_replace_init(struct list_head *old, + struct list_head *new) +{ + list_replace(old, new); + INIT_LIST_HEAD(old); +} + +/** + * list_del_init - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +static inline void list_del_init(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + INIT_LIST_HEAD(entry); +} + +/** + * list_move - delete from one list and add as another's head + * @list: the entry to move + * @head: the head that will precede our entry + */ +static inline void list_move(struct list_head *list, struct list_head *head) +{ + __list_del(list->prev, list->next); + list_add(list, head); +} + +/** + * list_move_tail - delete from one list and add as another's tail + * @list: the entry to move + * @head: the head that will follow our entry + */ +static inline void list_move_tail(struct list_head *list, + struct list_head *head) +{ + __list_del(list->prev, list->next); + list_add_tail(list, head); +} + +/** + * list_is_last - tests whether @list is the last entry in list @head + * @list: the entry to test + * @head: the head of the list + */ +static inline int list_is_last(const struct list_head *list, + const struct list_head *head) +{ + return list->next == head; +} + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static inline int list_empty(const struct list_head *head) +{ + return head->next == head; +} + +/** + * list_empty_careful - tests whether a list is empty and not being modified + * @head: the list to test + * + * Description: + * tests whether a list is empty _and_ checks that no other CPU might be + * in the process of modifying either member (next or prev) + * + * NOTE: using list_empty_careful() without synchronization + * can only be safe if the only activity that can happen + * to the list entry is list_del_init(). Eg. it cannot be used + * if another CPU could re-list_add() it. + */ +static inline int list_empty_careful(const struct list_head *head) +{ + struct list_head *next = head->next; + return (next == head) && (next == head->prev); +} + +/** + * list_is_singular - tests whether a list has just one entry. + * @head: the list to test. + */ +static inline int list_is_singular(const struct list_head *head) +{ + return !list_empty(head) && (head->next == head->prev); +} + +static inline void __list_cut_position(struct list_head *list, + struct list_head *head, struct list_head *entry) +{ + struct list_head *new_first = entry->next; + list->next = head->next; + list->next->prev = list; + list->prev = entry; + entry->next = list; + head->next = new_first; + new_first->prev = head; +} + +/** + * list_cut_position - cut a list into two + * @list: a new list to add all removed entries + * @head: a list with entries + * @entry: an entry within head, could be the head itself + * and if so we won't cut the list + * + * This helper moves the initial part of @head, up to and + * including @entry, from @head to @list. You should + * pass on @entry an element you know is on @head. @list + * should be an empty list or a list you do not care about + * losing its data. + * + */ +static inline void list_cut_position(struct list_head *list, + struct list_head *head, struct list_head *entry) +{ + if (list_empty(head)) + return; + if (list_is_singular(head) && + (head->next != entry && head != entry)) + return; + if (entry == head) + INIT_LIST_HEAD(list); + else + __list_cut_position(list, head, entry); +} + +static inline void __list_splice(const struct list_head *list, + struct list_head *prev, + struct list_head *next) +{ + struct list_head *first = list->next; + struct list_head *last = list->prev; + + first->prev = prev; + prev->next = first; + + last->next = next; + next->prev = last; +} + +/** + * list_splice - join two lists, this is designed for stacks + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice(const struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head, head->next); +} + +/** + * list_splice_tail - join two lists, each list being a queue + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice_tail(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head->prev, head); +} + +/** + * list_splice_init - join two lists and reinitialise the emptied list. + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * The list at @list is reinitialised + */ +static inline void list_splice_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head, head->next); + INIT_LIST_HEAD(list); + } +} + +/** + * list_splice_tail_init - join two lists and reinitialise the emptied list + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * Each of the lists is a queue. + * The list at @list is reinitialised + */ +static inline void list_splice_tail_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head->prev, head); + INIT_LIST_HEAD(list); + } +} + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + */ +#define list_entry(ptr, type, member) \ + container_of(ptr, type, member) + +/** + * list_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define list_first_entry(ptr, type, member) \ + list_entry((ptr)->next, type, member) + +/** + * list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each(pos, head) \ + for (pos = (head)->next; prefetch(pos->next), pos != (head); \ + pos = pos->next) + +/** + * __list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + * + * This variant differs from list_for_each() in that it's the + * simplest possible list iteration code, no prefetching is done. + * Use this for code that knows the list to be very short (empty + * or 1 entry) most of the time. + */ +#define __list_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * list_for_each_prev - iterate over a list backwards + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each_prev(pos, head) \ + for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \ + pos = pos->prev) + +/** + * list_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; \ + prefetch(pos->prev), pos != (head); \ + pos = n, n = pos->prev) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_reverse - iterate backwards over list of given type. + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_reverse(pos, head, member) \ + for (pos = list_entry((head)->prev, typeof(*pos), member); \ + prefetch(pos->member.prev), &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** + * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() + * @pos: the type * to use as a start point + * @head: the head of the list + * @member: the name of the list_struct within the struct. + * + * Prepares a pos entry for use as a start point in list_for_each_entry_continue(). + */ +#define list_prepare_entry(pos, head, member) \ + ((pos) ? : list_entry(head, typeof(*pos), member)) + +/** + * list_for_each_entry_continue - continue iteration over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Continue to iterate over list of given type, continuing after + * the current position. + */ +#define list_for_each_entry_continue(pos, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member); \ + prefetch(pos->member.next), &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_continue_reverse - iterate backwards from the given point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Start to iterate over list of given type backwards, continuing after + * the current position. + */ +#define list_for_each_entry_continue_reverse(pos, head, member) \ + for (pos = list_entry(pos->member.prev, typeof(*pos), member); \ + prefetch(pos->member.prev), &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** + * list_for_each_entry_from - iterate over list of given type from the current point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type, continuing from current position. + */ +#define list_for_each_entry_from(pos, head, member) \ + for (; prefetch(pos->member.next), &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_continue + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type, continuing after current point, + * safe against removal of list entry. + */ +#define list_for_each_entry_safe_continue(pos, n, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_from + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type from current point, safe against + * removal of list entry. + */ +#define list_for_each_entry_safe_from(pos, n, head, member) \ + for (n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_reverse + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate backwards over list of given type, safe against removal + * of list entry. + */ +#define list_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = list_entry((head)->prev, typeof(*pos), member), \ + n = list_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.prev, typeof(*n), member)) + +struct offset { + struct list_head list; + unsigned offset; +}; + +struct table { + struct list_head offsets; + unsigned offset_max; + unsigned nentry; + unsigned *table; + char *gpu_prefix; +}; + +struct offset* offset_new(unsigned o) +{ + struct offset *offset; + + offset = (struct offset*)malloc(sizeof(struct offset)); + if (offset) { + INIT_LIST_HEAD(&offset->list); + offset->offset = o; + } + return offset; +} + +void table_offset_add(struct table *t, struct offset *offset) +{ + list_add_tail(&offset->list, &t->offsets); +} + +void table_init(struct table *t) +{ + INIT_LIST_HEAD(&t->offsets); + t->offset_max = 0; + t->nentry = 0; + t->table = NULL; +} + +void table_print(struct table *t) +{ + unsigned nlloop, i, j, n, c, id; + + nlloop = (t->nentry + 3) / 4; + c = t->nentry; + printf("static const unsigned %s_reg_safe_bm[%d] = {\n", t->gpu_prefix, t->nentry); + for(i = 0, id = 0; i < nlloop; i++) { + n = 4; + if (n > c) { + n = c; + } + c -= n; + for(j = 0; j < n; j++) { + if (j == 0) printf("\t"); + else printf(" "); + printf("0x%08X,", t->table[id++]); + } + printf("\n"); + } + printf("};\n"); +} + +int table_build(struct table *t) +{ + struct offset *offset; + unsigned i, m; + + t->nentry = ((t->offset_max >> 2) + 31) / 32; + t->table = (unsigned*)malloc(sizeof(unsigned) * t->nentry); + if (t->table == NULL) { + return -1; + } + memset(t->table, 0xff, sizeof(unsigned) * t->nentry); + list_for_each_entry(offset, &t->offsets, list) { + i = (offset->offset >> 2) / 32; + m = (offset->offset >> 2) & 31; + m = 1 << m; + t->table[i] ^= m; + } + return 0; +} + +static char gpu_name[10]; +int parser_auth(struct table *t, const char *filename) +{ + FILE *file; + regex_t mask_rex; + regmatch_t match[4]; + char buf[1024]; + size_t end; + int len; + int done = 0; + int r; + unsigned o; + struct offset *offset; + char last_reg_s[10]; + int last_reg; + + if (regcomp(&mask_rex, "(0x[0-9a-fA-F]*) *([_a-zA-Z0-9]*)", REG_EXTENDED)) { + fprintf(stderr, "Failed to compile regular expression\n"); + return -1; + } + file = fopen(filename, "r"); + if (file == NULL) { + fprintf(stderr, "Failed to open: %s\n", filename); + return -1; + } + fseek(file, 0, SEEK_END); + end = ftell(file); + fseek(file, 0, SEEK_SET); + + /* get header */ + if (fgets(buf, 1024, file) == NULL) + return -1; + + /* first line will contain the last register + * and gpu name */ + sscanf(buf, "%s %s", gpu_name, last_reg_s); + t->gpu_prefix = gpu_name; + last_reg = strtol(last_reg_s, NULL, 16); + + do { + if (fgets(buf, 1024, file) == NULL) + return -1; + len = strlen(buf); + if (ftell(file) == end) { + done = 1; + } + if (len) { + r = regexec(&mask_rex, buf, 4, match, 0); + if (r == REG_NOMATCH) { + } else if (r) { + fprintf(stderr, "Error matching regular expression %d in %s\n", + r, filename); + return -1; + } else { + buf[match[0].rm_eo] = 0; + buf[match[1].rm_eo] = 0; + buf[match[2].rm_eo] = 0; + o = strtol(&buf[match[1].rm_so], NULL, 16); + offset = offset_new(o); + table_offset_add(t, offset); + if (o > t->offset_max) { + t->offset_max = o; + } + } + } + } while (!done); + fclose(file); + if (t->offset_max < last_reg) + t->offset_max = last_reg; + return table_build(t); +} + +int main(int argc, char *argv[]) +{ + struct table t; + + if (argc != 2) { + fprintf(stderr, "Usage: %s \n", + argv[0]); + exit(1); + } + table_init(&t); + if (parser_auth(&t, argv[1])) { + fprintf(stderr, "Failed to parse file %s\n", argv[1]); + return -1; + } + table_print(&t); + return 0; +} diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index c47579d..482d6b2 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -33,6 +33,8 @@ #include "radeon_drm.h" #include "radeon_share.h" +#include "r300_reg_safe.h" + /* r300,r350,rv350,rv370,rv380 depends on : */ void r100_hdp_reset(struct radeon_device *rdev); int r100_cp_reset(struct radeon_device *rdev); @@ -953,49 +955,6 @@ static inline void r300_cs_track_clear(struct r300_cs_track *track) } } -static const unsigned r300_reg_safe_bm[159] = { - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF, - 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000, - 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF, - 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF, - 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, - 0x00000000, 0x0000C100, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x0003FC01, 0xFFFFFFF8, 0xFE800B19, -}; - static int r300_packet0_check(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, unsigned idx, unsigned reg) diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300 new file mode 100644 index 0000000..b4bd5b6 --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/r300 @@ -0,0 +1,728 @@ +r300 0x4f60 +0x1434 SRC_Y_X +0x1438 DST_Y_X +0x143C DST_HEIGHT_WIDTH +0x146C DP_GUI_MASTER_CNTL +0x1474 BRUSH_Y_X +0x1478 DP_BRUSH_BKGD_CLR +0x147C DP_BRUSH_FRGD_CLR +0x1480 BRUSH_DATA0 +0x1484 BRUSH_DATA1 +0x1598 DST_WIDTH_HEIGHT +0x15C0 CLR_CMP_CNTL +0x15C4 CLR_CMP_CLR_SRC +0x15C8 CLR_CMP_CLR_DST +0x15CC CLR_CMP_MSK +0x15D8 DP_SRC_FRGD_CLR +0x15DC DP_SRC_BKGD_CLR +0x1600 DST_LINE_START +0x1604 DST_LINE_END +0x1608 DST_LINE_PATCOUNT +0x16C0 DP_CNTL +0x16CC DP_WRITE_MSK +0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR +0x16E8 DEFAULT_SC_BOTTOM_RIGHT +0x16EC SC_TOP_LEFT +0x16F0 SC_BOTTOM_RIGHT +0x16F4 SRC_SC_BOTTOM_RIGHT +0x1714 DSTCACHE_CTLSTAT +0x1720 WAIT_UNTIL +0x172C RBBM_GUICNTL +0x1D98 VAP_VPORT_XSCALE +0x1D9C VAP_VPORT_XOFFSET +0x1DA0 VAP_VPORT_YSCALE +0x1DA4 VAP_VPORT_YOFFSET +0x1DA8 VAP_VPORT_ZSCALE +0x1DAC VAP_VPORT_ZOFFSET +0x2080 VAP_CNTL +0x2090 VAP_OUT_VTX_FMT_0 +0x2094 VAP_OUT_VTX_FMT_1 +0x20B0 VAP_VTE_CNTL +0x2138 VAP_VF_MIN_VTX_INDX +0x2140 VAP_CNTL_STATUS +0x2150 VAP_PROG_STREAM_CNTL_0 +0x2154 VAP_PROG_STREAM_CNTL_1 +0x2158 VAP_PROG_STREAM_CNTL_2 +0x215C VAP_PROG_STREAM_CNTL_3 +0x2160 VAP_PROG_STREAM_CNTL_4 +0x2164 VAP_PROG_STREAM_CNTL_5 +0x2168 VAP_PROG_STREAM_CNTL_6 +0x216C VAP_PROG_STREAM_CNTL_7 +0x2180 VAP_VTX_STATE_CNTL +0x2184 VAP_VSM_VTX_ASSM +0x2188 VAP_VTX_STATE_IND_REG_0 +0x218C VAP_VTX_STATE_IND_REG_1 +0x2190 VAP_VTX_STATE_IND_REG_2 +0x2194 VAP_VTX_STATE_IND_REG_3 +0x2198 VAP_VTX_STATE_IND_REG_4 +0x219C VAP_VTX_STATE_IND_REG_5 +0x21A0 VAP_VTX_STATE_IND_REG_6 +0x21A4 VAP_VTX_STATE_IND_REG_7 +0x21A8 VAP_VTX_STATE_IND_REG_8 +0x21AC VAP_VTX_STATE_IND_REG_9 +0x21B0 VAP_VTX_STATE_IND_REG_10 +0x21B4 VAP_VTX_STATE_IND_REG_11 +0x21B8 VAP_VTX_STATE_IND_REG_12 +0x21BC VAP_VTX_STATE_IND_REG_13 +0x21C0 VAP_VTX_STATE_IND_REG_14 +0x21C4 VAP_VTX_STATE_IND_REG_15 +0x21DC VAP_PSC_SGN_NORM_CNTL +0x21E0 VAP_PROG_STREAM_CNTL_EXT_0 +0x21E4 VAP_PROG_STREAM_CNTL_EXT_1 +0x21E8 VAP_PROG_STREAM_CNTL_EXT_2 +0x21EC VAP_PROG_STREAM_CNTL_EXT_3 +0x21F0 VAP_PROG_STREAM_CNTL_EXT_4 +0x21F4 VAP_PROG_STREAM_CNTL_EXT_5 +0x21F8 VAP_PROG_STREAM_CNTL_EXT_6 +0x21FC VAP_PROG_STREAM_CNTL_EXT_7 +0x2200 VAP_PVS_VECTOR_INDX_REG +0x2204 VAP_PVS_VECTOR_DATA_REG +0x2208 VAP_PVS_VECTOR_DATA_REG_128 +0x221C VAP_CLIP_CNTL +0x2220 VAP_GB_VERT_CLIP_ADJ +0x2224 VAP_GB_VERT_DISC_ADJ +0x2228 VAP_GB_HORZ_CLIP_ADJ +0x222C VAP_GB_HORZ_DISC_ADJ +0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0 +0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1 +0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2 +0x223C VAP_PVS_FLOW_CNTL_ADDRS_3 +0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4 +0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5 +0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6 +0x224C VAP_PVS_FLOW_CNTL_ADDRS_7 +0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8 +0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9 +0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10 +0x225C VAP_PVS_FLOW_CNTL_ADDRS_11 +0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12 +0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13 +0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14 +0x226C VAP_PVS_FLOW_CNTL_ADDRS_15 +0x2284 VAP_PVS_STATE_FLUSH_REG +0x2288 VAP_PVS_VTX_TIMEOUT_REG +0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 +0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1 +0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2 +0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3 +0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4 +0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5 +0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6 +0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7 +0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8 +0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9 +0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10 +0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11 +0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12 +0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13 +0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14 +0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15 +0x22D0 VAP_PVS_CODE_CNTL_0 +0x22D4 VAP_PVS_CONST_CNTL +0x22D8 VAP_PVS_CODE_CNTL_1 +0x22DC VAP_PVS_FLOW_CNTL_OPC +0x342C RB2D_DSTCACHE_CTLSTAT +0x4000 GB_VAP_RASTER_VTX_FMT_0 +0x4004 GB_VAP_RASTER_VTX_FMT_1 +0x4008 GB_ENABLE +0x401C GB_SELECT +0x4020 GB_AA_CONFIG +0x4024 GB_FIFO_SIZE +0x4100 TX_INVALTAGS +0x4200 GA_POINT_S0 +0x4204 GA_POINT_T0 +0x4208 GA_POINT_S1 +0x420C GA_POINT_T1 +0x4214 GA_TRIANGLE_STIPPLE +0x421C GA_POINT_SIZE +0x4230 GA_POINT_MINMAX +0x4234 GA_LINE_CNTL +0x4238 GA_LINE_STIPPLE_CONFIG +0x4260 GA_LINE_STIPPLE_VALUE +0x4264 GA_LINE_S0 +0x4268 GA_LINE_S1 +0x4278 GA_COLOR_CONTROL +0x427C GA_SOLID_RG +0x4280 GA_SOLID_BA +0x4288 GA_POLY_MODE +0x428C GA_ROUND_MODE +0x4290 GA_OFFSET +0x4294 GA_FOG_SCALE +0x4298 GA_FOG_OFFSET +0x42A0 SU_TEX_WRAP +0x42A4 SU_POLY_OFFSET_FRONT_SCALE +0x42A8 SU_POLY_OFFSET_FRONT_OFFSET +0x42AC SU_POLY_OFFSET_BACK_SCALE +0x42B0 SU_POLY_OFFSET_BACK_OFFSET +0x42B4 SU_POLY_OFFSET_ENABLE +0x42B8 SU_CULL_MODE +0x42C0 SU_DEPTH_SCALE +0x42C4 SU_DEPTH_OFFSET +0x42C8 SU_REG_DEST +0x4300 RS_COUNT +0x4304 RS_INST_COUNT +0x4310 RS_IP_0 +0x4314 RS_IP_1 +0x4318 RS_IP_2 +0x431C RS_IP_3 +0x4320 RS_IP_4 +0x4324 RS_IP_5 +0x4328 RS_IP_6 +0x432C RS_IP_7 +0x4330 RS_INST_0 +0x4334 RS_INST_1 +0x4338 RS_INST_2 +0x433C RS_INST_3 +0x4340 RS_INST_4 +0x4344 RS_INST_5 +0x4348 RS_INST_6 +0x434C RS_INST_7 +0x4350 RS_INST_8 +0x4354 RS_INST_9 +0x4358 RS_INST_10 +0x435C RS_INST_11 +0x4360 RS_INST_12 +0x4364 RS_INST_13 +0x4368 RS_INST_14 +0x436C RS_INST_15 +0x43A4 SC_HYPERZ_EN +0x43A8 SC_EDGERULE +0x43B0 SC_CLIP_0_A +0x43B4 SC_CLIP_0_B +0x43B8 SC_CLIP_1_A +0x43BC SC_CLIP_1_B +0x43C0 SC_CLIP_2_A +0x43C4 SC_CLIP_2_B +0x43C8 SC_CLIP_3_A +0x43CC SC_CLIP_3_B +0x43D0 SC_CLIP_RULE +0x43E0 SC_SCISSOR0 +0x43E8 SC_SCREENDOOR +0x4440 TX_FILTER1_0 +0x4444 TX_FILTER1_1 +0x4448 TX_FILTER1_2 +0x444C TX_FILTER1_3 +0x4450 TX_FILTER1_4 +0x4454 TX_FILTER1_5 +0x4458 TX_FILTER1_6 +0x445C TX_FILTER1_7 +0x4460 TX_FILTER1_8 +0x4464 TX_FILTER1_9 +0x4468 TX_FILTER1_10 +0x446C TX_FILTER1_11 +0x4470 TX_FILTER1_12 +0x4474 TX_FILTER1_13 +0x4478 TX_FILTER1_14 +0x447C TX_FILTER1_15 +0x4580 TX_CHROMA_KEY_0 +0x4584 TX_CHROMA_KEY_1 +0x4588 TX_CHROMA_KEY_2 +0x458C TX_CHROMA_KEY_3 +0x4590 TX_CHROMA_KEY_4 +0x4594 TX_CHROMA_KEY_5 +0x4598 TX_CHROMA_KEY_6 +0x459C TX_CHROMA_KEY_7 +0x45A0 TX_CHROMA_KEY_8 +0x45A4 TX_CHROMA_KEY_9 +0x45A8 TX_CHROMA_KEY_10 +0x45AC TX_CHROMA_KEY_11 +0x45B0 TX_CHROMA_KEY_12 +0x45B4 TX_CHROMA_KEY_13 +0x45B8 TX_CHROMA_KEY_14 +0x45BC TX_CHROMA_KEY_15 +0x45C0 TX_BORDER_COLOR_0 +0x45C4 TX_BORDER_COLOR_1 +0x45C8 TX_BORDER_COLOR_2 +0x45CC TX_BORDER_COLOR_3 +0x45D0 TX_BORDER_COLOR_4 +0x45D4 TX_BORDER_COLOR_5 +0x45D8 TX_BORDER_COLOR_6 +0x45DC TX_BORDER_COLOR_7 +0x45E0 TX_BORDER_COLOR_8 +0x45E4 TX_BORDER_COLOR_9 +0x45E8 TX_BORDER_COLOR_10 +0x45EC TX_BORDER_COLOR_11 +0x45F0 TX_BORDER_COLOR_12 +0x45F4 TX_BORDER_COLOR_13 +0x45F8 TX_BORDER_COLOR_14 +0x45FC TX_BORDER_COLOR_15 +0x4600 US_CONFIG +0x4604 US_PIXSIZE +0x4608 US_CODE_OFFSET +0x460C US_RESET +0x4610 US_CODE_ADDR_0 +0x4614 US_CODE_ADDR_1 +0x4618 US_CODE_ADDR_2 +0x461C US_CODE_ADDR_3 +0x4620 US_TEX_INST_0 +0x4624 US_TEX_INST_1 +0x4628 US_TEX_INST_2 +0x462C US_TEX_INST_3 +0x4630 US_TEX_INST_4 +0x4634 US_TEX_INST_5 +0x4638 US_TEX_INST_6 +0x463C US_TEX_INST_7 +0x4640 US_TEX_INST_8 +0x4644 US_TEX_INST_9 +0x4648 US_TEX_INST_10 +0x464C US_TEX_INST_11 +0x4650 US_TEX_INST_12 +0x4654 US_TEX_INST_13 +0x4658 US_TEX_INST_14 +0x465C US_TEX_INST_15 +0x4660 US_TEX_INST_16 +0x4664 US_TEX_INST_17 +0x4668 US_TEX_INST_18 +0x466C US_TEX_INST_19 +0x4670 US_TEX_INST_20 +0x4674 US_TEX_INST_21 +0x4678 US_TEX_INST_22 +0x467C US_TEX_INST_23 +0x4680 US_TEX_INST_24 +0x4684 US_TEX_INST_25 +0x4688 US_TEX_INST_26 +0x468C US_TEX_INST_27 +0x4690 US_TEX_INST_28 +0x4694 US_TEX_INST_29 +0x4698 US_TEX_INST_30 +0x469C US_TEX_INST_31 +0x46A4 US_OUT_FMT_0 +0x46A8 US_OUT_FMT_1 +0x46AC US_OUT_FMT_2 +0x46B0 US_OUT_FMT_3 +0x46B4 US_W_FMT +0x46C0 US_ALU_RGB_ADDR_0 +0x46C4 US_ALU_RGB_ADDR_1 +0x46C8 US_ALU_RGB_ADDR_2 +0x46CC US_ALU_RGB_ADDR_3 +0x46D0 US_ALU_RGB_ADDR_4 +0x46D4 US_ALU_RGB_ADDR_5 +0x46D8 US_ALU_RGB_ADDR_6 +0x46DC US_ALU_RGB_ADDR_7 +0x46E0 US_ALU_RGB_ADDR_8 +0x46E4 US_ALU_RGB_ADDR_9 +0x46E8 US_ALU_RGB_ADDR_10 +0x46EC US_ALU_RGB_ADDR_11 +0x46F0 US_ALU_RGB_ADDR_12 +0x46F4 US_ALU_RGB_ADDR_13 +0x46F8 US_ALU_RGB_ADDR_14 +0x46FC US_ALU_RGB_ADDR_15 +0x4700 US_ALU_RGB_ADDR_16 +0x4704 US_ALU_RGB_ADDR_17 +0x4708 US_ALU_RGB_ADDR_18 +0x470C US_ALU_RGB_ADDR_19 +0x4710 US_ALU_RGB_ADDR_20 +0x4714 US_ALU_RGB_ADDR_21 +0x4718 US_ALU_RGB_ADDR_22 +0x471C US_ALU_RGB_ADDR_23 +0x4720 US_ALU_RGB_ADDR_24 +0x4724 US_ALU_RGB_ADDR_25 +0x4728 US_ALU_RGB_ADDR_26 +0x472C US_ALU_RGB_ADDR_27 +0x4730 US_ALU_RGB_ADDR_28 +0x4734 US_ALU_RGB_ADDR_29 +0x4738 US_ALU_RGB_ADDR_30 +0x473C US_ALU_RGB_ADDR_31 +0x4740 US_ALU_RGB_ADDR_32 +0x4744 US_ALU_RGB_ADDR_33 +0x4748 US_ALU_RGB_ADDR_34 +0x474C US_ALU_RGB_ADDR_35 +0x4750 US_ALU_RGB_ADDR_36 +0x4754 US_ALU_RGB_ADDR_37 +0x4758 US_ALU_RGB_ADDR_38 +0x475C US_ALU_RGB_ADDR_39 +0x4760 US_ALU_RGB_ADDR_40 +0x4764 US_ALU_RGB_ADDR_41 +0x4768 US_ALU_RGB_ADDR_42 +0x476C US_ALU_RGB_ADDR_43 +0x4770 US_ALU_RGB_ADDR_44 +0x4774 US_ALU_RGB_ADDR_45 +0x4778 US_ALU_RGB_ADDR_46 +0x477C US_ALU_RGB_ADDR_47 +0x4780 US_ALU_RGB_ADDR_48 +0x4784 US_ALU_RGB_ADDR_49 +0x4788 US_ALU_RGB_ADDR_50 +0x478C US_ALU_RGB_ADDR_51 +0x4790 US_ALU_RGB_ADDR_52 +0x4794 US_ALU_RGB_ADDR_53 +0x4798 US_ALU_RGB_ADDR_54 +0x479C US_ALU_RGB_ADDR_55 +0x47A0 US_ALU_RGB_ADDR_56 +0x47A4 US_ALU_RGB_ADDR_57 +0x47A8 US_ALU_RGB_ADDR_58 +0x47AC US_ALU_RGB_ADDR_59 +0x47B0 US_ALU_RGB_ADDR_60 +0x47B4 US_ALU_RGB_ADDR_61 +0x47B8 US_ALU_RGB_ADDR_62 +0x47BC US_ALU_RGB_ADDR_63 +0x47C0 US_ALU_ALPHA_ADDR_0 +0x47C4 US_ALU_ALPHA_ADDR_1 +0x47C8 US_ALU_ALPHA_ADDR_2 +0x47CC US_ALU_ALPHA_ADDR_3 +0x47D0 US_ALU_ALPHA_ADDR_4 +0x47D4 US_ALU_ALPHA_ADDR_5 +0x47D8 US_ALU_ALPHA_ADDR_6 +0x47DC US_ALU_ALPHA_ADDR_7 +0x47E0 US_ALU_ALPHA_ADDR_8 +0x47E4 US_ALU_ALPHA_ADDR_9 +0x47E8 US_ALU_ALPHA_ADDR_10 +0x47EC US_ALU_ALPHA_ADDR_11 +0x47F0 US_ALU_ALPHA_ADDR_12 +0x47F4 US_ALU_ALPHA_ADDR_13 +0x47F8 US_ALU_ALPHA_ADDR_14 +0x47FC US_ALU_ALPHA_ADDR_15 +0x4800 US_ALU_ALPHA_ADDR_16 +0x4804 US_ALU_ALPHA_ADDR_17 +0x4808 US_ALU_ALPHA_ADDR_18 +0x480C US_ALU_ALPHA_ADDR_19 +0x4810 US_ALU_ALPHA_ADDR_20 +0x4814 US_ALU_ALPHA_ADDR_21 +0x4818 US_ALU_ALPHA_ADDR_22 +0x481C US_ALU_ALPHA_ADDR_23 +0x4820 US_ALU_ALPHA_ADDR_24 +0x4824 US_ALU_ALPHA_ADDR_25 +0x4828 US_ALU_ALPHA_ADDR_26 +0x482C US_ALU_ALPHA_ADDR_27 +0x4830 US_ALU_ALPHA_ADDR_28 +0x4834 US_ALU_ALPHA_ADDR_29 +0x4838 US_ALU_ALPHA_ADDR_30 +0x483C US_ALU_ALPHA_ADDR_31 +0x4840 US_ALU_ALPHA_ADDR_32 +0x4844 US_ALU_ALPHA_ADDR_33 +0x4848 US_ALU_ALPHA_ADDR_34 +0x484C US_ALU_ALPHA_ADDR_35 +0x4850 US_ALU_ALPHA_ADDR_36 +0x4854 US_ALU_ALPHA_ADDR_37 +0x4858 US_ALU_ALPHA_ADDR_38 +0x485C US_ALU_ALPHA_ADDR_39 +0x4860 US_ALU_ALPHA_ADDR_40 +0x4864 US_ALU_ALPHA_ADDR_41 +0x4868 US_ALU_ALPHA_ADDR_42 +0x486C US_ALU_ALPHA_ADDR_43 +0x4870 US_ALU_ALPHA_ADDR_44 +0x4874 US_ALU_ALPHA_ADDR_45 +0x4878 US_ALU_ALPHA_ADDR_46 +0x487C US_ALU_ALPHA_ADDR_47 +0x4880 US_ALU_ALPHA_ADDR_48 +0x4884 US_ALU_ALPHA_ADDR_49 +0x4888 US_ALU_ALPHA_ADDR_50 +0x488C US_ALU_ALPHA_ADDR_51 +0x4890 US_ALU_ALPHA_ADDR_52 +0x4894 US_ALU_ALPHA_ADDR_53 +0x4898 US_ALU_ALPHA_ADDR_54 +0x489C US_ALU_ALPHA_ADDR_55 +0x48A0 US_ALU_ALPHA_ADDR_56 +0x48A4 US_ALU_ALPHA_ADDR_57 +0x48A8 US_ALU_ALPHA_ADDR_58 +0x48AC US_ALU_ALPHA_ADDR_59 +0x48B0 US_ALU_ALPHA_ADDR_60 +0x48B4 US_ALU_ALPHA_ADDR_61 +0x48B8 US_ALU_ALPHA_ADDR_62 +0x48BC US_ALU_ALPHA_ADDR_63 +0x48C0 US_ALU_RGB_INST_0 +0x48C4 US_ALU_RGB_INST_1 +0x48C8 US_ALU_RGB_INST_2 +0x48CC US_ALU_RGB_INST_3 +0x48D0 US_ALU_RGB_INST_4 +0x48D4 US_ALU_RGB_INST_5 +0x48D8 US_ALU_RGB_INST_6 +0x48DC US_ALU_RGB_INST_7 +0x48E0 US_ALU_RGB_INST_8 +0x48E4 US_ALU_RGB_INST_9 +0x48E8 US_ALU_RGB_INST_10 +0x48EC US_ALU_RGB_INST_11 +0x48F0 US_ALU_RGB_INST_12 +0x48F4 US_ALU_RGB_INST_13 +0x48F8 US_ALU_RGB_INST_14 +0x48FC US_ALU_RGB_INST_15 +0x4900 US_ALU_RGB_INST_16 +0x4904 US_ALU_RGB_INST_17 +0x4908 US_ALU_RGB_INST_18 +0x490C US_ALU_RGB_INST_19 +0x4910 US_ALU_RGB_INST_20 +0x4914 US_ALU_RGB_INST_21 +0x4918 US_ALU_RGB_INST_22 +0x491C US_ALU_RGB_INST_23 +0x4920 US_ALU_RGB_INST_24 +0x4924 US_ALU_RGB_INST_25 +0x4928 US_ALU_RGB_INST_26 +0x492C US_ALU_RGB_INST_27 +0x4930 US_ALU_RGB_INST_28 +0x4934 US_ALU_RGB_INST_29 +0x4938 US_ALU_RGB_INST_30 +0x493C US_ALU_RGB_INST_31 +0x4940 US_ALU_RGB_INST_32 +0x4944 US_ALU_RGB_INST_33 +0x4948 US_ALU_RGB_INST_34 +0x494C US_ALU_RGB_INST_35 +0x4950 US_ALU_RGB_INST_36 +0x4954 US_ALU_RGB_INST_37 +0x4958 US_ALU_RGB_INST_38 +0x495C US_ALU_RGB_INST_39 +0x4960 US_ALU_RGB_INST_40 +0x4964 US_ALU_RGB_INST_41 +0x4968 US_ALU_RGB_INST_42 +0x496C US_ALU_RGB_INST_43 +0x4970 US_ALU_RGB_INST_44 +0x4974 US_ALU_RGB_INST_45 +0x4978 US_ALU_RGB_INST_46 +0x497C US_ALU_RGB_INST_47 +0x4980 US_ALU_RGB_INST_48 +0x4984 US_ALU_RGB_INST_49 +0x4988 US_ALU_RGB_INST_50 +0x498C US_ALU_RGB_INST_51 +0x4990 US_ALU_RGB_INST_52 +0x4994 US_ALU_RGB_INST_53 +0x4998 US_ALU_RGB_INST_54 +0x499C US_ALU_RGB_INST_55 +0x49A0 US_ALU_RGB_INST_56 +0x49A4 US_ALU_RGB_INST_57 +0x49A8 US_ALU_RGB_INST_58 +0x49AC US_ALU_RGB_INST_59 +0x49B0 US_ALU_RGB_INST_60 +0x49B4 US_ALU_RGB_INST_61 +0x49B8 US_ALU_RGB_INST_62 +0x49BC US_ALU_RGB_INST_63 +0x49C0 US_ALU_ALPHA_INST_0 +0x49C4 US_ALU_ALPHA_INST_1 +0x49C8 US_ALU_ALPHA_INST_2 +0x49CC US_ALU_ALPHA_INST_3 +0x49D0 US_ALU_ALPHA_INST_4 +0x49D4 US_ALU_ALPHA_INST_5 +0x49D8 US_ALU_ALPHA_INST_6 +0x49DC US_ALU_ALPHA_INST_7 +0x49E0 US_ALU_ALPHA_INST_8 +0x49E4 US_ALU_ALPHA_INST_9 +0x49E8 US_ALU_ALPHA_INST_10 +0x49EC US_ALU_ALPHA_INST_11 +0x49F0 US_ALU_ALPHA_INST_12 +0x49F4 US_ALU_ALPHA_INST_13 +0x49F8 US_ALU_ALPHA_INST_14 +0x49FC US_ALU_ALPHA_INST_15 +0x4A00 US_ALU_ALPHA_INST_16 +0x4A04 US_ALU_ALPHA_INST_17 +0x4A08 US_ALU_ALPHA_INST_18 +0x4A0C US_ALU_ALPHA_INST_19 +0x4A10 US_ALU_ALPHA_INST_20 +0x4A14 US_ALU_ALPHA_INST_21 +0x4A18 US_ALU_ALPHA_INST_22 +0x4A1C US_ALU_ALPHA_INST_23 +0x4A20 US_ALU_ALPHA_INST_24 +0x4A24 US_ALU_ALPHA_INST_25 +0x4A28 US_ALU_ALPHA_INST_26 +0x4A2C US_ALU_ALPHA_INST_27 +0x4A30 US_ALU_ALPHA_INST_28 +0x4A34 US_ALU_ALPHA_INST_29 +0x4A38 US_ALU_ALPHA_INST_30 +0x4A3C US_ALU_ALPHA_INST_31 +0x4A40 US_ALU_ALPHA_INST_32 +0x4A44 US_ALU_ALPHA_INST_33 +0x4A48 US_ALU_ALPHA_INST_34 +0x4A4C US_ALU_ALPHA_INST_35 +0x4A50 US_ALU_ALPHA_INST_36 +0x4A54 US_ALU_ALPHA_INST_37 +0x4A58 US_ALU_ALPHA_INST_38 +0x4A5C US_ALU_ALPHA_INST_39 +0x4A60 US_ALU_ALPHA_INST_40 +0x4A64 US_ALU_ALPHA_INST_41 +0x4A68 US_ALU_ALPHA_INST_42 +0x4A6C US_ALU_ALPHA_INST_43 +0x4A70 US_ALU_ALPHA_INST_44 +0x4A74 US_ALU_ALPHA_INST_45 +0x4A78 US_ALU_ALPHA_INST_46 +0x4A7C US_ALU_ALPHA_INST_47 +0x4A80 US_ALU_ALPHA_INST_48 +0x4A84 US_ALU_ALPHA_INST_49 +0x4A88 US_ALU_ALPHA_INST_50 +0x4A8C US_ALU_ALPHA_INST_51 +0x4A90 US_ALU_ALPHA_INST_52 +0x4A94 US_ALU_ALPHA_INST_53 +0x4A98 US_ALU_ALPHA_INST_54 +0x4A9C US_ALU_ALPHA_INST_55 +0x4AA0 US_ALU_ALPHA_INST_56 +0x4AA4 US_ALU_ALPHA_INST_57 +0x4AA8 US_ALU_ALPHA_INST_58 +0x4AAC US_ALU_ALPHA_INST_59 +0x4AB0 US_ALU_ALPHA_INST_60 +0x4AB4 US_ALU_ALPHA_INST_61 +0x4AB8 US_ALU_ALPHA_INST_62 +0x4ABC US_ALU_ALPHA_INST_63 +0x4BC0 FG_FOG_BLEND +0x4BC4 FG_FOG_FACTOR +0x4BC8 FG_FOG_COLOR_R +0x4BCC FG_FOG_COLOR_G +0x4BD0 FG_FOG_COLOR_B +0x4BD4 FG_ALPHA_FUNC +0x4BD8 FG_DEPTH_SRC +0x4C00 US_ALU_CONST_R_0 +0x4C04 US_ALU_CONST_G_0 +0x4C08 US_ALU_CONST_B_0 +0x4C0C US_ALU_CONST_A_0 +0x4C10 US_ALU_CONST_R_1 +0x4C14 US_ALU_CONST_G_1 +0x4C18 US_ALU_CONST_B_1 +0x4C1C US_ALU_CONST_A_1 +0x4C20 US_ALU_CONST_R_2 +0x4C24 US_ALU_CONST_G_2 +0x4C28 US_ALU_CONST_B_2 +0x4C2C US_ALU_CONST_A_2 +0x4C30 US_ALU_CONST_R_3 +0x4C34 US_ALU_CONST_G_3 +0x4C38 US_ALU_CONST_B_3 +0x4C3C US_ALU_CONST_A_3 +0x4C40 US_ALU_CONST_R_4 +0x4C44 US_ALU_CONST_G_4 +0x4C48 US_ALU_CONST_B_4 +0x4C4C US_ALU_CONST_A_4 +0x4C50 US_ALU_CONST_R_5 +0x4C54 US_ALU_CONST_G_5 +0x4C58 US_ALU_CONST_B_5 +0x4C5C US_ALU_CONST_A_5 +0x4C60 US_ALU_CONST_R_6 +0x4C64 US_ALU_CONST_G_6 +0x4C68 US_ALU_CONST_B_6 +0x4C6C US_ALU_CONST_A_6 +0x4C70 US_ALU_CONST_R_7 +0x4C74 US_ALU_CONST_G_7 +0x4C78 US_ALU_CONST_B_7 +0x4C7C US_ALU_CONST_A_7 +0x4C80 US_ALU_CONST_R_8 +0x4C84 US_ALU_CONST_G_8 +0x4C88 US_ALU_CONST_B_8 +0x4C8C US_ALU_CONST_A_8 +0x4C90 US_ALU_CONST_R_9 +0x4C94 US_ALU_CONST_G_9 +0x4C98 US_ALU_CONST_B_9 +0x4C9C US_ALU_CONST_A_9 +0x4CA0 US_ALU_CONST_R_10 +0x4CA4 US_ALU_CONST_G_10 +0x4CA8 US_ALU_CONST_B_10 +0x4CAC US_ALU_CONST_A_10 +0x4CB0 US_ALU_CONST_R_11 +0x4CB4 US_ALU_CONST_G_11 +0x4CB8 US_ALU_CONST_B_11 +0x4CBC US_ALU_CONST_A_11 +0x4CC0 US_ALU_CONST_R_12 +0x4CC4 US_ALU_CONST_G_12 +0x4CC8 US_ALU_CONST_B_12 +0x4CCC US_ALU_CONST_A_12 +0x4CD0 US_ALU_CONST_R_13 +0x4CD4 US_ALU_CONST_G_13 +0x4CD8 US_ALU_CONST_B_13 +0x4CDC US_ALU_CONST_A_13 +0x4CE0 US_ALU_CONST_R_14 +0x4CE4 US_ALU_CONST_G_14 +0x4CE8 US_ALU_CONST_B_14 +0x4CEC US_ALU_CONST_A_14 +0x4CF0 US_ALU_CONST_R_15 +0x4CF4 US_ALU_CONST_G_15 +0x4CF8 US_ALU_CONST_B_15 +0x4CFC US_ALU_CONST_A_15 +0x4D00 US_ALU_CONST_R_16 +0x4D04 US_ALU_CONST_G_16 +0x4D08 US_ALU_CONST_B_16 +0x4D0C US_ALU_CONST_A_16 +0x4D10 US_ALU_CONST_R_17 +0x4D14 US_ALU_CONST_G_17 +0x4D18 US_ALU_CONST_B_17 +0x4D1C US_ALU_CONST_A_17 +0x4D20 US_ALU_CONST_R_18 +0x4D24 US_ALU_CONST_G_18 +0x4D28 US_ALU_CONST_B_18 +0x4D2C US_ALU_CONST_A_18 +0x4D30 US_ALU_CONST_R_19 +0x4D34 US_ALU_CONST_G_19 +0x4D38 US_ALU_CONST_B_19 +0x4D3C US_ALU_CONST_A_19 +0x4D40 US_ALU_CONST_R_20 +0x4D44 US_ALU_CONST_G_20 +0x4D48 US_ALU_CONST_B_20 +0x4D4C US_ALU_CONST_A_20 +0x4D50 US_ALU_CONST_R_21 +0x4D54 US_ALU_CONST_G_21 +0x4D58 US_ALU_CONST_B_21 +0x4D5C US_ALU_CONST_A_21 +0x4D60 US_ALU_CONST_R_22 +0x4D64 US_ALU_CONST_G_22 +0x4D68 US_ALU_CONST_B_22 +0x4D6C US_ALU_CONST_A_22 +0x4D70 US_ALU_CONST_R_23 +0x4D74 US_ALU_CONST_G_23 +0x4D78 US_ALU_CONST_B_23 +0x4D7C US_ALU_CONST_A_23 +0x4D80 US_ALU_CONST_R_24 +0x4D84 US_ALU_CONST_G_24 +0x4D88 US_ALU_CONST_B_24 +0x4D8C US_ALU_CONST_A_24 +0x4D90 US_ALU_CONST_R_25 +0x4D94 US_ALU_CONST_G_25 +0x4D98 US_ALU_CONST_B_25 +0x4D9C US_ALU_CONST_A_25 +0x4DA0 US_ALU_CONST_R_26 +0x4DA4 US_ALU_CONST_G_26 +0x4DA8 US_ALU_CONST_B_26 +0x4DAC US_ALU_CONST_A_26 +0x4DB0 US_ALU_CONST_R_27 +0x4DB4 US_ALU_CONST_G_27 +0x4DB8 US_ALU_CONST_B_27 +0x4DBC US_ALU_CONST_A_27 +0x4DC0 US_ALU_CONST_R_28 +0x4DC4 US_ALU_CONST_G_28 +0x4DC8 US_ALU_CONST_B_28 +0x4DCC US_ALU_CONST_A_28 +0x4DD0 US_ALU_CONST_R_29 +0x4DD4 US_ALU_CONST_G_29 +0x4DD8 US_ALU_CONST_B_29 +0x4DDC US_ALU_CONST_A_29 +0x4DE0 US_ALU_CONST_R_30 +0x4DE4 US_ALU_CONST_G_30 +0x4DE8 US_ALU_CONST_B_30 +0x4DEC US_ALU_CONST_A_30 +0x4DF0 US_ALU_CONST_R_31 +0x4DF4 US_ALU_CONST_G_31 +0x4DF8 US_ALU_CONST_B_31 +0x4DFC US_ALU_CONST_A_31 +0x4E04 RB3D_BLENDCNTL_R3 +0x4E08 RB3D_ABLENDCNTL_R3 +0x4E0C RB3D_COLOR_CHANNEL_MASK +0x4E10 RB3D_CONSTANT_COLOR +0x4E14 RB3D_COLOR_CLEAR_VALUE +0x4E18 RB3D_ROPCNTL_R3 +0x4E1C RB3D_CLRCMP_FLIPE_R3 +0x4E20 RB3D_CLRCMP_CLR_R3 +0x4E24 RB3D_CLRCMP_MSK_R3 +0x4E48 RB3D_DEBUG_CTL +0x4E4C RB3D_DSTCACHE_CTLSTAT_R3 +0x4E50 RB3D_DITHER_CTL +0x4E54 RB3D_CMASK_OFFSET0 +0x4E58 RB3D_CMASK_OFFSET1 +0x4E5C RB3D_CMASK_OFFSET2 +0x4E60 RB3D_CMASK_OFFSET3 +0x4E64 RB3D_CMASK_PITCH0 +0x4E68 RB3D_CMASK_PITCH1 +0x4E6C RB3D_CMASK_PITCH2 +0x4E70 RB3D_CMASK_PITCH3 +0x4E74 RB3D_CMASK_WRINDEX +0x4E78 RB3D_CMASK_DWORD +0x4E7C RB3D_CMASK_RDINDEX +0x4E80 RB3D_AARESOLVE_OFFSET +0x4E84 RB3D_AARESOLVE_PITCH +0x4E88 RB3D_AARESOLVE_CTL +0x4F04 ZB_ZSTENCILCNTL +0x4F08 ZB_STENCILREFMASK +0x4F14 ZB_ZTOP +0x4F18 ZB_ZCACHE_CTLSTAT +0x4F1C ZB_BW_CNTL +0x4F28 ZB_DEPTHCLEARVALUE +0x4F30 ZB_ZMASK_OFFSET +0x4F34 ZB_ZMASK_PITCH +0x4F38 ZB_ZMASK_WRINDEX +0x4F3C ZB_ZMASK_DWORD +0x4F40 ZB_ZMASK_RDINDEX +0x4F44 ZB_HIZ_OFFSET +0x4F48 ZB_HIZ_WRINDEX +0x4F4C ZB_HIZ_DWORD +0x4F50 ZB_HIZ_RDINDEX +0x4F54 ZB_HIZ_PITCH +0x4F58 ZB_ZPASS_DATA +0x4F60 ZB_DEPTHXY_OFFSET diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515 new file mode 100644 index 0000000..d1fcf38 --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/rv515 @@ -0,0 +1,486 @@ +rv515 0x6d40 +0x1434 SRC_Y_X +0x1438 DST_Y_X +0x143C DST_HEIGHT_WIDTH +0x146C DP_GUI_MASTER_CNTL +0x1474 BRUSH_Y_X +0x1478 DP_BRUSH_BKGD_CLR +0x147C DP_BRUSH_FRGD_CLR +0x1480 BRUSH_DATA0 +0x1484 BRUSH_DATA1 +0x1598 DST_WIDTH_HEIGHT +0x15C0 CLR_CMP_CNTL +0x15C4 CLR_CMP_CLR_SRC +0x15C8 CLR_CMP_CLR_DST +0x15CC CLR_CMP_MSK +0x15D8 DP_SRC_FRGD_CLR +0x15DC DP_SRC_BKGD_CLR +0x1600 DST_LINE_START +0x1604 DST_LINE_END +0x1608 DST_LINE_PATCOUNT +0x16C0 DP_CNTL +0x16CC DP_WRITE_MSK +0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR +0x16E8 DEFAULT_SC_BOTTOM_RIGHT +0x16EC SC_TOP_LEFT +0x16F0 SC_BOTTOM_RIGHT +0x16F4 SRC_SC_BOTTOM_RIGHT +0x1714 DSTCACHE_CTLSTAT +0x1720 WAIT_UNTIL +0x172C RBBM_GUICNTL +0x1D98 VAP_VPORT_XSCALE +0x1D9C VAP_VPORT_XOFFSET +0x1DA0 VAP_VPORT_YSCALE +0x1DA4 VAP_VPORT_YOFFSET +0x1DA8 VAP_VPORT_ZSCALE +0x1DAC VAP_VPORT_ZOFFSET +0x2080 VAP_CNTL +0x2090 VAP_OUT_VTX_FMT_0 +0x2094 VAP_OUT_VTX_FMT_1 +0x20B0 VAP_VTE_CNTL +0x2138 VAP_VF_MIN_VTX_INDX +0x2140 VAP_CNTL_STATUS +0x2150 VAP_PROG_STREAM_CNTL_0 +0x2154 VAP_PROG_STREAM_CNTL_1 +0x2158 VAP_PROG_STREAM_CNTL_2 +0x215C VAP_PROG_STREAM_CNTL_3 +0x2160 VAP_PROG_STREAM_CNTL_4 +0x2164 VAP_PROG_STREAM_CNTL_5 +0x2168 VAP_PROG_STREAM_CNTL_6 +0x216C VAP_PROG_STREAM_CNTL_7 +0x2180 VAP_VTX_STATE_CNTL +0x2184 VAP_VSM_VTX_ASSM +0x2188 VAP_VTX_STATE_IND_REG_0 +0x218C VAP_VTX_STATE_IND_REG_1 +0x2190 VAP_VTX_STATE_IND_REG_2 +0x2194 VAP_VTX_STATE_IND_REG_3 +0x2198 VAP_VTX_STATE_IND_REG_4 +0x219C VAP_VTX_STATE_IND_REG_5 +0x21A0 VAP_VTX_STATE_IND_REG_6 +0x21A4 VAP_VTX_STATE_IND_REG_7 +0x21A8 VAP_VTX_STATE_IND_REG_8 +0x21AC VAP_VTX_STATE_IND_REG_9 +0x21B0 VAP_VTX_STATE_IND_REG_10 +0x21B4 VAP_VTX_STATE_IND_REG_11 +0x21B8 VAP_VTX_STATE_IND_REG_12 +0x21BC VAP_VTX_STATE_IND_REG_13 +0x21C0 VAP_VTX_STATE_IND_REG_14 +0x21C4 VAP_VTX_STATE_IND_REG_15 +0x21DC VAP_PSC_SGN_NORM_CNTL +0x21E0 VAP_PROG_STREAM_CNTL_EXT_0 +0x21E4 VAP_PROG_STREAM_CNTL_EXT_1 +0x21E8 VAP_PROG_STREAM_CNTL_EXT_2 +0x21EC VAP_PROG_STREAM_CNTL_EXT_3 +0x21F0 VAP_PROG_STREAM_CNTL_EXT_4 +0x21F4 VAP_PROG_STREAM_CNTL_EXT_5 +0x21F8 VAP_PROG_STREAM_CNTL_EXT_6 +0x21FC VAP_PROG_STREAM_CNTL_EXT_7 +0x2200 VAP_PVS_VECTOR_INDX_REG +0x2204 VAP_PVS_VECTOR_DATA_REG +0x2208 VAP_PVS_VECTOR_DATA_REG_128 +0x2218 VAP_TEX_TO_COLOR_CNTL +0x221C VAP_CLIP_CNTL +0x2220 VAP_GB_VERT_CLIP_ADJ +0x2224 VAP_GB_VERT_DISC_ADJ +0x2228 VAP_GB_HORZ_CLIP_ADJ +0x222C VAP_GB_HORZ_DISC_ADJ +0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0 +0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1 +0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2 +0x223C VAP_PVS_FLOW_CNTL_ADDRS_3 +0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4 +0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5 +0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6 +0x224C VAP_PVS_FLOW_CNTL_ADDRS_7 +0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8 +0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9 +0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10 +0x225C VAP_PVS_FLOW_CNTL_ADDRS_11 +0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12 +0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13 +0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14 +0x226C VAP_PVS_FLOW_CNTL_ADDRS_15 +0x2284 VAP_PVS_STATE_FLUSH_REG +0x2288 VAP_PVS_VTX_TIMEOUT_REG +0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 +0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1 +0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2 +0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3 +0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4 +0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5 +0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6 +0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7 +0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8 +0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9 +0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10 +0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11 +0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12 +0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13 +0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14 +0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15 +0x22D0 VAP_PVS_CODE_CNTL_0 +0x22D4 VAP_PVS_CONST_CNTL +0x22D8 VAP_PVS_CODE_CNTL_1 +0x22DC VAP_PVS_FLOW_CNTL_OPC +0x2500 VAP_PVS_FLOW_CNTL_ADDRS_LW_0 +0x2504 VAP_PVS_FLOW_CNTL_ADDRS_UW_0 +0x2508 VAP_PVS_FLOW_CNTL_ADDRS_LW_1 +0x250C VAP_PVS_FLOW_CNTL_ADDRS_UW_1 +0x2510 VAP_PVS_FLOW_CNTL_ADDRS_LW_2 +0x2514 VAP_PVS_FLOW_CNTL_ADDRS_UW_2 +0x2518 VAP_PVS_FLOW_CNTL_ADDRS_LW_3 +0x251C VAP_PVS_FLOW_CNTL_ADDRS_UW_3 +0x2520 VAP_PVS_FLOW_CNTL_ADDRS_LW_4 +0x2524 VAP_PVS_FLOW_CNTL_ADDRS_UW_4 +0x2528 VAP_PVS_FLOW_CNTL_ADDRS_LW_5 +0x252C VAP_PVS_FLOW_CNTL_ADDRS_UW_5 +0x2530 VAP_PVS_FLOW_CNTL_ADDRS_LW_6 +0x2534 VAP_PVS_FLOW_CNTL_ADDRS_UW_6 +0x2538 VAP_PVS_FLOW_CNTL_ADDRS_LW_7 +0x253C VAP_PVS_FLOW_CNTL_ADDRS_UW_7 +0x2540 VAP_PVS_FLOW_CNTL_ADDRS_LW_8 +0x2544 VAP_PVS_FLOW_CNTL_ADDRS_UW_8 +0x2548 VAP_PVS_FLOW_CNTL_ADDRS_LW_9 +0x254C VAP_PVS_FLOW_CNTL_ADDRS_UW_9 +0x2550 VAP_PVS_FLOW_CNTL_ADDRS_LW_10 +0x2554 VAP_PVS_FLOW_CNTL_ADDRS_UW_10 +0x2558 VAP_PVS_FLOW_CNTL_ADDRS_LW_11 +0x255C VAP_PVS_FLOW_CNTL_ADDRS_UW_11 +0x2560 VAP_PVS_FLOW_CNTL_ADDRS_LW_12 +0x2564 VAP_PVS_FLOW_CNTL_ADDRS_UW_12 +0x2568 VAP_PVS_FLOW_CNTL_ADDRS_LW_13 +0x256C VAP_PVS_FLOW_CNTL_ADDRS_UW_13 +0x2570 VAP_PVS_FLOW_CNTL_ADDRS_LW_14 +0x2574 VAP_PVS_FLOW_CNTL_ADDRS_UW_14 +0x2578 VAP_PVS_FLOW_CNTL_ADDRS_LW_15 +0x257C VAP_PVS_FLOW_CNTL_ADDRS_UW_15 +0x342C RB2D_DSTCACHE_CTLSTAT +0x4000 GB_VAP_RASTER_VTX_FMT_0 +0x4004 GB_VAP_RASTER_VTX_FMT_1 +0x4008 GB_ENABLE +0x401C GB_SELECT +0x4020 GB_AA_CONFIG +0x4024 GB_FIFO_SIZE +0x4100 TX_INVALTAGS +0x4200 GA_POINT_S0 +0x4204 GA_POINT_T0 +0x4208 GA_POINT_S1 +0x420C GA_POINT_T1 +0x4214 GA_TRIANGLE_STIPPLE +0x421C GA_POINT_SIZE +0x4230 GA_POINT_MINMAX +0x4234 GA_LINE_CNTL +0x4238 GA_LINE_STIPPLE_CONFIG +0x4260 GA_LINE_STIPPLE_VALUE +0x4264 GA_LINE_S0 +0x4268 GA_LINE_S1 +0x4278 GA_COLOR_CONTROL +0x427C GA_SOLID_RG +0x4280 GA_SOLID_BA +0x4288 GA_POLY_MODE +0x428C GA_ROUND_MODE +0x4290 GA_OFFSET +0x4294 GA_FOG_SCALE +0x4298 GA_FOG_OFFSET +0x42A0 SU_TEX_WRAP +0x42A4 SU_POLY_OFFSET_FRONT_SCALE +0x42A8 SU_POLY_OFFSET_FRONT_OFFSET +0x42AC SU_POLY_OFFSET_BACK_SCALE +0x42B0 SU_POLY_OFFSET_BACK_OFFSET +0x42B4 SU_POLY_OFFSET_ENABLE +0x42B8 SU_CULL_MODE +0x42C0 SU_DEPTH_SCALE +0x42C4 SU_DEPTH_OFFSET +0x42C8 SU_REG_DEST +0x4300 RS_COUNT +0x4304 RS_INST_COUNT +0x4074 RS_IP_0 +0x4078 RS_IP_1 +0x407C RS_IP_2 +0x4080 RS_IP_3 +0x4084 RS_IP_4 +0x4088 RS_IP_5 +0x408C RS_IP_6 +0x4090 RS_IP_7 +0x4094 RS_IP_8 +0x4098 RS_IP_9 +0x409C RS_IP_10 +0x40A0 RS_IP_11 +0x40A4 RS_IP_12 +0x40A8 RS_IP_13 +0x40AC RS_IP_14 +0x40B0 RS_IP_15 +0x4320 RS_INST_0 +0x4324 RS_INST_1 +0x4328 RS_INST_2 +0x432C RS_INST_3 +0x4330 RS_INST_4 +0x4334 RS_INST_5 +0x4338 RS_INST_6 +0x433C RS_INST_7 +0x4340 RS_INST_8 +0x4344 RS_INST_9 +0x4348 RS_INST_10 +0x434C RS_INST_11 +0x4350 RS_INST_12 +0x4354 RS_INST_13 +0x4358 RS_INST_14 +0x435C RS_INST_15 +0x43A4 SC_HYPERZ_EN +0x43A8 SC_EDGERULE +0x43B0 SC_CLIP_0_A +0x43B4 SC_CLIP_0_B +0x43B8 SC_CLIP_1_A +0x43BC SC_CLIP_1_B +0x43C0 SC_CLIP_2_A +0x43C4 SC_CLIP_2_B +0x43C8 SC_CLIP_3_A +0x43CC SC_CLIP_3_B +0x43D0 SC_CLIP_RULE +0x43E0 SC_SCISSOR0 +0x43E8 SC_SCREENDOOR +0x4440 TX_FILTER1_0 +0x4444 TX_FILTER1_1 +0x4448 TX_FILTER1_2 +0x444C TX_FILTER1_3 +0x4450 TX_FILTER1_4 +0x4454 TX_FILTER1_5 +0x4458 TX_FILTER1_6 +0x445C TX_FILTER1_7 +0x4460 TX_FILTER1_8 +0x4464 TX_FILTER1_9 +0x4468 TX_FILTER1_10 +0x446C TX_FILTER1_11 +0x4470 TX_FILTER1_12 +0x4474 TX_FILTER1_13 +0x4478 TX_FILTER1_14 +0x447C TX_FILTER1_15 +0x4580 TX_CHROMA_KEY_0 +0x4584 TX_CHROMA_KEY_1 +0x4588 TX_CHROMA_KEY_2 +0x458C TX_CHROMA_KEY_3 +0x4590 TX_CHROMA_KEY_4 +0x4594 TX_CHROMA_KEY_5 +0x4598 TX_CHROMA_KEY_6 +0x459C TX_CHROMA_KEY_7 +0x45A0 TX_CHROMA_KEY_8 +0x45A4 TX_CHROMA_KEY_9 +0x45A8 TX_CHROMA_KEY_10 +0x45AC TX_CHROMA_KEY_11 +0x45B0 TX_CHROMA_KEY_12 +0x45B4 TX_CHROMA_KEY_13 +0x45B8 TX_CHROMA_KEY_14 +0x45BC TX_CHROMA_KEY_15 +0x45C0 TX_BORDER_COLOR_0 +0x45C4 TX_BORDER_COLOR_1 +0x45C8 TX_BORDER_COLOR_2 +0x45CC TX_BORDER_COLOR_3 +0x45D0 TX_BORDER_COLOR_4 +0x45D4 TX_BORDER_COLOR_5 +0x45D8 TX_BORDER_COLOR_6 +0x45DC TX_BORDER_COLOR_7 +0x45E0 TX_BORDER_COLOR_8 +0x45E4 TX_BORDER_COLOR_9 +0x45E8 TX_BORDER_COLOR_10 +0x45EC TX_BORDER_COLOR_11 +0x45F0 TX_BORDER_COLOR_12 +0x45F4 TX_BORDER_COLOR_13 +0x45F8 TX_BORDER_COLOR_14 +0x45FC TX_BORDER_COLOR_15 +0x4250 GA_US_VECTOR_INDEX +0x4254 GA_US_VECTOR_DATA +0x4600 US_CONFIG +0x4604 US_PIXSIZE +0x4620 US_FC_BOOL_CONST +0x4624 US_FC_CTRL +0x4630 US_CODE_ADDR +0x4634 US_CODE_RANGE +0x4638 US_CODE_OFFSET +0x46A4 US_OUT_FMT_0 +0x46A8 US_OUT_FMT_1 +0x46AC US_OUT_FMT_2 +0x46B0 US_OUT_FMT_3 +0x46B4 US_W_FMT +0x4BC0 FG_FOG_BLEND +0x4BC4 FG_FOG_FACTOR +0x4BC8 FG_FOG_COLOR_R +0x4BCC FG_FOG_COLOR_G +0x4BD0 FG_FOG_COLOR_B +0x4BD4 FG_ALPHA_FUNC +0x4BD8 FG_DEPTH_SRC +0x4C00 US_ALU_CONST_R_0 +0x4C04 US_ALU_CONST_G_0 +0x4C08 US_ALU_CONST_B_0 +0x4C0C US_ALU_CONST_A_0 +0x4C10 US_ALU_CONST_R_1 +0x4C14 US_ALU_CONST_G_1 +0x4C18 US_ALU_CONST_B_1 +0x4C1C US_ALU_CONST_A_1 +0x4C20 US_ALU_CONST_R_2 +0x4C24 US_ALU_CONST_G_2 +0x4C28 US_ALU_CONST_B_2 +0x4C2C US_ALU_CONST_A_2 +0x4C30 US_ALU_CONST_R_3 +0x4C34 US_ALU_CONST_G_3 +0x4C38 US_ALU_CONST_B_3 +0x4C3C US_ALU_CONST_A_3 +0x4C40 US_ALU_CONST_R_4 +0x4C44 US_ALU_CONST_G_4 +0x4C48 US_ALU_CONST_B_4 +0x4C4C US_ALU_CONST_A_4 +0x4C50 US_ALU_CONST_R_5 +0x4C54 US_ALU_CONST_G_5 +0x4C58 US_ALU_CONST_B_5 +0x4C5C US_ALU_CONST_A_5 +0x4C60 US_ALU_CONST_R_6 +0x4C64 US_ALU_CONST_G_6 +0x4C68 US_ALU_CONST_B_6 +0x4C6C US_ALU_CONST_A_6 +0x4C70 US_ALU_CONST_R_7 +0x4C74 US_ALU_CONST_G_7 +0x4C78 US_ALU_CONST_B_7 +0x4C7C US_ALU_CONST_A_7 +0x4C80 US_ALU_CONST_R_8 +0x4C84 US_ALU_CONST_G_8 +0x4C88 US_ALU_CONST_B_8 +0x4C8C US_ALU_CONST_A_8 +0x4C90 US_ALU_CONST_R_9 +0x4C94 US_ALU_CONST_G_9 +0x4C98 US_ALU_CONST_B_9 +0x4C9C US_ALU_CONST_A_9 +0x4CA0 US_ALU_CONST_R_10 +0x4CA4 US_ALU_CONST_G_10 +0x4CA8 US_ALU_CONST_B_10 +0x4CAC US_ALU_CONST_A_10 +0x4CB0 US_ALU_CONST_R_11 +0x4CB4 US_ALU_CONST_G_11 +0x4CB8 US_ALU_CONST_B_11 +0x4CBC US_ALU_CONST_A_11 +0x4CC0 US_ALU_CONST_R_12 +0x4CC4 US_ALU_CONST_G_12 +0x4CC8 US_ALU_CONST_B_12 +0x4CCC US_ALU_CONST_A_12 +0x4CD0 US_ALU_CONST_R_13 +0x4CD4 US_ALU_CONST_G_13 +0x4CD8 US_ALU_CONST_B_13 +0x4CDC US_ALU_CONST_A_13 +0x4CE0 US_ALU_CONST_R_14 +0x4CE4 US_ALU_CONST_G_14 +0x4CE8 US_ALU_CONST_B_14 +0x4CEC US_ALU_CONST_A_14 +0x4CF0 US_ALU_CONST_R_15 +0x4CF4 US_ALU_CONST_G_15 +0x4CF8 US_ALU_CONST_B_15 +0x4CFC US_ALU_CONST_A_15 +0x4D00 US_ALU_CONST_R_16 +0x4D04 US_ALU_CONST_G_16 +0x4D08 US_ALU_CONST_B_16 +0x4D0C US_ALU_CONST_A_16 +0x4D10 US_ALU_CONST_R_17 +0x4D14 US_ALU_CONST_G_17 +0x4D18 US_ALU_CONST_B_17 +0x4D1C US_ALU_CONST_A_17 +0x4D20 US_ALU_CONST_R_18 +0x4D24 US_ALU_CONST_G_18 +0x4D28 US_ALU_CONST_B_18 +0x4D2C US_ALU_CONST_A_18 +0x4D30 US_ALU_CONST_R_19 +0x4D34 US_ALU_CONST_G_19 +0x4D38 US_ALU_CONST_B_19 +0x4D3C US_ALU_CONST_A_19 +0x4D40 US_ALU_CONST_R_20 +0x4D44 US_ALU_CONST_G_20 +0x4D48 US_ALU_CONST_B_20 +0x4D4C US_ALU_CONST_A_20 +0x4D50 US_ALU_CONST_R_21 +0x4D54 US_ALU_CONST_G_21 +0x4D58 US_ALU_CONST_B_21 +0x4D5C US_ALU_CONST_A_21 +0x4D60 US_ALU_CONST_R_22 +0x4D64 US_ALU_CONST_G_22 +0x4D68 US_ALU_CONST_B_22 +0x4D6C US_ALU_CONST_A_22 +0x4D70 US_ALU_CONST_R_23 +0x4D74 US_ALU_CONST_G_23 +0x4D78 US_ALU_CONST_B_23 +0x4D7C US_ALU_CONST_A_23 +0x4D80 US_ALU_CONST_R_24 +0x4D84 US_ALU_CONST_G_24 +0x4D88 US_ALU_CONST_B_24 +0x4D8C US_ALU_CONST_A_24 +0x4D90 US_ALU_CONST_R_25 +0x4D94 US_ALU_CONST_G_25 +0x4D98 US_ALU_CONST_B_25 +0x4D9C US_ALU_CONST_A_25 +0x4DA0 US_ALU_CONST_R_26 +0x4DA4 US_ALU_CONST_G_26 +0x4DA8 US_ALU_CONST_B_26 +0x4DAC US_ALU_CONST_A_26 +0x4DB0 US_ALU_CONST_R_27 +0x4DB4 US_ALU_CONST_G_27 +0x4DB8 US_ALU_CONST_B_27 +0x4DBC US_ALU_CONST_A_27 +0x4DC0 US_ALU_CONST_R_28 +0x4DC4 US_ALU_CONST_G_28 +0x4DC8 US_ALU_CONST_B_28 +0x4DCC US_ALU_CONST_A_28 +0x4DD0 US_ALU_CONST_R_29 +0x4DD4 US_ALU_CONST_G_29 +0x4DD8 US_ALU_CONST_B_29 +0x4DDC US_ALU_CONST_A_29 +0x4DE0 US_ALU_CONST_R_30 +0x4DE4 US_ALU_CONST_G_30 +0x4DE8 US_ALU_CONST_B_30 +0x4DEC US_ALU_CONST_A_30 +0x4DF0 US_ALU_CONST_R_31 +0x4DF4 US_ALU_CONST_G_31 +0x4DF8 US_ALU_CONST_B_31 +0x4DFC US_ALU_CONST_A_31 +0x4E04 RB3D_BLENDCNTL_R3 +0x4E08 RB3D_ABLENDCNTL_R3 +0x4E0C RB3D_COLOR_CHANNEL_MASK +0x4E10 RB3D_CONSTANT_COLOR +0x4E14 RB3D_COLOR_CLEAR_VALUE +0x4E18 RB3D_ROPCNTL_R3 +0x4E1C RB3D_CLRCMP_FLIPE_R3 +0x4E20 RB3D_CLRCMP_CLR_R3 +0x4E24 RB3D_CLRCMP_MSK_R3 +0x4E48 RB3D_DEBUG_CTL +0x4E4C RB3D_DSTCACHE_CTLSTAT_R3 +0x4E50 RB3D_DITHER_CTL +0x4E54 RB3D_CMASK_OFFSET0 +0x4E58 RB3D_CMASK_OFFSET1 +0x4E5C RB3D_CMASK_OFFSET2 +0x4E60 RB3D_CMASK_OFFSET3 +0x4E64 RB3D_CMASK_PITCH0 +0x4E68 RB3D_CMASK_PITCH1 +0x4E6C RB3D_CMASK_PITCH2 +0x4E70 RB3D_CMASK_PITCH3 +0x4E74 RB3D_CMASK_WRINDEX +0x4E78 RB3D_CMASK_DWORD +0x4E7C RB3D_CMASK_RDINDEX +0x4E80 RB3D_AARESOLVE_OFFSET +0x4E84 RB3D_AARESOLVE_PITCH +0x4E88 RB3D_AARESOLVE_CTL +0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD +0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD +0x4EF8 RB3D_CONSTANT_COLOR_AR +0x4EFC RB3D_CONSTANT_COLOR_GB +0x4F04 ZB_ZSTENCILCNTL +0x4F08 ZB_STENCILREFMASK +0x4F14 ZB_ZTOP +0x4F18 ZB_ZCACHE_CTLSTAT +0x4F1C ZB_BW_CNTL +0x4F28 ZB_DEPTHCLEARVALUE +0x4F30 ZB_ZMASK_OFFSET +0x4F34 ZB_ZMASK_PITCH +0x4F38 ZB_ZMASK_WRINDEX +0x4F3C ZB_ZMASK_DWORD +0x4F40 ZB_ZMASK_RDINDEX +0x4F44 ZB_HIZ_OFFSET +0x4F48 ZB_HIZ_WRINDEX +0x4F4C ZB_HIZ_DWORD +0x4F50 ZB_HIZ_RDINDEX +0x4F54 ZB_HIZ_PITCH +0x4F58 ZB_ZPASS_DATA +0x4F60 ZB_DEPTHXY_OFFSET diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 31a7f66..60a194f 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c @@ -31,6 +31,7 @@ #include "radeon.h" #include "radeon_share.h" +#include "rv515_reg_safe.h" /* rv515 depends on : */ void r100_hdp_reset(struct radeon_device *rdev); int r100_cp_reset(struct radeon_device *rdev); @@ -464,72 +465,13 @@ int rv515_debugfs_ga_info_init(struct radeon_device *rdev) #endif } - /* * Asic initialization */ -static const unsigned r500_reg_safe_bm[219] = { - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF, - 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000, - 0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF, - 0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF, - 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, - 0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x0003FC01, 0x3FFFFCF8, 0xFE800B19, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, -}; - int rv515_init(struct radeon_device *rdev) { - rdev->config.r300.reg_safe_bm = r500_reg_safe_bm; - rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm); + rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; + rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); return 0; } -- cgit v0.10.2 From 4516fc0454e7ffe2f369e80045b23c2b32155004 Mon Sep 17 00:00:00 2001 From: Jeff Layton Date: Fri, 14 Aug 2009 12:57:54 -0400 Subject: sunrpc: add routine for comparing addresses lockd needs these sort of routines, as does the NFSv4 callback code. Move lockd's routines into common code and rename them so that they can be used by others. Signed-off-by: Jeff Layton Acked-by: Chuck Lever Signed-off-by: J. Bruce Fields diff --git a/fs/lockd/clntlock.c b/fs/lockd/clntlock.c index 1f3b0fc..fc9032d 100644 --- a/fs/lockd/clntlock.c +++ b/fs/lockd/clntlock.c @@ -166,7 +166,7 @@ __be32 nlmclnt_grant(const struct sockaddr *addr, const struct nlm_lock *lock) */ if (fl_blocked->fl_u.nfs_fl.owner->pid != lock->svid) continue; - if (!nlm_cmp_addr(nlm_addr(block->b_host), addr)) + if (!rpc_cmp_addr(nlm_addr(block->b_host), addr)) continue; if (nfs_compare_fh(NFS_FH(fl_blocked->fl_file->f_path.dentry->d_inode) ,fh) != 0) continue; diff --git a/fs/lockd/host.c b/fs/lockd/host.c index 7cb076a..4600c20 100644 --- a/fs/lockd/host.c +++ b/fs/lockd/host.c @@ -111,7 +111,7 @@ static struct nlm_host *nlm_lookup_host(struct nlm_lookup_host_info *ni) */ chain = &nlm_hosts[nlm_hash_address(ni->sap)]; hlist_for_each_entry(host, pos, chain, h_hash) { - if (!nlm_cmp_addr(nlm_addr(host), ni->sap)) + if (!rpc_cmp_addr(nlm_addr(host), ni->sap)) continue; /* See if we have an NSM handle for this client */ @@ -125,7 +125,7 @@ static struct nlm_host *nlm_lookup_host(struct nlm_lookup_host_info *ni) if (host->h_server != ni->server) continue; if (ni->server && - !nlm_cmp_addr(nlm_srcaddr(host), ni->src_sap)) + !rpc_cmp_addr(nlm_srcaddr(host), ni->src_sap)) continue; /* Move to head of hash chain. */ diff --git a/fs/lockd/mon.c b/fs/lockd/mon.c index 30c9331..f956651 100644 --- a/fs/lockd/mon.c +++ b/fs/lockd/mon.c @@ -209,7 +209,7 @@ static struct nsm_handle *nsm_lookup_addr(const struct sockaddr *sap) struct nsm_handle *nsm; list_for_each_entry(nsm, &nsm_handles, sm_link) - if (nlm_cmp_addr(nsm_addr(nsm), sap)) + if (rpc_cmp_addr(nsm_addr(nsm), sap)) return nsm; return NULL; } diff --git a/fs/lockd/svcsubs.c b/fs/lockd/svcsubs.c index 9e4d6aab..ad478da 100644 --- a/fs/lockd/svcsubs.c +++ b/fs/lockd/svcsubs.c @@ -417,7 +417,7 @@ EXPORT_SYMBOL_GPL(nlmsvc_unlock_all_by_sb); static int nlmsvc_match_ip(void *datap, struct nlm_host *host) { - return nlm_cmp_addr(nlm_srcaddr(host), datap); + return rpc_cmp_addr(nlm_srcaddr(host), datap); } /** diff --git a/include/linux/lockd/lockd.h b/include/linux/lockd/lockd.h index c325b18..e7a251a 100644 --- a/include/linux/lockd/lockd.h +++ b/include/linux/lockd/lockd.h @@ -338,49 +338,6 @@ static inline int nlm_privileged_requester(const struct svc_rqst *rqstp) } } -static inline int __nlm_cmp_addr4(const struct sockaddr *sap1, - const struct sockaddr *sap2) -{ - const struct sockaddr_in *sin1 = (const struct sockaddr_in *)sap1; - const struct sockaddr_in *sin2 = (const struct sockaddr_in *)sap2; - return sin1->sin_addr.s_addr == sin2->sin_addr.s_addr; -} - -#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) -static inline int __nlm_cmp_addr6(const struct sockaddr *sap1, - const struct sockaddr *sap2) -{ - const struct sockaddr_in6 *sin1 = (const struct sockaddr_in6 *)sap1; - const struct sockaddr_in6 *sin2 = (const struct sockaddr_in6 *)sap2; - return ipv6_addr_equal(&sin1->sin6_addr, &sin2->sin6_addr); -} -#else /* !(CONFIG_IPV6 || CONFIG_IPV6_MODULE) */ -static inline int __nlm_cmp_addr6(const struct sockaddr *sap1, - const struct sockaddr *sap2) -{ - return 0; -} -#endif /* !(CONFIG_IPV6 || CONFIG_IPV6_MODULE) */ - -/* - * Compare two host addresses - * - * Return TRUE if the addresses are the same; otherwise FALSE. - */ -static inline int nlm_cmp_addr(const struct sockaddr *sap1, - const struct sockaddr *sap2) -{ - if (sap1->sa_family == sap2->sa_family) { - switch (sap1->sa_family) { - case AF_INET: - return __nlm_cmp_addr4(sap1, sap2); - case AF_INET6: - return __nlm_cmp_addr6(sap1, sap2); - } - } - return 0; -} - /* * Compare two NLM locks. * When the second lock is of type F_UNLCK, this acts like a wildcard. diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h index ab3f6e9..b17df36 100644 --- a/include/linux/sunrpc/clnt.h +++ b/include/linux/sunrpc/clnt.h @@ -22,6 +22,7 @@ #include #include #include +#include struct rpc_inode; @@ -188,5 +189,52 @@ static inline void rpc_set_port(struct sockaddr *sap, #define IPV6_SCOPE_DELIMITER '%' #define IPV6_SCOPE_ID_LEN sizeof("%nnnnnnnnnn") +static inline bool __rpc_cmp_addr4(const struct sockaddr *sap1, + const struct sockaddr *sap2) +{ + const struct sockaddr_in *sin1 = (const struct sockaddr_in *)sap1; + const struct sockaddr_in *sin2 = (const struct sockaddr_in *)sap2; + + return sin1->sin_addr.s_addr == sin2->sin_addr.s_addr; +} + +#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) +static inline bool __rpc_cmp_addr6(const struct sockaddr *sap1, + const struct sockaddr *sap2) +{ + const struct sockaddr_in6 *sin1 = (const struct sockaddr_in6 *)sap1; + const struct sockaddr_in6 *sin2 = (const struct sockaddr_in6 *)sap2; + return ipv6_addr_equal(&sin1->sin6_addr, &sin2->sin6_addr); +} +#else /* !(CONFIG_IPV6 || CONFIG_IPV6_MODULE) */ +static inline bool __rpc_cmp_addr6(const struct sockaddr *sap1, + const struct sockaddr *sap2) +{ + return false; +} +#endif /* !(CONFIG_IPV6 || CONFIG_IPV6_MODULE) */ + +/** + * rpc_cmp_addr - compare the address portion of two sockaddrs. + * @sap1: first sockaddr + * @sap2: second sockaddr + * + * Just compares the family and address portion. Ignores port, scope, etc. + * Returns true if the addrs are equal, false if they aren't. + */ +static inline bool rpc_cmp_addr(const struct sockaddr *sap1, + const struct sockaddr *sap2) +{ + if (sap1->sa_family == sap2->sa_family) { + switch (sap1->sa_family) { + case AF_INET: + return __rpc_cmp_addr4(sap1, sap2); + case AF_INET6: + return __rpc_cmp_addr6(sap1, sap2); + } + } + return false; +} + #endif /* __KERNEL__ */ #endif /* _LINUX_SUNRPC_CLNT_H */ -- cgit v0.10.2 From be3ad6b0b675fd1d6b48362ca30bdee75fbef6b4 Mon Sep 17 00:00:00 2001 From: Jeff Layton Date: Fri, 14 Aug 2009 12:57:55 -0400 Subject: sunrpc: add common routine for copying address portion of a sockaddr Signed-off-by: Jeff Layton Acked-by: Chuck Lever Signed-off-by: J. Bruce Fields diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h index b17df36..044f531 100644 --- a/include/linux/sunrpc/clnt.h +++ b/include/linux/sunrpc/clnt.h @@ -198,6 +198,17 @@ static inline bool __rpc_cmp_addr4(const struct sockaddr *sap1, return sin1->sin_addr.s_addr == sin2->sin_addr.s_addr; } +static inline bool __rpc_copy_addr4(struct sockaddr *dst, + const struct sockaddr *src) +{ + const struct sockaddr_in *ssin = (struct sockaddr_in *) src; + struct sockaddr_in *dsin = (struct sockaddr_in *) dst; + + dsin->sin_family = ssin->sin_family; + dsin->sin_addr.s_addr = ssin->sin_addr.s_addr; + return true; +} + #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) static inline bool __rpc_cmp_addr6(const struct sockaddr *sap1, const struct sockaddr *sap2) @@ -206,12 +217,29 @@ static inline bool __rpc_cmp_addr6(const struct sockaddr *sap1, const struct sockaddr_in6 *sin2 = (const struct sockaddr_in6 *)sap2; return ipv6_addr_equal(&sin1->sin6_addr, &sin2->sin6_addr); } + +static inline bool __rpc_copy_addr6(struct sockaddr *dst, + const struct sockaddr *src) +{ + const struct sockaddr_in6 *ssin6 = (const struct sockaddr_in6 *) src; + struct sockaddr_in6 *dsin6 = (struct sockaddr_in6 *) dst; + + dsin6->sin6_family = ssin6->sin6_family; + ipv6_addr_copy(&dsin6->sin6_addr, &ssin6->sin6_addr); + return true; +} #else /* !(CONFIG_IPV6 || CONFIG_IPV6_MODULE) */ static inline bool __rpc_cmp_addr6(const struct sockaddr *sap1, const struct sockaddr *sap2) { return false; } + +static inline bool __rpc_copy_addr6(struct sockaddr *dst, + const struct sockaddr *src) +{ + return false; +} #endif /* !(CONFIG_IPV6 || CONFIG_IPV6_MODULE) */ /** @@ -236,5 +264,27 @@ static inline bool rpc_cmp_addr(const struct sockaddr *sap1, return false; } +/** + * rpc_copy_addr - copy the address portion of one sockaddr to another + * @dst: destination sockaddr + * @src: source sockaddr + * + * Just copies the address portion and family. Ignores port, scope, etc. + * Caller is responsible for making certain that dst is large enough to hold + * the address in src. Returns true if address family is supported. Returns + * false otherwise. + */ +static inline bool rpc_copy_addr(struct sockaddr *dst, + const struct sockaddr *src) +{ + switch (src->sa_family) { + case AF_INET: + return __rpc_copy_addr4(dst, src); + case AF_INET6: + return __rpc_copy_addr6(dst, src); + } + return false; +} + #endif /* __KERNEL__ */ #endif /* _LINUX_SUNRPC_CLNT_H */ -- cgit v0.10.2 From 363168b4ea8ec26aeb982ac6024a09f907ecd27e Mon Sep 17 00:00:00 2001 From: Jeff Layton Date: Fri, 14 Aug 2009 12:57:56 -0400 Subject: nfsd: make nfs4_client->cl_addr a struct sockaddr_storage It's currently a __be32, which isn't big enough to hold an IPv6 address. Signed-off-by: Jeff Layton Acked-by: Chuck Lever Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 9295c4b..bfc14d8 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -55,6 +55,7 @@ #include #include #include +#include #define NFSDDBG_FACILITY NFSDDBG_PROC @@ -1220,13 +1221,15 @@ nfsd4_exchange_id(struct svc_rqst *rqstp, int status; unsigned int strhashval; char dname[HEXDIR_LEN]; + char addr_str[INET6_ADDRSTRLEN]; nfs4_verifier verf = exid->verifier; - u32 ip_addr = svc_addr_in(rqstp)->sin_addr.s_addr; + struct sockaddr *sa = svc_addr(rqstp); + rpc_ntop(sa, addr_str, sizeof(addr_str)); dprintk("%s rqstp=%p exid=%p clname.len=%u clname.data=%p " - " ip_addr=%u flags %x, spa_how %d\n", + "ip_addr=%s flags %x, spa_how %d\n", __func__, rqstp, exid, exid->clname.len, exid->clname.data, - ip_addr, exid->flags, exid->spa_how); + addr_str, exid->flags, exid->spa_how); if (!check_name(exid->clname) || (exid->flags & ~EXCHGID4_FLAG_MASK_A)) return nfserr_inval; @@ -1315,7 +1318,7 @@ out_new: copy_verf(new, &verf); copy_cred(&new->cl_cred, &rqstp->rq_cred); - new->cl_addr = ip_addr; + rpc_copy_addr((struct sockaddr *) &new->cl_addr, sa); gen_clid(new); gen_confirm(new); add_to_unconfirmed(new, strhashval); @@ -1389,7 +1392,7 @@ nfsd4_create_session(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, struct nfsd4_create_session *cr_ses) { - u32 ip_addr = svc_addr_in(rqstp)->sin_addr.s_addr; + struct sockaddr *sa = svc_addr(rqstp); struct nfs4_client *conf, *unconf; struct nfsd4_clid_slot *cs_slot = NULL; int status = 0; @@ -1417,7 +1420,7 @@ nfsd4_create_session(struct svc_rqst *rqstp, cs_slot->sl_seqid++; } else if (unconf) { if (!same_creds(&unconf->cl_cred, &rqstp->rq_cred) || - (ip_addr != unconf->cl_addr)) { + !rpc_cmp_addr(sa, (struct sockaddr *) &unconf->cl_addr)) { status = nfserr_clid_inuse; goto out; } @@ -1564,7 +1567,7 @@ __be32 nfsd4_setclientid(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, struct nfsd4_setclientid *setclid) { - struct sockaddr_in *sin = svc_addr_in(rqstp); + struct sockaddr *sa = svc_addr(rqstp); struct xdr_netobj clname = { .len = setclid->se_namelen, .data = setclid->se_name, @@ -1596,8 +1599,11 @@ nfsd4_setclientid(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, /* RFC 3530 14.2.33 CASE 0: */ status = nfserr_clid_inuse; if (!same_creds(&conf->cl_cred, &rqstp->rq_cred)) { - dprintk("NFSD: setclientid: string in use by client" - " at %pI4\n", &conf->cl_addr); + char addr_str[INET6_ADDRSTRLEN]; + rpc_ntop((struct sockaddr *) &conf->cl_addr, addr_str, + sizeof(addr_str)); + dprintk("NFSD: setclientid: string in use by client " + "at %s\n", addr_str); goto out; } } @@ -1659,7 +1665,7 @@ nfsd4_setclientid(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, gen_clid(new); } copy_verf(new, &clverifier); - new->cl_addr = sin->sin_addr.s_addr; + rpc_copy_addr((struct sockaddr *) &new->cl_addr, sa); new->cl_flavor = rqstp->rq_flavor; princ = svc_gss_principal(rqstp); if (princ) { @@ -1693,7 +1699,7 @@ nfsd4_setclientid_confirm(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, struct nfsd4_setclientid_confirm *setclientid_confirm) { - struct sockaddr_in *sin = svc_addr_in(rqstp); + struct sockaddr *sa = svc_addr(rqstp); struct nfs4_client *conf, *unconf; nfs4_verifier confirm = setclientid_confirm->sc_confirm; clientid_t * clid = &setclientid_confirm->sc_clientid; @@ -1712,9 +1718,9 @@ nfsd4_setclientid_confirm(struct svc_rqst *rqstp, unconf = find_unconfirmed_client(clid); status = nfserr_clid_inuse; - if (conf && conf->cl_addr != sin->sin_addr.s_addr) + if (conf && !rpc_cmp_addr((struct sockaddr *) &conf->cl_addr, sa)) goto out; - if (unconf && unconf->cl_addr != sin->sin_addr.s_addr) + if (unconf && !rpc_cmp_addr((struct sockaddr *) &unconf->cl_addr, sa)) goto out; /* diff --git a/include/linux/nfsd/state.h b/include/linux/nfsd/state.h index 58bb197..3510ddd 100644 --- a/include/linux/nfsd/state.h +++ b/include/linux/nfsd/state.h @@ -200,7 +200,7 @@ struct nfs4_client { char cl_recdir[HEXDIR_LEN]; /* recovery dir */ nfs4_verifier cl_verifier; /* generated by client */ time_t cl_time; /* time of last lease renewal */ - __be32 cl_addr; /* client ipaddress */ + struct sockaddr_storage cl_addr; /* client ipaddress */ u32 cl_flavor; /* setclientid pseudoflavor */ char *cl_principal; /* setclientid principal name */ struct svc_cred cl_cred; /* setclientid principal */ -- cgit v0.10.2 From aa9a4ec7707a5391cde556f3fa1b0eb4bca3bcf6 Mon Sep 17 00:00:00 2001 From: Jeff Layton Date: Fri, 14 Aug 2009 12:57:57 -0400 Subject: nfsd: convert nfs4_cb_conn struct to hold address in sockaddr_storage ...rather than as a separate address and port fields. This will be necessary for implementing callbacks over IPv6. Also, convert gen_callback to use the standard rpcuaddr2sockaddr routine rather than its own private one. Signed-off-by: Jeff Layton Acked-by: Chuck Lever Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4callback.c b/fs/nfsd/nfs4callback.c index 3fd23f7..81d1c52 100644 --- a/fs/nfsd/nfs4callback.c +++ b/fs/nfsd/nfs4callback.c @@ -377,7 +377,6 @@ static int max_cb_time(void) int setup_callback_client(struct nfs4_client *clp) { - struct sockaddr_in addr; struct nfs4_cb_conn *cb = &clp->cl_cb_conn; struct rpc_timeout timeparms = { .to_initval = max_cb_time(), @@ -385,8 +384,8 @@ int setup_callback_client(struct nfs4_client *clp) }; struct rpc_create_args args = { .protocol = IPPROTO_TCP, - .address = (struct sockaddr *)&addr, - .addrsize = sizeof(addr), + .address = (struct sockaddr *) &cb->cb_addr, + .addrsize = cb->cb_addrlen, .timeout = &timeparms, .program = &cb_program, .prognumber = cb->cb_prog, @@ -400,12 +399,6 @@ int setup_callback_client(struct nfs4_client *clp) if (!clp->cl_principal && (clp->cl_flavor >= RPC_AUTH_GSS_KRB5)) return -EINVAL; - /* Initialize address */ - memset(&addr, 0, sizeof(addr)); - addr.sin_family = AF_INET; - addr.sin_port = htons(cb->cb_port); - addr.sin_addr.s_addr = htonl(cb->cb_addr); - /* Create RPC client */ client = rpc_create(&args); if (IS_ERR(client)) { diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index bfc14d8..96a7423 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -897,76 +897,6 @@ find_unconfirmed_client_by_str(const char *dname, unsigned int hashval, return NULL; } -/* a helper function for parse_callback */ -static int -parse_octet(unsigned int *lenp, char **addrp) -{ - unsigned int len = *lenp; - char *p = *addrp; - int n = -1; - char c; - - for (;;) { - if (!len) - break; - len--; - c = *p++; - if (c == '.') - break; - if ((c < '0') || (c > '9')) { - n = -1; - break; - } - if (n < 0) - n = 0; - n = (n * 10) + (c - '0'); - if (n > 255) { - n = -1; - break; - } - } - *lenp = len; - *addrp = p; - return n; -} - -/* parse and set the setclientid ipv4 callback address */ -static int -parse_ipv4(unsigned int addr_len, char *addr_val, unsigned int *cbaddrp, unsigned short *cbportp) -{ - int temp = 0; - u32 cbaddr = 0; - u16 cbport = 0; - u32 addrlen = addr_len; - char *addr = addr_val; - int i, shift; - - /* ipaddress */ - shift = 24; - for(i = 4; i > 0 ; i--) { - if ((temp = parse_octet(&addrlen, &addr)) < 0) { - return 0; - } - cbaddr |= (temp << shift); - if (shift > 0) - shift -= 8; - } - *cbaddrp = cbaddr; - - /* port */ - shift = 8; - for(i = 2; i > 0 ; i--) { - if ((temp = parse_octet(&addrlen, &addr)) < 0) { - return 0; - } - cbport |= (temp << shift); - if (shift > 0) - shift -= 8; - } - *cbportp = cbport; - return 1; -} - static void gen_callback(struct nfs4_client *clp, struct nfsd4_setclientid *se) { @@ -976,14 +906,21 @@ gen_callback(struct nfs4_client *clp, struct nfsd4_setclientid *se) if ((se->se_callback_netid_len != 3) || memcmp((char *)se->se_callback_netid_val, "tcp", 3)) goto out_err; - if ( !(parse_ipv4(se->se_callback_addr_len, se->se_callback_addr_val, - &cb->cb_addr, &cb->cb_port))) + cb->cb_addrlen = rpc_uaddr2sockaddr(se->se_callback_addr_val, + se->se_callback_addr_len, + (struct sockaddr *) &cb->cb_addr, + sizeof(cb->cb_addr)); + + if (!cb->cb_addrlen || cb->cb_addr.ss_family != AF_INET) goto out_err; + cb->cb_minorversion = 0; cb->cb_prog = se->se_callback_prog; cb->cb_ident = se->se_callback_ident; return; out_err: + cb->cb_addr.ss_family = AF_UNSPEC; + cb->cb_addrlen = 0; dprintk(KERN_INFO "NFSD: this client (clientid %08x/%08x) " "will not receive delegations\n", clp->cl_clientid.cl_boot, clp->cl_clientid.cl_id); diff --git a/include/linux/nfsd/state.h b/include/linux/nfsd/state.h index 3510ddd..fb0c404 100644 --- a/include/linux/nfsd/state.h +++ b/include/linux/nfsd/state.h @@ -81,8 +81,8 @@ struct nfs4_delegation { /* client delegation callback info */ struct nfs4_cb_conn { /* SETCLIENTID info */ - u32 cb_addr; - unsigned short cb_port; + struct sockaddr_storage cb_addr; + size_t cb_addrlen; u32 cb_prog; u32 cb_minorversion; u32 cb_ident; /* minorversion 0 only */ -- cgit v0.10.2 From 7077ecbabd626cce1fcf5cc9766c83ec04d919f9 Mon Sep 17 00:00:00 2001 From: Jeff Layton Date: Fri, 14 Aug 2009 12:57:58 -0400 Subject: nfsd: add support for NFSv4 callbacks over IPv6 The framework to add this is all in place. Now, add the code to allow support for establishing a callback channel on an IPv6 socket. Signed-off-by: Jeff Layton Acked-by: Chuck Lever Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 96a7423..9ec0ca1 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -901,9 +901,16 @@ static void gen_callback(struct nfs4_client *clp, struct nfsd4_setclientid *se) { struct nfs4_cb_conn *cb = &clp->cl_cb_conn; - - /* Currently, we only support tcp for the callback channel */ - if ((se->se_callback_netid_len != 3) || memcmp((char *)se->se_callback_netid_val, "tcp", 3)) + unsigned short expected_family; + + /* Currently, we only support tcp and tcp6 for the callback channel */ + if (se->se_callback_netid_len == 3 && + !memcmp(se->se_callback_netid_val, "tcp", 3)) + expected_family = AF_INET; + else if (se->se_callback_netid_len == 4 && + !memcmp(se->se_callback_netid_val, "tcp6", 4)) + expected_family = AF_INET6; + else goto out_err; cb->cb_addrlen = rpc_uaddr2sockaddr(se->se_callback_addr_val, @@ -911,7 +918,7 @@ gen_callback(struct nfs4_client *clp, struct nfsd4_setclientid *se) (struct sockaddr *) &cb->cb_addr, sizeof(cb->cb_addr)); - if (!cb->cb_addrlen || cb->cb_addr.ss_family != AF_INET) + if (!cb->cb_addrlen || cb->cb_addr.ss_family != expected_family) goto out_err; cb->cb_minorversion = 0; -- cgit v0.10.2 From fbf4665f41b02e757ab9d9198df65e319388e728 Mon Sep 17 00:00:00 2001 From: Jeff Layton Date: Fri, 14 Aug 2009 12:57:59 -0400 Subject: nfsd: populate sin6_scope_id on callback address with scopeid from rq_addr on SETCLIENTID call When a SETCLIENTID call comes in, one of the args given is the svc_rqst. This struct contains an rq_addr field which holds the address that sent the call. If this is an IPv6 address, then we can use the sin6_scope_id field in this address to populate the sin6_scope_id field in the callback address. AFAICT, the rq_addr.sin6_scope_id is non-zero if and only if the client mounted the server's link-local address. Signed-off-by: Jeff Layton Acked-by: Chuck Lever Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 9ec0ca1..d2a0524 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -898,7 +898,7 @@ find_unconfirmed_client_by_str(const char *dname, unsigned int hashval, } static void -gen_callback(struct nfs4_client *clp, struct nfsd4_setclientid *se) +gen_callback(struct nfs4_client *clp, struct nfsd4_setclientid *se, u32 scopeid) { struct nfs4_cb_conn *cb = &clp->cl_cb_conn; unsigned short expected_family; @@ -921,6 +921,9 @@ gen_callback(struct nfs4_client *clp, struct nfsd4_setclientid *se) if (!cb->cb_addrlen || cb->cb_addr.ss_family != expected_family) goto out_err; + if (cb->cb_addr.ss_family == AF_INET6) + ((struct sockaddr_in6 *) &cb->cb_addr)->sin6_scope_id = scopeid; + cb->cb_minorversion = 0; cb->cb_prog = se->se_callback_prog; cb->cb_ident = se->se_callback_ident; @@ -1621,7 +1624,7 @@ nfsd4_setclientid(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, } copy_cred(&new->cl_cred, &rqstp->rq_cred); gen_confirm(new); - gen_callback(new, setclid); + gen_callback(new, setclid, rpc_get_scope_id(sa)); add_to_unconfirmed(new, strhashval); setclid->se_clientid.cl_boot = new->cl_clientid.cl_boot; setclid->se_clientid.cl_id = new->cl_clientid.cl_id; diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h index 044f531..3d02558 100644 --- a/include/linux/sunrpc/clnt.h +++ b/include/linux/sunrpc/clnt.h @@ -286,5 +286,20 @@ static inline bool rpc_copy_addr(struct sockaddr *dst, return false; } +/** + * rpc_get_scope_id - return scopeid for a given sockaddr + * @sa: sockaddr to get scopeid from + * + * Returns the value of the sin6_scope_id for AF_INET6 addrs, or 0 if + * not an AF_INET6 address. + */ +static inline u32 rpc_get_scope_id(const struct sockaddr *sa) +{ + if (sa->sa_family != AF_INET6) + return 0; + + return ((struct sockaddr_in6 *) sa)->sin6_scope_id; +} + #endif /* __KERNEL__ */ #endif /* _LINUX_SUNRPC_CLNT_H */ -- cgit v0.10.2 From 8c6866b071cb242584df287dbd342e5815e8407f Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Sat, 15 Aug 2009 13:57:48 +0300 Subject: UBIFS: constify file and inode operations This patch adds 'const' qualifier to UBIFS xattr inode and file operations. Pointed-out-by: Julia Lawall Signed-off-by: Artem Bityutskiy diff --git a/fs/ubifs/xattr.c b/fs/ubifs/xattr.c index adafcf5..7998cc3 100644 --- a/fs/ubifs/xattr.c +++ b/fs/ubifs/xattr.c @@ -78,9 +78,9 @@ enum { SECURITY_XATTR, }; -static struct inode_operations none_inode_operations; +static const struct inode_operations none_inode_operations; static struct address_space_operations none_address_operations; -static struct file_operations none_file_operations; +static const struct file_operations none_file_operations; /** * create_xattr - create an extended attribute. -- cgit v0.10.2 From 071e13746f9ebb259987c71ea77f11e7656769a2 Mon Sep 17 00:00:00 2001 From: Matt Kraai Date: Sun, 23 Aug 2009 22:30:22 -0700 Subject: intel-iommu: Mark functions with __init Mark si_domain_init and iommu_prepare_static_identity_mapping with __init, to eliminate the following warnings: WARNING: drivers/pci/built-in.o(.text+0xf1f4): Section mismatch in reference from the function si_domain_init() to the function .init.text:si_domain_work_fn() The function si_domain_init() references the function __init si_domain_work_fn(). This is often because si_domain_init lacks a __init annotation or the annotation of si_domain_work_fn is wrong. WARNING: drivers/pci/built-in.o(.text+0xe340): Section mismatch in reference from the function iommu_prepare_static_identity_mapping() to the function .init.text:si_domain_init() The function iommu_prepare_static_identity_mapping() references the function __init si_domain_init(). This is often because iommu_prepare_static_identity_mapping lacks a __init annotation or the annotation of si_domain_init is wrong. Signed-off-by: Matt Kraai Signed-off-by: David Woodhouse diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index 09606e9..e67335b 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -2038,7 +2038,7 @@ static int __init si_domain_work_fn(unsigned long start_pfn, } -static int si_domain_init(int hw) +static int __init si_domain_init(int hw) { struct dmar_drhd_unit *drhd; struct intel_iommu *iommu; @@ -2167,7 +2167,7 @@ static int iommu_should_identity_map(struct pci_dev *pdev, int startup) return 1; } -static int iommu_prepare_static_identity_mapping(int hw) +static int __init iommu_prepare_static_identity_mapping(int hw) { struct pci_dev *pdev = NULL; int ret; -- cgit v0.10.2 From 94a91b5051a77d8a71d4f11a3240f0d9c51b6cf2 Mon Sep 17 00:00:00 2001 From: Donald Dutile Date: Thu, 20 Aug 2009 16:51:34 -0400 Subject: intel-iommu: iommu init error path bug fixes The kcalloc() failure path in iommu_init_domains() calls free_dmar_iommu(), which assumes that ->domains, ->domain_ids, and ->lock have been properly initialized. Add checks in free_[dmar]_iommu to not use ->domains,->domain_ids if not alloced. Move the lock init to prior to the kcalloc()'s, so it is valid in free_context_table() when free_dmar_iommu() invokes it at the end. Patch based on iommu-2.6, commit 132032274a594ee9ffb6b9c9e2e9698149a09ea9 Signed-off-by: Donald Dutile Signed-off-by: David Woodhouse diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index e67335b..beb5ccf 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -1158,6 +1158,8 @@ static int iommu_init_domains(struct intel_iommu *iommu) pr_debug("Number of Domains supportd <%ld>\n", ndomains); nlongs = BITS_TO_LONGS(ndomains); + spin_lock_init(&iommu->lock); + /* TBD: there might be 64K domains, * consider other allocation for future chip */ @@ -1170,12 +1172,9 @@ static int iommu_init_domains(struct intel_iommu *iommu) GFP_KERNEL); if (!iommu->domains) { printk(KERN_ERR "Allocating domain array failed\n"); - kfree(iommu->domain_ids); return -ENOMEM; } - spin_lock_init(&iommu->lock); - /* * if Caching mode is set, then invalid translations are tagged * with domainid 0. Hence we need to pre-allocate it. @@ -1195,22 +1194,24 @@ void free_dmar_iommu(struct intel_iommu *iommu) int i; unsigned long flags; - i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap)); - for (; i < cap_ndoms(iommu->cap); ) { - domain = iommu->domains[i]; - clear_bit(i, iommu->domain_ids); + if ((iommu->domains) && (iommu->domain_ids)) { + i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap)); + for (; i < cap_ndoms(iommu->cap); ) { + domain = iommu->domains[i]; + clear_bit(i, iommu->domain_ids); + + spin_lock_irqsave(&domain->iommu_lock, flags); + if (--domain->iommu_count == 0) { + if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) + vm_domain_exit(domain); + else + domain_exit(domain); + } + spin_unlock_irqrestore(&domain->iommu_lock, flags); - spin_lock_irqsave(&domain->iommu_lock, flags); - if (--domain->iommu_count == 0) { - if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) - vm_domain_exit(domain); - else - domain_exit(domain); + i = find_next_bit(iommu->domain_ids, + cap_ndoms(iommu->cap), i+1); } - spin_unlock_irqrestore(&domain->iommu_lock, flags); - - i = find_next_bit(iommu->domain_ids, - cap_ndoms(iommu->cap), i+1); } if (iommu->gcmd & DMA_GCMD_TE) -- cgit v0.10.2 From 8f55f3c0a013c42fb733997da54a3326c74601e8 Mon Sep 17 00:00:00 2001 From: Alexandros Batsakis Date: Thu, 20 Aug 2009 03:34:19 +0300 Subject: nfsd41: sunrpc: svc_tcp_recv_record() Factor functionality out of svc_tcp_recvfrom() to simplify routine Signed-off-by: Alexandros Batsakis Signed-off-by: Ricardo Labiaga Signed-off-by: Benny Halevy Signed-off-by: J. Bruce Fields diff --git a/net/sunrpc/svcsock.c b/net/sunrpc/svcsock.c index 99a826d..76a380d 100644 --- a/net/sunrpc/svcsock.c +++ b/net/sunrpc/svcsock.c @@ -854,21 +854,15 @@ failed: } /* - * Receive data from a TCP socket. + * Receive data. + * If we haven't gotten the record length yet, get the next four bytes. + * Otherwise try to gobble up as much as possible up to the complete + * record length. */ -static int svc_tcp_recvfrom(struct svc_rqst *rqstp) +static int svc_tcp_recv_record(struct svc_sock *svsk, struct svc_rqst *rqstp) { - struct svc_sock *svsk = - container_of(rqstp->rq_xprt, struct svc_sock, sk_xprt); struct svc_serv *serv = svsk->sk_xprt.xpt_server; - int len; - struct kvec *vec; - int pnum, vlen; - - dprintk("svc: tcp_recv %p data %d conn %d close %d\n", - svsk, test_bit(XPT_DATA, &svsk->sk_xprt.xpt_flags), - test_bit(XPT_CONN, &svsk->sk_xprt.xpt_flags), - test_bit(XPT_CLOSE, &svsk->sk_xprt.xpt_flags)); + int len; if (test_and_clear_bit(XPT_CHNGBUF, &svsk->sk_xprt.xpt_flags)) /* sndbuf needs to have room for one request @@ -889,10 +883,6 @@ static int svc_tcp_recvfrom(struct svc_rqst *rqstp) clear_bit(XPT_DATA, &svsk->sk_xprt.xpt_flags); - /* Receive data. If we haven't got the record length yet, get - * the next four bytes. Otherwise try to gobble up as much as - * possible up to the complete record length. - */ if (svsk->sk_tcplen < sizeof(rpc_fraghdr)) { int want = sizeof(rpc_fraghdr) - svsk->sk_tcplen; struct kvec iov; @@ -907,7 +897,7 @@ static int svc_tcp_recvfrom(struct svc_rqst *rqstp) dprintk("svc: short recvfrom while reading record " "length (%d of %d)\n", len, want); svc_xprt_received(&svsk->sk_xprt); - return -EAGAIN; /* record header not complete */ + goto err_again; /* record header not complete */ } svsk->sk_reclen = ntohl(svsk->sk_reclen); @@ -922,6 +912,7 @@ static int svc_tcp_recvfrom(struct svc_rqst *rqstp) "per record not supported\n"); goto err_delete; } + svsk->sk_reclen &= RPC_FRAGMENT_SIZE_MASK; dprintk("svc: TCP record, %d bytes\n", svsk->sk_reclen); if (svsk->sk_reclen > serv->sv_max_mesg) { @@ -942,11 +933,45 @@ static int svc_tcp_recvfrom(struct svc_rqst *rqstp) dprintk("svc: incomplete TCP record (%d of %d)\n", len, svsk->sk_reclen); svc_xprt_received(&svsk->sk_xprt); - return -EAGAIN; /* record not complete */ + goto err_again; /* record not complete */ } len = svsk->sk_reclen; set_bit(XPT_DATA, &svsk->sk_xprt.xpt_flags); + return len; + error: + if (len == -EAGAIN) { + dprintk("RPC: TCP recv_record got EAGAIN\n"); + svc_xprt_received(&svsk->sk_xprt); + } + return len; + err_delete: + set_bit(XPT_CLOSE, &svsk->sk_xprt.xpt_flags); + err_again: + return -EAGAIN; +} + +/* + * Receive data from a TCP socket. + */ +static int svc_tcp_recvfrom(struct svc_rqst *rqstp) +{ + struct svc_sock *svsk = + container_of(rqstp->rq_xprt, struct svc_sock, sk_xprt); + struct svc_serv *serv = svsk->sk_xprt.xpt_server; + int len; + struct kvec *vec; + int pnum, vlen; + + dprintk("svc: tcp_recv %p data %d conn %d close %d\n", + svsk, test_bit(XPT_DATA, &svsk->sk_xprt.xpt_flags), + test_bit(XPT_CONN, &svsk->sk_xprt.xpt_flags), + test_bit(XPT_CLOSE, &svsk->sk_xprt.xpt_flags)); + + len = svc_tcp_recv_record(svsk, rqstp); + if (len < 0) + goto error; + vec = rqstp->rq_vec; vec[0] = rqstp->rq_arg.head[0]; vlen = PAGE_SIZE; @@ -962,7 +987,7 @@ static int svc_tcp_recvfrom(struct svc_rqst *rqstp) /* Now receive data */ len = svc_recvfrom(rqstp, vec, pnum, len); if (len < 0) - goto error; + goto err_again; dprintk("svc: TCP complete record (%d bytes)\n", len); rqstp->rq_arg.len = len; @@ -988,21 +1013,19 @@ static int svc_tcp_recvfrom(struct svc_rqst *rqstp) return len; - err_delete: - set_bit(XPT_CLOSE, &svsk->sk_xprt.xpt_flags); - return -EAGAIN; - - error: +err_again: if (len == -EAGAIN) { dprintk("RPC: TCP recvfrom got EAGAIN\n"); svc_xprt_received(&svsk->sk_xprt); - } else { + return len; + } +error: + if (len != -EAGAIN) { printk(KERN_NOTICE "%s: recvfrom returned errno %d\n", svsk->sk_xprt.xpt_server->sv_name, -len); - goto err_delete; + set_bit(XPT_CLOSE, &svsk->sk_xprt.xpt_flags); } - - return len; + return -EAGAIN; } /* -- cgit v0.10.2 From 55bb55dca0cecac2fb7b8c743db41361c011c8a8 Mon Sep 17 00:00:00 2001 From: Frank Filz Date: Fri, 14 Aug 2009 15:02:30 -0700 Subject: nfsd: Fix unnecessary deny bits in NFSv4 ACL The group deny entries end up denying tcy even though tcy was just allowed by the allow entry. This appears to be due to: ace->access_mask = mask_from_posix(deny, flags); instead of: ace->access_mask = deny_mask_from_posix(deny, flags); Denying a previously allowed bit has no effect, so this shouldn't affect behavior, but it's ugly. Signed-off-by: Frank Filz Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4acl.c b/fs/nfsd/nfs4acl.c index 54b8b41..5320c2b 100644 --- a/fs/nfsd/nfs4acl.c +++ b/fs/nfsd/nfs4acl.c @@ -335,7 +335,7 @@ _posix_to_nfsv4_one(struct posix_acl *pacl, struct nfs4_acl *acl, if (deny) { ace->type = NFS4_ACE_ACCESS_DENIED_ACE_TYPE; ace->flag = eflag | NFS4_ACE_IDENTIFIER_GROUP; - ace->access_mask = mask_from_posix(deny, flags); + ace->access_mask = deny_mask_from_posix(deny, flags); ace->whotype = NFS4_ACL_WHO_NAMED; ace->who = pa->e_id; ace++; -- cgit v0.10.2 From ed2d8aed52212610d4cb79be3cbf535b04be38dc Mon Sep 17 00:00:00 2001 From: Ryusei Yamaguchi Date: Sun, 16 Aug 2009 00:54:41 +0900 Subject: knfsd: Replace lock_kernel with a mutex in nfsd pool stats. lock_kernel() in knfsd was replaced with a mutex. The later commit 03cf6c9f49a8fea953d38648d016e3f46e814991 ("knfsd: add file to export stats about nfsd pools") did not follow that change. This patch fixes the issue. Also move the get and put of nfsd_serv to the open and close methods (instead of start and stop methods) to allow atomic check and increment of reference count in the open method (where we can still return an error). Signed-off-by: Ryusei Yamaguchi Signed-off-by: Isaku Yamahata Signed-off-by: YOSHIFUJI Hideaki Cc: Greg Banks Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfsctl.c b/fs/nfsd/nfsctl.c index b764d7d..00388d2 100644 --- a/fs/nfsd/nfsctl.c +++ b/fs/nfsd/nfsctl.c @@ -174,12 +174,13 @@ static const struct file_operations exports_operations = { }; extern int nfsd_pool_stats_open(struct inode *inode, struct file *file); +extern int nfsd_pool_stats_release(struct inode *inode, struct file *file); static struct file_operations pool_stats_operations = { .open = nfsd_pool_stats_open, .read = seq_read, .llseek = seq_lseek, - .release = seq_release, + .release = nfsd_pool_stats_release, .owner = THIS_MODULE, }; diff --git a/fs/nfsd/nfssvc.c b/fs/nfsd/nfssvc.c index d68cd05..675d395 100644 --- a/fs/nfsd/nfssvc.c +++ b/fs/nfsd/nfssvc.c @@ -34,6 +34,7 @@ #include #include #include +#include #define NFSDDBG_FACILITY NFSDDBG_SVC @@ -614,7 +615,25 @@ nfsd_dispatch(struct svc_rqst *rqstp, __be32 *statp) int nfsd_pool_stats_open(struct inode *inode, struct file *file) { - if (nfsd_serv == NULL) + int ret; + mutex_lock(&nfsd_mutex); + if (nfsd_serv == NULL) { + mutex_unlock(&nfsd_mutex); return -ENODEV; - return svc_pool_stats_open(nfsd_serv, file); + } + /* bump up the psudo refcount while traversing */ + svc_get(nfsd_serv); + ret = svc_pool_stats_open(nfsd_serv, file); + mutex_unlock(&nfsd_mutex); + return ret; +} + +int nfsd_pool_stats_release(struct inode *inode, struct file *file) +{ + int ret = seq_release(inode, file); + mutex_lock(&nfsd_mutex); + /* this function really, really should have been called svc_put() */ + svc_destroy(nfsd_serv); + mutex_unlock(&nfsd_mutex); + return ret; } diff --git a/net/sunrpc/svc_xprt.c b/net/sunrpc/svc_xprt.c index 27d4433..dcd2d1e 100644 --- a/net/sunrpc/svc_xprt.c +++ b/net/sunrpc/svc_xprt.c @@ -1166,11 +1166,6 @@ static void *svc_pool_stats_start(struct seq_file *m, loff_t *pos) dprintk("svc_pool_stats_start, *pidx=%u\n", pidx); - lock_kernel(); - /* bump up the pseudo refcount while traversing */ - svc_get(serv); - unlock_kernel(); - if (!pidx) return SEQ_START_TOKEN; return (pidx > serv->sv_nrpools ? NULL : &serv->sv_pools[pidx-1]); @@ -1198,12 +1193,6 @@ static void *svc_pool_stats_next(struct seq_file *m, void *p, loff_t *pos) static void svc_pool_stats_stop(struct seq_file *m, void *p) { - struct svc_serv *serv = m->private; - - lock_kernel(); - /* this function really, really should have been called svc_put() */ - svc_destroy(serv); - unlock_kernel(); } static int svc_pool_stats_show(struct seq_file *m, void *p) -- cgit v0.10.2 From eac81736e6884484ebb45f8d0cba639f3285382b Mon Sep 17 00:00:00 2001 From: Wei Yongjun Date: Tue, 4 Aug 2009 17:27:52 +0800 Subject: sunrpc: reply AUTH_BADCRED to RPCSEC_GSS with unknown service When an RPC message is received with RPCSEC_GSS with an unknown service (not RPC_GSS_SVC_NONE, RPC_GSS_SVC_INTEGRITY, or RPC_GSS_SVC_PRIVACY), svcauth_gss_accept() returns AUTH_BADCRED, but svcauth_gss_release() subsequently drops the response entirely, discarding the error. Fix that so the AUTH_BADCRED error is returned to the client. Signed-off-by: Wei Yongjun Signed-off-by: J. Bruce Fields diff --git a/net/sunrpc/auth_gss/svcauth_gss.c b/net/sunrpc/auth_gss/svcauth_gss.c index 2e6a148..f6c51e5 100644 --- a/net/sunrpc/auth_gss/svcauth_gss.c +++ b/net/sunrpc/auth_gss/svcauth_gss.c @@ -1374,8 +1374,10 @@ svcauth_gss_release(struct svc_rqst *rqstp) if (stat) goto out_err; break; - default: - goto out_err; + /* + * For any other gc_svc value, svcauth_gss_accept() already set + * the auth_error appropriately; just fall through: + */ } out: -- cgit v0.10.2 From 2ff729f5445cc47d1910386c36e53fc6b1c5e47a Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Wed, 26 Aug 2009 14:25:41 +0100 Subject: intel-iommu: Cope with yet another BIOS screwup causing crashes Signed-off-by: David Woodhouse diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index beb5ccf..d36fa80 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -1974,6 +1974,17 @@ static int iommu_prepare_identity_map(struct pci_dev *pdev, printk(KERN_INFO "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n", pci_name(pdev), start, end); + + if (end >> agaw_to_width(domain->agaw)) { + WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n" + "BIOS vendor: %s; Ver: %s; Product Version: %s\n", + agaw_to_width(domain->agaw), + dmi_get_system_info(DMI_BIOS_VENDOR), + dmi_get_system_info(DMI_BIOS_VERSION), + dmi_get_system_info(DMI_PRODUCT_VERSION)); + ret = -EIO; + goto error; + } ret = iommu_domain_identity_map(domain, start, end); if (ret) -- cgit v0.10.2 From c9c97b8c75019814d8c007059bc827bb475be917 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 27 Aug 2009 09:53:47 +1000 Subject: drm/ttm: consolidate cache flushing code in one place. This merges the TTM and drm cache flushing into one file in the drm core. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 0e994a0..3a5575e 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -45,25 +45,58 @@ drm_clflush_page(struct page *page) clflush(page_virtual + i); kunmap_atomic(page_virtual, KM_USER0); } -#endif +static void drm_cache_flush_clflush(struct page *pages[], + unsigned long num_pages) +{ + unsigned long i; + + mb(); + for (i = 0; i < num_pages; i++) + drm_clflush_page(*pages++); + mb(); +} + +static void +drm_clflush_ipi_handler(void *null) +{ + wbinvd(); +} +#elif !defined(__powerpc__) +static void drm_cache_ipi_handler(void *dummy) +{ +} +#endif void drm_clflush_pages(struct page *pages[], unsigned long num_pages) { #if defined(CONFIG_X86) if (cpu_has_clflush) { - unsigned long i; - - mb(); - for (i = 0; i < num_pages; ++i) - drm_clflush_page(*pages++); - mb(); - + drm_cache_flush_clflush(pages, num_pages); return; } - wbinvd(); + if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) + printk(KERN_ERR "Timed out waiting for cache flush.\n"); + +#elif defined(__powerpc__) + unsigned long i; + for (i = 0; i < num_pages; i++) { + struct page *page = pages[i]; + void *page_virtual; + + if (unlikely(page == NULL)) + continue; + + page_virtual = kmap_atomic(page, KM_USER0); + flush_dcache_range((unsigned long)page_virtual, + (unsigned long)page_virtual + PAGE_SIZE); + kunmap_atomic(page_virtual, KM_USER0); + } +#else + if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) + printk(KERN_ERR "Timed out waiting for drm cache flush\n"); #endif } EXPORT_SYMBOL(drm_clflush_pages); diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 42cca55..a55ee1a 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -34,76 +34,13 @@ #include #include #include +#include "drm_cache.h" #include "ttm/ttm_module.h" #include "ttm/ttm_bo_driver.h" #include "ttm/ttm_placement.h" static int ttm_tt_swapin(struct ttm_tt *ttm); -#if defined(CONFIG_X86) -static void ttm_tt_clflush_page(struct page *page) -{ - uint8_t *page_virtual; - unsigned int i; - - if (unlikely(page == NULL)) - return; - - page_virtual = kmap_atomic(page, KM_USER0); - - for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size) - clflush(page_virtual + i); - - kunmap_atomic(page_virtual, KM_USER0); -} - -static void ttm_tt_cache_flush_clflush(struct page *pages[], - unsigned long num_pages) -{ - unsigned long i; - - mb(); - for (i = 0; i < num_pages; ++i) - ttm_tt_clflush_page(*pages++); - mb(); -} -#elif !defined(__powerpc__) -static void ttm_tt_ipi_handler(void *null) -{ - ; -} -#endif - -void ttm_tt_cache_flush(struct page *pages[], unsigned long num_pages) -{ - -#if defined(CONFIG_X86) - if (cpu_has_clflush) { - ttm_tt_cache_flush_clflush(pages, num_pages); - return; - } -#elif defined(__powerpc__) - unsigned long i; - - for (i = 0; i < num_pages; ++i) { - struct page *page = pages[i]; - void *page_virtual; - - if (unlikely(page == NULL)) - continue; - - page_virtual = kmap_atomic(page, KM_USER0); - flush_dcache_range((unsigned long) page_virtual, - (unsigned long) page_virtual + PAGE_SIZE); - kunmap_atomic(page_virtual, KM_USER0); - } -#else - if (on_each_cpu(ttm_tt_ipi_handler, NULL, 1) != 0) - printk(KERN_ERR TTM_PFX - "Timed out waiting for drm cache flush.\n"); -#endif -} - /** * Allocates storage for pointers to the pages that back the ttm. * @@ -302,7 +239,7 @@ static int ttm_tt_set_caching(struct ttm_tt *ttm, } if (ttm->caching_state == tt_cached) - ttm_tt_cache_flush(ttm->pages, ttm->num_pages); + drm_clflush_pages(ttm->pages, ttm->num_pages); for (i = 0; i < ttm->num_pages; ++i) { cur_page = ttm->pages[i]; diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h new file mode 100644 index 0000000..7bfb063 --- /dev/null +++ b/include/drm/drm_cache.h @@ -0,0 +1,38 @@ +/************************************************************************** + * + * Copyright 2009 Red Hat Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * + **************************************************************************/ +/* + * Authors: + * Dave Airlie + */ + +#ifndef _DRM_CACHE_H_ +#define _DRM_CACHE_H_ + +void drm_clflush_pages(struct page *pages[], unsigned long num_pages); + +#endif -- cgit v0.10.2 From ece2be7993cc5e269cbf0cad6442b401a2c31915 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Sun, 23 Aug 2009 18:34:25 +0100 Subject: drm/mga: Use request_firmware() to load microcode Image format is IHEX, one record for each pipe in order (record addresses are ignored). Signed-off-by: Ben Hutchings Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 39b393d..10edc9b 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -116,6 +116,7 @@ endchoice config DRM_MGA tristate "Matrox g200/g400" depends on DRM + select FW_LOADER help Choose this option if you have a Matrox G200, G400 or G450 graphics card. If M is selected, the module will be called mga. AGP diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c index 6c67a02..3c917fb 100644 --- a/drivers/gpu/drm/mga/mga_dma.c +++ b/drivers/gpu/drm/mga/mga_dma.c @@ -444,7 +444,7 @@ static int mga_do_agp_dma_bootstrap(struct drm_device * dev, { drm_mga_private_t *const dev_priv = (drm_mga_private_t *) dev->dev_private; - unsigned int warp_size = mga_warp_microcode_size(dev_priv); + unsigned int warp_size = MGA_WARP_UCODE_SIZE; int err; unsigned offset; const unsigned secondary_size = dma_bs->secondary_bin_count @@ -619,7 +619,7 @@ static int mga_do_pci_dma_bootstrap(struct drm_device * dev, { drm_mga_private_t *const dev_priv = (drm_mga_private_t *) dev->dev_private; - unsigned int warp_size = mga_warp_microcode_size(dev_priv); + unsigned int warp_size = MGA_WARP_UCODE_SIZE; unsigned int primary_size; unsigned int bin_count; int err; diff --git a/drivers/gpu/drm/mga/mga_drv.h b/drivers/gpu/drm/mga/mga_drv.h index 3d264f28..be6c6b9 100644 --- a/drivers/gpu/drm/mga/mga_drv.h +++ b/drivers/gpu/drm/mga/mga_drv.h @@ -177,7 +177,6 @@ extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf); /* mga_warp.c */ -extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv); extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv); extern int mga_warp_init(drm_mga_private_t * dev_priv); diff --git a/drivers/gpu/drm/mga/mga_ucode.h b/drivers/gpu/drm/mga/mga_ucode.h deleted file mode 100644 index b611e27..0000000 --- a/drivers/gpu/drm/mga/mga_ucode.h +++ /dev/null @@ -1,11645 +0,0 @@ -/* mga_ucode.h -- Matrox G200/G400 WARP engine microcode -*- linux-c -*- - * Created: Thu Jan 11 21:20:43 2001 by gareth@valinux.com - * - * Copyright 1999 Matrox Graphics Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE - * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Kernel-based WARP engine management: - * Gareth Hughes - */ - -/* - * WARP pipes are named according to the functions they perform, where: - * - * - T stands for computation of texture stage 0 - * - T2 stands for computation of both texture stage 0 and texture stage 1 - * - G stands for computation of triangle intensity (Gouraud interpolation) - * - Z stands for computation of Z buffer interpolation - * - S stands for computation of specular highlight - * - A stands for computation of the alpha channel - * - F stands for computation of vertex fog interpolation - */ - -static unsigned char warp_g200_tgz[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x72, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x60, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x03, 0x80, 0x0A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x57, 0x39, 0x20, 0xE9, - 0x28, 0x19, 0x60, 0xEC, - - 0x2B, 0x32, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0xB3, 0x05, - 0x00, 0xE0, - 0x16, 0x28, 0x20, 0xE9, - - 0x23, 0x3B, 0x33, 0xAD, - 0x1E, 0x2B, 0x20, 0xE9, - - 0x1C, 0x80, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x85, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x84, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x82, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x7F, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgza[] = { - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x7D, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x6B, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x2D, 0x44, 0x4C, 0xB6, - 0x25, 0x44, 0x54, 0xB6, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x2D, 0x20, - 0x25, 0x20, - 0x07, 0xC0, 0x44, 0xC6, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x1F, 0x62, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x3F, 0x3D, 0x5D, 0x9F, - 0x00, 0xE0, - 0x07, 0x20, - - 0x00, 0x80, 0x00, 0xE8, - 0x28, 0x19, 0x60, 0xEC, - - 0xB3, 0x05, - 0x00, 0xE0, - 0x00, 0x80, 0x00, 0xE8, - - 0x23, 0x3B, 0x33, 0xAD, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0x26, 0x1F, 0xDF, - 0x9D, 0x1F, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x9E, 0x3F, 0x4F, 0xE9, - - 0x07, 0x07, 0x1F, 0xAF, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x9C, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x7A, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x79, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x77, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x74, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgzaf[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x83, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x21, 0x45, 0x80, 0xE8, - 0x1A, 0x4D, 0x80, 0xE8, - - 0x31, 0x55, 0x80, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x6F, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0D, 0x21, 0x1A, 0xB6, - 0x05, 0x21, 0x31, 0xB6, - - 0x2D, 0x44, 0x4C, 0xB6, - 0x25, 0x44, 0x54, 0xB6, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x0D, 0x20, - 0x05, 0x20, - 0x2F, 0xC0, 0x21, 0xC6, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x00, 0xE0, - 0x25, 0x20, - 0x07, 0xC0, 0x44, 0xC6, - - 0x17, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x2D, 0x20, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0xE0, - 0x2F, 0x20, - - 0x1F, 0x62, 0x57, 0x9F, - 0x00, 0xE0, - 0x07, 0x20, - - 0x3F, 0x3D, 0x5D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x28, 0x19, 0x60, 0xEC, - - 0xB3, 0x05, - 0x00, 0xE0, - 0x17, 0x26, 0x17, 0xDF, - - 0x23, 0x3B, 0x33, 0xAD, - 0x35, 0x17, 0x4F, 0xE9, - - 0x1F, 0x26, 0x1F, 0xDF, - 0x9D, 0x1F, 0x4F, 0xE9, - - 0x9E, 0x3F, 0x4F, 0xE9, - 0x39, 0x37, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x17, 0xAF, - 0x00, 0x80, 0x00, 0xE8, - - 0x07, 0x07, 0x1F, 0xAF, - 0x00, 0x80, 0x00, 0xE8, - - 0x31, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x9C, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x74, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x73, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x71, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x6E, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgzf[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x7F, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x21, 0x45, 0x80, 0xE8, - 0x1A, 0x4D, 0x80, 0xE8, - - 0x31, 0x55, 0x80, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x6B, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0D, 0x21, 0x1A, 0xB6, - 0x05, 0x21, 0x31, 0xB6, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x0D, 0x20, - 0x05, 0x20, - 0x2F, 0xC0, 0x21, 0xC6, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x17, 0x50, 0x56, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0xE0, - 0x2F, 0x20, - - 0x00, 0x80, 0x00, 0xE8, - 0x28, 0x19, 0x60, 0xEC, - - 0xB3, 0x05, - 0x00, 0xE0, - 0x00, 0x80, 0x00, 0xE8, - - 0x23, 0x3B, 0x33, 0xAD, - 0x00, 0x80, 0x00, 0xE8, - - 0x17, 0x26, 0x17, 0xDF, - 0x35, 0x17, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x39, 0x37, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x17, 0xAF, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x31, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x78, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x77, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x75, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x72, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgzs[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x8B, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x21, 0x45, 0x80, 0xE8, - 0x1A, 0x4D, 0x80, 0xE8, - - 0x31, 0x55, 0x80, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x77, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x2D, 0x21, 0x1A, 0xB0, - 0x25, 0x21, 0x31, 0xB0, - - 0x0D, 0x21, 0x1A, 0xB2, - 0x05, 0x21, 0x31, 0xB2, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x2D, 0x20, - 0x25, 0x20, - 0x05, 0x20, - 0x0D, 0x20, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x2F, 0xC0, 0x21, 0xC0, - - 0x16, 0x42, 0x56, 0x9F, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x1E, 0x62, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x21, 0x31, 0xB4, - 0x2D, 0x21, 0x1A, 0xB4, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0x05, - 0x00, 0xE0, - 0x28, 0x19, 0x60, 0xEC, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0xE0, - 0x2F, 0x20, - - 0x23, 0x3B, 0x33, 0xAD, - 0x1E, 0x26, 0x1E, 0xDF, - - 0xA7, 0x1E, 0x4F, 0xE9, - 0x17, 0x26, 0x16, 0xDF, - - 0x2D, 0x20, - 0x00, 0xE0, - 0xA8, 0x3F, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x1E, 0xAF, - 0x25, 0x20, - 0x00, 0xE0, - - 0xA4, 0x16, 0x4F, 0xE9, - 0x0F, 0xC0, 0x21, 0xC2, - - 0xA6, 0x80, 0x4F, 0xE9, - 0x1F, 0x62, 0x57, 0x9F, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0xE0, - 0x8F, 0x20, - - 0xA5, 0x37, 0x4F, 0xE9, - 0x0F, 0x17, 0x0F, 0xAF, - - 0x06, 0xC0, 0x21, 0xC4, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0xA3, 0x80, 0x4F, 0xE9, - - 0x06, 0x20, - 0x00, 0xE0, - 0x1F, 0x26, 0x1F, 0xDF, - - 0xA1, 0x1F, 0x4F, 0xE9, - 0xA2, 0x3F, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x06, 0x06, 0x1F, 0xAF, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x6C, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x6B, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x69, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgzsa[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x8F, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x21, 0x45, 0x80, 0xE8, - 0x1A, 0x4D, 0x80, 0xE8, - - 0x31, 0x55, 0x80, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x7B, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x2D, 0x21, 0x1A, 0xB0, - 0x25, 0x21, 0x31, 0xB0, - - 0x0D, 0x21, 0x1A, 0xB2, - 0x05, 0x21, 0x31, 0xB2, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x2D, 0x20, - 0x25, 0x20, - 0x05, 0x20, - 0x0D, 0x20, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x2F, 0xC0, 0x21, 0xC0, - - 0x16, 0x42, 0x56, 0x9F, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x1E, 0x62, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x21, 0x31, 0xB4, - 0x2D, 0x21, 0x1A, 0xB4, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0x05, - 0x00, 0xE0, - 0x28, 0x19, 0x60, 0xEC, - - 0x0D, 0x44, 0x4C, 0xB6, - 0x05, 0x44, 0x54, 0xB6, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0xE0, - 0x2F, 0x20, - - 0x23, 0x3B, 0x33, 0xAD, - 0x1E, 0x26, 0x1E, 0xDF, - - 0xA7, 0x1E, 0x4F, 0xE9, - 0x17, 0x26, 0x16, 0xDF, - - 0x2D, 0x20, - 0x00, 0xE0, - 0xA8, 0x3F, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x1E, 0xAF, - 0x25, 0x20, - 0x00, 0xE0, - - 0xA4, 0x16, 0x4F, 0xE9, - 0x0F, 0xC0, 0x21, 0xC2, - - 0xA6, 0x80, 0x4F, 0xE9, - 0x1F, 0x62, 0x57, 0x9F, - - 0x0D, 0x20, - 0x05, 0x20, - 0x00, 0x80, 0x00, 0xE8, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0xE0, - 0x0F, 0x20, - - 0x17, 0x50, 0x56, 0x9F, - 0xA5, 0x37, 0x4F, 0xE9, - - 0x06, 0xC0, 0x21, 0xC4, - 0x0F, 0x17, 0x0F, 0xAF, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x2F, 0xC0, 0x44, 0xC6, - 0xA3, 0x80, 0x4F, 0xE9, - - 0x06, 0x20, - 0x00, 0xE0, - 0x1F, 0x26, 0x1F, 0xDF, - - 0x17, 0x26, 0x17, 0xDF, - 0x9D, 0x17, 0x4F, 0xE9, - - 0xA1, 0x1F, 0x4F, 0xE9, - 0xA2, 0x3F, 0x4F, 0xE9, - - 0x06, 0x06, 0x1F, 0xAF, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x9E, 0x37, 0x4F, 0xE9, - 0x2F, 0x17, 0x2F, 0xAF, - - 0xA0, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x9C, 0x80, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x68, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x67, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x65, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x62, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgzsaf[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x94, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x21, 0x45, 0x80, 0xE8, - 0x1A, 0x4D, 0x80, 0xE8, - - 0x31, 0x55, 0x80, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x80, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x2D, 0x21, 0x1A, 0xB0, - 0x25, 0x21, 0x31, 0xB0, - - 0x0D, 0x21, 0x1A, 0xB2, - 0x05, 0x21, 0x31, 0xB2, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x2D, 0x20, - 0x25, 0x20, - 0x05, 0x20, - 0x0D, 0x20, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x2F, 0xC0, 0x21, 0xC0, - - 0x16, 0x42, 0x56, 0x9F, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x1E, 0x62, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x21, 0x31, 0xB4, - 0x2D, 0x21, 0x1A, 0xB4, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0x05, - 0x00, 0xE0, - 0x28, 0x19, 0x60, 0xEC, - - 0x0D, 0x21, 0x1A, 0xB6, - 0x05, 0x21, 0x31, 0xB6, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0xE0, - 0x2F, 0x20, - - 0x23, 0x3B, 0x33, 0xAD, - 0x1E, 0x26, 0x1E, 0xDF, - - 0xA7, 0x1E, 0x4F, 0xE9, - 0x17, 0x26, 0x16, 0xDF, - - 0x2D, 0x20, - 0x00, 0xE0, - 0xA8, 0x3F, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x1E, 0xAF, - 0x25, 0x20, - 0x00, 0xE0, - - 0xA4, 0x16, 0x4F, 0xE9, - 0x0F, 0xC0, 0x21, 0xC2, - - 0xA6, 0x80, 0x4F, 0xE9, - 0x1F, 0x62, 0x57, 0x9F, - - 0x0D, 0x20, - 0x05, 0x20, - 0x2F, 0xC0, 0x21, 0xC6, - - 0x2D, 0x44, 0x4C, 0xB6, - 0x25, 0x44, 0x54, 0xB6, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0xE0, - 0x0F, 0x20, - - 0x2D, 0x20, - 0x25, 0x20, - 0x07, 0xC0, 0x44, 0xC6, - - 0x17, 0x50, 0x56, 0x9F, - 0xA5, 0x37, 0x4F, 0xE9, - - 0x06, 0xC0, 0x21, 0xC4, - 0x0F, 0x17, 0x0F, 0xAF, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x1E, 0x62, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x3E, 0x3D, 0x5D, 0x9F, - 0x00, 0xE0, - 0x07, 0x20, - - 0x2F, 0x20, - 0x00, 0xE0, - 0xA3, 0x0F, 0x4F, 0xE9, - - 0x06, 0x20, - 0x00, 0xE0, - 0x1F, 0x26, 0x1F, 0xDF, - - 0x17, 0x26, 0x17, 0xDF, - 0xA1, 0x1F, 0x4F, 0xE9, - - 0x1E, 0x26, 0x1E, 0xDF, - 0x9D, 0x1E, 0x4F, 0xE9, - - 0x35, 0x17, 0x4F, 0xE9, - 0xA2, 0x3F, 0x4F, 0xE9, - - 0x06, 0x06, 0x1F, 0xAF, - 0x39, 0x37, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x17, 0xAF, - 0x07, 0x07, 0x1E, 0xAF, - - 0xA0, 0x80, 0x4F, 0xE9, - 0x9E, 0x3E, 0x4F, 0xE9, - - 0x31, 0x80, 0x4F, 0xE9, - 0x9C, 0x80, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x63, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x62, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x60, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x5D, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g200_tgzsf[] = { - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x98, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x81, 0x04, - 0x89, 0x04, - 0x01, 0x04, - 0x09, 0x04, - - 0xC9, 0x41, 0xC0, 0xEC, - 0x11, 0x04, - 0x00, 0xE0, - - 0x41, 0xCC, 0x41, 0xCD, - 0x49, 0xCC, 0x49, 0xCD, - - 0xD1, 0x41, 0xC0, 0xEC, - 0x51, 0xCC, 0x51, 0xCD, - - 0x80, 0x04, - 0x10, 0x04, - 0x08, 0x04, - 0x00, 0xE0, - - 0x00, 0xCC, 0xC0, 0xCD, - 0xD1, 0x49, 0xC0, 0xEC, - - 0x8A, 0x1F, 0x20, 0xE9, - 0x8B, 0x3F, 0x20, 0xE9, - - 0x41, 0x3C, 0x41, 0xAD, - 0x49, 0x3C, 0x49, 0xAD, - - 0x10, 0xCC, 0x10, 0xCD, - 0x08, 0xCC, 0x08, 0xCD, - - 0xB9, 0x41, 0x49, 0xBB, - 0x1F, 0xF0, 0x41, 0xCD, - - 0x51, 0x3C, 0x51, 0xAD, - 0x00, 0x98, 0x80, 0xE9, - - 0x8F, 0x80, 0x07, 0xEA, - 0x24, 0x1F, 0x20, 0xE9, - - 0x21, 0x45, 0x80, 0xE8, - 0x1A, 0x4D, 0x80, 0xE8, - - 0x31, 0x55, 0x80, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0x41, 0x49, 0xBD, - 0x1D, 0x41, 0x51, 0xBD, - - 0x2E, 0x41, 0x2A, 0xB8, - 0x34, 0x53, 0xA0, 0xE8, - - 0x15, 0x30, - 0x1D, 0x30, - 0x58, 0xE3, - 0x00, 0xE0, - - 0xB5, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x24, 0x43, 0xA0, 0xE8, - 0x2C, 0x4B, 0xA0, 0xE8, - - 0x15, 0x72, - 0x09, 0xE3, - 0x00, 0xE0, - 0x1D, 0x72, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0x97, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x6C, 0x64, 0xC8, 0xEC, - 0x98, 0xE1, - 0xB5, 0x05, - - 0xBD, 0x05, - 0x2E, 0x30, - 0x32, 0xC0, 0xA0, 0xE8, - - 0x33, 0xC0, 0xA0, 0xE8, - 0x74, 0x64, 0xC8, 0xEC, - - 0x40, 0x3C, 0x40, 0xAD, - 0x32, 0x6A, - 0x2A, 0x30, - - 0x20, 0x73, - 0x33, 0x6A, - 0x00, 0xE0, - 0x28, 0x73, - - 0x1C, 0x72, - 0x83, 0xE2, - 0x7B, 0x80, 0x15, 0xEA, - - 0xB8, 0x3D, 0x28, 0xDF, - 0x30, 0x35, 0x20, 0xDF, - - 0x40, 0x30, - 0x00, 0xE0, - 0xCC, 0xE2, - 0x64, 0x72, - - 0x25, 0x42, 0x52, 0xBF, - 0x2D, 0x42, 0x4A, 0xBF, - - 0x30, 0x2E, 0x30, 0xDF, - 0x38, 0x2E, 0x38, 0xDF, - - 0x18, 0x1D, 0x45, 0xE9, - 0x1E, 0x15, 0x45, 0xE9, - - 0x2B, 0x49, 0x51, 0xBD, - 0x00, 0xE0, - 0x1F, 0x73, - - 0x38, 0x38, 0x40, 0xAF, - 0x30, 0x30, 0x40, 0xAF, - - 0x24, 0x1F, 0x24, 0xDF, - 0x1D, 0x32, 0x20, 0xE9, - - 0x2C, 0x1F, 0x2C, 0xDF, - 0x1A, 0x33, 0x20, 0xE9, - - 0xB0, 0x10, - 0x08, 0xE3, - 0x40, 0x10, - 0xB8, 0x10, - - 0x26, 0xF0, 0x30, 0xCD, - 0x2F, 0xF0, 0x38, 0xCD, - - 0x2B, 0x80, 0x20, 0xE9, - 0x2A, 0x80, 0x20, 0xE9, - - 0xA6, 0x20, - 0x88, 0xE2, - 0x00, 0xE0, - 0xAF, 0x20, - - 0x28, 0x2A, 0x26, 0xAF, - 0x20, 0x2A, 0xC0, 0xAF, - - 0x34, 0x1F, 0x34, 0xDF, - 0x46, 0x24, 0x46, 0xDF, - - 0x28, 0x30, 0x80, 0xBF, - 0x20, 0x38, 0x80, 0xBF, - - 0x47, 0x24, 0x47, 0xDF, - 0x4E, 0x2C, 0x4E, 0xDF, - - 0x4F, 0x2C, 0x4F, 0xDF, - 0x56, 0x34, 0x56, 0xDF, - - 0x28, 0x15, 0x28, 0xDF, - 0x20, 0x1D, 0x20, 0xDF, - - 0x57, 0x34, 0x57, 0xDF, - 0x00, 0xE0, - 0x1D, 0x05, - - 0x04, 0x80, 0x10, 0xEA, - 0x89, 0xE2, - 0x2B, 0x30, - - 0x3F, 0xC1, 0x1D, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x68, - 0xBF, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x20, 0xC0, 0x20, 0xAF, - 0x28, 0x05, - 0x97, 0x74, - - 0x00, 0xE0, - 0x2A, 0x10, - 0x16, 0xC0, 0x20, 0xE9, - - 0x04, 0x80, 0x10, 0xEA, - 0x8C, 0xE2, - 0x95, 0x05, - - 0x28, 0xC1, 0x28, 0xAD, - 0x1F, 0xC1, 0x15, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xA8, 0x67, - 0x9F, 0x6B, - 0x00, 0x80, 0x00, 0xE8, - - 0x28, 0xC0, 0x28, 0xAD, - 0x1D, 0x25, - 0x20, 0x05, - - 0x28, 0x32, 0x80, 0xAD, - 0x40, 0x2A, 0x40, 0xBD, - - 0x1C, 0x80, 0x20, 0xE9, - 0x20, 0x33, 0x20, 0xAD, - - 0x20, 0x73, - 0x00, 0xE0, - 0xB6, 0x49, 0x51, 0xBB, - - 0x26, 0x2F, 0xB0, 0xE8, - 0x19, 0x20, 0x20, 0xE9, - - 0x35, 0x20, 0x35, 0xDF, - 0x3D, 0x20, 0x3D, 0xDF, - - 0x15, 0x20, 0x15, 0xDF, - 0x1D, 0x20, 0x1D, 0xDF, - - 0x26, 0xD0, 0x26, 0xCD, - 0x29, 0x49, 0x2A, 0xB8, - - 0x26, 0x40, 0x80, 0xBD, - 0x3B, 0x48, 0x50, 0xBD, - - 0x3E, 0x54, 0x57, 0x9F, - 0x00, 0xE0, - 0x82, 0xE1, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x26, 0x30, - 0x29, 0x30, - 0x48, 0x3C, 0x48, 0xAD, - - 0x2B, 0x72, - 0xC2, 0xE1, - 0x2C, 0xC0, 0x44, 0xC2, - - 0x05, 0x24, 0x34, 0xBF, - 0x0D, 0x24, 0x2C, 0xBF, - - 0x2D, 0x46, 0x4E, 0xBF, - 0x25, 0x46, 0x56, 0xBF, - - 0x20, 0x1D, 0x6F, 0x8F, - 0x32, 0x3E, 0x5F, 0xE9, - - 0x3E, 0x50, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x30, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x33, 0x1E, 0x5F, 0xE9, - - 0x05, 0x44, 0x54, 0xB2, - 0x0D, 0x44, 0x4C, 0xB2, - - 0x19, 0xC0, 0xB0, 0xE8, - 0x34, 0xC0, 0x44, 0xC4, - - 0x33, 0x73, - 0x00, 0xE0, - 0x3E, 0x62, 0x57, 0x9F, - - 0x1E, 0xAF, 0x59, 0x9F, - 0x00, 0xE0, - 0x0D, 0x20, - - 0x84, 0x3E, 0x58, 0xE9, - 0x28, 0x1D, 0x6F, 0x8F, - - 0x05, 0x20, - 0x00, 0xE0, - 0x85, 0x1E, 0x58, 0xE9, - - 0x9B, 0x3B, 0x33, 0xDF, - 0x20, 0x20, 0x42, 0xAF, - - 0x30, 0x42, 0x56, 0x9F, - 0x80, 0x3E, 0x57, 0xE9, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x30, 0x80, 0x5F, 0xE9, - - 0x28, 0x28, 0x24, 0xAF, - 0x81, 0x1E, 0x57, 0xE9, - - 0x05, 0x47, 0x57, 0xBF, - 0x0D, 0x47, 0x4F, 0xBF, - - 0x88, 0x80, 0x58, 0xE9, - 0x1B, 0x29, 0x1B, 0xDF, - - 0x30, 0x1D, 0x6F, 0x8F, - 0x3A, 0x30, 0x4F, 0xE9, - - 0x1C, 0x30, 0x26, 0xDF, - 0x09, 0xE3, - 0x3B, 0x05, - - 0x3E, 0x50, 0x56, 0x9F, - 0x3B, 0x3F, 0x4F, 0xE9, - - 0x1E, 0x8F, 0x51, 0x9F, - 0x00, 0xE0, - 0xAC, 0x20, - - 0x2D, 0x44, 0x4C, 0xB4, - 0x2C, 0x1C, 0xC0, 0xAF, - - 0x25, 0x44, 0x54, 0xB4, - 0x00, 0xE0, - 0xC8, 0x30, - - 0x30, 0x46, 0x30, 0xAF, - 0x1B, 0x1B, 0x48, 0xAF, - - 0x00, 0xE0, - 0x25, 0x20, - 0x38, 0x2C, 0x4F, 0xE9, - - 0x86, 0x80, 0x57, 0xE9, - 0x38, 0x1D, 0x6F, 0x8F, - - 0x28, 0x74, - 0x00, 0xE0, - 0x0D, 0x44, 0x4C, 0xB0, - - 0x05, 0x44, 0x54, 0xB0, - 0x2D, 0x20, - 0x9B, 0x10, - - 0x82, 0x3E, 0x57, 0xE9, - 0x32, 0xF0, 0x1B, 0xCD, - - 0x1E, 0xBD, 0x59, 0x9F, - 0x83, 0x1E, 0x57, 0xE9, - - 0x38, 0x47, 0x38, 0xAF, - 0x34, 0x20, - 0x2A, 0x30, - - 0x00, 0xE0, - 0x0D, 0x20, - 0x32, 0x20, - 0x05, 0x20, - - 0x87, 0x80, 0x57, 0xE9, - 0x1F, 0x54, 0x57, 0x9F, - - 0x17, 0x42, 0x56, 0x9F, - 0x00, 0xE0, - 0x3B, 0x6A, - - 0x3F, 0x8F, 0x51, 0x9F, - 0x37, 0x1E, 0x4F, 0xE9, - - 0x37, 0x32, 0x2A, 0xAF, - 0x00, 0xE0, - 0x32, 0x00, - - 0x00, 0x80, 0x00, 0xE8, - 0x27, 0xC0, 0x44, 0xC0, - - 0x36, 0x1F, 0x4F, 0xE9, - 0x1F, 0x1F, 0x26, 0xDF, - - 0x37, 0x1B, 0x37, 0xBF, - 0x17, 0x26, 0x17, 0xDF, - - 0x3E, 0x17, 0x4F, 0xE9, - 0x3F, 0x3F, 0x4F, 0xE9, - - 0x34, 0x1F, 0x34, 0xAF, - 0x2B, 0x05, - 0xA7, 0x20, - - 0x33, 0x2B, 0x37, 0xDF, - 0x27, 0x17, 0xC0, 0xAF, - - 0x34, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x2D, 0x21, 0x1A, 0xB0, - 0x25, 0x21, 0x31, 0xB0, - - 0x0D, 0x21, 0x1A, 0xB2, - 0x05, 0x21, 0x31, 0xB2, - - 0x03, 0x80, 0x2A, 0xEA, - 0x17, 0xC1, 0x2B, 0xBD, - - 0x2D, 0x20, - 0x25, 0x20, - 0x05, 0x20, - 0x0D, 0x20, - - 0xB3, 0x68, - 0x97, 0x25, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0xC0, 0x33, 0xAF, - 0x2F, 0xC0, 0x21, 0xC0, - - 0x16, 0x42, 0x56, 0x9F, - 0x3C, 0x27, 0x4F, 0xE9, - - 0x1E, 0x62, 0x57, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x21, 0x31, 0xB4, - 0x2D, 0x21, 0x1A, 0xB4, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x33, 0x05, - 0x00, 0xE0, - 0x28, 0x19, 0x60, 0xEC, - - 0x0D, 0x21, 0x1A, 0xB6, - 0x05, 0x21, 0x31, 0xB6, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0xE0, - 0x2F, 0x20, - - 0x23, 0x3B, 0x33, 0xAD, - 0x1E, 0x26, 0x1E, 0xDF, - - 0xA7, 0x1E, 0x4F, 0xE9, - 0x17, 0x26, 0x16, 0xDF, - - 0x2D, 0x20, - 0x00, 0xE0, - 0xA8, 0x3F, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x1E, 0xAF, - 0x25, 0x20, - 0x00, 0xE0, - - 0xA4, 0x16, 0x4F, 0xE9, - 0x0F, 0xC0, 0x21, 0xC2, - - 0xA6, 0x80, 0x4F, 0xE9, - 0x1F, 0x62, 0x57, 0x9F, - - 0x0D, 0x20, - 0x05, 0x20, - 0x2F, 0xC0, 0x21, 0xC6, - - 0x3F, 0x2F, 0x5D, 0x9F, - 0x00, 0xE0, - 0x0F, 0x20, - - 0x17, 0x50, 0x56, 0x9F, - 0xA5, 0x37, 0x4F, 0xE9, - - 0x06, 0xC0, 0x21, 0xC4, - 0x0F, 0x17, 0x0F, 0xAF, - - 0x37, 0x0F, 0x5C, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x2F, 0x20, - 0x00, 0xE0, - 0xA3, 0x80, 0x4F, 0xE9, - - 0x06, 0x20, - 0x00, 0xE0, - 0x1F, 0x26, 0x1F, 0xDF, - - 0x17, 0x26, 0x17, 0xDF, - 0x35, 0x17, 0x4F, 0xE9, - - 0xA1, 0x1F, 0x4F, 0xE9, - 0xA2, 0x3F, 0x4F, 0xE9, - - 0x06, 0x06, 0x1F, 0xAF, - 0x39, 0x37, 0x4F, 0xE9, - - 0x2F, 0x2F, 0x17, 0xAF, - 0x00, 0x80, 0x00, 0xE8, - - 0xA0, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x31, 0x80, 0x4F, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x57, 0x39, 0x20, 0xE9, - - 0x16, 0x28, 0x20, 0xE9, - 0x1D, 0x3B, 0x20, 0xE9, - - 0x1E, 0x2B, 0x20, 0xE9, - 0x2B, 0x32, 0x20, 0xE9, - - 0x1C, 0x23, 0x20, 0xE9, - 0x57, 0x36, 0x20, 0xE9, - - 0x00, 0x80, 0xA0, 0xE9, - 0x40, 0x40, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x90, 0xE2, - 0x00, 0xE0, - - 0x68, 0xFF, 0x20, 0xEA, - 0x19, 0xC8, 0xC1, 0xCD, - - 0x1F, 0xD7, 0x18, 0xBD, - 0x3F, 0xD7, 0x22, 0xBD, - - 0x9F, 0x41, 0x49, 0xBD, - 0x00, 0x80, 0x00, 0xE8, - - 0x25, 0x41, 0x49, 0xBD, - 0x2D, 0x41, 0x51, 0xBD, - - 0x0D, 0x80, 0x07, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x35, 0x40, 0x48, 0xBD, - 0x3D, 0x40, 0x50, 0xBD, - - 0x00, 0x80, 0x00, 0xE8, - 0x25, 0x30, - 0x2D, 0x30, - - 0x35, 0x30, - 0xB5, 0x30, - 0xBD, 0x30, - 0x3D, 0x30, - - 0x9C, 0xA7, 0x5B, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x67, 0xFF, 0x0A, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0xC9, 0x41, 0xC8, 0xEC, - 0x42, 0xE1, - 0x00, 0xE0, - - 0x65, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0xC8, 0x40, 0xC0, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x62, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - -}; - -static unsigned char warp_g400_t2gz[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x78, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x69, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0x34, 0x80, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x25, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x3D, 0xCF, 0x74, 0xC2, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x2A, 0x44, 0x54, 0xB4, - 0x1A, 0x44, 0x64, 0xB4, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x9F, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xBE, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x7D, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gza[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x7C, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x6D, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0x34, 0x80, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x29, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0F, 0xCF, 0x74, 0xC6, - 0x3D, 0xCF, 0x74, 0xC2, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x0F, 0x20, 0xE9, - - 0x0A, 0x44, 0x54, 0xB4, - 0x02, 0x44, 0x64, 0xB4, - - 0x2A, 0x44, 0x54, 0xB6, - 0x1A, 0x44, 0x64, 0xB6, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x36, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x37, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x9B, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xBA, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x79, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzaf[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x81, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x72, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x31, 0x53, 0x2F, 0x9F, - 0x34, 0x37, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x2E, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x3D, 0xCF, 0x74, 0xC2, - 0x0F, 0xCF, 0x74, 0xC6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x0F, 0x20, 0xE9, - - 0x0A, 0x44, 0x54, 0xB4, - 0x02, 0x44, 0x64, 0xB4, - - 0x2A, 0x44, 0x54, 0xB6, - 0x1A, 0x44, 0x64, 0xB6, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x3D, 0xCF, 0x75, 0xC6, - 0x00, 0x80, 0x00, 0xE8, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x0A, 0x45, 0x55, 0xB6, - 0x02, 0x45, 0x65, 0xB6, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x31, 0x3D, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x38, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x96, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xB5, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x74, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzf[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x7D, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x6E, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x34, 0x80, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x88, 0x73, 0x5E, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0F, 0xCF, 0x75, 0xC6, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x28, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x3D, 0xCF, 0x74, 0xC2, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x31, 0x0F, 0x20, 0xE9, - - 0x0A, 0x44, 0x54, 0xB4, - 0x02, 0x44, 0x64, 0xB4, - - 0x2A, 0x45, 0x55, 0xB6, - 0x1A, 0x45, 0x65, 0xB6, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x36, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x37, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x39, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x9A, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xBB, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x78, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzs[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x85, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x76, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x0F, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x31, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0F, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB4, - 0x1A, 0x44, 0x64, 0xB4, - - 0x0A, 0x45, 0x55, 0xB0, - 0x02, 0x45, 0x65, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x2A, 0x45, 0x55, 0xB2, - 0x1A, 0x45, 0x65, 0xB2, - - 0x0A, 0x45, 0x55, 0xB4, - 0x02, 0x45, 0x65, 0xB4, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x20, - 0x1A, 0x20, - 0x0A, 0x20, - 0x02, 0x20, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0xA7, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x92, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xB2, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x70, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzsa[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x8A, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x7B, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x0F, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x36, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0F, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB4, - 0x1A, 0x44, 0x64, 0xB4, - - 0x0A, 0x45, 0x55, 0xB0, - 0x02, 0x45, 0x65, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x45, 0x55, 0xB2, - 0x1A, 0x45, 0x65, 0xB2, - - 0x0A, 0x45, 0x55, 0xB4, - 0x02, 0x45, 0x65, 0xB4, - - 0x0F, 0xCF, 0x74, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA7, 0x30, 0x4F, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x2A, 0x44, 0x54, 0xB6, - 0x1A, 0x44, 0x64, 0xB6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x8D, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xAD, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x6B, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzsaf[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x8E, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x7F, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x0F, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x3A, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0F, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB4, - 0x1A, 0x44, 0x64, 0xB4, - - 0x0A, 0x45, 0x55, 0xB0, - 0x02, 0x45, 0x65, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x45, 0x55, 0xB2, - 0x1A, 0x45, 0x65, 0xB2, - - 0x0A, 0x45, 0x55, 0xB4, - 0x02, 0x45, 0x65, 0xB4, - - 0x0F, 0xCF, 0x74, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA7, 0x30, 0x4F, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x2A, 0x44, 0x54, 0xB6, - 0x1A, 0x44, 0x64, 0xB6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x0A, 0x45, 0x55, 0xB6, - 0x02, 0x45, 0x65, 0xB6, - - 0x3D, 0xCF, 0x75, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x31, 0x3D, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x38, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x89, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xA9, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x67, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_t2gzsf[] = { - - 0x00, 0x8A, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x0A, 0x40, 0x50, 0xBF, - 0x2A, 0x40, 0x60, 0xBF, - - 0x32, 0x41, 0x51, 0xBF, - 0x3A, 0x41, 0x61, 0xBF, - - 0xC3, 0x6B, - 0xD3, 0x6B, - 0x00, 0x8A, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x53, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x23, 0x9F, - 0x00, 0xE0, - 0x51, 0x04, - - 0x90, 0xE2, - 0x61, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x51, 0x41, 0xE0, 0xEC, - 0x39, 0x67, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x63, 0xA0, 0xE8, - - 0x61, 0x41, 0xE0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x8A, 0x80, 0x15, 0xEA, - 0x10, 0x04, - 0x20, 0x04, - - 0x61, 0x51, 0xE0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x52, 0xBF, - 0x0F, 0x52, 0xA0, 0xE8, - - 0x1A, 0x42, 0x62, 0xBF, - 0x1E, 0x51, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x0E, 0x61, 0x60, 0xEA, - - 0x32, 0x40, 0x50, 0xBD, - 0x22, 0x40, 0x60, 0xBD, - - 0x12, 0x41, 0x51, 0xBD, - 0x3A, 0x41, 0x61, 0xBD, - - 0xBF, 0x2F, 0x0E, 0xBD, - 0x97, 0xE2, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x35, 0x48, 0xB1, 0xE8, - 0x3D, 0x59, 0xB1, 0xE8, - - 0x46, 0x31, 0x46, 0xBF, - 0x56, 0x31, 0x56, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x66, 0x31, 0x66, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x57, 0x39, 0x57, 0xBF, - 0x67, 0x39, 0x67, 0xBF, - - 0x7B, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x35, 0x00, - 0x3D, 0x00, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0x8D, 0x2F, 0x1E, 0xBD, - - 0x43, 0x75, 0xF8, 0xEC, - 0x35, 0x20, - 0x3D, 0x20, - - 0x43, 0x43, 0x2D, 0xDF, - 0x53, 0x53, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x0E, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x48, 0x35, 0x48, 0xBF, - 0x58, 0x35, 0x58, 0xBF, - - 0x68, 0x35, 0x68, 0xBF, - 0x49, 0x3D, 0x49, 0xBF, - - 0x59, 0x3D, 0x59, 0xBF, - 0x69, 0x3D, 0x69, 0xBF, - - 0x63, 0x63, 0x2D, 0xDF, - 0x4D, 0x7D, 0xF8, 0xEC, - - 0x59, 0xE3, - 0x00, 0xE0, - 0xB8, 0x38, 0x33, 0xBF, - - 0x2D, 0x73, - 0x30, 0x76, - 0x18, 0x3A, 0x41, 0xE9, - - 0x3F, 0x53, 0xA0, 0xE8, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x63, 0xA0, 0xE8, - - 0x50, 0x70, 0xF8, 0xEC, - 0x2B, 0x50, 0x3C, 0xE9, - - 0x1F, 0x0F, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x59, 0x78, 0xF8, 0xEC, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x46, 0x37, 0x46, 0xDF, - 0x56, 0x3F, 0x56, 0xDF, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x66, 0x3D, 0x66, 0xDF, - - 0x1D, 0x32, 0x41, 0xE9, - 0x67, 0x3D, 0x67, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3F, 0x57, 0xDF, - - 0x2A, 0x40, 0x20, 0xE9, - 0x59, 0x3F, 0x59, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x69, 0x3D, 0x69, 0xDF, - - 0x48, 0x37, 0x48, 0xDF, - 0x58, 0x3F, 0x58, 0xDF, - - 0x68, 0x3D, 0x68, 0xDF, - 0x49, 0x37, 0x49, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x0F, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x54, 0xB0, - 0x02, 0x44, 0x64, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB2, - 0x1A, 0x44, 0x64, 0xB2, - - 0x36, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0F, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x54, 0xB4, - 0x1A, 0x44, 0x64, 0xB4, - - 0x0A, 0x45, 0x55, 0xB0, - 0x02, 0x45, 0x65, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x45, 0x55, 0xB2, - 0x1A, 0x45, 0x65, 0xB2, - - 0x0A, 0x45, 0x55, 0xB4, - 0x02, 0x45, 0x65, 0xB4, - - 0x0F, 0xCF, 0x75, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA7, 0x30, 0x4F, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x31, 0x0F, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x2A, 0x45, 0x55, 0xB6, - 0x1A, 0x45, 0x65, 0xB6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x56, 0xBF, - 0x1A, 0x46, 0x66, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x0A, 0x47, 0x57, 0xBF, - 0x02, 0x47, 0x67, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x53, 0xBF, - 0x1A, 0x43, 0x63, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x39, 0x4F, 0xE9, - - 0x0A, 0x48, 0x58, 0xBF, - 0x02, 0x48, 0x68, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x2A, 0x49, 0x59, 0xBF, - 0x1A, 0x49, 0x69, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x82, 0x30, 0x57, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x83, 0x38, 0x57, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x84, 0x31, 0x5E, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x85, 0x39, 0x5E, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8A, 0x36, 0x20, 0xE9, - - 0x87, 0x77, 0x57, 0xE9, - 0x8B, 0x3E, 0xBF, 0xEA, - - 0x80, 0x30, 0x57, 0xE9, - 0x81, 0x38, 0x57, 0xE9, - - 0x82, 0x31, 0x57, 0xE9, - 0x86, 0x78, 0x57, 0xE9, - - 0x83, 0x39, 0x57, 0xE9, - 0x87, 0x79, 0x57, 0xE9, - - 0x30, 0x1F, 0x5F, 0xE9, - 0x8A, 0x34, 0x20, 0xE9, - - 0x8B, 0x3C, 0x20, 0xE9, - 0x37, 0x50, 0x60, 0xBD, - - 0x57, 0x0D, 0x20, 0xE9, - 0x35, 0x51, 0x61, 0xBD, - - 0x2B, 0x50, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x0E, 0x77, - - 0x24, 0x51, 0x20, 0xE9, - 0x8D, 0xFF, 0x20, 0xEA, - - 0x16, 0x0E, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x0B, 0x46, 0xA0, 0xE8, - 0x1B, 0x56, 0xA0, 0xE8, - - 0x2B, 0x66, 0xA0, 0xE8, - 0x0C, 0x47, 0xA0, 0xE8, - - 0x1C, 0x57, 0xA0, 0xE8, - 0x2C, 0x67, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x57, 0x80, 0x57, 0xCF, - - 0x66, 0x33, 0x66, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x67, 0x3B, 0x67, 0xCF, - - 0x0B, 0x48, 0xA0, 0xE8, - 0x1B, 0x58, 0xA0, 0xE8, - - 0x2B, 0x68, 0xA0, 0xE8, - 0x0C, 0x49, 0xA0, 0xE8, - - 0x1C, 0x59, 0xA0, 0xE8, - 0x2C, 0x69, 0xA0, 0xE8, - - 0x0B, 0x00, - 0x1B, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x0C, 0x00, - 0x1C, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x0B, 0x65, - 0x1B, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x0C, 0x65, - 0x1C, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x0B, 0x1B, 0x60, 0xEC, - 0x34, 0xD7, 0x34, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x0C, 0x1C, 0x60, 0xEC, - - 0x3C, 0xD7, 0x3C, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x0B, 0x2B, 0xDE, 0xE8, - 0x1B, 0x80, 0xDE, 0xE8, - - 0x34, 0x80, 0x34, 0xBD, - 0x3C, 0x80, 0x3C, 0xBD, - - 0x33, 0xD7, 0x0B, 0xBD, - 0x3B, 0xD7, 0x1B, 0xBD, - - 0x48, 0x80, 0x48, 0xCF, - 0x59, 0x80, 0x59, 0xCF, - - 0x68, 0x33, 0x68, 0xCF, - 0x49, 0x3B, 0x49, 0xCF, - - 0xAD, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x58, 0x33, 0x58, 0xCF, - 0x69, 0x3B, 0x69, 0xCF, - - 0x6B, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgz[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x58, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x4A, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0x34, 0x80, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x1D, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x3D, 0xCF, 0x74, 0xC2, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x2A, 0x44, 0x4C, 0xB4, - 0x1A, 0x44, 0x54, 0xB4, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0xAF, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xD6, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x9D, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgza[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x5C, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x4E, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0x34, 0x80, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x27, 0xCF, 0x74, 0xC6, - 0x3D, 0xCF, 0x74, 0xC2, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x20, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x27, 0x20, 0xE9, - - 0x0A, 0x44, 0x4C, 0xB4, - 0x02, 0x44, 0x54, 0xB4, - - 0x2A, 0x44, 0x4C, 0xB6, - 0x1A, 0x44, 0x54, 0xB6, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x36, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x37, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0xAB, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xD3, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x99, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgzaf[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x61, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x53, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x31, 0x53, 0x2F, 0x9F, - 0x34, 0x37, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x26, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x3D, 0xCF, 0x74, 0xC2, - 0x27, 0xCF, 0x74, 0xC6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x27, 0x20, 0xE9, - - 0x0A, 0x44, 0x4C, 0xB4, - 0x02, 0x44, 0x54, 0xB4, - - 0x2A, 0x44, 0x4C, 0xB6, - 0x1A, 0x44, 0x54, 0xB6, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x3D, 0xCF, 0x75, 0xC6, - 0x00, 0x80, 0x00, 0xE8, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x0A, 0x45, 0x4D, 0xB6, - 0x02, 0x45, 0x55, 0xB6, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x31, 0x3D, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0xA6, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xCD, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x94, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgzf[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x5D, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x4F, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x37, 0xCF, 0x74, 0xC4, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x34, 0x80, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x88, 0x73, 0x5E, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x27, 0xCF, 0x75, 0xC6, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x20, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x3D, 0xCF, 0x74, 0xC2, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x31, 0x27, 0x20, 0xE9, - - 0x0A, 0x44, 0x4C, 0xB4, - 0x02, 0x44, 0x54, 0xB4, - - 0x2A, 0x45, 0x4D, 0xB6, - 0x1A, 0x45, 0x55, 0xB6, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x38, 0x3D, 0x20, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x36, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x37, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0xAA, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xD3, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x98, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgzs[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x65, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x57, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x27, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x29, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x27, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB4, - 0x1A, 0x44, 0x54, 0xB4, - - 0x0A, 0x45, 0x4D, 0xB0, - 0x02, 0x45, 0x55, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x2A, 0x45, 0x4D, 0xB2, - 0x1A, 0x45, 0x55, 0xB2, - - 0x0A, 0x45, 0x4D, 0xB4, - 0x02, 0x45, 0x55, 0xB4, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x0A, 0x20, - 0x02, 0x20, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0xA7, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0xA2, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xCA, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x90, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgzsa[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x6A, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x5C, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x27, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x2E, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x27, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB4, - 0x1A, 0x44, 0x54, 0xB4, - - 0x0A, 0x45, 0x4D, 0xB0, - 0x02, 0x45, 0x55, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x45, 0x4D, 0xB2, - 0x1A, 0x45, 0x55, 0xB2, - - 0x0A, 0x45, 0x4D, 0xB4, - 0x02, 0x45, 0x55, 0xB4, - - 0x27, 0xCF, 0x74, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA7, 0x30, 0x4F, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB6, - 0x1A, 0x44, 0x54, 0xB6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0x9D, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xC5, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x8B, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgzsaf[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x6E, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x60, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x27, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x32, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x27, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB4, - 0x1A, 0x44, 0x54, 0xB4, - - 0x0A, 0x45, 0x4D, 0xB0, - 0x02, 0x45, 0x55, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x45, 0x4D, 0xB2, - 0x1A, 0x45, 0x55, 0xB2, - - 0x0A, 0x45, 0x4D, 0xB4, - 0x02, 0x45, 0x55, 0xB4, - - 0x27, 0xCF, 0x74, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA7, 0x30, 0x4F, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9C, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB6, - 0x1A, 0x44, 0x54, 0xB6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x0A, 0x45, 0x4D, 0xB6, - 0x02, 0x45, 0x55, 0xB6, - - 0x3D, 0xCF, 0x75, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x31, 0x3D, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x9D, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x9E, 0x39, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x30, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x38, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0x99, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xC1, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x87, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; - -static unsigned char warp_g400_tgzsf[] = { - - 0x00, 0x88, 0x98, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - - 0xFF, 0x80, 0xC0, 0xE9, - 0x00, 0x80, 0x00, 0xE8, - - 0x22, 0x40, 0x48, 0xBF, - 0x2A, 0x40, 0x50, 0xBF, - - 0x32, 0x41, 0x49, 0xBF, - 0x3A, 0x41, 0x51, 0xBF, - - 0xC3, 0x6B, - 0xCB, 0x6B, - 0x00, 0x88, 0x98, 0xE9, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x96, 0xE2, - 0x41, 0x04, - - 0x7B, 0x43, 0xA0, 0xE8, - 0x73, 0x4B, 0xA0, 0xE8, - - 0xAD, 0xEE, 0x29, 0x9F, - 0x00, 0xE0, - 0x49, 0x04, - - 0x90, 0xE2, - 0x51, 0x04, - 0x31, 0x46, 0xB1, 0xE8, - - 0x49, 0x41, 0xC0, 0xEC, - 0x39, 0x57, 0xB1, 0xE8, - - 0x00, 0x04, - 0x46, 0xE2, - 0x73, 0x53, 0xA0, 0xE8, - - 0x51, 0x41, 0xC0, 0xEC, - 0x31, 0x00, - 0x39, 0x00, - - 0x6A, 0x80, 0x15, 0xEA, - 0x08, 0x04, - 0x10, 0x04, - - 0x51, 0x49, 0xC0, 0xEC, - 0x2F, 0x41, 0x60, 0xEA, - - 0x31, 0x20, - 0x39, 0x20, - 0x1F, 0x42, 0xA0, 0xE8, - - 0x2A, 0x42, 0x4A, 0xBF, - 0x27, 0x4A, 0xA0, 0xE8, - - 0x1A, 0x42, 0x52, 0xBF, - 0x1E, 0x49, 0x60, 0xEA, - - 0x73, 0x7B, 0xC8, 0xEC, - 0x26, 0x51, 0x60, 0xEA, - - 0x32, 0x40, 0x48, 0xBD, - 0x22, 0x40, 0x50, 0xBD, - - 0x12, 0x41, 0x49, 0xBD, - 0x3A, 0x41, 0x51, 0xBD, - - 0xBF, 0x2F, 0x26, 0xBD, - 0x00, 0xE0, - 0x7B, 0x72, - - 0x32, 0x20, - 0x22, 0x20, - 0x12, 0x20, - 0x3A, 0x20, - - 0x46, 0x31, 0x46, 0xBF, - 0x4E, 0x31, 0x4E, 0xBF, - - 0xB3, 0xE2, 0x2D, 0x9F, - 0x00, 0x80, 0x00, 0xE8, - - 0x56, 0x31, 0x56, 0xBF, - 0x47, 0x39, 0x47, 0xBF, - - 0x4F, 0x39, 0x4F, 0xBF, - 0x57, 0x39, 0x57, 0xBF, - - 0x5C, 0x80, 0x07, 0xEA, - 0x24, 0x41, 0x20, 0xE9, - - 0x42, 0x73, 0xF8, 0xEC, - 0x00, 0xE0, - 0x2D, 0x73, - - 0x33, 0x72, - 0x0C, 0xE3, - 0xA5, 0x2F, 0x1E, 0xBD, - - 0x43, 0x43, 0x2D, 0xDF, - 0x4B, 0x4B, 0x2D, 0xDF, - - 0xAE, 0x1E, 0x26, 0xBD, - 0x58, 0xE3, - 0x33, 0x66, - - 0x53, 0x53, 0x2D, 0xDF, - 0x00, 0x80, 0x00, 0xE8, - - 0xB8, 0x38, 0x33, 0xBF, - 0x00, 0xE0, - 0x59, 0xE3, - - 0x1E, 0x12, 0x41, 0xE9, - 0x1A, 0x22, 0x41, 0xE9, - - 0x2B, 0x40, 0x3D, 0xE9, - 0x3F, 0x4B, 0xA0, 0xE8, - - 0x2D, 0x73, - 0x30, 0x76, - 0x05, 0x80, 0x3D, 0xEA, - - 0x37, 0x43, 0xA0, 0xE8, - 0x3D, 0x53, 0xA0, 0xE8, - - 0x48, 0x70, 0xF8, 0xEC, - 0x2B, 0x48, 0x3C, 0xE9, - - 0x1F, 0x27, 0xBC, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x00, 0x80, 0x00, 0xE8, - 0x00, 0x80, 0x00, 0xE8, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x15, 0xC0, 0x20, 0xE9, - 0x15, 0xC0, 0x20, 0xE9, - - 0x18, 0x3A, 0x41, 0xE9, - 0x1D, 0x32, 0x41, 0xE9, - - 0x2A, 0x40, 0x20, 0xE9, - 0x56, 0x3D, 0x56, 0xDF, - - 0x46, 0x37, 0x46, 0xDF, - 0x4E, 0x3F, 0x4E, 0xDF, - - 0x16, 0x30, 0x20, 0xE9, - 0x4F, 0x3F, 0x4F, 0xDF, - - 0x47, 0x37, 0x47, 0xDF, - 0x57, 0x3D, 0x57, 0xDF, - - 0x32, 0x32, 0x2D, 0xDF, - 0x22, 0x22, 0x2D, 0xDF, - - 0x12, 0x12, 0x2D, 0xDF, - 0x3A, 0x3A, 0x2D, 0xDF, - - 0x27, 0xCF, 0x74, 0xC2, - 0x37, 0xCF, 0x74, 0xC4, - - 0x0A, 0x44, 0x4C, 0xB0, - 0x02, 0x44, 0x54, 0xB0, - - 0x3D, 0xCF, 0x74, 0xC0, - 0x34, 0x37, 0x20, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x38, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3C, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB2, - 0x1A, 0x44, 0x54, 0xB2, - - 0x2E, 0x80, 0x3A, 0xEA, - 0x0A, 0x20, - 0x02, 0x20, - - 0x27, 0xCF, 0x75, 0xC0, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x30, 0x50, 0x2E, 0x9F, - 0x32, 0x31, 0x5F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x33, 0x39, 0x5F, 0xE9, - - 0x3D, 0xCF, 0x75, 0xC2, - 0x37, 0xCF, 0x75, 0xC4, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA6, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA3, 0x3D, 0x20, 0xE9, - - 0x2A, 0x44, 0x4C, 0xB4, - 0x1A, 0x44, 0x54, 0xB4, - - 0x0A, 0x45, 0x4D, 0xB0, - 0x02, 0x45, 0x55, 0xB0, - - 0x88, 0x73, 0x5E, 0xE9, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA0, 0x37, 0x20, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x3E, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x3F, 0x38, 0x4F, 0xE9, - - 0x30, 0x50, 0x2E, 0x9F, - 0x3A, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x3B, 0x39, 0x4F, 0xE9, - - 0x2A, 0x45, 0x4D, 0xB2, - 0x1A, 0x45, 0x55, 0xB2, - - 0x0A, 0x45, 0x4D, 0xB4, - 0x02, 0x45, 0x55, 0xB4, - - 0x27, 0xCF, 0x75, 0xC6, - 0x2A, 0x20, - 0x1A, 0x20, - - 0xA7, 0x30, 0x4F, 0xE9, - 0x0A, 0x20, - 0x02, 0x20, - - 0x31, 0x53, 0x2F, 0x9F, - 0x31, 0x27, 0x20, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA8, 0x38, 0x4F, 0xE9, - - 0x2A, 0x45, 0x4D, 0xB6, - 0x1A, 0x45, 0x55, 0xB6, - - 0x30, 0x50, 0x2E, 0x9F, - 0x36, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x37, 0x39, 0x4F, 0xE9, - - 0x00, 0x80, 0x00, 0xE8, - 0x2A, 0x20, - 0x1A, 0x20, - - 0x2A, 0x46, 0x4E, 0xBF, - 0x1A, 0x46, 0x56, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA4, 0x31, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA5, 0x39, 0x4F, 0xE9, - - 0x0A, 0x47, 0x4F, 0xBF, - 0x02, 0x47, 0x57, 0xBF, - - 0x31, 0x53, 0x2F, 0x9F, - 0xA1, 0x30, 0x4F, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0xA2, 0x38, 0x4F, 0xE9, - - 0x2A, 0x43, 0x4B, 0xBF, - 0x1A, 0x43, 0x53, 0xBF, - - 0x30, 0x50, 0x2E, 0x9F, - 0x35, 0x31, 0x4F, 0xE9, - - 0x38, 0x21, 0x2C, 0x9F, - 0x39, 0x39, 0x4F, 0xE9, - - 0x31, 0x53, 0x2F, 0x9F, - 0x80, 0x31, 0x57, 0xE9, - - 0x39, 0xE5, 0x2C, 0x9F, - 0x81, 0x39, 0x57, 0xE9, - - 0x37, 0x48, 0x50, 0xBD, - 0x8A, 0x36, 0x20, 0xE9, - - 0x86, 0x76, 0x57, 0xE9, - 0x8B, 0x3E, 0x20, 0xE9, - - 0x82, 0x30, 0x57, 0xE9, - 0x87, 0x77, 0x57, 0xE9, - - 0x83, 0x38, 0x57, 0xE9, - 0x35, 0x49, 0x51, 0xBD, - - 0x84, 0x31, 0x5E, 0xE9, - 0x30, 0x1F, 0x5F, 0xE9, - - 0x85, 0x39, 0x5E, 0xE9, - 0x57, 0x25, 0x20, 0xE9, - - 0x2B, 0x48, 0x20, 0xE9, - 0x1D, 0x37, 0xE1, 0xEA, - - 0x1E, 0x35, 0xE1, 0xEA, - 0x00, 0xE0, - 0x26, 0x77, - - 0x24, 0x49, 0x20, 0xE9, - 0x9D, 0xFF, 0x20, 0xEA, - - 0x16, 0x26, 0x20, 0xE9, - 0x57, 0x2E, 0xBF, 0xEA, - - 0x1C, 0x46, 0xA0, 0xE8, - 0x23, 0x4E, 0xA0, 0xE8, - - 0x2B, 0x56, 0xA0, 0xE8, - 0x1D, 0x47, 0xA0, 0xE8, - - 0x24, 0x4F, 0xA0, 0xE8, - 0x2C, 0x57, 0xA0, 0xE8, - - 0x1C, 0x00, - 0x23, 0x00, - 0x2B, 0x00, - 0x00, 0xE0, - - 0x1D, 0x00, - 0x24, 0x00, - 0x2C, 0x00, - 0x00, 0xE0, - - 0x1C, 0x65, - 0x23, 0x65, - 0x2B, 0x65, - 0x00, 0xE0, - - 0x1D, 0x65, - 0x24, 0x65, - 0x2C, 0x65, - 0x00, 0xE0, - - 0x1C, 0x23, 0x60, 0xEC, - 0x36, 0xD7, 0x36, 0xAD, - - 0x2B, 0x80, 0x60, 0xEC, - 0x1D, 0x24, 0x60, 0xEC, - - 0x3E, 0xD7, 0x3E, 0xAD, - 0x2C, 0x80, 0x60, 0xEC, - - 0x1C, 0x2B, 0xDE, 0xE8, - 0x23, 0x80, 0xDE, 0xE8, - - 0x36, 0x80, 0x36, 0xBD, - 0x3E, 0x80, 0x3E, 0xBD, - - 0x33, 0xD7, 0x1C, 0xBD, - 0x3B, 0xD7, 0x23, 0xBD, - - 0x46, 0x80, 0x46, 0xCF, - 0x4F, 0x80, 0x4F, 0xCF, - - 0x56, 0x33, 0x56, 0xCF, - 0x47, 0x3B, 0x47, 0xCF, - - 0xC5, 0xFF, 0x20, 0xEA, - 0x00, 0x80, 0x00, 0xE8, - - 0x4E, 0x33, 0x4E, 0xCF, - 0x57, 0x3B, 0x57, 0xCF, - - 0x8B, 0xFF, 0x20, 0xEA, - 0x57, 0xC0, 0xBF, 0xEA, - - 0x00, 0x80, 0xA0, 0xE9, - 0x00, 0x00, 0xD8, 0xEC, - -}; diff --git a/drivers/gpu/drm/mga/mga_warp.c b/drivers/gpu/drm/mga/mga_warp.c index 651b93c..9aad484 100644 --- a/drivers/gpu/drm/mga/mga_warp.c +++ b/drivers/gpu/drm/mga/mga_warp.c @@ -27,132 +27,108 @@ * Gareth Hughes */ +#include +#include +#include + #include "drmP.h" #include "drm.h" #include "mga_drm.h" #include "mga_drv.h" -#include "mga_ucode.h" + +#define FIRMWARE_G200 "matrox/g200_warp.fw" +#define FIRMWARE_G400 "matrox/g400_warp.fw" + +MODULE_FIRMWARE(FIRMWARE_G200); +MODULE_FIRMWARE(FIRMWARE_G400); #define MGA_WARP_CODE_ALIGN 256 /* in bytes */ -#define WARP_UCODE_SIZE( which ) \ - ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN) - -#define WARP_UCODE_INSTALL( which, where ) \ -do { \ - DRM_DEBUG( " pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase );\ - dev_priv->warp_pipe_phys[where] = pcbase; \ - memcpy( vcbase, which, sizeof(which) ); \ - pcbase += WARP_UCODE_SIZE( which ); \ - vcbase += WARP_UCODE_SIZE( which ); \ -} while (0) - -static const unsigned int mga_warp_g400_microcode_size = - (WARP_UCODE_SIZE(warp_g400_tgz) + - WARP_UCODE_SIZE(warp_g400_tgza) + - WARP_UCODE_SIZE(warp_g400_tgzaf) + - WARP_UCODE_SIZE(warp_g400_tgzf) + - WARP_UCODE_SIZE(warp_g400_tgzs) + - WARP_UCODE_SIZE(warp_g400_tgzsa) + - WARP_UCODE_SIZE(warp_g400_tgzsaf) + - WARP_UCODE_SIZE(warp_g400_tgzsf) + - WARP_UCODE_SIZE(warp_g400_t2gz) + - WARP_UCODE_SIZE(warp_g400_t2gza) + - WARP_UCODE_SIZE(warp_g400_t2gzaf) + - WARP_UCODE_SIZE(warp_g400_t2gzf) + - WARP_UCODE_SIZE(warp_g400_t2gzs) + - WARP_UCODE_SIZE(warp_g400_t2gzsa) + - WARP_UCODE_SIZE(warp_g400_t2gzsaf) + WARP_UCODE_SIZE(warp_g400_t2gzsf)); - -static const unsigned int mga_warp_g200_microcode_size = - (WARP_UCODE_SIZE(warp_g200_tgz) + - WARP_UCODE_SIZE(warp_g200_tgza) + - WARP_UCODE_SIZE(warp_g200_tgzaf) + - WARP_UCODE_SIZE(warp_g200_tgzf) + - WARP_UCODE_SIZE(warp_g200_tgzs) + - WARP_UCODE_SIZE(warp_g200_tgzsa) + - WARP_UCODE_SIZE(warp_g200_tgzsaf) + WARP_UCODE_SIZE(warp_g200_tgzsf)); - -unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv) +#define WARP_UCODE_SIZE(size) ALIGN(size, MGA_WARP_CODE_ALIGN) + +int mga_warp_install_microcode(drm_mga_private_t * dev_priv) { + unsigned char *vcbase = dev_priv->warp->handle; + unsigned long pcbase = dev_priv->warp->offset; + const char *firmware_name; + struct platform_device *pdev; + const struct firmware *fw = NULL; + const struct ihex_binrec *rec; + unsigned int size; + int n_pipes, where; + int rc = 0; + switch (dev_priv->chipset) { case MGA_CARD_TYPE_G400: case MGA_CARD_TYPE_G550: - return PAGE_ALIGN(mga_warp_g400_microcode_size); + firmware_name = FIRMWARE_G400; + n_pipes = MGA_MAX_G400_PIPES; + break; case MGA_CARD_TYPE_G200: - return PAGE_ALIGN(mga_warp_g200_microcode_size); + firmware_name = FIRMWARE_G200; + n_pipes = MGA_MAX_G200_PIPES; + break; default: - return 0; + return -EINVAL; } -} - -static int mga_warp_install_g400_microcode(drm_mga_private_t * dev_priv) -{ - unsigned char *vcbase = dev_priv->warp->handle; - unsigned long pcbase = dev_priv->warp->offset; - - memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); - - WARP_UCODE_INSTALL(warp_g400_tgz, MGA_WARP_TGZ); - WARP_UCODE_INSTALL(warp_g400_tgzf, MGA_WARP_TGZF); - WARP_UCODE_INSTALL(warp_g400_tgza, MGA_WARP_TGZA); - WARP_UCODE_INSTALL(warp_g400_tgzaf, MGA_WARP_TGZAF); - WARP_UCODE_INSTALL(warp_g400_tgzs, MGA_WARP_TGZS); - WARP_UCODE_INSTALL(warp_g400_tgzsf, MGA_WARP_TGZSF); - WARP_UCODE_INSTALL(warp_g400_tgzsa, MGA_WARP_TGZSA); - WARP_UCODE_INSTALL(warp_g400_tgzsaf, MGA_WARP_TGZSAF); - - WARP_UCODE_INSTALL(warp_g400_t2gz, MGA_WARP_T2GZ); - WARP_UCODE_INSTALL(warp_g400_t2gzf, MGA_WARP_T2GZF); - WARP_UCODE_INSTALL(warp_g400_t2gza, MGA_WARP_T2GZA); - WARP_UCODE_INSTALL(warp_g400_t2gzaf, MGA_WARP_T2GZAF); - WARP_UCODE_INSTALL(warp_g400_t2gzs, MGA_WARP_T2GZS); - WARP_UCODE_INSTALL(warp_g400_t2gzsf, MGA_WARP_T2GZSF); - WARP_UCODE_INSTALL(warp_g400_t2gzsa, MGA_WARP_T2GZSA); - WARP_UCODE_INSTALL(warp_g400_t2gzsaf, MGA_WARP_T2GZSAF); - - return 0; -} - -static int mga_warp_install_g200_microcode(drm_mga_private_t * dev_priv) -{ - unsigned char *vcbase = dev_priv->warp->handle; - unsigned long pcbase = dev_priv->warp->offset; - - memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); - - WARP_UCODE_INSTALL(warp_g200_tgz, MGA_WARP_TGZ); - WARP_UCODE_INSTALL(warp_g200_tgzf, MGA_WARP_TGZF); - WARP_UCODE_INSTALL(warp_g200_tgza, MGA_WARP_TGZA); - WARP_UCODE_INSTALL(warp_g200_tgzaf, MGA_WARP_TGZAF); - WARP_UCODE_INSTALL(warp_g200_tgzs, MGA_WARP_TGZS); - WARP_UCODE_INSTALL(warp_g200_tgzsf, MGA_WARP_TGZSF); - WARP_UCODE_INSTALL(warp_g200_tgzsa, MGA_WARP_TGZSA); - WARP_UCODE_INSTALL(warp_g200_tgzsaf, MGA_WARP_TGZSAF); - return 0; -} + pdev = platform_device_register_simple("mga_warp", 0, NULL, 0); + if (IS_ERR(pdev)) { + DRM_ERROR("mga: Failed to register microcode\n"); + return PTR_ERR(pdev); + } + rc = request_ihex_firmware(&fw, firmware_name, &pdev->dev); + platform_device_unregister(pdev); + if (rc) { + DRM_ERROR("mga: Failed to load microcode \"%s\"\n", + firmware_name); + return rc; + } -int mga_warp_install_microcode(drm_mga_private_t * dev_priv) -{ - const unsigned int size = mga_warp_microcode_size(dev_priv); + size = 0; + where = 0; + for (rec = (const struct ihex_binrec *)fw->data; + rec; + rec = ihex_next_binrec(rec)) { + size += WARP_UCODE_SIZE(be16_to_cpu(rec->len)); + where++; + } + if (where != n_pipes) { + DRM_ERROR("mga: Invalid microcode \"%s\"\n", firmware_name); + rc = -EINVAL; + goto out; + } + size = PAGE_ALIGN(size); DRM_DEBUG("MGA ucode size = %d bytes\n", size); if (size > dev_priv->warp->size) { DRM_ERROR("microcode too large! (%u > %lu)\n", size, dev_priv->warp->size); - return -ENOMEM; + rc = -ENOMEM; + goto out; } - switch (dev_priv->chipset) { - case MGA_CARD_TYPE_G400: - case MGA_CARD_TYPE_G550: - return mga_warp_install_g400_microcode(dev_priv); - case MGA_CARD_TYPE_G200: - return mga_warp_install_g200_microcode(dev_priv); - default: - return -EINVAL; + memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); + + where = 0; + for (rec = (const struct ihex_binrec *)fw->data; + rec; + rec = ihex_next_binrec(rec)) { + unsigned int src_size, dst_size; + + DRM_DEBUG(" pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase); + dev_priv->warp_pipe_phys[where] = pcbase; + src_size = be16_to_cpu(rec->len); + dst_size = WARP_UCODE_SIZE(src_size); + memcpy(vcbase, rec->data, src_size); + pcbase += dst_size; + vcbase += dst_size; + where++; } + +out: + release_firmware(fw); + return rc; } #define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE) diff --git a/firmware/Makefile b/firmware/Makefile index 621de8e..0e39f7e 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -42,6 +42,7 @@ fw-shipped-$(CONFIG_COMPUTONE) += intelliport2.bin fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \ cxgb3/t3c_psram-1.1.0.bin \ cxgb3/t3fw-7.4.0.bin +fw-shipped-$(CONFIG_DRM_MGA) += matrox/g200_warp.fw matrox/g400_warp.fw fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \ diff --git a/firmware/WHENCE b/firmware/WHENCE index 0f5649a..5db34a8 100644 --- a/firmware/WHENCE +++ b/firmware/WHENCE @@ -698,3 +698,35 @@ Found in hex form in kernel source, with the following comment: Copyright (c) 1998-2002 by Paul Davis -------------------------------------------------------------------------- + +Driver: mga - Matrox G200/G400/G550 + +File: matrox/g200_warp.fw +File: matrox/g400_warp.fw + +Licence: + +Copyright 1999 Matrox Graphics Inc. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Found in hex form in kernel source. + +-------------------------------------------------------------------------- diff --git a/firmware/matrox/g200_warp.H16 b/firmware/matrox/g200_warp.H16 new file mode 100644 index 0000000..5064b6f --- /dev/null +++ b/firmware/matrox/g200_warp.H16 @@ -0,0 +1,28 @@ +/* + * WARP pipes are named according to the functions they perform, where + * + * - T stands for computation of texture stage 0 + * - T2 stands for computation of both texture stage 0 and texture stage 1 + * - G stands for computation of triangle intensity (Gouraud interpolation) + * - Z stands for computation of Z buffer interpolation + * - S stands for computation of specular highlight + * - A stands for computation of the alpha channel + * - F stands for computation of vertex fog interpolation + */ +/* TGZ */ +:04B8000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E9728007EA241F20E9154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E2608015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E803800AEA17C12BBD008000E8008000E8B3689725008000E833C033AF3C274FE9573920E9281960EC2B3220E91D3B20E9B30500E0162820E9233B33AD1E2B20E91C8020E9573620E90080A0E94040D8ECFF80C0E990E200E085FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E884FF0AEA008000E8C941C8EC42E100E082FF20EA008000E8008000E8008000E8C840C0EC008000E87FFF20EA008000E8008000E8008000E871 +/* TGZF */ +:0548000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E97F8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E26B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E80D211AB6052131B603802AEA17C12BBD0D2005202FC021C6B3689725008000E833C033AF3C274FE91750569F008000E8370F5C9F00E02F20008000E8281960ECB30500E0008000E8233B33AD008000E8172617DF35174FE9008000E8008000E8008000E839374FE92F2F17AF008000E8008000E8008000E831804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E078FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E877FF0AEA008000E8C941C8EC42E100E075FF20EA008000E8008000E8008000E8C840C0EC008000E872FF20EA008000E8008000E8008000E8BB +/* TGZA */ +:04E80000000098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E97D8007EA241F20E9154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E26B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D444CB6254454B603802AEA17C12BBD2D20252007C044C6B3689725008000E833C033AF3C274FE91F62579F008000E83F3D5D9F00E00720008000E8281960ECB30500E0008000E8233B33AD008000E81F261FDF9D1F4FE9008000E8008000E8008000E89E3F4FE907071FAF008000E8008000E8008000E89C804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E07AFF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E879FF0AEA008000E8C941C8EC42E100E077FF20EA008000E8008000E8008000E8C840C0EC008000E874FF20EA008000E8008000E8008000E8D9 +/* TGZAF */ +:0568000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E9838007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E26F8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E80D211AB6052131B62D444CB6254454B603802AEA17C12BBD0D2005202FC021C6B3689725008000E833C033AF3C274FE900E0252007C044C61750569F00E02D20370F5C9F00E02F201F62579F00E007203F3D5D9F008000E8008000E8281960ECB30500E0172617DF233B33AD35174FE91F261FDF9D1F4FE99E3F4FE939374FE92F2F17AF008000E807071FAF008000E831804FE9008000E89C804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E074FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E873FF0AEA008000E8C941C8EC42E100E071FF20EA008000E8008000E8008000E8C840C0EC008000E86EFF20EA008000E8008000E8008000E830 +/* TGZS */ +:05C0000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E98B8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E2778015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F3F2F5D9F00E08F20A5374FE90F170FAF06C021C4008000E8008000E8A3804FE9062000E01F261FDFA11F4FE9A23F4FE9008000E8008000E806061FAF008000E8008000E8008000E8A0804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E06CFF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E86BFF0AEA008000E8C941C8EC42E100E069FF20EA008000E8008000E8008000E8C840C0EC008000E866FF20EA008000E8008000E8008000E85C +/* TGZSF */ +:05E0000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E98F8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E27B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC0D211AB6052131B6370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F0D2005202FC021C63F2F5D9F00E00F201750569FA5374FE906C021C40F170FAF370F5C9F008000E82F2000E0A3804FE9062000E01F261FDF172617DF35174FE9A11F4FE9A23F4FE906061FAF39374FE92F2F17AF008000E8A0804FE9008000E831804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E068FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E867FF0AEA008000E8C941C8EC42E100E065FF20EA008000E8008000E8008000E8C840C0EC008000E862FF20EA008000E8008000E8008000E8F9 +/* TGZSA */ +:05E0000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E98F8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E27B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC0D444CB6054454B6370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F0D200520008000E83F2F5D9F00E00F201750569FA5374FE906C021C40F170FAF370F5C9F008000E82FC044C6A3804FE9062000E01F261FDF172617DF9D174FE9A11F4FE9A23F4FE906061FAF00E0AF209E374FE92F172FAFA0804FE9008000E8008000E89C804FE9008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E068FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E867FF0AEA008000E8C941C8EC42E100E065FF20EA008000E8008000E8008000E8C840C0EC008000E862FF20EA008000E8008000E8008000E883 +/* TGZAF */ +:05B8000000008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E9948007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E2808015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC0D211AB6052131B6370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F0D2005202FC021C62D444CB6254454B63F2F5D9F00E00F202D20252007C044C61750569FA5374FE906C021C40F170FAF370F5C9F008000E81E62579F008000E83E3D5D9F00E007202F2000E0A30F4FE9062000E01F261FDF172617DFA11F4FE91E261EDF9D1E4FE935174FE9A23F4FE906061FAF39374FE92F2F17AF07071EAFA0804FE99E3E4FE931804FE99C804FE9008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E063FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E862FF0AEA008000E8C941C8EC42E100E060FF20EA008000E8008000E8008000E8C840C0EC008000E85DFF20EA008000E8008000E8008000E8D8 +:0000000001FF diff --git a/firmware/matrox/g400_warp.H16 b/firmware/matrox/g400_warp.H16 new file mode 100644 index 0000000..b432d10 --- /dev/null +++ b/firmware/matrox/g400_warp.H16 @@ -0,0 +1,44 @@ +/* + * WARP pipes are named according to the functions they perform, where + * + * - T stands for computation of texture stage 0 + * - T2 stands for computation of both texture stage 0 and texture stage 1 + * - G stands for computation of triangle intensity (Gouraud interpolation) + * - Z stands for computation of Z buffer interpolation + * - S stands for computation of specular highlight + * - A stands for computation of the alpha channel + * - F stands for computation of vertex fog interpolation + */ +/* TGZ */ +:0338000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC31003900588015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF4A8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E90A444CB0024454B02A444CB21A4454B21D803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F008000E82A444CB41A4454B439E52C9F383D20E988735EE92A201A202A464EBF1A4656BF31532F9F3E304FE939E52C9F3F384FE90A474FBF024757BF31532F9F3A314FE939E52C9F3B394FE92A434BBF1A4353BF30502E9F36314FE938212C9F37394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9AFFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFD6FF20EA008000E84E334ECF573B57CF9DFF20EA57C0BFEA0080A0E90000D8EC59 +/* TGZF */ +:0360000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039005D8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF4F8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C439E52C9F348020E931532F9F008000E888735EE9008000E827CF75C63C3D20E90A444CB0024454B02A444CB21A4454B220803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F312720E90A444CB4024454B42A454DB61A4555B639E52C9F383D20E90A2002202A201A200A474FBF024757BF30502E9F3E304FE938212C9F3F384FE92A464EBF1A4656BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A434BBF1A4353BF30502E9F35314FE938212C9F39394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9AAFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFD3FF20EA008000E84E334ECF573B57CF98FF20EA57C0BFEA0080A0E90000D8EC90 +/* TGZA */ +:0358000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039005C8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF4E8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E927CF74C63DCF74C20A444CB0024454B02A444CB21A4454B220803AEA0A20022088735EE92A201A2030502E9F32315FE938212C9F33395FE931532F9F9C2720E90A444CB4024454B42A444CB61A4454B639E52C9F383D20E90A2002202A201A200A474FBF024757BF30502E9F3E304FE938212C9F3F384FE92A464EBF1A4656BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A434BBF1A4353BF30502E9F9D314FE938212C9F9E394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9ABFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFD3FF20EA008000E84E334ECF573B57CF99FF20EA57C0BFEA0080A0E90000D8EC35 +/* TGZAF */ +:0380000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC31003900618015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF538007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C40A444CB0024454B031532F9F343720E939E52C9F3C3D20E92A444CB21A4454B226803AEA0A20022088735EE92A201A203DCF74C227CF74C630502E9F32315FE938212C9F33395FE931532F9F9C2720E90A444CB4024454B42A444CB61A4454B639E52C9F383D20E90A2002202A201A203DCF75C6008000E830502E9F3E304FE938212C9F3F384FE90A454DB6024555B631532F9F3A314FE939E52C9F3B394FE9313D20E90A2002202A464EBF1A4656BF0A474FBF024757BF30502E9F36304FE938212C9F37384FE931532F9F9D314FE939E52C9F9E394FE92A434BBF1A4353BF30502E9F35304FE938212C9F39384FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9A6FF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFCDFF20EA008000E84E334ECF573B57CF94FF20EA57C0BFEA0080A0E90000D8EC89 +/* TGZS */ +:03A0000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC31003900658015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF578007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B229803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE92A454DB21A4555B20A454DB4024555B438212C9F3B394FE90A2002202A201A202A464EBF1A4656BF31532F9F36314FE939E52C9F37394FE930502E9FA7304FE938212C9FA8384FE90A474FBF024757BF31532F9FA4314FE939E52C9FA5394FE92A434BBF1A4353BF30502E9FA1304FE938212C9FA2384FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9A2FF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFCAFF20EA008000E84E334ECF573B57CF90FF20EA57C0BFEA0080A0E90000D8ECD8 +/* TGZSF */ +:03C8000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039006A8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF5C8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B22E803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A454DB21A4555B20A454DB4024555B427CF75C62A201A20A7304FE90A20022031532F9F312720E939E52C9FA8384FE92A454DB61A4555B630502E9F36314FE938212C9F37394FE9008000E82A201A202A464EBF1A4656BF31532F9FA4314FE939E52C9FA5394FE90A474FBF024757BF31532F9FA1304FE939E52C9FA2384FE92A434BBF1A4353BF30502E9F35314FE938212C9F39394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E99DFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFC5FF20EA008000E84E334ECF573B57CF8BFF20EA57C0BFEA0080A0E90000D8ECD3 +/* TGZSA */ +:03C8000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039006A8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF5C8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B22E803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A454DB21A4555B20A454DB4024555B427CF74C62A201A20A7304FE90A20022031532F9F9C2720E939E52C9FA8384FE92A444CB61A4454B630502E9F36314FE938212C9F37394FE9008000E82A201A202A464EBF1A4656BF31532F9FA4314FE939E52C9FA5394FE90A474FBF024757BF31532F9FA1304FE939E52C9FA2384FE92A434BBF1A4353BF30502E9F9D314FE938212C9F9E394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E99DFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFC5FF20EA008000E84E334ECF573B57CF8BFF20EA57C0BFEA0080A0E90000D8ECA0 +/* TGZSAF */ +:03E8000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039006E8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF608007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B232803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A454DB21A4555B20A454DB4024555B427CF74C62A201A20A7304FE90A20022031532F9F9C2720E939E52C9FA8384FE92A444CB61A4454B630502E9F36314FE938212C9F37394FE90A454DB6024555B63DCF75C62A201A202A464EBF1A4656BF31532F9FA4314FE939E52C9FA5394FE9313D20E90A2002200A474FBF024757BF30502E9FA1304FE938212C9FA2384FE931532F9F9D314FE939E52C9F9E394FE92A434BBF1A4353BF30502E9F35304FE938212C9F39384FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E999FF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFC1FF20EA008000E84E334ECF573B57CF87FF20EA57C0BFEA0080A0E90000D8EC83 +/* T2GZ */ +:0438000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC31003900788015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF698007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E90A4454B0024464B02A4454B21A4464B225803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F008000E82A4454B41A4464B439E52C9F383D20E988735EE92A201A202A4656BF1A4666BF31532F9F3E304FE939E52C9F3F384FE90A4757BF024767BF31532F9F3A314FE939E52C9F3B394FE92A4353BF1A4363BF30502E9F36314FE938212C9F37394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E99FFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFBEFF20EA008000E8583358CF693B69CF7DFF20EA57C0BFEA0080A0E90000D8ECAC +/* T2GZF */ +:0460000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039007D8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF6E8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C439E52C9F348020E931532F9F008000E888735EE9008000E80FCF75C63C3D20E90A4454B0024464B02A4454B21A4464B228803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F310F20E90A4454B4024464B42A4555B61A4565B639E52C9F383D20E90A2002202A201A200A4757BF024767BF30502E9F3E304FE938212C9F3F384FE92A4656BF1A4666BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A4353BF1A4363BF30502E9F35314FE938212C9F39394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E99AFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFBBFF20EA008000E8583358CF693B69CF78FF20EA57C0BFEA0080A0E90000D8ECFB +/* T2GZA */ +:0458000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039007C8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF6D8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E90A4454B0024464B02A4454B21A4464B229803AEA0A2002200FCF74C63DCF74C288735EE92A201A2030502E9F32315FE938212C9F33395FE931532F9F9C0F20E90A4454B4024464B42A4454B61A4464B639E52C9F383D20E90A2002202A201A200A4757BF024767BF30502E9F3E304FE938212C9F3F384FE92A4656BF1A4666BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A4353BF1A4363BF30502E9F9D314FE938212C9F9E394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E99BFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFBAFF20EA008000E8583358CF693B69CF79FF20EA57C0BFEA0080A0E90000D8ECA0 +/* T2GZAF */ +:0480000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC31003900818015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF728007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C40A4454B0024464B031532F9F343720E939E52C9F3C3D20E92A4454B21A4464B22E803AEA0A20022088735EE92A201A203DCF74C20FCF74C630502E9F32315FE938212C9F33395FE931532F9F9C0F20E90A4454B4024464B42A4454B61A4464B639E52C9F383D20E90A2002202A201A203DCF75C6008000E830502E9F3E304FE938212C9F3F384FE90A4555B6024565B631532F9F3A314FE939E52C9F3B394FE9313D20E90A2002202A4656BF1A4666BF0A4757BF024767BF30502E9F36304FE938212C9F37384FE931532F9F9D314FE939E52C9F9E394FE92A4353BF1A4363BF30502E9F35304FE938212C9F39384FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E996FF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFB5FF20EA008000E8583358CF693B69CF74FF20EA57C0BFEA0080A0E90000D8ECDC +/* T2GZS */ +:04A0000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC31003900858015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF768007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B231803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE92A4555B21A4565B20A4555B4024565B438212C9F3B394FE92A201A200A2002202A4656BF1A4666BF31532F9F36314FE939E52C9F37394FE930502E9FA7304FE938212C9FA8384FE90A4757BF024767BF31532F9FA4314FE939E52C9FA5394FE92A4353BF1A4363BF30502E9FA1304FE938212C9FA2384FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E992FF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFB2FF20EA008000E8583358CF693B69CF70FF20EA57C0BFEA0080A0E90000D8EC43 +/* T2GZSF */ +:04C8000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039008A8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF7B8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B236803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A4555B21A4565B20A4555B4024565B40FCF75C62A201A20A7304FE90A20022031532F9F310F20E939E52C9FA8384FE92A4555B61A4565B630502E9F36314FE938212C9F37394FE9008000E82A201A202A4656BF1A4666BF31532F9FA4314FE939E52C9FA5394FE90A4757BF024767BF31532F9FA1304FE939E52C9FA2384FE92A4353BF1A4363BF30502E9F35314FE938212C9F39394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E98DFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFADFF20EA008000E8583358CF693B69CF6BFF20EA57C0BFEA0080A0E90000D8EC56 +/* T2GZSA */ +:04C8000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039008A8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF7B8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B236803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A4555B21A4565B20A4555B4024565B40FCF74C62A201A20A7304FE90A20022031532F9F9C0F20E939E52C9FA8384FE92A4454B61A4464B630502E9F36314FE938212C9F37394FE9008000E82A201A202A4656BF1A4666BF31532F9FA4314FE939E52C9FA5394FE90A4757BF024767BF31532F9FA1304FE939E52C9FA2384FE92A4353BF1A4363BF30502E9F9D314FE938212C9F9E394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E98DFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFADFF20EA008000E8583358CF693B69CF6BFF20EA57C0BFEA0080A0E90000D8EC23 +/* T2GZSAF */ +:04E8000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039008E8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF7F8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B23A803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A4555B21A4565B20A4555B4024565B40FCF74C62A201A20A7304FE90A20022031532F9F9C0F20E939E52C9FA8384FE92A4454B61A4464B630502E9F36314FE938212C9F37394FE90A4555B6024565B63DCF75C62A201A202A4656BF1A4666BF31532F9FA4314FE939E52C9FA5394FE9313D20E90A2002200A4757BF024767BF30502E9FA1304FE938212C9FA2384FE931532F9F9D314FE939E52C9F9E394FE92A4353BF1A4363BF30502E9F35304FE938212C9F39384FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E989FF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFA9FF20EA008000E8583358CF693B69CF67FF20EA57C0BFEA0080A0E90000D8ECEE +:0000000001FF -- cgit v0.10.2 From 52f97df5da1f94d2b7db1bb53a2f053ae162b649 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Sun, 23 Aug 2009 18:37:26 +0100 Subject: drm/r128: Use request_firmware() to load CCE microcode Firmware blob looks like this: __be32 datah __be32 datal Signed-off-by: Ben Hutchings Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 10edc9b..a07abb8 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -36,6 +36,7 @@ config DRM_TDFX config DRM_R128 tristate "ATI Rage 128" depends on DRM && PCI + select FW_LOADER help Choose this option if you have an ATI Rage 128 graphics card. If M is selected, the module will be called r128. AGP support for diff --git a/drivers/gpu/drm/r128/r128_cce.c b/drivers/gpu/drm/r128/r128_cce.c index c75fd35..15252f6 100644 --- a/drivers/gpu/drm/r128/r128_cce.c +++ b/drivers/gpu/drm/r128/r128_cce.c @@ -29,6 +29,9 @@ * Gareth Hughes */ +#include +#include + #include "drmP.h" #include "drm.h" #include "r128_drm.h" @@ -36,50 +39,9 @@ #define R128_FIFO_DEBUG 0 -/* CCE microcode (from ATI) */ -static u32 r128_cce_microcode[] = { - 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, - 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, - 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, - 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, - 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, - 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, - 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, - 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, - 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, - 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, - 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, - 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, - 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, - 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, - 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, - 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, - 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, - 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, - 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, - 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, - 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, - 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, - 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, - 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, - 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, - 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, - 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, - 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, - 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, - 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, - 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, - 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, - 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, - 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, - 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; +#define FIRMWARE_NAME "r128/r128_cce.bin" + +MODULE_FIRMWARE(FIRMWARE_NAME); static int R128_READ_PLL(struct drm_device * dev, int addr) { @@ -176,20 +138,50 @@ static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) */ /* Load the microcode for the CCE */ -static void r128_cce_load_microcode(drm_r128_private_t * dev_priv) +static int r128_cce_load_microcode(drm_r128_private_t *dev_priv) { - int i; + struct platform_device *pdev; + const struct firmware *fw; + const __be32 *fw_data; + int rc, i; DRM_DEBUG("\n"); + pdev = platform_device_register_simple("r128_cce", 0, NULL, 0); + if (IS_ERR(pdev)) { + printk(KERN_ERR "r128_cce: Failed to register firmware\n"); + return PTR_ERR(pdev); + } + rc = request_firmware(&fw, FIRMWARE_NAME, &pdev->dev); + platform_device_unregister(pdev); + if (rc) { + printk(KERN_ERR "r128_cce: Failed to load firmware \"%s\"\n", + FIRMWARE_NAME); + return rc; + } + + if (fw->size != 256 * 8) { + printk(KERN_ERR + "r128_cce: Bogus length %zu in firmware \"%s\"\n", + fw->size, FIRMWARE_NAME); + rc = -EINVAL; + goto out_release; + } + r128_do_wait_for_idle(dev_priv); + fw_data = (const __be32 *)fw->data; R128_WRITE(R128_PM4_MICROCODE_ADDR, 0); for (i = 0; i < 256; i++) { - R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]); + R128_WRITE(R128_PM4_MICROCODE_DATAH, + be32_to_cpup(&fw_data[i * 2])); R128_WRITE(R128_PM4_MICROCODE_DATAL, - r128_cce_microcode[i * 2 + 1]); + be32_to_cpup(&fw_data[i * 2 + 1])); } + +out_release: + release_firmware(fw); + return rc; } /* Flush any pending commands to the CCE. This should only be used just @@ -350,6 +342,7 @@ static void r128_cce_init_ring_buffer(struct drm_device * dev, static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) { drm_r128_private_t *dev_priv; + int rc; DRM_DEBUG("\n"); @@ -575,13 +568,18 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) #endif r128_cce_init_ring_buffer(dev, dev_priv); - r128_cce_load_microcode(dev_priv); + rc = r128_cce_load_microcode(dev_priv); dev->dev_private = (void *)dev_priv; r128_do_engine_reset(dev); - return 0; + if (rc) { + DRM_ERROR("Failed to load firmware!\n"); + r128_do_cleanup_cce(dev); + } + + return rc; } int r128_do_cleanup_cce(struct drm_device * dev) diff --git a/firmware/Makefile b/firmware/Makefile index 0e39f7e..6ea4e3d 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -43,6 +43,7 @@ fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \ cxgb3/t3c_psram-1.1.0.bin \ cxgb3/t3fw-7.4.0.bin fw-shipped-$(CONFIG_DRM_MGA) += matrox/g200_warp.fw matrox/g400_warp.fw +fw-shipped-$(CONFIG_DRM_R128) += r128/r128_cce.bin fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \ diff --git a/firmware/WHENCE b/firmware/WHENCE index 5db34a8..578d859 100644 --- a/firmware/WHENCE +++ b/firmware/WHENCE @@ -730,3 +730,34 @@ OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Found in hex form in kernel source. -------------------------------------------------------------------------- + +Driver: r128 - ATI Rage 128 + +File: r128/r128_cce.bin + +Licence: + +Copyright 2000 Advanced Micro Devices, Inc. + + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + +Found in decimal form in kernel source. + +-------------------------------------------------------------------------- diff --git a/firmware/r128/r128_cce.bin.ihex b/firmware/r128/r128_cce.bin.ihex new file mode 100644 index 0000000..4831315 --- /dev/null +++ b/firmware/r128/r128_cce.bin.ihex @@ -0,0 +1,129 @@ +:1000000000000000108038000000000010003800E0 +:10001000000000020000008E0000000200000091BD +:1000200000000000402E2423000000006062124FF8 +:10003000000000002E2B596D000000007677753E01 +:1000400000000000898984820000000023BC8B0D21 +:10005000000000002323232300000000238DABB405 +:1000600000000000232323230000000100B028002B +:100070000000000100032800000000010004C0008F +:100080000000000100030800000000023660300E8E +:100090000000000B00040000000000000000000051 +:1000A000000000010200151D0000000100001D0EEF +:1000B00000000001000039D900000001000019D73C +:1000C0000000000C0000001C00000001000019D618 +:1000D0000000000C0000001C0000000200000017DF +:1000E0000000000B01200000000000000100358A24 +:1000F0000000000100064000000000090000001E92 +:100100000000000108D015B4000000101910100004 +:100110000000000300002000000000000000280094 +:1001200000000001000308000000000100003D0E77 +:10013000000000010000C8000000000A0000882A3A +:10014000000000090000002A000000010200150F55 +:1001500000000002000028240000000100003D65AE +:100160000000000100003D66000000020000002BBE +:100170000000000100F32DB4000000012200D8BFF0 +:100180000000000100E088BF0000000C1333383786 +:1001900000000001020615650000000C0000003799 +:1001A00000000001020015640000000100003D662F +:1001B000000000020000002E000000040020083AA9 +:1001C0000000000100080800000000010006C0FF58 +:1001D000000000040040003D000000010007C800CE +:1001E00000000001000700FF000000030000000005 +:1001F0000000000C0000005C000000020000002E67 +:100200000000000C000000B00000000100003D767E +:100210000000000100032800000000010000480069 +:1002200000000001000208000000000106001D0E91 +:1002300000000001000248000000000100028800E8 +:100240000000000100F3C5F80000000100100000EC +:10025000000000060030004E0000000100003D6379 +:100260000000001080303DF0000000021000384314 +:1002700000000002000028430000000C000000B055 +:100280000000000100003D760000000100003D7705 +:100290000000000100003D0E0000000100003D0FC5 +:1002A000000000010050280000000006003000524D +:1002B0000000001080303DF00000000100003DF81B +:1002C00000000002000000520000000100053D0E89 +:1002D0000000000100103D0F00000002003000553A +:1002E0000000000100003D700000000100001E89B8 +:1002F0000000000100003D710000000300003D729D +:100300000000000C0000005C000000020000006221 +:100310000000000100003F280000000100003F270E +:100320000000000100003E820000000100003E8845 +:100330000000000100003E660000000100003E6772 +:100340000000000100003E760000000100003E6851 +:100350000000000100003E690000000100003E6C4A +:100360000000000000003E6D0000000100002800B9 +:1003700000000001005028000000000100003D685E +:100380000000000100030800000000060000006EED +:10039000000000010002C0000000000106303D62C4 +:1003A0000000000200000070000000020030006F3A +:1003B00000000000200038C0000000010001C0C0A3 +:1003C0000000000E0000007D0000000C0003287FEC +:1003D00000000001020015BB0000000C00030880B3 +:1003E0000000000002003DBC0000000100003DBB19 +:1003F0000000000000003DBC00000003000480007D +:100400000000000100048000000000030006C0029C +:100410000000000100B0280000000000306038003B +:100420000000000100C028000000000100B008002A +:100430000000000100D600000000000712801086B6 +:10044000000000000000280000000001000039CC7E +:1004500000000001000039CD00000001000039C992 +:1004600000000001000039CA00000000000039CB84 +:10047000000000011003B80000000001009000001F +:100480000000000110003800000000010003080017 +:100490000000000100903D1B0000000140203D0ACB +:1004A0000000000140203D0B00000001000880001A +:1004B000000000010001C0C00000000E0000009F0D +:1004C0000000000C000308800000000142203DBD38 +:1004D0000000000C0003087F0000000142003DBB4B +:1004E0000000000C000308800000000142203DBC19 +:1004F00000000002000000A20000000140203DBDFD +:100500000000000140003DBB0000000140203DBC58 +:1005100000000001000840000000000100A00000F1 +:1005200000000006003000A6000000101060380037 +:1005300000000009000000A80000000300400000C7 +:100540000000000300403D1D00000000000000000E +:1005500000000000000001000000000E000000AEDE +:10056000000000010001C0A900000001020015C741 +:100570000000000C000000B0000000000000280097 +:10058000000000010001C0AA00000001020015D215 +:10059000000000010001C0A900000003020015C70F +:1005A0000000000100003E88000000010001C0BA08 +:1005B0000000000102001728000000010001C0BB7C +:1005C000000000010200165A0000000000003E5B1F +:1005D000000000000000010000000000000010000A +:1005E000000000010006400B00000009000000BCF4 +:1005F00000000000000028000000000000000000D3 +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF -- cgit v0.10.2 From 3f7dc91adef90a20f806282724c40d68d5b020aa Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 27 Aug 2009 11:10:15 +1000 Subject: drm/rs600/690: use autogenerated safe register tables. This ports rs690 to the safe reg tables and makes rs600 also use the same table. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 8e17718..b2213a5 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -17,10 +17,15 @@ $(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable $(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable $(call if_changed,mkregtable) +$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable + $(call if_changed,mkregtable) + $(obj)/rv515.o: $(obj)/rv515_reg_safe.h $(obj)/r300.o: $(obj)/r300_reg_safe.h +$(obj)/rs600.o: $(obj)/rs600_reg_safe.h + radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \ radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \ atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \ diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 7ca6c13..8ace151 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -266,6 +266,7 @@ static struct radeon_asic rs400_asic = { /* * rs600. */ +int rs600_init(struct radeon_device *rdev); void rs600_errata(struct radeon_device *rdev); void rs600_vram_info(struct radeon_device *rdev); int rs600_mc_init(struct radeon_device *rdev); @@ -281,7 +282,7 @@ uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); void rs600_bandwidth_update(struct radeon_device *rdev); static struct radeon_asic rs600_asic = { - .init = &r300_init, + .init = &rs600_init, .errata = &rs600_errata, .vram_info = &rs600_vram_info, .gpu_reset = &r300_gpu_reset, @@ -316,7 +317,6 @@ static struct radeon_asic rs600_asic = { /* * rs690,rs740 */ -int rs690_init(struct radeon_device *rdev); void rs690_errata(struct radeon_device *rdev); void rs690_vram_info(struct radeon_device *rdev); int rs690_mc_init(struct radeon_device *rdev); @@ -325,7 +325,7 @@ uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); void rs690_bandwidth_update(struct radeon_device *rdev); static struct radeon_asic rs690_asic = { - .init = &rs690_init, + .init = &rs600_init, .errata = &rs690_errata, .vram_info = &rs690_vram_info, .gpu_reset = &r300_gpu_reset, diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600 new file mode 100644 index 0000000..498c581 --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/rs600 @@ -0,0 +1,728 @@ +rs600 0x6d40 +0x1434 SRC_Y_X +0x1438 DST_Y_X +0x143C DST_HEIGHT_WIDTH +0x146C DP_GUI_MASTER_CNTL +0x1474 BRUSH_Y_X +0x1478 DP_BRUSH_BKGD_CLR +0x147C DP_BRUSH_FRGD_CLR +0x1480 BRUSH_DATA0 +0x1484 BRUSH_DATA1 +0x1598 DST_WIDTH_HEIGHT +0x15C0 CLR_CMP_CNTL +0x15C4 CLR_CMP_CLR_SRC +0x15C8 CLR_CMP_CLR_DST +0x15CC CLR_CMP_MSK +0x15D8 DP_SRC_FRGD_CLR +0x15DC DP_SRC_BKGD_CLR +0x1600 DST_LINE_START +0x1604 DST_LINE_END +0x1608 DST_LINE_PATCOUNT +0x16C0 DP_CNTL +0x16CC DP_WRITE_MSK +0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR +0x16E8 DEFAULT_SC_BOTTOM_RIGHT +0x16EC SC_TOP_LEFT +0x16F0 SC_BOTTOM_RIGHT +0x16F4 SRC_SC_BOTTOM_RIGHT +0x1714 DSTCACHE_CTLSTAT +0x1720 WAIT_UNTIL +0x172C RBBM_GUICNTL +0x1D98 VAP_VPORT_XSCALE +0x1D9C VAP_VPORT_XOFFSET +0x1DA0 VAP_VPORT_YSCALE +0x1DA4 VAP_VPORT_YOFFSET +0x1DA8 VAP_VPORT_ZSCALE +0x1DAC VAP_VPORT_ZOFFSET +0x2080 VAP_CNTL +0x2090 VAP_OUT_VTX_FMT_0 +0x2094 VAP_OUT_VTX_FMT_1 +0x20B0 VAP_VTE_CNTL +0x2138 VAP_VF_MIN_VTX_INDX +0x2140 VAP_CNTL_STATUS +0x2150 VAP_PROG_STREAM_CNTL_0 +0x2154 VAP_PROG_STREAM_CNTL_1 +0x2158 VAP_PROG_STREAM_CNTL_2 +0x215C VAP_PROG_STREAM_CNTL_3 +0x2160 VAP_PROG_STREAM_CNTL_4 +0x2164 VAP_PROG_STREAM_CNTL_5 +0x2168 VAP_PROG_STREAM_CNTL_6 +0x216C VAP_PROG_STREAM_CNTL_7 +0x2180 VAP_VTX_STATE_CNTL +0x2184 VAP_VSM_VTX_ASSM +0x2188 VAP_VTX_STATE_IND_REG_0 +0x218C VAP_VTX_STATE_IND_REG_1 +0x2190 VAP_VTX_STATE_IND_REG_2 +0x2194 VAP_VTX_STATE_IND_REG_3 +0x2198 VAP_VTX_STATE_IND_REG_4 +0x219C VAP_VTX_STATE_IND_REG_5 +0x21A0 VAP_VTX_STATE_IND_REG_6 +0x21A4 VAP_VTX_STATE_IND_REG_7 +0x21A8 VAP_VTX_STATE_IND_REG_8 +0x21AC VAP_VTX_STATE_IND_REG_9 +0x21B0 VAP_VTX_STATE_IND_REG_10 +0x21B4 VAP_VTX_STATE_IND_REG_11 +0x21B8 VAP_VTX_STATE_IND_REG_12 +0x21BC VAP_VTX_STATE_IND_REG_13 +0x21C0 VAP_VTX_STATE_IND_REG_14 +0x21C4 VAP_VTX_STATE_IND_REG_15 +0x21DC VAP_PSC_SGN_NORM_CNTL +0x21E0 VAP_PROG_STREAM_CNTL_EXT_0 +0x21E4 VAP_PROG_STREAM_CNTL_EXT_1 +0x21E8 VAP_PROG_STREAM_CNTL_EXT_2 +0x21EC VAP_PROG_STREAM_CNTL_EXT_3 +0x21F0 VAP_PROG_STREAM_CNTL_EXT_4 +0x21F4 VAP_PROG_STREAM_CNTL_EXT_5 +0x21F8 VAP_PROG_STREAM_CNTL_EXT_6 +0x21FC VAP_PROG_STREAM_CNTL_EXT_7 +0x2200 VAP_PVS_VECTOR_INDX_REG +0x2204 VAP_PVS_VECTOR_DATA_REG +0x2208 VAP_PVS_VECTOR_DATA_REG_128 +0x221C VAP_CLIP_CNTL +0x2220 VAP_GB_VERT_CLIP_ADJ +0x2224 VAP_GB_VERT_DISC_ADJ +0x2228 VAP_GB_HORZ_CLIP_ADJ +0x222C VAP_GB_HORZ_DISC_ADJ +0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0 +0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1 +0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2 +0x223C VAP_PVS_FLOW_CNTL_ADDRS_3 +0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4 +0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5 +0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6 +0x224C VAP_PVS_FLOW_CNTL_ADDRS_7 +0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8 +0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9 +0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10 +0x225C VAP_PVS_FLOW_CNTL_ADDRS_11 +0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12 +0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13 +0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14 +0x226C VAP_PVS_FLOW_CNTL_ADDRS_15 +0x2284 VAP_PVS_STATE_FLUSH_REG +0x2288 VAP_PVS_VTX_TIMEOUT_REG +0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 +0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1 +0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2 +0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3 +0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4 +0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5 +0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6 +0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7 +0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8 +0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9 +0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10 +0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11 +0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12 +0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13 +0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14 +0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15 +0x22D0 VAP_PVS_CODE_CNTL_0 +0x22D4 VAP_PVS_CONST_CNTL +0x22D8 VAP_PVS_CODE_CNTL_1 +0x22DC VAP_PVS_FLOW_CNTL_OPC +0x342C RB2D_DSTCACHE_CTLSTAT +0x4000 GB_VAP_RASTER_VTX_FMT_0 +0x4004 GB_VAP_RASTER_VTX_FMT_1 +0x4008 GB_ENABLE +0x401C GB_SELECT +0x4020 GB_AA_CONFIG +0x4024 GB_FIFO_SIZE +0x4100 TX_INVALTAGS +0x4200 GA_POINT_S0 +0x4204 GA_POINT_T0 +0x4208 GA_POINT_S1 +0x420C GA_POINT_T1 +0x4214 GA_TRIANGLE_STIPPLE +0x421C GA_POINT_SIZE +0x4230 GA_POINT_MINMAX +0x4234 GA_LINE_CNTL +0x4238 GA_LINE_STIPPLE_CONFIG +0x4260 GA_LINE_STIPPLE_VALUE +0x4264 GA_LINE_S0 +0x4268 GA_LINE_S1 +0x4278 GA_COLOR_CONTROL +0x427C GA_SOLID_RG +0x4280 GA_SOLID_BA +0x4288 GA_POLY_MODE +0x428C GA_ROUND_MODE +0x4290 GA_OFFSET +0x4294 GA_FOG_SCALE +0x4298 GA_FOG_OFFSET +0x42A0 SU_TEX_WRAP +0x42A4 SU_POLY_OFFSET_FRONT_SCALE +0x42A8 SU_POLY_OFFSET_FRONT_OFFSET +0x42AC SU_POLY_OFFSET_BACK_SCALE +0x42B0 SU_POLY_OFFSET_BACK_OFFSET +0x42B4 SU_POLY_OFFSET_ENABLE +0x42B8 SU_CULL_MODE +0x42C0 SU_DEPTH_SCALE +0x42C4 SU_DEPTH_OFFSET +0x42C8 SU_REG_DEST +0x4300 RS_COUNT +0x4304 RS_INST_COUNT +0x4310 RS_IP_0 +0x4314 RS_IP_1 +0x4318 RS_IP_2 +0x431C RS_IP_3 +0x4320 RS_IP_4 +0x4324 RS_IP_5 +0x4328 RS_IP_6 +0x432C RS_IP_7 +0x4330 RS_INST_0 +0x4334 RS_INST_1 +0x4338 RS_INST_2 +0x433C RS_INST_3 +0x4340 RS_INST_4 +0x4344 RS_INST_5 +0x4348 RS_INST_6 +0x434C RS_INST_7 +0x4350 RS_INST_8 +0x4354 RS_INST_9 +0x4358 RS_INST_10 +0x435C RS_INST_11 +0x4360 RS_INST_12 +0x4364 RS_INST_13 +0x4368 RS_INST_14 +0x436C RS_INST_15 +0x43A4 SC_HYPERZ_EN +0x43A8 SC_EDGERULE +0x43B0 SC_CLIP_0_A +0x43B4 SC_CLIP_0_B +0x43B8 SC_CLIP_1_A +0x43BC SC_CLIP_1_B +0x43C0 SC_CLIP_2_A +0x43C4 SC_CLIP_2_B +0x43C8 SC_CLIP_3_A +0x43CC SC_CLIP_3_B +0x43D0 SC_CLIP_RULE +0x43E0 SC_SCISSOR0 +0x43E8 SC_SCREENDOOR +0x4440 TX_FILTER1_0 +0x4444 TX_FILTER1_1 +0x4448 TX_FILTER1_2 +0x444C TX_FILTER1_3 +0x4450 TX_FILTER1_4 +0x4454 TX_FILTER1_5 +0x4458 TX_FILTER1_6 +0x445C TX_FILTER1_7 +0x4460 TX_FILTER1_8 +0x4464 TX_FILTER1_9 +0x4468 TX_FILTER1_10 +0x446C TX_FILTER1_11 +0x4470 TX_FILTER1_12 +0x4474 TX_FILTER1_13 +0x4478 TX_FILTER1_14 +0x447C TX_FILTER1_15 +0x4580 TX_CHROMA_KEY_0 +0x4584 TX_CHROMA_KEY_1 +0x4588 TX_CHROMA_KEY_2 +0x458C TX_CHROMA_KEY_3 +0x4590 TX_CHROMA_KEY_4 +0x4594 TX_CHROMA_KEY_5 +0x4598 TX_CHROMA_KEY_6 +0x459C TX_CHROMA_KEY_7 +0x45A0 TX_CHROMA_KEY_8 +0x45A4 TX_CHROMA_KEY_9 +0x45A8 TX_CHROMA_KEY_10 +0x45AC TX_CHROMA_KEY_11 +0x45B0 TX_CHROMA_KEY_12 +0x45B4 TX_CHROMA_KEY_13 +0x45B8 TX_CHROMA_KEY_14 +0x45BC TX_CHROMA_KEY_15 +0x45C0 TX_BORDER_COLOR_0 +0x45C4 TX_BORDER_COLOR_1 +0x45C8 TX_BORDER_COLOR_2 +0x45CC TX_BORDER_COLOR_3 +0x45D0 TX_BORDER_COLOR_4 +0x45D4 TX_BORDER_COLOR_5 +0x45D8 TX_BORDER_COLOR_6 +0x45DC TX_BORDER_COLOR_7 +0x45E0 TX_BORDER_COLOR_8 +0x45E4 TX_BORDER_COLOR_9 +0x45E8 TX_BORDER_COLOR_10 +0x45EC TX_BORDER_COLOR_11 +0x45F0 TX_BORDER_COLOR_12 +0x45F4 TX_BORDER_COLOR_13 +0x45F8 TX_BORDER_COLOR_14 +0x45FC TX_BORDER_COLOR_15 +0x4600 US_CONFIG +0x4604 US_PIXSIZE +0x4608 US_CODE_OFFSET +0x460C US_RESET +0x4610 US_CODE_ADDR_0 +0x4614 US_CODE_ADDR_1 +0x4618 US_CODE_ADDR_2 +0x461C US_CODE_ADDR_3 +0x4620 US_TEX_INST_0 +0x4624 US_TEX_INST_1 +0x4628 US_TEX_INST_2 +0x462C US_TEX_INST_3 +0x4630 US_TEX_INST_4 +0x4634 US_TEX_INST_5 +0x4638 US_TEX_INST_6 +0x463C US_TEX_INST_7 +0x4640 US_TEX_INST_8 +0x4644 US_TEX_INST_9 +0x4648 US_TEX_INST_10 +0x464C US_TEX_INST_11 +0x4650 US_TEX_INST_12 +0x4654 US_TEX_INST_13 +0x4658 US_TEX_INST_14 +0x465C US_TEX_INST_15 +0x4660 US_TEX_INST_16 +0x4664 US_TEX_INST_17 +0x4668 US_TEX_INST_18 +0x466C US_TEX_INST_19 +0x4670 US_TEX_INST_20 +0x4674 US_TEX_INST_21 +0x4678 US_TEX_INST_22 +0x467C US_TEX_INST_23 +0x4680 US_TEX_INST_24 +0x4684 US_TEX_INST_25 +0x4688 US_TEX_INST_26 +0x468C US_TEX_INST_27 +0x4690 US_TEX_INST_28 +0x4694 US_TEX_INST_29 +0x4698 US_TEX_INST_30 +0x469C US_TEX_INST_31 +0x46A4 US_OUT_FMT_0 +0x46A8 US_OUT_FMT_1 +0x46AC US_OUT_FMT_2 +0x46B0 US_OUT_FMT_3 +0x46B4 US_W_FMT +0x46C0 US_ALU_RGB_ADDR_0 +0x46C4 US_ALU_RGB_ADDR_1 +0x46C8 US_ALU_RGB_ADDR_2 +0x46CC US_ALU_RGB_ADDR_3 +0x46D0 US_ALU_RGB_ADDR_4 +0x46D4 US_ALU_RGB_ADDR_5 +0x46D8 US_ALU_RGB_ADDR_6 +0x46DC US_ALU_RGB_ADDR_7 +0x46E0 US_ALU_RGB_ADDR_8 +0x46E4 US_ALU_RGB_ADDR_9 +0x46E8 US_ALU_RGB_ADDR_10 +0x46EC US_ALU_RGB_ADDR_11 +0x46F0 US_ALU_RGB_ADDR_12 +0x46F4 US_ALU_RGB_ADDR_13 +0x46F8 US_ALU_RGB_ADDR_14 +0x46FC US_ALU_RGB_ADDR_15 +0x4700 US_ALU_RGB_ADDR_16 +0x4704 US_ALU_RGB_ADDR_17 +0x4708 US_ALU_RGB_ADDR_18 +0x470C US_ALU_RGB_ADDR_19 +0x4710 US_ALU_RGB_ADDR_20 +0x4714 US_ALU_RGB_ADDR_21 +0x4718 US_ALU_RGB_ADDR_22 +0x471C US_ALU_RGB_ADDR_23 +0x4720 US_ALU_RGB_ADDR_24 +0x4724 US_ALU_RGB_ADDR_25 +0x4728 US_ALU_RGB_ADDR_26 +0x472C US_ALU_RGB_ADDR_27 +0x4730 US_ALU_RGB_ADDR_28 +0x4734 US_ALU_RGB_ADDR_29 +0x4738 US_ALU_RGB_ADDR_30 +0x473C US_ALU_RGB_ADDR_31 +0x4740 US_ALU_RGB_ADDR_32 +0x4744 US_ALU_RGB_ADDR_33 +0x4748 US_ALU_RGB_ADDR_34 +0x474C US_ALU_RGB_ADDR_35 +0x4750 US_ALU_RGB_ADDR_36 +0x4754 US_ALU_RGB_ADDR_37 +0x4758 US_ALU_RGB_ADDR_38 +0x475C US_ALU_RGB_ADDR_39 +0x4760 US_ALU_RGB_ADDR_40 +0x4764 US_ALU_RGB_ADDR_41 +0x4768 US_ALU_RGB_ADDR_42 +0x476C US_ALU_RGB_ADDR_43 +0x4770 US_ALU_RGB_ADDR_44 +0x4774 US_ALU_RGB_ADDR_45 +0x4778 US_ALU_RGB_ADDR_46 +0x477C US_ALU_RGB_ADDR_47 +0x4780 US_ALU_RGB_ADDR_48 +0x4784 US_ALU_RGB_ADDR_49 +0x4788 US_ALU_RGB_ADDR_50 +0x478C US_ALU_RGB_ADDR_51 +0x4790 US_ALU_RGB_ADDR_52 +0x4794 US_ALU_RGB_ADDR_53 +0x4798 US_ALU_RGB_ADDR_54 +0x479C US_ALU_RGB_ADDR_55 +0x47A0 US_ALU_RGB_ADDR_56 +0x47A4 US_ALU_RGB_ADDR_57 +0x47A8 US_ALU_RGB_ADDR_58 +0x47AC US_ALU_RGB_ADDR_59 +0x47B0 US_ALU_RGB_ADDR_60 +0x47B4 US_ALU_RGB_ADDR_61 +0x47B8 US_ALU_RGB_ADDR_62 +0x47BC US_ALU_RGB_ADDR_63 +0x47C0 US_ALU_ALPHA_ADDR_0 +0x47C4 US_ALU_ALPHA_ADDR_1 +0x47C8 US_ALU_ALPHA_ADDR_2 +0x47CC US_ALU_ALPHA_ADDR_3 +0x47D0 US_ALU_ALPHA_ADDR_4 +0x47D4 US_ALU_ALPHA_ADDR_5 +0x47D8 US_ALU_ALPHA_ADDR_6 +0x47DC US_ALU_ALPHA_ADDR_7 +0x47E0 US_ALU_ALPHA_ADDR_8 +0x47E4 US_ALU_ALPHA_ADDR_9 +0x47E8 US_ALU_ALPHA_ADDR_10 +0x47EC US_ALU_ALPHA_ADDR_11 +0x47F0 US_ALU_ALPHA_ADDR_12 +0x47F4 US_ALU_ALPHA_ADDR_13 +0x47F8 US_ALU_ALPHA_ADDR_14 +0x47FC US_ALU_ALPHA_ADDR_15 +0x4800 US_ALU_ALPHA_ADDR_16 +0x4804 US_ALU_ALPHA_ADDR_17 +0x4808 US_ALU_ALPHA_ADDR_18 +0x480C US_ALU_ALPHA_ADDR_19 +0x4810 US_ALU_ALPHA_ADDR_20 +0x4814 US_ALU_ALPHA_ADDR_21 +0x4818 US_ALU_ALPHA_ADDR_22 +0x481C US_ALU_ALPHA_ADDR_23 +0x4820 US_ALU_ALPHA_ADDR_24 +0x4824 US_ALU_ALPHA_ADDR_25 +0x4828 US_ALU_ALPHA_ADDR_26 +0x482C US_ALU_ALPHA_ADDR_27 +0x4830 US_ALU_ALPHA_ADDR_28 +0x4834 US_ALU_ALPHA_ADDR_29 +0x4838 US_ALU_ALPHA_ADDR_30 +0x483C US_ALU_ALPHA_ADDR_31 +0x4840 US_ALU_ALPHA_ADDR_32 +0x4844 US_ALU_ALPHA_ADDR_33 +0x4848 US_ALU_ALPHA_ADDR_34 +0x484C US_ALU_ALPHA_ADDR_35 +0x4850 US_ALU_ALPHA_ADDR_36 +0x4854 US_ALU_ALPHA_ADDR_37 +0x4858 US_ALU_ALPHA_ADDR_38 +0x485C US_ALU_ALPHA_ADDR_39 +0x4860 US_ALU_ALPHA_ADDR_40 +0x4864 US_ALU_ALPHA_ADDR_41 +0x4868 US_ALU_ALPHA_ADDR_42 +0x486C US_ALU_ALPHA_ADDR_43 +0x4870 US_ALU_ALPHA_ADDR_44 +0x4874 US_ALU_ALPHA_ADDR_45 +0x4878 US_ALU_ALPHA_ADDR_46 +0x487C US_ALU_ALPHA_ADDR_47 +0x4880 US_ALU_ALPHA_ADDR_48 +0x4884 US_ALU_ALPHA_ADDR_49 +0x4888 US_ALU_ALPHA_ADDR_50 +0x488C US_ALU_ALPHA_ADDR_51 +0x4890 US_ALU_ALPHA_ADDR_52 +0x4894 US_ALU_ALPHA_ADDR_53 +0x4898 US_ALU_ALPHA_ADDR_54 +0x489C US_ALU_ALPHA_ADDR_55 +0x48A0 US_ALU_ALPHA_ADDR_56 +0x48A4 US_ALU_ALPHA_ADDR_57 +0x48A8 US_ALU_ALPHA_ADDR_58 +0x48AC US_ALU_ALPHA_ADDR_59 +0x48B0 US_ALU_ALPHA_ADDR_60 +0x48B4 US_ALU_ALPHA_ADDR_61 +0x48B8 US_ALU_ALPHA_ADDR_62 +0x48BC US_ALU_ALPHA_ADDR_63 +0x48C0 US_ALU_RGB_INST_0 +0x48C4 US_ALU_RGB_INST_1 +0x48C8 US_ALU_RGB_INST_2 +0x48CC US_ALU_RGB_INST_3 +0x48D0 US_ALU_RGB_INST_4 +0x48D4 US_ALU_RGB_INST_5 +0x48D8 US_ALU_RGB_INST_6 +0x48DC US_ALU_RGB_INST_7 +0x48E0 US_ALU_RGB_INST_8 +0x48E4 US_ALU_RGB_INST_9 +0x48E8 US_ALU_RGB_INST_10 +0x48EC US_ALU_RGB_INST_11 +0x48F0 US_ALU_RGB_INST_12 +0x48F4 US_ALU_RGB_INST_13 +0x48F8 US_ALU_RGB_INST_14 +0x48FC US_ALU_RGB_INST_15 +0x4900 US_ALU_RGB_INST_16 +0x4904 US_ALU_RGB_INST_17 +0x4908 US_ALU_RGB_INST_18 +0x490C US_ALU_RGB_INST_19 +0x4910 US_ALU_RGB_INST_20 +0x4914 US_ALU_RGB_INST_21 +0x4918 US_ALU_RGB_INST_22 +0x491C US_ALU_RGB_INST_23 +0x4920 US_ALU_RGB_INST_24 +0x4924 US_ALU_RGB_INST_25 +0x4928 US_ALU_RGB_INST_26 +0x492C US_ALU_RGB_INST_27 +0x4930 US_ALU_RGB_INST_28 +0x4934 US_ALU_RGB_INST_29 +0x4938 US_ALU_RGB_INST_30 +0x493C US_ALU_RGB_INST_31 +0x4940 US_ALU_RGB_INST_32 +0x4944 US_ALU_RGB_INST_33 +0x4948 US_ALU_RGB_INST_34 +0x494C US_ALU_RGB_INST_35 +0x4950 US_ALU_RGB_INST_36 +0x4954 US_ALU_RGB_INST_37 +0x4958 US_ALU_RGB_INST_38 +0x495C US_ALU_RGB_INST_39 +0x4960 US_ALU_RGB_INST_40 +0x4964 US_ALU_RGB_INST_41 +0x4968 US_ALU_RGB_INST_42 +0x496C US_ALU_RGB_INST_43 +0x4970 US_ALU_RGB_INST_44 +0x4974 US_ALU_RGB_INST_45 +0x4978 US_ALU_RGB_INST_46 +0x497C US_ALU_RGB_INST_47 +0x4980 US_ALU_RGB_INST_48 +0x4984 US_ALU_RGB_INST_49 +0x4988 US_ALU_RGB_INST_50 +0x498C US_ALU_RGB_INST_51 +0x4990 US_ALU_RGB_INST_52 +0x4994 US_ALU_RGB_INST_53 +0x4998 US_ALU_RGB_INST_54 +0x499C US_ALU_RGB_INST_55 +0x49A0 US_ALU_RGB_INST_56 +0x49A4 US_ALU_RGB_INST_57 +0x49A8 US_ALU_RGB_INST_58 +0x49AC US_ALU_RGB_INST_59 +0x49B0 US_ALU_RGB_INST_60 +0x49B4 US_ALU_RGB_INST_61 +0x49B8 US_ALU_RGB_INST_62 +0x49BC US_ALU_RGB_INST_63 +0x49C0 US_ALU_ALPHA_INST_0 +0x49C4 US_ALU_ALPHA_INST_1 +0x49C8 US_ALU_ALPHA_INST_2 +0x49CC US_ALU_ALPHA_INST_3 +0x49D0 US_ALU_ALPHA_INST_4 +0x49D4 US_ALU_ALPHA_INST_5 +0x49D8 US_ALU_ALPHA_INST_6 +0x49DC US_ALU_ALPHA_INST_7 +0x49E0 US_ALU_ALPHA_INST_8 +0x49E4 US_ALU_ALPHA_INST_9 +0x49E8 US_ALU_ALPHA_INST_10 +0x49EC US_ALU_ALPHA_INST_11 +0x49F0 US_ALU_ALPHA_INST_12 +0x49F4 US_ALU_ALPHA_INST_13 +0x49F8 US_ALU_ALPHA_INST_14 +0x49FC US_ALU_ALPHA_INST_15 +0x4A00 US_ALU_ALPHA_INST_16 +0x4A04 US_ALU_ALPHA_INST_17 +0x4A08 US_ALU_ALPHA_INST_18 +0x4A0C US_ALU_ALPHA_INST_19 +0x4A10 US_ALU_ALPHA_INST_20 +0x4A14 US_ALU_ALPHA_INST_21 +0x4A18 US_ALU_ALPHA_INST_22 +0x4A1C US_ALU_ALPHA_INST_23 +0x4A20 US_ALU_ALPHA_INST_24 +0x4A24 US_ALU_ALPHA_INST_25 +0x4A28 US_ALU_ALPHA_INST_26 +0x4A2C US_ALU_ALPHA_INST_27 +0x4A30 US_ALU_ALPHA_INST_28 +0x4A34 US_ALU_ALPHA_INST_29 +0x4A38 US_ALU_ALPHA_INST_30 +0x4A3C US_ALU_ALPHA_INST_31 +0x4A40 US_ALU_ALPHA_INST_32 +0x4A44 US_ALU_ALPHA_INST_33 +0x4A48 US_ALU_ALPHA_INST_34 +0x4A4C US_ALU_ALPHA_INST_35 +0x4A50 US_ALU_ALPHA_INST_36 +0x4A54 US_ALU_ALPHA_INST_37 +0x4A58 US_ALU_ALPHA_INST_38 +0x4A5C US_ALU_ALPHA_INST_39 +0x4A60 US_ALU_ALPHA_INST_40 +0x4A64 US_ALU_ALPHA_INST_41 +0x4A68 US_ALU_ALPHA_INST_42 +0x4A6C US_ALU_ALPHA_INST_43 +0x4A70 US_ALU_ALPHA_INST_44 +0x4A74 US_ALU_ALPHA_INST_45 +0x4A78 US_ALU_ALPHA_INST_46 +0x4A7C US_ALU_ALPHA_INST_47 +0x4A80 US_ALU_ALPHA_INST_48 +0x4A84 US_ALU_ALPHA_INST_49 +0x4A88 US_ALU_ALPHA_INST_50 +0x4A8C US_ALU_ALPHA_INST_51 +0x4A90 US_ALU_ALPHA_INST_52 +0x4A94 US_ALU_ALPHA_INST_53 +0x4A98 US_ALU_ALPHA_INST_54 +0x4A9C US_ALU_ALPHA_INST_55 +0x4AA0 US_ALU_ALPHA_INST_56 +0x4AA4 US_ALU_ALPHA_INST_57 +0x4AA8 US_ALU_ALPHA_INST_58 +0x4AAC US_ALU_ALPHA_INST_59 +0x4AB0 US_ALU_ALPHA_INST_60 +0x4AB4 US_ALU_ALPHA_INST_61 +0x4AB8 US_ALU_ALPHA_INST_62 +0x4ABC US_ALU_ALPHA_INST_63 +0x4BC0 FG_FOG_BLEND +0x4BC4 FG_FOG_FACTOR +0x4BC8 FG_FOG_COLOR_R +0x4BCC FG_FOG_COLOR_G +0x4BD0 FG_FOG_COLOR_B +0x4BD4 FG_ALPHA_FUNC +0x4BD8 FG_DEPTH_SRC +0x4C00 US_ALU_CONST_R_0 +0x4C04 US_ALU_CONST_G_0 +0x4C08 US_ALU_CONST_B_0 +0x4C0C US_ALU_CONST_A_0 +0x4C10 US_ALU_CONST_R_1 +0x4C14 US_ALU_CONST_G_1 +0x4C18 US_ALU_CONST_B_1 +0x4C1C US_ALU_CONST_A_1 +0x4C20 US_ALU_CONST_R_2 +0x4C24 US_ALU_CONST_G_2 +0x4C28 US_ALU_CONST_B_2 +0x4C2C US_ALU_CONST_A_2 +0x4C30 US_ALU_CONST_R_3 +0x4C34 US_ALU_CONST_G_3 +0x4C38 US_ALU_CONST_B_3 +0x4C3C US_ALU_CONST_A_3 +0x4C40 US_ALU_CONST_R_4 +0x4C44 US_ALU_CONST_G_4 +0x4C48 US_ALU_CONST_B_4 +0x4C4C US_ALU_CONST_A_4 +0x4C50 US_ALU_CONST_R_5 +0x4C54 US_ALU_CONST_G_5 +0x4C58 US_ALU_CONST_B_5 +0x4C5C US_ALU_CONST_A_5 +0x4C60 US_ALU_CONST_R_6 +0x4C64 US_ALU_CONST_G_6 +0x4C68 US_ALU_CONST_B_6 +0x4C6C US_ALU_CONST_A_6 +0x4C70 US_ALU_CONST_R_7 +0x4C74 US_ALU_CONST_G_7 +0x4C78 US_ALU_CONST_B_7 +0x4C7C US_ALU_CONST_A_7 +0x4C80 US_ALU_CONST_R_8 +0x4C84 US_ALU_CONST_G_8 +0x4C88 US_ALU_CONST_B_8 +0x4C8C US_ALU_CONST_A_8 +0x4C90 US_ALU_CONST_R_9 +0x4C94 US_ALU_CONST_G_9 +0x4C98 US_ALU_CONST_B_9 +0x4C9C US_ALU_CONST_A_9 +0x4CA0 US_ALU_CONST_R_10 +0x4CA4 US_ALU_CONST_G_10 +0x4CA8 US_ALU_CONST_B_10 +0x4CAC US_ALU_CONST_A_10 +0x4CB0 US_ALU_CONST_R_11 +0x4CB4 US_ALU_CONST_G_11 +0x4CB8 US_ALU_CONST_B_11 +0x4CBC US_ALU_CONST_A_11 +0x4CC0 US_ALU_CONST_R_12 +0x4CC4 US_ALU_CONST_G_12 +0x4CC8 US_ALU_CONST_B_12 +0x4CCC US_ALU_CONST_A_12 +0x4CD0 US_ALU_CONST_R_13 +0x4CD4 US_ALU_CONST_G_13 +0x4CD8 US_ALU_CONST_B_13 +0x4CDC US_ALU_CONST_A_13 +0x4CE0 US_ALU_CONST_R_14 +0x4CE4 US_ALU_CONST_G_14 +0x4CE8 US_ALU_CONST_B_14 +0x4CEC US_ALU_CONST_A_14 +0x4CF0 US_ALU_CONST_R_15 +0x4CF4 US_ALU_CONST_G_15 +0x4CF8 US_ALU_CONST_B_15 +0x4CFC US_ALU_CONST_A_15 +0x4D00 US_ALU_CONST_R_16 +0x4D04 US_ALU_CONST_G_16 +0x4D08 US_ALU_CONST_B_16 +0x4D0C US_ALU_CONST_A_16 +0x4D10 US_ALU_CONST_R_17 +0x4D14 US_ALU_CONST_G_17 +0x4D18 US_ALU_CONST_B_17 +0x4D1C US_ALU_CONST_A_17 +0x4D20 US_ALU_CONST_R_18 +0x4D24 US_ALU_CONST_G_18 +0x4D28 US_ALU_CONST_B_18 +0x4D2C US_ALU_CONST_A_18 +0x4D30 US_ALU_CONST_R_19 +0x4D34 US_ALU_CONST_G_19 +0x4D38 US_ALU_CONST_B_19 +0x4D3C US_ALU_CONST_A_19 +0x4D40 US_ALU_CONST_R_20 +0x4D44 US_ALU_CONST_G_20 +0x4D48 US_ALU_CONST_B_20 +0x4D4C US_ALU_CONST_A_20 +0x4D50 US_ALU_CONST_R_21 +0x4D54 US_ALU_CONST_G_21 +0x4D58 US_ALU_CONST_B_21 +0x4D5C US_ALU_CONST_A_21 +0x4D60 US_ALU_CONST_R_22 +0x4D64 US_ALU_CONST_G_22 +0x4D68 US_ALU_CONST_B_22 +0x4D6C US_ALU_CONST_A_22 +0x4D70 US_ALU_CONST_R_23 +0x4D74 US_ALU_CONST_G_23 +0x4D78 US_ALU_CONST_B_23 +0x4D7C US_ALU_CONST_A_23 +0x4D80 US_ALU_CONST_R_24 +0x4D84 US_ALU_CONST_G_24 +0x4D88 US_ALU_CONST_B_24 +0x4D8C US_ALU_CONST_A_24 +0x4D90 US_ALU_CONST_R_25 +0x4D94 US_ALU_CONST_G_25 +0x4D98 US_ALU_CONST_B_25 +0x4D9C US_ALU_CONST_A_25 +0x4DA0 US_ALU_CONST_R_26 +0x4DA4 US_ALU_CONST_G_26 +0x4DA8 US_ALU_CONST_B_26 +0x4DAC US_ALU_CONST_A_26 +0x4DB0 US_ALU_CONST_R_27 +0x4DB4 US_ALU_CONST_G_27 +0x4DB8 US_ALU_CONST_B_27 +0x4DBC US_ALU_CONST_A_27 +0x4DC0 US_ALU_CONST_R_28 +0x4DC4 US_ALU_CONST_G_28 +0x4DC8 US_ALU_CONST_B_28 +0x4DCC US_ALU_CONST_A_28 +0x4DD0 US_ALU_CONST_R_29 +0x4DD4 US_ALU_CONST_G_29 +0x4DD8 US_ALU_CONST_B_29 +0x4DDC US_ALU_CONST_A_29 +0x4DE0 US_ALU_CONST_R_30 +0x4DE4 US_ALU_CONST_G_30 +0x4DE8 US_ALU_CONST_B_30 +0x4DEC US_ALU_CONST_A_30 +0x4DF0 US_ALU_CONST_R_31 +0x4DF4 US_ALU_CONST_G_31 +0x4DF8 US_ALU_CONST_B_31 +0x4DFC US_ALU_CONST_A_31 +0x4E04 RB3D_BLENDCNTL_R3 +0x4E08 RB3D_ABLENDCNTL_R3 +0x4E0C RB3D_COLOR_CHANNEL_MASK +0x4E10 RB3D_CONSTANT_COLOR +0x4E14 RB3D_COLOR_CLEAR_VALUE +0x4E18 RB3D_ROPCNTL_R3 +0x4E1C RB3D_CLRCMP_FLIPE_R3 +0x4E20 RB3D_CLRCMP_CLR_R3 +0x4E24 RB3D_CLRCMP_MSK_R3 +0x4E48 RB3D_DEBUG_CTL +0x4E4C RB3D_DSTCACHE_CTLSTAT_R3 +0x4E50 RB3D_DITHER_CTL +0x4E54 RB3D_CMASK_OFFSET0 +0x4E58 RB3D_CMASK_OFFSET1 +0x4E5C RB3D_CMASK_OFFSET2 +0x4E60 RB3D_CMASK_OFFSET3 +0x4E64 RB3D_CMASK_PITCH0 +0x4E68 RB3D_CMASK_PITCH1 +0x4E6C RB3D_CMASK_PITCH2 +0x4E70 RB3D_CMASK_PITCH3 +0x4E74 RB3D_CMASK_WRINDEX +0x4E78 RB3D_CMASK_DWORD +0x4E7C RB3D_CMASK_RDINDEX +0x4E80 RB3D_AARESOLVE_OFFSET +0x4E84 RB3D_AARESOLVE_PITCH +0x4E88 RB3D_AARESOLVE_CTL +0x4F04 ZB_ZSTENCILCNTL +0x4F08 ZB_STENCILREFMASK +0x4F14 ZB_ZTOP +0x4F18 ZB_ZCACHE_CTLSTAT +0x4F1C ZB_BW_CNTL +0x4F28 ZB_DEPTHCLEARVALUE +0x4F30 ZB_ZMASK_OFFSET +0x4F34 ZB_ZMASK_PITCH +0x4F38 ZB_ZMASK_WRINDEX +0x4F3C ZB_ZMASK_DWORD +0x4F40 ZB_ZMASK_RDINDEX +0x4F44 ZB_HIZ_OFFSET +0x4F48 ZB_HIZ_WRINDEX +0x4F4C ZB_HIZ_DWORD +0x4F50 ZB_HIZ_RDINDEX +0x4F54 ZB_HIZ_PITCH +0x4F58 ZB_ZPASS_DATA +0x4F60 ZB_DEPTHXY_OFFSET diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index 7e8ce98..1b8d62f 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c @@ -29,6 +29,8 @@ #include "radeon_reg.h" #include "radeon.h" +#include "rs600_reg_safe.h" + /* rs600 depends on : */ void r100_hdp_reset(struct radeon_device *rdev); int r100_gui_wait_for_idle(struct radeon_device *rdev); @@ -409,3 +411,10 @@ void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) ((reg) & RS600_MC_ADDR_MASK)); WREG32(RS600_MC_DATA, v); } + +int rs600_init(struct radeon_device *rdev) +{ + rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; + rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); + return 0; +} diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index bc6b7c5..839595b 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c @@ -652,68 +652,3 @@ void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) WREG32(RS690_MC_DATA, v); WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); } - -static const unsigned rs690_reg_safe_bm[219] = { - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0x17FF1FFF,0xFFFFFFFC,0xFFFFFFFF,0xFF30FFBF, - 0xFFFFFFF8,0xC3E6FFFF,0xFFFFF6DF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFF03F, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFEFCE,0xF00EBFFF,0x007C0000, - 0xF0000078,0xFF000009,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFF7FF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFC78,0xFFFFFFFF,0xFFFFFFFE,0xFFFFFFFF, - 0x38FF8F50,0xFFF88082,0xF000000C,0xFAE009FF, - 0x0000FFFF,0xFFFFFFFF,0xFFFFFFFF,0x00000000, - 0x00000000,0x0000C100,0x00000000,0x00000000, - 0x00000000,0x00000000,0x00000000,0x00000000, - 0x00000000,0xFFFF0000,0xFFFFFFFF,0xFF80FFFF, - 0x00000000,0x00000000,0x00000000,0x00000000, - 0x0003FC01,0xFFFFFFF8,0xFE800B19,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, - 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, -}; - -int rs690_init(struct radeon_device *rdev) -{ - rdev->config.r300.reg_safe_bm = rs690_reg_safe_bm; - rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs690_reg_safe_bm); - return 0; -} -- cgit v0.10.2 From a1a2d1d32250f6fcc317419e9dfb4a5a6946d2e6 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Sun, 23 Aug 2009 12:40:55 +0300 Subject: drm: GEM handles are u32, not int Several functions in the GEM kernel API used int as handle type, but user API has it __u32 which is also the intended type. Replace int with u32. Signed-off-by: Pekka Paalanen Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index ffe8f43..230c9ff 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -164,7 +164,7 @@ EXPORT_SYMBOL(drm_gem_object_alloc); * Removes the mapping from handle to filp for this object. */ static int -drm_gem_handle_delete(struct drm_file *filp, int handle) +drm_gem_handle_delete(struct drm_file *filp, u32 handle) { struct drm_device *dev; struct drm_gem_object *obj; @@ -207,7 +207,7 @@ drm_gem_handle_delete(struct drm_file *filp, int handle) int drm_gem_handle_create(struct drm_file *file_priv, struct drm_gem_object *obj, - int *handlep) + u32 *handlep) { int ret; @@ -221,7 +221,7 @@ again: /* do the allocation under our spinlock */ spin_lock(&file_priv->table_lock); - ret = idr_get_new_above(&file_priv->object_idr, obj, 1, handlep); + ret = idr_get_new_above(&file_priv->object_idr, obj, 1, (int *)handlep); spin_unlock(&file_priv->table_lock); if (ret == -EAGAIN) goto again; @@ -237,7 +237,7 @@ EXPORT_SYMBOL(drm_gem_handle_create); /** Returns a reference to the object named by the handle. */ struct drm_gem_object * drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp, - int handle) + u32 handle) { struct drm_gem_object *obj; @@ -344,7 +344,7 @@ drm_gem_open_ioctl(struct drm_device *dev, void *data, struct drm_gem_open *args = data; struct drm_gem_object *obj; int ret; - int handle; + u32 handle; if (!(dev->driver->driver_features & DRIVER_GEM)) return -ENODEV; @@ -539,7 +539,6 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) vma->vm_flags |= VM_RESERVED | VM_IO | VM_PFNMAP | VM_DONTEXPAND; vma->vm_ops = obj->dev->driver->gem_vm_ops; vma->vm_private_data = map->handle; - /* FIXME: use pgprot_writecombine when available */ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); /* Take a ref for this mapping of the object, so that the fault diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 140bee1..0e6c9cc 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -111,7 +111,8 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data, { struct drm_i915_gem_create *args = data; struct drm_gem_object *obj; - int handle, ret; + int ret; + u32 handle; args->size = roundup(args->size, PAGE_SIZE); diff --git a/include/drm/drmP.h b/include/drm/drmP.h index e0f1c1f..eeefb63 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -1441,7 +1441,7 @@ drm_gem_object_unreference(struct drm_gem_object *obj) int drm_gem_handle_create(struct drm_file *file_priv, struct drm_gem_object *obj, - int *handlep); + u32 *handlep); static inline void drm_gem_object_handle_reference(struct drm_gem_object *obj) @@ -1467,7 +1467,7 @@ drm_gem_object_handle_unreference(struct drm_gem_object *obj) struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp, - int handle); + u32 handle); int drm_gem_close_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int drm_gem_flink_ioctl(struct drm_device *dev, void *data, -- cgit v0.10.2 From 5853a9f6dda244b4163b9daad663bdc41a74f596 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Tue, 2 Jun 2009 13:20:00 +0800 Subject: ACPICA: Fix several pointer casts to avoid possible compile warnings Fixes warnings with gcc -Wcast-qual flag. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/exdump.c b/drivers/acpi/acpica/exdump.c index ec52461..de34463 100644 --- a/drivers/acpi/acpica/exdump.c +++ b/drivers/acpi/acpica/exdump.c @@ -418,9 +418,9 @@ acpi_ex_dump_object(union acpi_operand_object *obj_desc, case ACPI_EXD_REFERENCE: acpi_ex_out_string("Class Name", - (char *) - acpi_ut_get_reference_name - (obj_desc)); + ACPI_CAST_PTR(char, + acpi_ut_get_reference_name + (obj_desc))); acpi_ex_dump_reference_obj(obj_desc); break; diff --git a/drivers/acpi/acpica/nsutils.c b/drivers/acpi/acpica/nsutils.c index 78277ed..ea55ab4 100644 --- a/drivers/acpi/acpica/nsutils.c +++ b/drivers/acpi/acpica/nsutils.c @@ -88,7 +88,8 @@ acpi_ns_report_error(const char *module_name, /* There is a non-ascii character in the name */ - ACPI_MOVE_32_TO_32(&bad_name, internal_name); + ACPI_MOVE_32_TO_32(&bad_name, + ACPI_CAST_PTR(u32, internal_name)); acpi_os_printf("[0x%4.4X] (NON-ASCII)", bad_name); } else { /* Convert path to external format */ @@ -836,7 +837,7 @@ acpi_ns_get_node(struct acpi_namespace_node *prefix_node, acpi_status status; char *internal_path; - ACPI_FUNCTION_TRACE_PTR(ns_get_node, pathname); + ACPI_FUNCTION_TRACE_PTR(ns_get_node, ACPI_CAST_PTR(char, pathname)); if (!pathname) { *return_node = prefix_node; -- cgit v0.10.2 From f8d80cdf40fe4d2393159012b38ce9f85a488686 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Tue, 2 Jun 2009 13:28:13 +0800 Subject: ACPICA: Remove duplicate extern declarations for public globals Some were defined twice, causes a warning with gcc -Wredundant-decls. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/acglobal.h b/drivers/acpi/acpica/acglobal.h index 3d87362..0b73b31 100644 --- a/drivers/acpi/acpica/acglobal.h +++ b/drivers/acpi/acpica/acglobal.h @@ -58,6 +58,10 @@ #define ACPI_INIT_GLOBAL(a,b) a #endif +#ifdef DEFINE_ACPI_GLOBALS + +/* Public globals, available from outside ACPICA subsystem */ + /***************************************************************************** * * Runtime configuration (static defaults that can be overriden at runtime) @@ -78,7 +82,7 @@ * 5) Allow unresolved references (invalid target name) in package objects * 6) Enable warning messages for behavior that is not ACPI spec compliant */ -ACPI_EXTERN u8 ACPI_INIT_GLOBAL(acpi_gbl_enable_interpreter_slack, FALSE); +u8 ACPI_INIT_GLOBAL(acpi_gbl_enable_interpreter_slack, FALSE); /* * Automatically serialize ALL control methods? Default is FALSE, meaning @@ -86,27 +90,36 @@ ACPI_EXTERN u8 ACPI_INIT_GLOBAL(acpi_gbl_enable_interpreter_slack, FALSE); * Only change this if the ASL code is poorly written and cannot handle * reentrancy even though methods are marked "NotSerialized". */ -ACPI_EXTERN u8 ACPI_INIT_GLOBAL(acpi_gbl_all_methods_serialized, FALSE); +u8 ACPI_INIT_GLOBAL(acpi_gbl_all_methods_serialized, FALSE); /* * Create the predefined _OSI method in the namespace? Default is TRUE * because ACPI CA is fully compatible with other ACPI implementations. * Changing this will revert ACPI CA (and machine ASL) to pre-OSI behavior. */ -ACPI_EXTERN u8 ACPI_INIT_GLOBAL(acpi_gbl_create_osi_method, TRUE); +u8 ACPI_INIT_GLOBAL(acpi_gbl_create_osi_method, TRUE); /* * Disable wakeup GPEs during runtime? Default is TRUE because WAKE and * RUNTIME GPEs should never be shared, and WAKE GPEs should typically only * be enabled just before going to sleep. */ -ACPI_EXTERN u8 ACPI_INIT_GLOBAL(acpi_gbl_leave_wake_gpes_disabled, TRUE); +u8 ACPI_INIT_GLOBAL(acpi_gbl_leave_wake_gpes_disabled, TRUE); /* * Optionally use default values for the ACPI register widths. Set this to * TRUE to use the defaults, if an FADT contains incorrect widths/lengths. */ -ACPI_EXTERN u8 ACPI_INIT_GLOBAL(acpi_gbl_use_default_register_widths, TRUE); +u8 ACPI_INIT_GLOBAL(acpi_gbl_use_default_register_widths, TRUE); + +/* acpi_gbl_FADT is a local copy of the FADT, converted to a common format. */ + +struct acpi_table_fadt acpi_gbl_FADT; +u32 acpi_current_gpe_count; +u32 acpi_gbl_trace_flags; +acpi_name acpi_gbl_trace_method_name; + +#endif /***************************************************************************** * @@ -114,11 +127,6 @@ ACPI_EXTERN u8 ACPI_INIT_GLOBAL(acpi_gbl_use_default_register_widths, TRUE); * ****************************************************************************/ -/* Runtime configuration of debug print levels */ - -extern u32 acpi_dbg_level; -extern u32 acpi_dbg_layer; - /* Procedure nesting level for debug output */ extern u32 acpi_gbl_nesting_level; @@ -127,10 +135,8 @@ extern u32 acpi_gbl_nesting_level; ACPI_EXTERN u32 acpi_gbl_original_dbg_level; ACPI_EXTERN u32 acpi_gbl_original_dbg_layer; -ACPI_EXTERN acpi_name acpi_gbl_trace_method_name; ACPI_EXTERN u32 acpi_gbl_trace_dbg_level; ACPI_EXTERN u32 acpi_gbl_trace_dbg_layer; -ACPI_EXTERN u32 acpi_gbl_trace_flags; /***************************************************************************** * @@ -142,10 +148,8 @@ ACPI_EXTERN u32 acpi_gbl_trace_flags; * acpi_gbl_root_table_list is the master list of ACPI tables found in the * RSDT/XSDT. * - * acpi_gbl_FADT is a local copy of the FADT, converted to a common format. */ ACPI_EXTERN struct acpi_internal_rsdt acpi_gbl_root_table_list; -ACPI_EXTERN struct acpi_table_fadt acpi_gbl_FADT; ACPI_EXTERN struct acpi_table_facs *acpi_gbl_FACS; /* These addresses are calculated from the FADT Event Block addresses */ @@ -340,7 +344,6 @@ ACPI_EXTERN struct acpi_fixed_event_handler ACPI_EXTERN struct acpi_gpe_xrupt_info *acpi_gbl_gpe_xrupt_list_head; ACPI_EXTERN struct acpi_gpe_block_info *acpi_gbl_gpe_fadt_blocks[ACPI_MAX_GPE_BLOCKS]; -ACPI_EXTERN u32 acpi_current_gpe_count; /***************************************************************************** * diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index 82ec6a3..2aecaa5 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -64,6 +64,7 @@ extern u8 acpi_gbl_enable_interpreter_slack; extern u8 acpi_gbl_all_methods_serialized; extern u8 acpi_gbl_create_osi_method; extern u8 acpi_gbl_leave_wake_gpes_disabled; +extern u8 acpi_gbl_use_default_register_widths; extern acpi_name acpi_gbl_trace_method_name; extern u32 acpi_gbl_trace_flags; -- cgit v0.10.2 From c6b5774caafa4c12b6019366e2fdaaff117e95a4 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Wed, 24 Jun 2009 09:44:06 +0800 Subject: ACPICA: Add 64-bit support to acpi_read and acpi_write Needed by drivers for new ACPi tables. Internal versions of these functions still use 32-bit max transfers, in order to minimize disruption and stack use for the standard ACPI registers (FADT-based). Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/achware.h b/drivers/acpi/acpica/achware.h index 4afa3d8..36192f1 100644 --- a/drivers/acpi/acpica/achware.h +++ b/drivers/acpi/acpica/achware.h @@ -62,6 +62,14 @@ u32 acpi_hw_get_mode(void); /* * hwregs - ACPI Register I/O */ +acpi_status +acpi_hw_validate_register(struct acpi_generic_address *reg, + u8 max_bit_width, u64 *address); + +acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg); + +acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg); + struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id); acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control); diff --git a/drivers/acpi/acpica/evgpe.c b/drivers/acpi/acpica/evgpe.c index b9d8ee6..afacf44 100644 --- a/drivers/acpi/acpica/evgpe.c +++ b/drivers/acpi/acpica/evgpe.c @@ -424,8 +424,8 @@ u32 acpi_ev_gpe_detect(struct acpi_gpe_xrupt_info * gpe_xrupt_list) /* Read the Status Register */ status = - acpi_read(&status_reg, - &gpe_register_info->status_address); + acpi_hw_read(&status_reg, + &gpe_register_info->status_address); if (ACPI_FAILURE(status)) { goto unlock_and_exit; } @@ -433,8 +433,8 @@ u32 acpi_ev_gpe_detect(struct acpi_gpe_xrupt_info * gpe_xrupt_list) /* Read the Enable Register */ status = - acpi_read(&enable_reg, - &gpe_register_info->enable_address); + acpi_hw_read(&enable_reg, + &gpe_register_info->enable_address); if (ACPI_FAILURE(status)) { goto unlock_and_exit; } diff --git a/drivers/acpi/acpica/evgpeblk.c b/drivers/acpi/acpica/evgpeblk.c index 7b34636..a60aaa7 100644 --- a/drivers/acpi/acpica/evgpeblk.c +++ b/drivers/acpi/acpica/evgpeblk.c @@ -843,14 +843,14 @@ acpi_ev_create_gpe_info_blocks(struct acpi_gpe_block_info *gpe_block) /* Disable all GPEs within this register */ - status = acpi_write(0x00, &this_register->enable_address); + status = acpi_hw_write(0x00, &this_register->enable_address); if (ACPI_FAILURE(status)) { goto error_exit; } /* Clear any pending GPE events within this register */ - status = acpi_write(0xFF, &this_register->status_address); + status = acpi_hw_write(0xFF, &this_register->status_address); if (ACPI_FAILURE(status)) { goto error_exit; } diff --git a/drivers/acpi/acpica/hwgpe.c b/drivers/acpi/acpica/hwgpe.c index d3b7e37..c28c41b 100644 --- a/drivers/acpi/acpica/hwgpe.c +++ b/drivers/acpi/acpica/hwgpe.c @@ -82,7 +82,7 @@ acpi_status acpi_hw_low_disable_gpe(struct acpi_gpe_event_info *gpe_event_info) /* Get current value of the enable register that contains this GPE */ - status = acpi_read(&enable_mask, &gpe_register_info->enable_address); + status = acpi_hw_read(&enable_mask, &gpe_register_info->enable_address); if (ACPI_FAILURE(status)) { return (status); } @@ -95,7 +95,7 @@ acpi_status acpi_hw_low_disable_gpe(struct acpi_gpe_event_info *gpe_event_info) /* Write the updated enable mask */ - status = acpi_write(enable_mask, &gpe_register_info->enable_address); + status = acpi_hw_write(enable_mask, &gpe_register_info->enable_address); return (status); } @@ -130,8 +130,8 @@ acpi_hw_write_gpe_enable_reg(struct acpi_gpe_event_info * gpe_event_info) /* Write the entire GPE (runtime) enable register */ - status = acpi_write(gpe_register_info->enable_for_run, - &gpe_register_info->enable_address); + status = acpi_hw_write(gpe_register_info->enable_for_run, + &gpe_register_info->enable_address); return (status); } @@ -163,8 +163,8 @@ acpi_status acpi_hw_clear_gpe(struct acpi_gpe_event_info * gpe_event_info) * Write a one to the appropriate bit in the status register to * clear this GPE. */ - status = acpi_write(register_bit, - &gpe_event_info->register_info->status_address); + status = acpi_hw_write(register_bit, + &gpe_event_info->register_info->status_address); return (status); } @@ -222,7 +222,7 @@ acpi_hw_get_gpe_status(struct acpi_gpe_event_info * gpe_event_info, /* GPE currently active (status bit == 1)? */ - status = acpi_read(&in_byte, &gpe_register_info->status_address); + status = acpi_hw_read(&in_byte, &gpe_register_info->status_address); if (ACPI_FAILURE(status)) { goto unlock_and_exit; } @@ -266,8 +266,8 @@ acpi_hw_disable_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info, /* Disable all GPEs in this register */ status = - acpi_write(0x00, - &gpe_block->register_info[i].enable_address); + acpi_hw_write(0x00, + &gpe_block->register_info[i].enable_address); if (ACPI_FAILURE(status)) { return (status); } @@ -303,8 +303,8 @@ acpi_hw_clear_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info, /* Clear status on all GPEs in this register */ status = - acpi_write(0xFF, - &gpe_block->register_info[i].status_address); + acpi_hw_write(0xFF, + &gpe_block->register_info[i].status_address); if (ACPI_FAILURE(status)) { return (status); } @@ -345,9 +345,9 @@ acpi_hw_enable_runtime_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info, /* Enable all "runtime" GPEs in this register */ - status = acpi_write(gpe_block->register_info[i].enable_for_run, - &gpe_block->register_info[i]. - enable_address); + status = + acpi_hw_write(gpe_block->register_info[i].enable_for_run, + &gpe_block->register_info[i].enable_address); if (ACPI_FAILURE(status)) { return (status); } @@ -387,9 +387,9 @@ acpi_hw_enable_wakeup_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info, /* Enable all "wake" GPEs in this register */ - status = acpi_write(gpe_block->register_info[i].enable_for_wake, - &gpe_block->register_info[i]. - enable_address); + status = + acpi_hw_write(gpe_block->register_info[i].enable_for_wake, + &gpe_block->register_info[i].enable_address); if (ACPI_FAILURE(status)) { return (status); } diff --git a/drivers/acpi/acpica/hwregs.c b/drivers/acpi/acpica/hwregs.c index 23d5505..15c9ed2 100644 --- a/drivers/acpi/acpica/hwregs.c +++ b/drivers/acpi/acpica/hwregs.c @@ -62,6 +62,184 @@ acpi_hw_write_multiple(u32 value, struct acpi_generic_address *register_a, struct acpi_generic_address *register_b); +/****************************************************************************** + * + * FUNCTION: acpi_hw_validate_register + * + * PARAMETERS: Reg - GAS register structure + * max_bit_width - Max bit_width supported (32 or 64) + * Address - Pointer to where the gas->address + * is returned + * + * RETURN: Status + * + * DESCRIPTION: Validate the contents of a GAS register. Checks the GAS + * pointer, Address, space_id, bit_width, and bit_offset. + * + ******************************************************************************/ + +acpi_status +acpi_hw_validate_register(struct acpi_generic_address *reg, + u8 max_bit_width, u64 *address) +{ + + /* Must have a valid pointer to a GAS structure */ + + if (!reg) { + return (AE_BAD_PARAMETER); + } + + /* + * Copy the target address. This handles possible alignment issues. + * Address must not be null. A null address also indicates an optional + * ACPI register that is not supported, so no error message. + */ + ACPI_MOVE_64_TO_64(address, ®->address); + if (!(*address)) { + return (AE_BAD_ADDRESS); + } + + /* Validate the space_iD */ + + if ((reg->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) && + (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO)) { + ACPI_ERROR((AE_INFO, + "Unsupported address space: 0x%X", reg->space_id)); + return (AE_SUPPORT); + } + + /* Validate the bit_width */ + + if ((reg->bit_width != 8) && + (reg->bit_width != 16) && + (reg->bit_width != 32) && (reg->bit_width != max_bit_width)) { + ACPI_ERROR((AE_INFO, + "Unsupported register bit width: 0x%X", + reg->bit_width)); + return (AE_SUPPORT); + } + + /* Validate the bit_offset. Just a warning for now. */ + + if (reg->bit_offset != 0) { + ACPI_WARNING((AE_INFO, + "Unsupported register bit offset: 0x%X", + reg->bit_offset)); + } + + return (AE_OK); +} + +/****************************************************************************** + * + * FUNCTION: acpi_hw_read + * + * PARAMETERS: Value - Where the value is returned + * Reg - GAS register structure + * + * RETURN: Status + * + * DESCRIPTION: Read from either memory or IO space. This is a 32-bit max + * version of acpi_read, used internally since the overhead of + * 64-bit values is not needed. + * + * LIMITATIONS: + * bit_width must be exactly 8, 16, or 32. + * space_iD must be system_memory or system_iO. + * bit_offset and access_width are currently ignored, as there has + * not been a need to implement these. + * + ******************************************************************************/ + +acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg) +{ + u64 address; + acpi_status status; + + ACPI_FUNCTION_NAME(hw_read); + + /* Validate contents of the GAS register */ + + status = acpi_hw_validate_register(reg, 32, &address); + if (ACPI_FAILURE(status)) { + return (status); + } + + /* Initialize entire 32-bit return value to zero */ + + *value = 0; + + /* + * Two address spaces supported: Memory or IO. PCI_Config is + * not supported here because the GAS structure is insufficient + */ + if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { + status = acpi_os_read_memory((acpi_physical_address) + address, value, reg->bit_width); + } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ + + status = acpi_hw_read_port((acpi_io_address) + address, value, reg->bit_width); + } + + ACPI_DEBUG_PRINT((ACPI_DB_IO, + "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n", + *value, reg->bit_width, ACPI_FORMAT_UINT64(address), + acpi_ut_get_region_name(reg->space_id))); + + return (status); +} + +/****************************************************************************** + * + * FUNCTION: acpi_hw_write + * + * PARAMETERS: Value - Value to be written + * Reg - GAS register structure + * + * RETURN: Status + * + * DESCRIPTION: Write to either memory or IO space. This is a 32-bit max + * version of acpi_write, used internally since the overhead of + * 64-bit values is not needed. + * + ******************************************************************************/ + +acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg) +{ + u64 address; + acpi_status status; + + ACPI_FUNCTION_NAME(hw_write); + + /* Validate contents of the GAS register */ + + status = acpi_hw_validate_register(reg, 32, &address); + if (ACPI_FAILURE(status)) { + return (status); + } + + /* + * Two address spaces supported: Memory or IO. PCI_Config is + * not supported here because the GAS structure is insufficient + */ + if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { + status = acpi_os_write_memory((acpi_physical_address) + address, value, reg->bit_width); + } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ + + status = acpi_hw_write_port((acpi_io_address) + address, value, reg->bit_width); + } + + ACPI_DEBUG_PRINT((ACPI_DB_IO, + "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n", + value, reg->bit_width, ACPI_FORMAT_UINT64(address), + acpi_ut_get_region_name(reg->space_id))); + + return (status); +} + /******************************************************************************* * * FUNCTION: acpi_hw_clear_acpi_status @@ -152,15 +330,16 @@ acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control) ACPI_FUNCTION_TRACE(hw_write_pm1_control); - status = acpi_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block); + status = + acpi_hw_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block); if (ACPI_FAILURE(status)) { return_ACPI_STATUS(status); } if (acpi_gbl_FADT.xpm1b_control_block.address) { status = - acpi_write(pm1b_control, - &acpi_gbl_FADT.xpm1b_control_block); + acpi_hw_write(pm1b_control, + &acpi_gbl_FADT.xpm1b_control_block); } return_ACPI_STATUS(status); } @@ -218,12 +397,13 @@ acpi_hw_register_read(u32 register_id, u32 * return_value) case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */ - status = acpi_read(&value, &acpi_gbl_FADT.xpm2_control_block); + status = + acpi_hw_read(&value, &acpi_gbl_FADT.xpm2_control_block); break; case ACPI_REGISTER_PM_TIMER: /* 32-bit access */ - status = acpi_read(&value, &acpi_gbl_FADT.xpm_timer_block); + status = acpi_hw_read(&value, &acpi_gbl_FADT.xpm_timer_block); break; case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */ @@ -340,7 +520,8 @@ acpi_status acpi_hw_register_write(u32 register_id, u32 value) * as per the ACPI spec. */ status = - acpi_read(&read_value, &acpi_gbl_FADT.xpm2_control_block); + acpi_hw_read(&read_value, + &acpi_gbl_FADT.xpm2_control_block); if (ACPI_FAILURE(status)) { goto exit; } @@ -350,12 +531,13 @@ acpi_status acpi_hw_register_write(u32 register_id, u32 value) ACPI_INSERT_BITS(value, ACPI_PM2_CONTROL_PRESERVED_BITS, read_value); - status = acpi_write(value, &acpi_gbl_FADT.xpm2_control_block); + status = + acpi_hw_write(value, &acpi_gbl_FADT.xpm2_control_block); break; case ACPI_REGISTER_PM_TIMER: /* 32-bit access */ - status = acpi_write(value, &acpi_gbl_FADT.xpm_timer_block); + status = acpi_hw_write(value, &acpi_gbl_FADT.xpm_timer_block); break; case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */ @@ -401,7 +583,7 @@ acpi_hw_read_multiple(u32 *value, /* The first register is always required */ - status = acpi_read(&value_a, register_a); + status = acpi_hw_read(&value_a, register_a); if (ACPI_FAILURE(status)) { return (status); } @@ -409,7 +591,7 @@ acpi_hw_read_multiple(u32 *value, /* Second register is optional */ if (register_b->address) { - status = acpi_read(&value_b, register_b); + status = acpi_hw_read(&value_b, register_b); if (ACPI_FAILURE(status)) { return (status); } @@ -452,7 +634,7 @@ acpi_hw_write_multiple(u32 value, /* The first register is always required */ - status = acpi_write(value, register_a); + status = acpi_hw_write(value, register_a); if (ACPI_FAILURE(status)) { return (status); } @@ -470,7 +652,7 @@ acpi_hw_write_multiple(u32 value, * and writes have no side effects" */ if (register_b->address) { - status = acpi_write(value, register_b); + status = acpi_hw_write(value, register_b); } return (status); diff --git a/drivers/acpi/acpica/hwtimer.c b/drivers/acpi/acpica/hwtimer.c index b7f522c..6b282e8 100644 --- a/drivers/acpi/acpica/hwtimer.c +++ b/drivers/acpi/acpica/hwtimer.c @@ -100,7 +100,7 @@ acpi_status acpi_get_timer(u32 * ticks) } status = - acpi_hw_low_level_read(32, ticks, &acpi_gbl_FADT.xpm_timer_block); + acpi_hw_read(ticks, &acpi_gbl_FADT.xpm_timer_block); return_ACPI_STATUS(status); } diff --git a/drivers/acpi/acpica/hwxface.c b/drivers/acpi/acpica/hwxface.c index 9829979..4ead85f 100644 --- a/drivers/acpi/acpica/hwxface.c +++ b/drivers/acpi/acpica/hwxface.c @@ -80,7 +80,7 @@ acpi_status acpi_reset(void) /* Write the reset value to the reset register */ - status = acpi_write(acpi_gbl_FADT.reset_value, reset_reg); + status = acpi_hw_write(acpi_gbl_FADT.reset_value, reset_reg); return_ACPI_STATUS(status); } @@ -97,67 +97,92 @@ ACPI_EXPORT_SYMBOL(acpi_reset) * * DESCRIPTION: Read from either memory or IO space. * + * LIMITATIONS: + * bit_width must be exactly 8, 16, 32, or 64. + * space_iD must be system_memory or system_iO. + * bit_offset and access_width are currently ignored, as there has + * not been a need to implement these. + * ******************************************************************************/ -acpi_status acpi_read(u32 *value, struct acpi_generic_address *reg) +acpi_status acpi_read(u64 *return_value, struct acpi_generic_address *reg) { + u32 value; u32 width; u64 address; acpi_status status; ACPI_FUNCTION_NAME(acpi_read); - /* - * Must have a valid pointer to a GAS structure, and a non-zero address - * within. - */ - if (!reg) { + if (!return_value) { return (AE_BAD_PARAMETER); } - /* Get a local copy of the address. Handles possible alignment issues */ + /* Validate contents of the GAS register. Allow 64-bit transfers */ - ACPI_MOVE_64_TO_64(&address, ®->address); - if (!address) { - return (AE_BAD_ADDRESS); + status = acpi_hw_validate_register(reg, 64, &address); + if (ACPI_FAILURE(status)) { + return (status); } - /* Supported widths are 8/16/32 */ - width = reg->bit_width; - if ((width != 8) && (width != 16) && (width != 32)) { - return (AE_SUPPORT); + if (width == 64) { + width = 32; /* Break into two 32-bit transfers */ } - /* Initialize entire 32-bit return value to zero */ + /* Initialize entire 64-bit return value to zero */ - *value = 0; + *return_value = 0; + value = 0; /* * Two address spaces supported: Memory or IO. PCI_Config is * not supported here because the GAS structure is insufficient */ - switch (reg->space_id) { - case ACPI_ADR_SPACE_SYSTEM_MEMORY: + if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { + status = acpi_os_read_memory((acpi_physical_address) + address, &value, width); + if (ACPI_FAILURE(status)) { + return (status); + } + *return_value = value; + + if (reg->bit_width == 64) { - status = acpi_os_read_memory((acpi_physical_address) address, - value, width); - break; + /* Read the top 32 bits */ - case ACPI_ADR_SPACE_SYSTEM_IO: + status = acpi_os_read_memory((acpi_physical_address) + (address + 4), &value, 32); + if (ACPI_FAILURE(status)) { + return (status); + } + *return_value |= ((u64)value << 32); + } + } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ - status = - acpi_hw_read_port((acpi_io_address) address, value, width); - break; + status = acpi_hw_read_port((acpi_io_address) + address, &value, width); + if (ACPI_FAILURE(status)) { + return (status); + } + *return_value = value; - default: - ACPI_ERROR((AE_INFO, - "Unsupported address space: %X", reg->space_id)); - return (AE_BAD_PARAMETER); + if (reg->bit_width == 64) { + + /* Read the top 32 bits */ + + status = acpi_hw_read_port((acpi_io_address) + (address + 4), &value, 32); + if (ACPI_FAILURE(status)) { + return (status); + } + *return_value |= ((u64)value << 32); + } } ACPI_DEBUG_PRINT((ACPI_DB_IO, - "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n", - *value, width, ACPI_FORMAT_UINT64(address), + "Read: %8.8X%8.8X width %2d from %8.8X%8.8X (%s)\n", + ACPI_FORMAT_UINT64(*return_value), reg->bit_width, + ACPI_FORMAT_UINT64(address), acpi_ut_get_region_name(reg->space_id))); return (status); @@ -169,7 +194,7 @@ ACPI_EXPORT_SYMBOL(acpi_read) * * FUNCTION: acpi_write * - * PARAMETERS: Value - To be written + * PARAMETERS: Value - Value to be written * Reg - GAS register structure * * RETURN: Status @@ -177,7 +202,7 @@ ACPI_EXPORT_SYMBOL(acpi_read) * DESCRIPTION: Write to either memory or IO space. * ******************************************************************************/ -acpi_status acpi_write(u32 value, struct acpi_generic_address *reg) +acpi_status acpi_write(u64 value, struct acpi_generic_address *reg) { u32 width; u64 address; @@ -185,54 +210,61 @@ acpi_status acpi_write(u32 value, struct acpi_generic_address *reg) ACPI_FUNCTION_NAME(acpi_write); - /* - * Must have a valid pointer to a GAS structure, and a non-zero address - * within. - */ - if (!reg) { - return (AE_BAD_PARAMETER); - } + /* Validate contents of the GAS register. Allow 64-bit transfers */ - /* Get a local copy of the address. Handles possible alignment issues */ - - ACPI_MOVE_64_TO_64(&address, ®->address); - if (!address) { - return (AE_BAD_ADDRESS); + status = acpi_hw_validate_register(reg, 64, &address); + if (ACPI_FAILURE(status)) { + return (status); } - /* Supported widths are 8/16/32 */ - width = reg->bit_width; - if ((width != 8) && (width != 16) && (width != 32)) { - return (AE_SUPPORT); + if (width == 64) { + width = 32; /* Break into two 32-bit transfers */ } /* - * Two address spaces supported: Memory or IO. - * PCI_Config is not supported here because the GAS struct is insufficient + * Two address spaces supported: Memory or IO. PCI_Config is + * not supported here because the GAS structure is insufficient */ - switch (reg->space_id) { - case ACPI_ADR_SPACE_SYSTEM_MEMORY: - - status = acpi_os_write_memory((acpi_physical_address) address, - value, width); - break; + if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { + status = acpi_os_write_memory((acpi_physical_address) + address, ACPI_LODWORD(value), + width); + if (ACPI_FAILURE(status)) { + return (status); + } - case ACPI_ADR_SPACE_SYSTEM_IO: + if (reg->bit_width == 64) { + status = acpi_os_write_memory((acpi_physical_address) + (address + 4), + ACPI_HIDWORD(value), 32); + if (ACPI_FAILURE(status)) { + return (status); + } + } + } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ - status = acpi_hw_write_port((acpi_io_address) address, value, + status = acpi_hw_write_port((acpi_io_address) + address, ACPI_LODWORD(value), width); - break; + if (ACPI_FAILURE(status)) { + return (status); + } - default: - ACPI_ERROR((AE_INFO, - "Unsupported address space: %X", reg->space_id)); - return (AE_BAD_PARAMETER); + if (reg->bit_width == 64) { + status = acpi_hw_write_port((acpi_io_address) + (address + 4), + ACPI_HIDWORD(value), 32); + if (ACPI_FAILURE(status)) { + return (status); + } + } } ACPI_DEBUG_PRINT((ACPI_DB_IO, - "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n", - value, width, ACPI_FORMAT_UINT64(address), + "Wrote: %8.8X%8.8X width %2d to %8.8X%8.8X (%s)\n", + ACPI_FORMAT_UINT64(value), reg->bit_width, + ACPI_FORMAT_UINT64(address), acpi_ut_get_region_name(reg->space_id))); return (status); diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index 2aecaa5..b450a19 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -360,9 +360,9 @@ acpi_status acpi_set_firmware_waking_vector(u32 physical_address); acpi_status acpi_set_firmware_waking_vector64(u64 physical_address); #endif -acpi_status acpi_read(u32 *value, struct acpi_generic_address *reg); +acpi_status acpi_read(u64 *value, struct acpi_generic_address *reg); -acpi_status acpi_write(u32 value, struct acpi_generic_address *reg); +acpi_status acpi_write(u64 value, struct acpi_generic_address *reg); acpi_status acpi_get_sleep_type_data(u8 sleep_state, u8 * slp_typ_a, u8 * slp_typ_b); -- cgit v0.10.2 From 9c61b34cf7078da72cce276ff8cfae5d6e9955bc Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Wed, 24 Jun 2009 09:45:17 +0800 Subject: ACPICA: Remove duplicate prototypes from header Two duplicates in acdebug.h. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/acdebug.h b/drivers/acpi/acpica/acdebug.h index 62c59df..a4fb001 100644 --- a/drivers/acpi/acpica/acdebug.h +++ b/drivers/acpi/acpica/acdebug.h @@ -154,10 +154,6 @@ void acpi_db_display_argument_object(union acpi_operand_object *obj_desc, struct acpi_walk_state *walk_state); -void acpi_db_check_predefined_names(void); - -void acpi_db_batch_execute(void); - /* * dbexec - debugger control method execution */ -- cgit v0.10.2 From 15b8dd53f5ffaf8e2d9095c423f713423f576c0f Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Mon, 29 Jun 2009 13:39:29 +0800 Subject: ACPICA: Major update for acpi_get_object_info external interface Completed a major update for the acpi_get_object_info external interface. Changes include: - Support for variable, unlimited length HID, UID, and CID strings - Support Processor objects the same as Devices (HID,UID,CID,ADR,STA, etc.) - Call the _SxW power methods on behalf of a device object - Determine if a device is a PCI root bridge - Change the ACPI_BUFFER parameter to ACPI_DEVICE_INFO. These changes will require an update to all callers of this interface. See the ACPICA Programmer Reference for details. Also, update all invocations of acpi_get_object_info interface Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c index 8cfb001..674a837 100644 --- a/arch/ia64/hp/common/sba_iommu.c +++ b/arch/ia64/hp/common/sba_iommu.c @@ -2026,24 +2026,21 @@ acpi_sba_ioc_add(struct acpi_device *device) struct ioc *ioc; acpi_status status; u64 hpa, length; - struct acpi_buffer buffer; struct acpi_device_info *dev_info; status = hp_acpi_csr_space(device->handle, &hpa, &length); if (ACPI_FAILURE(status)) return 1; - buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER; - status = acpi_get_object_info(device->handle, &buffer); + status = acpi_get_object_info(device->handle, &dev_info); if (ACPI_FAILURE(status)) return 1; - dev_info = buffer.pointer; /* * For HWP0001, only SBA appears in ACPI namespace. It encloses the PCI * root bridges, and its CSR space includes the IOC function. */ - if (strncmp("HWP0001", dev_info->hardware_id.value, 7) == 0) { + if (strncmp("HWP0001", dev_info->hardware_id.string, 7) == 0) { hpa += ZX1_IOC_OFFSET; /* zx1 based systems default to kernel page size iommu pages */ if (!iovp_shift) diff --git a/drivers/acpi/acpi_memhotplug.c b/drivers/acpi/acpi_memhotplug.c index 9a62224..80eacbe 100644 --- a/drivers/acpi/acpi_memhotplug.c +++ b/drivers/acpi/acpi_memhotplug.c @@ -481,26 +481,23 @@ static acpi_status is_memory_device(acpi_handle handle) { char *hardware_id; acpi_status status; - struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; struct acpi_device_info *info; - - status = acpi_get_object_info(handle, &buffer); + status = acpi_get_object_info(handle, &info); if (ACPI_FAILURE(status)) return status; - info = buffer.pointer; if (!(info->valid & ACPI_VALID_HID)) { - kfree(buffer.pointer); + kfree(info); return AE_ERROR; } - hardware_id = info->hardware_id.value; + hardware_id = info->hardware_id.string; if ((hardware_id == NULL) || (strcmp(hardware_id, ACPI_MEMORY_DEVICE_HID))) status = AE_ERROR; - kfree(buffer.pointer); + kfree(info); return status; } diff --git a/drivers/acpi/acpica/Makefile b/drivers/acpi/acpica/Makefile index 72ac28d..0e7d561 100644 --- a/drivers/acpi/acpica/Makefile +++ b/drivers/acpi/acpica/Makefile @@ -44,4 +44,4 @@ acpi-y += tbxface.o tbinstal.o tbutils.o tbfind.o tbfadt.o tbxfroot.o acpi-y += utalloc.o utdebug.o uteval.o utinit.o utmisc.o utxface.o \ utcopy.o utdelete.o utglobal.o utmath.o utobject.o \ - utstate.o utmutex.o utobject.o utresrc.o utlock.o + utstate.o utmutex.o utobject.o utresrc.o utlock.o utids.o diff --git a/drivers/acpi/acpica/acconfig.h b/drivers/acpi/acpica/acconfig.h index e6777fb..6c1fb2d 100644 --- a/drivers/acpi/acpica/acconfig.h +++ b/drivers/acpi/acpica/acconfig.h @@ -203,6 +203,11 @@ #define ACPI_SMBUS_BUFFER_SIZE 34 +/* _sx_d and _sx_w control methods */ + +#define ACPI_NUM_sx_d_METHODS 4 +#define ACPI_NUM_sx_w_METHODS 5 + /****************************************************************************** * * ACPI AML Debugger diff --git a/drivers/acpi/acpica/acglobal.h b/drivers/acpi/acpica/acglobal.h index 0b73b31..6389f7c 100644 --- a/drivers/acpi/acpica/acglobal.h +++ b/drivers/acpi/acpica/acglobal.h @@ -265,7 +265,8 @@ ACPI_EXTERN u8 acpi_gbl_osi_data; extern u8 acpi_gbl_shutdown; extern u32 acpi_gbl_startup_flags; extern const char *acpi_gbl_sleep_state_names[ACPI_S_STATE_COUNT]; -extern const char *acpi_gbl_highest_dstate_names[4]; +extern const char *acpi_gbl_lowest_dstate_names[ACPI_NUM_sx_w_METHODS]; +extern const char *acpi_gbl_highest_dstate_names[ACPI_NUM_sx_d_METHODS]; extern const struct acpi_opcode_info acpi_gbl_aml_op_info[AML_NUM_OPCODES]; extern const char *acpi_gbl_region_types[ACPI_NUM_PREDEFINED_REGIONS]; diff --git a/drivers/acpi/acpica/acinterp.h b/drivers/acpi/acpica/acinterp.h index e8db7a3..5db9f29 100644 --- a/drivers/acpi/acpica/acinterp.h +++ b/drivers/acpi/acpica/acinterp.h @@ -461,9 +461,9 @@ void acpi_ex_acquire_global_lock(u32 rule); void acpi_ex_release_global_lock(u32 rule); -void acpi_ex_eisa_id_to_string(u32 numeric_id, char *out_string); +void acpi_ex_eisa_id_to_string(char *dest, acpi_integer compressed_id); -void acpi_ex_unsigned_integer_to_string(acpi_integer value, char *out_string); +void acpi_ex_integer_to_string(char *dest, acpi_integer value); /* * exregion - default op_region handlers diff --git a/drivers/acpi/acpica/acutils.h b/drivers/acpi/acpica/acutils.h index 897810b..b0add85 100644 --- a/drivers/acpi/acpica/acutils.h +++ b/drivers/acpi/acpica/acutils.h @@ -324,26 +324,30 @@ acpi_ut_evaluate_object(struct acpi_namespace_node *prefix_node, acpi_status acpi_ut_evaluate_numeric_object(char *object_name, struct acpi_namespace_node *device_node, - acpi_integer * address); + acpi_integer *value); acpi_status -acpi_ut_execute_HID(struct acpi_namespace_node *device_node, - struct acpica_device_id *hid); +acpi_ut_execute_STA(struct acpi_namespace_node *device_node, u32 *status_flags); acpi_status -acpi_ut_execute_CID(struct acpi_namespace_node *device_node, - struct acpi_compatible_id_list **return_cid_list); +acpi_ut_execute_power_methods(struct acpi_namespace_node *device_node, + const char **method_names, + u8 method_count, u8 *out_values); +/* + * utids - device ID support + */ acpi_status -acpi_ut_execute_STA(struct acpi_namespace_node *device_node, - u32 * status_flags); +acpi_ut_execute_HID(struct acpi_namespace_node *device_node, + struct acpica_device_id **return_id); acpi_status acpi_ut_execute_UID(struct acpi_namespace_node *device_node, - struct acpica_device_id *uid); + struct acpica_device_id **return_id); acpi_status -acpi_ut_execute_sxds(struct acpi_namespace_node *device_node, u8 * highest); +acpi_ut_execute_CID(struct acpi_namespace_node *device_node, + struct acpica_device_id_list **return_cid_list); /* * utlock - reader/writer locks @@ -445,6 +449,8 @@ acpi_ut_short_divide(acpi_integer in_dividend, */ const char *acpi_ut_validate_exception(acpi_status status); +u8 acpi_ut_is_pci_root_bridge(char *id); + u8 acpi_ut_is_aml_table(struct acpi_table_header *table); acpi_status acpi_ut_allocate_owner_id(acpi_owner_id * owner_id); diff --git a/drivers/acpi/acpica/evrgnini.c b/drivers/acpi/acpica/evrgnini.c index 284a7be..cf29c49 100644 --- a/drivers/acpi/acpica/evrgnini.c +++ b/drivers/acpi/acpica/evrgnini.c @@ -50,8 +50,6 @@ ACPI_MODULE_NAME("evrgnini") /* Local prototypes */ -static u8 acpi_ev_match_pci_root_bridge(char *id); - static u8 acpi_ev_is_pci_root_bridge(struct acpi_namespace_node *node); /******************************************************************************* @@ -332,37 +330,6 @@ acpi_ev_pci_config_region_setup(acpi_handle handle, /******************************************************************************* * - * FUNCTION: acpi_ev_match_pci_root_bridge - * - * PARAMETERS: Id - The HID/CID in string format - * - * RETURN: TRUE if the Id is a match for a PCI/PCI-Express Root Bridge - * - * DESCRIPTION: Determine if the input ID is a PCI Root Bridge ID. - * - ******************************************************************************/ - -static u8 acpi_ev_match_pci_root_bridge(char *id) -{ - - /* - * Check if this is a PCI root. - * ACPI 3.0+: check for a PCI Express root also. - */ - if (!(ACPI_STRNCMP(id, - PCI_ROOT_HID_STRING, - sizeof(PCI_ROOT_HID_STRING))) || - !(ACPI_STRNCMP(id, - PCI_EXPRESS_ROOT_HID_STRING, - sizeof(PCI_EXPRESS_ROOT_HID_STRING)))) { - return (TRUE); - } - - return (FALSE); -} - -/******************************************************************************* - * * FUNCTION: acpi_ev_is_pci_root_bridge * * PARAMETERS: Node - Device node being examined @@ -377,9 +344,10 @@ static u8 acpi_ev_match_pci_root_bridge(char *id) static u8 acpi_ev_is_pci_root_bridge(struct acpi_namespace_node *node) { acpi_status status; - struct acpica_device_id hid; - struct acpi_compatible_id_list *cid; + struct acpica_device_id *hid; + struct acpica_device_id_list *cid; u32 i; + u8 match; /* Get the _HID and check for a PCI Root Bridge */ @@ -388,7 +356,10 @@ static u8 acpi_ev_is_pci_root_bridge(struct acpi_namespace_node *node) return (FALSE); } - if (acpi_ev_match_pci_root_bridge(hid.value)) { + match = acpi_ut_is_pci_root_bridge(hid->string); + ACPI_FREE(hid); + + if (match) { return (TRUE); } @@ -402,7 +373,7 @@ static u8 acpi_ev_is_pci_root_bridge(struct acpi_namespace_node *node) /* Check all _CIDs in the returned list */ for (i = 0; i < cid->count; i++) { - if (acpi_ev_match_pci_root_bridge(cid->id[i].value)) { + if (acpi_ut_is_pci_root_bridge(cid->ids[i].string)) { ACPI_FREE(cid); return (TRUE); } diff --git a/drivers/acpi/acpica/exutils.c b/drivers/acpi/acpica/exutils.c index 87730e9..7d41f99 100644 --- a/drivers/acpi/acpica/exutils.c +++ b/drivers/acpi/acpica/exutils.c @@ -358,50 +358,67 @@ static u32 acpi_ex_digits_needed(acpi_integer value, u32 base) * * FUNCTION: acpi_ex_eisa_id_to_string * - * PARAMETERS: numeric_id - EISA ID to be converted + * PARAMETERS: compressed_id - EISAID to be converted * out_string - Where to put the converted string (8 bytes) * * RETURN: None * - * DESCRIPTION: Convert a numeric EISA ID to string representation + * DESCRIPTION: Convert a numeric EISAID to string representation. Return + * buffer must be large enough to hold the string. The string + * returned is always exactly of length ACPI_EISAID_STRING_SIZE + * (includes null terminator). The EISAID is always 32 bits. * ******************************************************************************/ -void acpi_ex_eisa_id_to_string(u32 numeric_id, char *out_string) +void acpi_ex_eisa_id_to_string(char *out_string, acpi_integer compressed_id) { - u32 eisa_id; + u32 swapped_id; ACPI_FUNCTION_ENTRY(); + /* The EISAID should be a 32-bit integer */ + + if (compressed_id > ACPI_UINT32_MAX) { + ACPI_WARNING((AE_INFO, + "Expected EISAID is larger than 32 bits: 0x%8.8X%8.8X, truncating", + ACPI_FORMAT_UINT64(compressed_id))); + } + /* Swap ID to big-endian to get contiguous bits */ - eisa_id = acpi_ut_dword_byte_swap(numeric_id); + swapped_id = acpi_ut_dword_byte_swap((u32)compressed_id); - out_string[0] = (char)('@' + (((unsigned long)eisa_id >> 26) & 0x1f)); - out_string[1] = (char)('@' + ((eisa_id >> 21) & 0x1f)); - out_string[2] = (char)('@' + ((eisa_id >> 16) & 0x1f)); - out_string[3] = acpi_ut_hex_to_ascii_char((acpi_integer) eisa_id, 12); - out_string[4] = acpi_ut_hex_to_ascii_char((acpi_integer) eisa_id, 8); - out_string[5] = acpi_ut_hex_to_ascii_char((acpi_integer) eisa_id, 4); - out_string[6] = acpi_ut_hex_to_ascii_char((acpi_integer) eisa_id, 0); + /* First 3 bytes are uppercase letters. Next 4 bytes are hexadecimal */ + + out_string[0] = + (char)(0x40 + (((unsigned long)swapped_id >> 26) & 0x1F)); + out_string[1] = (char)(0x40 + ((swapped_id >> 21) & 0x1F)); + out_string[2] = (char)(0x40 + ((swapped_id >> 16) & 0x1F)); + out_string[3] = acpi_ut_hex_to_ascii_char((acpi_integer)swapped_id, 12); + out_string[4] = acpi_ut_hex_to_ascii_char((acpi_integer)swapped_id, 8); + out_string[5] = acpi_ut_hex_to_ascii_char((acpi_integer)swapped_id, 4); + out_string[6] = acpi_ut_hex_to_ascii_char((acpi_integer)swapped_id, 0); out_string[7] = 0; } /******************************************************************************* * - * FUNCTION: acpi_ex_unsigned_integer_to_string + * FUNCTION: acpi_ex_integer_to_string * - * PARAMETERS: Value - Value to be converted - * out_string - Where to put the converted string (8 bytes) + * PARAMETERS: out_string - Where to put the converted string. At least + * 21 bytes are needed to hold the largest + * possible 64-bit integer. + * Value - Value to be converted * * RETURN: None, string * - * DESCRIPTION: Convert a number to string representation. Assumes string - * buffer is large enough to hold the string. + * DESCRIPTION: Convert a 64-bit integer to decimal string representation. + * Assumes string buffer is large enough to hold the string. The + * largest string is (ACPI_MAX64_DECIMAL_DIGITS + 1). * ******************************************************************************/ -void acpi_ex_unsigned_integer_to_string(acpi_integer value, char *out_string) +void acpi_ex_integer_to_string(char *out_string, acpi_integer value) { u32 count; u32 digits_needed; diff --git a/drivers/acpi/acpica/nsdumpdv.c b/drivers/acpi/acpica/nsdumpdv.c index 41994fe..0fe87f1 100644 --- a/drivers/acpi/acpica/nsdumpdv.c +++ b/drivers/acpi/acpica/nsdumpdv.c @@ -70,7 +70,6 @@ static acpi_status acpi_ns_dump_one_device(acpi_handle obj_handle, u32 level, void *context, void **return_value) { - struct acpi_buffer buffer; struct acpi_device_info *info; acpi_status status; u32 i; @@ -80,17 +79,15 @@ acpi_ns_dump_one_device(acpi_handle obj_handle, status = acpi_ns_dump_one_object(obj_handle, level, context, return_value); - buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER; - status = acpi_get_object_info(obj_handle, &buffer); + status = acpi_get_object_info(obj_handle, &info); if (ACPI_SUCCESS(status)) { - info = buffer.pointer; for (i = 0; i < level; i++) { ACPI_DEBUG_PRINT_RAW((ACPI_DB_TABLES, " ")); } ACPI_DEBUG_PRINT_RAW((ACPI_DB_TABLES, " HID: %s, ADR: %8.8X%8.8X, Status: %X\n", - info->hardware_id.value, + info->hardware_id.string, ACPI_FORMAT_UINT64(info->address), info->current_status)); ACPI_FREE(info); diff --git a/drivers/acpi/acpica/nsxfeval.c b/drivers/acpi/acpica/nsxfeval.c index daf4ad3..4929dbd 100644 --- a/drivers/acpi/acpica/nsxfeval.c +++ b/drivers/acpi/acpica/nsxfeval.c @@ -535,10 +535,11 @@ acpi_ns_get_device_callback(acpi_handle obj_handle, acpi_status status; struct acpi_namespace_node *node; u32 flags; - struct acpica_device_id hid; - struct acpi_compatible_id_list *cid; + struct acpica_device_id *hid; + struct acpica_device_id_list *cid; u32 i; - int found; + u8 found; + int no_match; status = acpi_ut_acquire_mutex(ACPI_MTX_NAMESPACE); if (ACPI_FAILURE(status)) { @@ -582,10 +583,14 @@ acpi_ns_get_device_callback(acpi_handle obj_handle, return (AE_CTRL_DEPTH); } - if (ACPI_STRNCMP(hid.value, info->hid, sizeof(hid.value)) != 0) { - - /* Get the list of Compatible IDs */ + no_match = ACPI_STRCMP(hid->string, info->hid); + ACPI_FREE(hid); + if (no_match) { + /* + * HID does not match, attempt match within the + * list of Compatible IDs (CIDs) + */ status = acpi_ut_execute_CID(node, &cid); if (status == AE_NOT_FOUND) { return (AE_OK); @@ -597,10 +602,8 @@ acpi_ns_get_device_callback(acpi_handle obj_handle, found = 0; for (i = 0; i < cid->count; i++) { - if (ACPI_STRNCMP(cid->id[i].value, info->hid, - sizeof(struct - acpi_compatible_id)) == - 0) { + if (ACPI_STRCMP(cid->ids[i].string, info->hid) + == 0) { found = 1; break; } diff --git a/drivers/acpi/acpica/nsxfname.c b/drivers/acpi/acpica/nsxfname.c index f23593d..ddc84af 100644 --- a/drivers/acpi/acpica/nsxfname.c +++ b/drivers/acpi/acpica/nsxfname.c @@ -51,6 +51,11 @@ #define _COMPONENT ACPI_NAMESPACE ACPI_MODULE_NAME("nsxfname") +/* Local prototypes */ +static char *acpi_ns_copy_device_id(struct acpica_device_id *dest, + struct acpica_device_id *source, + char *string_area); + /****************************************************************************** * * FUNCTION: acpi_get_handle @@ -68,6 +73,7 @@ ACPI_MODULE_NAME("nsxfname") * namespace handle. * ******************************************************************************/ + acpi_status acpi_get_handle(acpi_handle parent, acpi_string pathname, acpi_handle * ret_handle) @@ -210,10 +216,38 @@ ACPI_EXPORT_SYMBOL(acpi_get_name) /****************************************************************************** * + * FUNCTION: acpi_ns_copy_device_id + * + * PARAMETERS: Dest - Pointer to the destination DEVICE_ID + * Source - Pointer to the source DEVICE_ID + * string_area - Pointer to where to copy the dest string + * + * RETURN: Pointer to the next string area + * + * DESCRIPTION: Copy a single DEVICE_ID, including the string data. + * + ******************************************************************************/ +static char *acpi_ns_copy_device_id(struct acpica_device_id *dest, + struct acpica_device_id *source, + char *string_area) +{ + /* Create the destination DEVICE_ID */ + + dest->string = string_area; + dest->length = source->length; + + /* Copy actual string and return a pointer to the next string area */ + + ACPI_MEMCPY(string_area, source->string, source->length); + return (string_area + source->length); +} + +/****************************************************************************** + * * FUNCTION: acpi_get_object_info * - * PARAMETERS: Handle - Object Handle - * Buffer - Where the info is returned + * PARAMETERS: Handle - Object Handle + * return_buffer - Where the info is returned * * RETURN: Status * @@ -221,33 +255,37 @@ ACPI_EXPORT_SYMBOL(acpi_get_name) * namespace node and possibly by running several standard * control methods (Such as in the case of a device.) * + * For Device and Processor objects, run the Device _HID, _UID, _CID, _STA, + * _ADR, _sx_w, and _sx_d methods. + * + * Note: Allocates the return buffer, must be freed by the caller. + * ******************************************************************************/ + acpi_status -acpi_get_object_info(acpi_handle handle, struct acpi_buffer * buffer) +acpi_get_object_info(acpi_handle handle, + struct acpi_device_info **return_buffer) { - acpi_status status; struct acpi_namespace_node *node; struct acpi_device_info *info; - struct acpi_device_info *return_info; - struct acpi_compatible_id_list *cid_list = NULL; - acpi_size size; + struct acpica_device_id_list *cid_list = NULL; + struct acpica_device_id *hid = NULL; + struct acpica_device_id *uid = NULL; + char *next_id_string; + acpi_object_type type; + acpi_name name; + u8 param_count = 0; + u8 valid = 0; + u32 info_size; + u32 i; + acpi_status status; /* Parameter validation */ - if (!handle || !buffer) { + if (!handle || !return_buffer) { return (AE_BAD_PARAMETER); } - status = acpi_ut_validate_buffer(buffer); - if (ACPI_FAILURE(status)) { - return (status); - } - - info = ACPI_ALLOCATE_ZEROED(sizeof(struct acpi_device_info)); - if (!info) { - return (AE_NO_MEMORY); - } - status = acpi_ut_acquire_mutex(ACPI_MTX_NAMESPACE); if (ACPI_FAILURE(status)) { goto cleanup; @@ -256,66 +294,91 @@ acpi_get_object_info(acpi_handle handle, struct acpi_buffer * buffer) node = acpi_ns_map_handle_to_node(handle); if (!node) { (void)acpi_ut_release_mutex(ACPI_MTX_NAMESPACE); - status = AE_BAD_PARAMETER; - goto cleanup; + return (AE_BAD_PARAMETER); } - /* Init return structure */ - - size = sizeof(struct acpi_device_info); + /* Get the namespace node data while the namespace is locked */ - info->type = node->type; - info->name = node->name.integer; - info->valid = 0; + info_size = sizeof(struct acpi_device_info); + type = node->type; + name = node->name.integer; if (node->type == ACPI_TYPE_METHOD) { - info->param_count = node->object->method.param_count; + param_count = node->object->method.param_count; } status = acpi_ut_release_mutex(ACPI_MTX_NAMESPACE); if (ACPI_FAILURE(status)) { - goto cleanup; + return (status); } - /* If not a device, we are all done */ - - if (info->type == ACPI_TYPE_DEVICE) { + if ((type == ACPI_TYPE_DEVICE) || (type == ACPI_TYPE_PROCESSOR)) { /* - * Get extra info for ACPI Devices objects only: - * Run the Device _HID, _UID, _CID, _STA, _ADR and _sx_d methods. + * Get extra info for ACPI Device/Processor objects only: + * Run the Device _HID, _UID, and _CID methods. * * Note: none of these methods are required, so they may or may - * not be present for this device. The Info->Valid bitfield is used - * to indicate which methods were found and ran successfully. + * not be present for this device. The Info->Valid bitfield is used + * to indicate which methods were found and run successfully. */ /* Execute the Device._HID method */ - status = acpi_ut_execute_HID(node, &info->hardware_id); + status = acpi_ut_execute_HID(node, &hid); if (ACPI_SUCCESS(status)) { - info->valid |= ACPI_VALID_HID; + info_size += hid->length; + valid |= ACPI_VALID_HID; } /* Execute the Device._UID method */ - status = acpi_ut_execute_UID(node, &info->unique_id); + status = acpi_ut_execute_UID(node, &uid); if (ACPI_SUCCESS(status)) { - info->valid |= ACPI_VALID_UID; + info_size += uid->length; + valid |= ACPI_VALID_UID; } /* Execute the Device._CID method */ status = acpi_ut_execute_CID(node, &cid_list); if (ACPI_SUCCESS(status)) { - size += cid_list->size; - info->valid |= ACPI_VALID_CID; + + /* Add size of CID strings and CID pointer array */ + + info_size += + (cid_list->list_size - + sizeof(struct acpica_device_id_list)); + valid |= ACPI_VALID_CID; } + } + + /* + * Now that we have the variable-length data, we can allocate the + * return buffer + */ + info = ACPI_ALLOCATE_ZEROED(info_size); + if (!info) { + status = AE_NO_MEMORY; + goto cleanup; + } + + /* Get the fixed-length data */ + + if ((type == ACPI_TYPE_DEVICE) || (type == ACPI_TYPE_PROCESSOR)) { + /* + * Get extra info for ACPI Device/Processor objects only: + * Run the _STA, _ADR and, sx_w, and _sx_d methods. + * + * Note: none of these methods are required, so they may or may + * not be present for this device. The Info->Valid bitfield is used + * to indicate which methods were found and run successfully. + */ /* Execute the Device._STA method */ status = acpi_ut_execute_STA(node, &info->current_status); if (ACPI_SUCCESS(status)) { - info->valid |= ACPI_VALID_STA; + valid |= ACPI_VALID_STA; } /* Execute the Device._ADR method */ @@ -323,36 +386,100 @@ acpi_get_object_info(acpi_handle handle, struct acpi_buffer * buffer) status = acpi_ut_evaluate_numeric_object(METHOD_NAME__ADR, node, &info->address); if (ACPI_SUCCESS(status)) { - info->valid |= ACPI_VALID_ADR; + valid |= ACPI_VALID_ADR; + } + + /* Execute the Device._sx_w methods */ + + status = acpi_ut_execute_power_methods(node, + acpi_gbl_lowest_dstate_names, + ACPI_NUM_sx_w_METHODS, + info->lowest_dstates); + if (ACPI_SUCCESS(status)) { + valid |= ACPI_VALID_SXWS; } /* Execute the Device._sx_d methods */ - status = acpi_ut_execute_sxds(node, info->highest_dstates); + status = acpi_ut_execute_power_methods(node, + acpi_gbl_highest_dstate_names, + ACPI_NUM_sx_d_METHODS, + info->highest_dstates); if (ACPI_SUCCESS(status)) { - info->valid |= ACPI_VALID_SXDS; + valid |= ACPI_VALID_SXDS; } } - /* Validate/Allocate/Clear caller buffer */ + /* + * Create a pointer to the string area of the return buffer. + * Point to the end of the base struct acpi_device_info structure. + */ + next_id_string = ACPI_CAST_PTR(char, info->compatible_id_list.ids); + if (cid_list) { - status = acpi_ut_initialize_buffer(buffer, size); - if (ACPI_FAILURE(status)) { - goto cleanup; + /* Point past the CID DEVICE_ID array */ + + next_id_string += + ((acpi_size) cid_list->count * + sizeof(struct acpica_device_id)); } - /* Populate the return buffer */ + /* + * Copy the HID, UID, and CIDs to the return buffer. The variable-length + * strings are copied to the reserved area at the end of the buffer. + * + * For HID and CID, check if the ID is a PCI Root Bridge. + */ + if (hid) { + next_id_string = acpi_ns_copy_device_id(&info->hardware_id, + hid, next_id_string); + + if (acpi_ut_is_pci_root_bridge(hid->string)) { + info->flags |= ACPI_PCI_ROOT_BRIDGE; + } + } - return_info = buffer->pointer; - ACPI_MEMCPY(return_info, info, sizeof(struct acpi_device_info)); + if (uid) { + next_id_string = acpi_ns_copy_device_id(&info->unique_id, + uid, next_id_string); + } if (cid_list) { - ACPI_MEMCPY(&return_info->compatibility_id, cid_list, - cid_list->size); + info->compatible_id_list.count = cid_list->count; + info->compatible_id_list.list_size = cid_list->list_size; + + /* Copy each CID */ + + for (i = 0; i < cid_list->count; i++) { + next_id_string = + acpi_ns_copy_device_id(&info->compatible_id_list. + ids[i], &cid_list->ids[i], + next_id_string); + + if (acpi_ut_is_pci_root_bridge(cid_list->ids[i].string)) { + info->flags |= ACPI_PCI_ROOT_BRIDGE; + } + } } + /* Copy the fixed-length data */ + + info->info_size = info_size; + info->type = type; + info->name = name; + info->param_count = param_count; + info->valid = valid; + + *return_buffer = info; + status = AE_OK; + cleanup: - ACPI_FREE(info); + if (hid) { + ACPI_FREE(hid); + } + if (uid) { + ACPI_FREE(uid); + } if (cid_list) { ACPI_FREE(cid_list); } diff --git a/drivers/acpi/acpica/uteval.c b/drivers/acpi/acpica/uteval.c index 006b16c..5503307 100644 --- a/drivers/acpi/acpica/uteval.c +++ b/drivers/acpi/acpica/uteval.c @@ -44,19 +44,10 @@ #include #include "accommon.h" #include "acnamesp.h" -#include "acinterp.h" #define _COMPONENT ACPI_UTILITIES ACPI_MODULE_NAME("uteval") -/* Local prototypes */ -static void -acpi_ut_copy_id_string(char *destination, char *source, acpi_size max_length); - -static acpi_status -acpi_ut_translate_one_cid(union acpi_operand_object *obj_desc, - struct acpi_compatible_id *one_cid); - /* * Strings supported by the _OSI predefined (internal) method. * @@ -213,7 +204,7 @@ acpi_status acpi_osi_invalidate(char *interface) * RETURN: Status * * DESCRIPTION: Evaluates a namespace object and verifies the type of the - * return object. Common code that simplifies accessing objects + * return object. Common code that simplifies accessing objects * that have required return objects of fixed types. * * NOTE: Internal function, no parameter validation @@ -298,7 +289,7 @@ acpi_ut_evaluate_object(struct acpi_namespace_node *prefix_node, if ((acpi_gbl_enable_interpreter_slack) && (!expected_return_btypes)) { /* - * We received a return object, but one was not expected. This can + * We received a return object, but one was not expected. This can * happen frequently if the "implicit return" feature is enabled. * Just delete the return object and return AE_OK. */ @@ -340,12 +331,12 @@ acpi_ut_evaluate_object(struct acpi_namespace_node *prefix_node, * * PARAMETERS: object_name - Object name to be evaluated * device_node - Node for the device - * Address - Where the value is returned + * Value - Where the value is returned * * RETURN: Status * * DESCRIPTION: Evaluates a numeric namespace object for a selected device - * and stores result in *Address. + * and stores result in *Value. * * NOTE: Internal function, no parameter validation * @@ -354,7 +345,7 @@ acpi_ut_evaluate_object(struct acpi_namespace_node *prefix_node, acpi_status acpi_ut_evaluate_numeric_object(char *object_name, struct acpi_namespace_node *device_node, - acpi_integer * address) + acpi_integer *value) { union acpi_operand_object *obj_desc; acpi_status status; @@ -369,295 +360,7 @@ acpi_ut_evaluate_numeric_object(char *object_name, /* Get the returned Integer */ - *address = obj_desc->integer.value; - - /* On exit, we must delete the return object */ - - acpi_ut_remove_reference(obj_desc); - return_ACPI_STATUS(status); -} - -/******************************************************************************* - * - * FUNCTION: acpi_ut_copy_id_string - * - * PARAMETERS: Destination - Where to copy the string - * Source - Source string - * max_length - Length of the destination buffer - * - * RETURN: None - * - * DESCRIPTION: Copies an ID string for the _HID, _CID, and _UID methods. - * Performs removal of a leading asterisk if present -- workaround - * for a known issue on a bunch of machines. - * - ******************************************************************************/ - -static void -acpi_ut_copy_id_string(char *destination, char *source, acpi_size max_length) -{ - - /* - * Workaround for ID strings that have a leading asterisk. This construct - * is not allowed by the ACPI specification (ID strings must be - * alphanumeric), but enough existing machines have this embedded in their - * ID strings that the following code is useful. - */ - if (*source == '*') { - source++; - } - - /* Do the actual copy */ - - ACPI_STRNCPY(destination, source, max_length); -} - -/******************************************************************************* - * - * FUNCTION: acpi_ut_execute_HID - * - * PARAMETERS: device_node - Node for the device - * Hid - Where the HID is returned - * - * RETURN: Status - * - * DESCRIPTION: Executes the _HID control method that returns the hardware - * ID of the device. - * - * NOTE: Internal function, no parameter validation - * - ******************************************************************************/ - -acpi_status -acpi_ut_execute_HID(struct acpi_namespace_node *device_node, - struct acpica_device_id *hid) -{ - union acpi_operand_object *obj_desc; - acpi_status status; - - ACPI_FUNCTION_TRACE(ut_execute_HID); - - status = acpi_ut_evaluate_object(device_node, METHOD_NAME__HID, - ACPI_BTYPE_INTEGER | ACPI_BTYPE_STRING, - &obj_desc); - if (ACPI_FAILURE(status)) { - return_ACPI_STATUS(status); - } - - if (obj_desc->common.type == ACPI_TYPE_INTEGER) { - - /* Convert the Numeric HID to string */ - - acpi_ex_eisa_id_to_string((u32) obj_desc->integer.value, - hid->value); - } else { - /* Copy the String HID from the returned object */ - - acpi_ut_copy_id_string(hid->value, obj_desc->string.pointer, - sizeof(hid->value)); - } - - /* On exit, we must delete the return object */ - - acpi_ut_remove_reference(obj_desc); - return_ACPI_STATUS(status); -} - -/******************************************************************************* - * - * FUNCTION: acpi_ut_translate_one_cid - * - * PARAMETERS: obj_desc - _CID object, must be integer or string - * one_cid - Where the CID string is returned - * - * RETURN: Status - * - * DESCRIPTION: Return a numeric or string _CID value as a string. - * (Compatible ID) - * - * NOTE: Assumes a maximum _CID string length of - * ACPI_MAX_CID_LENGTH. - * - ******************************************************************************/ - -static acpi_status -acpi_ut_translate_one_cid(union acpi_operand_object *obj_desc, - struct acpi_compatible_id *one_cid) -{ - - switch (obj_desc->common.type) { - case ACPI_TYPE_INTEGER: - - /* Convert the Numeric CID to string */ - - acpi_ex_eisa_id_to_string((u32) obj_desc->integer.value, - one_cid->value); - return (AE_OK); - - case ACPI_TYPE_STRING: - - if (obj_desc->string.length > ACPI_MAX_CID_LENGTH) { - return (AE_AML_STRING_LIMIT); - } - - /* Copy the String CID from the returned object */ - - acpi_ut_copy_id_string(one_cid->value, obj_desc->string.pointer, - ACPI_MAX_CID_LENGTH); - return (AE_OK); - - default: - - return (AE_TYPE); - } -} - -/******************************************************************************* - * - * FUNCTION: acpi_ut_execute_CID - * - * PARAMETERS: device_node - Node for the device - * return_cid_list - Where the CID list is returned - * - * RETURN: Status - * - * DESCRIPTION: Executes the _CID control method that returns one or more - * compatible hardware IDs for the device. - * - * NOTE: Internal function, no parameter validation - * - ******************************************************************************/ - -acpi_status -acpi_ut_execute_CID(struct acpi_namespace_node * device_node, - struct acpi_compatible_id_list ** return_cid_list) -{ - union acpi_operand_object *obj_desc; - acpi_status status; - u32 count; - u32 size; - struct acpi_compatible_id_list *cid_list; - u32 i; - - ACPI_FUNCTION_TRACE(ut_execute_CID); - - /* Evaluate the _CID method for this device */ - - status = acpi_ut_evaluate_object(device_node, METHOD_NAME__CID, - ACPI_BTYPE_INTEGER | ACPI_BTYPE_STRING - | ACPI_BTYPE_PACKAGE, &obj_desc); - if (ACPI_FAILURE(status)) { - return_ACPI_STATUS(status); - } - - /* Get the number of _CIDs returned */ - - count = 1; - if (obj_desc->common.type == ACPI_TYPE_PACKAGE) { - count = obj_desc->package.count; - } - - /* Allocate a worst-case buffer for the _CIDs */ - - size = (((count - 1) * sizeof(struct acpi_compatible_id)) + - sizeof(struct acpi_compatible_id_list)); - - cid_list = ACPI_ALLOCATE_ZEROED((acpi_size) size); - if (!cid_list) { - return_ACPI_STATUS(AE_NO_MEMORY); - } - - /* Init CID list */ - - cid_list->count = count; - cid_list->size = size; - - /* - * A _CID can return either a single compatible ID or a package of - * compatible IDs. Each compatible ID can be one of the following: - * 1) Integer (32 bit compressed EISA ID) or - * 2) String (PCI ID format, e.g. "PCI\VEN_vvvv&DEV_dddd&SUBSYS_ssssssss") - */ - - /* The _CID object can be either a single CID or a package (list) of CIDs */ - - if (obj_desc->common.type == ACPI_TYPE_PACKAGE) { - - /* Translate each package element */ - - for (i = 0; i < count; i++) { - status = - acpi_ut_translate_one_cid(obj_desc->package. - elements[i], - &cid_list->id[i]); - if (ACPI_FAILURE(status)) { - break; - } - } - } else { - /* Only one CID, translate to a string */ - - status = acpi_ut_translate_one_cid(obj_desc, cid_list->id); - } - - /* Cleanup on error */ - - if (ACPI_FAILURE(status)) { - ACPI_FREE(cid_list); - } else { - *return_cid_list = cid_list; - } - - /* On exit, we must delete the _CID return object */ - - acpi_ut_remove_reference(obj_desc); - return_ACPI_STATUS(status); -} - -/******************************************************************************* - * - * FUNCTION: acpi_ut_execute_UID - * - * PARAMETERS: device_node - Node for the device - * Uid - Where the UID is returned - * - * RETURN: Status - * - * DESCRIPTION: Executes the _UID control method that returns the hardware - * ID of the device. - * - * NOTE: Internal function, no parameter validation - * - ******************************************************************************/ - -acpi_status -acpi_ut_execute_UID(struct acpi_namespace_node *device_node, - struct acpica_device_id *uid) -{ - union acpi_operand_object *obj_desc; - acpi_status status; - - ACPI_FUNCTION_TRACE(ut_execute_UID); - - status = acpi_ut_evaluate_object(device_node, METHOD_NAME__UID, - ACPI_BTYPE_INTEGER | ACPI_BTYPE_STRING, - &obj_desc); - if (ACPI_FAILURE(status)) { - return_ACPI_STATUS(status); - } - - if (obj_desc->common.type == ACPI_TYPE_INTEGER) { - - /* Convert the Numeric UID to string */ - - acpi_ex_unsigned_integer_to_string(obj_desc->integer.value, - uid->value); - } else { - /* Copy the String UID from the returned object */ - - acpi_ut_copy_id_string(uid->value, obj_desc->string.pointer, - sizeof(uid->value)); - } + *value = obj_desc->integer.value; /* On exit, we must delete the return object */ @@ -716,60 +419,64 @@ acpi_ut_execute_STA(struct acpi_namespace_node *device_node, u32 * flags) /******************************************************************************* * - * FUNCTION: acpi_ut_execute_Sxds + * FUNCTION: acpi_ut_execute_power_methods * * PARAMETERS: device_node - Node for the device - * Flags - Where the status flags are returned + * method_names - Array of power method names + * method_count - Number of methods to execute + * out_values - Where the power method values are returned * - * RETURN: Status + * RETURN: Status, out_values * - * DESCRIPTION: Executes _STA for selected device and stores results in - * *Flags. + * DESCRIPTION: Executes the specified power methods for the device and returns + * the result(s). * * NOTE: Internal function, no parameter validation * - ******************************************************************************/ +******************************************************************************/ acpi_status -acpi_ut_execute_sxds(struct acpi_namespace_node *device_node, u8 * highest) +acpi_ut_execute_power_methods(struct acpi_namespace_node *device_node, + const char **method_names, + u8 method_count, u8 *out_values) { union acpi_operand_object *obj_desc; acpi_status status; + acpi_status final_status = AE_NOT_FOUND; u32 i; - ACPI_FUNCTION_TRACE(ut_execute_sxds); + ACPI_FUNCTION_TRACE(ut_execute_power_methods); - for (i = 0; i < 4; i++) { - highest[i] = 0xFF; + for (i = 0; i < method_count; i++) { + /* + * Execute the power method (_sx_d or _sx_w). The only allowable + * return type is an Integer. + */ status = acpi_ut_evaluate_object(device_node, ACPI_CAST_PTR(char, - acpi_gbl_highest_dstate_names - [i]), + method_names[i]), ACPI_BTYPE_INTEGER, &obj_desc); - if (ACPI_FAILURE(status)) { - if (status != AE_NOT_FOUND) { - ACPI_DEBUG_PRINT((ACPI_DB_EXEC, - "%s on Device %4.4s, %s\n", - ACPI_CAST_PTR(char, - acpi_gbl_highest_dstate_names - [i]), - acpi_ut_get_node_name - (device_node), - acpi_format_exception - (status))); - - return_ACPI_STATUS(status); - } - } else { - /* Extract the Dstate value */ - - highest[i] = (u8) obj_desc->integer.value; + if (ACPI_SUCCESS(status)) { + out_values[i] = (u8)obj_desc->integer.value; /* Delete the return object */ acpi_ut_remove_reference(obj_desc); + final_status = AE_OK; /* At least one value is valid */ + continue; } + + out_values[i] = ACPI_UINT8_MAX; + if (status == AE_NOT_FOUND) { + continue; /* Ignore if not found */ + } + + ACPI_DEBUG_PRINT((ACPI_DB_EXEC, + "Failed %s on Device %4.4s, %s\n", + ACPI_CAST_PTR(char, method_names[i]), + acpi_ut_get_node_name(device_node), + acpi_format_exception(status))); } - return_ACPI_STATUS(AE_OK); + return_ACPI_STATUS(final_status); } diff --git a/drivers/acpi/acpica/utglobal.c b/drivers/acpi/acpica/utglobal.c index 59e46f2..ed7a33c 100644 --- a/drivers/acpi/acpica/utglobal.c +++ b/drivers/acpi/acpica/utglobal.c @@ -90,7 +90,15 @@ const char *acpi_gbl_sleep_state_names[ACPI_S_STATE_COUNT] = { "\\_S5_" }; -const char *acpi_gbl_highest_dstate_names[4] = { +const char *acpi_gbl_lowest_dstate_names[ACPI_NUM_sx_w_METHODS] = { + "_S0W", + "_S1W", + "_S2W", + "_S3W", + "_S4W" +}; + +const char *acpi_gbl_highest_dstate_names[ACPI_NUM_sx_d_METHODS] = { "_S1D", "_S2D", "_S3D", diff --git a/drivers/acpi/acpica/utids.c b/drivers/acpi/acpica/utids.c new file mode 100644 index 0000000..52eaae4 --- /dev/null +++ b/drivers/acpi/acpica/utids.c @@ -0,0 +1,382 @@ +/****************************************************************************** + * + * Module Name: utids - support for device IDs - HID, UID, CID + * + *****************************************************************************/ + +/* + * Copyright (C) 2000 - 2009, Intel Corp. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * substantially similar to the "NO WARRANTY" disclaimer below + * ("Disclaimer") and any redistribution must be conditioned upon + * including a substantially similar Disclaimer requirement for further + * binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGES. + */ + +#include +#include "accommon.h" +#include "acinterp.h" + +#define _COMPONENT ACPI_UTILITIES +ACPI_MODULE_NAME("utids") + +/* Local prototypes */ +static void acpi_ut_copy_id_string(char *destination, char *source); + +/******************************************************************************* + * + * FUNCTION: acpi_ut_copy_id_string + * + * PARAMETERS: Destination - Where to copy the string + * Source - Source string + * + * RETURN: None + * + * DESCRIPTION: Copies an ID string for the _HID, _CID, and _UID methods. + * Performs removal of a leading asterisk if present -- workaround + * for a known issue on a bunch of machines. + * + ******************************************************************************/ + +static void acpi_ut_copy_id_string(char *destination, char *source) +{ + + /* + * Workaround for ID strings that have a leading asterisk. This construct + * is not allowed by the ACPI specification (ID strings must be + * alphanumeric), but enough existing machines have this embedded in their + * ID strings that the following code is useful. + */ + if (*source == '*') { + source++; + } + + /* Do the actual copy */ + + ACPI_STRCPY(destination, source); +} + +/******************************************************************************* + * + * FUNCTION: acpi_ut_execute_HID + * + * PARAMETERS: device_node - Node for the device + * return_id - Where the string HID is returned + * + * RETURN: Status + * + * DESCRIPTION: Executes the _HID control method that returns the hardware + * ID of the device. The HID is either an 32-bit encoded EISAID + * Integer or a String. A string is always returned. An EISAID + * is converted to a string. + * + * NOTE: Internal function, no parameter validation + * + ******************************************************************************/ + +acpi_status +acpi_ut_execute_HID(struct acpi_namespace_node *device_node, + struct acpica_device_id **return_id) +{ + union acpi_operand_object *obj_desc; + struct acpica_device_id *hid; + u32 length; + acpi_status status; + + ACPI_FUNCTION_TRACE(ut_execute_HID); + + status = acpi_ut_evaluate_object(device_node, METHOD_NAME__HID, + ACPI_BTYPE_INTEGER | ACPI_BTYPE_STRING, + &obj_desc); + if (ACPI_FAILURE(status)) { + return_ACPI_STATUS(status); + } + + /* Get the size of the String to be returned, includes null terminator */ + + if (obj_desc->common.type == ACPI_TYPE_INTEGER) { + length = ACPI_EISAID_STRING_SIZE; + } else { + length = obj_desc->string.length + 1; + } + + /* Allocate a buffer for the HID */ + + hid = + ACPI_ALLOCATE_ZEROED(sizeof(struct acpica_device_id) + + (acpi_size) length); + if (!hid) { + status = AE_NO_MEMORY; + goto cleanup; + } + + /* Area for the string starts after DEVICE_ID struct */ + + hid->string = ACPI_ADD_PTR(char, hid, sizeof(struct acpica_device_id)); + + /* Convert EISAID to a string or simply copy existing string */ + + if (obj_desc->common.type == ACPI_TYPE_INTEGER) { + acpi_ex_eisa_id_to_string(hid->string, obj_desc->integer.value); + } else { + acpi_ut_copy_id_string(hid->string, obj_desc->string.pointer); + } + + hid->length = length; + *return_id = hid; + +cleanup: + + /* On exit, we must delete the return object */ + + acpi_ut_remove_reference(obj_desc); + return_ACPI_STATUS(status); +} + +/******************************************************************************* + * + * FUNCTION: acpi_ut_execute_UID + * + * PARAMETERS: device_node - Node for the device + * return_id - Where the string UID is returned + * + * RETURN: Status + * + * DESCRIPTION: Executes the _UID control method that returns the unique + * ID of the device. The UID is either a 64-bit Integer (NOT an + * EISAID) or a string. Always returns a string. A 64-bit integer + * is converted to a decimal string. + * + * NOTE: Internal function, no parameter validation + * + ******************************************************************************/ + +acpi_status +acpi_ut_execute_UID(struct acpi_namespace_node *device_node, + struct acpica_device_id **return_id) +{ + union acpi_operand_object *obj_desc; + struct acpica_device_id *uid; + u32 length; + acpi_status status; + + ACPI_FUNCTION_TRACE(ut_execute_UID); + + status = acpi_ut_evaluate_object(device_node, METHOD_NAME__UID, + ACPI_BTYPE_INTEGER | ACPI_BTYPE_STRING, + &obj_desc); + if (ACPI_FAILURE(status)) { + return_ACPI_STATUS(status); + } + + /* Get the size of the String to be returned, includes null terminator */ + + if (obj_desc->common.type == ACPI_TYPE_INTEGER) { + length = ACPI_MAX64_DECIMAL_DIGITS + 1; + } else { + length = obj_desc->string.length + 1; + } + + /* Allocate a buffer for the UID */ + + uid = + ACPI_ALLOCATE_ZEROED(sizeof(struct acpica_device_id) + + (acpi_size) length); + if (!uid) { + status = AE_NO_MEMORY; + goto cleanup; + } + + /* Area for the string starts after DEVICE_ID struct */ + + uid->string = ACPI_ADD_PTR(char, uid, sizeof(struct acpica_device_id)); + + /* Convert an Integer to string, or just copy an existing string */ + + if (obj_desc->common.type == ACPI_TYPE_INTEGER) { + acpi_ex_integer_to_string(uid->string, obj_desc->integer.value); + } else { + acpi_ut_copy_id_string(uid->string, obj_desc->string.pointer); + } + + uid->length = length; + *return_id = uid; + +cleanup: + + /* On exit, we must delete the return object */ + + acpi_ut_remove_reference(obj_desc); + return_ACPI_STATUS(status); +} + +/******************************************************************************* + * + * FUNCTION: acpi_ut_execute_CID + * + * PARAMETERS: device_node - Node for the device + * return_cid_list - Where the CID list is returned + * + * RETURN: Status, list of CID strings + * + * DESCRIPTION: Executes the _CID control method that returns one or more + * compatible hardware IDs for the device. + * + * NOTE: Internal function, no parameter validation + * + * A _CID method can return either a single compatible ID or a package of + * compatible IDs. Each compatible ID can be one of the following: + * 1) Integer (32 bit compressed EISA ID) or + * 2) String (PCI ID format, e.g. "PCI\VEN_vvvv&DEV_dddd&SUBSYS_ssssssss") + * + * The Integer CIDs are converted to string format by this function. + * + ******************************************************************************/ + +acpi_status +acpi_ut_execute_CID(struct acpi_namespace_node *device_node, + struct acpica_device_id_list **return_cid_list) +{ + union acpi_operand_object **cid_objects; + union acpi_operand_object *obj_desc; + struct acpica_device_id_list *cid_list; + char *next_id_string; + u32 string_area_size; + u32 length; + u32 cid_list_size; + acpi_status status; + u32 count; + u32 i; + + ACPI_FUNCTION_TRACE(ut_execute_CID); + + /* Evaluate the _CID method for this device */ + + status = acpi_ut_evaluate_object(device_node, METHOD_NAME__CID, + ACPI_BTYPE_INTEGER | ACPI_BTYPE_STRING + | ACPI_BTYPE_PACKAGE, &obj_desc); + if (ACPI_FAILURE(status)) { + return_ACPI_STATUS(status); + } + + /* + * Get the count and size of the returned _CIDs. _CID can return either + * a Package of Integers/Strings or a single Integer or String. + * Note: This section also validates that all CID elements are of the + * correct type (Integer or String). + */ + if (obj_desc->common.type == ACPI_TYPE_PACKAGE) { + count = obj_desc->package.count; + cid_objects = obj_desc->package.elements; + } else { /* Single Integer or String CID */ + + count = 1; + cid_objects = &obj_desc; + } + + string_area_size = 0; + for (i = 0; i < count; i++) { + + /* String lengths include null terminator */ + + switch (cid_objects[i]->common.type) { + case ACPI_TYPE_INTEGER: + string_area_size += ACPI_EISAID_STRING_SIZE; + break; + + case ACPI_TYPE_STRING: + string_area_size += cid_objects[i]->string.length + 1; + break; + + default: + status = AE_TYPE; + goto cleanup; + } + } + + /* + * Now that we know the length of the CIDs, allocate return buffer: + * 1) Size of the base structure + + * 2) Size of the CID DEVICE_ID array + + * 3) Size of the actual CID strings + */ + cid_list_size = sizeof(struct acpica_device_id_list) + + ((count - 1) * sizeof(struct acpica_device_id)) + string_area_size; + + cid_list = ACPI_ALLOCATE_ZEROED(cid_list_size); + if (!cid_list) { + status = AE_NO_MEMORY; + goto cleanup; + } + + /* Area for CID strings starts after the CID DEVICE_ID array */ + + next_id_string = ACPI_CAST_PTR(char, cid_list->ids) + + ((acpi_size) count * sizeof(struct acpica_device_id)); + + /* Copy/convert the CIDs to the return buffer */ + + for (i = 0; i < count; i++) { + if (cid_objects[i]->common.type == ACPI_TYPE_INTEGER) { + + /* Convert the Integer (EISAID) CID to a string */ + + acpi_ex_eisa_id_to_string(next_id_string, + cid_objects[i]->integer. + value); + length = ACPI_EISAID_STRING_SIZE; + } else { /* ACPI_TYPE_STRING */ + + /* Copy the String CID from the returned object */ + + acpi_ut_copy_id_string(next_id_string, + cid_objects[i]->string.pointer); + length = cid_objects[i]->string.length + 1; + } + + cid_list->ids[i].string = next_id_string; + cid_list->ids[i].length = length; + next_id_string += length; + } + + /* Finish the CID list */ + + cid_list->count = count; + cid_list->list_size = cid_list_size; + *return_cid_list = cid_list; + +cleanup: + + /* On exit, we must delete the _CID return object */ + + acpi_ut_remove_reference(obj_desc); + return_ACPI_STATUS(status); +} diff --git a/drivers/acpi/acpica/utmisc.c b/drivers/acpi/acpica/utmisc.c index fbe7823..9cd6533 100644 --- a/drivers/acpi/acpica/utmisc.c +++ b/drivers/acpi/acpica/utmisc.c @@ -120,6 +120,34 @@ const char *acpi_ut_validate_exception(acpi_status status) /******************************************************************************* * + * FUNCTION: acpi_ut_is_pci_root_bridge + * + * PARAMETERS: Id - The HID/CID in string format + * + * RETURN: TRUE if the Id is a match for a PCI/PCI-Express Root Bridge + * + * DESCRIPTION: Determine if the input ID is a PCI Root Bridge ID. + * + ******************************************************************************/ + +u8 acpi_ut_is_pci_root_bridge(char *id) +{ + + /* + * Check if this is a PCI root bridge. + * ACPI 3.0+: check for a PCI Express root also. + */ + if (!(ACPI_STRCMP(id, + PCI_ROOT_HID_STRING)) || + !(ACPI_STRCMP(id, PCI_EXPRESS_ROOT_HID_STRING))) { + return (TRUE); + } + + return (FALSE); +} + +/******************************************************************************* + * * FUNCTION: acpi_ut_is_aml_table * * PARAMETERS: Table - An ACPI table diff --git a/drivers/acpi/container.c b/drivers/acpi/container.c index fe0cdf8..2aee8c2 100644 --- a/drivers/acpi/container.c +++ b/drivers/acpi/container.c @@ -200,20 +200,17 @@ container_walk_namespace_cb(acpi_handle handle, u32 lvl, void *context, void **rv) { char *hid = NULL; - struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; struct acpi_device_info *info; acpi_status status; int *action = context; - - status = acpi_get_object_info(handle, &buffer); - if (ACPI_FAILURE(status) || !buffer.pointer) { + status = acpi_get_object_info(handle, &info); + if (ACPI_FAILURE(status)) { return AE_OK; } - info = buffer.pointer; if (info->valid & ACPI_VALID_HID) - hid = info->hardware_id.value; + hid = info->hardware_id.string; if (hid == NULL) { goto end; @@ -240,7 +237,7 @@ container_walk_namespace_cb(acpi_handle handle, } end: - kfree(buffer.pointer); + kfree(info); return AE_OK; } diff --git a/drivers/acpi/dock.c b/drivers/acpi/dock.c index efb959d..39536b8 100644 --- a/drivers/acpi/dock.c +++ b/drivers/acpi/dock.c @@ -231,18 +231,16 @@ static int is_ata(acpi_handle handle) static int is_battery(acpi_handle handle) { struct acpi_device_info *info; - struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; int ret = 1; - if (!ACPI_SUCCESS(acpi_get_object_info(handle, &buffer))) + if (!ACPI_SUCCESS(acpi_get_object_info(handle, &info))) return 0; - info = buffer.pointer; if (!(info->valid & ACPI_VALID_HID)) ret = 0; else - ret = !strcmp("PNP0C0A", info->hardware_id.value); + ret = !strcmp("PNP0C0A", info->hardware_id.string); - kfree(buffer.pointer); + kfree(info); return ret; } diff --git a/drivers/acpi/glue.c b/drivers/acpi/glue.c index a8a5c29..27a7072 100644 --- a/drivers/acpi/glue.c +++ b/drivers/acpi/glue.c @@ -93,15 +93,13 @@ do_acpi_find_child(acpi_handle handle, u32 lvl, void *context, void **rv) { acpi_status status; struct acpi_device_info *info; - struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; struct acpi_find_child *find = context; - status = acpi_get_object_info(handle, &buffer); + status = acpi_get_object_info(handle, &info); if (ACPI_SUCCESS(status)) { - info = buffer.pointer; if (info->address == find->address) find->handle = handle; - kfree(buffer.pointer); + kfree(info); } return AE_OK; } diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 781435d..0ab526d 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -60,13 +60,13 @@ static int create_modalias(struct acpi_device *acpi_dev, char *modalias, } if (acpi_dev->flags.compatible_ids) { - struct acpi_compatible_id_list *cid_list; + struct acpica_device_id_list *cid_list; int i; cid_list = acpi_dev->pnp.cid_list; for (i = 0; i < cid_list->count; i++) { count = snprintf(&modalias[len], size, "%s:", - cid_list->id[i].value); + cid_list->ids[i].string); if (count < 0 || count >= size) { printk(KERN_ERR PREFIX "%s cid[%i] exceeds event buffer size", acpi_dev->pnp.device_name, i); @@ -287,14 +287,14 @@ int acpi_match_device_ids(struct acpi_device *device, } if (device->flags.compatible_ids) { - struct acpi_compatible_id_list *cid_list = device->pnp.cid_list; + struct acpica_device_id_list *cid_list = device->pnp.cid_list; int i; for (id = ids; id->id[0]; id++) { /* compare multiple _CID entries against driver ids */ for (i = 0; i < cid_list->count; i++) { if (!strcmp((char*)id->id, - cid_list->id[i].value)) + cid_list->ids[i].string)) return 0; } } @@ -999,33 +999,89 @@ static int acpi_dock_match(struct acpi_device *device) return acpi_get_handle(device->handle, "_DCK", &tmp); } +static struct acpica_device_id_list* +acpi_add_cid( + struct acpi_device_info *info, + struct acpica_device_id *new_cid) +{ + struct acpica_device_id_list *cid; + char *next_id_string; + acpi_size cid_length; + acpi_size new_cid_length; + u32 i; + + + /* Allocate new CID list with room for the new CID */ + + if (!new_cid) + new_cid_length = info->compatible_id_list.list_size; + else if (info->compatible_id_list.list_size) + new_cid_length = info->compatible_id_list.list_size + + new_cid->length + sizeof(struct acpica_device_id); + else + new_cid_length = sizeof(struct acpica_device_id_list) + new_cid->length; + + cid = ACPI_ALLOCATE_ZEROED(new_cid_length); + if (!cid) { + return NULL; + } + + cid->list_size = new_cid_length; + cid->count = info->compatible_id_list.count; + if (new_cid) + cid->count++; + next_id_string = (char *) cid->ids + (cid->count * sizeof(struct acpica_device_id)); + + /* Copy all existing CIDs */ + + for (i = 0; i < info->compatible_id_list.count; i++) { + cid_length = info->compatible_id_list.ids[i].length; + cid->ids[i].string = next_id_string; + cid->ids[i].length = cid_length; + + ACPI_MEMCPY(next_id_string, info->compatible_id_list.ids[i].string, + cid_length); + + next_id_string += cid_length; + } + + /* Append the new CID */ + + if (new_cid) { + cid->ids[i].string = next_id_string; + cid->ids[i].length = new_cid->length; + + ACPI_MEMCPY(next_id_string, new_cid->string, new_cid->length); + } + + return cid; +} + static void acpi_device_set_id(struct acpi_device *device, struct acpi_device *parent, acpi_handle handle, int type) { - struct acpi_device_info *info; - struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + struct acpi_device_info *info = NULL; char *hid = NULL; char *uid = NULL; - struct acpi_compatible_id_list *cid_list = NULL; - const char *cid_add = NULL; + struct acpica_device_id_list *cid_list = NULL; + char *cid_add = NULL; acpi_status status; switch (type) { case ACPI_BUS_TYPE_DEVICE: - status = acpi_get_object_info(handle, &buffer); + status = acpi_get_object_info(handle, &info); if (ACPI_FAILURE(status)) { printk(KERN_ERR PREFIX "%s: Error reading device info\n", __func__); return; } - info = buffer.pointer; if (info->valid & ACPI_VALID_HID) - hid = info->hardware_id.value; + hid = info->hardware_id.string; if (info->valid & ACPI_VALID_UID) - uid = info->unique_id.value; + uid = info->unique_id.string; if (info->valid & ACPI_VALID_CID) - cid_list = &info->compatibility_id; + cid_list = &info->compatible_id_list; if (info->valid & ACPI_VALID_ADR) { device->pnp.bus_address = info->address; device->flags.bus_address = 1; @@ -1076,55 +1132,44 @@ static void acpi_device_set_id(struct acpi_device *device, } if (hid) { - strcpy(device->pnp.hardware_id, hid); - device->flags.hardware_id = 1; - } + device->pnp.hardware_id = ACPI_ALLOCATE_ZEROED(strlen (hid) + 1); + if (device->pnp.hardware_id) { + strcpy(device->pnp.hardware_id, hid); + device->flags.hardware_id = 1; + } + } else + device->pnp.hardware_id = NULL; + if (uid) { - strcpy(device->pnp.unique_id, uid); - device->flags.unique_id = 1; - } + device->pnp.unique_id = ACPI_ALLOCATE_ZEROED(strlen (uid) + 1); + if (device->pnp.unique_id) { + strcpy(device->pnp.unique_id, uid); + device->flags.unique_id = 1; + } + } else + device->pnp.unique_id = NULL; + if (cid_list || cid_add) { - struct acpi_compatible_id_list *list; - int size = 0; - int count = 0; - - if (cid_list) { - size = cid_list->size; - } else if (cid_add) { - size = sizeof(struct acpi_compatible_id_list); - cid_list = ACPI_ALLOCATE_ZEROED((acpi_size) size); - if (!cid_list) { - printk(KERN_ERR "Memory allocation error\n"); - kfree(buffer.pointer); - return; - } else { - cid_list->count = 0; - cid_list->size = size; - } + struct acpica_device_id_list *list; + + if (cid_add) { + struct acpica_device_id cid; + cid.length = strlen (cid_add) + 1; + cid.string = cid_add; + + list = acpi_add_cid(info, &cid); + } else { + list = acpi_add_cid(info, NULL); } - if (cid_add) - size += sizeof(struct acpi_compatible_id); - list = kmalloc(size, GFP_KERNEL); if (list) { - if (cid_list) { - memcpy(list, cid_list, cid_list->size); - count = cid_list->count; - } - if (cid_add) { - strncpy(list->id[count].value, cid_add, - ACPI_MAX_CID_LENGTH); - count++; - device->flags.compatible_ids = 1; - } - list->size = size; - list->count = count; device->pnp.cid_list = list; - } else - printk(KERN_ERR PREFIX "Memory allocation error\n"); + if (cid_add) + device->flags.compatible_ids = 1; + } } - kfree(buffer.pointer); + kfree(info); } static int acpi_device_set_context(struct acpi_device *device, int type) diff --git a/drivers/char/agp/hp-agp.c b/drivers/char/agp/hp-agp.c index 8f3d4c1..7bead4c 100644 --- a/drivers/char/agp/hp-agp.c +++ b/drivers/char/agp/hp-agp.c @@ -478,7 +478,6 @@ zx1_gart_probe (acpi_handle obj, u32 depth, void *context, void **ret) { acpi_handle handle, parent; acpi_status status; - struct acpi_buffer buffer; struct acpi_device_info *info; u64 lba_hpa, sba_hpa, length; int match; @@ -490,13 +489,11 @@ zx1_gart_probe (acpi_handle obj, u32 depth, void *context, void **ret) /* Look for an enclosing IOC scope and find its CSR space */ handle = obj; do { - buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER; - status = acpi_get_object_info(handle, &buffer); + status = acpi_get_object_info(handle, &info); if (ACPI_SUCCESS(status)) { /* TBD check _CID also */ - info = buffer.pointer; - info->hardware_id.value[sizeof(info->hardware_id)-1] = '\0'; - match = (strcmp(info->hardware_id.value, "HWP0001") == 0); + info->hardware_id.string[sizeof(info->hardware_id.length)-1] = '\0'; + match = (strcmp(info->hardware_id.string, "HWP0001") == 0); kfree(info); if (match) { status = hp_acpi_csr_space(handle, &sba_hpa, &length); diff --git a/drivers/ide/ide-acpi.c b/drivers/ide/ide-acpi.c index c509c99..c0cf45a 100644 --- a/drivers/ide/ide-acpi.c +++ b/drivers/ide/ide-acpi.c @@ -114,8 +114,6 @@ static int ide_get_dev_handle(struct device *dev, acpi_handle *handle, unsigned int bus, devnum, func; acpi_integer addr; acpi_handle dev_handle; - struct acpi_buffer buffer = {.length = ACPI_ALLOCATE_BUFFER, - .pointer = NULL}; acpi_status status; struct acpi_device_info *dinfo = NULL; int ret = -ENODEV; @@ -134,12 +132,11 @@ static int ide_get_dev_handle(struct device *dev, acpi_handle *handle, goto err; } - status = acpi_get_object_info(dev_handle, &buffer); + status = acpi_get_object_info(dev_handle, &dinfo); if (ACPI_FAILURE(status)) { DEBPRINT("get_object_info for device failed\n"); goto err; } - dinfo = buffer.pointer; if (dinfo && (dinfo->valid & ACPI_VALID_ADR) && dinfo->address == addr) { *pcidevfn = addr; diff --git a/drivers/pci/hotplug/acpiphp_ibm.c b/drivers/pci/hotplug/acpiphp_ibm.c index 5befa7e..a9d926b 100644 --- a/drivers/pci/hotplug/acpiphp_ibm.c +++ b/drivers/pci/hotplug/acpiphp_ibm.c @@ -398,23 +398,21 @@ static acpi_status __init ibm_find_acpi_device(acpi_handle handle, acpi_handle *phandle = (acpi_handle *)context; acpi_status status; struct acpi_device_info *info; - struct acpi_buffer info_buffer = { ACPI_ALLOCATE_BUFFER, NULL }; int retval = 0; - status = acpi_get_object_info(handle, &info_buffer); + status = acpi_get_object_info(handle, &info); if (ACPI_FAILURE(status)) { err("%s: Failed to get device information status=0x%x\n", __func__, status); return retval; } - info = info_buffer.pointer; - info->hardware_id.value[sizeof(info->hardware_id.value) - 1] = '\0'; + info->hardware_id.string[sizeof(info->hardware_id.length) - 1] = '\0'; if (info->current_status && (info->valid & ACPI_VALID_HID) && - (!strcmp(info->hardware_id.value, IBM_HARDWARE_ID1) || - !strcmp(info->hardware_id.value, IBM_HARDWARE_ID2))) { + (!strcmp(info->hardware_id.string, IBM_HARDWARE_ID1) || + !strcmp(info->hardware_id.string, IBM_HARDWARE_ID2))) { dbg("found hardware: %s, handle: %p\n", - info->hardware_id.value, handle); + info->hardware_id.string, handle); *phandle = handle; /* returning non-zero causes the search to stop * and returns this value to the caller of diff --git a/drivers/platform/x86/sony-laptop.c b/drivers/platform/x86/sony-laptop.c index dafaa4a..f9f68e0 100644 --- a/drivers/platform/x86/sony-laptop.c +++ b/drivers/platform/x86/sony-laptop.c @@ -976,15 +976,12 @@ static acpi_status sony_walk_callback(acpi_handle handle, u32 level, void *context, void **return_value) { struct acpi_device_info *info; - struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; - - if (ACPI_SUCCESS(acpi_get_object_info(handle, &buffer))) { - info = buffer.pointer; + if (ACPI_SUCCESS(acpi_get_object_info(handle, &info))) { printk(KERN_WARNING DRV_PFX "method: name: %4.4s, args %X\n", (char *)&info->name, info->param_count); - kfree(buffer.pointer); + kfree(info); } return AE_OK; diff --git a/drivers/pnp/pnpacpi/core.c b/drivers/pnp/pnpacpi/core.c index 9496494f..c07fdb9 100644 --- a/drivers/pnp/pnpacpi/core.c +++ b/drivers/pnp/pnpacpi/core.c @@ -194,13 +194,13 @@ static int __init pnpacpi_add_device(struct acpi_device *device) pnpacpi_parse_resource_option_data(dev); if (device->flags.compatible_ids) { - struct acpi_compatible_id_list *cid_list = device->pnp.cid_list; + struct acpica_device_id_list *cid_list = device->pnp.cid_list; int i; for (i = 0; i < cid_list->count; i++) { - if (!ispnpidacpi(cid_list->id[i].value)) + if (!ispnpidacpi(cid_list->ids[i].string)) continue; - pnp_add_id(dev, cid_list->id[i].value); + pnp_add_id(dev, cid_list->ids[i].string); } } diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index c65e4ce..b91420b 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -173,17 +173,15 @@ struct acpi_device_dir { typedef char acpi_bus_id[8]; typedef unsigned long acpi_bus_address; -typedef char acpi_hardware_id[15]; -typedef char acpi_unique_id[9]; typedef char acpi_device_name[40]; typedef char acpi_device_class[20]; struct acpi_device_pnp { acpi_bus_id bus_id; /* Object name */ acpi_bus_address bus_address; /* _ADR */ - acpi_hardware_id hardware_id; /* _HID */ - struct acpi_compatible_id_list *cid_list; /* _CIDs */ - acpi_unique_id unique_id; /* _UID */ + char *hardware_id; /* _HID */ + struct acpica_device_id_list *cid_list; /* _CIDs */ + char *unique_id; /* _UID */ acpi_device_name device_name; /* Driver-determined */ acpi_device_class device_class; /* " */ }; diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index b450a19..04904c7 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -200,7 +200,8 @@ acpi_evaluate_object_typed(acpi_handle object, acpi_object_type return_type); acpi_status -acpi_get_object_info(acpi_handle handle, struct acpi_buffer *return_buffer); +acpi_get_object_info(acpi_handle handle, + struct acpi_device_info **return_buffer); acpi_status acpi_install_method(u8 *buffer); diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h index 37ba576..7a4ff79 100644 --- a/include/acpi/actypes.h +++ b/include/acpi/actypes.h @@ -338,7 +338,7 @@ typedef u32 acpi_physical_address; /* PM Timer ticks per second (HZ) */ -#define PM_TIMER_FREQUENCY 3579545 +#define PM_TIMER_FREQUENCY 3579545 /******************************************************************************* * @@ -969,38 +969,60 @@ acpi_status(*acpi_walk_callback) (acpi_handle obj_handle, #define ACPI_INTERRUPT_NOT_HANDLED 0x00 #define ACPI_INTERRUPT_HANDLED 0x01 -/* Length of _HID, _UID, _CID, and UUID values */ +/* Length of 32-bit EISAID values when converted back to a string */ + +#define ACPI_EISAID_STRING_SIZE 8 /* Includes null terminator */ + +/* Length of UUID (string) values */ -#define ACPI_DEVICE_ID_LENGTH 0x09 -#define ACPI_MAX_CID_LENGTH 48 #define ACPI_UUID_LENGTH 16 -/* Common string version of device HIDs and UIDs */ +/* Structures used for device/processor HID, UID, CID */ struct acpica_device_id { - char value[ACPI_DEVICE_ID_LENGTH]; + u32 length; /* Length of string + null */ + char *string; }; -/* Common string version of device CIDs */ - -struct acpi_compatible_id { - char value[ACPI_MAX_CID_LENGTH]; +struct acpica_device_id_list { + u32 count; /* Number of IDs in Ids array */ + u32 list_size; /* Size of list, including ID strings */ + struct acpica_device_id ids[1]; /* ID array */ }; -struct acpi_compatible_id_list { - u32 count; - u32 size; - struct acpi_compatible_id id[1]; +/* + * Structure returned from acpi_get_object_info. + * Optimized for both 32- and 64-bit builds + */ +struct acpi_device_info { + u32 info_size; /* Size of info, including ID strings */ + u32 name; /* ACPI object Name */ + acpi_object_type type; /* ACPI object Type */ + u8 param_count; /* If a method, required parameter count */ + u8 valid; /* Indicates which optional fields are valid */ + u8 flags; /* Miscellaneous info */ + u8 highest_dstates[4]; /* _sx_d values: 0xFF indicates not valid */ + u8 lowest_dstates[5]; /* _sx_w values: 0xFF indicates not valid */ + u32 current_status; /* _STA value */ + acpi_integer address; /* _ADR value */ + struct acpica_device_id hardware_id; /* _HID value */ + struct acpica_device_id unique_id; /* _UID value */ + struct acpica_device_id_list compatible_id_list; /* _CID list */ }; -/* Structure and flags for acpi_get_object_info */ +/* Values for Flags field above (acpi_get_object_info) */ + +#define ACPI_PCI_ROOT_BRIDGE 0x01 -#define ACPI_VALID_STA 0x0001 -#define ACPI_VALID_ADR 0x0002 -#define ACPI_VALID_HID 0x0004 -#define ACPI_VALID_UID 0x0008 -#define ACPI_VALID_CID 0x0010 -#define ACPI_VALID_SXDS 0x0020 +/* Flags for Valid field above (acpi_get_object_info) */ + +#define ACPI_VALID_STA 0x01 +#define ACPI_VALID_ADR 0x02 +#define ACPI_VALID_HID 0x04 +#define ACPI_VALID_UID 0x08 +#define ACPI_VALID_CID 0x10 +#define ACPI_VALID_SXDS 0x20 +#define ACPI_VALID_SXWS 0x40 /* Flags for _STA method */ @@ -1011,29 +1033,6 @@ struct acpi_compatible_id_list { #define ACPI_STA_DEVICE_OK 0x08 /* Synonym */ #define ACPI_STA_BATTERY_PRESENT 0x10 -#define ACPI_COMMON_OBJ_INFO \ - acpi_object_type type; /* ACPI object type */ \ - acpi_name name /* ACPI object Name */ - -struct acpi_obj_info_header { - ACPI_COMMON_OBJ_INFO; -}; - -/* Structure returned from Get Object Info */ - -struct acpi_device_info { - ACPI_COMMON_OBJ_INFO; - - u32 param_count; /* If a method, required parameter count */ - u32 valid; /* Indicates which fields below are valid */ - u32 current_status; /* _STA value */ - acpi_integer address; /* _ADR value if any */ - struct acpica_device_id hardware_id; /* _HID value if any */ - struct acpica_device_id unique_id; /* _UID value if any */ - u8 highest_dstates[4]; /* _sx_d values: 0xFF indicates not valid */ - struct acpi_compatible_id_list compatibility_id; /* List of _CIDs if any */ -}; - /* Context structs for address space handlers */ struct acpi_pci_id { -- cgit v0.10.2 From dbdc8f02fe8339686623c84745ba15b0f4f889a1 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Wed, 24 Jun 2009 11:22:22 +0800 Subject: ACPICA: Fix possible memory leak in nspredef Fixed a possible leak when an attempt is made to repair a return object. The only current repair is an automatic buffer to string conversion. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/nspredef.c b/drivers/acpi/acpica/nspredef.c index 7f8e066..abbb855 100644 --- a/drivers/acpi/acpica/nspredef.c +++ b/drivers/acpi/acpica/nspredef.c @@ -1046,22 +1046,25 @@ acpi_ns_repair_object(u32 expected_btypes, ACPI_MEMCPY(new_object->string.pointer, return_object->buffer.pointer, length); - /* Install the new return object */ - - acpi_ut_remove_reference(return_object); - *return_object_ptr = new_object; - /* - * If the object is a package element, we need to: - * 1. Decrement the reference count of the orignal object, it was - * incremented when building the package - * 2. Increment the reference count of the new object, it will be - * decremented when releasing the package + * If the original object is a package element, we need to: + * 1. Set the reference count of the new object to match the + * reference count of the old object. + * 2. Decrement the reference count of the original object. */ if (package_index != ACPI_NOT_PACKAGE) { - acpi_ut_remove_reference(return_object); - acpi_ut_add_reference(new_object); + new_object->common.reference_count = + return_object->common.reference_count; + + if (return_object->common.reference_count > 1) { + return_object->common.reference_count--; + } } + + /* Delete old object, install the new return object */ + + acpi_ut_remove_reference(return_object); + *return_object_ptr = new_object; return (AE_OK); default: -- cgit v0.10.2 From 3db20bed579bc4e7fe581c48ad1bde853aa9ff68 Mon Sep 17 00:00:00 2001 From: Lin Ming Date: Wed, 24 Jun 2009 11:25:17 +0800 Subject: ACPICA: ACPI 4.0: iASL/Disassembler - IPMI keyword support. Adds support for the new IPMI operation region keyword. ACPICA BZ 771, 772. http://acpica.org/bugzilla/show_bug.cgi?id=771 http://acpica.org/bugzilla/show_bug.cgi?id=772 Signed-off-by: Lin Ming Signed-off-by: Bob Moore Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/acconfig.h b/drivers/acpi/acpica/acconfig.h index 6c1fb2d..9123d5a 100644 --- a/drivers/acpi/acpica/acconfig.h +++ b/drivers/acpi/acpica/acconfig.h @@ -183,7 +183,7 @@ /* Operation regions */ -#define ACPI_NUM_PREDEFINED_REGIONS 8 +#define ACPI_NUM_PREDEFINED_REGIONS 9 #define ACPI_USER_REGION_BEGIN 0x80 /* Maximum space_ids for Operation Regions */ diff --git a/drivers/acpi/acpica/amlcode.h b/drivers/acpi/acpica/amlcode.h index 067f967..4940249 100644 --- a/drivers/acpi/acpica/amlcode.h +++ b/drivers/acpi/acpica/amlcode.h @@ -404,6 +404,7 @@ typedef enum { REGION_SMBUS, REGION_CMOS, REGION_PCI_BAR, + REGION_IPMI, REGION_DATA_TABLE, /* Internal use only */ REGION_FIXED_HW = 0x7F } AML_REGION_TYPES; diff --git a/drivers/acpi/acpica/utglobal.c b/drivers/acpi/acpica/utglobal.c index ed7a33c..9e33b62 100644 --- a/drivers/acpi/acpica/utglobal.c +++ b/drivers/acpi/acpica/utglobal.c @@ -359,6 +359,7 @@ const char *acpi_gbl_region_types[ACPI_NUM_PREDEFINED_REGIONS] = { "SMBus", "SystemCMOS", "PCIBARTarget", + "IPMI", "DataTable" }; -- cgit v0.10.2 From 6557a49a443a347d24aed58076365432ded30edc Mon Sep 17 00:00:00 2001 From: Lin Ming Date: Wed, 24 Jun 2009 11:32:04 +0800 Subject: ACPICA: ACPI 4.0: Interpreter support for IPMI. Adds support for IPMI which is similar to SMBus and uses a bi-directional data buffer. ACPICA BZ 773. http://acpica.org/bugzilla/show_bug.cgi?id=773 Signed-off-by: Lin Ming Signed-off-by: Bob Moore Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/acconfig.h b/drivers/acpi/acpica/acconfig.h index 9123d5a..8e679ef 100644 --- a/drivers/acpi/acpica/acconfig.h +++ b/drivers/acpi/acpica/acconfig.h @@ -199,9 +199,10 @@ #define ACPI_RSDP_CHECKSUM_LENGTH 20 #define ACPI_RSDP_XCHECKSUM_LENGTH 36 -/* SMBus bidirectional buffer size */ +/* SMBus and IPMI bidirectional buffer size */ #define ACPI_SMBUS_BUFFER_SIZE 34 +#define ACPI_IPMI_BUFFER_SIZE 66 /* _sx_d and _sx_w control methods */ diff --git a/drivers/acpi/acpica/exfield.c b/drivers/acpi/acpica/exfield.c index 546dcdd..0b33d6c 100644 --- a/drivers/acpi/acpica/exfield.c +++ b/drivers/acpi/acpica/exfield.c @@ -72,6 +72,7 @@ acpi_ex_read_data_from_field(struct acpi_walk_state *walk_state, union acpi_operand_object *buffer_desc; acpi_size length; void *buffer; + u32 function; ACPI_FUNCTION_TRACE_PTR(ex_read_data_from_field, obj_desc); @@ -97,13 +98,27 @@ acpi_ex_read_data_from_field(struct acpi_walk_state *walk_state, } } else if ((obj_desc->common.type == ACPI_TYPE_LOCAL_REGION_FIELD) && (obj_desc->field.region_obj->region.space_id == - ACPI_ADR_SPACE_SMBUS)) { + ACPI_ADR_SPACE_SMBUS + || obj_desc->field.region_obj->region.space_id == + ACPI_ADR_SPACE_IPMI)) { /* - * This is an SMBus read. We must create a buffer to hold the data - * and directly access the region handler. + * This is an SMBus or IPMI read. We must create a buffer to hold + * the data and then directly access the region handler. + * + * Note: Smbus protocol value is passed in upper 16-bits of Function */ - buffer_desc = - acpi_ut_create_buffer_object(ACPI_SMBUS_BUFFER_SIZE); + if (obj_desc->field.region_obj->region.space_id == + ACPI_ADR_SPACE_SMBUS) { + length = ACPI_SMBUS_BUFFER_SIZE; + function = + ACPI_READ | (obj_desc->field.attribute << 16); + } else { /* IPMI */ + + length = ACPI_IPMI_BUFFER_SIZE; + function = ACPI_READ; + } + + buffer_desc = acpi_ut_create_buffer_object(length); if (!buffer_desc) { return_ACPI_STATUS(AE_NO_MEMORY); } @@ -112,16 +127,13 @@ acpi_ex_read_data_from_field(struct acpi_walk_state *walk_state, acpi_ex_acquire_global_lock(obj_desc->common_field.field_flags); - /* - * Perform the read. - * Note: Smbus protocol value is passed in upper 16-bits of Function - */ + /* Call the region handler for the read */ + status = acpi_ex_access_region(obj_desc, 0, ACPI_CAST_PTR(acpi_integer, buffer_desc-> buffer.pointer), - ACPI_READ | (obj_desc->field. - attribute << 16)); + function); acpi_ex_release_global_lock(obj_desc->common_field.field_flags); goto exit; } @@ -212,6 +224,7 @@ acpi_ex_write_data_to_field(union acpi_operand_object *source_desc, u32 length; void *buffer; union acpi_operand_object *buffer_desc; + u32 function; ACPI_FUNCTION_TRACE_PTR(ex_write_data_to_field, obj_desc); @@ -234,39 +247,56 @@ acpi_ex_write_data_to_field(union acpi_operand_object *source_desc, } } else if ((obj_desc->common.type == ACPI_TYPE_LOCAL_REGION_FIELD) && (obj_desc->field.region_obj->region.space_id == - ACPI_ADR_SPACE_SMBUS)) { + ACPI_ADR_SPACE_SMBUS + || obj_desc->field.region_obj->region.space_id == + ACPI_ADR_SPACE_IPMI)) { /* - * This is an SMBus write. We will bypass the entire field mechanism - * and handoff the buffer directly to the handler. + * This is an SMBus or IPMI write. We will bypass the entire field + * mechanism and handoff the buffer directly to the handler. For + * these address spaces, the buffer is bi-directional; on a write, + * return data is returned in the same buffer. + * + * Source must be a buffer of sufficient size: + * ACPI_SMBUS_BUFFER_SIZE or ACPI_IPMI_BUFFER_SIZE. * - * Source must be a buffer of sufficient size (ACPI_SMBUS_BUFFER_SIZE). + * Note: SMBus protocol type is passed in upper 16-bits of Function */ if (source_desc->common.type != ACPI_TYPE_BUFFER) { ACPI_ERROR((AE_INFO, - "SMBus write requires Buffer, found type %s", + "SMBus or IPMI write requires Buffer, found type %s", acpi_ut_get_object_type_name(source_desc))); return_ACPI_STATUS(AE_AML_OPERAND_TYPE); } - if (source_desc->buffer.length < ACPI_SMBUS_BUFFER_SIZE) { + if (obj_desc->field.region_obj->region.space_id == + ACPI_ADR_SPACE_SMBUS) { + length = ACPI_SMBUS_BUFFER_SIZE; + function = + ACPI_WRITE | (obj_desc->field.attribute << 16); + } else { /* IPMI */ + + length = ACPI_IPMI_BUFFER_SIZE; + function = ACPI_WRITE; + } + + if (source_desc->buffer.length < length) { ACPI_ERROR((AE_INFO, - "SMBus write requires Buffer of length %X, found length %X", - ACPI_SMBUS_BUFFER_SIZE, - source_desc->buffer.length)); + "SMBus or IPMI write requires Buffer of length %X, found length %X", + length, source_desc->buffer.length)); return_ACPI_STATUS(AE_AML_BUFFER_LIMIT); } - buffer_desc = - acpi_ut_create_buffer_object(ACPI_SMBUS_BUFFER_SIZE); + /* Create the bi-directional buffer */ + + buffer_desc = acpi_ut_create_buffer_object(length); if (!buffer_desc) { return_ACPI_STATUS(AE_NO_MEMORY); } buffer = buffer_desc->buffer.pointer; - ACPI_MEMCPY(buffer, source_desc->buffer.pointer, - ACPI_SMBUS_BUFFER_SIZE); + ACPI_MEMCPY(buffer, source_desc->buffer.pointer, length); /* Lock entire transaction if requested */ @@ -275,12 +305,10 @@ acpi_ex_write_data_to_field(union acpi_operand_object *source_desc, /* * Perform the write (returns status and perhaps data in the * same buffer) - * Note: SMBus protocol type is passed in upper 16-bits of Function. */ status = acpi_ex_access_region(obj_desc, 0, (acpi_integer *) buffer, - ACPI_WRITE | (obj_desc->field. - attribute << 16)); + function); acpi_ex_release_global_lock(obj_desc->common_field.field_flags); *result_desc = buffer_desc; diff --git a/drivers/acpi/acpica/exfldio.c b/drivers/acpi/acpica/exfldio.c index 6687be1..d7b3b41 100644 --- a/drivers/acpi/acpica/exfldio.c +++ b/drivers/acpi/acpica/exfldio.c @@ -120,12 +120,13 @@ acpi_ex_setup_region(union acpi_operand_object *obj_desc, } /* - * Exit now for SMBus address space, it has a non-linear address space + * Exit now for SMBus or IPMI address space, it has a non-linear address space * and the request cannot be directly validated */ - if (rgn_desc->region.space_id == ACPI_ADR_SPACE_SMBUS) { + if (rgn_desc->region.space_id == ACPI_ADR_SPACE_SMBUS || + rgn_desc->region.space_id == ACPI_ADR_SPACE_IPMI) { - /* SMBus has a non-linear address space */ + /* SMBus or IPMI has a non-linear address space */ return_ACPI_STATUS(AE_OK); } diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h index 7a4ff79..4371805 100644 --- a/include/acpi/actypes.h +++ b/include/acpi/actypes.h @@ -732,7 +732,8 @@ typedef u8 acpi_adr_space_type; #define ACPI_ADR_SPACE_SMBUS (acpi_adr_space_type) 4 #define ACPI_ADR_SPACE_CMOS (acpi_adr_space_type) 5 #define ACPI_ADR_SPACE_PCI_BAR_TARGET (acpi_adr_space_type) 6 -#define ACPI_ADR_SPACE_DATA_TABLE (acpi_adr_space_type) 7 +#define ACPI_ADR_SPACE_IPMI (acpi_adr_space_type) 7 +#define ACPI_ADR_SPACE_DATA_TABLE (acpi_adr_space_type) 8 #define ACPI_ADR_SPACE_FIXED_HARDWARE (acpi_adr_space_type) 127 /* -- cgit v0.10.2 From 8e4319c425077c4cc540696a5bb6c4d12f017dcd Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Mon, 29 Jun 2009 13:43:27 +0800 Subject: ACPICA: Fix several acpi_attach_data problems Handler was never invoked. Now invoked if/when host node is deleted. Data object was not automatically deleted when host node was deleted. Interface to handler had an unused parameter, removed it. ACPICA BZ 778. http://acpica.org/bugzilla/show_bug.cgi?id=778 Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/acnamesp.h b/drivers/acpi/acpica/acnamesp.h index 94cdc2b..a78e02f 100644 --- a/drivers/acpi/acpica/acnamesp.h +++ b/drivers/acpi/acpica/acnamesp.h @@ -144,6 +144,8 @@ struct acpi_namespace_node *acpi_ns_create_node(u32 name); void acpi_ns_delete_node(struct acpi_namespace_node *node); +void acpi_ns_remove_node(struct acpi_namespace_node *node); + void acpi_ns_delete_namespace_subtree(struct acpi_namespace_node *parent_handle); diff --git a/drivers/acpi/acpica/nsalloc.c b/drivers/acpi/acpica/nsalloc.c index efc971a..8a58a1b 100644 --- a/drivers/acpi/acpica/nsalloc.c +++ b/drivers/acpi/acpica/nsalloc.c @@ -96,17 +96,68 @@ struct acpi_namespace_node *acpi_ns_create_node(u32 name) * * RETURN: None * - * DESCRIPTION: Delete a namespace node + * DESCRIPTION: Delete a namespace node. All node deletions must come through + * here. Detaches any attached objects, including any attached + * data. If a handler is associated with attached data, it is + * invoked before the node is deleted. * ******************************************************************************/ void acpi_ns_delete_node(struct acpi_namespace_node *node) { + union acpi_operand_object *obj_desc; + + ACPI_FUNCTION_NAME(ns_delete_node); + + /* Detach an object if there is one */ + + acpi_ns_detach_object(node); + + /* + * Delete an attached data object if present (an object that was created + * and attached via acpi_attach_data). Note: After any normal object is + * detached above, the only possible remaining object is a data object. + */ + obj_desc = node->object; + if (obj_desc && (obj_desc->common.type == ACPI_TYPE_LOCAL_DATA)) { + + /* Invoke the attached data deletion handler if present */ + + if (obj_desc->data.handler) { + obj_desc->data.handler(node, obj_desc->data.pointer); + } + + acpi_ut_remove_reference(obj_desc); + } + + /* Now we can delete the node */ + + (void)acpi_os_release_object(acpi_gbl_namespace_cache, node); + + ACPI_MEM_TRACKING(acpi_gbl_ns_node_list->total_freed++); + ACPI_DEBUG_PRINT((ACPI_DB_ALLOCATIONS, "Node %p, Remaining %X\n", + node, acpi_gbl_current_node_count)); +} + +/******************************************************************************* + * + * FUNCTION: acpi_ns_remove_node + * + * PARAMETERS: Node - Node to be removed/deleted + * + * RETURN: None + * + * DESCRIPTION: Remove (unlink) and delete a namespace node + * + ******************************************************************************/ + +void acpi_ns_remove_node(struct acpi_namespace_node *node) +{ struct acpi_namespace_node *parent_node; struct acpi_namespace_node *prev_node; struct acpi_namespace_node *next_node; - ACPI_FUNCTION_TRACE_PTR(ns_delete_node, node); + ACPI_FUNCTION_TRACE_PTR(ns_remove_node, node); parent_node = acpi_ns_get_parent_node(node); @@ -142,12 +193,9 @@ void acpi_ns_delete_node(struct acpi_namespace_node *node) } } - ACPI_MEM_TRACKING(acpi_gbl_ns_node_list->total_freed++); - - /* Detach an object if there is one, then delete the node */ + /* Delete the node and any attached objects */ - acpi_ns_detach_object(node); - (void)acpi_os_release_object(acpi_gbl_namespace_cache, node); + acpi_ns_delete_node(node); return_VOID; } @@ -273,25 +321,11 @@ void acpi_ns_delete_children(struct acpi_namespace_node *parent_node) parent_node, child_node)); } - /* Now we can free this child object */ - - ACPI_MEM_TRACKING(acpi_gbl_ns_node_list->total_freed++); - - ACPI_DEBUG_PRINT((ACPI_DB_ALLOCATIONS, - "Object %p, Remaining %X\n", child_node, - acpi_gbl_current_node_count)); - - /* Detach an object if there is one, then free the child node */ - - acpi_ns_detach_object(child_node); - - /* Now we can delete the node */ - - (void)acpi_os_release_object(acpi_gbl_namespace_cache, - child_node); - - /* And move on to the next child in the list */ - + /* + * Delete this child node and move on to the next child in the list. + * No need to unlink the node since we are deleting the entire branch. + */ + acpi_ns_delete_node(child_node); child_node = next_node; } while (!(flags & ANOBJ_END_OF_PEER_LIST)); @@ -433,7 +467,7 @@ void acpi_ns_delete_namespace_by_owner(acpi_owner_id owner_id) if (deletion_node) { acpi_ns_delete_children(deletion_node); - acpi_ns_delete_node(deletion_node); + acpi_ns_remove_node(deletion_node); deletion_node = NULL; } diff --git a/drivers/acpi/acpica/nsload.c b/drivers/acpi/acpica/nsload.c index dcd7a6a..a7234e6 100644 --- a/drivers/acpi/acpica/nsload.c +++ b/drivers/acpi/acpica/nsload.c @@ -270,8 +270,7 @@ static acpi_status acpi_ns_delete_subtree(acpi_handle start_handle) /* Now delete the starting object, and we are done */ - acpi_ns_delete_node(child_handle); - + acpi_ns_remove_node(child_handle); return_ACPI_STATUS(AE_OK); } diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 2876fc7..620183f 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -141,7 +141,7 @@ int acpi_bus_get_status(struct acpi_device *device) EXPORT_SYMBOL(acpi_bus_get_status); void acpi_bus_private_data_handler(acpi_handle handle, - u32 function, void *context) + void *context) { return; } diff --git a/drivers/acpi/glue.c b/drivers/acpi/glue.c index 27a7072..9a4ce33 100644 --- a/drivers/acpi/glue.c +++ b/drivers/acpi/glue.c @@ -119,7 +119,7 @@ EXPORT_SYMBOL(acpi_get_child); /* Link ACPI devices with physical devices */ static void acpi_glue_data_handler(acpi_handle handle, - u32 function, void *context) + void *context) { /* we provide an empty handler */ } diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 0ab526d..9606af1 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -687,7 +687,7 @@ acpi_bus_get_ejd(acpi_handle handle, acpi_handle *ejd) } EXPORT_SYMBOL_GPL(acpi_bus_get_ejd); -void acpi_bus_data_handler(acpi_handle handle, u32 function, void *context) +void acpi_bus_data_handler(acpi_handle handle, void *context) { /* TBD */ diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index b91420b..6e83a68 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -312,7 +312,7 @@ struct acpi_bus_event { extern struct kobject *acpi_kobj; extern int acpi_bus_generate_netlink_event(const char*, const char*, u8, int); -void acpi_bus_private_data_handler(acpi_handle, u32, void *); +void acpi_bus_private_data_handler(acpi_handle, void *); int acpi_bus_get_private_data(acpi_handle, void **); extern int acpi_notifier_call_chain(struct acpi_device *, u32, u32); extern int register_acpi_notifier(struct notifier_block *); @@ -325,7 +325,7 @@ extern void unregister_acpi_bus_notifier(struct notifier_block *nb); */ int acpi_bus_get_device(acpi_handle handle, struct acpi_device **device); -void acpi_bus_data_handler(acpi_handle handle, u32 function, void *context); +void acpi_bus_data_handler(acpi_handle handle, void *context); int acpi_bus_get_status(struct acpi_device *device); int acpi_bus_get_power(acpi_handle handle, int *state); int acpi_bus_set_power(acpi_handle handle, int state); diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h index 4371805..ef46011 100644 --- a/include/acpi/actypes.h +++ b/include/acpi/actypes.h @@ -922,7 +922,7 @@ typedef void (*acpi_notify_handler) (acpi_handle device, u32 value, void *context); typedef -void (*acpi_object_handler) (acpi_handle object, u32 function, void *data); +void (*acpi_object_handler) (acpi_handle object, void *data); typedef acpi_status(*acpi_init_handler) (acpi_handle object, u32 function); -- cgit v0.10.2 From cf02cd47d4747abf8ff0617e15fc05a00202e6d5 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Wed, 24 Jun 2009 11:38:46 +0800 Subject: ACPICA: Dump table header - suppress output of non-printable characters Function acpi_tb_print_table_header. Some ACPI tables contain non-printable characters in one of the string fields of the the header - Signature, OemId, OemTableId, or CompilerId. Invalid characters are replaced by '?'. ACPICA BZ 788. http://acpica.org/bugzilla/show_bug.cgi?id=788 Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/tbutils.c b/drivers/acpi/acpica/tbutils.c index ef7d2c2..1f15497 100644 --- a/drivers/acpi/acpica/tbutils.c +++ b/drivers/acpi/acpica/tbutils.c @@ -49,6 +49,12 @@ ACPI_MODULE_NAME("tbutils") /* Local prototypes */ +static void acpi_tb_fix_string(char *string, acpi_size length); + +static void +acpi_tb_cleanup_table_header(struct acpi_table_header *out_header, + struct acpi_table_header *header); + static acpi_physical_address acpi_tb_get_root_table_entry(u8 *table_entry, u32 table_entry_size); @@ -161,6 +167,59 @@ u8 acpi_tb_tables_loaded(void) /******************************************************************************* * + * FUNCTION: acpi_tb_fix_string + * + * PARAMETERS: String - String to be repaired + * Length - Maximum length + * + * RETURN: None + * + * DESCRIPTION: Replace every non-printable or non-ascii byte in the string + * with a question mark '?'. + * + ******************************************************************************/ + +static void acpi_tb_fix_string(char *string, acpi_size length) +{ + + while (length && *string) { + if (!ACPI_IS_PRINT(*string)) { + *string = '?'; + } + string++; + length--; + } +} + +/******************************************************************************* + * + * FUNCTION: acpi_tb_cleanup_table_header + * + * PARAMETERS: out_header - Where the cleaned header is returned + * Header - Input ACPI table header + * + * RETURN: Returns the cleaned header in out_header + * + * DESCRIPTION: Copy the table header and ensure that all "string" fields in + * the header consist of printable characters. + * + ******************************************************************************/ + +static void +acpi_tb_cleanup_table_header(struct acpi_table_header *out_header, + struct acpi_table_header *header) +{ + + ACPI_MEMCPY(out_header, header, sizeof(struct acpi_table_header)); + + acpi_tb_fix_string(out_header->signature, ACPI_NAME_SIZE); + acpi_tb_fix_string(out_header->oem_id, ACPI_OEM_ID_SIZE); + acpi_tb_fix_string(out_header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE); + acpi_tb_fix_string(out_header->asl_compiler_id, ACPI_NAME_SIZE); +} + +/******************************************************************************* + * * FUNCTION: acpi_tb_print_table_header * * PARAMETERS: Address - Table physical address @@ -176,6 +235,7 @@ void acpi_tb_print_table_header(acpi_physical_address address, struct acpi_table_header *header) { + struct acpi_table_header local_header; /* * The reason that the Address is cast to a void pointer is so that we @@ -192,6 +252,11 @@ acpi_tb_print_table_header(acpi_physical_address address, /* RSDP has no common fields */ + ACPI_MEMCPY(local_header.oem_id, + ACPI_CAST_PTR(struct acpi_table_rsdp, + header)->oem_id, ACPI_OEM_ID_SIZE); + acpi_tb_fix_string(local_header.oem_id, ACPI_OEM_ID_SIZE); + ACPI_INFO((AE_INFO, "RSDP %p %05X (v%.2d %6.6s)", ACPI_CAST_PTR (void, address), (ACPI_CAST_PTR(struct acpi_table_rsdp, header)-> @@ -200,18 +265,21 @@ acpi_tb_print_table_header(acpi_physical_address address, header)->length : 20, ACPI_CAST_PTR(struct acpi_table_rsdp, header)->revision, - ACPI_CAST_PTR(struct acpi_table_rsdp, - header)->oem_id)); + local_header.oem_id)); } else { /* Standard ACPI table with full common header */ + acpi_tb_cleanup_table_header(&local_header, header); + ACPI_INFO((AE_INFO, "%4.4s %p %05X (v%.2d %6.6s %8.8s %08X %4.4s %08X)", - header->signature, ACPI_CAST_PTR (void, address), - header->length, header->revision, header->oem_id, - header->oem_table_id, header->oem_revision, - header->asl_compiler_id, - header->asl_compiler_revision)); + local_header.signature, ACPI_CAST_PTR(void, address), + local_header.length, local_header.revision, + local_header.oem_id, local_header.oem_table_id, + local_header.oem_revision, + local_header.asl_compiler_id, + local_header.asl_compiler_revision)); + } } -- cgit v0.10.2 From 0444e8f6d72d6e38f92d48884bc90bbc6c22fd5a Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Wed, 24 Jun 2009 13:38:02 +0800 Subject: ACPICA: Fix: Predefined object repair executed only once This fixes a problem where the code that attempts to repair/convert an object of incorrect type is only executed on the first time the predefined method is called. The mechanism that disables warnings on subsequent calls was interfering with the repair mechanism. ACPICA BZ 781. http://acpica.org/bugzilla/show_bug.cgi?id=781 Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/aclocal.h b/drivers/acpi/acpica/aclocal.h index ee986ed..ff6689e 100644 --- a/drivers/acpi/acpica/aclocal.h +++ b/drivers/acpi/acpica/aclocal.h @@ -369,6 +369,19 @@ union acpi_predefined_info { struct acpi_package_info3 ret_info3; }; +/* Data block used during object validation */ + +struct acpi_predefined_data { + char *pathname; + const union acpi_predefined_info *predefined; + u32 flags; + u8 node_flags; +}; + +/* Defines for Flags field above */ + +#define ACPI_OBJECT_REPAIRED 1 + /* * Bitmapped return value types * Note: the actual data types must be contiguous, a loop in nspredef.c diff --git a/drivers/acpi/acpica/acmacros.h b/drivers/acpi/acpica/acmacros.h index 91ac7d7..3acd9c6 100644 --- a/drivers/acpi/acpica/acmacros.h +++ b/drivers/acpi/acpica/acmacros.h @@ -340,6 +340,7 @@ */ #define ACPI_ERROR_NAMESPACE(s, e) acpi_ns_report_error (AE_INFO, s, e); #define ACPI_ERROR_METHOD(s, n, p, e) acpi_ns_report_method_error (AE_INFO, s, n, p, e); +#define ACPI_WARN_PREDEFINED(plist) acpi_ut_predefined_warning plist #else @@ -347,6 +348,7 @@ #define ACPI_ERROR_NAMESPACE(s, e) #define ACPI_ERROR_METHOD(s, n, p, e) +#define ACPI_WARN_PREDEFINED(plist) #endif /* ACPI_NO_ERROR_MESSAGES */ /* diff --git a/drivers/acpi/acpica/acutils.h b/drivers/acpi/acpica/acutils.h index b0add85..863a264 100644 --- a/drivers/acpi/acpica/acutils.h +++ b/drivers/acpi/acpica/acutils.h @@ -475,6 +475,12 @@ u8 acpi_ut_valid_acpi_char(char character, u32 position); acpi_status acpi_ut_strtoul64(char *string, u32 base, acpi_integer * ret_integer); +void ACPI_INTERNAL_VAR_XFACE +acpi_ut_predefined_warning(const char *module_name, + u32 line_number, + char *pathname, + u8 node_flags, const char *format, ...); + /* Values for Base above (16=Hex, 10=Decimal) */ #define ACPI_ANY_BASE 0 diff --git a/drivers/acpi/acpica/nspredef.c b/drivers/acpi/acpica/nspredef.c index abbb855..1dc1a47 100644 --- a/drivers/acpi/acpica/nspredef.c +++ b/drivers/acpi/acpica/nspredef.c @@ -72,31 +72,33 @@ ACPI_MODULE_NAME("nspredef") ******************************************************************************/ /* Local prototypes */ static acpi_status -acpi_ns_check_package(char *pathname, - union acpi_operand_object **return_object_ptr, - const union acpi_predefined_info *predefined); +acpi_ns_check_package(struct acpi_predefined_data *data, + union acpi_operand_object **return_object_ptr); static acpi_status -acpi_ns_check_package_elements(char *pathname, +acpi_ns_check_package_elements(struct acpi_predefined_data *data, union acpi_operand_object **elements, u8 type1, u32 count1, u8 type2, u32 count2, u32 start_index); static acpi_status -acpi_ns_check_object_type(char *pathname, +acpi_ns_check_object_type(struct acpi_predefined_data *data, union acpi_operand_object **return_object_ptr, u32 expected_btypes, u32 package_index); static acpi_status -acpi_ns_check_reference(char *pathname, +acpi_ns_check_reference(struct acpi_predefined_data *data, union acpi_operand_object *return_object); static acpi_status -acpi_ns_repair_object(u32 expected_btypes, +acpi_ns_repair_object(struct acpi_predefined_data *data, + u32 expected_btypes, u32 package_index, union acpi_operand_object **return_object_ptr); +static void acpi_ns_get_expected_types(char *buffer, u32 expected_btypes); + /* * Names for the types that can be returned by the predefined objects. * Used for warning messages. Must be in the same order as the ACPI_RTYPEs @@ -109,13 +111,21 @@ static const char *acpi_rtype_names[] = { "/Reference", }; -#define ACPI_NOT_PACKAGE ACPI_UINT32_MAX +/* Object is not a package element */ + +#define ACPI_NOT_PACKAGE_ELEMENT ACPI_UINT32_MAX + +/* Always emit warning message, not dependent on node flags */ + +#define ACPI_WARN_ALWAYS 0 /******************************************************************************* * * FUNCTION: acpi_ns_check_predefined_names * * PARAMETERS: Node - Namespace node for the method/object + * user_param_count - Number of parameters actually passed + * return_status - Status from the object evaluation * return_object_ptr - Pointer to the object returned from the * evaluation of a method or object * @@ -135,12 +145,13 @@ acpi_ns_check_predefined_names(struct acpi_namespace_node *node, acpi_status status = AE_OK; const union acpi_predefined_info *predefined; char *pathname; + struct acpi_predefined_data *data; /* Match the name for this method/object against the predefined list */ predefined = acpi_ns_check_for_predefined_name(node); - /* Get the full pathname to the object, for use in error messages */ + /* Get the full pathname to the object, for use in warning messages */ pathname = acpi_ns_get_external_pathname(node); if (!pathname) { @@ -158,28 +169,17 @@ acpi_ns_check_predefined_names(struct acpi_namespace_node *node, /* If not a predefined name, we cannot validate the return object */ if (!predefined) { - goto exit; - } - - /* If the method failed, we cannot validate the return object */ - - if ((return_status != AE_OK) && (return_status != AE_CTRL_RETURN_VALUE)) { - goto exit; + goto cleanup; } /* - * Only validate the return value on the first successful evaluation of - * the method. This ensures that any warnings will only be emitted during - * the very first evaluation of the method/object. + * If the method failed or did not actually return an object, we cannot + * validate the return object */ - if (node->flags & ANOBJ_EVALUATED) { - goto exit; + if ((return_status != AE_OK) && (return_status != AE_CTRL_RETURN_VALUE)) { + goto cleanup; } - /* Mark the node as having been successfully evaluated */ - - node->flags |= ANOBJ_EVALUATED; - /* * If there is no return value, check if we require a return value for * this predefined name. Either one return value is expected, or none, @@ -190,46 +190,63 @@ acpi_ns_check_predefined_names(struct acpi_namespace_node *node, if (!return_object) { if ((predefined->info.expected_btypes) && (!(predefined->info.expected_btypes & ACPI_RTYPE_NONE))) { - ACPI_ERROR((AE_INFO, - "%s: Missing expected return value", - pathname)); + ACPI_WARN_PREDEFINED((AE_INFO, pathname, + ACPI_WARN_ALWAYS, + "Missing expected return value")); status = AE_AML_NO_RETURN_VALUE; } - goto exit; + goto cleanup; } /* * We have a return value, but if one wasn't expected, just exit, this is - * not a problem - * - * For example, if the "Implicit Return" feature is enabled, methods will - * always return a value + * not a problem. For example, if the "Implicit Return" feature is + * enabled, methods will always return a value. */ if (!predefined->info.expected_btypes) { - goto exit; + goto cleanup; + } + + /* Create the parameter data block for object validation */ + + data = ACPI_ALLOCATE_ZEROED(sizeof(struct acpi_predefined_data)); + if (!data) { + goto cleanup; } + data->predefined = predefined; + data->node_flags = node->flags; + data->pathname = pathname; /* * Check that the type of the return object is what is expected for * this predefined name */ - status = acpi_ns_check_object_type(pathname, return_object_ptr, + status = acpi_ns_check_object_type(data, return_object_ptr, predefined->info.expected_btypes, - ACPI_NOT_PACKAGE); + ACPI_NOT_PACKAGE_ELEMENT); if (ACPI_FAILURE(status)) { - goto exit; + goto check_validation_status; } /* For returned Package objects, check the type of all sub-objects */ if (return_object->common.type == ACPI_TYPE_PACKAGE) { - status = - acpi_ns_check_package(pathname, return_object_ptr, - predefined); + status = acpi_ns_check_package(data, return_object_ptr); } - exit: +check_validation_status: + /* + * If the object validation failed or if we successfully repaired one + * or more objects, mark the parent node to suppress further warning + * messages during the next evaluation of the same method/object. + */ + if (ACPI_FAILURE(status) || (data->flags & ACPI_OBJECT_REPAIRED)) { + node->flags |= ANOBJ_EVALUATED; + } + ACPI_FREE(data); + +cleanup: ACPI_FREE(pathname); return (status); } @@ -268,64 +285,58 @@ acpi_ns_check_parameter_count(char *pathname, param_count = node->object->method.param_count; } - /* Argument count check for non-predefined methods/objects */ - if (!predefined) { /* + * Check the parameter count for non-predefined methods/objects. + * * Warning if too few or too many arguments have been passed by the * caller. An incorrect number of arguments may not cause the method * to fail. However, the method will fail if there are too few * arguments and the method attempts to use one of the missing ones. */ if (user_param_count < param_count) { - ACPI_WARNING((AE_INFO, - "%s: Insufficient arguments - needs %d, found %d", - pathname, param_count, user_param_count)); + ACPI_WARN_PREDEFINED((AE_INFO, pathname, + ACPI_WARN_ALWAYS, + "Insufficient arguments - needs %u, found %u", + param_count, user_param_count)); } else if (user_param_count > param_count) { - ACPI_WARNING((AE_INFO, - "%s: Excess arguments - needs %d, found %d", - pathname, param_count, user_param_count)); + ACPI_WARN_PREDEFINED((AE_INFO, pathname, + ACPI_WARN_ALWAYS, + "Excess arguments - needs %u, found %u", + param_count, user_param_count)); } return; } - /* Allow two different legal argument counts (_SCP, etc.) */ - + /* + * Validate the user-supplied parameter count. + * Allow two different legal argument counts (_SCP, etc.) + */ required_params_current = predefined->info.param_count & 0x0F; required_params_old = predefined->info.param_count >> 4; if (user_param_count != ACPI_UINT32_MAX) { - - /* Validate the user-supplied parameter count */ - if ((user_param_count != required_params_current) && (user_param_count != required_params_old)) { - ACPI_WARNING((AE_INFO, - "%s: Parameter count mismatch - " - "caller passed %d, ACPI requires %d", - pathname, user_param_count, - required_params_current)); + ACPI_WARN_PREDEFINED((AE_INFO, pathname, + ACPI_WARN_ALWAYS, + "Parameter count mismatch - " + "caller passed %u, ACPI requires %u", + user_param_count, + required_params_current)); } } /* - * Only validate the argument count on the first successful evaluation of - * the method. This ensures that any warnings will only be emitted during - * the very first evaluation of the method/object. - */ - if (node->flags & ANOBJ_EVALUATED) { - return; - } - - /* * Check that the ASL-defined parameter count is what is expected for - * this predefined name. + * this predefined name (parameter count as defined by the ACPI + * specification) */ if ((param_count != required_params_current) && (param_count != required_params_old)) { - ACPI_WARNING((AE_INFO, - "%s: Parameter count mismatch - ASL declared %d, ACPI requires %d", - pathname, param_count, required_params_current)); + ACPI_WARN_PREDEFINED((AE_INFO, pathname, node->flags, + "Parameter count mismatch - ASL declared %u, ACPI requires %u", + param_count, required_params_current)); } } @@ -358,9 +369,6 @@ const union acpi_predefined_info *acpi_ns_check_for_predefined_name(struct this_name = predefined_names; while (this_name->info.name[0]) { if (ACPI_COMPARE_NAME(node->name.ascii, this_name->info.name)) { - - /* Return pointer to this table entry */ - return (this_name); } @@ -375,17 +383,16 @@ const union acpi_predefined_info *acpi_ns_check_for_predefined_name(struct this_name++; } - return (NULL); + return (NULL); /* Not found */ } /******************************************************************************* * * FUNCTION: acpi_ns_check_package * - * PARAMETERS: Pathname - Full pathname to the node (for error msgs) + * PARAMETERS: Data - Pointer to validation data structure * return_object_ptr - Pointer to the object returned from the * evaluation of a method or object - * Predefined - Pointer to entry in predefined name table * * RETURN: Status * @@ -395,9 +402,8 @@ const union acpi_predefined_info *acpi_ns_check_for_predefined_name(struct ******************************************************************************/ static acpi_status -acpi_ns_check_package(char *pathname, - union acpi_operand_object **return_object_ptr, - const union acpi_predefined_info *predefined) +acpi_ns_check_package(struct acpi_predefined_data *data, + union acpi_operand_object **return_object_ptr) { union acpi_operand_object *return_object = *return_object_ptr; const union acpi_predefined_info *package; @@ -414,11 +420,11 @@ acpi_ns_check_package(char *pathname, /* The package info for this name is in the next table entry */ - package = predefined + 1; + package = data->predefined + 1; ACPI_DEBUG_PRINT((ACPI_DB_NAMES, "%s Validating return Package of Type %X, Count %X\n", - pathname, package->ret_info.type, + data->pathname, package->ret_info.type, return_object->package.count)); /* Extract package count and elements array */ @@ -429,9 +435,8 @@ acpi_ns_check_package(char *pathname, /* The package must have at least one element, else invalid */ if (!count) { - ACPI_WARNING((AE_INFO, - "%s: Return Package has no elements (empty)", - pathname)); + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, data->node_flags, + "Return Package has no elements (empty)")); return (AE_AML_OPERAND_VALUE); } @@ -456,15 +461,16 @@ acpi_ns_check_package(char *pathname, if (count < expected_count) { goto package_too_small; } else if (count > expected_count) { - ACPI_WARNING((AE_INFO, - "%s: Return Package is larger than needed - " - "found %u, expected %u", pathname, count, - expected_count)); + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, + data->node_flags, + "Return Package is larger than needed - " + "found %u, expected %u", count, + expected_count)); } /* Validate all elements of the returned package */ - status = acpi_ns_check_package_elements(pathname, elements, + status = acpi_ns_check_package_elements(data, elements, package->ret_info. object_type1, package->ret_info. @@ -485,7 +491,7 @@ acpi_ns_check_package(char *pathname, * elements must be of the same type */ for (i = 0; i < count; i++) { - status = acpi_ns_check_object_type(pathname, elements, + status = acpi_ns_check_object_type(data, elements, package->ret_info. object_type1, i); if (ACPI_FAILURE(status)) { @@ -517,8 +523,7 @@ acpi_ns_check_package(char *pathname, /* These are the required package elements (0, 1, or 2) */ status = - acpi_ns_check_object_type(pathname, - elements, + acpi_ns_check_object_type(data, elements, package-> ret_info3. object_type[i], @@ -530,8 +535,7 @@ acpi_ns_check_package(char *pathname, /* These are the optional package elements */ status = - acpi_ns_check_object_type(pathname, - elements, + acpi_ns_check_object_type(data, elements, package-> ret_info3. tail_object_type, @@ -548,7 +552,7 @@ acpi_ns_check_package(char *pathname, /* First element is the (Integer) count of sub-packages to follow */ - status = acpi_ns_check_object_type(pathname, elements, + status = acpi_ns_check_object_type(data, elements, ACPI_RTYPE_INTEGER, 0); if (ACPI_FAILURE(status)) { return (status); @@ -585,9 +589,9 @@ acpi_ns_check_package(char *pathname, /* Each sub-object must be of type Package */ - status = - acpi_ns_check_object_type(pathname, &sub_package, - ACPI_RTYPE_PACKAGE, i); + status = acpi_ns_check_object_type(data, &sub_package, + ACPI_RTYPE_PACKAGE, + i); if (ACPI_FAILURE(status)) { return (status); } @@ -610,7 +614,7 @@ acpi_ns_check_package(char *pathname, } status = - acpi_ns_check_package_elements(pathname, + acpi_ns_check_package_elements(data, sub_elements, package-> ret_info. @@ -643,7 +647,7 @@ acpi_ns_check_package(char *pathname, for (j = 0; j < expected_count; j++) { status = - acpi_ns_check_object_type(pathname, + acpi_ns_check_object_type(data, &sub_elements[j], package->ret_info2.object_type[j], j); if (ACPI_FAILURE(status)) { @@ -665,7 +669,7 @@ acpi_ns_check_package(char *pathname, /* Check the type of each sub-package element */ status = - acpi_ns_check_package_elements(pathname, + acpi_ns_check_package_elements(data, sub_elements, package-> ret_info. @@ -684,7 +688,7 @@ acpi_ns_check_package(char *pathname, /* First element is the (Integer) count of elements to follow */ status = - acpi_ns_check_object_type(pathname, + acpi_ns_check_object_type(data, sub_elements, ACPI_RTYPE_INTEGER, 0); @@ -704,7 +708,7 @@ acpi_ns_check_package(char *pathname, /* Check the type of each sub-package element */ status = - acpi_ns_check_package_elements(pathname, + acpi_ns_check_package_elements(data, (sub_elements + 1), package-> @@ -730,9 +734,9 @@ acpi_ns_check_package(char *pathname, /* Should not get here if predefined info table is correct */ - ACPI_WARNING((AE_INFO, - "%s: Invalid internal return type in table entry: %X", - pathname, package->ret_info.type)); + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, data->node_flags, + "Invalid internal return type in table entry: %X", + package->ret_info.type)); return (AE_AML_INTERNAL); } @@ -743,9 +747,9 @@ acpi_ns_check_package(char *pathname, /* Error exit for the case with an incorrect package count */ - ACPI_WARNING((AE_INFO, "%s: Return Package is too small - " - "found %u, expected %u", pathname, count, - expected_count)); + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, data->node_flags, + "Return Package is too small - found %u, expected %u", + count, expected_count)); return (AE_AML_OPERAND_VALUE); } @@ -754,7 +758,7 @@ acpi_ns_check_package(char *pathname, * * FUNCTION: acpi_ns_check_package_elements * - * PARAMETERS: Pathname - Full pathname to the node (for error msgs) + * PARAMETERS: Data - Pointer to validation data structure * Elements - Pointer to the package elements array * Type1 - Object type for first group * Count1 - Count for first group @@ -770,7 +774,7 @@ acpi_ns_check_package(char *pathname, ******************************************************************************/ static acpi_status -acpi_ns_check_package_elements(char *pathname, +acpi_ns_check_package_elements(struct acpi_predefined_data *data, union acpi_operand_object **elements, u8 type1, u32 count1, @@ -786,7 +790,7 @@ acpi_ns_check_package_elements(char *pathname, * The second group can have a count of zero. */ for (i = 0; i < count1; i++) { - status = acpi_ns_check_object_type(pathname, this_element, + status = acpi_ns_check_object_type(data, this_element, type1, i + start_index); if (ACPI_FAILURE(status)) { return (status); @@ -795,7 +799,7 @@ acpi_ns_check_package_elements(char *pathname, } for (i = 0; i < count2; i++) { - status = acpi_ns_check_object_type(pathname, this_element, + status = acpi_ns_check_object_type(data, this_element, type2, (i + count1 + start_index)); if (ACPI_FAILURE(status)) { @@ -811,12 +815,13 @@ acpi_ns_check_package_elements(char *pathname, * * FUNCTION: acpi_ns_check_object_type * - * PARAMETERS: Pathname - Full pathname to the node (for error msgs) + * PARAMETERS: Data - Pointer to validation data structure * return_object_ptr - Pointer to the object returned from the * evaluation of a method or object * expected_btypes - Bitmap of expected return type(s) * package_index - Index of object within parent package (if - * applicable - ACPI_NOT_PACKAGE otherwise) + * applicable - ACPI_NOT_PACKAGE_ELEMENT + * otherwise) * * RETURN: Status * @@ -826,7 +831,7 @@ acpi_ns_check_package_elements(char *pathname, ******************************************************************************/ static acpi_status -acpi_ns_check_object_type(char *pathname, +acpi_ns_check_object_type(struct acpi_predefined_data *data, union acpi_operand_object **return_object_ptr, u32 expected_btypes, u32 package_index) { @@ -834,9 +839,6 @@ acpi_ns_check_object_type(char *pathname, acpi_status status = AE_OK; u32 return_btype; char type_buffer[48]; /* Room for 5 types */ - u32 this_rtype; - u32 i; - u32 j; /* * If we get a NULL return_object here, it is a NULL package element, @@ -849,10 +851,11 @@ acpi_ns_check_object_type(char *pathname, /* A Namespace node should not get here, but make sure */ if (ACPI_GET_DESCRIPTOR_TYPE(return_object) == ACPI_DESC_TYPE_NAMED) { - ACPI_WARNING((AE_INFO, - "%s: Invalid return type - Found a Namespace node [%4.4s] type %s", - pathname, return_object->node.name.ascii, - acpi_ut_get_type_name(return_object->node.type))); + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, data->node_flags, + "Invalid return type - Found a Namespace node [%4.4s] type %s", + return_object->node.name.ascii, + acpi_ut_get_type_name(return_object->node. + type))); return (AE_AML_OPERAND_TYPE); } @@ -897,10 +900,11 @@ acpi_ns_check_object_type(char *pathname, /* Type mismatch -- attempt repair of the returned object */ - status = acpi_ns_repair_object(expected_btypes, package_index, + status = acpi_ns_repair_object(data, expected_btypes, + package_index, return_object_ptr); if (ACPI_SUCCESS(status)) { - return (status); + return (AE_OK); /* Repair was successful */ } goto type_error_exit; } @@ -908,7 +912,7 @@ acpi_ns_check_object_type(char *pathname, /* For reference objects, check that the reference type is correct */ if (return_object->common.type == ACPI_TYPE_LOCAL_REFERENCE) { - status = acpi_ns_check_reference(pathname, return_object); + status = acpi_ns_check_reference(data, return_object); } return (status); @@ -917,33 +921,19 @@ acpi_ns_check_object_type(char *pathname, /* Create a string with all expected types for this predefined object */ - j = 1; - type_buffer[0] = 0; - this_rtype = ACPI_RTYPE_INTEGER; - - for (i = 0; i < ACPI_NUM_RTYPES; i++) { - - /* If one of the expected types, concatenate the name of this type */ - - if (expected_btypes & this_rtype) { - ACPI_STRCAT(type_buffer, &acpi_rtype_names[i][j]); - j = 0; /* Use name separator from now on */ - } - this_rtype <<= 1; /* Next Rtype */ - } + acpi_ns_get_expected_types(type_buffer, expected_btypes); - if (package_index == ACPI_NOT_PACKAGE) { - ACPI_WARNING((AE_INFO, - "%s: Return type mismatch - found %s, expected %s", - pathname, - acpi_ut_get_object_type_name(return_object), - type_buffer)); + if (package_index == ACPI_NOT_PACKAGE_ELEMENT) { + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, data->node_flags, + "Return type mismatch - found %s, expected %s", + acpi_ut_get_object_type_name + (return_object), type_buffer)); } else { - ACPI_WARNING((AE_INFO, - "%s: Return Package type mismatch at index %u - " - "found %s, expected %s", pathname, package_index, - acpi_ut_get_object_type_name(return_object), - type_buffer)); + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, data->node_flags, + "Return Package type mismatch at index %u - " + "found %s, expected %s", package_index, + acpi_ut_get_object_type_name + (return_object), type_buffer)); } return (AE_AML_OPERAND_TYPE); @@ -953,7 +943,7 @@ acpi_ns_check_object_type(char *pathname, * * FUNCTION: acpi_ns_check_reference * - * PARAMETERS: Pathname - Full pathname to the node (for error msgs) + * PARAMETERS: Data - Pointer to validation data structure * return_object - Object returned from the evaluation of a * method or object * @@ -966,7 +956,7 @@ acpi_ns_check_object_type(char *pathname, ******************************************************************************/ static acpi_status -acpi_ns_check_reference(char *pathname, +acpi_ns_check_reference(struct acpi_predefined_data *data, union acpi_operand_object *return_object) { @@ -979,11 +969,10 @@ acpi_ns_check_reference(char *pathname, return (AE_OK); } - ACPI_WARNING((AE_INFO, - "%s: Return type mismatch - " - "unexpected reference object type [%s] %2.2X", - pathname, acpi_ut_get_reference_name(return_object), - return_object->reference.class)); + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, data->node_flags, + "Return type mismatch - unexpected reference object type [%s] %2.2X", + acpi_ut_get_reference_name(return_object), + return_object->reference.class)); return (AE_AML_OPERAND_TYPE); } @@ -992,8 +981,11 @@ acpi_ns_check_reference(char *pathname, * * FUNCTION: acpi_ns_repair_object * - * PARAMETERS: Pathname - Full pathname to the node (for error msgs) - * package_index - Used to determine if target is in a package + * PARAMETERS: Data - Pointer to validation data structure + * expected_btypes - Object types expected + * package_index - Index of object within parent package (if + * applicable - ACPI_NOT_PACKAGE_ELEMENT + * otherwise) * return_object_ptr - Pointer to the object returned from the * evaluation of a method or object * @@ -1005,7 +997,8 @@ acpi_ns_check_reference(char *pathname, ******************************************************************************/ static acpi_status -acpi_ns_repair_object(u32 expected_btypes, +acpi_ns_repair_object(struct acpi_predefined_data *data, + u32 expected_btypes, u32 package_index, union acpi_operand_object **return_object_ptr) { @@ -1016,6 +1009,8 @@ acpi_ns_repair_object(u32 expected_btypes, switch (return_object->common.type) { case ACPI_TYPE_BUFFER: + /* Does the method/object legally return a string? */ + if (!(expected_btypes & ACPI_RTYPE_STRING)) { return (AE_AML_OPERAND_TYPE); } @@ -1052,19 +1047,29 @@ acpi_ns_repair_object(u32 expected_btypes, * reference count of the old object. * 2. Decrement the reference count of the original object. */ - if (package_index != ACPI_NOT_PACKAGE) { + if (package_index != ACPI_NOT_PACKAGE_ELEMENT) { new_object->common.reference_count = return_object->common.reference_count; if (return_object->common.reference_count > 1) { return_object->common.reference_count--; } + + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, + data->node_flags, + "Converted Buffer to expected String at index %u", + package_index)); + } else { + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, + data->node_flags, + "Converted Buffer to expected String")); } /* Delete old object, install the new return object */ acpi_ut_remove_reference(return_object); *return_object_ptr = new_object; + data->flags |= ACPI_OBJECT_REPAIRED; return (AE_OK); default: @@ -1073,3 +1078,39 @@ acpi_ns_repair_object(u32 expected_btypes, return (AE_AML_OPERAND_TYPE); } + +/******************************************************************************* + * + * FUNCTION: acpi_ns_get_expected_types + * + * PARAMETERS: Buffer - Pointer to where the string is returned + * expected_btypes - Bitmap of expected return type(s) + * + * RETURN: Buffer is populated with type names. + * + * DESCRIPTION: Translate the expected types bitmap into a string of ascii + * names of expected types, for use in warning messages. + * + ******************************************************************************/ + +static void acpi_ns_get_expected_types(char *buffer, u32 expected_btypes) +{ + u32 this_rtype; + u32 i; + u32 j; + + j = 1; + buffer[0] = 0; + this_rtype = ACPI_RTYPE_INTEGER; + + for (i = 0; i < ACPI_NUM_RTYPES; i++) { + + /* If one of the expected types, concatenate the name of this type */ + + if (expected_btypes & this_rtype) { + ACPI_STRCAT(buffer, &acpi_rtype_names[i][j]); + j = 0; /* Use name separator from now on */ + } + this_rtype <<= 1; /* Next Rtype */ + } +} diff --git a/drivers/acpi/acpica/utmisc.c b/drivers/acpi/acpica/utmisc.c index 9cd6533..5bd2960 100644 --- a/drivers/acpi/acpica/utmisc.c +++ b/drivers/acpi/acpica/utmisc.c @@ -50,6 +50,11 @@ #define _COMPONENT ACPI_UTILITIES ACPI_MODULE_NAME("utmisc") +/* + * Common suffix for messages + */ +#define ACPI_COMMON_MSG_SUFFIX \ + acpi_os_printf(" %8.8X %s-%u\n", ACPI_CA_VERSION, module_name, line_number) /******************************************************************************* * * FUNCTION: acpi_ut_validate_exception @@ -1065,8 +1070,7 @@ acpi_error(const char *module_name, u32 line_number, const char *format, ...) va_start(args, format); acpi_os_vprintf(format, args); - acpi_os_printf(" %8.8X %s-%u\n", ACPI_CA_VERSION, module_name, - line_number); + ACPI_COMMON_MSG_SUFFIX; va_end(args); } @@ -1080,8 +1084,7 @@ acpi_exception(const char *module_name, va_start(args, format); acpi_os_vprintf(format, args); - acpi_os_printf(" %8.8X %s-%u\n", ACPI_CA_VERSION, module_name, - line_number); + ACPI_COMMON_MSG_SUFFIX; va_end(args); } @@ -1094,8 +1097,7 @@ acpi_warning(const char *module_name, u32 line_number, const char *format, ...) va_start(args, format); acpi_os_vprintf(format, args); - acpi_os_printf(" %8.8X %s-%u\n", ACPI_CA_VERSION, module_name, - line_number); + ACPI_COMMON_MSG_SUFFIX; va_end(args); } @@ -1116,3 +1118,46 @@ ACPI_EXPORT_SYMBOL(acpi_error) ACPI_EXPORT_SYMBOL(acpi_exception) ACPI_EXPORT_SYMBOL(acpi_warning) ACPI_EXPORT_SYMBOL(acpi_info) + +/******************************************************************************* + * + * FUNCTION: acpi_ut_predefined_warning + * + * PARAMETERS: module_name - Caller's module name (for error output) + * line_number - Caller's line number (for error output) + * Pathname - Full pathname to the node + * node_flags - From Namespace node for the method/object + * Format - Printf format string + additional args + * + * RETURN: None + * + * DESCRIPTION: Warnings for the predefined validation module. Messages are + * only emitted the first time a problem with a particular + * method/object is detected. This prevents a flood of error + * messages for methods that are repeatedly evaluated. + * +******************************************************************************/ + +void ACPI_INTERNAL_VAR_XFACE +acpi_ut_predefined_warning(const char *module_name, + u32 line_number, + char *pathname, + u8 node_flags, const char *format, ...) +{ + va_list args; + + /* + * Warning messages for this method/object will be disabled after the + * first time a validation fails or an object is successfully repaired. + */ + if (node_flags & ANOBJ_EVALUATED) { + return; + } + + acpi_os_printf("ACPI Warning for %s: ", pathname); + + va_start(args, format); + acpi_os_vprintf(format, args); + ACPI_COMMON_MSG_SUFFIX; + va_end(args); +} -- cgit v0.10.2 From 8d590c7af1152685efcf302905baeb6dda3c2d2f Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Wed, 24 Jun 2009 13:39:29 +0800 Subject: ACPICA: Clarify common suffix for error/warning messages Added parens around the acpica version/modulename/linenumber to clearly differentiate this group from the rest of the message. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/utmisc.c b/drivers/acpi/acpica/utmisc.c index 5bd2960..61f6315 100644 --- a/drivers/acpi/acpica/utmisc.c +++ b/drivers/acpi/acpica/utmisc.c @@ -54,7 +54,7 @@ ACPI_MODULE_NAME("utmisc") * Common suffix for messages */ #define ACPI_COMMON_MSG_SUFFIX \ - acpi_os_printf(" %8.8X %s-%u\n", ACPI_CA_VERSION, module_name, line_number) + acpi_os_printf(" (%8.8X/%s-%u)\n", ACPI_CA_VERSION, module_name, line_number) /******************************************************************************* * * FUNCTION: acpi_ut_validate_exception -- cgit v0.10.2 From eb2289ba1ba994de25af0d94b5e80ba93d2c1c3c Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Wed, 24 Jun 2009 13:42:00 +0800 Subject: ACPICA: ACPI 4.0: Changes for existing ACPI tables. FACS: new flag and new OspmFlags field. SRAT: x2APIC - add ClockDomain field to descriptor #2 Includes header and disassembler support. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/include/acpi/actbl.h b/include/acpi/actbl.h index 222733d..0649a56 100644 --- a/include/acpi/actbl.h +++ b/include/acpi/actbl.h @@ -161,17 +161,24 @@ struct acpi_table_facs { u32 flags; u64 xfirmware_waking_vector; /* 64-bit version of the Firmware Waking Vector (ACPI 2.0+) */ u8 version; /* Version of this table (ACPI 2.0+) */ - u8 reserved[31]; /* Reserved, must be zero */ + u8 reserved[3]; /* Reserved, must be zero */ + u32 ospm_flags; /* Flags to be set by OSPM (ACPI 4.0) */ + u8 reserved1[24]; /* Reserved, must be zero */ }; -/* Flag macros */ +/* global_lock flags */ + +#define ACPI_GLOCK_PENDING (1) /* 00: Pending global lock ownership */ +#define ACPI_GLOCK_OWNED (1<<1) /* 01: Global lock is owned */ + +/* Flags */ -#define ACPI_FACS_S4_BIOS_PRESENT (1) /* 00: S4BIOS support is present */ +#define ACPI_FACS_S4_BIOS_PRESENT (1) /* 00: S4BIOS support is present */ +#define ACPI_FACS_64BIT_WAKE (1<<1) /* 01: 64-bit wake vector supported (ACPI 4.0) */ -/* Global lock flags */ +/* ospm_flags */ -#define ACPI_GLOCK_PENDING 0x01 /* 00: Pending global lock ownership */ -#define ACPI_GLOCK_OWNED 0x02 /* 01: Global lock is owned */ +#define ACPI_FACS_64BIT_ENVIRONMENT (1) /* 00: 64-bit wake environment is required (ACPI 4.0) */ /******************************************************************************* * diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 59ade07..ec36693 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1011,7 +1011,7 @@ struct acpi_madt_interrupt_source { #define ACPI_MADT_CPEI_OVERRIDE (1) -/* 9: Processor Local X2_APIC (07/2008) */ +/* 9: Processor Local X2APIC (ACPI 4.0) */ struct acpi_madt_local_x2apic { struct acpi_subtable_header header; @@ -1021,7 +1021,7 @@ struct acpi_madt_local_x2apic { u32 uid; /* ACPI processor UID */ }; -/* 10: Local X2APIC NMI (07/2008) */ +/* 10: Local X2APIC NMI (ACPI 4.0) */ struct acpi_madt_local_x2apic_nmi { struct acpi_subtable_header header; @@ -1211,7 +1211,7 @@ struct acpi_srat_mem_affinity { #define ACPI_SRAT_MEM_HOT_PLUGGABLE (1<<1) /* 01: Memory region is hot pluggable */ #define ACPI_SRAT_MEM_NON_VOLATILE (1<<2) /* 02: Memory region is non-volatile */ -/* 2: Processor Local X2_APIC Affinity (07/2008) */ +/* 2: Processor Local X2_APIC Affinity (ACPI 4.0) */ struct acpi_srat_x2apic_cpu_affinity { struct acpi_subtable_header header; @@ -1219,6 +1219,8 @@ struct acpi_srat_x2apic_cpu_affinity { u32 proximity_domain; u32 apic_id; u32 flags; + u32 clock_domain; + u32 reserved2; }; /* Flags for struct acpi_srat_cpu_affinity and struct acpi_srat_x2apic_cpu_affinity */ -- cgit v0.10.2 From 3ce804ed83827a7fd27190836f9421b29ac64512 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Thu, 25 Jun 2009 10:31:32 -0700 Subject: ACPICA: Update version to 20090625 Update version number. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index 04904c7..063e577 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -47,7 +47,7 @@ /* Current ACPICA subsystem version in YYYYMMDD format */ -#define ACPI_CA_VERSION 0x20090521 +#define ACPI_CA_VERSION 0x20090625 #include "actypes.h" #include "actbl.h" -- cgit v0.10.2 From a5fe1a03f7720b8da8364a1737e1e5a357904e99 Mon Sep 17 00:00:00 2001 From: Lin Ming Date: Thu, 13 Aug 2009 10:43:27 +0800 Subject: ACPICA: fix leak of acpi_os_validate_address http://bugzilla.kernel.org/show_bug.cgi?id=13620 If the dynamic region is created and added to resource list over and over again, it has the potential to be a memory leak by growing the list every time. This patch fixes the memory leak, as below 1) add a new field "count" to struct acpi_res_list. When inserting, if the region(addr, len) is already in the resource list, we just increase "count", otherwise, the region is inserted with count=1. When deleting, the "count" is decreased, if it's decreased to 0, the region is deleted from the resource list. With "count", the region with same address and length can only be inserted to the resource list once, so prevent potential memory leak. 2) add a new function acpi_os_invalidate_address, which is called when region is deleted. Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/utdelete.c b/drivers/acpi/acpica/utdelete.c index bc17103..96e26e7 100644 --- a/drivers/acpi/acpica/utdelete.c +++ b/drivers/acpi/acpica/utdelete.c @@ -215,6 +215,12 @@ static void acpi_ut_delete_internal_obj(union acpi_operand_object *object) ACPI_DEBUG_PRINT((ACPI_DB_ALLOCATIONS, "***** Region %p\n", object)); + /* Invalidate the region address/length via the host OS */ + + acpi_os_invalidate_address(object->region.space_id, + object->region.address, + (acpi_size) object->region.length); + second_desc = acpi_ns_get_secondary_object(object); if (second_desc) { /* diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index 5691f16..c5b4f1e 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c @@ -88,6 +88,7 @@ struct acpi_res_list { char name[5]; /* only can have a length of 4 chars, make use of this one instead of res->name, no need to kalloc then */ struct list_head resource_list; + int count; }; static LIST_HEAD(resource_list_head); @@ -1358,6 +1359,89 @@ acpi_os_validate_interface (char *interface) return AE_SUPPORT; } +static inline int acpi_res_list_add(struct acpi_res_list *res) +{ + struct acpi_res_list *res_list_elem; + + list_for_each_entry(res_list_elem, &resource_list_head, + resource_list) { + + if (res->resource_type == res_list_elem->resource_type && + res->start == res_list_elem->start && + res->end == res_list_elem->end) { + + /* + * The Region(addr,len) already exist in the list, + * just increase the count + */ + + res_list_elem->count++; + return 0; + } + } + + res->count = 1; + list_add(&res->resource_list, &resource_list_head); + return 1; +} + +static inline void acpi_res_list_del(struct acpi_res_list *res) +{ + struct acpi_res_list *res_list_elem; + + list_for_each_entry(res_list_elem, &resource_list_head, + resource_list) { + + if (res->resource_type == res_list_elem->resource_type && + res->start == res_list_elem->start && + res->end == res_list_elem->end) { + + /* + * If the res count is decreased to 0, + * remove and free it + */ + + if (--res_list_elem->count == 0) { + list_del(&res_list_elem->resource_list); + kfree(res_list_elem); + } + return; + } + } +} + +acpi_status +acpi_os_invalidate_address( + u8 space_id, + acpi_physical_address address, + acpi_size length) +{ + struct acpi_res_list res; + + switch (space_id) { + case ACPI_ADR_SPACE_SYSTEM_IO: + case ACPI_ADR_SPACE_SYSTEM_MEMORY: + /* Only interference checks against SystemIO and SytemMemory + are needed */ + res.start = address; + res.end = address + length - 1; + res.resource_type = space_id; + spin_lock(&acpi_res_lock); + acpi_res_list_del(&res); + spin_unlock(&acpi_res_lock); + break; + case ACPI_ADR_SPACE_PCI_CONFIG: + case ACPI_ADR_SPACE_EC: + case ACPI_ADR_SPACE_SMBUS: + case ACPI_ADR_SPACE_CMOS: + case ACPI_ADR_SPACE_PCI_BAR_TARGET: + case ACPI_ADR_SPACE_DATA_TABLE: + case ACPI_ADR_SPACE_FIXED_HARDWARE: + break; + } + return AE_OK; +} + /****************************************************************************** * * FUNCTION: acpi_os_validate_address @@ -1382,6 +1466,7 @@ acpi_os_validate_address ( char *name) { struct acpi_res_list *res; + int added; if (acpi_enforce_resources == ENFORCE_RESOURCES_NO) return AE_OK; @@ -1399,14 +1484,17 @@ acpi_os_validate_address ( res->end = address + length - 1; res->resource_type = space_id; spin_lock(&acpi_res_lock); - list_add(&res->resource_list, &resource_list_head); + added = acpi_res_list_add(res); spin_unlock(&acpi_res_lock); - pr_debug("Added %s resource: start: 0x%llx, end: 0x%llx, " - "name: %s\n", (space_id == ACPI_ADR_SPACE_SYSTEM_IO) + pr_debug("%s %s resource: start: 0x%llx, end: 0x%llx, " + "name: %s\n", added ? "Added" : "Already exist", + (space_id == ACPI_ADR_SPACE_SYSTEM_IO) ? "SystemIO" : "System Memory", (unsigned long long)res->start, (unsigned long long)res->end, res->name); + if (!added) + kfree(res); break; case ACPI_ADR_SPACE_PCI_CONFIG: case ACPI_ADR_SPACE_EC: diff --git a/include/acpi/acpiosxf.h b/include/acpi/acpiosxf.h index ab0b85c..eb0e718 100644 --- a/include/acpi/acpiosxf.h +++ b/include/acpi/acpiosxf.h @@ -245,6 +245,9 @@ acpi_status acpi_osi_invalidate(char* interface); acpi_status acpi_os_validate_address(u8 space_id, acpi_physical_address address, acpi_size length, char *name); +acpi_status +acpi_os_invalidate_address(u8 space_id, acpi_physical_address address, + acpi_size length); u64 acpi_os_get_timer(void); -- cgit v0.10.2 From 3b5e634103a5471d74e55d774e53db3df5c7b650 Mon Sep 17 00:00:00 2001 From: Zhang Rui Date: Thu, 6 Aug 2009 15:57:54 -0700 Subject: ACPI: video: remove unneeded memsets device->cap and video->cap are zeroed initially so we don't need to clear them again. Signed-off-by: Zhang Rui Signed-off-by: Andrew Morton Signed-off-by: Len Brown diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c index 8851315..a0cd0c7 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c @@ -934,9 +934,6 @@ static void acpi_video_device_find_cap(struct acpi_video_device *device) { acpi_handle h_dummy1; - - memset(&device->cap, 0, sizeof(device->cap)); - if (ACPI_SUCCESS(acpi_get_handle(device->dev->handle, "_ADR", &h_dummy1))) { device->cap._ADR = 1; } @@ -1039,7 +1036,6 @@ static void acpi_video_bus_find_cap(struct acpi_video_bus *video) { acpi_handle h_dummy1; - memset(&video->cap, 0, sizeof(video->cap)); if (ACPI_SUCCESS(acpi_get_handle(video->device->handle, "_DOS", &h_dummy1))) { video->cap._DOS = 1; } -- cgit v0.10.2 From aaf84eb95a9c610c6413cee4836764ea9194eed3 Mon Sep 17 00:00:00 2001 From: Benny Halevy Date: Thu, 20 Aug 2009 03:21:56 +0300 Subject: nfsd41: renew_client must be called under the state lock Until we work out the state locking so we can use a spin lock to protect the cl_lru, we need to take the state_lock to renew the client. Signed-off-by: Benny Halevy [nfsd41: Do not renew state on error] Signed-off-by: Ricardo Labiaga Signed-off-by: Benny Halevy [nfsd41: Simplify exit code] Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index d2a0524..5f634d2 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -1481,7 +1481,7 @@ nfsd4_sequence(struct svc_rqst *rqstp, * for nfsd4_svc_encode_compoundres processing */ status = nfsd4_replay_cache_entry(resp, seq); cstate->status = nfserr_replay_cache; - goto replay_cache; + goto out; } if (status) goto out; @@ -1497,15 +1497,18 @@ nfsd4_sequence(struct svc_rqst *rqstp, cstate->slot = slot; cstate->session = session; -replay_cache: - /* Renew the clientid on success and on replay. - * Hold a session reference until done processing the compound: + /* Hold a session reference until done processing the compound: * nfsd4_put_session called only if the cstate slot is set. */ - renew_client(session->se_client); nfsd4_get_session(session); out: spin_unlock(&sessionid_lock); + /* Renew the clientid on success and on replay */ + if (cstate->session) { + nfs4_lock_state(); + renew_client(session->se_client); + nfs4_unlock_state(); + } dprintk("%s: return %d\n", __func__, ntohl(status)); return status; } -- cgit v0.10.2 From b0401d725334a94d57335790b8ac2404144748ee Mon Sep 17 00:00:00 2001 From: Wei Yongjun Date: Thu, 27 Aug 2009 10:23:39 +0800 Subject: sunrpc: move the close processing after do recvfrom method sunrpc: "Move close processing to a single place" (d7979ae4a050a45b78af51832475001b68263d2a) moved the close processing before the recvfrom method. This may cause the close processing never to execute. So this patch moves it to the right place. Signed-off-by: Wei Yongjun Signed-off-by: J. Bruce Fields diff --git a/net/sunrpc/svc_xprt.c b/net/sunrpc/svc_xprt.c index dcd2d1e..912dea5 100644 --- a/net/sunrpc/svc_xprt.c +++ b/net/sunrpc/svc_xprt.c @@ -710,10 +710,7 @@ int svc_recv(struct svc_rqst *rqstp, long timeout) spin_unlock_bh(&pool->sp_lock); len = 0; - if (test_bit(XPT_CLOSE, &xprt->xpt_flags)) { - dprintk("svc_recv: found XPT_CLOSE\n"); - svc_delete_xprt(xprt); - } else if (test_bit(XPT_LISTENER, &xprt->xpt_flags)) { + if (test_bit(XPT_LISTENER, &xprt->xpt_flags)) { struct svc_xprt *newxpt; newxpt = xprt->xpt_ops->xpo_accept(xprt); if (newxpt) { @@ -739,7 +736,7 @@ int svc_recv(struct svc_rqst *rqstp, long timeout) svc_xprt_received(newxpt); } svc_xprt_received(xprt); - } else { + } else if (!test_bit(XPT_CLOSE, &xprt->xpt_flags)) { dprintk("svc: server %p, pool %u, transport %p, inuse=%d\n", rqstp, pool->sp_id, xprt, atomic_read(&xprt->xpt_ref.refcount)); @@ -752,6 +749,11 @@ int svc_recv(struct svc_rqst *rqstp, long timeout) dprintk("svc: got len=%d\n", len); } + if (test_bit(XPT_CLOSE, &xprt->xpt_flags)) { + dprintk("svc_recv: found XPT_CLOSE\n"); + svc_delete_xprt(xprt); + } + /* No data, incomplete (TCP) read, or accept() */ if (len == 0 || len == -EAGAIN) { rqstp->rq_res.len = 0; -- cgit v0.10.2 From d8d0b85b11476ce59684ad2998e91a522df518a0 Mon Sep 17 00:00:00 2001 From: Frank Filz Date: Thu, 27 Aug 2009 17:35:41 -0400 Subject: nfsd4: remove ACE4_IDENTIFIER_GROUP flag from GROUP@ entry RFC 3530 says "ACE4_IDENTIFIER_GROUP flag MUST be ignored on entries with these special identifiers. When encoding entries with these special identifiers, the ACE4_IDENTIFIER_GROUP flag SHOULD be set to zero." It really shouldn't matter either way, but the point is that this flag is used to distinguish named users from named groups (since unix allows a group to have the same name as a user), so it doesn't really make sense to use it on a special identifier such as this.) Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4acl.c b/fs/nfsd/nfs4acl.c index 5320c2b..725d02f 100644 --- a/fs/nfsd/nfs4acl.c +++ b/fs/nfsd/nfs4acl.c @@ -321,7 +321,7 @@ _posix_to_nfsv4_one(struct posix_acl *pacl, struct nfs4_acl *acl, deny = ~pas.group & pas.other; if (deny) { ace->type = NFS4_ACE_ACCESS_DENIED_ACE_TYPE; - ace->flag = eflag | NFS4_ACE_IDENTIFIER_GROUP; + ace->flag = eflag; ace->access_mask = deny_mask_from_posix(deny, flags); ace->whotype = NFS4_ACL_WHO_GROUP; ace++; -- cgit v0.10.2 From 468de9e54a900559b55aa939a4daeaea1915e572 Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Thu, 27 Aug 2009 12:07:40 -0400 Subject: nfsd41: expand solo sequence check Compounds consisting of only a sequence operation don't need any additional caching beyond the sequence information we store in the slot entry. Fix nfsd4_is_solo_sequence to identify this case correctly. The additional check for a failed sequence in nfsd4_store_cache_entry() is redundant, since the nfsd4_is_solo_sequence call lower down catches this case. The final ce_cachethis set in nfsd4_sequence is also redundant. Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 5f634d2..b44a2cf 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -991,16 +991,10 @@ nfsd4_store_cache_entry(struct nfsd4_compoundres *resp) { struct nfsd4_cache_entry *entry = &resp->cstate.slot->sl_cache_entry; struct svc_rqst *rqstp = resp->rqstp; - struct nfsd4_compoundargs *args = rqstp->rq_argp; - struct nfsd4_op *op = &args->ops[resp->opcnt]; struct kvec *resv = &rqstp->rq_res.head[0]; dprintk("--> %s entry %p\n", __func__, entry); - /* Don't cache a failed OP_SEQUENCE. */ - if (resp->opcnt == 1 && op->opnum == OP_SEQUENCE && resp->cstate.status) - return; - nfsd4_release_respages(entry->ce_respages, entry->ce_resused); entry->ce_opcnt = resp->opcnt; entry->ce_status = resp->cstate.status; @@ -1490,9 +1484,6 @@ nfsd4_sequence(struct svc_rqst *rqstp, slot->sl_inuse = true; slot->sl_seqid = seq->seqid; slot->sl_cache_entry.ce_cachethis = seq->cachethis; - /* Always set the cache entry cachethis for solo sequence */ - if (nfsd4_is_solo_sequence(resp)) - slot->sl_cache_entry.ce_cachethis = 1; cstate->slot = slot; cstate->session = session; diff --git a/include/linux/nfsd/xdr4.h b/include/linux/nfsd/xdr4.h index 5e4beb0..3f71660 100644 --- a/include/linux/nfsd/xdr4.h +++ b/include/linux/nfsd/xdr4.h @@ -467,7 +467,7 @@ struct nfsd4_compoundres { static inline bool nfsd4_is_solo_sequence(struct nfsd4_compoundres *resp) { struct nfsd4_compoundargs *args = resp->rqstp->rq_argp; - return args->opcnt == 1; + return resp->opcnt == 1 && args->ops[0].opnum == OP_SEQUENCE; } static inline bool nfsd4_not_cached(struct nfsd4_compoundres *resp) -- cgit v0.10.2 From c1b5310a957c47d1c66bb53035c6ba6aa20a150f Mon Sep 17 00:00:00 2001 From: Jonathan Woithe Date: Thu, 27 Aug 2009 18:45:33 -0400 Subject: fujitsu-laptop: fix config corner case This patch is a trivial fix for a config corner case, ensuring that fujitsu-laptop doesn't get compiled into the kernel when the led class is a module. Signed-off-by: Alan Jenkins Signed-off-by: Jonathan Woithe Signed-off-by: Len Brown diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index 77c6097..0b5a85b 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -99,6 +99,7 @@ config FUJITSU_LAPTOP depends on ACPI depends on INPUT depends on BACKLIGHT_CLASS_DEVICE + depends on LEDS_CLASS || LEDS_CLASS=n ---help--- This is a driver for laptops built by Fujitsu: -- cgit v0.10.2 From 1e384cb0f9a940f2a431d1708f963987e61d71e3 Mon Sep 17 00:00:00 2001 From: Stephen Gildea Date: Tue, 25 Aug 2009 14:41:52 +0930 Subject: fujitsu-laptop: support led-class as module Support fujitsu-laptop with led-class built as a module instead of being compiled in. Signed-off-by: Stephen Gildea Acked-by: Jonathan Woithe Signed-off-by: Len Brown diff --git a/drivers/platform/x86/fujitsu-laptop.c b/drivers/platform/x86/fujitsu-laptop.c index 218b9a1..4c8897a 100644 --- a/drivers/platform/x86/fujitsu-laptop.c +++ b/drivers/platform/x86/fujitsu-laptop.c @@ -66,7 +66,7 @@ #include #include #include -#ifdef CONFIG_LEDS_CLASS +#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) #include #endif @@ -96,7 +96,7 @@ /* FUNC interface - responses */ #define UNSUPPORTED_CMD 0x80000000 -#ifdef CONFIG_LEDS_CLASS +#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) /* FUNC interface - LED control */ #define FUNC_LED_OFF 0x1 #define FUNC_LED_ON 0x30001 @@ -176,7 +176,7 @@ static struct fujitsu_hotkey_t *fujitsu_hotkey; static void acpi_fujitsu_hotkey_notify(struct acpi_device *device, u32 event); -#ifdef CONFIG_LEDS_CLASS +#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) static enum led_brightness logolamp_get(struct led_classdev *cdev); static void logolamp_set(struct led_classdev *cdev, enum led_brightness brightness); @@ -257,7 +257,7 @@ static int call_fext_func(int cmd, int arg0, int arg1, int arg2) return out_obj.integer.value; } -#ifdef CONFIG_LEDS_CLASS +#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) /* LED class callbacks */ static void logolamp_set(struct led_classdev *cdev, @@ -911,7 +911,7 @@ static int acpi_fujitsu_hotkey_add(struct acpi_device *device) printk(KERN_INFO "fujitsu-laptop: BTNI: [0x%x]\n", call_fext_func(FUNC_BUTTONS, 0x0, 0x0, 0x0)); - #ifdef CONFIG_LEDS_CLASS + #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) if (call_fext_func(FUNC_LEDS, 0x0, 0x0, 0x0) & LOGOLAMP_POWERON) { result = led_classdev_register(&fujitsu->pf_device->dev, &logolamp_led); @@ -1204,7 +1204,7 @@ fail_acpi: static void __exit fujitsu_cleanup(void) { - #ifdef CONFIG_LEDS_CLASS + #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) if (fujitsu_hotkey->logolamp_registered != 0) led_classdev_unregister(&logolamp_led); -- cgit v0.10.2 From 14485c57270e8f3de2a25abaf93bae5712c97e9e Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Fri, 31 Jul 2009 18:12:00 +0930 Subject: fujitsu-laptop: Correct redundant test device and acpi_driver_data(device) were tested just a few lines above. A simplified version of the semantic match that finds this problem is as follows: (http://www.emn.fr/x-info/coccinelle/) // @r exists@ local idexpression x; expression E; @@ if (x == NULL || ...) { ... when forall return ...; } .. when != \(x=E\|x--\|x++\|--x\|++x\|x-=E\|x+=E\|x|=E\|x&=E\|&x\) ( *x == NULL | *x != NULL ) // Signed-off-by: Julia Lawall Acked-by: Jonathan Woithe Signed-off-by: Len Brown diff --git a/drivers/platform/x86/fujitsu-laptop.c b/drivers/platform/x86/fujitsu-laptop.c index 4c8897a..0d42f44 100644 --- a/drivers/platform/x86/fujitsu-laptop.c +++ b/drivers/platform/x86/fujitsu-laptop.c @@ -745,9 +745,6 @@ static int acpi_fujitsu_remove(struct acpi_device *device, int type) fujitsu = acpi_driver_data(device); - if (!device || !acpi_driver_data(device)) - return -EINVAL; - fujitsu->acpi_handle = NULL; return 0; -- cgit v0.10.2 From 67059406219d30a36b7ca93f863eb1f3032f05ce Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Fri, 31 Jul 2009 08:43:56 +0000 Subject: fujitsu-laptop: remove superfluous NULL pointer checks This takes care of the following entries from Dan's list: drivers/platform/x86/fujitsu-laptop.c +327 set_lcd_level(13) warning: variable derefenced before check 'fujitsu' drivers/platform/x86/fujitsu-laptop.c +358 set_lcd_level_alt(13) warning: variable derefenced before check 'fujitsu' Reported-by: Dan Carpenter Cc: corbet@lwn.net Cc: eteo@redhat.com Cc: Julia Lawall Signed-off-by: Bartlomiej Zolnierkiewicz Acked-by: Jonathan Woithe Signed-off-by: Len Brown diff --git a/drivers/platform/x86/fujitsu-laptop.c b/drivers/platform/x86/fujitsu-laptop.c index 0d42f44..f9e3e3a 100644 --- a/drivers/platform/x86/fujitsu-laptop.c +++ b/drivers/platform/x86/fujitsu-laptop.c @@ -324,9 +324,6 @@ static int set_lcd_level(int level) if (level < 0 || level >= fujitsu->max_brightness) return -EINVAL; - if (!fujitsu) - return -EINVAL; - status = acpi_get_handle(fujitsu->acpi_handle, "SBLL", &handle); if (ACPI_FAILURE(status)) { vdbg_printk(FUJLAPTOP_DBG_ERROR, "SBLL not present\n"); @@ -355,9 +352,6 @@ static int set_lcd_level_alt(int level) if (level < 0 || level >= fujitsu->max_brightness) return -EINVAL; - if (!fujitsu) - return -EINVAL; - status = acpi_get_handle(fujitsu->acpi_handle, "SBL2", &handle); if (ACPI_FAILURE(status)) { vdbg_printk(FUJLAPTOP_DBG_ERROR, "SBL2 not present\n"); -- cgit v0.10.2 From 72afeeafe54853881a4e53dc78d538e249130ad8 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Fri, 31 Jul 2009 18:16:02 +0930 Subject: fujitsu-laptop: driver [un]registration fixes * Move led_classdev_unregister() calls from fujitsu_cleanup() to acpi_fujitsu_hotkey_remove(). * Fix ordering in fujitsu_cleanup(). * Fix backlight_device_register() failure handling in fujitsu_init(). * Add missing sysfs group removal on failure to fujitsu_init(). * Add input device unregistering on failure to acpi_fujitsu_add() and acpi_fujitsu_hotkey_add(). * Add input device unregistering/freeing to acpi_fujitsu_remove() and acpi_fujitsu_hotkey_remove() (also remove superfluous 'device' and 'acpi_driver_data(device)' checks while at it). * Do few minor cleanups. Signed-off-by: Bartlomiej Zolnierkiewicz Acked-by: Jonathan Woithe Signed-off-by: Len Brown diff --git a/drivers/platform/x86/fujitsu-laptop.c b/drivers/platform/x86/fujitsu-laptop.c index f9e3e3a..b87a5a2 100644 --- a/drivers/platform/x86/fujitsu-laptop.c +++ b/drivers/platform/x86/fujitsu-laptop.c @@ -691,7 +691,7 @@ static int acpi_fujitsu_add(struct acpi_device *device) result = acpi_bus_get_power(fujitsu->acpi_handle, &state); if (result) { printk(KERN_ERR "Error reading power state\n"); - goto end; + goto err_unregister_input_dev; } printk(KERN_INFO PREFIX "%s [%s] (%s)\n", @@ -722,22 +722,22 @@ static int acpi_fujitsu_add(struct acpi_device *device) return result; -end: +err_unregister_input_dev: + input_unregister_device(input); err_free_input_dev: input_free_device(input); err_stop: - return result; } static int acpi_fujitsu_remove(struct acpi_device *device, int type) { - struct fujitsu_t *fujitsu = NULL; + struct fujitsu_t *fujitsu = acpi_driver_data(device); + struct input_dev *input = fujitsu->input; - if (!device || !acpi_driver_data(device)) - return -EINVAL; + input_unregister_device(input); - fujitsu = acpi_driver_data(device); + input_free_device(input); fujitsu->acpi_handle = NULL; @@ -862,7 +862,7 @@ static int acpi_fujitsu_hotkey_add(struct acpi_device *device) result = acpi_bus_get_power(fujitsu_hotkey->acpi_handle, &state); if (result) { printk(KERN_ERR "Error reading power state\n"); - goto end; + goto err_unregister_input_dev; } printk(KERN_INFO PREFIX "%s [%s] (%s)\n", @@ -902,7 +902,7 @@ static int acpi_fujitsu_hotkey_add(struct acpi_device *device) printk(KERN_INFO "fujitsu-laptop: BTNI: [0x%x]\n", call_fext_func(FUNC_BUTTONS, 0x0, 0x0, 0x0)); - #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) +#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) if (call_fext_func(FUNC_LEDS, 0x0, 0x0, 0x0) & LOGOLAMP_POWERON) { result = led_classdev_register(&fujitsu->pf_device->dev, &logolamp_led); @@ -925,33 +925,41 @@ static int acpi_fujitsu_hotkey_add(struct acpi_device *device) "LED handler for keyboard lamps, error %i\n", result); } } - #endif +#endif return result; -end: +err_unregister_input_dev: + input_unregister_device(input); err_free_input_dev: input_free_device(input); err_free_fifo: kfifo_free(fujitsu_hotkey->fifo); err_stop: - return result; } static int acpi_fujitsu_hotkey_remove(struct acpi_device *device, int type) { - struct fujitsu_hotkey_t *fujitsu_hotkey = NULL; + struct fujitsu_hotkey_t *fujitsu_hotkey = acpi_driver_data(device); + struct input_dev *input = fujitsu_hotkey->input; - if (!device || !acpi_driver_data(device)) - return -EINVAL; +#ifdef CONFIG_LEDS_CLASS + if (fujitsu_hotkey->logolamp_registered) + led_classdev_unregister(&logolamp_led); + + if (fujitsu_hotkey->kblamps_registered) + led_classdev_unregister(&kblamps_led); +#endif - fujitsu_hotkey = acpi_driver_data(device); + input_unregister_device(input); - fujitsu_hotkey->acpi_handle = NULL; + input_free_device(input); kfifo_free(fujitsu_hotkey->fifo); + fujitsu_hotkey->acpi_handle = NULL; + return 0; } @@ -1121,8 +1129,11 @@ static int __init fujitsu_init(void) fujitsu->bl_device = backlight_device_register("fujitsu-laptop", NULL, NULL, &fujitsubl_ops); - if (IS_ERR(fujitsu->bl_device)) - return PTR_ERR(fujitsu->bl_device); + if (IS_ERR(fujitsu->bl_device)) { + ret = PTR_ERR(fujitsu->bl_device); + fujitsu->bl_device = NULL; + goto fail_sysfs_group; + } max_brightness = fujitsu->max_brightness; fujitsu->bl_device->props.max_brightness = max_brightness - 1; fujitsu->bl_device->props.brightness = fujitsu->brightness_level; @@ -1162,32 +1173,22 @@ static int __init fujitsu_init(void) return 0; fail_hotkey1: - kfree(fujitsu_hotkey); - fail_hotkey: - platform_driver_unregister(&fujitsupf_driver); - fail_backlight: - if (fujitsu->bl_device) backlight_device_unregister(fujitsu->bl_device); - +fail_sysfs_group: + sysfs_remove_group(&fujitsu->pf_device->dev.kobj, + &fujitsupf_attribute_group); fail_platform_device2: - platform_device_del(fujitsu->pf_device); - fail_platform_device1: - platform_device_put(fujitsu->pf_device); - fail_platform_driver: - acpi_bus_unregister_driver(&acpi_fujitsu_driver); - fail_acpi: - kfree(fujitsu); return ret; @@ -1195,28 +1196,23 @@ fail_acpi: static void __exit fujitsu_cleanup(void) { - #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) - if (fujitsu_hotkey->logolamp_registered != 0) - led_classdev_unregister(&logolamp_led); + acpi_bus_unregister_driver(&acpi_fujitsu_hotkey_driver); - if (fujitsu_hotkey->kblamps_registered != 0) - led_classdev_unregister(&kblamps_led); - #endif + kfree(fujitsu_hotkey); - sysfs_remove_group(&fujitsu->pf_device->dev.kobj, - &fujitsupf_attribute_group); - platform_device_unregister(fujitsu->pf_device); platform_driver_unregister(&fujitsupf_driver); + if (fujitsu->bl_device) backlight_device_unregister(fujitsu->bl_device); - acpi_bus_unregister_driver(&acpi_fujitsu_driver); + sysfs_remove_group(&fujitsu->pf_device->dev.kobj, + &fujitsupf_attribute_group); - kfree(fujitsu); + platform_device_unregister(fujitsu->pf_device); - acpi_bus_unregister_driver(&acpi_fujitsu_hotkey_driver); + acpi_bus_unregister_driver(&acpi_fujitsu_driver); - kfree(fujitsu_hotkey); + kfree(fujitsu); printk(KERN_INFO "fujitsu-laptop: driver unloaded.\n"); } -- cgit v0.10.2 From 84a6ce267296dabdf427ea4aff73dc58164863bb Mon Sep 17 00:00:00 2001 From: Jonathan Woithe Date: Fri, 31 Jul 2009 18:16:59 +0930 Subject: fujitsu-laptop: increment driver version Increment driver version to reflect the changes from this patch series. Signed-off-by: Jonathan Woithe Signed-off-by: Len Brown diff --git a/drivers/platform/x86/fujitsu-laptop.c b/drivers/platform/x86/fujitsu-laptop.c index b87a5a2..1ed3513 100644 --- a/drivers/platform/x86/fujitsu-laptop.c +++ b/drivers/platform/x86/fujitsu-laptop.c @@ -70,7 +70,7 @@ #include #endif -#define FUJITSU_DRIVER_VERSION "0.5.0" +#define FUJITSU_DRIVER_VERSION "0.6.0" #define FUJITSU_LCD_N_LEVELS 8 -- cgit v0.10.2 From 6d41839e762f8b8b03dbb97fd0d41b244d0bc902 Mon Sep 17 00:00:00 2001 From: Alan Jenkins Date: Fri, 28 Aug 2009 12:56:32 +0000 Subject: eeepc-laptop: don't touch the pci slot if it was claimed by a different driver The whole point of registering as a PCI hotplug driver was to prevent conflict with pciehp. At the moment it happens to work because eeepc-laptop is loaded first, but it doesn't work the other way round. If pciehp is loaded first then we fail to claim the slot - we need to respect this and not handle hotplug events. Signed-off-by: Alan Jenkins Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index 222ffb89..69d73ed 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -664,15 +664,20 @@ static int eeepc_get_adapter_status(struct hotplug_slot *hotplug_slot, static void eeepc_hotplug_work(struct work_struct *work) { struct pci_dev *dev; - struct pci_bus *bus = pci_find_bus(0, 1); - bool blocked; + struct pci_bus *bus; + bool blocked = eeepc_wlan_rfkill_blocked(); + + rfkill_set_sw_state(ehotk->wlan_rfkill, blocked); + if (ehotk->hotplug_slot == NULL) + return; + + bus = pci_find_bus(0, 1); if (!bus) { pr_warning("Unable to find PCI bus 1?\n"); return; } - blocked = eeepc_wlan_rfkill_blocked(); if (!blocked) { dev = pci_get_slot(bus, 0); if (dev) { @@ -693,8 +698,6 @@ static void eeepc_hotplug_work(struct work_struct *work) pci_dev_put(dev); } } - - rfkill_set_sw_state(ehotk->wlan_rfkill, blocked); } static void eeepc_rfkill_notify(acpi_handle handle, u32 event, void *data) -- cgit v0.10.2 From dcf443b5813074031a45b05ad9c57da98bcae329 Mon Sep 17 00:00:00 2001 From: Alan Jenkins Date: Fri, 28 Aug 2009 12:56:33 +0000 Subject: eeepc-laptop: use a mutex to serialize pci hotplug (resume vs. notify) Commit d0265f0 "eeepc-laptop: fix hot-unplug on resume" used a workqueue to protect pci hotplug against multiple simultaneous calls during resume. It seems to work, but a mutex would be more appropriate. This is in preparation to fix the potential pci hotplug race on unload. Signed-off-by: Alan Jenkins Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index 69d73ed..1790103 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -143,7 +143,7 @@ struct eeepc_hotk { struct rfkill *bluetooth_rfkill; struct rfkill *wwan3g_rfkill; struct hotplug_slot *hotplug_slot; - struct work_struct hotplug_work; + struct mutex hotplug_lock; }; /* The actual device the driver binds to */ @@ -661,7 +661,7 @@ static int eeepc_get_adapter_status(struct hotplug_slot *hotplug_slot, return 0; } -static void eeepc_hotplug_work(struct work_struct *work) +static void eeepc_rfkill_hotplug(void) { struct pci_dev *dev; struct pci_bus *bus; @@ -669,13 +669,15 @@ static void eeepc_hotplug_work(struct work_struct *work) rfkill_set_sw_state(ehotk->wlan_rfkill, blocked); + mutex_lock(&ehotk->hotplug_lock); + if (ehotk->hotplug_slot == NULL) - return; + goto out_unlock; bus = pci_find_bus(0, 1); if (!bus) { pr_warning("Unable to find PCI bus 1?\n"); - return; + goto out_unlock; } if (!blocked) { @@ -683,7 +685,7 @@ static void eeepc_hotplug_work(struct work_struct *work) if (dev) { /* Device already present */ pci_dev_put(dev); - return; + goto out_unlock; } dev = pci_scan_single_device(bus, 0); if (dev) { @@ -698,6 +700,9 @@ static void eeepc_hotplug_work(struct work_struct *work) pci_dev_put(dev); } } + +out_unlock: + mutex_unlock(&ehotk->hotplug_lock); } static void eeepc_rfkill_notify(acpi_handle handle, u32 event, void *data) @@ -705,7 +710,7 @@ static void eeepc_rfkill_notify(acpi_handle handle, u32 event, void *data) if (event != ACPI_NOTIFY_BUS_CHECK) return; - schedule_work(&ehotk->hotplug_work); + eeepc_rfkill_hotplug(); } static void eeepc_hotk_notify(struct acpi_device *device, u32 event) @@ -896,7 +901,7 @@ static int eeepc_hotk_resume(struct acpi_device *device) rfkill_set_sw_state(ehotk->wlan_rfkill, wlan != 1); - schedule_work(&ehotk->hotplug_work); + eeepc_rfkill_hotplug(); } if (ehotk->bluetooth_rfkill) @@ -1097,7 +1102,7 @@ static int eeepc_rfkill_init(struct device *dev) { int result = 0; - INIT_WORK(&ehotk->hotplug_work, eeepc_hotplug_work); + mutex_init(&ehotk->hotplug_lock); eeepc_register_rfkill_notifier("\\_SB.PCI0.P0P6"); eeepc_register_rfkill_notifier("\\_SB.PCI0.P0P7"); -- cgit v0.10.2 From 07e84aa98f6b3a7278d3267f6f657955ed3eb973 Mon Sep 17 00:00:00 2001 From: Alan Jenkins Date: Fri, 28 Aug 2009 12:56:34 +0000 Subject: eeepc-laptop: fix pci hotplug race on load and unload Wifi rfkill state changes can race with pci hotplug cleanup. A simple fix is to refresh the hotplug state just before deregistering the pci hotplug slot. There is also potential for a hotplug notification to fire too early during setup, while the structures it uses are still being initialised. (This could only happen if the BIOS performs hotplug itself; a bug triggered by removing the battery while hibernated). Avoid this by registering the notifier later. The same refresh mechanism is used to handle rfkill state changes which can now race with registration. Signed-off-by: Alan Jenkins Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index 1790103..8dd86f7 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -667,37 +667,37 @@ static void eeepc_rfkill_hotplug(void) struct pci_bus *bus; bool blocked = eeepc_wlan_rfkill_blocked(); - rfkill_set_sw_state(ehotk->wlan_rfkill, blocked); + if (ehotk->wlan_rfkill) + rfkill_set_sw_state(ehotk->wlan_rfkill, blocked); mutex_lock(&ehotk->hotplug_lock); - if (ehotk->hotplug_slot == NULL) - goto out_unlock; - - bus = pci_find_bus(0, 1); - if (!bus) { - pr_warning("Unable to find PCI bus 1?\n"); - goto out_unlock; - } - - if (!blocked) { - dev = pci_get_slot(bus, 0); - if (dev) { - /* Device already present */ - pci_dev_put(dev); + if (ehotk->hotplug_slot) { + bus = pci_find_bus(0, 1); + if (!bus) { + pr_warning("Unable to find PCI bus 1?\n"); goto out_unlock; } - dev = pci_scan_single_device(bus, 0); - if (dev) { - pci_bus_assign_resources(bus); - if (pci_bus_add_device(dev)) - pr_err("Unable to hotplug wifi\n"); - } - } else { - dev = pci_get_slot(bus, 0); - if (dev) { - pci_remove_bus_device(dev); - pci_dev_put(dev); + + if (!blocked) { + dev = pci_get_slot(bus, 0); + if (dev) { + /* Device already present */ + pci_dev_put(dev); + goto out_unlock; + } + dev = pci_scan_single_device(bus, 0); + if (dev) { + pci_bus_assign_resources(bus); + if (pci_bus_add_device(dev)) + pr_err("Unable to hotplug wifi\n"); + } + } else { + dev = pci_get_slot(bus, 0); + if (dev) { + pci_remove_bus_device(dev); + pci_dev_put(dev); + } } } @@ -1029,14 +1029,22 @@ static void eeepc_rfkill_exit(void) { eeepc_unregister_rfkill_notifier("\\_SB.PCI0.P0P6"); eeepc_unregister_rfkill_notifier("\\_SB.PCI0.P0P7"); - if (ehotk->wlan_rfkill) + if (ehotk->wlan_rfkill) { rfkill_unregister(ehotk->wlan_rfkill); + ehotk->wlan_rfkill = NULL; + } + /* + * Refresh pci hotplug in case the rfkill state was changed after + * eeepc_unregister_rfkill_notifier() + */ + eeepc_rfkill_hotplug(); + if (ehotk->hotplug_slot) + pci_hp_deregister(ehotk->hotplug_slot); + if (ehotk->bluetooth_rfkill) rfkill_unregister(ehotk->bluetooth_rfkill); if (ehotk->wwan3g_rfkill) rfkill_unregister(ehotk->wwan3g_rfkill); - if (ehotk->hotplug_slot) - pci_hp_deregister(ehotk->hotplug_slot); } static void eeepc_input_exit(void) @@ -1104,9 +1112,6 @@ static int eeepc_rfkill_init(struct device *dev) mutex_init(&ehotk->hotplug_lock); - eeepc_register_rfkill_notifier("\\_SB.PCI0.P0P6"); - eeepc_register_rfkill_notifier("\\_SB.PCI0.P0P7"); - result = eeepc_new_rfkill(&ehotk->wlan_rfkill, "eeepc-wlan", dev, RFKILL_TYPE_WLAN, CM_ASL_WLAN); @@ -1136,6 +1141,14 @@ static int eeepc_rfkill_init(struct device *dev) if (result == -EBUSY) result = 0; + eeepc_register_rfkill_notifier("\\_SB.PCI0.P0P6"); + eeepc_register_rfkill_notifier("\\_SB.PCI0.P0P7"); + /* + * Refresh pci hotplug in case the rfkill state was changed during + * setup. + */ + eeepc_rfkill_hotplug(); + exit: if (result && result != -ENODEV) eeepc_rfkill_exit(); -- cgit v0.10.2 From 1e7798547fe6920ae27fb92c9202353e9e4c55db Mon Sep 17 00:00:00 2001 From: Alan Jenkins Date: Fri, 28 Aug 2009 12:56:35 +0000 Subject: eeepc-laptop: fix ordering of init and exit functions 1. input and backlight devices were registered after acpi notifications are enabled. This left a window where eeepc_hotk_notify() might find these devices in an inconsistent (half-initialized) state. -> Move all device registration into eeepc_hotk_add(), which is called before enabling acpi notifications. 2. input and backlight devices were unregistered before acpi notifications are disabled. This left a window where eeepc_hotk_notify() might find these devices in an inconsistent (half-destroyed) state. -> Move all device unregistration into eeepc_hotk_remove(), which is called after disabling acpi notifications. 3. The acpi driver was not freed if an error occured further down in eeepc_laptop_init(). -> The rest of eeepc_laptop_init() has been moved to eeepc_hotk_add(), so this is no longer a problem. 4. The acpi driver was unregistered before the platform driver. This left a window where a sysfs access could attempt to read the ehotk structure after it had been freed by eeepc_hotk_remove(). -> The acpi driver is now unregistered as the last step in eeepc_laptop_exit(), so this is no longer a problem. Signed-off-by: Alan Jenkins Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index 8dd86f7..cf47d1c 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -847,44 +847,6 @@ error_slot: return ret; } -static int eeepc_hotk_add(struct acpi_device *device) -{ - int result; - - if (!device) - return -EINVAL; - pr_notice(EEEPC_HOTK_NAME "\n"); - ehotk = kzalloc(sizeof(struct eeepc_hotk), GFP_KERNEL); - if (!ehotk) - return -ENOMEM; - ehotk->init_flag = DISABLE_ASL_WLAN | DISABLE_ASL_DISPLAYSWITCH; - ehotk->handle = device->handle; - strcpy(acpi_device_name(device), EEEPC_HOTK_DEVICE_NAME); - strcpy(acpi_device_class(device), EEEPC_HOTK_CLASS); - device->driver_data = ehotk; - ehotk->device = device; - result = eeepc_hotk_check(); - if (result) - goto ehotk_fail; - - return 0; - - ehotk_fail: - kfree(ehotk); - ehotk = NULL; - - return result; -} - -static int eeepc_hotk_remove(struct acpi_device *device, int type) -{ - if (!device || !acpi_driver_data(device)) - return -EINVAL; - - kfree(ehotk); - return 0; -} - static int eeepc_hotk_resume(struct acpi_device *device) { if (ehotk->wlan_rfkill) { @@ -1066,19 +1028,6 @@ static void eeepc_hwmon_exit(void) eeepc_hwmon_device = NULL; } -static void __exit eeepc_laptop_exit(void) -{ - eeepc_backlight_exit(); - eeepc_rfkill_exit(); - eeepc_input_exit(); - eeepc_hwmon_exit(); - acpi_bus_unregister_driver(&eeepc_hotk_driver); - sysfs_remove_group(&platform_device->dev.kobj, - &platform_attribute_group); - platform_device_unregister(platform_device); - platform_driver_unregister(&platform_driver); -} - static int eeepc_new_rfkill(struct rfkill **rfkill, const char *name, struct device *dev, enum rfkill_type type, int cm) @@ -1193,21 +1142,27 @@ static int eeepc_hwmon_init(struct device *dev) return result; } -static int __init eeepc_laptop_init(void) +static int eeepc_hotk_add(struct acpi_device *device) { struct device *dev; int result; - if (acpi_disabled) - return -ENODEV; - result = acpi_bus_register_driver(&eeepc_hotk_driver); - if (result < 0) - return result; - if (!ehotk) { - acpi_bus_unregister_driver(&eeepc_hotk_driver); - return -ENODEV; - } + if (!device) + return -EINVAL; + pr_notice(EEEPC_HOTK_NAME "\n"); + ehotk = kzalloc(sizeof(struct eeepc_hotk), GFP_KERNEL); + if (!ehotk) + return -ENOMEM; + ehotk->init_flag = DISABLE_ASL_WLAN | DISABLE_ASL_DISPLAYSWITCH; + ehotk->handle = device->handle; + strcpy(acpi_device_name(device), EEEPC_HOTK_DEVICE_NAME); + strcpy(acpi_device_class(device), EEEPC_HOTK_CLASS); + device->driver_data = ehotk; + ehotk->device = device; + result = eeepc_hotk_check(); + if (result) + goto fail_check; eeepc_enable_camera(); /* Register platform stuff */ @@ -1246,6 +1201,7 @@ static int __init eeepc_laptop_init(void) goto fail_rfkill; return 0; + fail_rfkill: eeepc_hwmon_exit(); fail_hwmon: @@ -1261,8 +1217,50 @@ fail_platform_device1: platform_driver_unregister(&platform_driver); fail_platform_driver: eeepc_input_exit(); +fail_check: + kfree(ehotk); + return result; } +static int eeepc_hotk_remove(struct acpi_device *device, int type) +{ + if (!device || !acpi_driver_data(device)) + return -EINVAL; + + eeepc_backlight_exit(); + eeepc_rfkill_exit(); + eeepc_input_exit(); + eeepc_hwmon_exit(); + sysfs_remove_group(&platform_device->dev.kobj, + &platform_attribute_group); + platform_device_unregister(platform_device); + platform_driver_unregister(&platform_driver); + + kfree(ehotk); + return 0; +} + +static int __init eeepc_laptop_init(void) +{ + int result; + + if (acpi_disabled) + return -ENODEV; + result = acpi_bus_register_driver(&eeepc_hotk_driver); + if (result < 0) + return result; + if (!ehotk) { + acpi_bus_unregister_driver(&eeepc_hotk_driver); + return -ENODEV; + } + return 0; +} + +static void __exit eeepc_laptop_exit(void) +{ + acpi_bus_unregister_driver(&eeepc_hotk_driver); +} + module_init(eeepc_laptop_init); module_exit(eeepc_laptop_exit); -- cgit v0.10.2 From f2a9d5e8a649c606f520b7a7b9f4f46fba79c327 Mon Sep 17 00:00:00 2001 From: Alan Jenkins Date: Fri, 28 Aug 2009 12:56:36 +0000 Subject: eeepc-laptop: make input device a child of the platform device Sysfs showed the ehotk input device as a "virtual" device - lies! The input device is provided by a physical device, the eeepc platform. This requires that we move the creation of the input device to come after platform device is created. Input initialization is moved from ehotk_check() [sic] to a new function called eeepc_input_init(). This brings the input device into line with the other eeepc-laptop devices. Also, refuse to load if we fail to register the input device. Signed-off-by: Alan Jenkins Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index cf47d1c..298dac9 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -579,7 +579,6 @@ static void cmsg_quirks(void) static int eeepc_hotk_check(void) { - const struct key_entry *key; struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; int result; @@ -604,31 +603,6 @@ static int eeepc_hotk_check(void) pr_info("Get control methods supported: 0x%x\n", ehotk->cm_supported); } - ehotk->inputdev = input_allocate_device(); - if (!ehotk->inputdev) { - pr_info("Unable to allocate input device\n"); - return 0; - } - ehotk->inputdev->name = "Asus EeePC extra buttons"; - ehotk->inputdev->phys = EEEPC_HOTK_FILE "/input0"; - ehotk->inputdev->id.bustype = BUS_HOST; - ehotk->inputdev->getkeycode = eeepc_getkeycode; - ehotk->inputdev->setkeycode = eeepc_setkeycode; - - for (key = eeepc_keymap; key->type != KE_END; key++) { - switch (key->type) { - case KE_KEY: - set_bit(EV_KEY, ehotk->inputdev->evbit); - set_bit(key->keycode, ehotk->inputdev->keybit); - break; - } - } - result = input_register_device(ehotk->inputdev); - if (result) { - pr_info("Unable to register input device\n"); - input_free_device(ehotk->inputdev); - return 0; - } } else { pr_err("Hotkey device not present, aborting\n"); return -EINVAL; @@ -1142,6 +1116,40 @@ static int eeepc_hwmon_init(struct device *dev) return result; } +static int eeepc_input_init(struct device *dev) +{ + const struct key_entry *key; + int result; + + ehotk->inputdev = input_allocate_device(); + if (!ehotk->inputdev) { + pr_info("Unable to allocate input device\n"); + return -ENOMEM; + } + ehotk->inputdev->name = "Asus EeePC extra buttons"; + ehotk->inputdev->dev.parent = dev; + ehotk->inputdev->phys = EEEPC_HOTK_FILE "/input0"; + ehotk->inputdev->id.bustype = BUS_HOST; + ehotk->inputdev->getkeycode = eeepc_getkeycode; + ehotk->inputdev->setkeycode = eeepc_setkeycode; + + for (key = eeepc_keymap; key->type != KE_END; key++) { + switch (key->type) { + case KE_KEY: + set_bit(EV_KEY, ehotk->inputdev->evbit); + set_bit(key->keycode, ehotk->inputdev->keybit); + break; + } + } + result = input_register_device(ehotk->inputdev); + if (result) { + pr_info("Unable to register input device\n"); + input_free_device(ehotk->inputdev); + return result; + } + return 0; +} + static int eeepc_hotk_add(struct acpi_device *device) { struct device *dev; @@ -1162,7 +1170,7 @@ static int eeepc_hotk_add(struct acpi_device *device) result = eeepc_hotk_check(); if (result) - goto fail_check; + goto fail_platform_driver; eeepc_enable_camera(); /* Register platform stuff */ @@ -1192,6 +1200,10 @@ static int eeepc_hotk_add(struct acpi_device *device) pr_info("Backlight controlled by ACPI video " "driver\n"); + result = eeepc_input_init(dev); + if (result) + goto fail_input; + result = eeepc_hwmon_init(dev); if (result) goto fail_hwmon; @@ -1205,6 +1217,8 @@ static int eeepc_hotk_add(struct acpi_device *device) fail_rfkill: eeepc_hwmon_exit(); fail_hwmon: + eeepc_input_exit(); +fail_input: eeepc_backlight_exit(); fail_backlight: sysfs_remove_group(&platform_device->dev.kobj, @@ -1216,8 +1230,6 @@ fail_platform_device2: fail_platform_device1: platform_driver_unregister(&platform_driver); fail_platform_driver: - eeepc_input_exit(); -fail_check: kfree(ehotk); return result; -- cgit v0.10.2 From ffb03575284e0f72d7ea001178c793afa265b8b5 Mon Sep 17 00:00:00 2001 From: Alan Jenkins Date: Fri, 28 Aug 2009 12:56:37 +0000 Subject: eeepc-laptop: remove redundant rfkill_set_sw_state in resume handler rfkill_set_sw_state() will already be called by eeepc_rfkill_hotplug(). Signed-off-by: Alan Jenkins Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index 298dac9..7f7573a 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -835,8 +835,7 @@ static int eeepc_hotk_resume(struct acpi_device *device) wlan = get_acpi(CM_ASL_WLAN); set_acpi(CM_ASL_WLAN, wlan); - rfkill_set_sw_state(ehotk->wlan_rfkill, wlan != 1); - + /* Refresh both rfkill state and pci hotplug */ eeepc_rfkill_hotplug(); } -- cgit v0.10.2 From a47461011a0f5110c497b9b163d1125d258418b2 Mon Sep 17 00:00:00 2001 From: Alan Jenkins Date: Fri, 28 Aug 2009 12:56:38 +0000 Subject: eeepc-laptop: check the 3G rfkill state on resume All the rfkill devices are treated as "persistent", 3G is no exception. This means their state may change over hibernation. Signed-off-by: Alan Jenkins Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index 7f7573a..8a32004 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -842,6 +842,9 @@ static int eeepc_hotk_resume(struct acpi_device *device) if (ehotk->bluetooth_rfkill) rfkill_set_sw_state(ehotk->bluetooth_rfkill, get_acpi(CM_ASL_BLUETOOTH) != 1); + if (ehotk->wwan3g_rfkill) + rfkill_set_sw_state(ehotk->wwan3g_rfkill, + get_acpi(CM_ASL_3G) != 1); return 0; } -- cgit v0.10.2 From c1edd99f1c2b0285ce810d217180bf37bbae550e Mon Sep 17 00:00:00 2001 From: Alan Jenkins Date: Fri, 28 Aug 2009 12:56:39 +0000 Subject: eeepc-laptop: correct the description of the hibernation abort bug Actually it is only the LED which is affected. The bios bug does not disable the wifi. Signed-off-by: Alan Jenkins Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index 8a32004..df68ae6 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -826,11 +826,10 @@ static int eeepc_hotk_resume(struct acpi_device *device) if (ehotk->wlan_rfkill) { bool wlan; - /* Workaround - it seems that _PTS disables the wireless - without notification or changing the value read by WLAN. - Normally this is fine because the correct value is restored - from the non-volatile storage on resume, but we need to do - it ourself if case suspend is aborted, or we lose wireless. + /* + * Work around bios bug - acpi _PTS turns off the wireless led + * during suspend. Normally it restores it on resume, but + * we should kick it ourselves in case suspend is aborted. */ wlan = get_acpi(CM_ASL_WLAN); set_acpi(CM_ASL_WLAN, wlan); -- cgit v0.10.2 From c200da5d2900df9c24fb8041870d92a4175bbef3 Mon Sep 17 00:00:00 2001 From: Alan Jenkins Date: Fri, 28 Aug 2009 12:56:40 +0000 Subject: eeepc-laptop: switch to dev_pm_ops This also involves switching the resume handler from the acpi device to the platform device. Using the more fine grained handlers allows two improvements: 1. We only need to recheck rfkill state after resume from hibernation. 2. The wireless LED workaround accounts for up to 1.1s out of 1.7s resuming devices (when wireless is enabled). We can limit the workaround to thaw(), so that it only delays suspend to disk. The workaround is only likely to help when hibernation is aborted. Suspend to ram cannot be aborted by the user. Device suspend errors may well happen before eeepc-laptop would even be frozen. Suspend errors which happen after that could be pretty funky anyway. Signed-off-by: Alan Jenkins Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index df68ae6..1c94860 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -150,10 +150,19 @@ struct eeepc_hotk { static struct eeepc_hotk *ehotk; /* Platform device/driver */ +static int eeepc_hotk_thaw(struct device *device); +static int eeepc_hotk_restore(struct device *device); + +static struct dev_pm_ops eeepc_pm_ops = { + .thaw = eeepc_hotk_thaw, + .restore = eeepc_hotk_restore, +}; + static struct platform_driver platform_driver = { .driver = { .name = EEEPC_HOTK_FILE, .owner = THIS_MODULE, + .pm = &eeepc_pm_ops, } }; @@ -192,7 +201,6 @@ static struct key_entry eeepc_keymap[] = { */ static int eeepc_hotk_add(struct acpi_device *device); static int eeepc_hotk_remove(struct acpi_device *device, int type); -static int eeepc_hotk_resume(struct acpi_device *device); static void eeepc_hotk_notify(struct acpi_device *device, u32 event); static const struct acpi_device_id eeepc_device_ids[] = { @@ -209,7 +217,6 @@ static struct acpi_driver eeepc_hotk_driver = { .ops = { .add = eeepc_hotk_add, .remove = eeepc_hotk_remove, - .resume = eeepc_hotk_resume, .notify = eeepc_hotk_notify, }, }; @@ -821,7 +828,7 @@ error_slot: return ret; } -static int eeepc_hotk_resume(struct acpi_device *device) +static int eeepc_hotk_thaw(struct device *device) { if (ehotk->wlan_rfkill) { bool wlan; @@ -829,14 +836,20 @@ static int eeepc_hotk_resume(struct acpi_device *device) /* * Work around bios bug - acpi _PTS turns off the wireless led * during suspend. Normally it restores it on resume, but - * we should kick it ourselves in case suspend is aborted. + * we should kick it ourselves in case hibernation is aborted. */ wlan = get_acpi(CM_ASL_WLAN); set_acpi(CM_ASL_WLAN, wlan); + } + + return 0; +} - /* Refresh both rfkill state and pci hotplug */ +static int eeepc_hotk_restore(struct device *device) +{ + /* Refresh both wlan rfkill state and pci hotplug */ + if (ehotk->wlan_rfkill) eeepc_rfkill_hotplug(); - } if (ehotk->bluetooth_rfkill) rfkill_set_sw_state(ehotk->bluetooth_rfkill, -- cgit v0.10.2 From d1ec9c3d434d94e3674bcf433e8e8e7462b8e1c0 Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:41 +0000 Subject: eeepc-laptop: add rfkill support for the Wimax in ASUS Eee PC 1000HG Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index 1c94860..c9febf4 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -142,6 +142,7 @@ struct eeepc_hotk { struct rfkill *wlan_rfkill; struct rfkill *bluetooth_rfkill; struct rfkill *wwan3g_rfkill; + struct rfkill *wimax_rfkill; struct hotplug_slot *hotplug_slot; struct mutex hotplug_lock; }; @@ -857,6 +858,9 @@ static int eeepc_hotk_restore(struct device *device) if (ehotk->wwan3g_rfkill) rfkill_set_sw_state(ehotk->wwan3g_rfkill, get_acpi(CM_ASL_3G) != 1); + if (ehotk->wimax_rfkill) + rfkill_set_sw_state(ehotk->wimax_rfkill, + get_acpi(CM_ASL_WIMAX) != 1); return 0; } @@ -995,6 +999,8 @@ static void eeepc_rfkill_exit(void) rfkill_unregister(ehotk->bluetooth_rfkill); if (ehotk->wwan3g_rfkill) rfkill_unregister(ehotk->wwan3g_rfkill); + if (ehotk->wimax_rfkill) + rfkill_unregister(ehotk->wimax_rfkill); } static void eeepc_input_exit(void) @@ -1070,6 +1076,13 @@ static int eeepc_rfkill_init(struct device *dev) if (result && result != -ENODEV) goto exit; + result = eeepc_new_rfkill(&ehotk->wimax_rfkill, + "eeepc-wimax", dev, + RFKILL_TYPE_WIMAX, CM_ASL_WIMAX); + + if (result && result != -ENODEV) + goto exit; + result = eeepc_setup_pci_hotplug(); /* * If we get -EBUSY then something else is handling the PCI hotplug - -- cgit v0.10.2 From d0a6825c9217cfc52d39b2b2bedd73bef8019f79 Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:42 +0000 Subject: eeepc-laptop: document sysfs interface Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/Documentation/ABI/testing/sysfs-platform-eeepc-laptop b/Documentation/ABI/testing/sysfs-platform-eeepc-laptop new file mode 100644 index 0000000..7445dfb --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-eeepc-laptop @@ -0,0 +1,50 @@ +What: /sys/devices/platform/eeepc-laptop/disp +Date: May 2008 +KernelVersion: 2.6.26 +Contact: "Corentin Chary" +Description: + This file allows display switching. + - 1 = LCD + - 2 = CRT + - 3 = LCD+CRT + If you run X11, you should use xrandr instead. + +What: /sys/devices/platform/eeepc-laptop/camera +Date: May 2008 +KernelVersion: 2.6.26 +Contact: "Corentin Chary" +Description: + Control the camera. 1 means on, 0 means off. + +What: /sys/devices/platform/eeepc-laptop/cardr +Date: May 2008 +KernelVersion: 2.6.26 +Contact: "Corentin Chary" +Description: + Control the card reader. 1 means on, 0 means off. + +What: /sys/devices/platform/eeepc-laptop/cpufv +Date: Jun 2009 +KernelVersion: 2.6.31 +Contact: "Corentin Chary" +Description: + Change CPU clock configuration. + On the Eee PC 1000H there are three available clock configuration: + * 0 -> Super Performance Mode + * 1 -> High Performance Mode + * 2 -> Power Saving Mode + On Eee PC 701 there is only 2 available clock configurations. + Available configuration are listed in available_cpufv file. + Reading this file will show the raw hexadecimal value which + is defined as follow: + | 8 bit | 8 bit | + | `---- Current mode + `------------ Availables modes + For example, 0x301 means: mode 1 selected, 3 available modes. + +What: /sys/devices/platform/eeepc-laptop/available_cpufv +Date: Jun 2009 +KernelVersion: 2.6.31 +Contact: "Corentin Chary" +Description: + List available cpufv modes. -- cgit v0.10.2 From 3c4c1b69a2d76ac9a1c716233fde956dba757d76 Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:43 +0000 Subject: video/backlight: document sysfs interface Date and KernelVersion may be wrong because the backlight interface was introduced before git initial import. Cc:Richard Purdie Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/Documentation/ABI/stable/sysfs-class-backlight b/Documentation/ABI/stable/sysfs-class-backlight new file mode 100644 index 0000000..4d637e1 --- /dev/null +++ b/Documentation/ABI/stable/sysfs-class-backlight @@ -0,0 +1,36 @@ +What: /sys/class/backlight//bl_power +Date: April 2005 +KernelVersion: 2.6.12 +Contact: Richard Purdie +Description: + Control BACKLIGHT power, values are FB_BLANK_* from fb.h + - FB_BLANK_UNBLANK (0) : power on. + - FB_BLANK_POWERDOWN (4) : power off +Users: HAL + +What: /sys/class/backlight//brightness +Date: April 2005 +KernelVersion: 2.6.12 +Contact: Richard Purdie +Description: + Control the brightness for this . Values + are between 0 and max_brightness. This file will also + show the brightness level stored in the driver, which + may not be the actual brightness (see actual_brightness). +Users: HAL + +What: /sys/class/backlight//actual_brightness +Date: March 2006 +KernelVersion: 2.6.17 +Contact: Richard Purdie +Description: + Show the actual brightness by querying the hardware. +Users: HAL + +What: /sys/class/backlight//max_brightness +Date: April 2005 +KernelVersion: 2.6.12 +Contact: Richard Purdie +Description: + Maximum brightness for . +Users: HAL -- cgit v0.10.2 From 243ca3e401bc62e704785d215931f1a51fd53bd7 Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:44 +0000 Subject: video/lcd: document sysfs interface Date and KernelVersion may be wrong because the lcd interface was introduced before git initial import. Cc: Richard Purdie Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/Documentation/ABI/testing/sysfs-class-lcd b/Documentation/ABI/testing/sysfs-class-lcd new file mode 100644 index 0000000..35906bf --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-lcd @@ -0,0 +1,23 @@ +What: /sys/class/lcd//lcd_power +Date: April 2005 +KernelVersion: 2.6.12 +Contact: Richard Purdie +Description: + Control LCD power, values are FB_BLANK_* from fb.h + - FB_BLANK_UNBLANK (0) : power on. + - FB_BLANK_POWERDOWN (4) : power off + +What: /sys/class/lcd//contrast +Date: April 2005 +KernelVersion: 2.6.12 +Contact: Richard Purdie +Description: + Current contrast of this LCD device. Value is between 0 and + /sys/class/lcd//max_contrast. + +What: /sys/class/lcd//max_contrast +Date: April 2005 +KernelVersion: 2.6.12 +Contact: Richard Purdie +Description: + Maximum contrast for this LCD device. -- cgit v0.10.2 From 5f634c6527249275df4199a294ee9cec2f3ff3b1 Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:45 +0000 Subject: led: document sysfs interface Also fix Documentation/led-class.txt, the acceptable range of values for brightness is 0-max_brightness, not 0-255. Cc: Richard Purdie Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/Documentation/ABI/testing/sysfs-class-led b/Documentation/ABI/testing/sysfs-class-led new file mode 100644 index 0000000..9e4541d --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-led @@ -0,0 +1,28 @@ +What: /sys/class/leds//brightness +Date: March 2006 +KernelVersion: 2.6.17 +Contact: Richard Purdie +Description: + Set the brightness of the LED. Most LEDs don't + have hardware brightness support so will just be turned on for + non-zero brightness settings. The value is between 0 and + /sys/class/leds//max_brightness. + +What: /sys/class/leds//max_brightness +Date: March 2006 +KernelVersion: 2.6.17 +Contact: Richard Purdie +Description: + Maximum brightness level for this led, default is 255 (LED_FULL). + +What: /sys/class/leds//trigger +Date: March 2006 +KernelVersion: 2.6.17 +Contact: Richard Purdie +Description: + Set the trigger for this LED. A trigger is a kernel based source + of led events. + You can change triggers in a similar manner to the way an IO + scheduler is chosen. Trigger specific parameters can appear in + /sys/class/leds/ once a given trigger is selected. + diff --git a/Documentation/leds-class.txt b/Documentation/leds-class.txt index 6399557..8fd5ca2 100644 --- a/Documentation/leds-class.txt +++ b/Documentation/leds-class.txt @@ -1,3 +1,4 @@ + LED handling under Linux ======================== @@ -5,10 +6,10 @@ If you're reading this and thinking about keyboard leds, these are handled by the input subsystem and the led class is *not* needed. In its simplest form, the LED class just allows control of LEDs from -userspace. LEDs appear in /sys/class/leds/. The brightness file will -set the brightness of the LED (taking a value 0-255). Most LEDs don't -have hardware brightness support so will just be turned on for non-zero -brightness settings. +userspace. LEDs appear in /sys/class/leds/. The maximum brightness of the +LED is defined in max_brightness file. The brightness file will set the brightness +of the LED (taking a value 0-max_brightness). Most LEDs don't have hardware +brightness support so will just be turned on for non-zero brightness settings. The class also introduces the optional concept of an LED trigger. A trigger is a kernel based source of led events. Triggers can either be simple or -- cgit v0.10.2 From 1d4a3800c764d111d67462a14589ed1611b2f55e Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:46 +0000 Subject: asus-laptop: Show HRWS in infos and fix output format Show HRWS in /sys/platform/devices/asus-laptop/infos. HRWS is a bitfield used to get information about Hardware available in the laptop. Also change sprintf format from 0x%04x to %#x. Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c index db657bb..2344950 100644 --- a/drivers/platform/x86/asus-laptop.c +++ b/drivers/platform/x86/asus-laptop.c @@ -516,7 +516,17 @@ static ssize_t show_infos(struct device *dev, */ rv = acpi_evaluate_integer(hotk->handle, "SFUN", NULL, &temp); if (!ACPI_FAILURE(rv)) - len += sprintf(page + len, "SFUN value : 0x%04x\n", + len += sprintf(page + len, "SFUN value : %#x\n", + (uint) temp); + /* + * The HWRS method return informations about the hardware. + * 0x80 bit is for WLAN, 0x100 for Bluetooth. + * The significance of others is yet to be found. + * If we don't find the method, we assume the device are present. + */ + rv = acpi_evaluate_integer(hotk->handle, "HRWS", NULL, &temp); + if (!ACPI_FAILURE(rv)) + len += sprintf(page + len, "HRWS value : %#x\n", (uint) temp); /* * Another value for userspace: the ASYM method returns 0x02 for @@ -527,7 +537,7 @@ static ssize_t show_infos(struct device *dev, */ rv = acpi_evaluate_integer(hotk->handle, "ASYM", NULL, &temp); if (!ACPI_FAILURE(rv)) - len += sprintf(page + len, "ASYM value : 0x%04x\n", + len += sprintf(page + len, "ASYM value : %#x\n", (uint) temp); if (asus_info) { snprintf(buf, 16, "%d", asus_info->length); -- cgit v0.10.2 From abfa57e15acaa6e1ec567c250e5212bc55d79e43 Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:47 +0000 Subject: asus-laptop: Add *_led_get() functions Add support for getting led brightness directly from the hardware. Currently we don't need it, but it is needed to support keyboard backlight/led. Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c index 2344950..88cc9a1 100644 --- a/drivers/platform/x86/asus-laptop.c +++ b/drivers/platform/x86/asus-laptop.c @@ -246,12 +246,15 @@ static struct workqueue_struct *led_workqueue; #define ASUS_LED(object, ledname) \ static void object##_led_set(struct led_classdev *led_cdev, \ enum led_brightness value); \ + static enum led_brightness object##_led_get( \ + struct led_classdev *led_cdev); \ static void object##_led_update(struct work_struct *ignored); \ static int object##_led_wk; \ static DECLARE_WORK(object##_led_work, object##_led_update); \ static struct led_classdev object##_led = { \ .name = "asus::" ledname, \ .brightness_set = object##_led_set, \ + .brightness_get = object##_led_get, \ } ASUS_LED(mled, "mail"); @@ -399,6 +402,11 @@ static void write_status(acpi_handle handle, int out, int mask) { \ int value = object##_led_wk; \ write_status(object##_set_handle, value, (mask)); \ + } \ + static enum led_brightness object##_led_get( \ + struct led_classdev *led_cdev) \ + { \ + return led_cdev->brightness; \ } ASUS_LED_HANDLER(mled, MLED_ON); -- cgit v0.10.2 From f641375b65f64e83be8be68ae1ebce21ee4fd578 Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:48 +0000 Subject: asus-laptop: Map X50R hotkeys Map some new hotkeys found on X50R. Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c index 88cc9a1..410e545 100644 --- a/drivers/platform/x86/asus-laptop.c +++ b/drivers/platform/x86/asus-laptop.c @@ -285,6 +285,9 @@ static struct key_entry asus_keymap[] = { {KE_KEY, 0x51, KEY_WWW}, {KE_KEY, 0x5C, KEY_SCREENLOCK}, /* Screenlock */ {KE_KEY, 0x5D, KEY_WLAN}, + {KE_KEY, 0x5E, KEY_WLAN}, + {KE_KEY, 0x5F, KEY_WLAN}, + {KE_KEY, 0x60, KEY_SWITCHVIDEOMODE}, {KE_KEY, 0x61, KEY_SWITCHVIDEOMODE}, {KE_KEY, 0x6B, BTN_TOUCH}, /* Lock Mouse */ {KE_KEY, 0x82, KEY_CAMERA}, -- cgit v0.10.2 From 977c328d81e31fde70c5ba381d9cf7357451dd74 Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:49 +0000 Subject: asus-laptop: set maximum led brightness Set the right maximum brightness which is one, because they can only be on or off. Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c index 410e545..652902e 100644 --- a/drivers/platform/x86/asus-laptop.c +++ b/drivers/platform/x86/asus-laptop.c @@ -243,7 +243,7 @@ static struct backlight_ops asusbl_ops = { * potentially bad time, such as a timer interrupt. */ static struct workqueue_struct *led_workqueue; -#define ASUS_LED(object, ledname) \ +#define ASUS_LED(object, ledname, max) \ static void object##_led_set(struct led_classdev *led_cdev, \ enum led_brightness value); \ static enum led_brightness object##_led_get( \ @@ -255,13 +255,14 @@ static struct workqueue_struct *led_workqueue; .name = "asus::" ledname, \ .brightness_set = object##_led_set, \ .brightness_get = object##_led_get, \ + .max_brightness = max \ } -ASUS_LED(mled, "mail"); -ASUS_LED(tled, "touchpad"); -ASUS_LED(rled, "record"); -ASUS_LED(pled, "phone"); -ASUS_LED(gled, "gaming"); +ASUS_LED(mled, "mail", 1); +ASUS_LED(tled, "touchpad", 1); +ASUS_LED(rled, "record", 1); +ASUS_LED(pled, "phone", 1); +ASUS_LED(gled, "gaming", 1); struct key_entry { char type; -- cgit v0.10.2 From b7d3fbc2ed624cc216adda0f2574570e6d6d6aed Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:50 +0000 Subject: asus-laptop: Add support for Keyboard backlight Add support for keyboard backlight found in Asus U50VG. The SMC driver for the Apples does it via LED. To be consistent with that we create /sys/class/leds/asus::kbd_backlight/ to control the keyboard backlight. SLKB and GLKB are used to get/set the backlight. On the U50VG is supports 4 brightness level, but this may change with other models. SLKB take a 8 bit integer where the higher bit is used to toggle the backlight, and the over 7 bits control the brightness level. Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c index 652902e..0fb4e59 100644 --- a/drivers/platform/x86/asus-laptop.c +++ b/drivers/platform/x86/asus-laptop.c @@ -86,6 +86,7 @@ #define GLED_ON 0x40 //Gaming LED #define LCD_ON 0x80 //LCD backlight #define GPS_ON 0x100 //GPS +#define KEY_ON 0x200 //Keyboard backlight #define ASUS_LOG ASUS_HOTK_FILE ": " #define ASUS_ERR KERN_ERR ASUS_LOG @@ -172,6 +173,10 @@ ASUS_HANDLE(gps_on, ASUS_HOTK_PREFIX "SDON"); /* R2H */ ASUS_HANDLE(gps_off, ASUS_HOTK_PREFIX "SDOF"); /* R2H */ ASUS_HANDLE(gps_status, ASUS_HOTK_PREFIX "GPST"); +/* Keyboard light */ +ASUS_HANDLE(kled_set, ASUS_HOTK_PREFIX "SLKB"); +ASUS_HANDLE(kled_get, ASUS_HOTK_PREFIX "GLKB"); + /* * This is the main structure, we can use it to store anything interesting * about the hotk device @@ -263,6 +268,7 @@ ASUS_LED(tled, "touchpad", 1); ASUS_LED(rled, "record", 1); ASUS_LED(pled, "phone", 1); ASUS_LED(gled, "gaming", 1); +ASUS_LED(kled, "kbd_backlight", 3); struct key_entry { char type; @@ -419,6 +425,60 @@ ASUS_LED_HANDLER(rled, RLED_ON); ASUS_LED_HANDLER(tled, TLED_ON); ASUS_LED_HANDLER(gled, GLED_ON); +/* + * Keyboard backlight + */ +static int get_kled_lvl(void) +{ + unsigned long long kblv; + struct acpi_object_list params; + union acpi_object in_obj; + acpi_status rv; + + params.count = 1; + params.pointer = &in_obj; + in_obj.type = ACPI_TYPE_INTEGER; + in_obj.integer.value = 2; + + rv = acpi_evaluate_integer(kled_get_handle, NULL, ¶ms, &kblv); + if (ACPI_FAILURE(rv)) { + pr_warning("Error reading kled level\n"); + return 0; + } + return kblv; +} + +static int set_kled_lvl(int kblv) +{ + if (kblv > 0) + kblv = (1 << 7) | (kblv & 0x7F); + else + kblv = 0; + + if (write_acpi_int(kled_set_handle, NULL, kblv, NULL)) { + pr_warning("Keyboard LED display write failed\n"); + return -EINVAL; + } + return 0; +} + +static void kled_led_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + kled_led_wk = value; + queue_work(led_workqueue, &kled_led_work); +} + +static void kled_led_update(struct work_struct *ignored) +{ + set_kled_lvl(kled_led_wk); +} + +static enum led_brightness kled_led_get(struct led_classdev *led_cdev) +{ + return get_kled_lvl(); +} + static int get_lcd_state(void) { return read_status(LCD_ON); @@ -1059,6 +1119,9 @@ static int asus_hotk_get_info(void) ASUS_HANDLE_INIT(ledd_set); + ASUS_HANDLE_INIT(kled_set); + ASUS_HANDLE_INIT(kled_get); + /* * The HWRS method return informations about the hardware. * 0x80 bit is for WLAN, 0x100 for Bluetooth. @@ -1190,6 +1253,10 @@ static int asus_hotk_add(struct acpi_device *device) /* LCD Backlight is on by default */ write_status(NULL, 1, LCD_ON); + /* Keyboard Backlight is on by default */ + if (kled_set_handle) + set_kled_lvl(1); + /* LED display is off by default */ hotk->ledd_status = 0xFFF; @@ -1244,6 +1311,7 @@ static void asus_led_exit(void) ASUS_LED_UNREGISTER(pled); ASUS_LED_UNREGISTER(rled); ASUS_LED_UNREGISTER(gled); + ASUS_LED_UNREGISTER(kled); } static void asus_input_exit(void) @@ -1323,13 +1391,20 @@ static int asus_led_init(struct device *dev) if (rv) goto out4; + if (kled_set_handle && kled_get_handle) + rv = ASUS_LED_REGISTER(kled, dev); + if (rv) + goto out5; + led_workqueue = create_singlethread_workqueue("led_workqueue"); if (!led_workqueue) - goto out5; + goto out6; return 0; -out5: +out6: rv = -ENOMEM; + ASUS_LED_UNREGISTER(kled); +out5: ASUS_LED_UNREGISTER(gled); out4: ASUS_LED_UNREGISTER(pled); -- cgit v0.10.2 From dc79526078d2c0f01445e54e1d9fdf7c15ffd63d Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:51 +0000 Subject: asus-laptop: handle keyboard backlight keys Add support for the Fn+F3/Fn+F4 keys and map them as KEY_KBDILLUMUP and KEY_KBDILLUMDOWN. Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c index 0fb4e59..dd926b9 100644 --- a/drivers/platform/x86/asus-laptop.c +++ b/drivers/platform/x86/asus-laptop.c @@ -301,6 +301,8 @@ static struct key_entry asus_keymap[] = { {KE_KEY, 0x8A, KEY_PROG1}, {KE_KEY, 0x95, KEY_MEDIA}, {KE_KEY, 0x99, KEY_PHONE}, + {KE_KEY, 0xc4, KEY_KBDILLUMUP}, + {KE_KEY, 0xc5, KEY_KBDILLUMDOWN}, {KE_END, 0}, }; -- cgit v0.10.2 From 4644d0e5bd1412bbaed77e46c0c3376c6d060a74 Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:52 +0000 Subject: asus-laptop: Add suport for another "Media" key Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c index dd926b9..0325f7c 100644 --- a/drivers/platform/x86/asus-laptop.c +++ b/drivers/platform/x86/asus-laptop.c @@ -288,6 +288,7 @@ static struct key_entry asus_keymap[] = { {KE_KEY, 0x41, KEY_NEXTSONG}, {KE_KEY, 0x43, KEY_STOPCD}, {KE_KEY, 0x45, KEY_PLAYPAUSE}, + {KE_KEY, 0x4c, KEY_MEDIA}, {KE_KEY, 0x50, KEY_EMAIL}, {KE_KEY, 0x51, KEY_WWW}, {KE_KEY, 0x5C, KEY_SCREENLOCK}, /* Screenlock */ -- cgit v0.10.2 From 0aa20f7d720ed1feeb74df8c63a6427d9a2d3ebd Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:53 +0000 Subject: asus-laptop: Add "calculator" hotkey Found on UX50V. Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c index 0325f7c..5b912cc 100644 --- a/drivers/platform/x86/asus-laptop.c +++ b/drivers/platform/x86/asus-laptop.c @@ -291,6 +291,7 @@ static struct key_entry asus_keymap[] = { {KE_KEY, 0x4c, KEY_MEDIA}, {KE_KEY, 0x50, KEY_EMAIL}, {KE_KEY, 0x51, KEY_WWW}, + {KE_KEY, 0x55, KEY_CALC}, {KE_KEY, 0x5C, KEY_SCREENLOCK}, /* Screenlock */ {KE_KEY, 0x5D, KEY_WLAN}, {KE_KEY, 0x5E, KEY_WLAN}, -- cgit v0.10.2 From 6ce2c9d9a531e8753005a25a686dafab9a5d04bb Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:54 +0000 Subject: asus-laptop: document the module Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/Documentation/laptops/asus-laptop.txt b/Documentation/laptops/asus-laptop.txt new file mode 100644 index 0000000..c1c5be8 --- /dev/null +++ b/Documentation/laptops/asus-laptop.txt @@ -0,0 +1,258 @@ +Asus Laptop Extras + +Version 0.1 +August 6, 2009 + +Corentin Chary +http://acpi4asus.sf.net/ + + This driver provides support for extra features of ACPI-compatible ASUS laptops. + It may also support some MEDION, JVC or VICTOR laptops (such as MEDION 9675 or + VICTOR XP7210 for example). It makes all the extra buttons generate standard + ACPI events that go through /proc/acpi/events and input events (like keyboards). + On some models adds support for changing the display brightness and output, + switching the LCD backlight on and off, and most importantly, allows you to + blink those fancy LEDs intended for reporting mail and wireless status. + +This driver supercedes the old asus_acpi driver. + +Requirements +------------ + + Kernel 2.6.X sources, configured for your computer, with ACPI support. + You also need CONFIG_INPUT and CONFIG_ACPI. + +Status +------ + + The features currently supported are the following (see below for + detailed description): + + - Fn key combinations + - Bluetooth enable and disable + - Wlan enable and disable + - GPS enable and disable + - Video output switching + - Ambient Light Sensor on and off + - LED control + - LED Display control + - LCD brightness control + - LCD on and off + + A compatibility table by model and feature is maintained on the web + site, http://acpi4asus.sf.net/. + +Usage +----- + + Try "modprobe asus_acpi". Check your dmesg (simply type dmesg). You should + see some lines like this : + + Asus Laptop Extras version 0.42 + L2D model detected. + + If it is not the output you have on your laptop, send it (and the laptop's + DSDT) to me. + + That's all, now, all the events generated by the hotkeys of your laptop + should be reported in your /proc/acpi/event entry. You can check with + "acpi_listen". + + Hotkeys are also reported as input keys (like keyboards) you can check + which key are supported using "xev" under X11. + + You can get informations on the version of your DSDT table by reading the + /sys/devices/platform/asus-laptop/infos entry. If you have a question or a + bug report to do, please include the output of this entry. + +LEDs +---- + + You can modify LEDs be echoing values to /sys/class/leds/asus::*/brightness : + echo 1 > /sys/class/leds/asus::mail/brightness + will switch the mail LED on. + You can also know if they are on/off by reading their content and use + kernel triggers like ide-disk or heartbeat. + +Backlight +--------- + + You can control lcd backlight power and brightness with + /sys/class/backlight/asus-laptop/. Brightness Values are between 0 and 15. + +Wireless devices +--------------- + + You can turn the internal Bluetooth adapter on/off with the bluetooth entry + (only on models with Bluetooth). This usually controls the associated LED. + Same for Wlan adapter. + +Display switching +----------------- + + Note: the display switching code is currently considered EXPERIMENTAL. + + Switching works for the following models: + L3800C + A2500H + L5800C + M5200N + W1000N (albeit with some glitches) + M6700R + A6JC + F3J + + Switching doesn't work for the following: + M3700N + L2X00D (locks the laptop under certain conditions) + + To switch the displays, echo values from 0 to 15 to + /sys/devices/platform/asus-laptop/display. The significance of those values + is as follows: + + +-------+-----+-----+-----+-----+-----+ + | Bin | Val | DVI | TV | CRT | LCD | + +-------+-----+-----+-----+-----+-----+ + + 0000 + 0 + + + + + + +-------+-----+-----+-----+-----+-----+ + + 0001 + 1 + + + + X + + +-------+-----+-----+-----+-----+-----+ + + 0010 + 2 + + + X + + + +-------+-----+-----+-----+-----+-----+ + + 0011 + 3 + + + X + X + + +-------+-----+-----+-----+-----+-----+ + + 0100 + 4 + + X + + + + +-------+-----+-----+-----+-----+-----+ + + 0101 + 5 + + X + + X + + +-------+-----+-----+-----+-----+-----+ + + 0110 + 6 + + X + X + + + +-------+-----+-----+-----+-----+-----+ + + 0111 + 7 + + X + X + X + + +-------+-----+-----+-----+-----+-----+ + + 1000 + 8 + X + + + + + +-------+-----+-----+-----+-----+-----+ + + 1001 + 9 + X + + + X + + +-------+-----+-----+-----+-----+-----+ + + 1010 + 10 + X + + X + + + +-------+-----+-----+-----+-----+-----+ + + 1011 + 11 + X + + X + X + + +-------+-----+-----+-----+-----+-----+ + + 1100 + 12 + X + X + + + + +-------+-----+-----+-----+-----+-----+ + + 1101 + 13 + X + X + + X + + +-------+-----+-----+-----+-----+-----+ + + 1110 + 14 + X + X + X + + + +-------+-----+-----+-----+-----+-----+ + + 1111 + 15 + X + X + X + X + + +-------+-----+-----+-----+-----+-----+ + + In most cases, the appropriate displays must be plugged in for the above + combinations to work. TV-Out may need to be initialized at boot time. + + Debugging: + 1) Check whether the Fn+F8 key: + a) does not lock the laptop (try disabling CONFIG_X86_UP_APIC or boot with + noapic / nolapic if it does) + b) generates events (0x6n, where n is the value corresponding to the + configuration above) + c) actually works + Record the disp value at every configuration. + 2) Echo values from 0 to 15 to /sys/devices/platform/asus-laptop/display. + Record its value, note any change. If nothing changes, try a broader range, + up to 65535. + 3) Send ANY output (both positive and negative reports are needed, unless your + machine is already listed above) to the acpi4asus-user mailing list. + + Note: on some machines (e.g. L3C), after the module has been loaded, only 0x6n + events are generated and no actual switching occurs. In such a case, a line + like: + + echo $((10#$arg-60)) > /sys/devices/platform/asus-laptop/display + + will usually do the trick ($arg is the 0000006n-like event passed to acpid). + + Note: there is currently no reliable way to read display status on xxN + (Centrino) models. + +LED display +----------- + + Some models like the W1N have a LED display that can be used to display + several informations. + + LED display works for the following models: + W1000N + W1J + + To control the LED display, use the following : + + echo 0x0T000DDD > /sys/devices/platform/asus-laptop/ + + where T control the 3 letters display, and DDD the 3 digits display, + according to the tables below. + + DDD (digits) + 000 to 999 = display digits + AAA = --- + BBB to FFF = turn-off + + T (type) + 0 = off + 1 = dvd + 2 = vcd + 3 = mp3 + 4 = cd + 5 = tv + 6 = cpu + 7 = vol + + For example "echo 0x01000001 >/sys/devices/platform/asus-laptop/ledd" + would display "DVD001". + +Driver options: +--------------- + + Options can be passed to the asus-laptop driver using the standard + module argument syntax (= when passing the option to the + module or asus-laptop.= on the kernel boot line when + asus-laptop is statically linked into the kernel). + + wapf: WAPF defines the behavior of the Fn+Fx wlan key + The significance of values is yet to be found, but + most of the time: + - 0x0 should do nothing + - 0x1 should allow to control the device with Fn+Fx key. + - 0x4 should send an ACPI event (0x88) while pressing the Fn+Fx key + - 0x5 like 0x1 or 0x4 + + The default value is 0x1. + +Unsupported models +------------------ + + These models will never be supported by this module, as they use a completely + different mechanism to handle LEDs and extra stuff (meaning we have no clue + how it works): + + - ASUS A1300 (A1B), A1370D + - ASUS L7300G + - ASUS L8400 + +Patches, Errors, Questions: +-------------------------- + + I appreciate any success or failure + reports, especially if they add to or correct the compatibility table. + Please include the following information in your report: + + - Asus model name + - a copy of your ACPI tables, using the "acpidump" utility + - a copy of /sys/devices/platform/asus-laptop/infos + - which driver features work and which don't + - the observed behavior of non-working features + + Any other comments or patches are also more than welcome. + + acpi4asus-user@lists.sourceforge.net + http://sourceforge.net/projects/acpi4asus + -- cgit v0.10.2 From b09f5fecf8b97c9de7add3e2eb0cfeb91ef28dbb Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Fri, 28 Aug 2009 12:56:55 +0000 Subject: asus-laptop: document sysfs interface Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/Documentation/ABI/testing/sysfs-platform-asus-laptop b/Documentation/ABI/testing/sysfs-platform-asus-laptop new file mode 100644 index 0000000..a1cb660 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-asus-laptop @@ -0,0 +1,52 @@ +What: /sys/devices/platform/asus-laptop/display +Date: January 2007 +KernelVersion: 2.6.20 +Contact: "Corentin Chary" +Description: + This file allows display switching. The value + is composed by 4 bits and defined as follow: + 4321 + |||`- LCD + ||`-- CRT + |`--- TV + `---- DVI + Ex: - 0 (0000b) means no display + - 3 (0011b) CRT+LCD. + +What: /sys/devices/platform/asus-laptop/gps +Date: January 2007 +KernelVersion: 2.6.20 +Contact: "Corentin Chary" +Description: + Control the gps device. 1 means on, 0 means off. +Users: Lapsus + +What: /sys/devices/platform/asus-laptop/ledd +Date: January 2007 +KernelVersion: 2.6.20 +Contact: "Corentin Chary" +Description: + Some models like the W1N have a LED display that can be + used to display several informations. + To control the LED display, use the following : + echo 0x0T000DDD > /sys/devices/platform/asus-laptop/ + where T control the 3 letters display, and DDD the 3 digits display. + The DDD table can be found in Documentation/laptops/asus-laptop.txt + +What: /sys/devices/platform/asus-laptop/bluetooth +Date: January 2007 +KernelVersion: 2.6.20 +Contact: "Corentin Chary" +Description: + Control the bluetooth device. 1 means on, 0 means off. + This may control the led, the device or both. +Users: Lapsus + +What: /sys/devices/platform/asus-laptop/wlan +Date: January 2007 +KernelVersion: 2.6.20 +Contact: "Corentin Chary" +Description: + Control the bluetooth device. 1 means on, 0 means off. + This may control the led, the device or both. +Users: Lapsus -- cgit v0.10.2 From aeb41b852fe90764b75ef7a9f185ca94696af6ff Mon Sep 17 00:00:00 2001 From: Len Brown Date: Fri, 28 Aug 2009 19:03:11 -0400 Subject: eeepc-laptop: whitespace for checkpatch.pl checkpatch doesn't like tab+space for a return statement. WARNING: suspect code indent for conditional statements (8, 17) + if (!device) + return -EINVAL; Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index c9febf4..819c685 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -1183,7 +1183,7 @@ static int eeepc_hotk_add(struct acpi_device *device) int result; if (!device) - return -EINVAL; + return -EINVAL; pr_notice(EEEPC_HOTK_NAME "\n"); ehotk = kzalloc(sizeof(struct eeepc_hotk), GFP_KERNEL); if (!ehotk) @@ -1265,7 +1265,7 @@ fail_platform_driver: static int eeepc_hotk_remove(struct acpi_device *device, int type) { if (!device || !acpi_driver_data(device)) - return -EINVAL; + return -EINVAL; eeepc_backlight_exit(); eeepc_rfkill_exit(); -- cgit v0.10.2 From b2deadd53c3630786e73746fb0ad8450f4e015bf Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Fri, 24 Jul 2009 10:56:43 +0800 Subject: ACPICA: Move predefined repair code to new file, no functional change New file is nsrepair.c. This is in preparation for additional errror correcting code. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/Makefile b/drivers/acpi/acpica/Makefile index 0e7d561..e7973bc 100644 --- a/drivers/acpi/acpica/Makefile +++ b/drivers/acpi/acpica/Makefile @@ -28,7 +28,7 @@ acpi-$(ACPI_FUTURE_USAGE) += hwtimer.o acpi-y += nsaccess.o nsload.o nssearch.o nsxfeval.o \ nsalloc.o nseval.o nsnames.o nsutils.o nsxfname.o \ nsdump.o nsinit.o nsobject.o nswalk.o nsxfobj.o \ - nsparse.o nspredef.o + nsparse.o nspredef.o nsrepair.o acpi-$(ACPI_FUTURE_USAGE) += nsdumpdv.o diff --git a/drivers/acpi/acpica/acnamesp.h b/drivers/acpi/acpica/acnamesp.h index a78e02f..908cfdd 100644 --- a/drivers/acpi/acpica/acnamesp.h +++ b/drivers/acpi/acpica/acnamesp.h @@ -73,6 +73,14 @@ #define ACPI_NS_WALK_UNLOCK 0x01 #define ACPI_NS_WALK_TEMP_NODES 0x02 +/* Object is not a package element */ + +#define ACPI_NOT_PACKAGE_ELEMENT ACPI_UINT32_MAX + +/* Always emit warning message, not dependent on node flags */ + +#define ACPI_WARN_ALWAYS 0 + /* * nsinit - Namespace initialization */ @@ -262,6 +270,15 @@ acpi_ns_get_attached_data(struct acpi_namespace_node *node, acpi_object_handler handler, void **data); /* + * nsrepair - return object repair for predefined methods/objects + */ +acpi_status +acpi_ns_repair_object(struct acpi_predefined_data *data, + u32 expected_btypes, + u32 package_index, + union acpi_operand_object **return_object_ptr); + +/* * nssearch - Namespace searching and entry */ acpi_status diff --git a/drivers/acpi/acpica/nspredef.c b/drivers/acpi/acpica/nspredef.c index 1dc1a47..e3f08dc 100644 --- a/drivers/acpi/acpica/nspredef.c +++ b/drivers/acpi/acpica/nspredef.c @@ -91,12 +91,6 @@ static acpi_status acpi_ns_check_reference(struct acpi_predefined_data *data, union acpi_operand_object *return_object); -static acpi_status -acpi_ns_repair_object(struct acpi_predefined_data *data, - u32 expected_btypes, - u32 package_index, - union acpi_operand_object **return_object_ptr); - static void acpi_ns_get_expected_types(char *buffer, u32 expected_btypes); /* @@ -111,14 +105,6 @@ static const char *acpi_rtype_names[] = { "/Reference", }; -/* Object is not a package element */ - -#define ACPI_NOT_PACKAGE_ELEMENT ACPI_UINT32_MAX - -/* Always emit warning message, not dependent on node flags */ - -#define ACPI_WARN_ALWAYS 0 - /******************************************************************************* * * FUNCTION: acpi_ns_check_predefined_names @@ -580,8 +566,8 @@ acpi_ns_check_package(struct acpi_predefined_data *data, case ACPI_PTYPE2_COUNT: /* - * These types all return a single package that consists of a variable - * number of sub-packages + * These types all return a single package that consists of a + * variable number of sub-packages. */ for (i = 0; i < count; i++) { sub_package = *elements; @@ -979,108 +965,6 @@ acpi_ns_check_reference(struct acpi_predefined_data *data, /******************************************************************************* * - * FUNCTION: acpi_ns_repair_object - * - * PARAMETERS: Data - Pointer to validation data structure - * expected_btypes - Object types expected - * package_index - Index of object within parent package (if - * applicable - ACPI_NOT_PACKAGE_ELEMENT - * otherwise) - * return_object_ptr - Pointer to the object returned from the - * evaluation of a method or object - * - * RETURN: Status. AE_OK if repair was successful. - * - * DESCRIPTION: Attempt to repair/convert a return object of a type that was - * not expected. - * - ******************************************************************************/ - -static acpi_status -acpi_ns_repair_object(struct acpi_predefined_data *data, - u32 expected_btypes, - u32 package_index, - union acpi_operand_object **return_object_ptr) -{ - union acpi_operand_object *return_object = *return_object_ptr; - union acpi_operand_object *new_object; - acpi_size length; - - switch (return_object->common.type) { - case ACPI_TYPE_BUFFER: - - /* Does the method/object legally return a string? */ - - if (!(expected_btypes & ACPI_RTYPE_STRING)) { - return (AE_AML_OPERAND_TYPE); - } - - /* - * Have a Buffer, expected a String, convert. Use a to_string - * conversion, no transform performed on the buffer data. The best - * example of this is the _BIF method, where the string data from - * the battery is often (incorrectly) returned as buffer object(s). - */ - length = 0; - while ((length < return_object->buffer.length) && - (return_object->buffer.pointer[length])) { - length++; - } - - /* Allocate a new string object */ - - new_object = acpi_ut_create_string_object(length); - if (!new_object) { - return (AE_NO_MEMORY); - } - - /* - * Copy the raw buffer data with no transform. String is already NULL - * terminated at Length+1. - */ - ACPI_MEMCPY(new_object->string.pointer, - return_object->buffer.pointer, length); - - /* - * If the original object is a package element, we need to: - * 1. Set the reference count of the new object to match the - * reference count of the old object. - * 2. Decrement the reference count of the original object. - */ - if (package_index != ACPI_NOT_PACKAGE_ELEMENT) { - new_object->common.reference_count = - return_object->common.reference_count; - - if (return_object->common.reference_count > 1) { - return_object->common.reference_count--; - } - - ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, - data->node_flags, - "Converted Buffer to expected String at index %u", - package_index)); - } else { - ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, - data->node_flags, - "Converted Buffer to expected String")); - } - - /* Delete old object, install the new return object */ - - acpi_ut_remove_reference(return_object); - *return_object_ptr = new_object; - data->flags |= ACPI_OBJECT_REPAIRED; - return (AE_OK); - - default: - break; - } - - return (AE_AML_OPERAND_TYPE); -} - -/******************************************************************************* - * * FUNCTION: acpi_ns_get_expected_types * * PARAMETERS: Buffer - Pointer to where the string is returned diff --git a/drivers/acpi/acpica/nsrepair.c b/drivers/acpi/acpica/nsrepair.c new file mode 100644 index 0000000..b64751e --- /dev/null +++ b/drivers/acpi/acpica/nsrepair.c @@ -0,0 +1,151 @@ +/****************************************************************************** + * + * Module Name: nsrepair - Repair for objects returned by predefined methods + * + *****************************************************************************/ + +/* + * Copyright (C) 2000 - 2009, Intel Corp. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * substantially similar to the "NO WARRANTY" disclaimer below + * ("Disclaimer") and any redistribution must be conditioned upon + * including a substantially similar Disclaimer requirement for further + * binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGES. + */ + +#include +#include "accommon.h" +#include "acnamesp.h" +#include "acpredef.h" + +#define _COMPONENT ACPI_NAMESPACE +ACPI_MODULE_NAME("nsrepair") + +/******************************************************************************* + * + * FUNCTION: acpi_ns_repair_object + * + * PARAMETERS: Data - Pointer to validation data structure + * expected_btypes - Object types expected + * package_index - Index of object within parent package (if + * applicable - ACPI_NOT_PACKAGE_ELEMENT + * otherwise) + * return_object_ptr - Pointer to the object returned from the + * evaluation of a method or object + * + * RETURN: Status. AE_OK if repair was successful. + * + * DESCRIPTION: Attempt to repair/convert a return object of a type that was + * not expected. + * + ******************************************************************************/ +acpi_status +acpi_ns_repair_object(struct acpi_predefined_data *data, + u32 expected_btypes, + u32 package_index, + union acpi_operand_object **return_object_ptr) +{ + union acpi_operand_object *return_object = *return_object_ptr; + union acpi_operand_object *new_object; + acpi_size length; + + switch (return_object->common.type) { + case ACPI_TYPE_BUFFER: + + /* Does the method/object legally return a string? */ + + if (!(expected_btypes & ACPI_RTYPE_STRING)) { + return (AE_AML_OPERAND_TYPE); + } + + /* + * Have a Buffer, expected a String, convert. Use a to_string + * conversion, no transform performed on the buffer data. The best + * example of this is the _BIF method, where the string data from + * the battery is often (incorrectly) returned as buffer object(s). + */ + length = 0; + while ((length < return_object->buffer.length) && + (return_object->buffer.pointer[length])) { + length++; + } + + /* Allocate a new string object */ + + new_object = acpi_ut_create_string_object(length); + if (!new_object) { + return (AE_NO_MEMORY); + } + + /* + * Copy the raw buffer data with no transform. String is already NULL + * terminated at Length+1. + */ + ACPI_MEMCPY(new_object->string.pointer, + return_object->buffer.pointer, length); + + /* + * If the original object is a package element, we need to: + * 1. Set the reference count of the new object to match the + * reference count of the old object. + * 2. Decrement the reference count of the original object. + */ + if (package_index != ACPI_NOT_PACKAGE_ELEMENT) { + new_object->common.reference_count = + return_object->common.reference_count; + + if (return_object->common.reference_count > 1) { + return_object->common.reference_count--; + } + + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, + data->node_flags, + "Converted Buffer to expected String at index %u", + package_index)); + } else { + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, + data->node_flags, + "Converted Buffer to expected String")); + } + + /* Delete old object, install the new return object */ + + acpi_ut_remove_reference(return_object); + *return_object_ptr = new_object; + data->flags |= ACPI_OBJECT_REPAIRED; + return (AE_OK); + + default: + break; + } + + return (AE_AML_OPERAND_TYPE); +} -- cgit v0.10.2 From e5f69d6ef7a6b0dbad8d4c00d83009960be02155 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Fri, 24 Jul 2009 11:03:09 +0800 Subject: ACPICA: Add repair for predefined methods that return nested packages Fixes a problem where a predefined method is defined to return a variable-length Package of sub-packages. If the length is one, the BIOS code occasionally creates a simple single package with no sub-packages. This code attempts to fix the problem by wrapping a new package object around the existing package. ACPICA BZ 790. http://acpica.org/bugzilla/show_bug.cgi?id=790 Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/acnamesp.h b/drivers/acpi/acpica/acnamesp.h index 908cfdd..f75a7a0 100644 --- a/drivers/acpi/acpica/acnamesp.h +++ b/drivers/acpi/acpica/acnamesp.h @@ -278,6 +278,10 @@ acpi_ns_repair_object(struct acpi_predefined_data *data, u32 package_index, union acpi_operand_object **return_object_ptr); +acpi_status +acpi_ns_repair_package_list(struct acpi_predefined_data *data, + union acpi_operand_object **obj_desc_ptr); + /* * nssearch - Namespace searching and entry */ diff --git a/drivers/acpi/acpica/nspredef.c b/drivers/acpi/acpica/nspredef.c index e3f08dc..0091504 100644 --- a/drivers/acpi/acpica/nspredef.c +++ b/drivers/acpi/acpica/nspredef.c @@ -566,9 +566,35 @@ acpi_ns_check_package(struct acpi_predefined_data *data, case ACPI_PTYPE2_COUNT: /* - * These types all return a single package that consists of a - * variable number of sub-packages. + * These types all return a single Package that consists of a + * variable number of sub-Packages. + * + * First, ensure that the first element is a sub-Package. If not, + * the BIOS may have incorrectly returned the object as a single + * package instead of a Package of Packages (a common error if + * there is only one entry). We may be able to repair this by + * wrapping the returned Package with a new outer Package. */ + if ((*elements)->common.type != ACPI_TYPE_PACKAGE) { + + /* Create the new outer package and populate it */ + + status = + acpi_ns_repair_package_list(data, + return_object_ptr); + if (ACPI_FAILURE(status)) { + return (status); + } + + /* Update locals to point to the new package (of 1 element) */ + + return_object = *return_object_ptr; + elements = return_object->package.elements; + count = 1; + } + + /* Validate each sub-Package in the parent Package */ + for (i = 0; i < count; i++) { sub_package = *elements; sub_elements = sub_package->package.elements; diff --git a/drivers/acpi/acpica/nsrepair.c b/drivers/acpi/acpica/nsrepair.c index b64751e..db2b2a9 100644 --- a/drivers/acpi/acpica/nsrepair.c +++ b/drivers/acpi/acpica/nsrepair.c @@ -149,3 +149,55 @@ acpi_ns_repair_object(struct acpi_predefined_data *data, return (AE_AML_OPERAND_TYPE); } + +/******************************************************************************* + * + * FUNCTION: acpi_ns_repair_package_list + * + * PARAMETERS: Data - Pointer to validation data structure + * obj_desc_ptr - Pointer to the object to repair. The new + * package object is returned here, + * overwriting the old object. + * + * RETURN: Status, new object in *obj_desc_ptr + * + * DESCRIPTION: Repair a common problem with objects that are defined to return + * a variable-length Package of Packages. If the variable-length + * is one, some BIOS code mistakenly simply declares a single + * Package instead of a Package with one sub-Package. This + * function attempts to repair this error by wrapping a Package + * object around the original Package, creating the correct + * Package with one sub-Package. + * + * Names that can be repaired in this manner include: + * _ALR, _CSD, _HPX, _MLS, _PRT, _PSS, _TRT, TSS + * + ******************************************************************************/ + +acpi_status +acpi_ns_repair_package_list(struct acpi_predefined_data *data, + union acpi_operand_object **obj_desc_ptr) +{ + union acpi_operand_object *pkg_obj_desc; + + /* + * Create the new outer package and populate it. The new package will + * have a single element, the lone subpackage. + */ + pkg_obj_desc = acpi_ut_create_package_object(1); + if (!pkg_obj_desc) { + return (AE_NO_MEMORY); + } + + pkg_obj_desc->package.elements[0] = *obj_desc_ptr; + + /* Return the new object in the object pointer */ + + *obj_desc_ptr = pkg_obj_desc; + data->flags |= ACPI_OBJECT_REPAIRED; + + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, data->node_flags, + "Incorrectly formed Package, attempting repair")); + + return (AE_OK); +} -- cgit v0.10.2 From 53e9387bdd8bfef6cffff2d2eb6bd28eca812682 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Fri, 24 Jul 2009 11:22:11 +0800 Subject: ACPICA: ACPI 4.0 : Add new return package type, restructure module. Added one new package type, a package that contains a revision number and a variable number of sub-packages. Restructured the module to put the sub-package list traversal in a separate function. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/acpredef.h b/drivers/acpi/acpica/acpredef.h index 63f656a..144b1f4 100644 --- a/drivers/acpi/acpica/acpredef.h +++ b/drivers/acpi/acpica/acpredef.h @@ -91,6 +91,8 @@ * ACPI_PTYPE2_MIN: Each subpackage has a variable but minimum length * (Used for _HPX) * + * ACPI_PTYPE2_REV_FIXED: Revision at start, each subpackage is Fixed-length + * *****************************************************************************/ enum acpi_return_package_types { @@ -101,7 +103,8 @@ enum acpi_return_package_types { ACPI_PTYPE2_COUNT = 5, ACPI_PTYPE2_PKG_COUNT = 6, ACPI_PTYPE2_FIXED = 7, - ACPI_PTYPE2_MIN = 8 + ACPI_PTYPE2_MIN = 8, + ACPI_PTYPE2_REV_FIXED = 9 }; /* diff --git a/drivers/acpi/acpica/nspredef.c b/drivers/acpi/acpica/nspredef.c index 0091504..0b2cdb3 100644 --- a/drivers/acpi/acpica/nspredef.c +++ b/drivers/acpi/acpica/nspredef.c @@ -76,6 +76,11 @@ acpi_ns_check_package(struct acpi_predefined_data *data, union acpi_operand_object **return_object_ptr); static acpi_status +acpi_ns_check_package_list(struct acpi_predefined_data *data, + const union acpi_predefined_info *package, + union acpi_operand_object **elements, u32 count); + +static acpi_status acpi_ns_check_package_elements(struct acpi_predefined_data *data, union acpi_operand_object **elements, u8 type1, @@ -393,14 +398,11 @@ acpi_ns_check_package(struct acpi_predefined_data *data, { union acpi_operand_object *return_object = *return_object_ptr; const union acpi_predefined_info *package; - union acpi_operand_object *sub_package; union acpi_operand_object **elements; - union acpi_operand_object **sub_elements; - acpi_status status; + acpi_status status = AE_OK; u32 expected_count; u32 count; u32 i; - u32 j; ACPI_FUNCTION_NAME(ns_check_package); @@ -465,9 +467,6 @@ acpi_ns_check_package(struct acpi_predefined_data *data, object_type2, package->ret_info. count2, 0); - if (ACPI_FAILURE(status)) { - return (status); - } break; case ACPI_PTYPE1_VAR: @@ -534,6 +533,25 @@ acpi_ns_check_package(struct acpi_predefined_data *data, } break; + case ACPI_PTYPE2_REV_FIXED: + + /* First element is the (Integer) revision */ + + status = acpi_ns_check_object_type(data, elements, + ACPI_RTYPE_INTEGER, 0); + if (ACPI_FAILURE(status)) { + return (status); + } + + elements++; + count--; + + /* Examine the sub-packages */ + + status = + acpi_ns_check_package_list(data, package, elements, count); + break; + case ACPI_PTYPE2_PKG_COUNT: /* First element is the (Integer) count of sub-packages to follow */ @@ -556,9 +574,11 @@ acpi_ns_check_package(struct acpi_predefined_data *data, count = expected_count; elements++; - /* Now we can walk the sub-packages */ + /* Examine the sub-packages */ - /*lint -fallthrough */ + status = + acpi_ns_check_package_list(data, package, elements, count); + break; case ACPI_PTYPE2: case ACPI_PTYPE2_FIXED: @@ -593,175 +613,213 @@ acpi_ns_check_package(struct acpi_predefined_data *data, count = 1; } - /* Validate each sub-Package in the parent Package */ + /* Examine the sub-packages */ - for (i = 0; i < count; i++) { - sub_package = *elements; - sub_elements = sub_package->package.elements; + status = + acpi_ns_check_package_list(data, package, elements, count); + break; - /* Each sub-object must be of type Package */ + default: - status = acpi_ns_check_object_type(data, &sub_package, - ACPI_RTYPE_PACKAGE, - i); - if (ACPI_FAILURE(status)) { - return (status); - } + /* Should not get here if predefined info table is correct */ - /* Examine the different types of sub-packages */ + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, data->node_flags, + "Invalid internal return type in table entry: %X", + package->ret_info.type)); - switch (package->ret_info.type) { - case ACPI_PTYPE2: - case ACPI_PTYPE2_PKG_COUNT: + return (AE_AML_INTERNAL); + } - /* Each subpackage has a fixed number of elements */ + return (status); - expected_count = - package->ret_info.count1 + - package->ret_info.count2; - if (sub_package->package.count != - expected_count) { - count = sub_package->package.count; - goto package_too_small; - } +package_too_small: - status = - acpi_ns_check_package_elements(data, - sub_elements, - package-> - ret_info. - object_type1, - package-> - ret_info. - count1, - package-> - ret_info. - object_type2, - package-> - ret_info. - count2, 0); - if (ACPI_FAILURE(status)) { - return (status); - } - break; + /* Error exit for the case with an incorrect package count */ - case ACPI_PTYPE2_FIXED: + ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, data->node_flags, + "Return Package is too small - found %u elements, expected %u", + count, expected_count)); - /* Each sub-package has a fixed length */ + return (AE_AML_OPERAND_VALUE); +} - expected_count = package->ret_info2.count; - if (sub_package->package.count < expected_count) { - count = sub_package->package.count; - goto package_too_small; - } +/******************************************************************************* + * + * FUNCTION: acpi_ns_check_package_list + * + * PARAMETERS: Data - Pointer to validation data structure + * Package - Pointer to package-specific info for method + * Elements - Element list of parent package. All elements + * of this list should be of type Package. + * Count - Count of subpackages + * + * RETURN: Status + * + * DESCRIPTION: Examine a list of subpackages + * + ******************************************************************************/ - /* Check the type of each sub-package element */ +static acpi_status +acpi_ns_check_package_list(struct acpi_predefined_data *data, + const union acpi_predefined_info *package, + union acpi_operand_object **elements, u32 count) +{ + union acpi_operand_object *sub_package; + union acpi_operand_object **sub_elements; + acpi_status status; + u32 expected_count; + u32 i; + u32 j; - for (j = 0; j < expected_count; j++) { - status = - acpi_ns_check_object_type(data, - &sub_elements[j], - package->ret_info2.object_type[j], j); - if (ACPI_FAILURE(status)) { - return (status); - } - } - break; + /* Validate each sub-Package in the parent Package */ - case ACPI_PTYPE2_MIN: + for (i = 0; i < count; i++) { + sub_package = *elements; + sub_elements = sub_package->package.elements; - /* Each sub-package has a variable but minimum length */ + /* Each sub-object must be of type Package */ - expected_count = package->ret_info.count1; - if (sub_package->package.count < expected_count) { - count = sub_package->package.count; - goto package_too_small; - } + status = acpi_ns_check_object_type(data, &sub_package, + ACPI_RTYPE_PACKAGE, i); + if (ACPI_FAILURE(status)) { + return (status); + } - /* Check the type of each sub-package element */ + /* Examine the different types of expected sub-packages */ - status = - acpi_ns_check_package_elements(data, - sub_elements, - package-> - ret_info. - object_type1, - sub_package-> - package. - count, 0, 0, - 0); - if (ACPI_FAILURE(status)) { - return (status); - } - break; + switch (package->ret_info.type) { + case ACPI_PTYPE2: + case ACPI_PTYPE2_PKG_COUNT: + case ACPI_PTYPE2_REV_FIXED: + + /* Each subpackage has a fixed number of elements */ + + expected_count = + package->ret_info.count1 + package->ret_info.count2; + if (sub_package->package.count < expected_count) { + goto package_too_small; + } + + status = + acpi_ns_check_package_elements(data, sub_elements, + package->ret_info. + object_type1, + package->ret_info. + count1, + package->ret_info. + object_type2, + package->ret_info. + count2, 0); + if (ACPI_FAILURE(status)) { + return (status); + } + break; + + case ACPI_PTYPE2_FIXED: + + /* Each sub-package has a fixed length */ - case ACPI_PTYPE2_COUNT: + expected_count = package->ret_info2.count; + if (sub_package->package.count < expected_count) { + goto package_too_small; + } - /* First element is the (Integer) count of elements to follow */ + /* Check the type of each sub-package element */ + for (j = 0; j < expected_count; j++) { status = acpi_ns_check_object_type(data, - sub_elements, - ACPI_RTYPE_INTEGER, - 0); + &sub_elements[j], + package-> + ret_info2. + object_type[j], + j); if (ACPI_FAILURE(status)) { return (status); } + } + break; - /* Make sure package is large enough for the Count */ + case ACPI_PTYPE2_MIN: - expected_count = - (u32) (*sub_elements)->integer.value; - if (sub_package->package.count < expected_count) { - count = sub_package->package.count; - goto package_too_small; - } + /* Each sub-package has a variable but minimum length */ - /* Check the type of each sub-package element */ + expected_count = package->ret_info.count1; + if (sub_package->package.count < expected_count) { + goto package_too_small; + } - status = - acpi_ns_check_package_elements(data, - (sub_elements - + 1), - package-> - ret_info. - object_type1, - (expected_count - - 1), 0, 0, - 1); - if (ACPI_FAILURE(status)) { - return (status); - } - break; + /* Check the type of each sub-package element */ - default: - break; + status = + acpi_ns_check_package_elements(data, sub_elements, + package->ret_info. + object_type1, + sub_package->package. + count, 0, 0, 0); + if (ACPI_FAILURE(status)) { + return (status); } + break; - elements++; - } - break; + case ACPI_PTYPE2_COUNT: - default: + /* + * First element is the (Integer) count of elements, including + * the count field. + */ + status = acpi_ns_check_object_type(data, sub_elements, + ACPI_RTYPE_INTEGER, + 0); + if (ACPI_FAILURE(status)) { + return (status); + } - /* Should not get here if predefined info table is correct */ + /* + * Make sure package is large enough for the Count and is + * is as large as the minimum size + */ + expected_count = (u32)(*sub_elements)->integer.value; + if (sub_package->package.count < expected_count) { + goto package_too_small; + } + if (sub_package->package.count < + package->ret_info.count1) { + expected_count = package->ret_info.count1; + goto package_too_small; + } - ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, data->node_flags, - "Invalid internal return type in table entry: %X", - package->ret_info.type)); + /* Check the type of each sub-package element */ - return (AE_AML_INTERNAL); + status = + acpi_ns_check_package_elements(data, + (sub_elements + 1), + package->ret_info. + object_type1, + (expected_count - 1), + 0, 0, 1); + if (ACPI_FAILURE(status)) { + return (status); + } + break; + + default: /* Should not get here, type was validated by caller */ + + return (AE_AML_INTERNAL); + } + + elements++; } return (AE_OK); - package_too_small: +package_too_small: - /* Error exit for the case with an incorrect package count */ + /* The sub-package count was smaller than required */ ACPI_WARN_PREDEFINED((AE_INFO, data->pathname, data->node_flags, - "Return Package is too small - found %u, expected %u", - count, expected_count)); + "Return Sub-Package[%u] is too small - found %u elements, expected %u", + i, sub_package->package.count, expected_count)); return (AE_AML_OPERAND_VALUE); } -- cgit v0.10.2 From 2f977b36e5f175e5126f280e7a94f0c53d1b1a16 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Fri, 24 Jul 2009 11:25:16 +0800 Subject: ACPICA: Fix fault if acpi_terminate is called twice Fixes a problem with the mechanism that prevents problems if the acpi_terminate interface is inadvertently called more than once before the ACPICA code is re-initialized. ACPICA BZ 795. http://acpica.org/bugzilla/show_bug.cgi?id=795 Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/utinit.c b/drivers/acpi/acpica/utinit.c index a54ca84..9d0919eb 100644 --- a/drivers/acpi/acpica/utinit.c +++ b/drivers/acpi/acpica/utinit.c @@ -99,33 +99,19 @@ static void acpi_ut_terminate(void) * * FUNCTION: acpi_ut_subsystem_shutdown * - * PARAMETERS: none + * PARAMETERS: None * - * RETURN: none + * RETURN: None * - * DESCRIPTION: Shutdown the various subsystems. Don't delete the mutex - * objects here -- because the AML debugger may be still running. + * DESCRIPTION: Shutdown the various components. Do not delete the mutex + * objects here, because the AML debugger may be still running. * ******************************************************************************/ void acpi_ut_subsystem_shutdown(void) { - ACPI_FUNCTION_TRACE(ut_subsystem_shutdown); - /* Just exit if subsystem is already shutdown */ - - if (acpi_gbl_shutdown) { - ACPI_ERROR((AE_INFO, "ACPI Subsystem is already terminated")); - return_VOID; - } - - /* Subsystem appears active, go ahead and shut it down */ - - acpi_gbl_shutdown = TRUE; - acpi_gbl_startup_flags = 0; - ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Shutting down ACPI Subsystem\n")); - #ifndef ACPI_ASL_COMPILER /* Close the acpi_event Handling */ diff --git a/drivers/acpi/acpica/utxface.c b/drivers/acpi/acpica/utxface.c index 078a2272..483edbb 100644 --- a/drivers/acpi/acpica/utxface.c +++ b/drivers/acpi/acpica/utxface.c @@ -318,7 +318,7 @@ ACPI_EXPORT_SYMBOL(acpi_initialize_objects) * * RETURN: Status * - * DESCRIPTION: Shutdown the ACPI subsystem. Release all resources. + * DESCRIPTION: Shutdown the ACPICA subsystem and release all resources. * ******************************************************************************/ acpi_status acpi_terminate(void) @@ -327,6 +327,19 @@ acpi_status acpi_terminate(void) ACPI_FUNCTION_TRACE(acpi_terminate); + /* Just exit if subsystem is already shutdown */ + + if (acpi_gbl_shutdown) { + ACPI_ERROR((AE_INFO, "ACPI Subsystem is already terminated")); + return_ACPI_STATUS(AE_OK); + } + + /* Subsystem appears active, go ahead and shut it down */ + + acpi_gbl_shutdown = TRUE; + acpi_gbl_startup_flags = 0; + ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Shutting down ACPI Subsystem\n")); + /* Terminate the AML Debugger if present */ ACPI_DEBUGGER_EXEC(acpi_gbl_db_terminate_threads = TRUE); @@ -353,6 +366,7 @@ acpi_status acpi_terminate(void) } ACPI_EXPORT_SYMBOL(acpi_terminate) + #ifndef ACPI_ASL_COMPILER #ifdef ACPI_FUTURE_USAGE /******************************************************************************* -- cgit v0.10.2 From b24aad44438d5bc21cbbfb94a99d9bf710d8295b Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Fri, 24 Jul 2009 13:30:17 +0800 Subject: ACPICA: Split large ACPI table header Split out the non-acpi-defined ACPI tables into the existing (but empty) actbl2.h file. Preparation for new ACPI 4.0 tables. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/include/acpi/actbl.h b/include/acpi/actbl.h index 0649a56..55fcfc6 100644 --- a/include/acpi/actbl.h +++ b/include/acpi/actbl.h @@ -44,6 +44,19 @@ #ifndef __ACTBL_H__ #define __ACTBL_H__ +/******************************************************************************* + * + * Fundamental ACPI tables + * + * This file contains definitions for the ACPI tables that are directly consumed + * by ACPICA. All other tables are consumed by the OS-dependent ACPI-related + * device drivers and other OS support code. + * + * The RSDP and FACS do not use the common ACPI table header. All other ACPI + * tables use the header. + * + ******************************************************************************/ + /* * Values for description table header signatures. Useful because they make * it more difficult to inadvertently type in the wrong signature. @@ -65,11 +78,6 @@ #pragma pack(1) /* - * These are the ACPI tables that are directly consumed by the subsystem. - * - * The RSDP and FACS do not use the common ACPI table header. All other ACPI - * tables use the header. - * * Note about bitfields: The u8 type is used for bitfields in ACPI tables. * This is the only type that is even remotely portable. Anything else is not * portable, so do not use any other bitfield types. @@ -77,9 +85,8 @@ /******************************************************************************* * - * ACPI Table Header. This common header is used by all tables except the - * RSDP and FACS. The define is used for direct inclusion of header into - * other ACPI tables + * Master ACPI Table Header. This common header is used by all ACPI tables + * except the RSDP and FACS. * ******************************************************************************/ @@ -95,13 +102,16 @@ struct acpi_table_header { u32 asl_compiler_revision; /* ASL compiler version */ }; -/* +/******************************************************************************* + * * GAS - Generic Address Structure (ACPI 2.0+) * * Note: Since this structure is used in the ACPI tables, it is byte aligned. - * If misalignment is not supported, access to the Address field must be - * performed with care. - */ + * If misaliged access is not supported by the hardware, accesses to the + * 64-bit Address field must be performed with care. + * + ******************************************************************************/ + struct acpi_generic_address { u8 space_id; /* Address space where struct or register exists */ u8 bit_width; /* Size in bits of given register */ @@ -325,5 +335,6 @@ struct acpi_table_desc { */ #include +#include #endif /* __ACTBL_H__ */ diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index ec36693..582af1f 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -46,41 +46,29 @@ /******************************************************************************* * - * Additional ACPI Tables + * Additional ACPI Tables (1) * * These tables are not consumed directly by the ACPICA subsystem, but are * included here to support device drivers and the AML disassembler. * + * The tables in this file are fully defined within the ACPI specification. + * ******************************************************************************/ /* * Values for description table header signatures. Useful because they make * it more difficult to inadvertently type in the wrong signature. */ -#define ACPI_SIG_ASF "ASF!" /* Alert Standard Format table */ #define ACPI_SIG_BERT "BERT" /* Boot Error Record Table */ -#define ACPI_SIG_BOOT "BOOT" /* Simple Boot Flag Table */ #define ACPI_SIG_CPEP "CPEP" /* Corrected Platform Error Polling table */ -#define ACPI_SIG_DBGP "DBGP" /* Debug Port table */ -#define ACPI_SIG_DMAR "DMAR" /* DMA Remapping table */ #define ACPI_SIG_ECDT "ECDT" /* Embedded Controller Boot Resources Table */ #define ACPI_SIG_EINJ "EINJ" /* Error Injection table */ #define ACPI_SIG_ERST "ERST" /* Error Record Serialization Table */ #define ACPI_SIG_HEST "HEST" /* Hardware Error Source Table */ -#define ACPI_SIG_HPET "HPET" /* High Precision Event Timer table */ -#define ACPI_SIG_IBFT "IBFT" /* i_sCSI Boot Firmware Table */ #define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */ -#define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */ #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */ -#define ACPI_SIG_SLIC "SLIC" /* Software Licensing Description Table */ #define ACPI_SIG_SLIT "SLIT" /* System Locality Distance Information Table */ -#define ACPI_SIG_SPCR "SPCR" /* Serial Port Console Redirection table */ -#define ACPI_SIG_SPMI "SPMI" /* Server Platform Management Interface table */ #define ACPI_SIG_SRAT "SRAT" /* System Resource Affinity Table */ -#define ACPI_SIG_TCPA "TCPA" /* Trusted Computing Platform Alliance table */ -#define ACPI_SIG_UEFI "UEFI" /* Uefi Boot Optimization Table */ -#define ACPI_SIG_WDAT "WDAT" /* Watchdog Action Table */ -#define ACPI_SIG_WDRT "WDRT" /* Watchdog Resource Table */ /* * All tables must be byte-packed to match the ACPI specification, since @@ -115,115 +103,6 @@ struct acpi_whea_header { /******************************************************************************* * - * ASF - Alert Standard Format table (Signature "ASF!") - * - * Conforms to the Alert Standard Format Specification V2.0, 23 April 2003 - * - ******************************************************************************/ - -struct acpi_table_asf { - struct acpi_table_header header; /* Common ACPI table header */ -}; - -/* ASF subtable header */ - -struct acpi_asf_header { - u8 type; - u8 reserved; - u16 length; -}; - -/* Values for Type field above */ - -enum acpi_asf_type { - ACPI_ASF_TYPE_INFO = 0, - ACPI_ASF_TYPE_ALERT = 1, - ACPI_ASF_TYPE_CONTROL = 2, - ACPI_ASF_TYPE_BOOT = 3, - ACPI_ASF_TYPE_ADDRESS = 4, - ACPI_ASF_TYPE_RESERVED = 5 -}; - -/* - * ASF subtables - */ - -/* 0: ASF Information */ - -struct acpi_asf_info { - struct acpi_asf_header header; - u8 min_reset_value; - u8 min_poll_interval; - u16 system_id; - u32 mfg_id; - u8 flags; - u8 reserved2[3]; -}; - -/* 1: ASF Alerts */ - -struct acpi_asf_alert { - struct acpi_asf_header header; - u8 assert_mask; - u8 deassert_mask; - u8 alerts; - u8 data_length; -}; - -struct acpi_asf_alert_data { - u8 address; - u8 command; - u8 mask; - u8 value; - u8 sensor_type; - u8 type; - u8 offset; - u8 source_type; - u8 severity; - u8 sensor_number; - u8 entity; - u8 instance; -}; - -/* 2: ASF Remote Control */ - -struct acpi_asf_remote { - struct acpi_asf_header header; - u8 controls; - u8 data_length; - u16 reserved2; -}; - -struct acpi_asf_control_data { - u8 function; - u8 address; - u8 command; - u8 value; -}; - -/* 3: ASF RMCP Boot Options */ - -struct acpi_asf_rmcp { - struct acpi_asf_header header; - u8 capabilities[7]; - u8 completion_code; - u32 enterprise_id; - u8 command; - u16 parameter; - u16 boot_options; - u16 oem_parameters; -}; - -/* 4: ASF Address */ - -struct acpi_asf_address { - struct acpi_asf_header header; - u8 eprom_address; - u8 devices; -}; - -/******************************************************************************* - * * BERT - Boot Error Record Table * ******************************************************************************/ @@ -253,18 +132,6 @@ struct acpi_bert_region { /******************************************************************************* * - * BOOT - Simple Boot Flag Table - * - ******************************************************************************/ - -struct acpi_table_boot { - struct acpi_table_header header; /* Common ACPI table header */ - u8 cmos_index; /* Index in CMOS RAM for the boot register */ - u8 reserved[3]; -}; - -/******************************************************************************* - * * CPEP - Corrected Platform Error Polling table * ******************************************************************************/ @@ -286,123 +153,6 @@ struct acpi_cpep_polling { /******************************************************************************* * - * DBGP - Debug Port table - * - ******************************************************************************/ - -struct acpi_table_dbgp { - struct acpi_table_header header; /* Common ACPI table header */ - u8 type; /* 0=full 16550, 1=subset of 16550 */ - u8 reserved[3]; - struct acpi_generic_address debug_port; -}; - -/******************************************************************************* - * - * DMAR - DMA Remapping table - * From "Intel Virtualization Technology for Directed I/O", Sept. 2007 - * - ******************************************************************************/ - -struct acpi_table_dmar { - struct acpi_table_header header; /* Common ACPI table header */ - u8 width; /* Host Address Width */ - u8 flags; - u8 reserved[10]; -}; - -/* Flags */ - -#define ACPI_DMAR_INTR_REMAP (1) - -/* DMAR subtable header */ - -struct acpi_dmar_header { - u16 type; - u16 length; -}; - -/* Values for subtable type in struct acpi_dmar_header */ - -enum acpi_dmar_type { - ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, - ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, - ACPI_DMAR_TYPE_ATSR = 2, - ACPI_DMAR_TYPE_RESERVED = 3 /* 3 and greater are reserved */ -}; - -struct acpi_dmar_device_scope { - u8 entry_type; - u8 length; - u16 reserved; - u8 enumeration_id; - u8 bus; -}; - -/* Values for entry_type in struct acpi_dmar_device_scope */ - -enum acpi_dmar_scope_type { - ACPI_DMAR_SCOPE_TYPE_NOT_USED = 0, - ACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1, - ACPI_DMAR_SCOPE_TYPE_BRIDGE = 2, - ACPI_DMAR_SCOPE_TYPE_IOAPIC = 3, - ACPI_DMAR_SCOPE_TYPE_HPET = 4, - ACPI_DMAR_SCOPE_TYPE_RESERVED = 5 /* 5 and greater are reserved */ -}; - -struct acpi_dmar_pci_path { - u8 dev; - u8 fn; -}; - -/* - * DMAR Sub-tables, correspond to Type in struct acpi_dmar_header - */ - -/* 0: Hardware Unit Definition */ - -struct acpi_dmar_hardware_unit { - struct acpi_dmar_header header; - u8 flags; - u8 reserved; - u16 segment; - u64 address; /* Register Base Address */ -}; - -/* Flags */ - -#define ACPI_DMAR_INCLUDE_ALL (1) - -/* 1: Reserved Memory Defininition */ - -struct acpi_dmar_reserved_memory { - struct acpi_dmar_header header; - u16 reserved; - u16 segment; - u64 base_address; /* 4_k aligned base address */ - u64 end_address; /* 4_k aligned limit address */ -}; - -/* Flags */ - -#define ACPI_DMAR_ALLOW_ALL (1) - - -/* 2: Root Port ATS Capability Reporting Structure */ - -struct acpi_dmar_atsr { - struct acpi_dmar_header header; - u8 flags; - u8 reserved; - u16 segment; -}; - -/* Flags */ - -#define ACPI_DMAR_ALL_PORTS (1) - -/******************************************************************************* - * * ECDT - Embedded Controller Boot Resources Table * ******************************************************************************/ @@ -764,119 +514,6 @@ struct acpi_hest_generic { /******************************************************************************* * - * HPET - High Precision Event Timer table - * - ******************************************************************************/ - -struct acpi_table_hpet { - struct acpi_table_header header; /* Common ACPI table header */ - u32 id; /* Hardware ID of event timer block */ - struct acpi_generic_address address; /* Address of event timer block */ - u8 sequence; /* HPET sequence number */ - u16 minimum_tick; /* Main counter min tick, periodic mode */ - u8 flags; -}; - -/*! Flags */ - -#define ACPI_HPET_PAGE_PROTECT (1) /* 00: No page protection */ -#define ACPI_HPET_PAGE_PROTECT_4 (1<<1) /* 01: 4KB page protected */ -#define ACPI_HPET_PAGE_PROTECT_64 (1<<2) /* 02: 64KB page protected */ - -/*! [End] no source code translation !*/ - -/******************************************************************************* - * - * IBFT - Boot Firmware Table - * - ******************************************************************************/ - -struct acpi_table_ibft { - struct acpi_table_header header; /* Common ACPI table header */ - u8 reserved[12]; -}; - -/* IBFT common subtable header */ - -struct acpi_ibft_header { - u8 type; - u8 version; - u16 length; - u8 index; - u8 flags; -}; - -/* Values for Type field above */ - -enum acpi_ibft_type { - ACPI_IBFT_TYPE_NOT_USED = 0, - ACPI_IBFT_TYPE_CONTROL = 1, - ACPI_IBFT_TYPE_INITIATOR = 2, - ACPI_IBFT_TYPE_NIC = 3, - ACPI_IBFT_TYPE_TARGET = 4, - ACPI_IBFT_TYPE_EXTENSIONS = 5, - ACPI_IBFT_TYPE_RESERVED = 6 /* 6 and greater are reserved */ -}; - -/* IBFT subtables */ - -struct acpi_ibft_control { - struct acpi_ibft_header header; - u16 extensions; - u16 initiator_offset; - u16 nic0_offset; - u16 target0_offset; - u16 nic1_offset; - u16 target1_offset; -}; - -struct acpi_ibft_initiator { - struct acpi_ibft_header header; - u8 sns_server[16]; - u8 slp_server[16]; - u8 primary_server[16]; - u8 secondary_server[16]; - u16 name_length; - u16 name_offset; -}; - -struct acpi_ibft_nic { - struct acpi_ibft_header header; - u8 ip_address[16]; - u8 subnet_mask_prefix; - u8 origin; - u8 gateway[16]; - u8 primary_dns[16]; - u8 secondary_dns[16]; - u8 dhcp[16]; - u16 vlan; - u8 mac_address[6]; - u16 pci_address; - u16 name_length; - u16 name_offset; -}; - -struct acpi_ibft_target { - struct acpi_ibft_header header; - u8 target_ip_address[16]; - u16 target_ip_socket; - u8 target_boot_lun[8]; - u8 chap_type; - u8 nic_association; - u16 target_name_length; - u16 target_name_offset; - u16 chap_name_length; - u16 chap_name_offset; - u16 chap_secret_length; - u16 chap_secret_offset; - u16 reverse_chap_name_length; - u16 reverse_chap_name_offset; - u16 reverse_chap_secret_length; - u16 reverse_chap_secret_offset; -}; - -/******************************************************************************* - * * MADT - Multiple APIC Description Table * ******************************************************************************/ @@ -1058,27 +695,6 @@ struct acpi_madt_local_x2apic_nmi { /******************************************************************************* * - * MCFG - PCI Memory Mapped Configuration table and sub-table - * - ******************************************************************************/ - -struct acpi_table_mcfg { - struct acpi_table_header header; /* Common ACPI table header */ - u8 reserved[8]; -}; - -/* Subtable */ - -struct acpi_mcfg_allocation { - u64 address; /* Base address, processor-relative */ - u16 pci_segment; /* PCI segment group number */ - u8 start_bus_number; /* Starting PCI Bus number */ - u8 end_bus_number; /* Final PCI Bus number */ - u32 reserved; -}; - -/******************************************************************************* - * * SBST - Smart Battery Specification Table * ******************************************************************************/ @@ -1104,59 +720,6 @@ struct acpi_table_slit { /******************************************************************************* * - * SPCR - Serial Port Console Redirection table - * - ******************************************************************************/ - -struct acpi_table_spcr { - struct acpi_table_header header; /* Common ACPI table header */ - u8 interface_type; /* 0=full 16550, 1=subset of 16550 */ - u8 reserved[3]; - struct acpi_generic_address serial_port; - u8 interrupt_type; - u8 pc_interrupt; - u32 interrupt; - u8 baud_rate; - u8 parity; - u8 stop_bits; - u8 flow_control; - u8 terminal_type; - u8 reserved1; - u16 pci_device_id; - u16 pci_vendor_id; - u8 pci_bus; - u8 pci_device; - u8 pci_function; - u32 pci_flags; - u8 pci_segment; - u32 reserved2; -}; - -/******************************************************************************* - * - * SPMI - Server Platform Management Interface table - * - ******************************************************************************/ - -struct acpi_table_spmi { - struct acpi_table_header header; /* Common ACPI table header */ - u8 reserved; - u8 interface_type; - u16 spec_revision; /* Version of IPMI */ - u8 interrupt_type; - u8 gpe_number; /* GPE assigned */ - u8 reserved1; - u8 pci_device_flag; - u32 interrupt; - struct acpi_generic_address ipmi_register; - u8 pci_segment; - u8 pci_bus; - u8 pci_device; - u8 pci_function; -}; - -/******************************************************************************* - * * SRAT - System Resource Affinity Table * ******************************************************************************/ @@ -1227,116 +790,6 @@ struct acpi_srat_x2apic_cpu_affinity { #define ACPI_SRAT_CPU_ENABLED (1) /* 00: Use affinity structure */ -/******************************************************************************* - * - * TCPA - Trusted Computing Platform Alliance table - * - ******************************************************************************/ - -struct acpi_table_tcpa { - struct acpi_table_header header; /* Common ACPI table header */ - u16 reserved; - u32 max_log_length; /* Maximum length for the event log area */ - u64 log_address; /* Address of the event log area */ -}; - -/******************************************************************************* - * - * UEFI - UEFI Boot optimization Table - * - ******************************************************************************/ - -struct acpi_table_uefi { - struct acpi_table_header header; /* Common ACPI table header */ - u8 identifier[16]; /* UUID identifier */ - u16 data_offset; /* Offset of remaining data in table */ - u8 data; -}; - -/******************************************************************************* - * - * WDAT - Watchdog Action Table - * - ******************************************************************************/ - -struct acpi_table_wdat { - struct acpi_table_header header; /* Common ACPI table header */ - u32 header_length; /* Watchdog Header Length */ - u16 pci_segment; /* PCI Segment number */ - u8 pci_bus; /* PCI Bus number */ - u8 pci_device; /* PCI Device number */ - u8 pci_function; /* PCI Function number */ - u8 reserved[3]; - u32 timer_period; /* Period of one timer count (msec) */ - u32 max_count; /* Maximum counter value supported */ - u32 min_count; /* Minimum counter value */ - u8 flags; - u8 reserved2[3]; - u32 entries; /* Number of watchdog entries that follow */ -}; - -/* WDAT Instruction Entries (actions) */ - -struct acpi_wdat_entry { - struct acpi_whea_header whea_header; /* Common header for WHEA tables */ -}; - -/* Values for Action field above */ - -enum acpi_wdat_actions { - ACPI_WDAT_RESET = 1, - ACPI_WDAT_GET_CURRENT_COUNTDOWN = 4, - ACPI_WDAT_GET_COUNTDOWN = 5, - ACPI_WDAT_SET_COUNTDOWN = 6, - ACPI_WDAT_GET_RUNNING_STATE = 8, - ACPI_WDAT_SET_RUNNING_STATE = 9, - ACPI_WDAT_GET_STOPPED_STATE = 10, - ACPI_WDAT_SET_STOPPED_STATE = 11, - ACPI_WDAT_GET_REBOOT = 16, - ACPI_WDAT_SET_REBOOT = 17, - ACPI_WDAT_GET_SHUTDOWN = 18, - ACPI_WDAT_SET_SHUTDOWN = 19, - ACPI_WDAT_GET_STATUS = 32, - ACPI_WDAT_SET_STATUS = 33, - ACPI_WDAT_ACTION_RESERVED = 34 /* 34 and greater are reserved */ -}; - -/* Values for Instruction field above */ - -enum acpi_wdat_instructions { - ACPI_WDAT_READ_VALUE = 0, - ACPI_WDAT_READ_COUNTDOWN = 1, - ACPI_WDAT_WRITE_VALUE = 2, - ACPI_WDAT_WRITE_COUNTDOWN = 3, - ACPI_WDAT_INSTRUCTION_RESERVED = 4, /* 4 and greater are reserved */ - ACPI_WDAT_PRESERVE_REGISTER = 0x80 /* Except for this value */ -}; - -/******************************************************************************* - * - * WDRT - Watchdog Resource Table - * - ******************************************************************************/ - -struct acpi_table_wdrt { - struct acpi_table_header header; /* Common ACPI table header */ - u32 header_length; /* Watchdog Header Length */ - u8 pci_segment; /* PCI Segment number */ - u8 pci_bus; /* PCI Bus number */ - u8 pci_device; /* PCI Device number */ - u8 pci_function; /* PCI Function number */ - u32 timer_period; /* Period of one timer count (msec) */ - u32 max_count; /* Maximum counter value supported */ - u32 min_count; /* Minimum counter value */ - u8 flags; - u8 reserved[3]; - u32 entries; /* Number of watchdog entries that follow */ -}; - -/* Flags */ - -#define ACPI_WDRT_TIMER_ENABLED (1) /* 00: Timer enabled */ - /* Reset to default packing */ #pragma pack() diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h new file mode 100644 index 0000000..b271aba --- /dev/null +++ b/include/acpi/actbl2.h @@ -0,0 +1,585 @@ +#ifndef __ACTBL2_H__ +#define __ACTBL2_H__ + +/******************************************************************************* + * + * Additional ACPI Tables (2) + * + * These tables are not consumed directly by the ACPICA subsystem, but are + * included here to support device drivers and the AML disassembler. + * + * The tables in this file are defined by third-party specifications, and are + * not defined directly by the ACPI specification itself. + * + ******************************************************************************/ + +/* + * Values for description table header signatures. Useful because they make + * it more difficult to inadvertently type in the wrong signature. + */ +#define ACPI_SIG_ASF "ASF!" /* Alert Standard Format table */ +#define ACPI_SIG_BOOT "BOOT" /* Simple Boot Flag Table */ +#define ACPI_SIG_DBGP "DBGP" /* Debug Port table */ +#define ACPI_SIG_DMAR "DMAR" /* DMA Remapping table */ +#define ACPI_SIG_HPET "HPET" /* High Precision Event Timer table */ +#define ACPI_SIG_IBFT "IBFT" /* i_sCSI Boot Firmware Table */ +#define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */ +#define ACPI_SIG_SLIC "SLIC" /* Software Licensing Description Table */ +#define ACPI_SIG_SPCR "SPCR" /* Serial Port Console Redirection table */ +#define ACPI_SIG_SPMI "SPMI" /* Server Platform Management Interface table */ +#define ACPI_SIG_TCPA "TCPA" /* Trusted Computing Platform Alliance table */ +#define ACPI_SIG_UEFI "UEFI" /* Uefi Boot Optimization Table */ +#define ACPI_SIG_WDAT "WDAT" /* Watchdog Action Table */ +#define ACPI_SIG_WDRT "WDRT" /* Watchdog Resource Table */ + +/* + * All tables must be byte-packed to match the ACPI specification, since + * the tables are provided by the system BIOS. + */ +#pragma pack(1) + +/* + * Note about bitfields: The u8 type is used for bitfields in ACPI tables. + * This is the only type that is even remotely portable. Anything else is not + * portable, so do not use any other bitfield types. + */ + +/******************************************************************************* + * + * ASF - Alert Standard Format table (Signature "ASF!") + * + * Conforms to the Alert Standard Format Specification V2.0, 23 April 2003 + * + ******************************************************************************/ + +struct acpi_table_asf { + struct acpi_table_header header; /* Common ACPI table header */ +}; + +/* ASF subtable header */ + +struct acpi_asf_header { + u8 type; + u8 reserved; + u16 length; +}; + +/* Values for Type field above */ + +enum acpi_asf_type { + ACPI_ASF_TYPE_INFO = 0, + ACPI_ASF_TYPE_ALERT = 1, + ACPI_ASF_TYPE_CONTROL = 2, + ACPI_ASF_TYPE_BOOT = 3, + ACPI_ASF_TYPE_ADDRESS = 4, + ACPI_ASF_TYPE_RESERVED = 5 +}; + +/* + * ASF subtables + */ + +/* 0: ASF Information */ + +struct acpi_asf_info { + struct acpi_asf_header header; + u8 min_reset_value; + u8 min_poll_interval; + u16 system_id; + u32 mfg_id; + u8 flags; + u8 reserved2[3]; +}; + +/* 1: ASF Alerts */ + +struct acpi_asf_alert { + struct acpi_asf_header header; + u8 assert_mask; + u8 deassert_mask; + u8 alerts; + u8 data_length; +}; + +struct acpi_asf_alert_data { + u8 address; + u8 command; + u8 mask; + u8 value; + u8 sensor_type; + u8 type; + u8 offset; + u8 source_type; + u8 severity; + u8 sensor_number; + u8 entity; + u8 instance; +}; + +/* 2: ASF Remote Control */ + +struct acpi_asf_remote { + struct acpi_asf_header header; + u8 controls; + u8 data_length; + u16 reserved2; +}; + +struct acpi_asf_control_data { + u8 function; + u8 address; + u8 command; + u8 value; +}; + +/* 3: ASF RMCP Boot Options */ + +struct acpi_asf_rmcp { + struct acpi_asf_header header; + u8 capabilities[7]; + u8 completion_code; + u32 enterprise_id; + u8 command; + u16 parameter; + u16 boot_options; + u16 oem_parameters; +}; + +/* 4: ASF Address */ + +struct acpi_asf_address { + struct acpi_asf_header header; + u8 eprom_address; + u8 devices; +}; + +/******************************************************************************* + * + * BOOT - Simple Boot Flag Table + * + ******************************************************************************/ + +struct acpi_table_boot { + struct acpi_table_header header; /* Common ACPI table header */ + u8 cmos_index; /* Index in CMOS RAM for the boot register */ + u8 reserved[3]; +}; + +/******************************************************************************* + * + * DBGP - Debug Port table + * + ******************************************************************************/ + +struct acpi_table_dbgp { + struct acpi_table_header header; /* Common ACPI table header */ + u8 type; /* 0=full 16550, 1=subset of 16550 */ + u8 reserved[3]; + struct acpi_generic_address debug_port; +}; + +/******************************************************************************* + * + * DMAR - DMA Remapping table + * From "Intel Virtualization Technology for Directed I/O", Sept. 2007 + * + ******************************************************************************/ + +struct acpi_table_dmar { + struct acpi_table_header header; /* Common ACPI table header */ + u8 width; /* Host Address Width */ + u8 flags; + u8 reserved[10]; +}; + +/* Flags */ + +#define ACPI_DMAR_INTR_REMAP (1) + +/* DMAR subtable header */ + +struct acpi_dmar_header { + u16 type; + u16 length; +}; + +/* Values for subtable type in struct acpi_dmar_header */ + +enum acpi_dmar_type { + ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, + ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, + ACPI_DMAR_TYPE_ATSR = 2, + ACPI_DMAR_TYPE_RESERVED = 3 /* 3 and greater are reserved */ +}; + +struct acpi_dmar_device_scope { + u8 entry_type; + u8 length; + u16 reserved; + u8 enumeration_id; + u8 bus; +}; + +/* Values for entry_type in struct acpi_dmar_device_scope */ + +enum acpi_dmar_scope_type { + ACPI_DMAR_SCOPE_TYPE_NOT_USED = 0, + ACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1, + ACPI_DMAR_SCOPE_TYPE_BRIDGE = 2, + ACPI_DMAR_SCOPE_TYPE_IOAPIC = 3, + ACPI_DMAR_SCOPE_TYPE_HPET = 4, + ACPI_DMAR_SCOPE_TYPE_RESERVED = 5 /* 5 and greater are reserved */ +}; + +struct acpi_dmar_pci_path { + u8 dev; + u8 fn; +}; + +/* + * DMAR Sub-tables, correspond to Type in struct acpi_dmar_header + */ + +/* 0: Hardware Unit Definition */ + +struct acpi_dmar_hardware_unit { + struct acpi_dmar_header header; + u8 flags; + u8 reserved; + u16 segment; + u64 address; /* Register Base Address */ +}; + +/* Flags */ + +#define ACPI_DMAR_INCLUDE_ALL (1) + +/* 1: Reserved Memory Defininition */ + +struct acpi_dmar_reserved_memory { + struct acpi_dmar_header header; + u16 reserved; + u16 segment; + u64 base_address; /* 4_k aligned base address */ + u64 end_address; /* 4_k aligned limit address */ +}; + +/* Flags */ + +#define ACPI_DMAR_ALLOW_ALL (1) + +/* 2: Root Port ATS Capability Reporting Structure */ + +struct acpi_dmar_atsr { + struct acpi_dmar_header header; + u8 flags; + u8 reserved; + u16 segment; +}; + +/* Flags */ + +#define ACPI_DMAR_ALL_PORTS (1) + +/******************************************************************************* + * + * HPET - High Precision Event Timer table + * + ******************************************************************************/ + +struct acpi_table_hpet { + struct acpi_table_header header; /* Common ACPI table header */ + u32 id; /* Hardware ID of event timer block */ + struct acpi_generic_address address; /* Address of event timer block */ + u8 sequence; /* HPET sequence number */ + u16 minimum_tick; /* Main counter min tick, periodic mode */ + u8 flags; +}; + +/*! Flags */ + +#define ACPI_HPET_PAGE_PROTECT (1) /* 00: No page protection */ +#define ACPI_HPET_PAGE_PROTECT_4 (1<<1) /* 01: 4KB page protected */ +#define ACPI_HPET_PAGE_PROTECT_64 (1<<2) /* 02: 64KB page protected */ + +/*! [End] no source code translation !*/ + +/******************************************************************************* + * + * IBFT - Boot Firmware Table + * + ******************************************************************************/ + +struct acpi_table_ibft { + struct acpi_table_header header; /* Common ACPI table header */ + u8 reserved[12]; +}; + +/* IBFT common subtable header */ + +struct acpi_ibft_header { + u8 type; + u8 version; + u16 length; + u8 index; + u8 flags; +}; + +/* Values for Type field above */ + +enum acpi_ibft_type { + ACPI_IBFT_TYPE_NOT_USED = 0, + ACPI_IBFT_TYPE_CONTROL = 1, + ACPI_IBFT_TYPE_INITIATOR = 2, + ACPI_IBFT_TYPE_NIC = 3, + ACPI_IBFT_TYPE_TARGET = 4, + ACPI_IBFT_TYPE_EXTENSIONS = 5, + ACPI_IBFT_TYPE_RESERVED = 6 /* 6 and greater are reserved */ +}; + +/* IBFT subtables */ + +struct acpi_ibft_control { + struct acpi_ibft_header header; + u16 extensions; + u16 initiator_offset; + u16 nic0_offset; + u16 target0_offset; + u16 nic1_offset; + u16 target1_offset; +}; + +struct acpi_ibft_initiator { + struct acpi_ibft_header header; + u8 sns_server[16]; + u8 slp_server[16]; + u8 primary_server[16]; + u8 secondary_server[16]; + u16 name_length; + u16 name_offset; +}; + +struct acpi_ibft_nic { + struct acpi_ibft_header header; + u8 ip_address[16]; + u8 subnet_mask_prefix; + u8 origin; + u8 gateway[16]; + u8 primary_dns[16]; + u8 secondary_dns[16]; + u8 dhcp[16]; + u16 vlan; + u8 mac_address[6]; + u16 pci_address; + u16 name_length; + u16 name_offset; +}; + +struct acpi_ibft_target { + struct acpi_ibft_header header; + u8 target_ip_address[16]; + u16 target_ip_socket; + u8 target_boot_lun[8]; + u8 chap_type; + u8 nic_association; + u16 target_name_length; + u16 target_name_offset; + u16 chap_name_length; + u16 chap_name_offset; + u16 chap_secret_length; + u16 chap_secret_offset; + u16 reverse_chap_name_length; + u16 reverse_chap_name_offset; + u16 reverse_chap_secret_length; + u16 reverse_chap_secret_offset; +}; + +/******************************************************************************* + * + * MCFG - PCI Memory Mapped Configuration table and sub-table + * + ******************************************************************************/ + +struct acpi_table_mcfg { + struct acpi_table_header header; /* Common ACPI table header */ + u8 reserved[8]; +}; + +/* Subtable */ + +struct acpi_mcfg_allocation { + u64 address; /* Base address, processor-relative */ + u16 pci_segment; /* PCI segment group number */ + u8 start_bus_number; /* Starting PCI Bus number */ + u8 end_bus_number; /* Final PCI Bus number */ + u32 reserved; +}; + +/******************************************************************************* + * + * SPCR - Serial Port Console Redirection table + * + ******************************************************************************/ + +struct acpi_table_spcr { + struct acpi_table_header header; /* Common ACPI table header */ + u8 interface_type; /* 0=full 16550, 1=subset of 16550 */ + u8 reserved[3]; + struct acpi_generic_address serial_port; + u8 interrupt_type; + u8 pc_interrupt; + u32 interrupt; + u8 baud_rate; + u8 parity; + u8 stop_bits; + u8 flow_control; + u8 terminal_type; + u8 reserved1; + u16 pci_device_id; + u16 pci_vendor_id; + u8 pci_bus; + u8 pci_device; + u8 pci_function; + u32 pci_flags; + u8 pci_segment; + u32 reserved2; +}; + +/******************************************************************************* + * + * SPMI - Server Platform Management Interface table + * + ******************************************************************************/ + +struct acpi_table_spmi { + struct acpi_table_header header; /* Common ACPI table header */ + u8 reserved; + u8 interface_type; + u16 spec_revision; /* Version of IPMI */ + u8 interrupt_type; + u8 gpe_number; /* GPE assigned */ + u8 reserved1; + u8 pci_device_flag; + u32 interrupt; + struct acpi_generic_address ipmi_register; + u8 pci_segment; + u8 pci_bus; + u8 pci_device; + u8 pci_function; +}; + +/******************************************************************************* + * + * TCPA - Trusted Computing Platform Alliance table + * + ******************************************************************************/ + +struct acpi_table_tcpa { + struct acpi_table_header header; /* Common ACPI table header */ + u16 reserved; + u32 max_log_length; /* Maximum length for the event log area */ + u64 log_address; /* Address of the event log area */ +}; + +/******************************************************************************* + * + * UEFI - UEFI Boot optimization Table + * + ******************************************************************************/ + +struct acpi_table_uefi { + struct acpi_table_header header; /* Common ACPI table header */ + u8 identifier[16]; /* UUID identifier */ + u16 data_offset; /* Offset of remaining data in table */ + u8 data; +}; + +/******************************************************************************* + * + * WDAT - Watchdog Action Table + * + ******************************************************************************/ + +struct acpi_table_wdat { + struct acpi_table_header header; /* Common ACPI table header */ + u32 header_length; /* Watchdog Header Length */ + u16 pci_segment; /* PCI Segment number */ + u8 pci_bus; /* PCI Bus number */ + u8 pci_device; /* PCI Device number */ + u8 pci_function; /* PCI Function number */ + u8 reserved[3]; + u32 timer_period; /* Period of one timer count (msec) */ + u32 max_count; /* Maximum counter value supported */ + u32 min_count; /* Minimum counter value */ + u8 flags; + u8 reserved2[3]; + u32 entries; /* Number of watchdog entries that follow */ +}; + +/* WDAT Instruction Entries (actions) */ + +struct acpi_wdat_entry { + struct acpi_whea_header whea_header; /* Common header for WHEA tables */ +}; + +/* Values for Action field above */ + +enum acpi_wdat_actions { + ACPI_WDAT_RESET = 1, + ACPI_WDAT_GET_CURRENT_COUNTDOWN = 4, + ACPI_WDAT_GET_COUNTDOWN = 5, + ACPI_WDAT_SET_COUNTDOWN = 6, + ACPI_WDAT_GET_RUNNING_STATE = 8, + ACPI_WDAT_SET_RUNNING_STATE = 9, + ACPI_WDAT_GET_STOPPED_STATE = 10, + ACPI_WDAT_SET_STOPPED_STATE = 11, + ACPI_WDAT_GET_REBOOT = 16, + ACPI_WDAT_SET_REBOOT = 17, + ACPI_WDAT_GET_SHUTDOWN = 18, + ACPI_WDAT_SET_SHUTDOWN = 19, + ACPI_WDAT_GET_STATUS = 32, + ACPI_WDAT_SET_STATUS = 33, + ACPI_WDAT_ACTION_RESERVED = 34 /* 34 and greater are reserved */ +}; + +/* Values for Instruction field above */ + +enum acpi_wdat_instructions { + ACPI_WDAT_READ_VALUE = 0, + ACPI_WDAT_READ_COUNTDOWN = 1, + ACPI_WDAT_WRITE_VALUE = 2, + ACPI_WDAT_WRITE_COUNTDOWN = 3, + ACPI_WDAT_INSTRUCTION_RESERVED = 4, /* 4 and greater are reserved */ + ACPI_WDAT_PRESERVE_REGISTER = 0x80 /* Except for this value */ +}; + +/******************************************************************************* + * + * WDRT - Watchdog Resource Table + * + ******************************************************************************/ + +struct acpi_table_wdrt { + struct acpi_table_header header; /* Common ACPI table header */ + u32 header_length; /* Watchdog Header Length */ + u8 pci_segment; /* PCI Segment number */ + u8 pci_bus; /* PCI Bus number */ + u8 pci_device; /* PCI Device number */ + u8 pci_function; /* PCI Function number */ + u32 timer_period; /* Period of one timer count (msec) */ + u32 max_count; /* Maximum counter value supported */ + u32 min_count; /* Minimum counter value */ + u8 flags; + u8 reserved[3]; + u32 entries; /* Number of watchdog entries that follow */ +}; + +/* Flags */ + +#define ACPI_WDRT_TIMER_ENABLED (1) /* 00: Timer enabled */ + +/* Reset to default packing */ + +#pragma pack() + +#endif /* __ACTBL2_H__ */ -- cgit v0.10.2 From 6e2d5ebd0d36199920676fdceaff4f4bfe66297b Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Mon, 27 Jul 2009 10:53:00 +0800 Subject: ACPICA: ACPI 4: Update headers for new and changed ACPI tables. Add IVRS,MSCT,UEFI,WAET,WDAT. Updated several existing tables for ACPI 4.0-related changes. Added document references for all tables not defined in ACPI spec. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/include/acpi/actbl.h b/include/acpi/actbl.h index 55fcfc6..1b65879 100644 --- a/include/acpi/actbl.h +++ b/include/acpi/actbl.h @@ -58,8 +58,9 @@ ******************************************************************************/ /* - * Values for description table header signatures. Useful because they make - * it more difficult to inadvertently type in the wrong signature. + * Values for description table header signatures for tables defined in this + * file. Useful because they make it more difficult to inadvertently type in + * the wrong signature. */ #define ACPI_SIG_DSDT "DSDT" /* Differentiated System Description Table */ #define ACPI_SIG_FADT "FACP" /* Fixed ACPI Description Table */ @@ -123,6 +124,7 @@ struct acpi_generic_address { /******************************************************************************* * * RSDP - Root System Description Pointer (Signature is "RSD PTR ") + * Version 2 * ******************************************************************************/ @@ -143,6 +145,7 @@ struct acpi_table_rsdp { /******************************************************************************* * * RSDT/XSDT - Root System Description Tables + * Version 1 (both) * ******************************************************************************/ @@ -176,23 +179,24 @@ struct acpi_table_facs { u8 reserved1[24]; /* Reserved, must be zero */ }; -/* global_lock flags */ +/* Masks for global_lock flag field above */ #define ACPI_GLOCK_PENDING (1) /* 00: Pending global lock ownership */ #define ACPI_GLOCK_OWNED (1<<1) /* 01: Global lock is owned */ -/* Flags */ +/* Masks for Flags field above */ #define ACPI_FACS_S4_BIOS_PRESENT (1) /* 00: S4BIOS support is present */ #define ACPI_FACS_64BIT_WAKE (1<<1) /* 01: 64-bit wake vector supported (ACPI 4.0) */ -/* ospm_flags */ +/* Masks for ospm_flags field above */ #define ACPI_FACS_64BIT_ENVIRONMENT (1) /* 00: 64-bit wake environment is required (ACPI 4.0) */ /******************************************************************************* * * FADT - Fixed ACPI Description Table (Signature "FACP") + * Version 4 * ******************************************************************************/ @@ -253,7 +257,7 @@ struct acpi_table_fadt { struct acpi_generic_address xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */ }; -/* FADT Boot Architecture Flags (boot_flags) */ +/* Masks for FADT Boot Architecture Flags (boot_flags) */ #define ACPI_FADT_LEGACY_DEVICES (1) /* 00: [V2] System has LPC or ISA bus devices */ #define ACPI_FADT_8042 (1<<1) /* 01: [V3] System has an 8042 controller on port 60/64 */ @@ -263,7 +267,7 @@ struct acpi_table_fadt { #define FADT2_REVISION_ID 3 -/* FADT flags */ +/* Masks for FADT flags */ #define ACPI_FADT_WBINVD (1) /* 00: [V1] The wbinvd instruction works properly */ #define ACPI_FADT_WBINVD_FLUSH (1<<1) /* 01: [V1] wbinvd flushes but does not invalidate caches */ @@ -286,7 +290,7 @@ struct acpi_table_fadt { #define ACPI_FADT_APIC_CLUSTER (1<<18) /* 18: [V4] All local APICs must use cluster model (ACPI 3.0) */ #define ACPI_FADT_APIC_PHYSICAL (1<<19) /* 19: [V4] All local x_aPICs must use physical dest mode (ACPI 3.0) */ -/* FADT Prefered Power Management Profiles */ +/* Values for preferred_profile (Prefered Power Management Profiles) */ enum acpi_prefered_pm_profiles { PM_UNSPECIFIED = 0, @@ -304,14 +308,16 @@ enum acpi_prefered_pm_profiles { #define ACPI_FADT_OFFSET(f) (u8) ACPI_OFFSET (struct acpi_table_fadt, f) +/* + * Internal table-related structures + */ union acpi_name_union { u32 integer; char ascii[4]; }; -/* - * Internal ACPI Table Descriptor. One per ACPI table - */ +/* Internal ACPI Table Descriptor. One per ACPI table. */ + struct acpi_table_desc { acpi_physical_address address; struct acpi_table_header *pointer; @@ -321,7 +327,7 @@ struct acpi_table_desc { u8 flags; }; -/* Flags for above */ +/* Masks for Flags field above */ #define ACPI_TABLE_ORIGIN_UNKNOWN (0) #define ACPI_TABLE_ORIGIN_MAPPED (1) diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 582af1f..0417f2a 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -56,8 +56,9 @@ ******************************************************************************/ /* - * Values for description table header signatures. Useful because they make - * it more difficult to inadvertently type in the wrong signature. + * Values for description table header signatures for tables defined in this + * file. Useful because they make it more difficult to inadvertently type in + * the wrong signature. */ #define ACPI_SIG_BERT "BERT" /* Boot Error Record Table */ #define ACPI_SIG_CPEP "CPEP" /* Corrected Platform Error Polling table */ @@ -66,6 +67,7 @@ #define ACPI_SIG_ERST "ERST" /* Error Record Serialization Table */ #define ACPI_SIG_HEST "HEST" /* Hardware Error Source Table */ #define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */ +#define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */ #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */ #define ACPI_SIG_SLIT "SLIT" /* System Locality Distance Information Table */ #define ACPI_SIG_SRAT "SRAT" /* System Resource Affinity Table */ @@ -82,14 +84,20 @@ * portable, so do not use any other bitfield types. */ -/* Common Subtable header (used in MADT, SRAT, etc.) */ +/******************************************************************************* + * + * Common subtable headers + * + ******************************************************************************/ + +/* Generic subtable header (used in MADT, SRAT, etc.) */ struct acpi_subtable_header { u8 type; u8 length; }; -/* Common Subtable header for WHEA tables (EINJ, ERST, WDAT) */ +/* Subtable header for WHEA tables (EINJ, ERST, WDAT) */ struct acpi_whea_header { u8 action; @@ -103,7 +111,8 @@ struct acpi_whea_header { /******************************************************************************* * - * BERT - Boot Error Record Table + * BERT - Boot Error Record Table (ACPI 4.0) + * Version 1 * ******************************************************************************/ @@ -113,26 +122,43 @@ struct acpi_table_bert { u64 address; /* Physical addresss of the error region */ }; -/* Boot Error Region */ +/* Boot Error Region (not a subtable, pointed to by Address field above) */ struct acpi_bert_region { - u32 block_status; - u32 raw_data_offset; - u32 raw_data_length; - u32 data_length; - u32 error_severity; + u32 block_status; /* Type of error information */ + u32 raw_data_offset; /* Offset to raw error data */ + u32 raw_data_length; /* Length of raw error data */ + u32 data_length; /* Length of generic error data */ + u32 error_severity; /* Severity code */ }; -/* block_status Flags */ +/* Values for block_status flags above */ #define ACPI_BERT_UNCORRECTABLE (1) -#define ACPI_BERT_CORRECTABLE (2) -#define ACPI_BERT_MULTIPLE_UNCORRECTABLE (4) -#define ACPI_BERT_MULTIPLE_CORRECTABLE (8) +#define ACPI_BERT_CORRECTABLE (1<<1) +#define ACPI_BERT_MULTIPLE_UNCORRECTABLE (1<<2) +#define ACPI_BERT_MULTIPLE_CORRECTABLE (1<<3) +#define ACPI_BERT_ERROR_ENTRY_COUNT (0xFF<<4) /* 8 bits, error count */ + +/* Values for error_severity above */ + +enum acpi_bert_error_severity { + ACPI_BERT_ERROR_CORRECTABLE = 0, + ACPI_BERT_ERROR_FATAL = 1, + ACPI_BERT_ERROR_CORRECTED = 2, + ACPI_BERT_ERROR_NONE = 3, + ACPI_BERT_ERROR_RESERVED = 4 /* 4 and greater are reserved */ +}; + +/* + * Note: The generic error data that follows the error_severity field above + * uses the struct acpi_hest_generic_data defined under the HEST table below + */ /******************************************************************************* * - * CPEP - Corrected Platform Error Polling table + * CPEP - Corrected Platform Error Polling table (ACPI 4.0) + * Version 1 * ******************************************************************************/ @@ -144,8 +170,7 @@ struct acpi_table_cpep { /* Subtable */ struct acpi_cpep_polling { - u8 type; - u8 length; + struct acpi_subtable_header header; u8 id; /* Processor ID */ u8 eid; /* Processor EID */ u32 interval; /* Polling interval (msec) */ @@ -154,6 +179,7 @@ struct acpi_cpep_polling { /******************************************************************************* * * ECDT - Embedded Controller Boot Resources Table + * Version 1 * ******************************************************************************/ @@ -168,14 +194,16 @@ struct acpi_table_ecdt { /******************************************************************************* * - * EINJ - Error Injection Table + * EINJ - Error Injection Table (ACPI 4.0) + * Version 1 * ******************************************************************************/ struct acpi_table_einj { struct acpi_table_header header; /* Common ACPI table header */ u32 header_length; - u32 reserved; + u8 flags; + u8 reserved[3]; u32 entries; }; @@ -185,6 +213,10 @@ struct acpi_einj_entry { struct acpi_whea_header whea_header; /* Common header for WHEA tables */ }; +/* Masks for Flags field above */ + +#define ACPI_EINJ_PRESERVE (1) + /* Values for Action field above */ enum acpi_einj_actions { @@ -220,9 +252,34 @@ struct acpi_einj_trigger { u32 entry_count; }; +/* Command status return values */ + +enum acpi_einj_command_status { + ACPI_EINJ_SUCCESS = 0, + ACPI_EINJ_FAILURE = 1, + ACPI_EINJ_INVALID_ACCESS = 2, + ACPI_EINJ_STATUS_RESERVED = 3 /* 3 and greater are reserved */ +}; + +/* Error types returned from ACPI_EINJ_GET_ERROR_TYPE (bitfield) */ + +#define ACPI_EINJ_PROCESSOR_CORRECTABLE (1) +#define ACPI_EINJ_PROCESSOR_UNCORRECTABLE (1<<1) +#define ACPI_EINJ_PROCESSOR_FATAL (1<<2) +#define ACPI_EINJ_MEMORY_CORRECTABLE (1<<3) +#define ACPI_EINJ_MEMORY_UNCORRECTABLE (1<<4) +#define ACPI_EINJ_MEMORY_FATAL (1<<5) +#define ACPI_EINJ_PCIX_CORRECTABLE (1<<6) +#define ACPI_EINJ_PCIX_UNCORRECTABLE (1<<7) +#define ACPI_EINJ_PCIX_FATAL (1<<8) +#define ACPI_EINJ_PLATFORM_CORRECTABLE (1<<9) +#define ACPI_EINJ_PLATFORM_UNCORRECTABLE (1<<10) +#define ACPI_EINJ_PLATFORM_FATAL (1<<11) + /******************************************************************************* * - * ERST - Error Record Serialization Table + * ERST - Error Record Serialization Table (ACPI 4.0) + * Version 1 * ******************************************************************************/ @@ -239,19 +296,23 @@ struct acpi_erst_entry { struct acpi_whea_header whea_header; /* Common header for WHEA tables */ }; +/* Masks for Flags field above */ + +#define ACPI_ERST_PRESERVE (1) + /* Values for Action field above */ enum acpi_erst_actions { - ACPI_ERST_BEGIN_WRITE_OPERATION = 0, - ACPI_ERST_BEGIN_READ_OPERATION = 1, - ACPI_ERST_BETGIN_CLEAR_OPERATION = 2, - ACPI_ERST_END_OPERATION = 3, + ACPI_ERST_BEGIN_WRITE = 0, + ACPI_ERST_BEGIN_READ = 1, + ACPI_ERST_BEGIN_CLEAR = 2, + ACPI_ERST_END = 3, ACPI_ERST_SET_RECORD_OFFSET = 4, ACPI_ERST_EXECUTE_OPERATION = 5, ACPI_ERST_CHECK_BUSY_STATUS = 6, ACPI_ERST_GET_COMMAND_STATUS = 7, - ACPI_ERST_GET_RECORD_IDENTIFIER = 8, - ACPI_ERST_SET_RECORD_IDENTIFIER = 9, + ACPI_ERST_GET_RECORD_ID = 8, + ACPI_ERST_SET_RECORD_ID = 9, ACPI_ERST_GET_RECORD_COUNT = 10, ACPI_ERST_BEGIN_DUMMY_WRIITE = 11, ACPI_ERST_NOT_USED = 12, @@ -286,9 +347,29 @@ enum acpi_erst_instructions { ACPI_ERST_INSTRUCTION_RESERVED = 19 /* 19 and greater are reserved */ }; +/* Command status return values */ + +enum acpi_erst_command_status { + ACPI_ERST_SUCESS = 0, + ACPI_ERST_NO_SPACE = 1, + ACPI_ERST_NOT_AVAILABLE = 2, + ACPI_ERST_FAILURE = 3, + ACPI_ERST_RECORD_EMPTY = 4, + ACPI_ERST_NOT_FOUND = 5, + ACPI_ERST_STATUS_RESERVED = 6 /* 6 and greater are reserved */ +}; + +/* Error Record Serialization Information */ + +struct acpi_erst_info { + u16 signature; /* Should be "ER" */ + u8 data[48]; +}; + /******************************************************************************* * - * HEST - Hardware Error Source Table + * HEST - Hardware Error Source Table (ACPI 4.0) + * Version 1 * ******************************************************************************/ @@ -301,70 +382,49 @@ struct acpi_table_hest { struct acpi_hest_header { u16 type; + u16 source_id; }; /* Values for Type field above for subtables */ enum acpi_hest_types { - ACPI_HEST_TYPE_XPF_MACHINE_CHECK = 0, - ACPI_HEST_TYPE_XPF_CORRECTED_MACHINE_CHECK = 1, - ACPI_HEST_TYPE_XPF_UNUSED = 2, - ACPI_HEST_TYPE_XPF_NON_MASKABLE_INTERRUPT = 3, - ACPI_HEST_TYPE_IPF_CORRECTED_MACHINE_CHECK = 4, - ACPI_HEST_TYPE_IPF_CORRECTED_PLATFORM_ERROR = 5, + ACPI_HEST_TYPE_IA32_CHECK = 0, + ACPI_HEST_TYPE_IA32_CORRECTED_CHECK = 1, + ACPI_HEST_TYPE_IA32_NMI = 2, + ACPI_HEST_TYPE_NOT_USED3 = 3, + ACPI_HEST_TYPE_NOT_USED4 = 4, + ACPI_HEST_TYPE_NOT_USED5 = 5, ACPI_HEST_TYPE_AER_ROOT_PORT = 6, ACPI_HEST_TYPE_AER_ENDPOINT = 7, ACPI_HEST_TYPE_AER_BRIDGE = 8, - ACPI_HEST_TYPE_GENERIC_HARDWARE_ERROR_SOURCE = 9, + ACPI_HEST_TYPE_GENERIC_ERROR = 9, ACPI_HEST_TYPE_RESERVED = 10 /* 10 and greater are reserved */ }; /* - * HEST Sub-subtables + * HEST substructures contained in subtables */ -/* XPF Machine Check Error Bank */ - -struct acpi_hest_xpf_error_bank { +/* + * IA32 Error Bank(s) - Follows the struct acpi_hest_ia_machine_check and + * struct acpi_hest_ia_corrected structures. + */ +struct acpi_hest_ia_error_bank { u8 bank_number; u8 clear_status_on_init; u8 status_format; - u8 config_write_enable; + u8 reserved; u32 control_register; - u64 control_init_data; + u64 control_data; u32 status_register; u32 address_register; u32 misc_register; }; -/* Generic Error Status */ - -struct acpi_hest_generic_status { - u32 block_status; - u32 raw_data_offset; - u32 raw_data_length; - u32 data_length; - u32 error_severity; -}; - -/* Generic Error Data */ - -struct acpi_hest_generic_data { - u8 section_type[16]; - u32 error_severity; - u16 revision; - u8 validation_bits; - u8 flags; - u32 error_data_length; - u8 fru_id[16]; - u8 fru_text[20]; -}; - -/* Common HEST structure for PCI/AER types below (6,7,8) */ +/* Common HEST sub-structure for PCI/AER structures below (6,7,8) */ struct acpi_hest_aer_common { - u16 source_id; - u16 config_write_enable; + u16 reserved1; u8 flags; u8 enabled; u32 records_to_pre_allocate; @@ -373,13 +433,18 @@ struct acpi_hest_aer_common { u16 device; u16 function; u16 device_control; - u16 reserved; + u16 reserved2; u32 uncorrectable_error_mask; u32 uncorrectable_error_severity; u32 correctable_error_mask; u32 advanced_error_capabilities; }; +/* Masks for HEST Flags fields */ + +#define ACPI_HEST_FIRMWARE_FIRST (1) +#define ACPI_HEST_GLOBAL (1<<1) + /* Hardware Error Notification */ struct acpi_hest_notify { @@ -405,71 +470,59 @@ enum acpi_hest_notify_types { ACPI_HEST_NOTIFY_RESERVED = 5 /* 5 and greater are reserved */ }; +/* Values for config_write_enable bitfield above */ + +#define ACPI_HEST_TYPE (1) +#define ACPI_HEST_POLL_INTERVAL (1<<1) +#define ACPI_HEST_POLL_THRESHOLD_VALUE (1<<2) +#define ACPI_HEST_POLL_THRESHOLD_WINDOW (1<<3) +#define ACPI_HEST_ERR_THRESHOLD_VALUE (1<<4) +#define ACPI_HEST_ERR_THRESHOLD_WINDOW (1<<5) + /* * HEST subtables - * - * From WHEA Design Document, 16 May 2007. - * Note: There is no subtable type 2 in this version of the document, - * and there are two different subtable type 3s. */ - /* 0: XPF Machine Check Exception */ +/* 0: IA32 Machine Check Exception */ -struct acpi_hest_xpf_machine_check { +struct acpi_hest_ia_machine_check { struct acpi_hest_header header; - u16 source_id; - u16 config_write_enable; + u16 reserved1; u8 flags; - u8 reserved1; + u8 enabled; u32 records_to_pre_allocate; u32 max_sections_per_record; u64 global_capability_data; u64 global_control_data; u8 num_hardware_banks; - u8 reserved2[7]; + u8 reserved3[7]; }; -/* 1: XPF Corrected Machine Check */ +/* 1: IA32 Corrected Machine Check */ -struct acpi_table_hest_xpf_corrected { +struct acpi_table_hest_ia_corrected { struct acpi_hest_header header; - u16 source_id; - u16 config_write_enable; + u16 reserved1; u8 flags; u8 enabled; u32 records_to_pre_allocate; u32 max_sections_per_record; struct acpi_hest_notify notify; u8 num_hardware_banks; - u8 reserved[3]; + u8 reserved2[3]; }; -/* 3: XPF Non-Maskable Interrupt */ +/* 2: IA32 Non-Maskable Interrupt */ -struct acpi_hest_xpf_nmi { +struct acpi_hest_ia_nmi { struct acpi_hest_header header; - u16 source_id; u32 reserved; u32 records_to_pre_allocate; u32 max_sections_per_record; u32 max_raw_data_length; }; -/* 4: IPF Corrected Machine Check */ - -struct acpi_hest_ipf_corrected { - struct acpi_hest_header header; - u8 enabled; - u8 reserved; -}; - -/* 5: IPF Corrected Platform Error */ - -struct acpi_hest_ipf_corrected_platform { - struct acpi_hest_header header; - u8 enabled; - u8 reserved; -}; +/* 3,4,5: Not used */ /* 6: PCI Express Root Port AER */ @@ -491,30 +544,61 @@ struct acpi_hest_aer { struct acpi_hest_aer_bridge { struct acpi_hest_header header; struct acpi_hest_aer_common aer; - u32 secondary_uncorrectable_error_mask; - u32 secondary_uncorrectable_error_severity; - u32 secondary_advanced_capabilities; + u32 second_uncorrectable_error_mask; + u32 second_uncorrectable_error_severity; + u32 second_advanced_capabilities; }; /* 9: Generic Hardware Error Source */ struct acpi_hest_generic { struct acpi_hest_header header; - u16 source_id; u16 related_source_id; - u8 config_write_enable; + u8 reserved; u8 enabled; u32 records_to_pre_allocate; u32 max_sections_per_record; u32 max_raw_data_length; struct acpi_generic_address error_status_address; struct acpi_hest_notify notify; - u32 error_status_block_length; + u32 error_block_length; +}; + +/* Generic Error Status block */ + +struct acpi_hest_generic_status { + u32 block_status; + u32 raw_data_offset; + u32 raw_data_length; + u32 data_length; + u32 error_severity; +}; + +/* Values for block_status flags above */ + +#define ACPI_HEST_UNCORRECTABLE (1) +#define ACPI_HEST_CORRECTABLE (1<<1) +#define ACPI_HEST_MULTIPLE_UNCORRECTABLE (1<<2) +#define ACPI_HEST_MULTIPLE_CORRECTABLE (1<<3) +#define ACPI_HEST_ERROR_ENTRY_COUNT (0xFF<<4) /* 8 bits, error count */ + +/* Generic Error Data entry */ + +struct acpi_hest_generic_data { + u8 section_type[16]; + u32 error_severity; + u16 revision; + u8 validation_bits; + u8 flags; + u32 error_data_length; + u8 fru_id[16]; + u8 fru_text[20]; }; /******************************************************************************* * * MADT - Multiple APIC Description Table + * Version 3 * ******************************************************************************/ @@ -524,16 +608,16 @@ struct acpi_table_madt { u32 flags; }; -/* Flags */ +/* Masks for Flags field above */ -#define ACPI_MADT_PCAT_COMPAT (1) /* 00: System also has dual 8259s */ +#define ACPI_MADT_PCAT_COMPAT (1) /* 00: System also has dual 8259s */ /* Values for PCATCompat flag */ #define ACPI_MADT_DUAL_PIC 0 #define ACPI_MADT_MULTIPLE_APIC 1 -/* Values for subtable type in struct acpi_subtable_header */ +/* Values for MADT subtable type in struct acpi_subtable_header */ enum acpi_madt_type { ACPI_MADT_TYPE_LOCAL_APIC = 0, @@ -644,7 +728,7 @@ struct acpi_madt_interrupt_source { u32 flags; /* Interrupt Source Flags */ }; -/* Flags field above */ +/* Masks for Flags field above */ #define ACPI_MADT_CPEI_OVERRIDE (1) @@ -695,7 +779,34 @@ struct acpi_madt_local_x2apic_nmi { /******************************************************************************* * + * MSCT - Maximum System Characteristics Table (ACPI 4.0) + * Version 1 + * + ******************************************************************************/ + +struct acpi_table_msct { + struct acpi_table_header header; /* Common ACPI table header */ + u32 proximity_offset; /* Location of proximity info struct(s) */ + u32 max_proximity_domains; /* Max number of proximity domains */ + u32 max_clock_domains; /* Max number of clock domains */ + u64 max_address; /* Max physical address in system */ +}; + +/* Subtable - Maximum Proximity Domain Information. Version 1 */ + +struct acpi_msct_proximity { + u8 revision; + u8 length; + u32 range_start; /* Start of domain range */ + u32 range_end; /* End of domain range */ + u32 processor_capacity; + u64 memory_capacity; /* In bytes */ +}; + +/******************************************************************************* + * * SBST - Smart Battery Specification Table + * Version 1 * ******************************************************************************/ @@ -709,6 +820,7 @@ struct acpi_table_sbst { /******************************************************************************* * * SLIT - System Locality Distance Information Table + * Version 1 * ******************************************************************************/ @@ -721,6 +833,7 @@ struct acpi_table_slit { /******************************************************************************* * * SRAT - System Resource Affinity Table + * Version 3 * ******************************************************************************/ @@ -755,6 +868,10 @@ struct acpi_srat_cpu_affinity { u32 reserved; /* Reserved, must be zero */ }; +/* Flags */ + +#define ACPI_SRAT_CPU_USE_AFFINITY (1) /* 00: Use affinity structure */ + /* 1: Memory Affinity */ struct acpi_srat_mem_affinity { diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index b271aba..6f3dce9 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -14,8 +14,9 @@ ******************************************************************************/ /* - * Values for description table header signatures. Useful because they make - * it more difficult to inadvertently type in the wrong signature. + * Values for description table header signatures for tables defined in this + * file. Useful because they make it more difficult to inadvertently type in + * the wrong signature. */ #define ACPI_SIG_ASF "ASF!" /* Alert Standard Format table */ #define ACPI_SIG_BOOT "BOOT" /* Simple Boot Flag Table */ @@ -23,12 +24,14 @@ #define ACPI_SIG_DMAR "DMAR" /* DMA Remapping table */ #define ACPI_SIG_HPET "HPET" /* High Precision Event Timer table */ #define ACPI_SIG_IBFT "IBFT" /* i_sCSI Boot Firmware Table */ +#define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */ #define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */ #define ACPI_SIG_SLIC "SLIC" /* Software Licensing Description Table */ #define ACPI_SIG_SPCR "SPCR" /* Serial Port Console Redirection table */ #define ACPI_SIG_SPMI "SPMI" /* Server Platform Management Interface table */ #define ACPI_SIG_TCPA "TCPA" /* Trusted Computing Platform Alliance table */ #define ACPI_SIG_UEFI "UEFI" /* Uefi Boot Optimization Table */ +#define ACPI_SIG_WAET "WAET" /* Windows ACPI Emulated devices Table */ #define ACPI_SIG_WDAT "WDAT" /* Watchdog Action Table */ #define ACPI_SIG_WDRT "WDRT" /* Watchdog Resource Table */ @@ -47,6 +50,7 @@ /******************************************************************************* * * ASF - Alert Standard Format table (Signature "ASF!") + * Revision 0x10 * * Conforms to the Alert Standard Format Specification V2.0, 23 April 2003 * @@ -91,6 +95,10 @@ struct acpi_asf_info { u8 reserved2[3]; }; +/* Masks for Flags field above */ + +#define ACPI_ASF_SMBUS_PROTOCOLS (1) + /* 1: ASF Alerts */ struct acpi_asf_alert { @@ -156,6 +164,9 @@ struct acpi_asf_address { /******************************************************************************* * * BOOT - Simple Boot Flag Table + * Version 1 + * + * Conforms to the "Simple Boot Flag Specification", Version 2.1 * ******************************************************************************/ @@ -168,6 +179,9 @@ struct acpi_table_boot { /******************************************************************************* * * DBGP - Debug Port table + * Version 1 + * + * Conforms to the "Debug Port Specification", Version 1.00, 2/9/2000 * ******************************************************************************/ @@ -181,7 +195,10 @@ struct acpi_table_dbgp { /******************************************************************************* * * DMAR - DMA Remapping table - * From "Intel Virtualization Technology for Directed I/O", Sept. 2007 + * Version 1 + * + * Conforms to "Intel Virtualization Technology for Directed I/O", + * Version 1.2, Sept. 2008 * ******************************************************************************/ @@ -192,7 +209,7 @@ struct acpi_table_dmar { u8 reserved[10]; }; -/* Flags */ +/* Masks for Flags field above */ #define ACPI_DMAR_INTR_REMAP (1) @@ -209,9 +226,12 @@ enum acpi_dmar_type { ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, ACPI_DMAR_TYPE_ATSR = 2, - ACPI_DMAR_TYPE_RESERVED = 3 /* 3 and greater are reserved */ + ACPI_DMAR_HARDWARE_AFFINITY = 3, + ACPI_DMAR_TYPE_RESERVED = 4 /* 4 and greater are reserved */ }; +/* DMAR Device Scope structure */ + struct acpi_dmar_device_scope { u8 entry_type; u8 length; @@ -250,7 +270,7 @@ struct acpi_dmar_hardware_unit { u64 address; /* Register Base Address */ }; -/* Flags */ +/* Masks for Flags field above */ #define ACPI_DMAR_INCLUDE_ALL (1) @@ -264,7 +284,7 @@ struct acpi_dmar_reserved_memory { u64 end_address; /* 4_k aligned limit address */ }; -/* Flags */ +/* Masks for Flags field above */ #define ACPI_DMAR_ALLOW_ALL (1) @@ -277,13 +297,26 @@ struct acpi_dmar_atsr { u16 segment; }; -/* Flags */ +/* Masks for Flags field above */ #define ACPI_DMAR_ALL_PORTS (1) +/* 3: Remapping Hardware Static Affinity Structure */ + +struct acpi_dmar_rhsa { + struct acpi_dmar_header header; + u32 reserved; + u64 base_address; + u32 proximity_domain; +}; + /******************************************************************************* * * HPET - High Precision Event Timer table + * Version 1 + * + * Conforms to "IA-PC HPET (High Precision Event Timers) Specification", + * Version 1.0a, October 2004 * ******************************************************************************/ @@ -296,17 +329,28 @@ struct acpi_table_hpet { u8 flags; }; -/*! Flags */ +/* Masks for Flags field above */ -#define ACPI_HPET_PAGE_PROTECT (1) /* 00: No page protection */ -#define ACPI_HPET_PAGE_PROTECT_4 (1<<1) /* 01: 4KB page protected */ -#define ACPI_HPET_PAGE_PROTECT_64 (1<<2) /* 02: 64KB page protected */ +#define ACPI_HPET_PAGE_PROTECT_MASK (3) -/*! [End] no source code translation !*/ +/* Values for Page Protect flags */ + +enum acpi_hpet_page_protect { + ACPI_HPET_NO_PAGE_PROTECT = 0, + ACPI_HPET_PAGE_PROTECT4 = 1, + ACPI_HPET_PAGE_PROTECT64 = 2 +}; /******************************************************************************* * * IBFT - Boot Firmware Table + * Version 1 + * + * Conforms to "iSCSI Boot Firmware Table (iBFT) as Defined in ACPI 3.0b + * Specification", Version 1.01, March 1, 2007 + * + * Note: It appears that this table is not intended to appear in the RSDT/XSDT. + * Therefore, it is not currently supported by the disassembler. * ******************************************************************************/ @@ -396,7 +440,182 @@ struct acpi_ibft_target { /******************************************************************************* * + * IVRS - I/O Virtualization Reporting Structure + * Version 1 + * + * Conforms to "AMD I/O Virtualization Technology (IOMMU) Specification", + * Revision 1.26, February 2009. + * + ******************************************************************************/ + +struct acpi_table_ivrs { + struct acpi_table_header header; /* Common ACPI table header */ + u32 info; /* Common virtualization info */ + u64 reserved; +}; + +/* Values for Info field above */ + +#define ACPI_IVRS_PHYSICAL_SIZE 0x00007F00 /* 7 bits, physical address size */ +#define ACPI_IVRS_VIRTUAL_SIZE 0x003F8000 /* 7 bits, virtual address size */ +#define ACPI_IVRS_ATS_RESERVED 0x00400000 /* ATS address translation range reserved */ + +/* IVRS subtable header */ + +struct acpi_ivrs_header { + u8 type; /* Subtable type */ + u8 flags; + u16 length; /* Subtable length */ + u16 device_id; /* ID of IOMMU */ +}; + +/* Values for subtable Type above */ + +enum acpi_ivrs_type { + ACPI_IVRS_TYPE_HARDWARE = 0x10, + ACPI_IVRS_TYPE_MEMORY1 = 0x20, + ACPI_IVRS_TYPE_MEMORY2 = 0x21, + ACPI_IVRS_TYPE_MEMORY3 = 0x22 +}; + +/* Masks for Flags field above for IVHD subtable */ + +#define ACPI_IVHD_TT_ENABLE (1) +#define ACPI_IVHD_PASS_PW (1<<1) +#define ACPI_IVHD_RES_PASS_PW (1<<2) +#define ACPI_IVHD_ISOC (1<<3) +#define ACPI_IVHD_IOTLB (1<<4) + +/* Masks for Flags field above for IVMD subtable */ + +#define ACPI_IVMD_UNITY (1) +#define ACPI_IVMD_READ (1<<1) +#define ACPI_IVMD_WRITE (1<<2) +#define ACPI_IVMD_EXCLUSION_RANGE (1<<3) + +/* + * IVRS subtables, correspond to Type in struct acpi_ivrs_header + */ + +/* 0x10: I/O Virtualization Hardware Definition Block (IVHD) */ + +struct acpi_ivrs_hardware { + struct acpi_ivrs_header header; + u16 capability_offset; /* Offset for IOMMU control fields */ + u64 base_address; /* IOMMU control registers */ + u16 pci_segment_group; + u16 info; /* MSI number and unit ID */ + u32 reserved; +}; + +/* Masks for Info field above */ + +#define ACPI_IVHD_MSI_NUMBER_MASK 0x001F /* 5 bits, MSI message number */ +#define ACPI_IVHD_UNIT_ID_MASK 0x1F00 /* 5 bits, unit_iD */ + +/* + * Device Entries for IVHD subtable, appear after struct acpi_ivrs_hardware structure. + * Upper two bits of the Type field are the (encoded) length of the structure. + * Currently, only 4 and 8 byte entries are defined. 16 and 32 byte entries + * are reserved for future use but not defined. + */ +struct acpi_ivrs_de_header { + u8 type; + u16 id; + u8 data_setting; +}; + +/* Length of device entry is in the top two bits of Type field above */ + +#define ACPI_IVHD_ENTRY_LENGTH 0xC0 + +/* Values for device entry Type field above */ + +enum acpi_ivrs_device_entry_type { + /* 4-byte device entries, all use struct acpi_ivrs_device4 */ + + ACPI_IVRS_TYPE_PAD4 = 0, + ACPI_IVRS_TYPE_ALL = 1, + ACPI_IVRS_TYPE_SELECT = 2, + ACPI_IVRS_TYPE_START = 3, + ACPI_IVRS_TYPE_END = 4, + + /* 8-byte device entries */ + + ACPI_IVRS_TYPE_PAD8 = 64, + ACPI_IVRS_TYPE_NOT_USED = 65, + ACPI_IVRS_TYPE_ALIAS_SELECT = 66, /* Uses struct acpi_ivrs_device8a */ + ACPI_IVRS_TYPE_ALIAS_START = 67, /* Uses struct acpi_ivrs_device8a */ + ACPI_IVRS_TYPE_EXT_SELECT = 70, /* Uses struct acpi_ivrs_device8b */ + ACPI_IVRS_TYPE_EXT_START = 71, /* Uses struct acpi_ivrs_device8b */ + ACPI_IVRS_TYPE_SPECIAL = 72 /* Uses struct acpi_ivrs_device8c */ +}; + +/* Values for Data field above */ + +#define ACPI_IVHD_INIT_PASS (1) +#define ACPI_IVHD_EINT_PASS (1<<1) +#define ACPI_IVHD_NMI_PASS (1<<2) +#define ACPI_IVHD_SYSTEM_MGMT (3<<4) +#define ACPI_IVHD_LINT0_PASS (1<<6) +#define ACPI_IVHD_LINT1_PASS (1<<7) + +/* Types 0-4: 4-byte device entry */ + +struct acpi_ivrs_device4 { + struct acpi_ivrs_de_header header; +}; + +/* Types 66-67: 8-byte device entry */ + +struct acpi_ivrs_device8a { + struct acpi_ivrs_de_header header; + u8 reserved1; + u16 used_id; + u8 reserved2; +}; + +/* Types 70-71: 8-byte device entry */ + +struct acpi_ivrs_device8b { + struct acpi_ivrs_de_header header; + u32 extended_data; +}; + +/* Values for extended_data above */ + +#define ACPI_IVHD_ATS_DISABLED (1<<31) + +/* Type 72: 8-byte device entry */ + +struct acpi_ivrs_device8c { + struct acpi_ivrs_de_header header; + u8 handle; + u16 used_id; + u8 variety; +}; + +/* Values for Variety field above */ + +#define ACPI_IVHD_IOAPIC 1 +#define ACPI_IVHD_HPET 2 + +/* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition Block (IVMD) */ + +struct acpi_ivrs_memory { + struct acpi_ivrs_header header; + u16 aux_data; + u64 reserved; + u64 start_address; + u64 memory_length; +}; + +/******************************************************************************* + * * MCFG - PCI Memory Mapped Configuration table and sub-table + * Version 1 + * + * Conforms to "PCI Firmware Specification", Revision 3.0, June 20, 2005 * ******************************************************************************/ @@ -418,6 +637,10 @@ struct acpi_mcfg_allocation { /******************************************************************************* * * SPCR - Serial Port Console Redirection table + * Version 1 + * + * Conforms to "Serial Port Console Redirection Table", + * Version 1.00, January 11, 2002 * ******************************************************************************/ @@ -445,16 +668,25 @@ struct acpi_table_spcr { u32 reserved2; }; +/* Masks for pci_flags field above */ + +#define ACPI_SPCR_DO_NOT_DISABLE (1) + /******************************************************************************* * * SPMI - Server Platform Management Interface table + * Version 5 + * + * Conforms to "Intelligent Platform Management Interface Specification + * Second Generation v2.0", Document Revision 1.0, February 12, 2004 with + * June 12, 2009 markup. * ******************************************************************************/ struct acpi_table_spmi { struct acpi_table_header header; /* Common ACPI table header */ - u8 reserved; u8 interface_type; + u8 reserved; /* Must be 1 */ u16 spec_revision; /* Version of IPMI */ u8 interrupt_type; u8 gpe_number; /* GPE assigned */ @@ -466,11 +698,27 @@ struct acpi_table_spmi { u8 pci_bus; u8 pci_device; u8 pci_function; + u8 reserved2; +}; + +/* Values for interface_type above */ + +enum acpi_spmi_interface_types { + ACPI_SPMI_NOT_USED = 0, + ACPI_SPMI_KEYBOARD = 1, + ACPI_SPMI_SMI = 2, + ACPI_SPMI_BLOCK_TRANSFER = 3, + ACPI_SPMI_SMBUS = 4, + ACPI_SPMI_RESERVED = 5 /* 5 and above are reserved */ }; /******************************************************************************* * * TCPA - Trusted Computing Platform Alliance table + * Version 1 + * + * Conforms to "TCG PC Specific Implementation Specification", + * Version 1.1, August 18, 2003 * ******************************************************************************/ @@ -484,6 +732,10 @@ struct acpi_table_tcpa { /******************************************************************************* * * UEFI - UEFI Boot optimization Table + * Version 1 + * + * Conforms to "Unified Extensible Firmware Interface Specification", + * Version 2.3, May 8, 2009 * ******************************************************************************/ @@ -491,12 +743,34 @@ struct acpi_table_uefi { struct acpi_table_header header; /* Common ACPI table header */ u8 identifier[16]; /* UUID identifier */ u16 data_offset; /* Offset of remaining data in table */ - u8 data; }; /******************************************************************************* * + * WAET - Windows ACPI Emulated devices Table + * Version 1 + * + * Conforms to "Windows ACPI Emulated Devices Table", version 1.0, April 6, 2009 + * + ******************************************************************************/ + +struct acpi_table_waet { + struct acpi_table_header header; /* Common ACPI table header */ + u32 flags; +}; + +/* Masks for Flags field above */ + +#define ACPI_WAET_RTC_NO_ACK (1) /* RTC requires no int acknowledge */ +#define ACPI_WAET_TIMER_ONE_READ (1<<1) /* PM timer requires only one read */ + +/******************************************************************************* + * * WDAT - Watchdog Action Table + * Version 1 + * + * Conforms to "Hardware Watchdog Timers Design Specification", + * Copyright 2006 Microsoft Corporation. * ******************************************************************************/ @@ -516,10 +790,20 @@ struct acpi_table_wdat { u32 entries; /* Number of watchdog entries that follow */ }; +/* Masks for Flags field above */ + +#define ACPI_WDAT_ENABLED (1) +#define ACPI_WDAT_STOPPED 0x80 + /* WDAT Instruction Entries (actions) */ struct acpi_wdat_entry { - struct acpi_whea_header whea_header; /* Common header for WHEA tables */ + u8 action; + u8 instruction; + u16 reserved; + struct acpi_generic_address register_region; + u32 value; /* Value used with Read/Write register */ + u32 mask; /* Bitmask required for this register instruction */ }; /* Values for Action field above */ @@ -556,28 +840,27 @@ enum acpi_wdat_instructions { /******************************************************************************* * * WDRT - Watchdog Resource Table + * Version 1 + * + * Conforms to "Watchdog Timer Hardware Requirements for Windows Server 2003", + * Version 1.01, August 28, 2006 * ******************************************************************************/ struct acpi_table_wdrt { struct acpi_table_header header; /* Common ACPI table header */ - u32 header_length; /* Watchdog Header Length */ - u8 pci_segment; /* PCI Segment number */ + struct acpi_generic_address control_register; + struct acpi_generic_address count_register; + u16 pci_device_id; + u16 pci_vendor_id; u8 pci_bus; /* PCI Bus number */ u8 pci_device; /* PCI Device number */ u8 pci_function; /* PCI Function number */ - u32 timer_period; /* Period of one timer count (msec) */ - u32 max_count; /* Maximum counter value supported */ - u32 min_count; /* Minimum counter value */ - u8 flags; - u8 reserved[3]; - u32 entries; /* Number of watchdog entries that follow */ + u8 pci_segment; /* PCI Segment number */ + u16 max_count; /* Maximum counter value supported */ + u8 units; }; -/* Flags */ - -#define ACPI_WDRT_TIMER_ENABLED (1) /* 00: Timer enabled */ - /* Reset to default packing */ #pragma pack() -- cgit v0.10.2 From d9adc2e031bd22d5d9607a53a8d3b30e0b675f39 Mon Sep 17 00:00:00 2001 From: Lin Ming Date: Mon, 27 Jul 2009 11:31:10 +0800 Subject: ACPICA: reformat predefined method table, no functional change Reformatted the methods that return package objects. Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/acpredef.h b/drivers/acpi/acpica/acpredef.h index 144b1f4..c81f14b 100644 --- a/drivers/acpi/acpica/acpredef.h +++ b/drivers/acpi/acpica/acpredef.h @@ -139,123 +139,180 @@ enum acpi_return_package_types { * is saved here (rather than in a separate table) in order to minimize the * overall size of the stored data. */ -static const union acpi_predefined_info predefined_names[] = { - {.info = {"_AC0", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_AC1", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_AC2", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_AC3", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_AC4", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_AC5", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_AC6", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_AC7", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_AC8", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_AC9", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_ADR", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_AL0", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_AL1", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_AL2", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_AL3", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_AL4", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_AL5", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_AL6", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_AL7", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_AL8", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_AL9", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_ALC", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_ALI", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_ALP", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_ALR", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2, ACPI_RTYPE_INTEGER, 2, 0, 0, 0}}, /* variable (Pkgs) each 2 (Ints) */ - {.info = {"_ALT", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_BBN", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_BCL", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 0, 0, 0, 0}}, /* variable (Ints) */ - {.info = {"_BCM", 1, 0}}, - {.info = {"_BDN", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_BFS", 1, 0}}, - {.info = {"_BIF", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, - 9, - ACPI_RTYPE_STRING | ACPI_RTYPE_BUFFER, 4, 0}}, /* fixed (9 Int),(4 Str) */ - {.info = {"_BLT", 3, 0}}, - {.info = {"_BMC", 1, 0}}, - {.info = {"_BMD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 5, 0, 0, 0}}, /* fixed (5 Int) */ - {.info = {"_BQC", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_BST", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4, 0, 0, 0}}, /* fixed (4 Int) */ - {.info = {"_BTM", 1, ACPI_RTYPE_INTEGER}}, - {.info = {"_BTP", 1, 0}}, - {.info = {"_CBA", 0, ACPI_RTYPE_INTEGER}}, /* see PCI firmware spec 3.0 */ - {.info = {"_CID", 0, - ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING | ACPI_RTYPE_PACKAGE}}, - {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING, 0, 0, 0, 0}}, /* variable (Ints/Strs) */ - {.info = {"_CRS", 0, ACPI_RTYPE_BUFFER}}, - {.info = {"_CRT", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_CSD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2_COUNT, ACPI_RTYPE_INTEGER, 0, 0, 0, 0}}, /* variable (1 Int(n), n-1 Int) */ - {.info = {"_CST", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2_PKG_COUNT, - ACPI_RTYPE_BUFFER, 1, - ACPI_RTYPE_INTEGER, 3, 0}}, /* variable (1 Int(n), n Pkg (1 Buf/3 Int) */ - {.info = {"_DCK", 1, ACPI_RTYPE_INTEGER}}, - {.info = {"_DCS", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_DDC", 1, ACPI_RTYPE_INTEGER | ACPI_RTYPE_BUFFER}}, - {.info = {"_DDN", 0, ACPI_RTYPE_STRING}}, - {.info = {"_DGS", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_DIS", 0, 0}}, - {.info = {"_DMA", 0, ACPI_RTYPE_BUFFER}}, - {.info = {"_DOD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 0, 0, 0, 0}}, /* variable (Ints) */ - {.info = {"_DOS", 1, 0}}, - {.info = {"_DSM", 4, ACPI_RTYPE_ALL}}, /* Must return a type, but it can be of any type */ - {.info = {"_DSS", 1, 0}}, - {.info = {"_DSW", 3, 0}}, - {.info = {"_EC_", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_EDL", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_EJ0", 1, 0}}, - {.info = {"_EJ1", 1, 0}}, - {.info = {"_EJ2", 1, 0}}, - {.info = {"_EJ3", 1, 0}}, - {.info = {"_EJ4", 1, 0}}, - {.info = {"_EJD", 0, ACPI_RTYPE_STRING}}, - {.info = {"_FDE", 0, ACPI_RTYPE_BUFFER}}, - {.info = {"_FDI", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 16, 0, 0, 0}}, /* fixed (16 Int) */ - {.info = {"_FDM", 1, 0}}, - {.info = {"_FIX", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 0, 0, 0, 0}}, /* variable (Ints) */ - {.info = {"_GLK", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_GPD", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_GPE", 0, ACPI_RTYPE_INTEGER}}, /* _GPE method, not _GPE scope */ - {.info = {"_GSB", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_GTF", 0, ACPI_RTYPE_BUFFER}}, - {.info = {"_GTM", 0, ACPI_RTYPE_BUFFER}}, - {.info = {"_GTS", 1, 0}}, - {.info = {"_HID", 0, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING}}, - {.info = {"_HOT", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_HPP", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4, 0, 0, 0}}, /* fixed (4 Int) */ +static const union acpi_predefined_info predefined_names[] = +{ + {{"_AC0", 0, ACPI_RTYPE_INTEGER}}, + {{"_AC1", 0, ACPI_RTYPE_INTEGER}}, + {{"_AC2", 0, ACPI_RTYPE_INTEGER}}, + {{"_AC3", 0, ACPI_RTYPE_INTEGER}}, + {{"_AC4", 0, ACPI_RTYPE_INTEGER}}, + {{"_AC5", 0, ACPI_RTYPE_INTEGER}}, + {{"_AC6", 0, ACPI_RTYPE_INTEGER}}, + {{"_AC7", 0, ACPI_RTYPE_INTEGER}}, + {{"_AC8", 0, ACPI_RTYPE_INTEGER}}, + {{"_AC9", 0, ACPI_RTYPE_INTEGER}}, + {{"_ADR", 0, ACPI_RTYPE_INTEGER}}, + {{"_AL0", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_AL1", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_AL2", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_AL3", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_AL4", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_AL5", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_AL6", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_AL7", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_AL8", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_AL9", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_ALC", 0, ACPI_RTYPE_INTEGER}}, + {{"_ALI", 0, ACPI_RTYPE_INTEGER}}, + {{"_ALP", 0, ACPI_RTYPE_INTEGER}}, + {{"_ALR", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each 2 (Ints) */ + {{{ACPI_PTYPE2, ACPI_RTYPE_INTEGER, 2,0}, 0,0}}, + + {{"_ALT", 0, ACPI_RTYPE_INTEGER}}, + {{"_BBN", 0, ACPI_RTYPE_INTEGER}}, + {{"_BCL", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Ints) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 0,0}, 0,0}}, + + {{"_BCM", 1, 0}}, + {{"_BDN", 0, ACPI_RTYPE_INTEGER}}, + {{"_BFS", 1, 0}}, + {{"_BIF", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (9 Int),(4 Str) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 9, ACPI_RTYPE_STRING}, 4,0}}, + + {{"_BLT", 3, 0}}, + {{"_BMC", 1, 0}}, + {{"_BMD", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (5 Int) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 5,0}, 0,0}}, + + {{"_BQC", 0, ACPI_RTYPE_INTEGER}}, + {{"_BST", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (4 Int) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4,0}, 0,0}}, + + {{"_BTM", 1, ACPI_RTYPE_INTEGER}}, + {{"_BTP", 1, 0}}, + {{"_CBA", 0, ACPI_RTYPE_INTEGER}}, /* See PCI firmware spec 3.0 */ + {{"_CID", 0, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING | ACPI_RTYPE_PACKAGE}}, /* Variable-length (Ints/Strs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING, 0,0}, 0,0}}, + + {{"_CRS", 0, ACPI_RTYPE_BUFFER}}, + {{"_CRT", 0, ACPI_RTYPE_INTEGER}}, + {{"_CSD", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (1 Int(n), n-1 Int) */ + {{{ACPI_PTYPE2_COUNT, ACPI_RTYPE_INTEGER, 0,0}, 0,0}}, + + {{"_CST", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (1 Int(n), n Pkg (1 Buf/3 Int) */ + {{{ACPI_PTYPE2_PKG_COUNT,ACPI_RTYPE_BUFFER, 1, ACPI_RTYPE_INTEGER}, 3,0}}, + + {{"_DCK", 1, ACPI_RTYPE_INTEGER}}, + {{"_DCS", 0, ACPI_RTYPE_INTEGER}}, + {{"_DDC", 1, ACPI_RTYPE_INTEGER | ACPI_RTYPE_BUFFER}}, + {{"_DDN", 0, ACPI_RTYPE_STRING}}, + {{"_DGS", 0, ACPI_RTYPE_INTEGER}}, + {{"_DIS", 0, 0}}, + {{"_DMA", 0, ACPI_RTYPE_BUFFER}}, + {{"_DOD", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Ints) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 0,0}, 0,0}}, + + {{"_DOS", 1, 0}}, + {{"_DSM", 4, ACPI_RTYPE_ALL}}, /* Must return a type, but it can be of any type */ + {{"_DSS", 1, 0}}, + {{"_DSW", 3, 0}}, + {{"_EC_", 0, ACPI_RTYPE_INTEGER}}, + {{"_EDL", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs)*/ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_EJ0", 1, 0}}, + {{"_EJ1", 1, 0}}, + {{"_EJ2", 1, 0}}, + {{"_EJ3", 1, 0}}, + {{"_EJ4", 1, 0}}, + {{"_EJD", 0, ACPI_RTYPE_STRING}}, + {{"_FDE", 0, ACPI_RTYPE_BUFFER}}, + {{"_FDI", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (16 Int) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 16,0}, 0,0}}, + + {{"_FDM", 1, 0}}, + {{"_FIX", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Ints) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 0,0}, 0,0}}, + + {{"_GLK", 0, ACPI_RTYPE_INTEGER}}, + {{"_GPD", 0, ACPI_RTYPE_INTEGER}}, + {{"_GPE", 0, ACPI_RTYPE_INTEGER}}, /* _GPE method, not _GPE scope */ + {{"_GSB", 0, ACPI_RTYPE_INTEGER}}, + {{"_GTF", 0, ACPI_RTYPE_BUFFER}}, + {{"_GTM", 0, ACPI_RTYPE_BUFFER}}, + {{"_GTS", 1, 0}}, + {{"_HID", 0, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING}}, + {{"_HOT", 0, ACPI_RTYPE_INTEGER}}, + {{"_HPP", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (4 Int) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4,0}, 0,0}}, /* - * For _HPX, a single package is returned, containing a variable number of sub-packages. - * Each sub-package contains a PCI record setting. There are several different type of - * record settings, of different lengths, but all elements of all settings are Integers. + * For _HPX, a single package is returned, containing a Variable-length number + * of sub-packages. Each sub-package contains a PCI record setting. + * There are several different type of record settings, of different + * lengths, but all elements of all settings are Integers. */ - {.info = {"_HPX", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2_MIN, ACPI_RTYPE_INTEGER, 5, 0, 0, 0}}, /* variable (Pkgs) each (var Ints) */ - {.info = {"_IFT", 0, ACPI_RTYPE_INTEGER}}, /* see IPMI spec */ - {.info = {"_INI", 0, 0}}, - {.info = {"_IRC", 0, 0}}, - {.info = {"_LCK", 1, 0}}, - {.info = {"_LID", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_MAT", 0, ACPI_RTYPE_BUFFER}}, - {.info = {"_MLS", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2, ACPI_RTYPE_STRING, 2, 0, 0, 0}}, /* variable (Pkgs) each (2 Str) */ - {.info = {"_MSG", 1, 0}}, - {.info = {"_OFF", 0, 0}}, - {.info = {"_ON_", 0, 0}}, - {.info = {"_OS_", 0, ACPI_RTYPE_STRING}}, - {.info = {"_OSC", 4, ACPI_RTYPE_BUFFER}}, - {.info = {"_OST", 3, 0}}, - {.info = {"_PCL", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_PCT", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_BUFFER, 2, 0, 0, 0}}, /* fixed (2 Buf) */ - {.info = {"_PDC", 1, 0}}, - {.info = {"_PIC", 1, 0}}, - {.info = {"_PLD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_BUFFER, 0, 0, 0, 0}}, /* variable (Bufs) */ - {.info = {"_PPC", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_PPE", 0, ACPI_RTYPE_INTEGER}}, /* see dig64 spec */ - {.info = {"_PR0", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_PR1", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_PR2", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_PRS", 0, ACPI_RTYPE_BUFFER}}, + {{"_HPX", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each (var Ints) */ + {{{ACPI_PTYPE2_MIN, ACPI_RTYPE_INTEGER, 5,0}, 0,0}}, + + {{"_IFT", 0, ACPI_RTYPE_INTEGER}}, /* See IPMI spec */ + {{"_INI", 0, 0}}, + {{"_IRC", 0, 0}}, + {{"_LCK", 1, 0}}, + {{"_LID", 0, ACPI_RTYPE_INTEGER}}, + {{"_MAT", 0, ACPI_RTYPE_BUFFER}}, + {{"_MLS", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each (2 Str) */ + {{{ACPI_PTYPE2, ACPI_RTYPE_STRING, 2,0}, 0,0}}, + + {{"_MSG", 1, 0}}, + {{"_OFF", 0, 0}}, + {{"_ON_", 0, 0}}, + {{"_OS_", 0, ACPI_RTYPE_STRING}}, + {{"_OSC", 4, ACPI_RTYPE_BUFFER}}, + {{"_OST", 3, 0}}, + {{"_PCL", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_PCT", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (2 Buf) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_BUFFER, 2,0}, 0,0}}, + + {{"_PDC", 1, 0}}, + {{"_PIC", 1, 0}}, + {{"_PLD", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Bufs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_BUFFER, 0,0}, 0,0}}, + + {{"_PPC", 0, ACPI_RTYPE_INTEGER}}, + {{"_PPE", 0, ACPI_RTYPE_INTEGER}}, /* See dig64 spec */ + {{"_PR0", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_PR1", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_PR2", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_PRS", 0, ACPI_RTYPE_BUFFER}}, /* * For _PRT, many BIOSs reverse the 2nd and 3rd Package elements. This bug is so prevalent that there @@ -263,115 +320,141 @@ static const union acpi_predefined_info predefined_names[] = { * and issue a warning. To allow this and eliminate the warning, add the ACPI_RTYPE_REFERENCE * type to the 2nd element (index 1) in the statement below. */ - {.info = {"_PRT", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2_FIXED, 4, - ACPI_RTYPE_INTEGER, - ACPI_RTYPE_INTEGER, - ACPI_RTYPE_INTEGER | ACPI_RTYPE_REFERENCE, ACPI_RTYPE_INTEGER}}, /* variable (Pkgs) each (4): Int,Int,Int/Ref,Int */ - - {.info = {"_PRW", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_OPTION, 2, - ACPI_RTYPE_INTEGER | - ACPI_RTYPE_PACKAGE, - ACPI_RTYPE_INTEGER, ACPI_RTYPE_REFERENCE, 0}}, /* variable (Pkgs) each: Pkg/Int,Int,[variable Refs] (Pkg is Ref/Int) */ - - {.info = {"_PS0", 0, 0}}, - {.info = {"_PS1", 0, 0}}, - {.info = {"_PS2", 0, 0}}, - {.info = {"_PS3", 0, 0}}, - {.info = {"_PSC", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_PSD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2_COUNT, ACPI_RTYPE_INTEGER, 0, 0, 0, 0}}, /* variable (Pkgs) each (5 Int) with count */ - {.info = {"_PSL", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_PSR", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_PSS", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2, ACPI_RTYPE_INTEGER, 6, 0, 0, 0}}, /* variable (Pkgs) each (6 Int) */ - {.info = {"_PSV", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_PSW", 1, 0}}, - {.info = {"_PTC", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_BUFFER, 2, 0, 0, 0}}, /* fixed (2 Buf) */ - {.info = {"_PTS", 1, 0}}, - {.info = {"_PXM", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_REG", 2, 0}}, - {.info = {"_REV", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_RMV", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_ROM", 2, ACPI_RTYPE_BUFFER}}, - {.info = {"_RTV", 0, ACPI_RTYPE_INTEGER}}, + {{"_PRT", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each (4): Int,Int,Int/Ref,Int */ + {{{ACPI_PTYPE2_FIXED, 4, ACPI_RTYPE_INTEGER,ACPI_RTYPE_INTEGER}, + ACPI_RTYPE_INTEGER | ACPI_RTYPE_REFERENCE,ACPI_RTYPE_INTEGER}}, + + {{"_PRW", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each: Pkg/Int,Int,[Variable-length Refs] (Pkg is Ref/Int) */ + {{{ACPI_PTYPE1_OPTION, 2, ACPI_RTYPE_INTEGER | ACPI_RTYPE_PACKAGE, + ACPI_RTYPE_INTEGER}, ACPI_RTYPE_REFERENCE,0}}, + + {{"_PS0", 0, 0}}, + {{"_PS1", 0, 0}}, + {{"_PS2", 0, 0}}, + {{"_PS3", 0, 0}}, + {{"_PSC", 0, ACPI_RTYPE_INTEGER}}, + {{"_PSD", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each (5 Int) with count */ + {{{ACPI_PTYPE2_COUNT, ACPI_RTYPE_INTEGER,0,0}, 0,0}}, + + {{"_PSL", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_PSR", 0, ACPI_RTYPE_INTEGER}}, + {{"_PSS", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each (6 Int) */ + {{{ACPI_PTYPE2, ACPI_RTYPE_INTEGER, 6,0}, 0,0}}, + + {{"_PSV", 0, ACPI_RTYPE_INTEGER}}, + {{"_PSW", 1, 0}}, + {{"_PTC", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (2 Buf) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_BUFFER, 2,0}, 0,0}}, + + {{"_PTS", 1, 0}}, + {{"_PXM", 0, ACPI_RTYPE_INTEGER}}, + {{"_REG", 2, 0}}, + {{"_REV", 0, ACPI_RTYPE_INTEGER}}, + {{"_RMV", 0, ACPI_RTYPE_INTEGER}}, + {{"_ROM", 2, ACPI_RTYPE_BUFFER}}, + {{"_RTV", 0, ACPI_RTYPE_INTEGER}}, /* - * For _S0_ through _S5_, the ACPI spec defines a return Package containing 1 Integer, - * but most DSDTs have it wrong - 2,3, or 4 integers. Allow this by making the objects "variable length", - * but all elements must be Integers. + * For _S0_ through _S5_, the ACPI spec defines a return Package + * containing 1 Integer, but most DSDTs have it wrong - 2,3, or 4 integers. + * Allow this by making the objects "Variable-length length", but all elements + * must be Integers. */ - {.info = {"_S0_", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1, 0, 0, 0}}, /* fixed (1 Int) */ - {.info = {"_S1_", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1, 0, 0, 0}}, /* fixed (1 Int) */ - {.info = {"_S2_", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1, 0, 0, 0}}, /* fixed (1 Int) */ - {.info = {"_S3_", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1, 0, 0, 0}}, /* fixed (1 Int) */ - {.info = {"_S4_", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1, 0, 0, 0}}, /* fixed (1 Int) */ - {.info = {"_S5_", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1, 0, 0, 0}}, /* fixed (1 Int) */ - - {.info = {"_S1D", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_S2D", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_S3D", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_S4D", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_S0W", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_S1W", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_S2W", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_S3W", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_S4W", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_SBS", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_SCP", 0x13, 0}}, /* Acpi 1.0 allowed 1 arg. Acpi 3.0 expanded to 3 args. Allow both. */ - /* Note: the 3-arg definition may be removed for ACPI 4.0 */ - {.info = {"_SDD", 1, 0}}, - {.info = {"_SEG", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_SLI", 0, ACPI_RTYPE_BUFFER}}, - {.info = {"_SPD", 1, ACPI_RTYPE_INTEGER}}, - {.info = {"_SRS", 1, 0}}, - {.info = {"_SRV", 0, ACPI_RTYPE_INTEGER}}, /* see IPMI spec */ - {.info = {"_SST", 1, 0}}, - {.info = {"_STA", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_STM", 3, 0}}, - {.info = {"_STR", 0, ACPI_RTYPE_BUFFER}}, - {.info = {"_SUN", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_SWS", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_TC1", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_TC2", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_TMP", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_TPC", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_TPT", 1, 0}}, - {.info = {"_TRT", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2, ACPI_RTYPE_REFERENCE, 2, - ACPI_RTYPE_INTEGER, 6, 0}}, /* variable (Pkgs) each 2_ref/6_int */ - {.info = {"_TSD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2_COUNT, ACPI_RTYPE_INTEGER, 5, 0, 0, 0}}, /* variable (Pkgs) each 5_int with count */ - {.info = {"_TSP", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_TSS", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE2, ACPI_RTYPE_INTEGER, 5, 0, 0, 0}}, /* variable (Pkgs) each 5_int */ - {.info = {"_TST", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_TTS", 1, 0}}, - {.info = {"_TZD", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0, 0, 0}}, /* variable (Refs) */ - {.info = {"_TZM", 0, ACPI_RTYPE_REFERENCE}}, - {.info = {"_TZP", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_UID", 0, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING}}, - {.info = {"_UPC", 0, ACPI_RTYPE_PACKAGE}}, {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4, 0, 0, 0}}, /* fixed (4 Int) */ - {.info = {"_UPD", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_UPP", 0, ACPI_RTYPE_INTEGER}}, - {.info = {"_VPO", 0, ACPI_RTYPE_INTEGER}}, + {{"_S0_", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (1 Int) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1,0}, 0,0}}, + + {{"_S1_", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (1 Int) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1,0}, 0,0}}, + + {{"_S2_", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (1 Int) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1,0}, 0,0}}, + + {{"_S3_", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (1 Int) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1,0}, 0,0}}, + + {{"_S4_", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (1 Int) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1,0}, 0,0}}, + + {{"_S5_", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (1 Int) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 1,0}, 0,0}}, + + {{"_S1D", 0, ACPI_RTYPE_INTEGER}}, + {{"_S2D", 0, ACPI_RTYPE_INTEGER}}, + {{"_S3D", 0, ACPI_RTYPE_INTEGER}}, + {{"_S4D", 0, ACPI_RTYPE_INTEGER}}, + {{"_S0W", 0, ACPI_RTYPE_INTEGER}}, + {{"_S1W", 0, ACPI_RTYPE_INTEGER}}, + {{"_S2W", 0, ACPI_RTYPE_INTEGER}}, + {{"_S3W", 0, ACPI_RTYPE_INTEGER}}, + {{"_S4W", 0, ACPI_RTYPE_INTEGER}}, + {{"_SBS", 0, ACPI_RTYPE_INTEGER}}, + {{"_SCP", 0x13, 0}}, /* Acpi 1.0 allowed 1 arg. Acpi 3.0 expanded to 3 args. Allow both. */ + /* Note: the 3-arg definition may be removed for ACPI 4.0 */ + {{"_SDD", 1, 0}}, + {{"_SEG", 0, ACPI_RTYPE_INTEGER}}, + {{"_SLI", 0, ACPI_RTYPE_BUFFER}}, + {{"_SPD", 1, ACPI_RTYPE_INTEGER}}, + {{"_SRS", 1, 0}}, + {{"_SRV", 0, ACPI_RTYPE_INTEGER}}, /* See IPMI spec */ + {{"_SST", 1, 0}}, + {{"_STA", 0, ACPI_RTYPE_INTEGER}}, + {{"_STM", 3, 0}}, + {{"_STR", 0, ACPI_RTYPE_BUFFER}}, + {{"_SUN", 0, ACPI_RTYPE_INTEGER}}, + {{"_SWS", 0, ACPI_RTYPE_INTEGER}}, + {{"_TC1", 0, ACPI_RTYPE_INTEGER}}, + {{"_TC2", 0, ACPI_RTYPE_INTEGER}}, + {{"_TMP", 0, ACPI_RTYPE_INTEGER}}, + {{"_TPC", 0, ACPI_RTYPE_INTEGER}}, + {{"_TPT", 1, 0}}, + {{"_TRT", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each 2_ref/6_int */ + {{{ACPI_PTYPE2, ACPI_RTYPE_REFERENCE, 2, ACPI_RTYPE_INTEGER}, 6, 0}}, + + {{"_TSD", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each 5_int with count */ + {{{ACPI_PTYPE2_COUNT,ACPI_RTYPE_INTEGER, 5,0}, 0,0}}, + + {{"_TSP", 0, ACPI_RTYPE_INTEGER}}, + {{"_TSS", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each 5_int */ + {{{ACPI_PTYPE2, ACPI_RTYPE_INTEGER, 5,0}, 0,0}}, + + {{"_TST", 0, ACPI_RTYPE_INTEGER}}, + {{"_TTS", 1, 0}}, + {{"_TZD", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + + {{"_TZM", 0, ACPI_RTYPE_REFERENCE}}, + {{"_TZP", 0, ACPI_RTYPE_INTEGER}}, + {{"_UID", 0, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING}}, + {{"_UPC", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (4 Int) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4,0}, 0,0}}, + + {{"_UPD", 0, ACPI_RTYPE_INTEGER}}, + {{"_UPP", 0, ACPI_RTYPE_INTEGER}}, + {{"_VPO", 0, ACPI_RTYPE_INTEGER}}, /* Acpi 1.0 defined _WAK with no return value. Later, it was changed to return a package */ - {.info = {"_WAK", 1, ACPI_RTYPE_NONE | ACPI_RTYPE_INTEGER | ACPI_RTYPE_PACKAGE}}, - {.ret_info = {ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 2, 0, 0, 0}}, /* fixed (2 Int), but is optional */ - {.ret_info = {0, 0, 0, 0, 0, 0}} /* Table terminator */ + {{"_WAK", 1, ACPI_RTYPE_NONE | ACPI_RTYPE_INTEGER | ACPI_RTYPE_PACKAGE}}, + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 2,0}, 0,0}}, /* Fixed-length (2 Int), but is optional */ + + {{{0,0,0,0}, 0,0}} /* Table terminator */ }; #if 0 /* Not implemented */ -{ -"_WDG", 0, ACPI_RTYPE_BUFFER}, /* MS Extension */ + {{"_WDG", 0, ACPI_RTYPE_BUFFER}}, /* MS Extension */ + {{"_WED", 1, ACPI_RTYPE_PACKAGE}}, /* MS Extension */ -{ -"_WED", 1, ACPI_RTYPE_PACKAGE}, /* MS Extension */ + /* This is an internally implemented control method, no need to check */ + {{"_OSI", 1, ACPI_RTYPE_INTEGER}}, - /* This is an internally implemented control method, no need to check */ -{ -"_OSI", 1, ACPI_RTYPE_INTEGER}, + /* TBD: */ - /* TBD: */ - _PRT - currently ignore reversed entries.attempt to fix here ? - think about code that attempts to fix package elements like _BIF, etc. + _PRT - currently ignore reversed entries. attempt to fix here? + think about possibly fixing package elements like _BIF, etc. #endif + #endif -- cgit v0.10.2 From 999e08f99846a1fd6ee9642ec306a2d318925116 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Thu, 13 Aug 2009 14:30:16 +0800 Subject: ACPICA: ACPI 4: Add validation for new predefined names. Added 31 new names for ACPI 4.0. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/acpredef.h b/drivers/acpi/acpica/acpredef.h index c81f14b..cd80d1d 100644 --- a/drivers/acpi/acpica/acpredef.h +++ b/drivers/acpi/acpica/acpredef.h @@ -64,8 +64,8 @@ * (Used for _PRW) * * - * 2) PTYPE2 packages contain a variable number of sub-packages. Each of the - * different types describe the contents of each of the sub-packages. + * 2) PTYPE2 packages contain a Variable-length number of sub-packages. Each + * of the different types describe the contents of each of the sub-packages. * * ACPI_PTYPE2: Each subpackage contains 1 or 2 object types: * object type @@ -92,6 +92,7 @@ * (Used for _HPX) * * ACPI_PTYPE2_REV_FIXED: Revision at start, each subpackage is Fixed-length + * (Used for _ART, _FPS) * *****************************************************************************/ @@ -107,6 +108,7 @@ enum acpi_return_package_types { ACPI_PTYPE2_REV_FIXED = 9 }; +#ifdef ACPI_CREATE_PREDEFINED_TABLE /* * Predefined method/object information table. * @@ -189,21 +191,32 @@ static const union acpi_predefined_info predefined_names[] = {{{ACPI_PTYPE2, ACPI_RTYPE_INTEGER, 2,0}, 0,0}}, {{"_ALT", 0, ACPI_RTYPE_INTEGER}}, + {{"_ART", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (1 Int(rev), n Pkg (2 Ref/11 Int) */ + {{{ACPI_PTYPE2_REV_FIXED, ACPI_RTYPE_REFERENCE, 2, ACPI_RTYPE_INTEGER}, + 11, 0}}, + {{"_BBN", 0, ACPI_RTYPE_INTEGER}}, {{"_BCL", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Ints) */ {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 0,0}, 0,0}}, {{"_BCM", 1, 0}}, + {{"_BCT", 1, ACPI_RTYPE_INTEGER}}, {{"_BDN", 0, ACPI_RTYPE_INTEGER}}, {{"_BFS", 1, 0}}, {{"_BIF", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (9 Int),(4 Str) */ {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 9, ACPI_RTYPE_STRING}, 4,0}}, + {{"_BIX", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (16 Int),(4 Str) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 16, ACPI_RTYPE_STRING}, 4, + 0}}, + {{"_BLT", 3, 0}}, + {{"_BMA", 1, ACPI_RTYPE_INTEGER}}, {{"_BMC", 1, 0}}, {{"_BMD", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (5 Int) */ {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 5,0}, 0,0}}, + {{"_BMS", 1, ACPI_RTYPE_INTEGER}}, {{"_BQC", 0, ACPI_RTYPE_INTEGER}}, {{"_BST", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (4 Int) */ {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4,0}, 0,0}}, @@ -211,6 +224,7 @@ static const union acpi_predefined_info predefined_names[] = {{"_BTM", 1, ACPI_RTYPE_INTEGER}}, {{"_BTP", 1, 0}}, {{"_CBA", 0, ACPI_RTYPE_INTEGER}}, /* See PCI firmware spec 3.0 */ + {{"_CDM", 0, ACPI_RTYPE_INTEGER}}, {{"_CID", 0, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING | ACPI_RTYPE_PACKAGE}}, /* Variable-length (Ints/Strs) */ {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER | ACPI_RTYPE_STRING, 0,0}, 0,0}}, @@ -236,6 +250,7 @@ static const union acpi_predefined_info predefined_names[] = {{"_DSM", 4, ACPI_RTYPE_ALL}}, /* Must return a type, but it can be of any type */ {{"_DSS", 1, 0}}, {{"_DSW", 3, 0}}, + {{"_DTI", 1, 0}}, {{"_EC_", 0, ACPI_RTYPE_INTEGER}}, {{"_EDL", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs)*/ {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, @@ -251,9 +266,21 @@ static const union acpi_predefined_info predefined_names[] = {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 16,0}, 0,0}}, {{"_FDM", 1, 0}}, + {{"_FIF", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (4 Int) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 4, 0}, 0, 0}}, + {{"_FIX", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Ints) */ {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_INTEGER, 0,0}, 0,0}}, + {{"_FPS", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (1 Int(rev), n Pkg (5 Int) */ + {{{ACPI_PTYPE2_REV_FIXED, ACPI_RTYPE_INTEGER, 5, 0}, 0, 0}}, + + {{"_FSL", 1, 0}}, + {{"_FST", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (3 Int) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 3, 0}, 0, 0}}, + + {{"_GAI", 0, ACPI_RTYPE_INTEGER}}, + {{"_GHL", 0, ACPI_RTYPE_INTEGER}}, {{"_GLK", 0, ACPI_RTYPE_INTEGER}}, {{"_GPD", 0, ACPI_RTYPE_INTEGER}}, {{"_GPE", 0, ACPI_RTYPE_INTEGER}}, /* _GPE method, not _GPE scope */ @@ -281,15 +308,21 @@ static const union acpi_predefined_info predefined_names[] = {{"_LCK", 1, 0}}, {{"_LID", 0, ACPI_RTYPE_INTEGER}}, {{"_MAT", 0, ACPI_RTYPE_BUFFER}}, + {{"_MBM", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (8 Int) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 8, 0}, 0, 0}}, + {{"_MLS", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each (2 Str) */ {{{ACPI_PTYPE2, ACPI_RTYPE_STRING, 2,0}, 0,0}}, {{"_MSG", 1, 0}}, + {{"_MSM", 4, ACPI_RTYPE_INTEGER}}, + {{"_NTT", 0, ACPI_RTYPE_INTEGER}}, {{"_OFF", 0, 0}}, {{"_ON_", 0, 0}}, {{"_OS_", 0, ACPI_RTYPE_STRING}}, {{"_OSC", 4, ACPI_RTYPE_BUFFER}}, {{"_OST", 3, 0}}, + {{"_PAI", 1, ACPI_RTYPE_INTEGER}}, {{"_PCL", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, @@ -297,10 +330,22 @@ static const union acpi_predefined_info predefined_names[] = {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_BUFFER, 2,0}, 0,0}}, {{"_PDC", 1, 0}}, + {{"_PDL", 0, ACPI_RTYPE_INTEGER}}, {{"_PIC", 1, 0}}, + {{"_PIF", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (3 Int),(3 Str) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 3, ACPI_RTYPE_STRING}, 3, 0}}, + {{"_PLD", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Bufs) */ {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_BUFFER, 0,0}, 0,0}}, + {{"_PMC", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (11 Int),(3 Str) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 11, ACPI_RTYPE_STRING}, 3, + 0}}, + + {{"_PMD", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0}, 0, 0}}, + + {{"_PMM", 0, ACPI_RTYPE_INTEGER}}, {{"_PPC", 0, ACPI_RTYPE_INTEGER}}, {{"_PPE", 0, ACPI_RTYPE_INTEGER}}, /* See dig64 spec */ {{"_PR0", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ @@ -312,17 +357,26 @@ static const union acpi_predefined_info predefined_names[] = {{"_PR2", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0,0}, 0,0}}, + {{"_PR3", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0}, 0, 0}}, + + {{"_PRL", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Refs) */ + {{{ACPI_PTYPE1_VAR, ACPI_RTYPE_REFERENCE, 0, 0}, 0, 0}}, + {{"_PRS", 0, ACPI_RTYPE_BUFFER}}, /* - * For _PRT, many BIOSs reverse the 2nd and 3rd Package elements. This bug is so prevalent that there - * is code in the ACPICA Resource Manager to detect this and switch them back. For now, do not allow - * and issue a warning. To allow this and eliminate the warning, add the ACPI_RTYPE_REFERENCE - * type to the 2nd element (index 1) in the statement below. + * For _PRT, many BIOSs reverse the 3rd and 4th Package elements (Source + * and source_index). This bug is so prevalent that there is code in the + * ACPICA Resource Manager to detect this and switch them back. For now, + * do not allow and issue a warning. To allow this and eliminate the + * warning, add the ACPI_RTYPE_REFERENCE type to the 4th element (index 3) + * in the statement below. */ {{"_PRT", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each (4): Int,Int,Int/Ref,Int */ {{{ACPI_PTYPE2_FIXED, 4, ACPI_RTYPE_INTEGER,ACPI_RTYPE_INTEGER}, - ACPI_RTYPE_INTEGER | ACPI_RTYPE_REFERENCE,ACPI_RTYPE_INTEGER}}, + ACPI_RTYPE_INTEGER | ACPI_RTYPE_REFERENCE, + ACPI_RTYPE_INTEGER}}, {{"_PRW", 0, ACPI_RTYPE_PACKAGE}}, /* Variable-length (Pkgs) each: Pkg/Int,Int,[Variable-length Refs] (Pkg is Ref/Int) */ {{{ACPI_PTYPE1_OPTION, 2, ACPI_RTYPE_INTEGER | ACPI_RTYPE_PACKAGE, @@ -348,7 +402,11 @@ static const union acpi_predefined_info predefined_names[] = {{"_PTC", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (2 Buf) */ {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_BUFFER, 2,0}, 0,0}}, + {{"_PTP", 2, ACPI_RTYPE_INTEGER}}, {{"_PTS", 1, 0}}, + {{"_PUR", 0, ACPI_RTYPE_PACKAGE}}, /* Fixed-length (2 Int) */ + {{{ACPI_PTYPE1_FIXED, ACPI_RTYPE_INTEGER, 2, 0}, 0, 0}}, + {{"_PXM", 0, ACPI_RTYPE_INTEGER}}, {{"_REG", 2, 0}}, {{"_REV", 0, ACPI_RTYPE_INTEGER}}, @@ -394,6 +452,7 @@ static const union acpi_predefined_info predefined_names[] = /* Note: the 3-arg definition may be removed for ACPI 4.0 */ {{"_SDD", 1, 0}}, {{"_SEG", 0, ACPI_RTYPE_INTEGER}}, + {{"_SHL", 1, ACPI_RTYPE_INTEGER}}, {{"_SLI", 0, ACPI_RTYPE_BUFFER}}, {{"_SPD", 1, ACPI_RTYPE_INTEGER}}, {{"_SRS", 1, 0}}, @@ -401,11 +460,15 @@ static const union acpi_predefined_info predefined_names[] = {{"_SST", 1, 0}}, {{"_STA", 0, ACPI_RTYPE_INTEGER}}, {{"_STM", 3, 0}}, + {{"_STP", 2, ACPI_RTYPE_INTEGER}}, {{"_STR", 0, ACPI_RTYPE_BUFFER}}, + {{"_STV", 2, ACPI_RTYPE_INTEGER}}, {{"_SUN", 0, ACPI_RTYPE_INTEGER}}, {{"_SWS", 0, ACPI_RTYPE_INTEGER}}, {{"_TC1", 0, ACPI_RTYPE_INTEGER}}, {{"_TC2", 0, ACPI_RTYPE_INTEGER}}, + {{"_TIP", 1, ACPI_RTYPE_INTEGER}}, + {{"_TIV", 1, ACPI_RTYPE_INTEGER}}, {{"_TMP", 0, ACPI_RTYPE_INTEGER}}, {{"_TPC", 0, ACPI_RTYPE_INTEGER}}, {{"_TPT", 1, 0}}, @@ -458,3 +521,4 @@ static const union acpi_predefined_info predefined_names[] = #endif #endif +#endif diff --git a/drivers/acpi/acpica/nspredef.c b/drivers/acpi/acpica/nspredef.c index 0b2cdb3..8314e6a 100644 --- a/drivers/acpi/acpica/nspredef.c +++ b/drivers/acpi/acpica/nspredef.c @@ -42,6 +42,8 @@ * POSSIBILITY OF SUCH DAMAGES. */ +#define ACPI_CREATE_PREDEFINED_TABLE + #include #include "accommon.h" #include "acnamesp.h" -- cgit v0.10.2 From 7f0c826a437157d2b19662977e9cf3b472cf24a6 Mon Sep 17 00:00:00 2001 From: Lin Ming Date: Thu, 13 Aug 2009 14:03:15 +0800 Subject: ACPICA: Add support for module-level executable AML code Add limited support for executable AML code that exists outside of any control method. This type of code has been illegal since ACPI 2.0. The code must exist in an If/Else/While block. All AML tables are supported, including tables that are dynamically loaded. ACPICA BZ 762. http://acpica.org/bugzilla/show_bug.cgi?id=762 Signed-off-by: Lin Ming Signed-off-by: Bob Moore Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/acglobal.h b/drivers/acpi/acpica/acglobal.h index 6389f7c..29ba66d 100644 --- a/drivers/acpi/acpica/acglobal.h +++ b/drivers/acpi/acpica/acglobal.h @@ -295,6 +295,7 @@ extern char const *acpi_gbl_exception_names_ctrl[]; ACPI_EXTERN struct acpi_namespace_node acpi_gbl_root_node_struct; ACPI_EXTERN struct acpi_namespace_node *acpi_gbl_root_node; ACPI_EXTERN struct acpi_namespace_node *acpi_gbl_fadt_gpe_device; +ACPI_EXTERN union acpi_operand_object *acpi_gbl_module_code_list; extern const u8 acpi_gbl_ns_properties[ACPI_NUM_NS_TYPES]; extern const struct acpi_predefined_names diff --git a/drivers/acpi/acpica/acnamesp.h b/drivers/acpi/acpica/acnamesp.h index f75a7a0..09a2764 100644 --- a/drivers/acpi/acpica/acnamesp.h +++ b/drivers/acpi/acpica/acnamesp.h @@ -196,6 +196,8 @@ acpi_ns_dump_objects(acpi_object_type type, */ acpi_status acpi_ns_evaluate(struct acpi_evaluate_info *info); +void acpi_ns_exec_module_code_list(void); + /* * nspredef - Support for predefined/reserved names */ diff --git a/drivers/acpi/acpica/acobject.h b/drivers/acpi/acpica/acobject.h index eb6f038..b39d682 100644 --- a/drivers/acpi/acpica/acobject.h +++ b/drivers/acpi/acpica/acobject.h @@ -98,6 +98,7 @@ #define AOPOBJ_SETUP_COMPLETE 0x10 #define AOPOBJ_SINGLE_DATUM 0x20 #define AOPOBJ_INVALID 0x40 /* Used if host OS won't allow an op_region address */ +#define AOPOBJ_MODULE_LEVEL 0x80 /****************************************************************************** * diff --git a/drivers/acpi/acpica/acparser.h b/drivers/acpi/acpica/acparser.h index 23ee0fb..22881e8 100644 --- a/drivers/acpi/acpica/acparser.h +++ b/drivers/acpi/acpica/acparser.h @@ -62,6 +62,8 @@ #define ACPI_PARSE_DEFERRED_OP 0x0100 #define ACPI_PARSE_DISASSEMBLE 0x0200 +#define ACPI_PARSE_MODULE_LEVEL 0x0400 + /****************************************************************************** * * Parser interfaces diff --git a/drivers/acpi/acpica/dsfield.c b/drivers/acpi/acpica/dsfield.c index 53e27bc..54a225e 100644 --- a/drivers/acpi/acpica/dsfield.c +++ b/drivers/acpi/acpica/dsfield.c @@ -123,9 +123,12 @@ acpi_ds_create_buffer_field(union acpi_parse_object *op, flags = ACPI_NS_NO_UPSEARCH | ACPI_NS_DONT_OPEN_SCOPE | ACPI_NS_ERROR_IF_FOUND; - /* Mark node temporary if we are executing a method */ - - if (walk_state->method_node) { + /* + * Mark node temporary if we are executing a normal control + * method. (Don't mark if this is a module-level code method) + */ + if (walk_state->method_node && + !(walk_state->parse_flags & ACPI_PARSE_MODULE_LEVEL)) { flags |= ACPI_NS_TEMPORARY; } @@ -456,9 +459,12 @@ acpi_ds_init_field_objects(union acpi_parse_object *op, flags = ACPI_NS_NO_UPSEARCH | ACPI_NS_DONT_OPEN_SCOPE | ACPI_NS_ERROR_IF_FOUND; - /* Mark node(s) temporary if we are executing a method */ - - if (walk_state->method_node) { + /* + * Mark node(s) temporary if we are executing a normal control + * method. (Don't mark if this is a module-level code method) + */ + if (walk_state->method_node && + !(walk_state->parse_flags & ACPI_PARSE_MODULE_LEVEL)) { flags |= ACPI_NS_TEMPORARY; } diff --git a/drivers/acpi/acpica/dsmethod.c b/drivers/acpi/acpica/dsmethod.c index 14b8b8e..567a489 100644 --- a/drivers/acpi/acpica/dsmethod.c +++ b/drivers/acpi/acpica/dsmethod.c @@ -578,10 +578,15 @@ acpi_ds_terminate_control_method(union acpi_operand_object *method_desc, } /* - * Delete any namespace objects created anywhere within - * the namespace by the execution of this method + * Delete any namespace objects created anywhere within the + * namespace by the execution of this method. Unless this method + * is a module-level executable code method, in which case we + * want make the objects permanent. */ - acpi_ns_delete_namespace_by_owner(method_desc->method.owner_id); + if (!(method_desc->method.flags & AOPOBJ_MODULE_LEVEL)) { + acpi_ns_delete_namespace_by_owner(method_desc->method. + owner_id); + } } /* Decrement the thread count on the method */ @@ -622,7 +627,9 @@ acpi_ds_terminate_control_method(union acpi_operand_object *method_desc, /* No more threads, we can free the owner_id */ - acpi_ut_release_owner_id(&method_desc->method.owner_id); + if (!(method_desc->method.flags & AOPOBJ_MODULE_LEVEL)) { + acpi_ut_release_owner_id(&method_desc->method.owner_id); + } } return_VOID; diff --git a/drivers/acpi/acpica/dswload.c b/drivers/acpi/acpica/dswload.c index 3023cea..6de3a99 100644 --- a/drivers/acpi/acpica/dswload.c +++ b/drivers/acpi/acpica/dswload.c @@ -581,21 +581,6 @@ acpi_ds_load2_begin_op(struct acpi_walk_state *walk_state, if ((!(walk_state->op_info->flags & AML_NSOPCODE) && (walk_state->opcode != AML_INT_NAMEPATH_OP)) || (!(walk_state->op_info->flags & AML_NAMED))) { -#ifdef ACPI_ENABLE_MODULE_LEVEL_CODE - if ((walk_state->op_info->class == AML_CLASS_EXECUTE) || - (walk_state->op_info->class == AML_CLASS_CONTROL)) { - ACPI_DEBUG_PRINT((ACPI_DB_DISPATCH, - "Begin/EXEC: %s (fl %8.8X)\n", - walk_state->op_info->name, - walk_state->op_info->flags)); - - /* Executing a type1 or type2 opcode outside of a method */ - - status = - acpi_ds_exec_begin_op(walk_state, out_op); - return_ACPI_STATUS(status); - } -#endif return_ACPI_STATUS(AE_OK); } @@ -768,7 +753,13 @@ acpi_ds_load2_begin_op(struct acpi_walk_state *walk_state, /* Execution mode, node cannot already exist, node is temporary */ - flags |= (ACPI_NS_ERROR_IF_FOUND | ACPI_NS_TEMPORARY); + flags |= ACPI_NS_ERROR_IF_FOUND; + + if (! + (walk_state-> + parse_flags & ACPI_PARSE_MODULE_LEVEL)) { + flags |= ACPI_NS_TEMPORARY; + } } /* Add new entry or lookup existing entry */ @@ -851,24 +842,6 @@ acpi_status acpi_ds_load2_end_op(struct acpi_walk_state *walk_state) /* Check if opcode had an associated namespace object */ if (!(walk_state->op_info->flags & AML_NSOBJECT)) { -#ifndef ACPI_NO_METHOD_EXECUTION -#ifdef ACPI_ENABLE_MODULE_LEVEL_CODE - /* No namespace object. Executable opcode? */ - - if ((walk_state->op_info->class == AML_CLASS_EXECUTE) || - (walk_state->op_info->class == AML_CLASS_CONTROL)) { - ACPI_DEBUG_PRINT((ACPI_DB_DISPATCH, - "End/EXEC: %s (fl %8.8X)\n", - walk_state->op_info->name, - walk_state->op_info->flags)); - - /* Executing a type1 or type2 opcode outside of a method */ - - status = acpi_ds_exec_end_op(walk_state); - return_ACPI_STATUS(status); - } -#endif -#endif return_ACPI_STATUS(AE_OK); } diff --git a/drivers/acpi/acpica/exconfig.c b/drivers/acpi/acpica/exconfig.c index 277fd60..24afef8 100644 --- a/drivers/acpi/acpica/exconfig.c +++ b/drivers/acpi/acpica/exconfig.c @@ -110,8 +110,15 @@ acpi_ex_add_table(u32 table_index, if (ACPI_FAILURE(status)) { acpi_ut_remove_reference(obj_desc); *ddb_handle = NULL; + return_ACPI_STATUS(status); } + /* Execute any module-level code that was found in the table */ + + acpi_ex_exit_interpreter(); + acpi_ns_exec_module_code_list(); + acpi_ex_enter_interpreter(); + return_ACPI_STATUS(status); } diff --git a/drivers/acpi/acpica/nseval.c b/drivers/acpi/acpica/nseval.c index 8e7dec1..846d113 100644 --- a/drivers/acpi/acpica/nseval.c +++ b/drivers/acpi/acpica/nseval.c @@ -50,6 +50,11 @@ #define _COMPONENT ACPI_NAMESPACE ACPI_MODULE_NAME("nseval") +/* Local prototypes */ +static void +acpi_ns_exec_module_code(union acpi_operand_object *method_obj, + struct acpi_evaluate_info *info); + /******************************************************************************* * * FUNCTION: acpi_ns_evaluate @@ -76,6 +81,7 @@ ACPI_MODULE_NAME("nseval") * MUTEX: Locks interpreter * ******************************************************************************/ + acpi_status acpi_ns_evaluate(struct acpi_evaluate_info * info) { acpi_status status; @@ -276,3 +282,134 @@ acpi_status acpi_ns_evaluate(struct acpi_evaluate_info * info) */ return_ACPI_STATUS(status); } + +/******************************************************************************* + * + * FUNCTION: acpi_ns_exec_module_code_list + * + * PARAMETERS: None + * + * RETURN: None. Exceptions during method execution are ignored, since + * we cannot abort a table load. + * + * DESCRIPTION: Execute all elements of the global module-level code list. + * Each element is executed as a single control method. + * + ******************************************************************************/ + +void acpi_ns_exec_module_code_list(void) +{ + union acpi_operand_object *prev; + union acpi_operand_object *next; + struct acpi_evaluate_info *info; + u32 method_count = 0; + + ACPI_FUNCTION_TRACE(ns_exec_module_code_list); + + /* Exit now if the list is empty */ + + next = acpi_gbl_module_code_list; + if (!next) { + return_VOID; + } + + /* Allocate the evaluation information block */ + + info = ACPI_ALLOCATE(sizeof(struct acpi_evaluate_info)); + if (!info) { + return_VOID; + } + + /* Walk the list, executing each "method" */ + + while (next) { + prev = next; + next = next->method.mutex; + + /* Clear the link field and execute the method */ + + prev->method.mutex = NULL; + acpi_ns_exec_module_code(prev, info); + method_count++; + + /* Delete the (temporary) method object */ + + acpi_ut_remove_reference(prev); + } + + ACPI_INFO((AE_INFO, + "Executed %u blocks of module-level executable AML code", + method_count)); + + ACPI_FREE(info); + acpi_gbl_module_code_list = NULL; + return_VOID; +} + +/******************************************************************************* + * + * FUNCTION: acpi_ns_exec_module_code + * + * PARAMETERS: method_obj - Object container for the module-level code + * Info - Info block for method evaluation + * + * RETURN: None. Exceptions during method execution are ignored, since + * we cannot abort a table load. + * + * DESCRIPTION: Execute a control method containing a block of module-level + * executable AML code. The control method is temporarily + * installed to the root node, then evaluated. + * + ******************************************************************************/ + +static void +acpi_ns_exec_module_code(union acpi_operand_object *method_obj, + struct acpi_evaluate_info *info) +{ + union acpi_operand_object *root_obj; + acpi_status status; + + ACPI_FUNCTION_TRACE(ns_exec_module_code); + + /* Initialize the evaluation information block */ + + ACPI_MEMSET(info, 0, sizeof(struct acpi_evaluate_info)); + info->prefix_node = acpi_gbl_root_node; + + /* + * Get the currently attached root object. Add a reference, because the + * ref count will be decreased when the method object is installed to + * the root node. + */ + root_obj = acpi_ns_get_attached_object(acpi_gbl_root_node); + acpi_ut_add_reference(root_obj); + + /* Install the method (module-level code) in the root node */ + + status = acpi_ns_attach_object(acpi_gbl_root_node, method_obj, + ACPI_TYPE_METHOD); + if (ACPI_FAILURE(status)) { + goto exit; + } + + /* Execute the root node as a control method */ + + status = acpi_ns_evaluate(info); + + ACPI_DEBUG_PRINT((ACPI_DB_INIT, "Executed module-level code at %p\n", + method_obj->method.aml_start)); + + /* Detach the temporary method object */ + + acpi_ns_detach_object(acpi_gbl_root_node); + + /* Restore the original root object */ + + status = + acpi_ns_attach_object(acpi_gbl_root_node, root_obj, + ACPI_TYPE_DEVICE); + + exit: + acpi_ut_remove_reference(root_obj); + return_VOID; +} diff --git a/drivers/acpi/acpica/psloop.c b/drivers/acpi/acpica/psloop.c index c5f6ce1..cd7995b 100644 --- a/drivers/acpi/acpica/psloop.c +++ b/drivers/acpi/acpica/psloop.c @@ -86,6 +86,9 @@ static acpi_status acpi_ps_complete_final_op(struct acpi_walk_state *walk_state, union acpi_parse_object *op, acpi_status status); +static void +acpi_ps_link_module_code(u8 *aml_start, u32 aml_length, acpi_owner_id owner_id); + /******************************************************************************* * * FUNCTION: acpi_ps_get_aml_opcode @@ -390,6 +393,7 @@ acpi_ps_get_arguments(struct acpi_walk_state *walk_state, { acpi_status status = AE_OK; union acpi_parse_object *arg = NULL; + const struct acpi_opcode_info *op_info; ACPI_FUNCTION_TRACE_PTR(ps_get_arguments, walk_state); @@ -449,13 +453,11 @@ acpi_ps_get_arguments(struct acpi_walk_state *walk_state, INCREMENT_ARG_LIST(walk_state->arg_types); } - /* Special processing for certain opcodes */ - - /* TBD (remove): Temporary mechanism to disable this code if needed */ - -#ifdef ACPI_ENABLE_MODULE_LEVEL_CODE - - if ((walk_state->pass_number <= ACPI_IMODE_LOAD_PASS1) && + /* + * Handle executable code at "module-level". This refers to + * executable opcodes that appear outside of any control method. + */ + if ((walk_state->pass_number <= ACPI_IMODE_LOAD_PASS2) && ((walk_state->parse_flags & ACPI_PARSE_DISASSEMBLE) == 0)) { /* * We want to skip If/Else/While constructs during Pass1 because we @@ -469,6 +471,23 @@ acpi_ps_get_arguments(struct acpi_walk_state *walk_state, case AML_ELSE_OP: case AML_WHILE_OP: + /* + * Currently supported module-level opcodes are: + * IF/ELSE/WHILE. These appear to be the most common, + * and easiest to support since they open an AML + * package. + */ + if (walk_state->pass_number == + ACPI_IMODE_LOAD_PASS1) { + acpi_ps_link_module_code(aml_op_start, + walk_state-> + parser_state. + pkg_end - + aml_op_start, + walk_state-> + owner_id); + } + ACPI_DEBUG_PRINT((ACPI_DB_PARSE, "Pass1: Skipping an If/Else/While body\n")); @@ -480,10 +499,34 @@ acpi_ps_get_arguments(struct acpi_walk_state *walk_state, break; default: + /* + * Check for an unsupported executable opcode at module + * level. We must be in PASS1, the parent must be a SCOPE, + * The opcode class must be EXECUTE, and the opcode must + * not be an argument to another opcode. + */ + if ((walk_state->pass_number == + ACPI_IMODE_LOAD_PASS1) + && (op->common.parent->common.aml_opcode == + AML_SCOPE_OP)) { + op_info = + acpi_ps_get_opcode_info(op->common. + aml_opcode); + if ((op_info->class == + AML_CLASS_EXECUTE) && (!arg)) { + ACPI_WARNING((AE_INFO, + "Detected an unsupported executable opcode " + "at module-level: [0x%.4X] at table offset 0x%.4X", + op->common.aml_opcode, + (u32)((aml_op_start - walk_state->parser_state.aml_start) + + sizeof(struct acpi_table_header)))); + } + } break; } } -#endif + + /* Special processing for certain opcodes */ switch (op->common.aml_opcode) { case AML_METHOD_OP: @@ -553,6 +596,66 @@ acpi_ps_get_arguments(struct acpi_walk_state *walk_state, /******************************************************************************* * + * FUNCTION: acpi_ps_link_module_code + * + * PARAMETERS: aml_start - Pointer to the AML + * aml_length - Length of executable AML + * owner_id - owner_id of module level code + * + * RETURN: None. + * + * DESCRIPTION: Wrap the module-level code with a method object and link the + * object to the global list. Note, the mutex field of the method + * object is used to link multiple module-level code objects. + * + ******************************************************************************/ + +static void +acpi_ps_link_module_code(u8 *aml_start, u32 aml_length, acpi_owner_id owner_id) +{ + union acpi_operand_object *prev; + union acpi_operand_object *next; + union acpi_operand_object *method_obj; + + /* Get the tail of the list */ + + prev = next = acpi_gbl_module_code_list; + while (next) { + prev = next; + next = next->method.mutex; + } + + /* + * Insert the module level code into the list. Merge it if it is + * adjacent to the previous element. + */ + if (!prev || + ((prev->method.aml_start + prev->method.aml_length) != aml_start)) { + + /* Create, initialize, and link a new temporary method object */ + + method_obj = acpi_ut_create_internal_object(ACPI_TYPE_METHOD); + if (!method_obj) { + return; + } + + method_obj->method.aml_start = aml_start; + method_obj->method.aml_length = aml_length; + method_obj->method.owner_id = owner_id; + method_obj->method.flags |= AOPOBJ_MODULE_LEVEL; + + if (!prev) { + acpi_gbl_module_code_list = method_obj; + } else { + prev->method.mutex = method_obj; + } + } else { + prev->method.aml_length += aml_length; + } +} + +/******************************************************************************* + * * FUNCTION: acpi_ps_complete_op * * PARAMETERS: walk_state - Current state diff --git a/drivers/acpi/acpica/psxface.c b/drivers/acpi/acpica/psxface.c index ff06032..dd9731c 100644 --- a/drivers/acpi/acpica/psxface.c +++ b/drivers/acpi/acpica/psxface.c @@ -280,6 +280,10 @@ acpi_status acpi_ps_execute_method(struct acpi_evaluate_info *info) goto cleanup; } + if (info->obj_desc->method.flags & AOPOBJ_MODULE_LEVEL) { + walk_state->parse_flags |= ACPI_PARSE_MODULE_LEVEL; + } + /* Invoke an internal method if necessary */ if (info->obj_desc->method.method_flags & AML_METHOD_INTERNAL_ONLY) { diff --git a/drivers/acpi/acpica/utglobal.c b/drivers/acpi/acpica/utglobal.c index 9e33b62..3f2c68f 100644 --- a/drivers/acpi/acpica/utglobal.c +++ b/drivers/acpi/acpica/utglobal.c @@ -807,6 +807,7 @@ acpi_status acpi_ut_init_globals(void) /* Namespace */ + acpi_gbl_module_code_list = NULL; acpi_gbl_root_node = NULL; acpi_gbl_root_node_struct.name.integer = ACPI_ROOT_NAME; acpi_gbl_root_node_struct.descriptor_type = ACPI_DESC_TYPE_NAMED; diff --git a/drivers/acpi/acpica/utxface.c b/drivers/acpi/acpica/utxface.c index 483edbb..b1f5f68 100644 --- a/drivers/acpi/acpica/utxface.c +++ b/drivers/acpi/acpica/utxface.c @@ -251,6 +251,16 @@ acpi_status acpi_initialize_objects(u32 flags) } /* + * Execute any module-level code that was detected during the table load + * phase. Although illegal since ACPI 2.0, there are many machines that + * contain this type of code. Each block of detected executable AML code + * outside of any control method is wrapped with a temporary control + * method object and placed on a global list. The methods on this list + * are executed below. + */ + acpi_ns_exec_module_code_list(); + + /* * Initialize the objects that remain uninitialized. This runs the * executable AML that may be part of the declaration of these objects: * operation_regions, buffer_fields, Buffers, and Packages. -- cgit v0.10.2 From c276e3884163355464a76e60ed9e272b52b4acc2 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Mon, 27 Jul 2009 14:55:02 +0800 Subject: ACPICA: Update definitions for HEST table Eliminate duplicated code in disassembler. Shorten identifiers that were too long. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 0417f2a..34b10c0 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -427,17 +427,17 @@ struct acpi_hest_aer_common { u16 reserved1; u8 flags; u8 enabled; - u32 records_to_pre_allocate; + u32 records_to_preallocate; u32 max_sections_per_record; u32 bus; u16 device; u16 function; u16 device_control; u16 reserved2; - u32 uncorrectable_error_mask; - u32 uncorrectable_error_severity; - u32 correctable_error_mask; - u32 advanced_error_capabilities; + u32 uncorrectable_mask; + u32 uncorrectable_severity; + u32 correctable_mask; + u32 advanced_capabilities; }; /* Masks for HEST Flags fields */ @@ -490,7 +490,7 @@ struct acpi_hest_ia_machine_check { u16 reserved1; u8 flags; u8 enabled; - u32 records_to_pre_allocate; + u32 records_to_preallocate; u32 max_sections_per_record; u64 global_capability_data; u64 global_control_data; @@ -505,7 +505,7 @@ struct acpi_table_hest_ia_corrected { u16 reserved1; u8 flags; u8 enabled; - u32 records_to_pre_allocate; + u32 records_to_preallocate; u32 max_sections_per_record; struct acpi_hest_notify notify; u8 num_hardware_banks; @@ -517,7 +517,7 @@ struct acpi_table_hest_ia_corrected { struct acpi_hest_ia_nmi { struct acpi_hest_header header; u32 reserved; - u32 records_to_pre_allocate; + u32 records_to_preallocate; u32 max_sections_per_record; u32 max_raw_data_length; }; @@ -544,9 +544,9 @@ struct acpi_hest_aer { struct acpi_hest_aer_bridge { struct acpi_hest_header header; struct acpi_hest_aer_common aer; - u32 second_uncorrectable_error_mask; - u32 second_uncorrectable_error_severity; - u32 second_advanced_capabilities; + u32 uncorrectable_mask2; + u32 uncorrectable_severity2; + u32 advanced_capabilities2; }; /* 9: Generic Hardware Error Source */ @@ -556,7 +556,7 @@ struct acpi_hest_generic { u16 related_source_id; u8 reserved; u8 enabled; - u32 records_to_pre_allocate; + u32 records_to_preallocate; u32 max_sections_per_record; u32 max_raw_data_length; struct acpi_generic_address error_status_address; -- cgit v0.10.2 From 1872bbc94b2d092ece22a8fbf1c3e81f0fba0052 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Thu, 13 Aug 2009 13:31:00 +0800 Subject: ACPICA: Fix typo for HEST ACPI table Problem with the name of one of the subtables. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 34b10c0..0b9b430 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -500,7 +500,7 @@ struct acpi_hest_ia_machine_check { /* 1: IA32 Corrected Machine Check */ -struct acpi_table_hest_ia_corrected { +struct acpi_hest_ia_corrected { struct acpi_hest_header header; u16 reserved1; u8 flags; -- cgit v0.10.2 From 8a964236800839263b3dddd7f7851d666e7d53e1 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Thu, 13 Aug 2009 13:42:19 +0800 Subject: ACPICA: acpi_reset: Bypass port validation mechanism Allow writes to reserved ports. This change may eventually be driven down in to acpi_write and acpi_read. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/hwxface.c b/drivers/acpi/acpica/hwxface.c index 4ead85f..647c7b6 100644 --- a/drivers/acpi/acpica/hwxface.c +++ b/drivers/acpi/acpica/hwxface.c @@ -78,9 +78,22 @@ acpi_status acpi_reset(void) return_ACPI_STATUS(AE_NOT_EXIST); } - /* Write the reset value to the reset register */ + if (reset_reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { + /* + * For I/O space, write directly to the OSL. This bypasses the port + * validation mechanism, which may block a valid write to the reset + * register. + */ + status = + acpi_os_write_port((acpi_io_address) reset_reg->address, + acpi_gbl_FADT.reset_value, + reset_reg->bit_width); + } else { + /* Write the reset value to the reset register */ + + status = acpi_hw_write(acpi_gbl_FADT.reset_value, reset_reg); + } - status = acpi_hw_write(acpi_gbl_FADT.reset_value, reset_reg); return_ACPI_STATUS(status); } -- cgit v0.10.2 From 49ae80c9944401222e47108883c486b5a5a24006 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Thu, 13 Aug 2009 13:43:12 +0800 Subject: ACPICA: Update version to 20090730 Version 20090730. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index 063e577..f3b358b 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -47,7 +47,7 @@ /* Current ACPICA subsystem version in YYYYMMDD format */ -#define ACPI_CA_VERSION 0x20090625 +#define ACPI_CA_VERSION 0x20090730 #include "actypes.h" #include "actbl.h" -- cgit v0.10.2 From a192a9580bcc41692be1f36b77c3b681827f566a Mon Sep 17 00:00:00 2001 From: Len Brown Date: Tue, 28 Jul 2009 16:45:54 -0400 Subject: ACPI: Move definition of PREFIX from acpi_bus.h to internal..h Linux/ACPI core files using internal.h all PREFIX "ACPI: ", however, not all ACPI drivers use/want it -- and they should not have to #undef PREFIX to define their own. Add GPL commment to internal.h while we are there. This does not change any actual console output, asside from a whitespace fix. Signed-off-by: Len Brown diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 712443e..81d3466 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -18,6 +18,8 @@ #include #include +#define PREFIX "ACPI: " + /* aperture is up to 256MB but BIOS may reserve less */ #define MMCONFIG_APER_MIN (2 * 1024*1024) #define MMCONFIG_APER_MAX (256 * 1024*1024) diff --git a/drivers/acpi/ac.c b/drivers/acpi/ac.c index 0df8fcb..98b9690 100644 --- a/drivers/acpi/ac.c +++ b/drivers/acpi/ac.c @@ -37,6 +37,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_AC_CLASS "ac_adapter" #define ACPI_AC_DEVICE_NAME "AC Adapter" #define ACPI_AC_FILE_STATE "state" diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c index 58b4517..f8c3d1b 100644 --- a/drivers/acpi/battery.c +++ b/drivers/acpi/battery.c @@ -45,6 +45,8 @@ #include #endif +#define PREFIX "ACPI: " + #define ACPI_BATTERY_VALUE_UNKNOWN 0xFFFFFFFF #define ACPI_BATTERY_CLASS "battery" diff --git a/drivers/acpi/blacklist.c b/drivers/acpi/blacklist.c index f6baa77..19152ea 100644 --- a/drivers/acpi/blacklist.c +++ b/drivers/acpi/blacklist.c @@ -34,6 +34,8 @@ #include #include +#include "internal.h" + enum acpi_blacklist_predicates { all_versions, less_than_or_equal, diff --git a/drivers/acpi/button.c b/drivers/acpi/button.c index 9195deb..d295bdc 100644 --- a/drivers/acpi/button.c +++ b/drivers/acpi/button.c @@ -33,6 +33,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_BUTTON_CLASS "button" #define ACPI_BUTTON_FILE_INFO "info" #define ACPI_BUTTON_FILE_STATE "state" diff --git a/drivers/acpi/cm_sbs.c b/drivers/acpi/cm_sbs.c index 332fe4b..6c9ee68 100644 --- a/drivers/acpi/cm_sbs.c +++ b/drivers/acpi/cm_sbs.c @@ -28,6 +28,8 @@ #include #include +#define PREFIX "ACPI: " + ACPI_MODULE_NAME("cm_sbs"); #define ACPI_AC_CLASS "ac_adapter" #define ACPI_BATTERY_CLASS "battery" diff --git a/drivers/acpi/container.c b/drivers/acpi/container.c index fe0cdf8..5f2c3c0 100644 --- a/drivers/acpi/container.c +++ b/drivers/acpi/container.c @@ -35,6 +35,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_CONTAINER_DEVICE_NAME "ACPI container device" #define ACPI_CONTAINER_CLASS "container" diff --git a/drivers/acpi/dock.c b/drivers/acpi/dock.c index efb959d..9a85566 100644 --- a/drivers/acpi/dock.c +++ b/drivers/acpi/dock.c @@ -33,6 +33,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_DOCK_DRIVER_DESCRIPTION "ACPI Dock Station Driver" ACPI_MODULE_NAME("dock"); diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index 391f331..5180f0f 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -47,7 +47,6 @@ #define ACPI_EC_DEVICE_NAME "Embedded Controller" #define ACPI_EC_FILE_INFO "info" -#undef PREFIX #define PREFIX "ACPI: EC: " /* EC status register */ diff --git a/drivers/acpi/event.c b/drivers/acpi/event.c index aeb7e5f..c511071 100644 --- a/drivers/acpi/event.c +++ b/drivers/acpi/event.c @@ -14,6 +14,8 @@ #include #include +#include "internal.h" + #define _COMPONENT ACPI_SYSTEM_COMPONENT ACPI_MODULE_NAME("event"); diff --git a/drivers/acpi/fan.c b/drivers/acpi/fan.c index 53698ea..f419849 100644 --- a/drivers/acpi/fan.c +++ b/drivers/acpi/fan.c @@ -34,6 +34,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_FAN_CLASS "fan" #define ACPI_FAN_FILE_STATE "state" diff --git a/drivers/acpi/glue.c b/drivers/acpi/glue.c index a8a5c29..dc36a44 100644 --- a/drivers/acpi/glue.c +++ b/drivers/acpi/glue.c @@ -12,6 +12,8 @@ #include #include +#include "internal.h" + #define ACPI_GLUE_DEBUG 0 #if ACPI_GLUE_DEBUG #define DBG(x...) printk(PREFIX x) diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h index 11a69b5..074cf86 100644 --- a/drivers/acpi/internal.h +++ b/drivers/acpi/internal.h @@ -1,4 +1,24 @@ -/* For use by Linux/ACPI infrastructure, not drivers */ +/* + * acpi/internal.h + * For use by Linux/ACPI infrastructure, not drivers + * + * Copyright (c) 2009, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#define PREFIX "ACPI: " int init_acpi_device_notify(void); int acpi_scan_init(void); diff --git a/drivers/acpi/numa.c b/drivers/acpi/numa.c index d440ccd..202dd0c 100644 --- a/drivers/acpi/numa.c +++ b/drivers/acpi/numa.c @@ -30,6 +30,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_NUMA 0x80000000 #define _COMPONENT ACPI_NUMA ACPI_MODULE_NAME("numa"); diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c index b794eb8..843699e 100644 --- a/drivers/acpi/pci_irq.c +++ b/drivers/acpi/pci_irq.c @@ -40,6 +40,8 @@ #include #include +#define PREFIX "ACPI: " + #define _COMPONENT ACPI_PCI_COMPONENT ACPI_MODULE_NAME("pci_irq"); diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c index 16e0f9d..394ae89 100644 --- a/drivers/acpi/pci_link.c +++ b/drivers/acpi/pci_link.c @@ -43,6 +43,8 @@ #include #include +#define PREFIX "ACPI: " + #define _COMPONENT ACPI_PCI_COMPONENT ACPI_MODULE_NAME("pci_link"); #define ACPI_PCI_LINK_CLASS "pci_irq_routing" diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index 55b5b90..dee9167 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -36,6 +36,8 @@ #include #include +#define PREFIX "ACPI: " + #define _COMPONENT ACPI_PCI_COMPONENT ACPI_MODULE_NAME("pci_root"); #define ACPI_PCI_ROOT_CLASS "pci_bridge" diff --git a/drivers/acpi/power.c b/drivers/acpi/power.c index d74365d..e86603f 100644 --- a/drivers/acpi/power.c +++ b/drivers/acpi/power.c @@ -44,6 +44,8 @@ #include #include +#define PREFIX "ACPI: " + #define _COMPONENT ACPI_POWER_COMPONENT ACPI_MODULE_NAME("power"); #define ACPI_POWER_CLASS "power_resource" diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 2cc4b30..b4a1ab2 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -59,6 +59,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_PROCESSOR_CLASS "processor" #define ACPI_PROCESSOR_DEVICE_NAME "Processor" #define ACPI_PROCESSOR_FILE_INFO "info" diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 66393d5..22aab1f 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -60,6 +60,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_PROCESSOR_CLASS "processor" #define _COMPONENT ACPI_PROCESSOR_COMPONENT ACPI_MODULE_NAME("processor_idle"); diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/processor_perflib.c index 60e543d..11088cf 100644 --- a/drivers/acpi/processor_perflib.c +++ b/drivers/acpi/processor_perflib.c @@ -39,6 +39,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_PROCESSOR_CLASS "processor" #define ACPI_PROCESSOR_FILE_PERFORMANCE "performance" #define _COMPONENT ACPI_PROCESSOR_COMPONENT diff --git a/drivers/acpi/processor_thermal.c b/drivers/acpi/processor_thermal.c index 31adda1..3e3181c 100644 --- a/drivers/acpi/processor_thermal.c +++ b/drivers/acpi/processor_thermal.c @@ -40,6 +40,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_PROCESSOR_CLASS "processor" #define _COMPONENT ACPI_PROCESSOR_COMPONENT ACPI_MODULE_NAME("processor_thermal"); diff --git a/drivers/acpi/processor_throttling.c b/drivers/acpi/processor_throttling.c index ae39797..b366b9c 100644 --- a/drivers/acpi/processor_throttling.c +++ b/drivers/acpi/processor_throttling.c @@ -41,6 +41,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_PROCESSOR_CLASS "processor" #define _COMPONENT ACPI_PROCESSOR_COMPONENT ACPI_MODULE_NAME("processor_throttling"); diff --git a/drivers/acpi/sbs.c b/drivers/acpi/sbs.c index 4b214b7..52b9db8 100644 --- a/drivers/acpi/sbs.c +++ b/drivers/acpi/sbs.c @@ -46,6 +46,8 @@ #include "sbshc.h" +#define PREFIX "ACPI: " + #define ACPI_SBS_CLASS "sbs" #define ACPI_AC_CLASS "ac_adapter" #define ACPI_BATTERY_CLASS "battery" diff --git a/drivers/acpi/sbshc.c b/drivers/acpi/sbshc.c index 0619734..d933980 100644 --- a/drivers/acpi/sbshc.c +++ b/drivers/acpi/sbshc.c @@ -15,6 +15,8 @@ #include #include "sbshc.h" +#define PREFIX "ACPI: " + #define ACPI_SMB_HC_CLASS "smbus_host_controller" #define ACPI_SMB_HC_DEVICE_NAME "ACPI SMBus HC" diff --git a/drivers/acpi/system.c b/drivers/acpi/system.c index 9c61ab2..d112829 100644 --- a/drivers/acpi/system.c +++ b/drivers/acpi/system.c @@ -31,6 +31,8 @@ #include +#define PREFIX "ACPI: " + #define _COMPONENT ACPI_SYSTEM_COMPONENT ACPI_MODULE_NAME("system"); diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c index 564ea14..65f6781 100644 --- a/drivers/acpi/thermal.c +++ b/drivers/acpi/thermal.c @@ -47,6 +47,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_THERMAL_CLASS "thermal_zone" #define ACPI_THERMAL_DEVICE_NAME "Thermal Zone" #define ACPI_THERMAL_FILE_STATE "state" diff --git a/drivers/acpi/utils.c b/drivers/acpi/utils.c index f844941..811fec1 100644 --- a/drivers/acpi/utils.c +++ b/drivers/acpi/utils.c @@ -30,6 +30,8 @@ #include #include +#include "internal.h" + #define _COMPONENT ACPI_BUS_COMPONENT ACPI_MODULE_NAME("utils"); diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c index 8851315..a0fa394 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c @@ -44,6 +44,8 @@ #include #include +#define PREFIX "ACPI: " + #define ACPI_VIDEO_CLASS "video" #define ACPI_VIDEO_BUS_NAME "Video Bus" #define ACPI_VIDEO_DEVICE_NAME "Video Device" diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c index 7cd2b63..7032f25 100644 --- a/drivers/acpi/video_detect.c +++ b/drivers/acpi/video_detect.c @@ -38,6 +38,8 @@ #include #include +#define PREFIX "ACPI: " + ACPI_MODULE_NAME("video"); #define _COMPONENT ACPI_VIDEO_COMPONENT diff --git a/drivers/pci/dmar.c b/drivers/pci/dmar.c index 7b287cb..998f02d 100644 --- a/drivers/pci/dmar.c +++ b/drivers/pci/dmar.c @@ -34,8 +34,7 @@ #include #include -#undef PREFIX -#define PREFIX "DMAR:" +#define PREFIX "DMAR: " /* No locks are needed as DMA remapping hardware unit * list is constructed at boot time and hotplug of diff --git a/drivers/platform/x86/fujitsu-laptop.c b/drivers/platform/x86/fujitsu-laptop.c index 218b9a1..eabddc9c 100644 --- a/drivers/platform/x86/fujitsu-laptop.c +++ b/drivers/platform/x86/fujitsu-laptop.c @@ -700,7 +700,7 @@ static int acpi_fujitsu_add(struct acpi_device *device) goto end; } - printk(KERN_INFO PREFIX "%s [%s] (%s)\n", + printk(KERN_INFO "ACPI: %s [%s] (%s)\n", acpi_device_name(device), acpi_device_bid(device), !device->power.state ? "on" : "off"); @@ -874,7 +874,7 @@ static int acpi_fujitsu_hotkey_add(struct acpi_device *device) goto end; } - printk(KERN_INFO PREFIX "%s [%s] (%s)\n", + printk(KERN_INFO "ACPI: %s [%s] (%s)\n", acpi_device_name(device), acpi_device_bid(device), !device->power.state ? "on" : "off"); diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c index f215a59..177f8d7 100644 --- a/drivers/platform/x86/wmi.c +++ b/drivers/platform/x86/wmi.c @@ -42,7 +42,6 @@ MODULE_LICENSE("GPL"); #define ACPI_WMI_CLASS "wmi" -#undef PREFIX #define PREFIX "ACPI: WMI: " static DEFINE_MUTEX(wmi_data_lock); diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index c65e4ce..f485107d 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -30,8 +30,6 @@ #include -#define PREFIX "ACPI: " - /* TBD: Make dynamic */ #define ACPI_MAX_HANDLES 10 struct acpi_handle_list { -- cgit v0.10.2 From f4a2d5840e9f0e48d1a787b66e7346087a756029 Mon Sep 17 00:00:00 2001 From: Len Brown Date: Tue, 28 Jul 2009 16:48:02 -0400 Subject: ACPI, PCI: Change PREFIX to "PCI" from "ACPI" in mmconfig-shared.c Signed-off-by: Len Brown Acked-by: Jesse Barnes diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 81d3466..b707a01 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -18,7 +18,7 @@ #include #include -#define PREFIX "ACPI: " +#define PREFIX "PCI: " /* aperture is up to 256MB but BIOS may reserve less */ #define MMCONFIG_APER_MIN (2 * 1024*1024) -- cgit v0.10.2 From e5b8fc6ac158f65598f58dba2c0d52ba3b412f52 Mon Sep 17 00:00:00 2001 From: Len Brown Date: Tue, 7 Jul 2009 23:22:58 -0400 Subject: ACPI: check acpi_disabled in acpi_table_parse() and acpi_table_parse_entries() Allow consumers of the acpi_table_parse()/acpi_table_parse_entries() API to gracefully handle the acpi_disabled=1 case via return value rather than checking the global flag themselves. Signed-off-by: Feng Tang Signed-off-by: Len Brown diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c index 646d39c..f336bca7 100644 --- a/drivers/acpi/tables.c +++ b/drivers/acpi/tables.c @@ -213,6 +213,9 @@ acpi_table_parse_entries(char *id, unsigned long table_end; acpi_size tbl_size; + if (acpi_disabled) + return -ENODEV; + if (!handler) return -EINVAL; @@ -277,6 +280,9 @@ int __init acpi_table_parse(char *id, acpi_table_handler handler) struct acpi_table_header *table = NULL; acpi_size tbl_size; + if (acpi_disabled) + return -ENODEV; + if (!handler) return -EINVAL; -- cgit v0.10.2 From 6349d9979beba240fe7182872cb547250264b865 Mon Sep 17 00:00:00 2001 From: Len Brown Date: Fri, 14 Aug 2009 15:07:14 -0400 Subject: SFI: Simple Firmware Interface - MAINTAINERS, Kconfig CONFIG_SFI=y enables the kernel to boot and run optimally on platforms that support the Simple Firmware Interface. Thanks to Jacob Pan for prototyping the initial Linux SFI support, and to Feng Tang for Linux bring-up and debug both in emulation and on Moorestown hardware. See http://simplefirmware.org for more information on SFI. Signed-off-by: Len Brown diff --git a/MAINTAINERS b/MAINTAINERS index 60299a9..055ba88 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4575,6 +4575,18 @@ L: linux-pci@vger.kernel.org S: Supported F: drivers/pci/hotplug/shpchp* +SIMPLE FIRMWARE INTERFACE (SFI) +P: Len Brown +M: lenb@kernel.org +L: sfi-devel@simplefirmware.org +W: http://simplefirmware.org/ +T: git git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-sfi-2.6.git +S: Supported +F: arch/x86/kernel/*sfi* +F: drivers/sfi/ +F: include/linux/sfi*.h + + SIMTEC EB110ATX (Chalice CATS) P: Ben Dooks M: Vincent Sanders diff --git a/drivers/sfi/Kconfig b/drivers/sfi/Kconfig new file mode 100644 index 0000000..dd11512 --- /dev/null +++ b/drivers/sfi/Kconfig @@ -0,0 +1,17 @@ +# +# SFI Configuration +# + +menuconfig SFI + bool "SFI (Simple Firmware Interface) Support" + ---help--- + The Simple Firmware Interface (SFI) provides a lightweight method + for platform firmware to pass information to the operating system + via static tables in memory. Kernel SFI support is required to + boot on SFI-only platforms. Currently, all SFI-only platforms are + based on the 2nd generation Intel Atom processor platform, + code-named Moorestown. + + For more information, see http://simplefirmware.org + + Say 'Y' here to enable the kernel to boot on SFI-only platforms. -- cgit v0.10.2 From e55a5999ffcf72dc4d43d73618957964cb87065a Mon Sep 17 00:00:00 2001 From: Feng Tang Date: Tue, 28 Jul 2009 17:41:53 +0800 Subject: ACPI: Handle CONFIG_ACPI=n better from linux/acpi.h linux/acpi.h is the top level header for interfacing with the ACPI sub-system, so acpi_disabled should be up there instead of down in asm/acpi.h -- particularly since asm/acpi.h doesn't exist for all architectures. Same story for acpi_table_parse(), which is a top-level API to Linux/ACPI. This is necessary for building some code that used to always depend on CONFIG_ACPI=y, but will soon also need to build with CONFIG_ACPI=n. Signed-off-by: Feng Tang Signed-off-by: Len Brown diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 20d1465..4518dc5 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -144,7 +144,6 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) #else /* !CONFIG_ACPI */ -#define acpi_disabled 1 #define acpi_lapic 0 #define acpi_ioapic 0 static inline void acpi_noirq_set(void) { } diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 34321cf..3fce811 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -292,7 +292,10 @@ void __init acpi_s4_no_nvs(void); extern acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 flags); extern void acpi_early_init(void); -#else /* CONFIG_ACPI */ +#else /* !CONFIG_ACPI */ + +#define acpi_disabled 1 + static inline void acpi_early_init(void) { } static inline int early_acpi_boot_init(void) @@ -331,5 +334,11 @@ static inline int acpi_check_mem_region(resource_size_t start, return 0; } +struct acpi_table_header; +static inline int acpi_table_parse(char *id, + int (*handler)(struct acpi_table_header *)) +{ + return -1; +} #endif /* !CONFIG_ACPI */ #endif /*_LINUX_ACPI_H*/ -- cgit v0.10.2 From 117a9ac777f8034d4675b821172d2ff71f6ec47a Mon Sep 17 00:00:00 2001 From: Feng Tang Date: Fri, 14 Aug 2009 15:10:24 -0400 Subject: SFI: create linux/sfi.h include/linux/include/sfi.h defines everything that customers of SFI need to know in order to use the SFI suport in the kernel. The primary API is sfi_table_parse(), where a driver or another part of the kernel can supply a handler to parse the named table. sfi.h also includes the currently defined table signatures and table formats. Signed-off-by: Feng Tang Signed-off-by: Len Brown diff --git a/include/linux/sfi.h b/include/linux/sfi.h new file mode 100644 index 0000000..9a6f760 --- /dev/null +++ b/include/linux/sfi.h @@ -0,0 +1,206 @@ +/* sfi.h Simple Firmware Interface */ + +/* + + This file is provided under a dual BSD/GPLv2 license. When using or + redistributing this file, you may do so under either license. + + GPL LICENSE SUMMARY + + Copyright(c) 2009 Intel Corporation. All rights reserved. + + This program is free software; you can redistribute it and/or modify + it under the terms of version 2 of the GNU General Public License as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + The full GNU General Public License is included in this distribution + in the file called LICENSE.GPL. + + BSD LICENSE + + Copyright(c) 2009 Intel Corporation. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _LINUX_SFI_H +#define _LINUX_SFI_H + +/* Table signatures reserved by the SFI specification */ +#define SFI_SIG_SYST "SYST" +#define SFI_SIG_FREQ "FREQ" +#define SFI_SIG_IDLE "IDLE" +#define SFI_SIG_CPUS "CPUS" +#define SFI_SIG_MTMR "MTMR" +#define SFI_SIG_MRTC "MRTC" +#define SFI_SIG_MMAP "MMAP" +#define SFI_SIG_APIC "APIC" +#define SFI_SIG_XSDT "XSDT" +#define SFI_SIG_WAKE "WAKE" +#define SFI_SIG_SPIB "SPIB" +#define SFI_SIG_I2CB "I2CB" +#define SFI_SIG_GPEM "GPEM" + +#define SFI_SIGNATURE_SIZE 4 +#define SFI_OEM_ID_SIZE 6 +#define SFI_OEM_TABLE_ID_SIZE 8 + +#define SFI_SYST_SEARCH_BEGIN 0x000E0000 +#define SFI_SYST_SEARCH_END 0x000FFFFF + +#define SFI_GET_NUM_ENTRIES(ptable, entry_type) \ + ((ptable->header.len - sizeof(struct sfi_table_header)) / \ + (sizeof(entry_type))) +/* + * Table structures must be byte-packed to match the SFI specification, + * as they are provided by the BIOS. + */ +struct sfi_table_header { + char sig[SFI_SIGNATURE_SIZE]; + u32 len; + u8 rev; + u8 csum; + char oem_id[SFI_OEM_ID_SIZE]; + char oem_table_id[SFI_OEM_TABLE_ID_SIZE]; +} __packed; + +struct sfi_table_simple { + struct sfi_table_header header; + u64 pentry[1]; +} __packed; + +/* Comply with UEFI spec 2.1 */ +struct sfi_mem_entry { + u32 type; + u64 phys_start; + u64 virt_start; + u64 pages; + u64 attrib; +} __packed; + +struct sfi_cpu_table_entry { + u32 apic_id; +} __packed; + +struct sfi_cstate_table_entry { + u32 hint; /* MWAIT hint */ + u32 latency; /* latency in ms */ +} __packed; + +struct sfi_apic_table_entry { + u64 phys_addr; /* phy base addr for APIC reg */ +} __packed; + +struct sfi_freq_table_entry { + u32 freq_mhz; /* in MHZ */ + u32 latency; /* transition latency in ms */ + u32 ctrl_val; /* value to write to PERF_CTL */ +} __packed; + +struct sfi_wake_table_entry { + u64 phys_addr; /* pointer to where the wake vector locates */ +} __packed; + +struct sfi_timer_table_entry { + u64 phys_addr; /* phy base addr for the timer */ + u32 freq_hz; /* in HZ */ + u32 irq; +} __packed; + +struct sfi_rtc_table_entry { + u64 phys_addr; /* phy base addr for the RTC */ + u32 irq; +} __packed; + +struct sfi_spi_table_entry { + u16 host_num; /* attached to host 0, 1...*/ + u16 cs; /* chip select */ + u16 irq_info; + char name[16]; + u8 dev_info[10]; +} __packed; + +struct sfi_i2c_table_entry { + u16 host_num; + u16 addr; /* slave addr */ + u16 irq_info; + char name[16]; + u8 dev_info[10]; +} __packed; + +struct sfi_gpe_table_entry { + u16 logical_id; /* logical id */ + u16 phys_id; /* physical GPE id */ +} __packed; + + +typedef int (*sfi_table_handler) (struct sfi_table_header *table); + +#ifdef CONFIG_SFI +extern void __init sfi_init(void); +extern int __init sfi_platform_init(void); +extern void __init sfi_init_late(void); +extern int sfi_table_parse(char *signature, char *oem_id, char *oem_table_id, + sfi_table_handler handler); + +extern int sfi_disabled; +static inline void disable_sfi(void) +{ + sfi_disabled = 1; +} + +#else /* !CONFIG_SFI */ + +static inline void sfi_init(void) +{ +} + +static inline void sfi_init_late(void) +{ +} + +#define sfi_disabled 0 + +static inline int sfi_table_parse(char *signature, char *oem_id, + char *oem_table_id, + sfi_table_handler handler) +{ + return -1; +} + +#endif /* !CONFIG_SFI */ + +#endif /*_LINUX_SFI_H*/ -- cgit v0.10.2 From 6ae6996a466e14bcf41618cde641a74ae03dc285 Mon Sep 17 00:00:00 2001 From: Feng Tang Date: Fri, 14 Aug 2009 15:13:46 -0400 Subject: SFI: add platform-independent core support drivers/sfi/sfi_core.c contains the generic SFI implementation. It has a private header, sfi_core.h, for its own use and the private use of future files in drivers/sfi/ Signed-off-by: Feng Tang Signed-off-by: Len Brown diff --git a/drivers/Makefile b/drivers/Makefile index bc4205d..ccfa259f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_PARISC) += parisc/ obj-$(CONFIG_RAPIDIO) += rapidio/ obj-y += video/ obj-$(CONFIG_ACPI) += acpi/ +obj-$(CONFIG_SFI) += sfi/ # PnP must come after ACPI since it will eventually need to check if acpi # was used and do nothing if so obj-$(CONFIG_PNP) += pnp/ diff --git a/drivers/sfi/Makefile b/drivers/sfi/Makefile new file mode 100644 index 0000000..2343732 --- /dev/null +++ b/drivers/sfi/Makefile @@ -0,0 +1,3 @@ +obj-y += sfi_acpi.o +obj-y += sfi_core.o + diff --git a/drivers/sfi/sfi_core.c b/drivers/sfi/sfi_core.c new file mode 100644 index 0000000..7bd6b18 --- /dev/null +++ b/drivers/sfi/sfi_core.c @@ -0,0 +1,412 @@ +/* sfi_core.c Simple Firmware Interface - core internals */ + +/* + + This file is provided under a dual BSD/GPLv2 license. When using or + redistributing this file, you may do so under either license. + + GPL LICENSE SUMMARY + + Copyright(c) 2009 Intel Corporation. All rights reserved. + + This program is free software; you can redistribute it and/or modify + it under the terms of version 2 of the GNU General Public License as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + The full GNU General Public License is included in this distribution + in the file called LICENSE.GPL. + + BSD LICENSE + + Copyright(c) 2009 Intel Corporation. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#define KMSG_COMPONENT "SFI" +#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "sfi_core.h" + +#define ON_SAME_PAGE(addr1, addr2) \ + (((unsigned long)(addr1) & PAGE_MASK) == \ + ((unsigned long)(addr2) & PAGE_MASK)) +#define TABLE_ON_PAGE(page, table, size) (ON_SAME_PAGE(page, table) && \ + ON_SAME_PAGE(page, table + size)) + +int sfi_disabled __read_mostly; +EXPORT_SYMBOL(sfi_disabled); + +static u64 syst_pa __read_mostly; +static struct sfi_table_simple *syst_va __read_mostly; + +/* + * FW creates and saves the SFI tables in memory. When these tables get + * used, they may need to be mapped to virtual address space, and the mapping + * can happen before or after the ioremap() is ready, so a flag is needed + * to indicating this + */ +static u32 sfi_use_ioremap __read_mostly; + +static void __iomem *sfi_map_memory(u64 phys, u32 size) +{ + if (!phys || !size) + return NULL; + + if (sfi_use_ioremap) + return ioremap(phys, size); + else + return early_ioremap(phys, size); +} + +static void sfi_unmap_memory(void __iomem *virt, u32 size) +{ + if (!virt || !size) + return; + + if (sfi_use_ioremap) + iounmap(virt); + else + early_iounmap(virt, size); +} + +static void sfi_print_table_header(unsigned long long pa, + struct sfi_table_header *header) +{ + pr_info("%4.4s %llX, %04X (v%d %6.6s %8.8s)\n", + header->sig, pa, + header->len, header->rev, header->oem_id, + header->oem_table_id); +} + +/* + * sfi_verify_table() + * Sanity check table lengh, calculate checksum + */ +static __init int sfi_verify_table(struct sfi_table_header *table) +{ + + u8 checksum = 0; + u8 *puchar = (u8 *)table; + u32 length = table->len; + + /* Sanity check table length against arbitrary 1MB limit */ + if (length > 0x100000) { + pr_err("Invalid table length 0x%x\n", length); + return -1; + } + + while (length--) + checksum += *puchar++; + + if (checksum) { + pr_err("Checksum %2.2X should be %2.2X\n", + table->csum, table->csum - checksum); + return -1; + } + return 0; +} + +/* + * sfi_map_table() + * + * Return address of mapped table + * Check for common case that we can re-use mapping to SYST, + * which requires syst_pa, syst_va to be initialized. + */ +struct sfi_table_header *sfi_map_table(u64 pa) +{ + struct sfi_table_header *th; + u32 length; + + if (!TABLE_ON_PAGE(syst_pa, pa, sizeof(struct sfi_table_header))) + th = sfi_map_memory(pa, sizeof(struct sfi_table_header)); + else + th = (void *)syst_va + (pa - syst_pa); + + /* If table fits on same page as its header, we are done */ + if (TABLE_ON_PAGE(th, th, th->len)) + return th; + + /* Entire table does not fit on same page as SYST */ + length = th->len; + if (!TABLE_ON_PAGE(syst_pa, pa, sizeof(struct sfi_table_header))) + sfi_unmap_memory(th, sizeof(struct sfi_table_header)); + + return sfi_map_memory(pa, length); +} + +/* + * sfi_unmap_table() + * + * Undoes effect of sfi_map_table() by unmapping table + * if it did not completely fit on same page as SYST. + */ +void sfi_unmap_table(struct sfi_table_header *th) +{ + if (!TABLE_ON_PAGE(syst_va, th, th->len)) + sfi_unmap_memory(th, TABLE_ON_PAGE(th, th, th->len) ? + sizeof(*th) : th->len); +} + +static int sfi_table_check_key(struct sfi_table_header *th, + struct sfi_table_key *key) +{ + + if (strncmp(th->sig, key->sig, SFI_SIGNATURE_SIZE) + || (key->oem_id && strncmp(th->oem_id, + key->oem_id, SFI_OEM_ID_SIZE)) + || (key->oem_table_id && strncmp(th->oem_table_id, + key->oem_table_id, SFI_OEM_TABLE_ID_SIZE))) + return -1; + + return 0; +} + +/* + * This function will be used in 2 cases: + * 1. used to enumerate and verify the tables addressed by SYST/XSDT, + * thus no signature will be given (in kernel boot phase) + * 2. used to parse one specific table, signature must exist, and + * the mapped virt address will be returned, and the virt space + * will be released by call sfi_put_table() later + * + * Return value: + * NULL: when can't find a table matching the key + * ERR_PTR(error): error value + * virt table address: when a matched table is found + */ +struct sfi_table_header *sfi_check_table(u64 pa, struct sfi_table_key *key) +{ + struct sfi_table_header *th; + void *ret = NULL; + + th = sfi_map_table(pa); + if (!th) + return ERR_PTR(-ENOMEM); + + if (!key->sig) { + sfi_print_table_header(pa, th); + if (sfi_verify_table(th)) + ret = ERR_PTR(-EINVAL); + } else { + if (!sfi_table_check_key(th, key)) + return th; /* Success */ + } + + sfi_unmap_table(th); + return ret; +} + +/* + * sfi_get_table() + * + * Search SYST for the specified table with the signature in + * the key, and return the mapped table + */ +struct sfi_table_header *sfi_get_table(struct sfi_table_key *key) +{ + struct sfi_table_header *th; + u32 tbl_cnt, i; + + tbl_cnt = SFI_GET_NUM_ENTRIES(syst_va, u64); + for (i = 0; i < tbl_cnt; i++) { + th = sfi_check_table(syst_va->pentry[i], key); + if (!IS_ERR(th) && th) + return th; + } + + return NULL; +} + +void sfi_put_table(struct sfi_table_header *th) +{ + sfi_unmap_table(th); +} + +/* Find table with signature, run handler on it */ +int sfi_table_parse(char *signature, char *oem_id, char *oem_table_id, + sfi_table_handler handler) +{ + struct sfi_table_header *table = NULL; + struct sfi_table_key key; + int ret = -EINVAL; + + if (sfi_disabled || !handler || !signature) + goto exit; + + key.sig = signature; + key.oem_id = oem_id; + key.oem_table_id = oem_table_id; + + table = sfi_get_table(&key); + if (!table) + goto exit; + + ret = handler(table); + sfi_put_table(table); +exit: + return ret; +} +EXPORT_SYMBOL_GPL(sfi_table_parse); + +/* + * sfi_parse_syst() + * Checksum all the tables in SYST and print their headers + * + * success: set syst_va, return 0 + */ +static int __init sfi_parse_syst(void) +{ + struct sfi_table_key key = SFI_ANY_KEY; + int tbl_cnt, i; + void *ret; + + syst_va = sfi_map_memory(syst_pa, sizeof(struct sfi_table_simple)); + if (!syst_va) + return -ENOMEM; + + tbl_cnt = SFI_GET_NUM_ENTRIES(syst_va, u64); + for (i = 0; i < tbl_cnt; i++) { + ret = sfi_check_table(syst_va->pentry[i], &key); + if (IS_ERR(ret)) + return PTR_ERR(ret); + } + + return 0; +} + +/* + * The OS finds the System Table by searching 16-byte boundaries between + * physical address 0x000E0000 and 0x000FFFFF. The OS shall search this region + * starting at the low address and shall stop searching when the 1st valid SFI + * System Table is found. + * + * success: set syst_pa, return 0 + * fail: return -1 + */ +static __init int sfi_find_syst(void) +{ + unsigned long offset, len; + void *start; + + len = SFI_SYST_SEARCH_END - SFI_SYST_SEARCH_BEGIN; + start = sfi_map_memory(SFI_SYST_SEARCH_BEGIN, len); + if (!start) + return -1; + + for (offset = 0; offset < len; offset += 16) { + struct sfi_table_header *syst_hdr; + + syst_hdr = start + offset; + if (strncmp(syst_hdr->sig, SFI_SIG_SYST, + SFI_SIGNATURE_SIZE)) + continue; + + if (syst_hdr->len > PAGE_SIZE) + continue; + + sfi_print_table_header(SFI_SYST_SEARCH_BEGIN + offset, + syst_hdr); + + if (sfi_verify_table(syst_hdr)) + continue; + + /* + * Enforce SFI spec mandate that SYST reside within a page. + */ + if (!ON_SAME_PAGE(syst_pa, syst_pa + syst_hdr->len)) { + pr_info("SYST 0x%llx + 0x%x crosses page\n", + syst_pa, syst_hdr->len); + continue; + } + + /* Success */ + syst_pa = SFI_SYST_SEARCH_BEGIN + offset; + sfi_unmap_memory(start, len); + return 0; + } + + sfi_unmap_memory(start, len); + return -1; +} + +void __init sfi_init(void) +{ + if (!acpi_disabled) + disable_sfi(); + + if (sfi_disabled) + return; + + pr_info("Simple Firmware Interface v0.7 http://simplefirmware.org\n"); + + if (sfi_find_syst() || sfi_parse_syst() || sfi_platform_init()) + disable_sfi(); + + return; +} + +void __init sfi_init_late(void) +{ + int length; + + if (sfi_disabled) + return; + + length = syst_va->header.len; + sfi_unmap_memory(syst_va, sizeof(struct sfi_table_simple)); + + /* Use ioremap now after it is ready */ + sfi_use_ioremap = 1; + syst_va = sfi_map_memory(syst_pa, length); + + sfi_acpi_init(); +} diff --git a/drivers/sfi/sfi_core.h b/drivers/sfi/sfi_core.h new file mode 100644 index 0000000..da82d39 --- /dev/null +++ b/drivers/sfi/sfi_core.h @@ -0,0 +1,70 @@ +/* sfi_core.h Simple Firmware Interface, internal header */ + +/* + + This file is provided under a dual BSD/GPLv2 license. When using or + redistributing this file, you may do so under either license. + + GPL LICENSE SUMMARY + + Copyright(c) 2009 Intel Corporation. All rights reserved. + + This program is free software; you can redistribute it and/or modify + it under the terms of version 2 of the GNU General Public License as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + The full GNU General Public License is included in this distribution + in the file called LICENSE.GPL. + + BSD LICENSE + + Copyright(c) 2009 Intel Corporation. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ +struct sfi_table_key{ + char *sig; + char *oem_id; + char *oem_table_id; +}; + +#define SFI_ANY_KEY { .sig = NULL, .oem_id = NULL, .oem_table_id = NULL } + +extern int __init sfi_acpi_init(void); +extern struct sfi_table_header *sfi_check_table(u64 paddr, + struct sfi_table_key *key); +struct sfi_table_header *sfi_get_table(struct sfi_table_key *key); +extern void sfi_put_table(struct sfi_table_header *table); diff --git a/init/main.c b/init/main.c index 11f4f14..9f110fb 100644 --- a/init/main.c +++ b/init/main.c @@ -68,6 +68,7 @@ #include #include #include +#include #include #include @@ -712,6 +713,7 @@ asmlinkage void __init start_kernel(void) check_bugs(); acpi_early_init(); /* before LAPIC and SMP init */ + sfi_init_late(); ftrace_init(); -- cgit v0.10.2 From 13e82d023c4c3f13ab1e665cbb917a7ebba8935c Mon Sep 17 00:00:00 2001 From: Feng Tang Date: Fri, 14 Aug 2009 15:17:53 -0400 Subject: SFI: add capability to parse ACPI tables Extend SFI to access standard ACPI tables. (eg. the PCI MCFG) using sfi_acpi_table_parse(). Note that this is _not_ a hybrid ACPI + SFI mode. The platform boots in either ACPI mode or SFI mode. SFI runs only with acpi_disabled=1, which can be set at build-time via CONFIG_ACPI=n, or at boot time by the failure to find ACPI platform support. So this extension simply allows SFI-platforms to re-use existing standard table formats that happen to be defined to live in ACPI envelopes. Signed-off-by: Feng Tang Signed-off-by: Len Brown diff --git a/drivers/sfi/sfi_acpi.c b/drivers/sfi/sfi_acpi.c new file mode 100644 index 0000000..34aba30 --- /dev/null +++ b/drivers/sfi/sfi_acpi.c @@ -0,0 +1,175 @@ +/* sfi_acpi.c Simple Firmware Interface - ACPI extensions */ + +/* + + This file is provided under a dual BSD/GPLv2 license. When using or + redistributing this file, you may do so under either license. + + GPL LICENSE SUMMARY + + Copyright(c) 2009 Intel Corporation. All rights reserved. + + This program is free software; you can redistribute it and/or modify + it under the terms of version 2 of the GNU General Public License as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + The full GNU General Public License is included in this distribution + in the file called LICENSE.GPL. + + BSD LICENSE + + Copyright(c) 2009 Intel Corporation. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#define KMSG_COMPONENT "SFI" +#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt + +#include +#include + +#include +#include "sfi_core.h" + +/* + * SFI can access ACPI-defined tables via an optional ACPI XSDT. + * + * This allows re-use, and avoids re-definition, of standard tables. + * For example, the "MCFG" table is defined by PCI, reserved by ACPI, + * and is expected to be present many SFI-only systems. + */ + +static struct acpi_table_xsdt *xsdt_va __read_mostly; + +#define XSDT_GET_NUM_ENTRIES(ptable, entry_type) \ + ((ptable->header.length - sizeof(struct acpi_table_header)) / \ + (sizeof(entry_type))) + +static inline struct sfi_table_header *acpi_to_sfi_th( + struct acpi_table_header *th) +{ + return (struct sfi_table_header *)th; +} + +static inline struct acpi_table_header *sfi_to_acpi_th( + struct sfi_table_header *th) +{ + return (struct acpi_table_header *)th; +} + +/* + * sfi_acpi_parse_xsdt() + * + * Parse the ACPI XSDT for later access by sfi_acpi_table_parse(). + */ +static int __init sfi_acpi_parse_xsdt(struct sfi_table_header *th) +{ + struct sfi_table_key key = SFI_ANY_KEY; + int tbl_cnt, i; + void *ret; + + xsdt_va = (struct acpi_table_xsdt *)th; + tbl_cnt = XSDT_GET_NUM_ENTRIES(xsdt_va, u64); + for (i = 0; i < tbl_cnt; i++) { + ret = sfi_check_table(xsdt_va->table_offset_entry[i], &key); + if (IS_ERR(ret)) { + disable_sfi(); + return -1; + } + } + + return 0; +} + +int __init sfi_acpi_init(void) +{ + struct sfi_table_key xsdt_key = { .sig = SFI_SIG_XSDT }; + + sfi_table_parse(SFI_SIG_XSDT, NULL, NULL, sfi_acpi_parse_xsdt); + + /* Only call the get_table to keep the table mapped */ + xsdt_va = (struct acpi_table_xsdt *)sfi_get_table(&xsdt_key); + return 0; +} + +static struct acpi_table_header *sfi_acpi_get_table(struct sfi_table_key *key) +{ + u32 tbl_cnt, i; + void *ret; + + tbl_cnt = XSDT_GET_NUM_ENTRIES(xsdt_va, u64); + for (i = 0; i < tbl_cnt; i++) { + ret = sfi_check_table(xsdt_va->table_offset_entry[i], key); + if (!IS_ERR(ret) && ret) + return sfi_to_acpi_th(ret); + } + + return NULL; +} + +static void sfi_acpi_put_table(struct acpi_table_header *table) +{ + sfi_put_table(acpi_to_sfi_th(table)); +} + +/* + * sfi_acpi_table_parse() + * + * Find specified table in XSDT, run handler on it and return its return value + */ +int sfi_acpi_table_parse(char *signature, char *oem_id, char *oem_table_id, + int(*handler)(struct acpi_table_header *)) +{ + struct acpi_table_header *table = NULL; + struct sfi_table_key key; + int ret = 0; + + if (sfi_disabled) + return -1; + + key.sig = signature; + key.oem_id = oem_id; + key.oem_table_id = oem_table_id; + + table = sfi_acpi_get_table(&key); + if (!table) + return -EINVAL; + + ret = handler(table); + sfi_acpi_put_table(table); + return ret; +} diff --git a/include/linux/sfi_acpi.h b/include/linux/sfi_acpi.h new file mode 100644 index 0000000..c4a5a8c --- /dev/null +++ b/include/linux/sfi_acpi.h @@ -0,0 +1,93 @@ +/* sfi.h Simple Firmware Interface */ + +/* + + This file is provided under a dual BSD/GPLv2 license. When using or + redistributing this file, you may do so under either license. + + GPL LICENSE SUMMARY + + Copyright(c) 2009 Intel Corporation. All rights reserved. + + This program is free software; you can redistribute it and/or modify + it under the terms of version 2 of the GNU General Public License as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + The full GNU General Public License is included in this distribution + in the file called LICENSE.GPL. + + BSD LICENSE + + Copyright(c) 2009 Intel Corporation. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _LINUX_SFI_ACPI_H +#define _LINUX_SFI_ACPI_H + +#ifdef CONFIG_SFI +#include /* struct acpi_table_header */ + +extern int sfi_acpi_table_parse(char *signature, char *oem_id, + char *oem_table_id, + int (*handler)(struct acpi_table_header *)); + +static inline int acpi_sfi_table_parse(char *signature, + int (*handler)(struct acpi_table_header *)) +{ + if (!acpi_table_parse(signature, handler)) + return 0; + + return sfi_acpi_table_parse(signature, NULL, NULL, handler); +} +#else /* !CONFIG_SFI */ + +static inline int sfi_acpi_table_parse(char *signature, char *oem_id, + char *oem_table_id, + int (*handler)(struct acpi_table_header *)) +{ + return -1; +} + +static inline int acpi_sfi_table_parse(char *signature, + int (*handler)(struct acpi_table_header *)) +{ + return acpi_table_parse(signature, handler); +} +#endif /* !CONFIG_SFI */ + +#endif /*_LINUX_SFI_ACPI_H*/ -- cgit v0.10.2 From efafc8b213e67ed148a5b53ade29ee7b48af907d Mon Sep 17 00:00:00 2001 From: Feng Tang Date: Fri, 14 Aug 2009 15:23:29 -0400 Subject: x86: add arch-specific SFI support arch/x86/kernel/sfi.c serves the dual-purpose of supporting the SFI core with arch specific code, as well as a home for the arch-specific code that uses SFI. analogous to ACPI, drivers/sfi/Kconfig is pulled in by arch/x86/Kconfig Signed-off-by: Feng Tang Signed-off-by: Len Brown Cc: x86@kernel.org diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 13ffa5d..d8ba424 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1683,6 +1683,8 @@ source "kernel/power/Kconfig" source "drivers/acpi/Kconfig" +source "drivers/sfi/Kconfig" + config X86_APM_BOOT bool default y diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 430d5b2..6321afa 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -55,6 +55,7 @@ obj-y += step.o obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-y += cpu/ obj-y += acpi/ +obj-$(CONFIG_SFI) += sfi.o obj-y += reboot.o obj-$(CONFIG_MCA) += mca_32.o obj-$(CONFIG_X86_MSR) += msr.o diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 63f32d2..d784ea2 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -990,6 +991,8 @@ void __init setup_arch(char **cmdline_p) */ acpi_boot_init(); + sfi_init(); + #if defined(CONFIG_X86_MPPARSE) || defined(CONFIG_X86_VISWS) /* * get boot-time SMP configuration: diff --git a/arch/x86/kernel/sfi.c b/arch/x86/kernel/sfi.c new file mode 100644 index 0000000..761df3f --- /dev/null +++ b/arch/x86/kernel/sfi.c @@ -0,0 +1,133 @@ +/* + * sfi.c - x86 architecture SFI support. + * + * Copyright (c) 2009, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#define KMSG_COMPONENT "SFI" +#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_X86_LOCAL_APIC +static unsigned long sfi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE; + +void __init mp_sfi_register_lapic_address(unsigned long address) +{ + mp_lapic_addr = address; + + set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); + if (boot_cpu_physical_apicid == -1U) + boot_cpu_physical_apicid = read_apic_id(); + + pr_info("Boot CPU = %d\n", boot_cpu_physical_apicid); +} + +/* All CPUs enumerated by SFI must be present and enabled */ +void __cpuinit mp_sfi_register_lapic(u8 id) +{ + int boot_cpu = 0; + + if (MAX_APICS - id <= 0) { + pr_warning("Processor #%d invalid (max %d)\n", + id, MAX_APICS); + return; + } + + if (id == boot_cpu_physical_apicid) + boot_cpu = 1; + pr_info("registering lapic[%d]\n", id); + + generic_processor_info(id, GET_APIC_VERSION(apic_read(APIC_LVR))); +} + +static int __init sfi_parse_cpus(struct sfi_table_header *table) +{ + struct sfi_table_simple *sb; + struct sfi_cpu_table_entry *pentry; + int i; + int cpu_num; + + sb = (struct sfi_table_simple *)table; + cpu_num = SFI_GET_NUM_ENTRIES(sb, struct sfi_cpu_table_entry); + pentry = (struct sfi_cpu_table_entry *)sb->pentry; + + for (i = 0; i < cpu_num; i++) { + mp_sfi_register_lapic(pentry->apic_id); + pentry++; + } + + smp_found_config = 1; + return 0; +} +#endif /* CONFIG_X86_LOCAL_APIC */ + +#ifdef CONFIG_X86_IO_APIC +static u32 gsi_base; + +static int __init sfi_parse_ioapic(struct sfi_table_header *table) +{ + struct sfi_table_simple *sb; + struct sfi_apic_table_entry *pentry; + int i, num; + + sb = (struct sfi_table_simple *)table; + num = SFI_GET_NUM_ENTRIES(sb, struct sfi_apic_table_entry); + pentry = (struct sfi_apic_table_entry *)sb->pentry; + + for (i = 0; i < num; i++) { + mp_register_ioapic(i, pentry->phys_addr, gsi_base); + gsi_base += io_apic_get_redir_entries(i); + pentry++; + } + + WARN(pic_mode, KERN_WARNING + "SFI: pic_mod shouldn't be 1 when IOAPIC table is present\n"); + pic_mode = 0; + return 0; +} +#endif /* CONFIG_X86_IO_APIC */ + +/* + * sfi_platform_init(): register lapics & io-apics + */ +int __init sfi_platform_init(void) +{ +#ifdef CONFIG_X86_LOCAL_APIC + mp_sfi_register_lapic_address(sfi_lapic_addr); + sfi_table_parse(SFI_SIG_CPUS, NULL, NULL, sfi_parse_cpus); +#endif +#ifdef CONFIG_X86_IO_APIC + sfi_table_parse(SFI_SIG_APIC, NULL, NULL, sfi_parse_ioapic); +#endif + return 0; +} -- cgit v0.10.2 From 5f0db7a2fb78895a197f64e548333b3bbd433996 Mon Sep 17 00:00:00 2001 From: Feng Tang Date: Fri, 14 Aug 2009 15:37:50 -0400 Subject: SFI: Hook PCI MMCONFIG First check ACPI, and if that fails, ask SFI to find the MCFG. Signed-off-by: Feng Tang Signed-off-by: Len Brown Cc: Jesse Barnes diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d8ba424..4c92c91 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1880,7 +1880,7 @@ config PCI_DIRECT config PCI_MMCONFIG def_bool y - depends on X86_32 && PCI && ACPI && (PCI_GOMMCONFIG || PCI_GOANY) + depends on X86_32 && PCI && (ACPI || SFI) && (PCI_GOMMCONFIG || PCI_GOANY) config PCI_OLPC def_bool y diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index b707a01..602c172d 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -13,10 +13,12 @@ #include #include #include +#include #include #include #include #include +#include #define PREFIX "PCI: " @@ -493,7 +495,7 @@ static void __init pci_mmcfg_reject_broken(int early) (unsigned int)cfg->start_bus_number, (unsigned int)cfg->end_bus_number); - if (!early) + if (!early && !acpi_disabled) valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0); if (valid) @@ -608,7 +610,7 @@ static void __init __pci_mmcfg_init(int early) } if (!known_bridge) - acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); + acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); pci_mmcfg_reject_broken(early); diff --git a/arch/x86/pci/mmconfig_32.c b/arch/x86/pci/mmconfig_32.c index 8b2d561..f10a7e9 100644 --- a/arch/x86/pci/mmconfig_32.c +++ b/arch/x86/pci/mmconfig_32.c @@ -11,9 +11,9 @@ #include #include -#include #include #include +#include /* Assume systems with more busses have correct MCFG */ #define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG)) -- cgit v0.10.2 From 2b022e3d4bf9885f781221c59d86283a2cdfc2ed Mon Sep 17 00:00:00 2001 From: Xiao Guangrong Date: Mon, 10 Aug 2009 10:48:59 +0800 Subject: timers: Add tracepoints for timer_list timers Add tracepoints which cover the timer life cycle. The tracepoints are integrated with the already existing debug_object debug points as far as possible. Based on patches from Mathieu: http://marc.info/?l=linux-kernel&m=123791201816247&w=2 and Anton: http://marc.info/?l=linux-kernel&m=124331396919301&w=2 [ tglx: Fixed timeout value in timer_start tracepoint, massaged comments and made the printk's more readable ] Signed-off-by: Xiao Guangrong Cc: Anton Blanchard Cc: Steven Rostedt Cc: Frederic Weisbecker Cc: Mathieu Desnoyers Cc: Peter Zijlstra Cc: KOSAKI Motohiro Cc: Zhaolei LKML-Reference: <4A7F8A9B.3040201@cn.fujitsu.com> Signed-off-by: Thomas Gleixner diff --git a/include/trace/events/timer.h b/include/trace/events/timer.h new file mode 100644 index 0000000..725892a --- /dev/null +++ b/include/trace/events/timer.h @@ -0,0 +1,137 @@ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM timer + +#if !defined(_TRACE_TIMER_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_TIMER_H + +#include +#include + +/** + * timer_init - called when the timer is initialized + * @timer: pointer to struct timer_list + */ +TRACE_EVENT(timer_init, + + TP_PROTO(struct timer_list *timer), + + TP_ARGS(timer), + + TP_STRUCT__entry( + __field( void *, timer ) + ), + + TP_fast_assign( + __entry->timer = timer; + ), + + TP_printk("timer %p", __entry->timer) +); + +/** + * timer_start - called when the timer is started + * @timer: pointer to struct timer_list + * @expires: the timers expiry time + */ +TRACE_EVENT(timer_start, + + TP_PROTO(struct timer_list *timer, unsigned long expires), + + TP_ARGS(timer, expires), + + TP_STRUCT__entry( + __field( void *, timer ) + __field( void *, function ) + __field( unsigned long, expires ) + __field( unsigned long, now ) + ), + + TP_fast_assign( + __entry->timer = timer; + __entry->function = timer->function; + __entry->expires = expires; + __entry->now = jiffies; + ), + + TP_printk("timer %p: func %pf, expires %lu, timeout %ld", + __entry->timer, __entry->function, __entry->expires, + (long)__entry->expires - __entry->now) +); + +/** + * timer_expire_entry - called immediately before the timer callback + * @timer: pointer to struct timer_list + * + * Allows to determine the timer latency. + */ +TRACE_EVENT(timer_expire_entry, + + TP_PROTO(struct timer_list *timer), + + TP_ARGS(timer), + + TP_STRUCT__entry( + __field( void *, timer ) + __field( unsigned long, now ) + ), + + TP_fast_assign( + __entry->timer = timer; + __entry->now = jiffies; + ), + + TP_printk("timer %p: now %lu", __entry->timer, __entry->now) +); + +/** + * timer_expire_exit - called immediately after the timer callback returns + * @timer: pointer to struct timer_list + * + * When used in combination with the timer_expire_entry tracepoint we can + * determine the runtime of the timer callback function. + * + * NOTE: Do NOT derefernce timer in TP_fast_assign. The pointer might + * be invalid. We solely track the pointer. + */ +TRACE_EVENT(timer_expire_exit, + + TP_PROTO(struct timer_list *timer), + + TP_ARGS(timer), + + TP_STRUCT__entry( + __field(void *, timer ) + ), + + TP_fast_assign( + __entry->timer = timer; + ), + + TP_printk("timer %p", __entry->timer) +); + +/** + * timer_cancel - called when the timer is canceled + * @timer: pointer to struct timer_list + */ +TRACE_EVENT(timer_cancel, + + TP_PROTO(struct timer_list *timer), + + TP_ARGS(timer), + + TP_STRUCT__entry( + __field( void *, timer ) + ), + + TP_fast_assign( + __entry->timer = timer; + ), + + TP_printk("timer %p", __entry->timer) +); + +#endif /* _TRACE_TIMER_H */ + +/* This part must be outside protection */ +#include diff --git a/kernel/timer.c b/kernel/timer.c index 8e92be6..a7352b0 100644 --- a/kernel/timer.c +++ b/kernel/timer.c @@ -46,6 +46,9 @@ #include #include +#define CREATE_TRACE_POINTS +#include + u64 jiffies_64 __cacheline_aligned_in_smp = INITIAL_JIFFIES; EXPORT_SYMBOL(jiffies_64); @@ -521,6 +524,25 @@ static inline void debug_timer_activate(struct timer_list *timer) { } static inline void debug_timer_deactivate(struct timer_list *timer) { } #endif +static inline void debug_init(struct timer_list *timer) +{ + debug_timer_init(timer); + trace_timer_init(timer); +} + +static inline void +debug_activate(struct timer_list *timer, unsigned long expires) +{ + debug_timer_activate(timer); + trace_timer_start(timer, expires); +} + +static inline void debug_deactivate(struct timer_list *timer) +{ + debug_timer_deactivate(timer); + trace_timer_cancel(timer); +} + static void __init_timer(struct timer_list *timer, const char *name, struct lock_class_key *key) @@ -549,7 +571,7 @@ void init_timer_key(struct timer_list *timer, const char *name, struct lock_class_key *key) { - debug_timer_init(timer); + debug_init(timer); __init_timer(timer, name, key); } EXPORT_SYMBOL(init_timer_key); @@ -568,7 +590,7 @@ static inline void detach_timer(struct timer_list *timer, { struct list_head *entry = &timer->entry; - debug_timer_deactivate(timer); + debug_deactivate(timer); __list_del(entry->prev, entry->next); if (clear_pending) @@ -632,7 +654,7 @@ __mod_timer(struct timer_list *timer, unsigned long expires, goto out_unlock; } - debug_timer_activate(timer); + debug_activate(timer, expires); new_base = __get_cpu_var(tvec_bases); @@ -787,7 +809,7 @@ void add_timer_on(struct timer_list *timer, int cpu) BUG_ON(timer_pending(timer) || !timer->function); spin_lock_irqsave(&base->lock, flags); timer_set_base(timer, base); - debug_timer_activate(timer); + debug_activate(timer, timer->expires); if (time_before(timer->expires, base->next_timer) && !tbase_get_deferrable(timer->base)) base->next_timer = timer->expires; @@ -1000,7 +1022,9 @@ static inline void __run_timers(struct tvec_base *base) */ lock_map_acquire(&lockdep_map); + trace_timer_expire_entry(timer); fn(data); + trace_timer_expire_exit(timer); lock_map_release(&lockdep_map); -- cgit v0.10.2 From c6a2a1770245f654f35f60e1458d4356680f9519 Mon Sep 17 00:00:00 2001 From: Xiao Guangrong Date: Mon, 10 Aug 2009 10:51:23 +0800 Subject: hrtimer: Add tracepoint for hrtimers Add tracepoints which cover the life cycle of a hrtimer. The tracepoints are integrated with the already existing debug_object debug points as far as possible. [ tglx: Fixed comments, made output conistent, easier to read and parse. Fixed output for 32bit archs which do not use the scalar representation of ktime_t. Hand current time to trace_hrtimer_expiry_entry instead of calling get_time() inside of the trace assignment. ] Signed-off-by: Xiao Guangrong Cc: Steven Rostedt Cc: Frederic Weisbecker Cc: Mathieu Desnoyers Cc: Anton Blanchard Cc: Peter Zijlstra Cc: KOSAKI Motohiro Cc: Zhaolei LKML-Reference: <4A7F8B2B.5020908@cn.fujitsu.com> Signed-off-by: Thomas Gleixner diff --git a/include/trace/events/timer.h b/include/trace/events/timer.h index 725892a..df3c07f 100644 --- a/include/trace/events/timer.h +++ b/include/trace/events/timer.h @@ -5,6 +5,7 @@ #define _TRACE_TIMER_H #include +#include #include /** @@ -131,6 +132,144 @@ TRACE_EVENT(timer_cancel, TP_printk("timer %p", __entry->timer) ); +/** + * hrtimer_init - called when the hrtimer is initialized + * @timer: pointer to struct hrtimer + * @clockid: the hrtimers clock + * @mode: the hrtimers mode + */ +TRACE_EVENT(hrtimer_init, + + TP_PROTO(struct hrtimer *timer, clockid_t clockid, + enum hrtimer_mode mode), + + TP_ARGS(timer, clockid, mode), + + TP_STRUCT__entry( + __field( void *, timer ) + __field( clockid_t, clockid ) + __field( enum hrtimer_mode, mode ) + ), + + TP_fast_assign( + __entry->timer = timer; + __entry->clockid = clockid; + __entry->mode = mode; + ), + + TP_printk("hrtimer %p, clockid %s, mode %s", __entry->timer, + __entry->clockid == CLOCK_REALTIME ? + "CLOCK_REALTIME" : "CLOCK_MONOTONIC", + __entry->mode == HRTIMER_MODE_ABS ? + "HRTIMER_MODE_ABS" : "HRTIMER_MODE_REL") +); + +/** + * hrtimer_start - called when the hrtimer is started + * @timer: pointer to struct hrtimer + */ +TRACE_EVENT(hrtimer_start, + + TP_PROTO(struct hrtimer *timer), + + TP_ARGS(timer), + + TP_STRUCT__entry( + __field( void *, timer ) + __field( void *, function ) + __field( s64, expires ) + __field( s64, softexpires ) + ), + + TP_fast_assign( + __entry->timer = timer; + __entry->function = timer->function; + __entry->expires = hrtimer_get_expires(timer).tv64; + __entry->softexpires = hrtimer_get_softexpires(timer).tv64; + ), + + TP_printk("hrtimer %p, func %pf, expires %llu, softexpires %llu", + __entry->timer, __entry->function, + (unsigned long long)ktime_to_ns((ktime_t) { + .tv64 = __entry->expires }), + (unsigned long long)ktime_to_ns((ktime_t) { + .tv64 = __entry->softexpires })) +); + +/** + * htimmer_expire_entry - called immediately before the hrtimer callback + * @timer: pointer to struct hrtimer + * @now: pointer to variable which contains current time of the + * timers base. + * + * Allows to determine the timer latency. + */ +TRACE_EVENT(hrtimer_expire_entry, + + TP_PROTO(struct hrtimer *timer, ktime_t *now), + + TP_ARGS(timer, now), + + TP_STRUCT__entry( + __field( void *, timer ) + __field( s64, now ) + ), + + TP_fast_assign( + __entry->timer = timer; + __entry->now = now->tv64; + ), + + TP_printk("hrtimer %p, now %llu", __entry->timer, + (unsigned long long)ktime_to_ns((ktime_t) { + .tv64 = __entry->now })) + ); + +/** + * hrtimer_expire_exit - called immediately after the hrtimer callback returns + * @timer: pointer to struct hrtimer + * + * When used in combination with the hrtimer_expire_entry tracepoint we can + * determine the runtime of the callback function. + */ +TRACE_EVENT(hrtimer_expire_exit, + + TP_PROTO(struct hrtimer *timer), + + TP_ARGS(timer), + + TP_STRUCT__entry( + __field( void *, timer ) + ), + + TP_fast_assign( + __entry->timer = timer; + ), + + TP_printk("hrtimer %p", __entry->timer) +); + +/** + * hrtimer_cancel - called when the hrtimer is canceled + * @timer: pointer to struct hrtimer + */ +TRACE_EVENT(hrtimer_cancel, + + TP_PROTO(struct hrtimer *timer), + + TP_ARGS(timer), + + TP_STRUCT__entry( + __field( void *, timer ) + ), + + TP_fast_assign( + __entry->timer = timer; + ), + + TP_printk("hrtimer %p", __entry->timer) +); + #endif /* _TRACE_TIMER_H */ /* This part must be outside protection */ diff --git a/kernel/hrtimer.c b/kernel/hrtimer.c index e2f91ec..b44d1b0 100644 --- a/kernel/hrtimer.c +++ b/kernel/hrtimer.c @@ -48,6 +48,8 @@ #include +#include + /* * The timer bases: * @@ -441,6 +443,26 @@ static inline void debug_hrtimer_activate(struct hrtimer *timer) { } static inline void debug_hrtimer_deactivate(struct hrtimer *timer) { } #endif +static inline void +debug_init(struct hrtimer *timer, clockid_t clockid, + enum hrtimer_mode mode) +{ + debug_hrtimer_init(timer); + trace_hrtimer_init(timer, clockid, mode); +} + +static inline void debug_activate(struct hrtimer *timer) +{ + debug_hrtimer_activate(timer); + trace_hrtimer_start(timer); +} + +static inline void debug_deactivate(struct hrtimer *timer) +{ + debug_hrtimer_deactivate(timer); + trace_hrtimer_cancel(timer); +} + /* High resolution timer related functions */ #ifdef CONFIG_HIGH_RES_TIMERS @@ -797,7 +819,7 @@ static int enqueue_hrtimer(struct hrtimer *timer, struct hrtimer *entry; int leftmost = 1; - debug_hrtimer_activate(timer); + debug_activate(timer); /* * Find the right place in the rbtree: @@ -883,7 +905,7 @@ remove_hrtimer(struct hrtimer *timer, struct hrtimer_clock_base *base) * reprogramming happens in the interrupt handler. This is a * rare case and less expensive than a smp call. */ - debug_hrtimer_deactivate(timer); + debug_deactivate(timer); timer_stats_hrtimer_clear_start_info(timer); reprogram = base->cpu_base == &__get_cpu_var(hrtimer_bases); __remove_hrtimer(timer, base, HRTIMER_STATE_INACTIVE, @@ -1116,7 +1138,7 @@ static void __hrtimer_init(struct hrtimer *timer, clockid_t clock_id, void hrtimer_init(struct hrtimer *timer, clockid_t clock_id, enum hrtimer_mode mode) { - debug_hrtimer_init(timer); + debug_init(timer, clock_id, mode); __hrtimer_init(timer, clock_id, mode); } EXPORT_SYMBOL_GPL(hrtimer_init); @@ -1140,7 +1162,7 @@ int hrtimer_get_res(const clockid_t which_clock, struct timespec *tp) } EXPORT_SYMBOL_GPL(hrtimer_get_res); -static void __run_hrtimer(struct hrtimer *timer) +static void __run_hrtimer(struct hrtimer *timer, ktime_t *now) { struct hrtimer_clock_base *base = timer->base; struct hrtimer_cpu_base *cpu_base = base->cpu_base; @@ -1149,7 +1171,7 @@ static void __run_hrtimer(struct hrtimer *timer) WARN_ON(!irqs_disabled()); - debug_hrtimer_deactivate(timer); + debug_deactivate(timer); __remove_hrtimer(timer, base, HRTIMER_STATE_CALLBACK, 0); timer_stats_account_hrtimer(timer); fn = timer->function; @@ -1160,7 +1182,9 @@ static void __run_hrtimer(struct hrtimer *timer) * the timer base. */ spin_unlock(&cpu_base->lock); + trace_hrtimer_expire_entry(timer, now); restart = fn(timer); + trace_hrtimer_expire_exit(timer); spin_lock(&cpu_base->lock); /* @@ -1271,7 +1295,7 @@ void hrtimer_interrupt(struct clock_event_device *dev) break; } - __run_hrtimer(timer); + __run_hrtimer(timer, &basenow); } base++; } @@ -1393,7 +1417,7 @@ void hrtimer_run_queues(void) hrtimer_get_expires_tv64(timer)) break; - __run_hrtimer(timer); + __run_hrtimer(timer, &base->softirq_time); } spin_unlock(&cpu_base->lock); } @@ -1569,7 +1593,7 @@ static void migrate_hrtimer_list(struct hrtimer_clock_base *old_base, while ((node = rb_first(&old_base->active))) { timer = rb_entry(node, struct hrtimer, node); BUG_ON(hrtimer_callback_running(timer)); - debug_hrtimer_deactivate(timer); + debug_deactivate(timer); /* * Mark it as STATE_MIGRATE not INACTIVE otherwise the -- cgit v0.10.2 From 3f0a525ebf4b8ef041a332bbe4a73aee94bb064b Mon Sep 17 00:00:00 2001 From: Xiao Guangrong Date: Mon, 10 Aug 2009 10:52:30 +0800 Subject: itimers: Add tracepoints for itimer Add tracepoints for all itimer variants: ITIMER_REAL, ITIMER_VIRTUAL and ITIMER_PROF. [ tglx: Fixed comments and made the output more readable, parseable and consistent. Replaced pid_vnr by pid_nr because the hrtimer callback can happen in any namespace ] Signed-off-by: Xiao Guangrong Cc: Steven Rostedt Cc: Frederic Weisbecker Cc: Mathieu Desnoyers Cc: Anton Blanchard Cc: Peter Zijlstra Cc: KOSAKI Motohiro Cc: Zhaolei LKML-Reference: <4A7F8B6E.2010109@cn.fujitsu.com> Signed-off-by: Thomas Gleixner diff --git a/include/trace/events/timer.h b/include/trace/events/timer.h index df3c07f..1844c48 100644 --- a/include/trace/events/timer.h +++ b/include/trace/events/timer.h @@ -270,6 +270,72 @@ TRACE_EVENT(hrtimer_cancel, TP_printk("hrtimer %p", __entry->timer) ); +/** + * itimer_state - called when itimer is started or canceled + * @which: name of the interval timer + * @value: the itimers value, itimer is canceled if value->it_value is + * zero, otherwise it is started + * @expires: the itimers expiry time + */ +TRACE_EVENT(itimer_state, + + TP_PROTO(int which, const struct itimerval *const value, + cputime_t expires), + + TP_ARGS(which, value, expires), + + TP_STRUCT__entry( + __field( int, which ) + __field( cputime_t, expires ) + __field( long, value_sec ) + __field( long, value_usec ) + __field( long, interval_sec ) + __field( long, interval_usec ) + ), + + TP_fast_assign( + __entry->which = which; + __entry->expires = expires; + __entry->value_sec = value->it_value.tv_sec; + __entry->value_usec = value->it_value.tv_usec; + __entry->interval_sec = value->it_interval.tv_sec; + __entry->interval_usec = value->it_interval.tv_usec; + ), + + TP_printk("which %d, expires %lu, it_value %lu.%lu, it_interval %lu.%lu", + __entry->which, __entry->expires, + __entry->value_sec, __entry->value_usec, + __entry->interval_sec, __entry->interval_usec) +); + +/** + * itimer_expire - called when itimer expires + * @which: type of the interval timer + * @pid: pid of the process which owns the timer + * @now: current time, used to calculate the latency of itimer + */ +TRACE_EVENT(itimer_expire, + + TP_PROTO(int which, struct pid *pid, cputime_t now), + + TP_ARGS(which, pid, now), + + TP_STRUCT__entry( + __field( int , which ) + __field( pid_t, pid ) + __field( cputime_t, now ) + ), + + TP_fast_assign( + __entry->which = which; + __entry->now = now; + __entry->pid = pid_nr(pid); + ), + + TP_printk("which %d, pid %d, now %lu", __entry->which, + (int) __entry->pid, __entry->now) +); + #endif /* _TRACE_TIMER_H */ /* This part must be outside protection */ diff --git a/kernel/itimer.c b/kernel/itimer.c index 8078a32..b03451e 100644 --- a/kernel/itimer.c +++ b/kernel/itimer.c @@ -12,6 +12,7 @@ #include #include #include +#include #include @@ -122,6 +123,7 @@ enum hrtimer_restart it_real_fn(struct hrtimer *timer) struct signal_struct *sig = container_of(timer, struct signal_struct, real_timer); + trace_itimer_expire(ITIMER_REAL, sig->leader_pid, 0); kill_pid_info(SIGALRM, SEND_SIG_PRIV, sig->leader_pid); return HRTIMER_NORESTART; @@ -166,6 +168,8 @@ static void set_cpu_itimer(struct task_struct *tsk, unsigned int clock_id, } it->expires = nval; it->incr = ninterval; + trace_itimer_state(clock_id == CPUCLOCK_VIRT ? + ITIMER_VIRTUAL : ITIMER_PROF, value, nval); spin_unlock_irq(&tsk->sighand->siglock); @@ -217,6 +221,7 @@ again: } else tsk->signal->it_real_incr.tv64 = 0; + trace_itimer_state(ITIMER_REAL, value, 0); spin_unlock_irq(&tsk->sighand->siglock); break; case ITIMER_VIRTUAL: diff --git a/kernel/posix-cpu-timers.c b/kernel/posix-cpu-timers.c index 12161f7..5c9dc22 100644 --- a/kernel/posix-cpu-timers.c +++ b/kernel/posix-cpu-timers.c @@ -8,6 +8,7 @@ #include #include #include +#include /* * Called after updating RLIMIT_CPU to set timer expiration if necessary. @@ -1090,9 +1091,13 @@ static void check_cpu_itimer(struct task_struct *tsk, struct cpu_itimer *it, cputime_one_jiffy); it->error -= onecputick; } - } else + } else { it->expires = cputime_zero; + } + trace_itimer_expire(signo == SIGPROF ? + ITIMER_PROF : ITIMER_VIRTUAL, + tsk->signal->leader_pid, cur_time); __group_send_sig_info(signo, SEND_SIG_PRIV, tsk); } -- cgit v0.10.2 From be96666065fd36ccfa09a13903d31d7ff5f4ef91 Mon Sep 17 00:00:00 2001 From: Corentin Chary Date: Sat, 29 Aug 2009 10:28:29 +0200 Subject: asus-laptop: Fix coding style for comments Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c index 5b912cc..b39d2bb 100644 --- a/drivers/platform/x86/asus-laptop.c +++ b/drivers/platform/x86/asus-laptop.c @@ -77,16 +77,16 @@ * Flags for hotk status * WL_ON and BT_ON are also used for wireless_status() */ -#define WL_ON 0x01 //internal Wifi -#define BT_ON 0x02 //internal Bluetooth -#define MLED_ON 0x04 //mail LED -#define TLED_ON 0x08 //touchpad LED -#define RLED_ON 0x10 //Record LED -#define PLED_ON 0x20 //Phone LED -#define GLED_ON 0x40 //Gaming LED -#define LCD_ON 0x80 //LCD backlight -#define GPS_ON 0x100 //GPS -#define KEY_ON 0x200 //Keyboard backlight +#define WL_ON 0x01 /* internal Wifi */ +#define BT_ON 0x02 /* internal Bluetooth */ +#define MLED_ON 0x04 /* mail LED */ +#define TLED_ON 0x08 /* touchpad LED */ +#define RLED_ON 0x10 /* Record LED */ +#define PLED_ON 0x20 /* Phone LED */ +#define GLED_ON 0x40 /* Gaming LED */ +#define LCD_ON 0x80 /* LCD backlight */ +#define GPS_ON 0x100 /* GPS */ +#define KEY_ON 0x200 /* Keyboard backlight */ #define ASUS_LOG ASUS_HOTK_FILE ": " #define ASUS_ERR KERN_ERR ASUS_LOG @@ -99,7 +99,8 @@ MODULE_AUTHOR("Julien Lerouge, Karol Kozimor, Corentin Chary"); MODULE_DESCRIPTION(ASUS_HOTK_NAME); MODULE_LICENSE("GPL"); -/* WAPF defines the behavior of the Fn+Fx wlan key +/* + * WAPF defines the behavior of the Fn+Fx wlan key * The significance of values is yet to be found, but * most of the time: * 0x0 will do nothing @@ -126,7 +127,8 @@ ASUS_HANDLE(gled_set, ASUS_HOTK_PREFIX "GLED"); /* G1, G2 (probably) */ /* LEDD */ ASUS_HANDLE(ledd_set, ASUS_HOTK_PREFIX "SLCM"); -/* Bluetooth and WLAN +/* + * Bluetooth and WLAN * WLED and BLED are not handled like other XLED, because in some dsdt * they also control the WLAN/Bluetooth device. */ @@ -150,22 +152,32 @@ ASUS_HANDLE(lcd_switch, "\\_SB.PCI0.SBRG.EC0._Q10", /* All new models */ /* Display */ ASUS_HANDLE(display_set, ASUS_HOTK_PREFIX "SDSP"); -ASUS_HANDLE(display_get, "\\_SB.PCI0.P0P1.VGA.GETD", /* A6B, A6K A6R A7D F3JM L4R M6R A3G - M6A M6V VX-1 V6J V6V W3Z */ - "\\_SB.PCI0.P0P2.VGA.GETD", /* A3E A4K, A4D A4L A6J A7J A8J Z71V M9V - S5A M5A z33A W1Jc W2V G1 */ - "\\_SB.PCI0.P0P3.VGA.GETD", /* A6V A6Q */ - "\\_SB.PCI0.P0PA.VGA.GETD", /* A6T, A6M */ - "\\_SB.PCI0.PCI1.VGAC.NMAP", /* L3C */ - "\\_SB.PCI0.VGA.GETD", /* Z96F */ - "\\ACTD", /* A2D */ - "\\ADVG", /* A4G Z71A W1N W5A W5F M2N M3N M5N M6N S1N S5N */ - "\\DNXT", /* P30 */ - "\\INFB", /* A2H D1 L2D L3D L3H L2E L5D L5C M1A M2E L4L W3V */ - "\\SSTE"); /* A3F A6F A3N A3L M6N W3N W6A */ - -ASUS_HANDLE(ls_switch, ASUS_HOTK_PREFIX "ALSC"); /* Z71A Z71V */ -ASUS_HANDLE(ls_level, ASUS_HOTK_PREFIX "ALSL"); /* Z71A Z71V */ +ASUS_HANDLE(display_get, + /* A6B, A6K A6R A7D F3JM L4R M6R A3G M6A M6V VX-1 V6J V6V W3Z */ + "\\_SB.PCI0.P0P1.VGA.GETD", + /* A3E A4K, A4D A4L A6J A7J A8J Z71V M9V S5A M5A z33A W1Jc W2V G1 */ + "\\_SB.PCI0.P0P2.VGA.GETD", + /* A6V A6Q */ + "\\_SB.PCI0.P0P3.VGA.GETD", + /* A6T, A6M */ + "\\_SB.PCI0.P0PA.VGA.GETD", + /* L3C */ + "\\_SB.PCI0.PCI1.VGAC.NMAP", + /* Z96F */ + "\\_SB.PCI0.VGA.GETD", + /* A2D */ + "\\ACTD", + /* A4G Z71A W1N W5A W5F M2N M3N M5N M6N S1N S5N */ + "\\ADVG", + /* P30 */ + "\\DNXT", + /* A2H D1 L2D L3D L3H L2E L5D L5C M1A M2E L4L W3V */ + "\\INFB", + /* A3F A6F A3N A3L M6N W3N W6A */ + "\\SSTE"); + +ASUS_HANDLE(ls_switch, ASUS_HOTK_PREFIX "ALSC"); /* Z71A Z71V */ +ASUS_HANDLE(ls_level, ASUS_HOTK_PREFIX "ALSL"); /* Z71A Z71V */ /* GPS */ /* R2H use different handle for GPS on/off */ @@ -182,14 +194,14 @@ ASUS_HANDLE(kled_get, ASUS_HOTK_PREFIX "GLKB"); * about the hotk device */ struct asus_hotk { - char *name; //laptop name - struct acpi_device *device; //the device we are in - acpi_handle handle; //the handle of the hotk device - char status; //status of the hotk, for LEDs, ... - u32 ledd_status; //status of the LED display - u8 light_level; //light sensor level - u8 light_switch; //light sensor switch value - u16 event_count[128]; //count for each event TODO make this better + char *name; /* laptop name */ + struct acpi_device *device; /* the device we are in */ + acpi_handle handle; /* the handle of the hotk device */ + char status; /* status of the hotk, for LEDs, ... */ + u32 ledd_status; /* status of the LED display */ + u8 light_level; /* light sensor level */ + u8 light_switch; /* light sensor switch value */ + u16 event_count[128]; /* count for each event TODO make this better */ struct input_dev *inputdev; u16 *keycode_map; }; @@ -242,10 +254,12 @@ static struct backlight_ops asusbl_ops = { .update_status = update_bl_status, }; -/* These functions actually update the LED's, and are called from a +/* + * These functions actually update the LED's, and are called from a * workqueue. By doing this as separate work rather than when the LED * subsystem asks, we avoid messing with the Asus ACPI stuff during a - * potentially bad time, such as a timer interrupt. */ + * potentially bad time, such as a timer interrupt. + */ static struct workqueue_struct *led_workqueue; #define ASUS_LED(object, ledname, max) \ @@ -318,8 +332,8 @@ static struct key_entry asus_keymap[] = { static int write_acpi_int(acpi_handle handle, const char *method, int val, struct acpi_buffer *output) { - struct acpi_object_list params; //list of input parameters (an int here) - union acpi_object in_obj; //the only param we use + struct acpi_object_list params; /* list of input parameters (an int) */ + union acpi_object in_obj; /* the only param we use */ acpi_status status; if (!handle) @@ -574,7 +588,7 @@ static ssize_t show_infos(struct device *dev, { int len = 0; unsigned long long temp; - char buf[16]; //enough for all info + char buf[16]; /* enough for all info */ acpi_status rv = AE_OK; /* @@ -734,8 +748,10 @@ static int read_display(void) unsigned long long value = 0; acpi_status rv = AE_OK; - /* In most of the case, we know how to set the display, but sometime - we can't read it */ + /* + * In most of the case, we know how to set the display, but sometime + * we can't read it + */ if (display_get_handle) { rv = acpi_evaluate_integer(display_get_handle, NULL, NULL, &value); @@ -1152,8 +1168,10 @@ static int asus_hotk_get_info(void) ASUS_HANDLE_INIT(display_set); ASUS_HANDLE_INIT(display_get); - /* There is a lot of models with "ALSL", but a few get - a real light sens, so we need to check it. */ + /* + * There is a lot of models with "ALSL", but a few get + * a real light sens, so we need to check it. + */ if (!ASUS_HANDLE_INIT(ls_switch)) ASUS_HANDLE_INIT(ls_level); -- cgit v0.10.2 From a8258069793609903b5ebf0bca3320249154c379 Mon Sep 17 00:00:00 2001 From: Alan Jenkins Date: Sat, 29 Aug 2009 10:28:30 +0200 Subject: eeepc-laptop: fix rfkill memory leak on unload rfkill_unregister() should always be followed by rfkill_destroy() Signed-off-by: Alan Jenkins Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index 819c685..6f9a448 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -985,6 +985,7 @@ static void eeepc_rfkill_exit(void) eeepc_unregister_rfkill_notifier("\\_SB.PCI0.P0P7"); if (ehotk->wlan_rfkill) { rfkill_unregister(ehotk->wlan_rfkill); + rfkill_destroy(ehotk->wlan_rfkill); ehotk->wlan_rfkill = NULL; } /* @@ -995,12 +996,21 @@ static void eeepc_rfkill_exit(void) if (ehotk->hotplug_slot) pci_hp_deregister(ehotk->hotplug_slot); - if (ehotk->bluetooth_rfkill) + if (ehotk->bluetooth_rfkill) { rfkill_unregister(ehotk->bluetooth_rfkill); - if (ehotk->wwan3g_rfkill) + rfkill_destroy(ehotk->bluetooth_rfkill); + ehotk->bluetooth_rfkill = NULL; + } + if (ehotk->wwan3g_rfkill) { rfkill_unregister(ehotk->wwan3g_rfkill); - if (ehotk->wimax_rfkill) + rfkill_destroy(ehotk->wwan3g_rfkill); + ehotk->wwan3g_rfkill = NULL; + } + if (ehotk->wimax_rfkill) { rfkill_unregister(ehotk->wimax_rfkill); + rfkill_destroy(ehotk->wimax_rfkill); + ehotk->wimax_rfkill = NULL; + } } static void eeepc_input_exit(void) -- cgit v0.10.2 From 52cc96bd5b61775db2792780c610979fc02313eb Mon Sep 17 00:00:00 2001 From: Alan Jenkins Date: Sat, 29 Aug 2009 10:28:31 +0200 Subject: eeepc-laptop: allow rfkill hotplug to work on the 900A model The 900A provides hotplug notifications on a different ACPI object to other models. Reported-by: Trevor Signed-off-by: Alan Jenkins Signed-off-by: Corentin Chary Signed-off-by: Len Brown diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index 6f9a448..da3c08b 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c @@ -981,6 +981,7 @@ static void eeepc_backlight_exit(void) static void eeepc_rfkill_exit(void) { + eeepc_unregister_rfkill_notifier("\\_SB.PCI0.P0P5"); eeepc_unregister_rfkill_notifier("\\_SB.PCI0.P0P6"); eeepc_unregister_rfkill_notifier("\\_SB.PCI0.P0P7"); if (ehotk->wlan_rfkill) { @@ -1101,6 +1102,7 @@ static int eeepc_rfkill_init(struct device *dev) if (result == -EBUSY) result = 0; + eeepc_register_rfkill_notifier("\\_SB.PCI0.P0P5"); eeepc_register_rfkill_notifier("\\_SB.PCI0.P0P6"); eeepc_register_rfkill_notifier("\\_SB.PCI0.P0P7"); /* -- cgit v0.10.2 From 138d15692bf76841f252d4b836a535cf5f9154e9 Mon Sep 17 00:00:00 2001 From: Alexey Starikovskiy Date: Fri, 28 Aug 2009 23:29:38 +0400 Subject: ACPICA: Don't switch task then not allowed Signed-off-by: Alexey Starikovskiy Signed-off-by: Len Brown diff --git a/include/acpi/platform/aclinux.h b/include/acpi/platform/aclinux.h index fcb8e4b..9d7febd 100644 --- a/include/acpi/platform/aclinux.h +++ b/include/acpi/platform/aclinux.h @@ -149,10 +149,10 @@ static inline void *acpi_os_acquire_object(acpi_cache_t * cache) #define ACPI_FREE(a) kfree(a) /* Used within ACPICA to show where it is safe to preempt execution */ - +#include #define ACPI_PREEMPTION_POINT() \ do { \ - if (!irqs_disabled()) \ + if (!in_atomic_preempt_off()) \ cond_resched(); \ } while (0) -- cgit v0.10.2 From 4e231fa4cbd3ff53fcb7d76eccd6fd86a152a95f Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Wed, 24 Jun 2009 15:17:36 +0800 Subject: ACPI video: ignore buggy _BQC _BQC doesn't return a value listed in _BCL method. http://bugzilla.kernel.org/show_bug.cgi?id=13511 ingore the buggy _BQC method in this case Signed-off-by: Vladimir Serbinenko Signed-off-by: Scott Howard Acked-by: Zhang Rui Signed-off-by: Len Brown diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c index a0cd0c7..2020907 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c @@ -603,6 +603,7 @@ acpi_video_device_lcd_get_level_current(struct acpi_video_device *device, unsigned long long *level) { acpi_status status = AE_OK; + int i; if (device->cap._BQC || device->cap._BCQ) { char *buf = device->cap._BQC ? "_BQC" : "_BCQ"; @@ -618,8 +619,15 @@ acpi_video_device_lcd_get_level_current(struct acpi_video_device *device, } *level += bqc_offset_aml_bug_workaround; - device->brightness->curr = *level; - return 0; + for (i = 2; i < device->brightness->count; i++) + if (device->brightness->levels[i] == *level) { + device->brightness->curr = *level; + return 0; + } + /* BQC returned an invalid level. Stop using it. */ + ACPI_WARNING((AE_INFO, "%s returned an invalid level", + buf)); + device->cap._BQC = device->cap._BCQ = 0; } else { /* Fixme: * should we return an error or ignore this failure? -- cgit v0.10.2 From bc76f90b8a5cf4aceedf210d08d5e8292f820cec Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 6 Aug 2009 15:57:48 -0700 Subject: ACPI battery: work around negative s16 battery current on Acer Acer Aspire 8930G laptops (and possibly others) report the battery current as a 16-bit signed negative when it is charging. It also reports it as 0x10000 when the current is 0. This patch adds a quirk for this which takes the absolute value of the reported current cast to an s16. This is a DSDT bug present in the latest BIOS revision (the EC register is 16 bits signed and the DSDT attempts to take the 16-bit two's complement of this, which works for discharge but not charge. It also breaks zero values because a 32-bit register is used and the high bits aren't thrown away). I've enabled this for all Acer systems which report in mA units. This should be safe since it won't break compliant systems unless they report a current above 32A, which is insane. The patch also detects the valid 32-bit value -1, which indicates unknown status, and does not attempt the fix in that case (note that this does not conflict with 16-bit -1, which is 65535 as read normally and gets translated to 1mA). Signed-off-by: Hector Martin Acked-by: Alexey Starikovskiy Signed-off-by: Andrew Morton Signed-off-by: Len Brown diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c index 58b4517..d7a786d 100644 --- a/drivers/acpi/battery.c +++ b/drivers/acpi/battery.c @@ -31,6 +31,7 @@ #include #include #include +#include #ifdef CONFIG_ACPI_PROCFS_POWER #include @@ -85,6 +86,10 @@ static const struct acpi_device_id battery_device_ids[] = { MODULE_DEVICE_TABLE(acpi, battery_device_ids); +/* For buggy DSDTs that report negative 16-bit values for either charging + * or discharging current and/or report 0 as 65536 due to bad math. + */ +#define QUIRK_SIGNED16_CURRENT 0x0001 struct acpi_battery { struct mutex lock; @@ -112,6 +117,7 @@ struct acpi_battery { int state; int power_unit; u8 alarm_present; + long quirks; }; #define to_acpi_battery(x) container_of(x, struct acpi_battery, bat); @@ -390,6 +396,11 @@ static int acpi_battery_get_state(struct acpi_battery *battery) state_offsets, ARRAY_SIZE(state_offsets)); battery->update_time = jiffies; kfree(buffer.pointer); + + if ((battery->quirks & QUIRK_SIGNED16_CURRENT) && + battery->rate_now != -1) + battery->rate_now = abs((s16)battery->rate_now); + return result; } @@ -495,6 +506,14 @@ static void sysfs_remove_battery(struct acpi_battery *battery) } #endif +static void acpi_battery_quirks(struct acpi_battery *battery) +{ + battery->quirks = 0; + if (dmi_name_in_vendors("Acer") && battery->power_unit) { + battery->quirks |= QUIRK_SIGNED16_CURRENT; + } +} + static int acpi_battery_update(struct acpi_battery *battery) { int result, old_present = acpi_battery_present(battery); @@ -513,6 +532,7 @@ static int acpi_battery_update(struct acpi_battery *battery) result = acpi_battery_get_info(battery); if (result) return result; + acpi_battery_quirks(battery); acpi_battery_init_alarm(battery); } #ifdef CONFIG_ACPI_SYSFS_POWER -- cgit v0.10.2 From 2a84cb9852f52c0cd1c48bca41a8792d44ad06cc Mon Sep 17 00:00:00 2001 From: Alexey Starikovskiy Date: Sun, 30 Aug 2009 03:06:14 +0400 Subject: ACPI: EC: Merge IRQ and POLL modes In general, EC transaction should complete in less than 1ms, thus it is possible to merge wait for 1ms in poll mode and 1ms of interrupt transaction timeout. Still, driver will wait 500ms for EC to complete transaction. This significantly simplifies driver and makes it immune to problematic EC interrupt implementations. It also may lessen kernel start-up time by 500ms. References: http://bugzilla.kernel.org/show_bug.cgi?id=12949 Signed-off-by: Alexey Starikovskiy Signed-off-by: Len Brown diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index 391f331..839b542 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -68,15 +68,13 @@ enum ec_command { #define ACPI_EC_DELAY 500 /* Wait 500ms max. during EC ops */ #define ACPI_EC_UDELAY_GLK 1000 /* Wait 1ms max. to get global lock */ #define ACPI_EC_CDELAY 10 /* Wait 10us before polling EC */ +#define ACPI_EC_MSI_UDELAY 550 /* Wait 550us for MSI EC */ #define ACPI_EC_STORM_THRESHOLD 8 /* number of false interrupts per one transaction */ enum { EC_FLAGS_QUERY_PENDING, /* Query is pending */ - EC_FLAGS_GPE_MODE, /* Expect GPE to be sent - * for status change */ - EC_FLAGS_NO_GPE, /* Don't use GPE mode */ EC_FLAGS_GPE_STORM, /* GPE storm detected */ EC_FLAGS_HANDLERS_INSTALLED /* Handlers for GPE and * OpReg are installed */ @@ -170,7 +168,7 @@ static void start_transaction(struct acpi_ec *ec) acpi_ec_write_cmd(ec, ec->curr->command); } -static void gpe_transaction(struct acpi_ec *ec, u8 status) +static void advance_transaction(struct acpi_ec *ec, u8 status) { unsigned long flags; spin_lock_irqsave(&ec->curr_lock, flags); @@ -201,29 +199,6 @@ unlock: spin_unlock_irqrestore(&ec->curr_lock, flags); } -static int acpi_ec_wait(struct acpi_ec *ec) -{ - if (wait_event_timeout(ec->wait, ec_transaction_done(ec), - msecs_to_jiffies(ACPI_EC_DELAY))) - return 0; - /* try restart command if we get any false interrupts */ - if (ec->curr->irq_count && - (acpi_ec_read_status(ec) & ACPI_EC_FLAG_IBF) == 0) { - pr_debug(PREFIX "controller reset, restart transaction\n"); - start_transaction(ec); - if (wait_event_timeout(ec->wait, ec_transaction_done(ec), - msecs_to_jiffies(ACPI_EC_DELAY))) - return 0; - } - /* missing GPEs, switch back to poll mode */ - if (printk_ratelimit()) - pr_info(PREFIX "missing confirmations, " - "switch off interrupt mode.\n"); - set_bit(EC_FLAGS_NO_GPE, &ec->flags); - clear_bit(EC_FLAGS_GPE_MODE, &ec->flags); - return 1; -} - static void acpi_ec_gpe_query(void *ec_cxt); static int ec_check_sci(struct acpi_ec *ec, u8 state) @@ -236,43 +211,51 @@ static int ec_check_sci(struct acpi_ec *ec, u8 state) return 0; } -static void ec_delay(void) -{ - /* EC in MSI notebooks don't tolerate delays other than 550 usec */ - if (EC_FLAGS_MSI) - udelay(ACPI_EC_DELAY); - else - /* Use shortest sleep available */ - msleep(1); -} - static int ec_poll(struct acpi_ec *ec) { - unsigned long delay = jiffies + msecs_to_jiffies(ACPI_EC_DELAY); - udelay(ACPI_EC_CDELAY); - while (time_before(jiffies, delay)) { - gpe_transaction(ec, acpi_ec_read_status(ec)); - ec_delay(); - if (ec_transaction_done(ec)) - return 0; + unsigned long flags; + int repeat = 2; /* number of command restarts */ + while (repeat--) { + unsigned long delay = jiffies + + msecs_to_jiffies(ACPI_EC_DELAY); + do { + /* don't sleep with disabled interrupts */ + if (EC_FLAGS_MSI || irqs_disabled()) { + udelay(ACPI_EC_MSI_UDELAY); + if (ec_transaction_done(ec)) + return 0; + } else { + if (wait_event_timeout(ec->wait, + ec_transaction_done(ec), + msecs_to_jiffies(1))) + return 0; + } + advance_transaction(ec, acpi_ec_read_status(ec)); + } while (time_before(jiffies, delay)); + if (!ec->curr->irq_count || + (acpi_ec_read_status(ec) & ACPI_EC_FLAG_IBF)) + break; + /* try restart command if we get any false interrupts */ + pr_debug(PREFIX "controller reset, restart transaction\n"); + spin_lock_irqsave(&ec->curr_lock, flags); + start_transaction(ec); + spin_unlock_irqrestore(&ec->curr_lock, flags); } return -ETIME; } static int acpi_ec_transaction_unlocked(struct acpi_ec *ec, - struct transaction *t, - int force_poll) + struct transaction *t) { unsigned long tmp; int ret = 0; pr_debug(PREFIX "transaction start\n"); /* disable GPE during transaction if storm is detected */ if (test_bit(EC_FLAGS_GPE_STORM, &ec->flags)) { - clear_bit(EC_FLAGS_GPE_MODE, &ec->flags); acpi_disable_gpe(NULL, ec->gpe); } if (EC_FLAGS_MSI) - udelay(ACPI_EC_DELAY); + udelay(ACPI_EC_MSI_UDELAY); /* start transaction */ spin_lock_irqsave(&ec->curr_lock, tmp); /* following two actions should be kept atomic */ @@ -281,11 +264,7 @@ static int acpi_ec_transaction_unlocked(struct acpi_ec *ec, if (ec->curr->command == ACPI_EC_COMMAND_QUERY) clear_bit(EC_FLAGS_QUERY_PENDING, &ec->flags); spin_unlock_irqrestore(&ec->curr_lock, tmp); - /* if we selected poll mode or failed in GPE-mode do a poll loop */ - if (force_poll || - !test_bit(EC_FLAGS_GPE_MODE, &ec->flags) || - acpi_ec_wait(ec)) - ret = ec_poll(ec); + ret = ec_poll(ec); pr_debug(PREFIX "transaction end\n"); spin_lock_irqsave(&ec->curr_lock, tmp); ec->curr = NULL; @@ -295,8 +274,7 @@ static int acpi_ec_transaction_unlocked(struct acpi_ec *ec, ec_check_sci(ec, acpi_ec_read_status(ec)); /* it is safe to enable GPE outside of transaction */ acpi_enable_gpe(NULL, ec->gpe); - } else if (test_bit(EC_FLAGS_GPE_MODE, &ec->flags) && - t->irq_count > ACPI_EC_STORM_THRESHOLD) { + } else if (t->irq_count > ACPI_EC_STORM_THRESHOLD) { pr_info(PREFIX "GPE storm detected, " "transactions will use polling mode\n"); set_bit(EC_FLAGS_GPE_STORM, &ec->flags); @@ -314,16 +292,14 @@ static int ec_wait_ibf0(struct acpi_ec *ec) { unsigned long delay = jiffies + msecs_to_jiffies(ACPI_EC_DELAY); /* interrupt wait manually if GPE mode is not active */ - unsigned long timeout = test_bit(EC_FLAGS_GPE_MODE, &ec->flags) ? - msecs_to_jiffies(ACPI_EC_DELAY) : msecs_to_jiffies(1); while (time_before(jiffies, delay)) - if (wait_event_timeout(ec->wait, ec_check_ibf0(ec), timeout)) + if (wait_event_timeout(ec->wait, ec_check_ibf0(ec), + msecs_to_jiffies(1))) return 0; return -ETIME; } -static int acpi_ec_transaction(struct acpi_ec *ec, struct transaction *t, - int force_poll) +static int acpi_ec_transaction(struct acpi_ec *ec, struct transaction *t) { int status; u32 glk; @@ -345,7 +321,7 @@ static int acpi_ec_transaction(struct acpi_ec *ec, struct transaction *t, status = -ETIME; goto end; } - status = acpi_ec_transaction_unlocked(ec, t, force_poll); + status = acpi_ec_transaction_unlocked(ec, t); end: if (ec->global_lock) acpi_release_global_lock(glk); @@ -365,7 +341,7 @@ static int acpi_ec_burst_enable(struct acpi_ec *ec) .wdata = NULL, .rdata = &d, .wlen = 0, .rlen = 1}; - return acpi_ec_transaction(ec, &t, 0); + return acpi_ec_transaction(ec, &t); } static int acpi_ec_burst_disable(struct acpi_ec *ec) @@ -375,7 +351,7 @@ static int acpi_ec_burst_disable(struct acpi_ec *ec) .wlen = 0, .rlen = 0}; return (acpi_ec_read_status(ec) & ACPI_EC_FLAG_BURST) ? - acpi_ec_transaction(ec, &t, 0) : 0; + acpi_ec_transaction(ec, &t) : 0; } static int acpi_ec_read(struct acpi_ec *ec, u8 address, u8 * data) @@ -386,7 +362,7 @@ static int acpi_ec_read(struct acpi_ec *ec, u8 address, u8 * data) .wdata = &address, .rdata = &d, .wlen = 1, .rlen = 1}; - result = acpi_ec_transaction(ec, &t, 0); + result = acpi_ec_transaction(ec, &t); *data = d; return result; } @@ -398,7 +374,7 @@ static int acpi_ec_write(struct acpi_ec *ec, u8 address, u8 data) .wdata = wdata, .rdata = NULL, .wlen = 2, .rlen = 0}; - return acpi_ec_transaction(ec, &t, 0); + return acpi_ec_transaction(ec, &t); } /* @@ -466,7 +442,7 @@ int ec_transaction(u8 command, if (!first_ec) return -ENODEV; - return acpi_ec_transaction(first_ec, &t, force_poll); + return acpi_ec_transaction(first_ec, &t); } EXPORT_SYMBOL(ec_transaction); @@ -487,7 +463,7 @@ static int acpi_ec_query(struct acpi_ec *ec, u8 * data) * bit to be cleared (and thus clearing the interrupt source). */ - result = acpi_ec_transaction(ec, &t, 0); + result = acpi_ec_transaction(ec, &t); if (result) return result; @@ -570,28 +546,10 @@ static u32 acpi_ec_gpe_handler(void *data) pr_debug(PREFIX "~~~> interrupt\n"); status = acpi_ec_read_status(ec); - if (test_bit(EC_FLAGS_GPE_MODE, &ec->flags)) { - gpe_transaction(ec, status); - if (ec_transaction_done(ec) && - (status & ACPI_EC_FLAG_IBF) == 0) - wake_up(&ec->wait); - } - + advance_transaction(ec, status); + if (ec_transaction_done(ec) && (status & ACPI_EC_FLAG_IBF) == 0) + wake_up(&ec->wait); ec_check_sci(ec, status); - if (!test_bit(EC_FLAGS_GPE_MODE, &ec->flags) && - !test_bit(EC_FLAGS_NO_GPE, &ec->flags)) { - /* this is non-query, must be confirmation */ - if (!test_bit(EC_FLAGS_GPE_STORM, &ec->flags)) { - if (printk_ratelimit()) - pr_info(PREFIX "non-query interrupt received," - " switching to interrupt mode\n"); - } else { - /* hush, STORM switches the mode every transaction */ - pr_debug(PREFIX "non-query interrupt received," - " switching to interrupt mode\n"); - } - set_bit(EC_FLAGS_GPE_MODE, &ec->flags); - } return ACPI_INTERRUPT_HANDLED; } @@ -837,8 +795,6 @@ static int acpi_ec_add(struct acpi_device *device) acpi_ec_add_fs(device); pr_info(PREFIX "GPE = 0x%lx, I/O: command/status = 0x%lx, data = 0x%lx\n", ec->gpe, ec->command_addr, ec->data_addr); - pr_info(PREFIX "driver started in %s mode\n", - (test_bit(EC_FLAGS_GPE_MODE, &ec->flags))?"interrupt":"poll"); return 0; } @@ -1054,8 +1010,6 @@ static int acpi_ec_suspend(struct acpi_device *device, pm_message_t state) { struct acpi_ec *ec = acpi_driver_data(device); /* Stop using GPE */ - set_bit(EC_FLAGS_NO_GPE, &ec->flags); - clear_bit(EC_FLAGS_GPE_MODE, &ec->flags); acpi_disable_gpe(NULL, ec->gpe); return 0; } @@ -1064,8 +1018,6 @@ static int acpi_ec_resume(struct acpi_device *device) { struct acpi_ec *ec = acpi_driver_data(device); /* Enable use of GPE back */ - clear_bit(EC_FLAGS_NO_GPE, &ec->flags); - set_bit(EC_FLAGS_GPE_MODE, &ec->flags); acpi_enable_gpe(NULL, ec->gpe); return 0; } -- cgit v0.10.2 From 6a63b06f3c494cc87eade97f081300bda60acec7 Mon Sep 17 00:00:00 2001 From: Alexey Starikovskiy Date: Fri, 28 Aug 2009 23:29:44 +0400 Subject: ACPI: EC: use BURST mode only for MSI notebooks Signed-off-by: Alexey Starikovskiy Signed-off-by: Len Brown diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index 839b542..788db78 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -575,7 +575,8 @@ acpi_ec_space_handler(u32 function, acpi_physical_address address, if (bits != 8 && acpi_strict) return AE_BAD_PARAMETER; - acpi_ec_burst_enable(ec); + if (EC_FLAGS_MSI) + acpi_ec_burst_enable(ec); if (function == ACPI_READ) { result = acpi_ec_read(ec, address, &temp); @@ -596,7 +597,8 @@ acpi_ec_space_handler(u32 function, acpi_physical_address address, } } - acpi_ec_burst_disable(ec); + if (EC_FLAGS_MSI) + acpi_ec_burst_disable(ec); switch (result) { case -EINVAL: -- cgit v0.10.2 From f25752e67d9d9ee7562ae9944314dd8c057d3fa2 Mon Sep 17 00:00:00 2001 From: Alexey Starikovskiy Date: Fri, 28 Aug 2009 23:29:51 +0400 Subject: ACPI: EC: Drop orphan comment Signed-off-by: Alexey Starikovskiy Signed-off-by: Len Brown diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index 788db78..dc55618 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -330,10 +330,6 @@ unlock: return status; } -/* - * Note: samsung nv5000 doesn't work with ec burst mode. - * http://bugzilla.kernel.org/show_bug.cgi?id=4980 - */ static int acpi_ec_burst_enable(struct acpi_ec *ec) { u8 d; -- cgit v0.10.2 From 36d1c6476be51101778882897b315bd928c8c7b5 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 14 Jul 2009 11:48:22 -0700 Subject: md/raid6: move the spare page to a percpu allocation In preparation for asynchronous handling of raid6 operations move the spare page to a percpu allocation to allow multiple simultaneous synchronous raid6 recovery operations. Make this allocation cpu hotplug aware to maximize allocation efficiency. Signed-off-by: Dan Williams diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 9411466..5359236 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -48,6 +48,7 @@ #include #include #include +#include #include "md.h" #include "raid5.h" #include "bitmap.h" @@ -2565,14 +2566,15 @@ static void handle_parity_checks5(raid5_conf_t *conf, struct stripe_head *sh, static void handle_parity_checks6(raid5_conf_t *conf, struct stripe_head *sh, - struct stripe_head_state *s, - struct r6_state *r6s, struct page *tmp_page, - int disks) + struct stripe_head_state *s, + struct r6_state *r6s, int disks) { int update_p = 0, update_q = 0; struct r5dev *dev; int pd_idx = sh->pd_idx; int qd_idx = sh->qd_idx; + unsigned long cpu; + struct page *tmp_page; set_bit(STRIPE_HANDLE, &sh->state); @@ -2583,78 +2585,75 @@ static void handle_parity_checks6(raid5_conf_t *conf, struct stripe_head *sh, * case we can only check one of them, possibly using the * other to generate missing data */ - - /* If !tmp_page, we cannot do the calculations, - * but as we have set STRIPE_HANDLE, we will soon be called - * by stripe_handle with a tmp_page - just wait until then. - */ - if (tmp_page) { - if (s->failed == r6s->q_failed) { - /* The only possible failed device holds 'Q', so it - * makes sense to check P (If anything else were failed, - * we would have used P to recreate it). - */ - compute_block_1(sh, pd_idx, 1); - if (!page_is_zero(sh->dev[pd_idx].page)) { - compute_block_1(sh, pd_idx, 0); - update_p = 1; - } - } - if (!r6s->q_failed && s->failed < 2) { - /* q is not failed, and we didn't use it to generate - * anything, so it makes sense to check it - */ - memcpy(page_address(tmp_page), - page_address(sh->dev[qd_idx].page), - STRIPE_SIZE); - compute_parity6(sh, UPDATE_PARITY); - if (memcmp(page_address(tmp_page), - page_address(sh->dev[qd_idx].page), - STRIPE_SIZE) != 0) { - clear_bit(STRIPE_INSYNC, &sh->state); - update_q = 1; - } + cpu = get_cpu(); + tmp_page = per_cpu_ptr(conf->percpu, cpu)->spare_page; + if (s->failed == r6s->q_failed) { + /* The only possible failed device holds 'Q', so it + * makes sense to check P (If anything else were failed, + * we would have used P to recreate it). + */ + compute_block_1(sh, pd_idx, 1); + if (!page_is_zero(sh->dev[pd_idx].page)) { + compute_block_1(sh, pd_idx, 0); + update_p = 1; } - if (update_p || update_q) { - conf->mddev->resync_mismatches += STRIPE_SECTORS; - if (test_bit(MD_RECOVERY_CHECK, &conf->mddev->recovery)) - /* don't try to repair!! */ - update_p = update_q = 0; + } + if (!r6s->q_failed && s->failed < 2) { + /* q is not failed, and we didn't use it to generate + * anything, so it makes sense to check it + */ + memcpy(page_address(tmp_page), + page_address(sh->dev[qd_idx].page), + STRIPE_SIZE); + compute_parity6(sh, UPDATE_PARITY); + if (memcmp(page_address(tmp_page), + page_address(sh->dev[qd_idx].page), + STRIPE_SIZE) != 0) { + clear_bit(STRIPE_INSYNC, &sh->state); + update_q = 1; } + } + put_cpu(); - /* now write out any block on a failed drive, - * or P or Q if they need it - */ + if (update_p || update_q) { + conf->mddev->resync_mismatches += STRIPE_SECTORS; + if (test_bit(MD_RECOVERY_CHECK, &conf->mddev->recovery)) + /* don't try to repair!! */ + update_p = update_q = 0; + } - if (s->failed == 2) { - dev = &sh->dev[r6s->failed_num[1]]; - s->locked++; - set_bit(R5_LOCKED, &dev->flags); - set_bit(R5_Wantwrite, &dev->flags); - } - if (s->failed >= 1) { - dev = &sh->dev[r6s->failed_num[0]]; - s->locked++; - set_bit(R5_LOCKED, &dev->flags); - set_bit(R5_Wantwrite, &dev->flags); - } + /* now write out any block on a failed drive, + * or P or Q if they need it + */ - if (update_p) { - dev = &sh->dev[pd_idx]; - s->locked++; - set_bit(R5_LOCKED, &dev->flags); - set_bit(R5_Wantwrite, &dev->flags); - } - if (update_q) { - dev = &sh->dev[qd_idx]; - s->locked++; - set_bit(R5_LOCKED, &dev->flags); - set_bit(R5_Wantwrite, &dev->flags); - } - clear_bit(STRIPE_DEGRADED, &sh->state); + if (s->failed == 2) { + dev = &sh->dev[r6s->failed_num[1]]; + s->locked++; + set_bit(R5_LOCKED, &dev->flags); + set_bit(R5_Wantwrite, &dev->flags); + } + if (s->failed >= 1) { + dev = &sh->dev[r6s->failed_num[0]]; + s->locked++; + set_bit(R5_LOCKED, &dev->flags); + set_bit(R5_Wantwrite, &dev->flags); + } - set_bit(STRIPE_INSYNC, &sh->state); + if (update_p) { + dev = &sh->dev[pd_idx]; + s->locked++; + set_bit(R5_LOCKED, &dev->flags); + set_bit(R5_Wantwrite, &dev->flags); + } + if (update_q) { + dev = &sh->dev[qd_idx]; + s->locked++; + set_bit(R5_LOCKED, &dev->flags); + set_bit(R5_Wantwrite, &dev->flags); } + clear_bit(STRIPE_DEGRADED, &sh->state); + + set_bit(STRIPE_INSYNC, &sh->state); } static void handle_stripe_expansion(raid5_conf_t *conf, struct stripe_head *sh, @@ -3009,7 +3008,7 @@ static bool handle_stripe5(struct stripe_head *sh) return blocked_rdev == NULL; } -static bool handle_stripe6(struct stripe_head *sh, struct page *tmp_page) +static bool handle_stripe6(struct stripe_head *sh) { raid5_conf_t *conf = sh->raid_conf; int disks = sh->disks; @@ -3164,7 +3163,7 @@ static bool handle_stripe6(struct stripe_head *sh, struct page *tmp_page) * data is available */ if (s.syncing && s.locked == 0 && !test_bit(STRIPE_INSYNC, &sh->state)) - handle_parity_checks6(conf, sh, &s, &r6s, tmp_page, disks); + handle_parity_checks6(conf, sh, &s, &r6s, disks); if (s.syncing && s.locked == 0 && test_bit(STRIPE_INSYNC, &sh->state)) { md_done_sync(conf->mddev, STRIPE_SECTORS,1); @@ -3247,16 +3246,14 @@ static bool handle_stripe6(struct stripe_head *sh, struct page *tmp_page) } /* returns true if the stripe was handled */ -static bool handle_stripe(struct stripe_head *sh, struct page *tmp_page) +static bool handle_stripe(struct stripe_head *sh) { if (sh->raid_conf->level == 6) - return handle_stripe6(sh, tmp_page); + return handle_stripe6(sh); else return handle_stripe5(sh); } - - static void raid5_activate_delayed(raid5_conf_t *conf) { if (atomic_read(&conf->preread_active_stripes) < IO_THRESHOLD) { @@ -4047,7 +4044,7 @@ static inline sector_t sync_request(mddev_t *mddev, sector_t sector_nr, int *ski spin_unlock(&sh->lock); /* wait for any blocked device to be handled */ - while(unlikely(!handle_stripe(sh, NULL))) + while (unlikely(!handle_stripe(sh))) ; release_stripe(sh); @@ -4104,7 +4101,7 @@ static int retry_aligned_read(raid5_conf_t *conf, struct bio *raid_bio) return handled; } - handle_stripe(sh, NULL); + handle_stripe(sh); release_stripe(sh); handled++; } @@ -4168,7 +4165,7 @@ static void raid5d(mddev_t *mddev) spin_unlock_irq(&conf->device_lock); handled++; - handle_stripe(sh, conf->spare_page); + handle_stripe(sh); release_stripe(sh); spin_lock_irq(&conf->device_lock); @@ -4309,15 +4306,104 @@ raid5_size(mddev_t *mddev, sector_t sectors, int raid_disks) return sectors * (raid_disks - conf->max_degraded); } +static void raid5_free_percpu(raid5_conf_t *conf) +{ + struct raid5_percpu *percpu; + unsigned long cpu; + + if (!conf->percpu) + return; + + get_online_cpus(); + for_each_possible_cpu(cpu) { + percpu = per_cpu_ptr(conf->percpu, cpu); + safe_put_page(percpu->spare_page); + } +#ifdef CONFIG_HOTPLUG_CPU + unregister_cpu_notifier(&conf->cpu_notify); +#endif + put_online_cpus(); + + free_percpu(conf->percpu); +} + static void free_conf(raid5_conf_t *conf) { shrink_stripes(conf); - safe_put_page(conf->spare_page); + raid5_free_percpu(conf); kfree(conf->disks); kfree(conf->stripe_hashtbl); kfree(conf); } +#ifdef CONFIG_HOTPLUG_CPU +static int raid456_cpu_notify(struct notifier_block *nfb, unsigned long action, + void *hcpu) +{ + raid5_conf_t *conf = container_of(nfb, raid5_conf_t, cpu_notify); + long cpu = (long)hcpu; + struct raid5_percpu *percpu = per_cpu_ptr(conf->percpu, cpu); + + switch (action) { + case CPU_UP_PREPARE: + case CPU_UP_PREPARE_FROZEN: + if (!percpu->spare_page) + percpu->spare_page = alloc_page(GFP_KERNEL); + if (!percpu->spare_page) { + pr_err("%s: failed memory allocation for cpu%ld\n", + __func__, cpu); + return NOTIFY_BAD; + } + break; + case CPU_DEAD: + case CPU_DEAD_FROZEN: + safe_put_page(percpu->spare_page); + percpu->spare_page = NULL; + break; + default: + break; + } + return NOTIFY_OK; +} +#endif + +static int raid5_alloc_percpu(raid5_conf_t *conf) +{ + unsigned long cpu; + struct page *spare_page; + struct raid5_percpu *allcpus; + int err; + + /* the only percpu data is the raid6 spare page */ + if (conf->level != 6) + return 0; + + allcpus = alloc_percpu(struct raid5_percpu); + if (!allcpus) + return -ENOMEM; + conf->percpu = allcpus; + + get_online_cpus(); + err = 0; + for_each_present_cpu(cpu) { + spare_page = alloc_page(GFP_KERNEL); + if (!spare_page) { + err = -ENOMEM; + break; + } + per_cpu_ptr(conf->percpu, cpu)->spare_page = spare_page; + } +#ifdef CONFIG_HOTPLUG_CPU + conf->cpu_notify.notifier_call = raid456_cpu_notify; + conf->cpu_notify.priority = 0; + if (err == 0) + err = register_cpu_notifier(&conf->cpu_notify); +#endif + put_online_cpus(); + + return err; +} + static raid5_conf_t *setup_conf(mddev_t *mddev) { raid5_conf_t *conf; @@ -4372,11 +4458,10 @@ static raid5_conf_t *setup_conf(mddev_t *mddev) if ((conf->stripe_hashtbl = kzalloc(PAGE_SIZE, GFP_KERNEL)) == NULL) goto abort; - if (mddev->new_level == 6) { - conf->spare_page = alloc_page(GFP_KERNEL); - if (!conf->spare_page) - goto abort; - } + conf->level = mddev->new_level; + if (raid5_alloc_percpu(conf) != 0) + goto abort; + spin_lock_init(&conf->device_lock); init_waitqueue_head(&conf->wait_for_stripe); init_waitqueue_head(&conf->wait_for_overlap); @@ -4412,7 +4497,6 @@ static raid5_conf_t *setup_conf(mddev_t *mddev) } conf->chunk_size = mddev->new_chunk; - conf->level = mddev->new_level; if (conf->level == 6) conf->max_degraded = 2; else diff --git a/drivers/md/raid5.h b/drivers/md/raid5.h index 52ba999..07a7a41 100644 --- a/drivers/md/raid5.h +++ b/drivers/md/raid5.h @@ -383,8 +383,13 @@ struct raid5_private_data { * (fresh device added). * Cleared when a sync completes. */ - - struct page *spare_page; /* Used when checking P/Q in raid6 */ + /* per cpu variables */ + struct raid5_percpu { + struct page *spare_page; /* Used when checking P/Q in raid6 */ + } *percpu; +#ifdef CONFIG_HOTPLUG_CPU + struct notifier_block cpu_notify; +#endif /* * Free stripes pool -- cgit v0.10.2 From d6f38f31f3ad4b0dd33fe970988f14e7c65ef702 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 14 Jul 2009 11:50:52 -0700 Subject: md/raid5,6: add percpu scribble region for buffer lists Use percpu memory rather than stack for storing the buffer lists used in parity calculations. Include space for dma address conversions and pass that to async_tx via the async_submit_ctl.scribble pointer. [ Impact: move memory pressure from stack to heap ] Signed-off-by: Dan Williams diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 5359236..7727954 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -642,11 +642,18 @@ static void ops_complete_compute5(void *stripe_head_ref) release_stripe(sh); } -static struct dma_async_tx_descriptor *ops_run_compute5(struct stripe_head *sh) +/* return a pointer to the address conversion region of the scribble buffer */ +static addr_conv_t *to_addr_conv(struct stripe_head *sh, + struct raid5_percpu *percpu) +{ + return percpu->scribble + sizeof(struct page *) * (sh->disks + 2); +} + +static struct dma_async_tx_descriptor * +ops_run_compute5(struct stripe_head *sh, struct raid5_percpu *percpu) { - /* kernel stack size limits the total number of disks */ int disks = sh->disks; - struct page *xor_srcs[disks]; + struct page **xor_srcs = percpu->scribble; int target = sh->ops.target; struct r5dev *tgt = &sh->dev[target]; struct page *xor_dest = tgt->page; @@ -666,7 +673,7 @@ static struct dma_async_tx_descriptor *ops_run_compute5(struct stripe_head *sh) atomic_inc(&sh->count); init_async_submit(&submit, ASYNC_TX_XOR_ZERO_DST, NULL, - ops_complete_compute5, sh, NULL); + ops_complete_compute5, sh, to_addr_conv(sh, percpu)); if (unlikely(count == 1)) tx = async_memcpy(xor_dest, xor_srcs[0], 0, 0, STRIPE_SIZE, &submit); else @@ -684,11 +691,11 @@ static void ops_complete_prexor(void *stripe_head_ref) } static struct dma_async_tx_descriptor * -ops_run_prexor(struct stripe_head *sh, struct dma_async_tx_descriptor *tx) +ops_run_prexor(struct stripe_head *sh, struct raid5_percpu *percpu, + struct dma_async_tx_descriptor *tx) { - /* kernel stack size limits the total number of disks */ int disks = sh->disks; - struct page *xor_srcs[disks]; + struct page **xor_srcs = percpu->scribble; int count = 0, pd_idx = sh->pd_idx, i; struct async_submit_ctl submit; @@ -706,7 +713,7 @@ ops_run_prexor(struct stripe_head *sh, struct dma_async_tx_descriptor *tx) } init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST, tx, - ops_complete_prexor, sh, NULL); + ops_complete_prexor, sh, to_addr_conv(sh, percpu)); tx = async_xor(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, &submit); return tx; @@ -775,11 +782,11 @@ static void ops_complete_postxor(void *stripe_head_ref) } static void -ops_run_postxor(struct stripe_head *sh, struct dma_async_tx_descriptor *tx) +ops_run_postxor(struct stripe_head *sh, struct raid5_percpu *percpu, + struct dma_async_tx_descriptor *tx) { - /* kernel stack size limits the total number of disks */ int disks = sh->disks; - struct page *xor_srcs[disks]; + struct page **xor_srcs = percpu->scribble; struct async_submit_ctl submit; int count = 0, pd_idx = sh->pd_idx, i; struct page *xor_dest; @@ -819,7 +826,8 @@ ops_run_postxor(struct stripe_head *sh, struct dma_async_tx_descriptor *tx) atomic_inc(&sh->count); - init_async_submit(&submit, flags, tx, ops_complete_postxor, sh, NULL); + init_async_submit(&submit, flags, tx, ops_complete_postxor, sh, + to_addr_conv(sh, percpu)); if (unlikely(count == 1)) tx = async_memcpy(xor_dest, xor_srcs[0], 0, 0, STRIPE_SIZE, &submit); else @@ -838,11 +846,10 @@ static void ops_complete_check(void *stripe_head_ref) release_stripe(sh); } -static void ops_run_check(struct stripe_head *sh) +static void ops_run_check(struct stripe_head *sh, struct raid5_percpu *percpu) { - /* kernel stack size limits the total number of disks */ int disks = sh->disks; - struct page *xor_srcs[disks]; + struct page **xor_srcs = percpu->scribble; struct dma_async_tx_descriptor *tx; struct async_submit_ctl submit; @@ -858,7 +865,8 @@ static void ops_run_check(struct stripe_head *sh) xor_srcs[count++] = dev->page; } - init_async_submit(&submit, 0, NULL, NULL, NULL, NULL); + init_async_submit(&submit, 0, NULL, NULL, NULL, + to_addr_conv(sh, percpu)); tx = async_xor_val(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, &sh->ops.zero_sum_result, &submit); @@ -871,21 +879,26 @@ static void raid5_run_ops(struct stripe_head *sh, unsigned long ops_request) { int overlap_clear = 0, i, disks = sh->disks; struct dma_async_tx_descriptor *tx = NULL; + raid5_conf_t *conf = sh->raid_conf; + struct raid5_percpu *percpu; + unsigned long cpu; + cpu = get_cpu(); + percpu = per_cpu_ptr(conf->percpu, cpu); if (test_bit(STRIPE_OP_BIOFILL, &ops_request)) { ops_run_biofill(sh); overlap_clear++; } if (test_bit(STRIPE_OP_COMPUTE_BLK, &ops_request)) { - tx = ops_run_compute5(sh); + tx = ops_run_compute5(sh, percpu); /* terminate the chain if postxor is not set to be run */ if (tx && !test_bit(STRIPE_OP_POSTXOR, &ops_request)) async_tx_ack(tx); } if (test_bit(STRIPE_OP_PREXOR, &ops_request)) - tx = ops_run_prexor(sh, tx); + tx = ops_run_prexor(sh, percpu, tx); if (test_bit(STRIPE_OP_BIODRAIN, &ops_request)) { tx = ops_run_biodrain(sh, tx); @@ -893,10 +906,10 @@ static void raid5_run_ops(struct stripe_head *sh, unsigned long ops_request) } if (test_bit(STRIPE_OP_POSTXOR, &ops_request)) - ops_run_postxor(sh, tx); + ops_run_postxor(sh, percpu, tx); if (test_bit(STRIPE_OP_CHECK, &ops_request)) - ops_run_check(sh); + ops_run_check(sh, percpu); if (overlap_clear) for (i = disks; i--; ) { @@ -904,6 +917,7 @@ static void raid5_run_ops(struct stripe_head *sh, unsigned long ops_request) if (test_and_clear_bit(R5_Overlap, &dev->flags)) wake_up(&sh->raid_conf->wait_for_overlap); } + put_cpu(); } static int grow_one_stripe(raid5_conf_t *conf) @@ -953,6 +967,28 @@ static int grow_stripes(raid5_conf_t *conf, int num) return 0; } +/** + * scribble_len - return the required size of the scribble region + * @num - total number of disks in the array + * + * The size must be enough to contain: + * 1/ a struct page pointer for each device in the array +2 + * 2/ room to convert each entry in (1) to its corresponding dma + * (dma_map_page()) or page (page_address()) address. + * + * Note: the +2 is for the destination buffers of the ddf/raid6 case where we + * calculate over all devices (not just the data blocks), using zeros in place + * of the P and Q blocks. + */ +static size_t scribble_len(int num) +{ + size_t len; + + len = sizeof(struct page *) * (num+2) + sizeof(addr_conv_t) * (num+2); + + return len; +} + static int resize_stripes(raid5_conf_t *conf, int newsize) { /* Make all the stripes able to hold 'newsize' devices. @@ -981,6 +1017,7 @@ static int resize_stripes(raid5_conf_t *conf, int newsize) struct stripe_head *osh, *nsh; LIST_HEAD(newstripes); struct disk_info *ndisks; + unsigned long cpu; int err; struct kmem_cache *sc; int i; @@ -1046,7 +1083,7 @@ static int resize_stripes(raid5_conf_t *conf, int newsize) /* Step 3. * At this point, we are holding all the stripes so the array * is completely stalled, so now is a good time to resize - * conf->disks. + * conf->disks and the scribble region */ ndisks = kzalloc(newsize * sizeof(struct disk_info), GFP_NOIO); if (ndisks) { @@ -1057,10 +1094,30 @@ static int resize_stripes(raid5_conf_t *conf, int newsize) } else err = -ENOMEM; + get_online_cpus(); + conf->scribble_len = scribble_len(newsize); + for_each_present_cpu(cpu) { + struct raid5_percpu *percpu; + void *scribble; + + percpu = per_cpu_ptr(conf->percpu, cpu); + scribble = kmalloc(conf->scribble_len, GFP_NOIO); + + if (scribble) { + kfree(percpu->scribble); + percpu->scribble = scribble; + } else { + err = -ENOMEM; + break; + } + } + put_online_cpus(); + /* Step 4, return new stripes to service */ while(!list_empty(&newstripes)) { nsh = list_entry(newstripes.next, struct stripe_head, lru); list_del_init(&nsh->lru); + for (i=conf->raid_disks; i < newsize; i++) if (nsh->dev[i].page == NULL) { struct page *p = alloc_page(GFP_NOIO); @@ -4318,6 +4375,7 @@ static void raid5_free_percpu(raid5_conf_t *conf) for_each_possible_cpu(cpu) { percpu = per_cpu_ptr(conf->percpu, cpu); safe_put_page(percpu->spare_page); + kfree(percpu->scribble); } #ifdef CONFIG_HOTPLUG_CPU unregister_cpu_notifier(&conf->cpu_notify); @@ -4347,9 +4405,15 @@ static int raid456_cpu_notify(struct notifier_block *nfb, unsigned long action, switch (action) { case CPU_UP_PREPARE: case CPU_UP_PREPARE_FROZEN: - if (!percpu->spare_page) + if (conf->level == 6 && !percpu->spare_page) percpu->spare_page = alloc_page(GFP_KERNEL); - if (!percpu->spare_page) { + if (!percpu->scribble) + percpu->scribble = kmalloc(conf->scribble_len, GFP_KERNEL); + + if (!percpu->scribble || + (conf->level == 6 && !percpu->spare_page)) { + safe_put_page(percpu->spare_page); + kfree(percpu->scribble); pr_err("%s: failed memory allocation for cpu%ld\n", __func__, cpu); return NOTIFY_BAD; @@ -4358,7 +4422,9 @@ static int raid456_cpu_notify(struct notifier_block *nfb, unsigned long action, case CPU_DEAD: case CPU_DEAD_FROZEN: safe_put_page(percpu->spare_page); + kfree(percpu->scribble); percpu->spare_page = NULL; + percpu->scribble = NULL; break; default: break; @@ -4372,12 +4438,9 @@ static int raid5_alloc_percpu(raid5_conf_t *conf) unsigned long cpu; struct page *spare_page; struct raid5_percpu *allcpus; + void *scribble; int err; - /* the only percpu data is the raid6 spare page */ - if (conf->level != 6) - return 0; - allcpus = alloc_percpu(struct raid5_percpu); if (!allcpus) return -ENOMEM; @@ -4386,12 +4449,20 @@ static int raid5_alloc_percpu(raid5_conf_t *conf) get_online_cpus(); err = 0; for_each_present_cpu(cpu) { - spare_page = alloc_page(GFP_KERNEL); - if (!spare_page) { + if (conf->level == 6) { + spare_page = alloc_page(GFP_KERNEL); + if (!spare_page) { + err = -ENOMEM; + break; + } + per_cpu_ptr(conf->percpu, cpu)->spare_page = spare_page; + } + scribble = kmalloc(scribble_len(conf->raid_disks), GFP_KERNEL); + if (!scribble) { err = -ENOMEM; break; } - per_cpu_ptr(conf->percpu, cpu)->spare_page = spare_page; + per_cpu_ptr(conf->percpu, cpu)->scribble = scribble; } #ifdef CONFIG_HOTPLUG_CPU conf->cpu_notify.notifier_call = raid456_cpu_notify; @@ -4443,6 +4514,7 @@ static raid5_conf_t *setup_conf(mddev_t *mddev) goto abort; conf->raid_disks = mddev->raid_disks; + conf->scribble_len = scribble_len(conf->raid_disks); if (mddev->reshape_position == MaxSector) conf->previous_raid_disks = mddev->raid_disks; else diff --git a/drivers/md/raid5.h b/drivers/md/raid5.h index 07a7a41..e7baabf 100644 --- a/drivers/md/raid5.h +++ b/drivers/md/raid5.h @@ -386,7 +386,15 @@ struct raid5_private_data { /* per cpu variables */ struct raid5_percpu { struct page *spare_page; /* Used when checking P/Q in raid6 */ + void *scribble; /* space for constructing buffer + * lists and performing address + * conversions + */ } *percpu; + size_t scribble_len; /* size of scribble region must be + * associated with conf to handle + * cpu hotplug while reshaping + */ #ifdef CONFIG_HOTPLUG_CPU struct notifier_block cpu_notify; #endif -- cgit v0.10.2 From ad283ea4a3ce82cda2efe33163748a397b31b1eb Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Sat, 29 Aug 2009 19:09:26 -0700 Subject: async_tx: add sum check flags Replace the flat zero_sum_result with a collection of flags to contain the P (xor) zero-sum result, and the soon to be utilized Q (raid6 reed solomon syndrome) zero-sum result. Use the SUM_CHECK_ namespace instead of DMA_ since these flags will be used on non-dma-zero-sum enabled platforms. Reviewed-by: Andre Noll Acked-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/arch/arm/include/asm/hardware/iop3xx-adma.h b/arch/arm/include/asm/hardware/iop3xx-adma.h index 83e6ba3..26eefea 100644 --- a/arch/arm/include/asm/hardware/iop3xx-adma.h +++ b/arch/arm/include/asm/hardware/iop3xx-adma.h @@ -756,13 +756,14 @@ static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, hw_desc->src[0] = val; } -static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) +static inline enum sum_check_flags +iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) { struct iop3xx_desc_aau *hw_desc = desc->hw_desc; struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; iop_paranoia(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en)); - return desc_ctrl.zero_result_err; + return desc_ctrl.zero_result_err << SUM_CHECK_P; } static inline void iop_chan_append(struct iop_adma_chan *chan) diff --git a/arch/arm/mach-iop13xx/include/mach/adma.h b/arch/arm/mach-iop13xx/include/mach/adma.h index 5722e86..1cd31df8 100644 --- a/arch/arm/mach-iop13xx/include/mach/adma.h +++ b/arch/arm/mach-iop13xx/include/mach/adma.h @@ -428,18 +428,20 @@ static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, hw_desc->block_fill_data = val; } -static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) +static inline enum sum_check_flags +iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) { struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field; + enum sum_check_flags flags; BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result)); - if (desc_ctrl.pq_xfer_en) - return byte_count.zero_result_err_q; - else - return byte_count.zero_result_err; + flags = byte_count.zero_result_err_q << SUM_CHECK_Q; + flags |= byte_count.zero_result_err << SUM_CHECK_P; + + return flags; } static inline void iop_chan_append(struct iop_adma_chan *chan) diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index 1e96c4d..78fb778 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c @@ -246,7 +246,7 @@ static int page_is_zero(struct page *p, unsigned int offset, size_t len) */ struct dma_async_tx_descriptor * async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, - int src_cnt, size_t len, u32 *result, + int src_cnt, size_t len, enum sum_check_flags *result, struct async_submit_ctl *submit) { struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR_VAL, @@ -304,7 +304,7 @@ async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, async_tx_quiesce(&tx); - *result = page_is_zero(dest, offset, len) ? 0 : 1; + *result = !page_is_zero(dest, offset, len) << SUM_CHECK_P; async_tx_sync_epilog(submit); submit->flags = flags_orig; diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 7727954..1f2a266 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -2590,7 +2590,7 @@ static void handle_parity_checks5(raid5_conf_t *conf, struct stripe_head *sh, * we are done. Otherwise update the mismatch count and repair * parity if !MD_RECOVERY_CHECK */ - if (sh->ops.zero_sum_result == 0) + if ((sh->ops.zero_sum_result & SUM_CHECK_P_RESULT) == 0) /* parity is correct (on disc, * not in buffer any more) */ diff --git a/drivers/md/raid5.h b/drivers/md/raid5.h index e7baabf..75f2c6c 100644 --- a/drivers/md/raid5.h +++ b/drivers/md/raid5.h @@ -2,6 +2,7 @@ #define _RAID5_H #include +#include /* * @@ -215,8 +216,8 @@ struct stripe_head { * @target - STRIPE_OP_COMPUTE_BLK target */ struct stripe_operations { - int target; - u32 zero_sum_result; + int target; + enum sum_check_flags zero_sum_result; } ops; struct r5dev { struct bio req; diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index 00cfb63..3d21a25 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h @@ -148,7 +148,7 @@ async_xor(struct page *dest, struct page **src_list, unsigned int offset, struct dma_async_tx_descriptor * async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, - int src_cnt, size_t len, u32 *result, + int src_cnt, size_t len, enum sum_check_flags *result, struct async_submit_ctl *submit); struct dma_async_tx_descriptor * diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 6768727..02447af 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -87,6 +87,25 @@ enum dma_ctrl_flags { }; /** + * enum sum_check_bits - bit position of pq_check_flags + */ +enum sum_check_bits { + SUM_CHECK_P = 0, + SUM_CHECK_Q = 1, +}; + +/** + * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations + * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise + * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise + */ +enum sum_check_flags { + SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), + SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), +}; + + +/** * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. * See linux/cpumask.h */ @@ -245,7 +264,7 @@ struct dma_device { unsigned int src_cnt, size_t len, unsigned long flags); struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, - size_t len, u32 *result, unsigned long flags); + size_t len, enum sum_check_flags *result, unsigned long flags); struct dma_async_tx_descriptor *(*device_prep_dma_memset)( struct dma_chan *chan, dma_addr_t dest, int value, size_t len, unsigned long flags); -- cgit v0.10.2 From af1f951eb6ef27b01cbfb3f6c21b770af4368a6d Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Sat, 29 Aug 2009 19:09:26 -0700 Subject: async_tx: kill needless module_{init|exit} If module_init and module_exit are nops then neither need to be defined. [ Impact: pure cleanup ] Reviewed-by: Andre Noll Acked-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/crypto/async_tx/async_memcpy.c b/crypto/async_tx/async_memcpy.c index 89e0555..98e15bd 100644 --- a/crypto/async_tx/async_memcpy.c +++ b/crypto/async_tx/async_memcpy.c @@ -90,19 +90,6 @@ async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset, } EXPORT_SYMBOL_GPL(async_memcpy); -static int __init async_memcpy_init(void) -{ - return 0; -} - -static void __exit async_memcpy_exit(void) -{ - do { } while (0); -} - -module_init(async_memcpy_init); -module_exit(async_memcpy_exit); - MODULE_AUTHOR("Intel Corporation"); MODULE_DESCRIPTION("asynchronous memcpy api"); MODULE_LICENSE("GPL"); diff --git a/crypto/async_tx/async_memset.c b/crypto/async_tx/async_memset.c index c144372..b896a6e5 100644 --- a/crypto/async_tx/async_memset.c +++ b/crypto/async_tx/async_memset.c @@ -80,19 +80,6 @@ async_memset(struct page *dest, int val, unsigned int offset, size_t len, } EXPORT_SYMBOL_GPL(async_memset); -static int __init async_memset_init(void) -{ - return 0; -} - -static void __exit async_memset_exit(void) -{ - do { } while (0); -} - -module_init(async_memset_init); -module_exit(async_memset_exit); - MODULE_AUTHOR("Intel Corporation"); MODULE_DESCRIPTION("asynchronous memset api"); MODULE_LICENSE("GPL"); diff --git a/crypto/async_tx/async_tx.c b/crypto/async_tx/async_tx.c index 802a5ce4..6e37ad3 100644 --- a/crypto/async_tx/async_tx.c +++ b/crypto/async_tx/async_tx.c @@ -42,6 +42,9 @@ static void __exit async_tx_exit(void) async_dmaengine_put(); } +module_init(async_tx_init); +module_exit(async_tx_exit); + /** * __async_tx_find_channel - find a channel to carry out the operation or let * the transaction execute synchronously @@ -61,17 +64,6 @@ __async_tx_find_channel(struct async_submit_ctl *submit, return async_dma_find_channel(tx_type); } EXPORT_SYMBOL_GPL(__async_tx_find_channel); -#else -static int __init async_tx_init(void) -{ - printk(KERN_INFO "async_tx: api initialized (sync-only)\n"); - return 0; -} - -static void __exit async_tx_exit(void) -{ - do { } while (0); -} #endif @@ -298,9 +290,6 @@ void async_tx_quiesce(struct dma_async_tx_descriptor **tx) } EXPORT_SYMBOL_GPL(async_tx_quiesce); -module_init(async_tx_init); -module_exit(async_tx_exit); - MODULE_AUTHOR("Intel Corporation"); MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API"); MODULE_LICENSE("GPL"); -- cgit v0.10.2 From 95475e57113c66aac7583925736ed2e2d58c990d Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 14 Jul 2009 12:19:02 -0700 Subject: async_tx: remove walk of tx->parent chain in dma_wait_for_async_tx We currently walk the parent chain when waiting for a given tx to complete however this walk may race with the driver cleanup routine. The routines in async_raid6_recov.c may fall back to the synchronous path at any point so we need to be prepared to call async_tx_quiesce() (which calls dma_wait_for_async_tx). To remove the ->parent walk we guarantee that every time a dependency is attached ->issue_pending() is invoked, then we can simply poll the initial descriptor until completion. This also allows for a lighter weight 'issue pending' implementation as there is no longer a requirement to iterate through all the channels' ->issue_pending() routines as long as operations have been submitted in an ordered chain. async_tx_issue_pending() is added for this case. Signed-off-by: Dan Williams diff --git a/crypto/async_tx/async_tx.c b/crypto/async_tx/async_tx.c index 6e37ad3..60615fe 100644 --- a/crypto/async_tx/async_tx.c +++ b/crypto/async_tx/async_tx.c @@ -77,8 +77,8 @@ static void async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx, struct dma_async_tx_descriptor *tx) { - struct dma_chan *chan; - struct dma_device *device; + struct dma_chan *chan = depend_tx->chan; + struct dma_device *device = chan->device; struct dma_async_tx_descriptor *intr_tx = (void *) ~0; /* first check to see if we can still append to depend_tx */ @@ -90,11 +90,11 @@ async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx, } spin_unlock_bh(&depend_tx->lock); - if (!intr_tx) + /* attached dependency, flush the parent channel */ + if (!intr_tx) { + device->device_issue_pending(chan); return; - - chan = depend_tx->chan; - device = chan->device; + } /* see if we can schedule an interrupt * otherwise poll for completion @@ -128,6 +128,7 @@ async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx, intr_tx->tx_submit(intr_tx); async_tx_ack(intr_tx); } + device->device_issue_pending(chan); } else { if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR) panic("%s: DMA_ERROR waiting for depend_tx\n", diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 6781e8f..e002e0e 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -934,49 +934,24 @@ EXPORT_SYMBOL(dma_async_tx_descriptor_init); /* dma_wait_for_async_tx - spin wait for a transaction to complete * @tx: in-flight transaction to wait on - * - * This routine assumes that tx was obtained from a call to async_memcpy, - * async_xor, async_memset, etc which ensures that tx is "in-flight" (prepped - * and submitted). Walking the parent chain is only meant to cover for DMA - * drivers that do not implement the DMA_INTERRUPT capability and may race with - * the driver's descriptor cleanup routine. */ enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) { - enum dma_status status; - struct dma_async_tx_descriptor *iter; - struct dma_async_tx_descriptor *parent; + unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000); if (!tx) return DMA_SUCCESS; - WARN_ONCE(tx->parent, "%s: speculatively walking dependency chain for" - " %s\n", __func__, dma_chan_name(tx->chan)); - - /* poll through the dependency chain, return when tx is complete */ - do { - iter = tx; - - /* find the root of the unsubmitted dependency chain */ - do { - parent = iter->parent; - if (!parent) - break; - else - iter = parent; - } while (parent); - - /* there is a small window for ->parent == NULL and - * ->cookie == -EBUSY - */ - while (iter->cookie == -EBUSY) - cpu_relax(); - - status = dma_sync_wait(iter->chan, iter->cookie); - } while (status == DMA_IN_PROGRESS || (iter != tx)); - - return status; + while (tx->cookie == -EBUSY) { + if (time_after_eq(jiffies, dma_sync_wait_timeout)) { + pr_err("%s timeout waiting for descriptor submission\n", + __func__); + return DMA_ERROR; + } + cpu_relax(); + } + return dma_sync_wait(tx->chan, tx->cookie); } EXPORT_SYMBOL_GPL(dma_wait_for_async_tx); diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index 3d21a25..12a2efc 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h @@ -83,6 +83,24 @@ struct async_submit_ctl { #ifdef CONFIG_DMA_ENGINE #define async_tx_issue_pending_all dma_issue_pending_all + +/** + * async_tx_issue_pending - send pending descriptor to the hardware channel + * @tx: descriptor handle to retrieve hardware context + * + * Note: any dependent operations will have already been issued by + * async_tx_channel_switch, or (in the case of no channel switch) will + * be already pending on this channel. + */ +static inline void async_tx_issue_pending(struct dma_async_tx_descriptor *tx) +{ + if (likely(tx)) { + struct dma_chan *chan = tx->chan; + struct dma_device *dma = chan->device; + + dma->device_issue_pending(chan); + } +} #ifdef CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL #include #else @@ -98,6 +116,11 @@ static inline void async_tx_issue_pending_all(void) do { } while (0); } +static inline void async_tx_issue_pending(struct dma_async_tx_descriptor *tx) +{ + do { } while (0); +} + static inline struct dma_chan * async_tx_find_channel(struct async_submit_ctl *submit, enum dma_transaction_type tx_type, struct page **dst, -- cgit v0.10.2 From b2f46fd8ef3dff2ab30f31126833f78b7480283a Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 14 Jul 2009 12:20:36 -0700 Subject: async_tx: add support for asynchronous GF multiplication [ Based on an original patch by Yuri Tikhonov ] This adds support for doing asynchronous GF multiplication by adding two additional functions to the async_tx API: async_gen_syndrome() does simultaneous XOR and Galois field multiplication of sources. async_syndrome_val() validates the given source buffers against known P and Q values. When a request is made to run async_pq against more than the hardware maximum number of supported sources we need to reuse the previous generated P and Q values as sources into the next operation. Care must be taken to remove Q from P' and P from Q'. For example to perform a 5 source pq op with hardware that only supports 4 sources at a time the following approach is taken: p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08})) p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10})) p' = p + q + q + src4 = p + src4 q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4 Note: 4 is the minimum acceptable maxpq otherwise we punt to synchronous-software path. The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as sources (in the above manner) and fill the remaining slots up to maxpq with the new sources/coefficients. Note1: Some devices have native support for P+Q continuation and can skip this extra work. Devices with this capability can advertise it with dma_set_maxpq. It is up to each driver how to handle the DMA_PREP_CONTINUE flag. Note2: The api supports disabling the generation of P when generating Q, this is ignored by the synchronous path but is implemented by some dma devices to save unnecessary writes. In this case the continuation algorithm is simplified to only reuse Q as a source. Cc: H. Peter Anvin Cc: David Woodhouse Signed-off-by: Yuri Tikhonov Signed-off-by: Ilya Yanok Reviewed-by: Andre Noll Acked-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/Documentation/crypto/async-tx-api.txt b/Documentation/crypto/async-tx-api.txt index 6b15e48..0e48e054 100644 --- a/Documentation/crypto/async-tx-api.txt +++ b/Documentation/crypto/async-tx-api.txt @@ -64,6 +64,9 @@ xor - xor a series of source buffers and write the result to a xor_val - xor a series of source buffers and set a flag if the result is zero. The implementation attempts to prevent writes to memory +pq - generate the p+q (raid6 syndrome) from a series of source buffers +pq_val - validate that a p and or q buffer are in sync with a given series of + sources 3.3 Descriptor management: The return value is non-NULL and points to a 'descriptor' when the operation diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c index 9800228..2e7ca0d 100644 --- a/arch/arm/mach-iop13xx/setup.c +++ b/arch/arm/mach-iop13xx/setup.c @@ -506,7 +506,7 @@ void __init iop13xx_platform_init(void) dma_cap_set(DMA_MEMSET, plat_data->cap_mask); dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); - dma_cap_set(DMA_PQ_XOR, plat_data->cap_mask); + dma_cap_set(DMA_PQ, plat_data->cap_mask); dma_cap_set(DMA_PQ_UPDATE, plat_data->cap_mask); dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask); break; diff --git a/crypto/async_tx/Kconfig b/crypto/async_tx/Kconfig index d8fb3914..cb6d731 100644 --- a/crypto/async_tx/Kconfig +++ b/crypto/async_tx/Kconfig @@ -14,3 +14,7 @@ config ASYNC_MEMSET tristate select ASYNC_CORE +config ASYNC_PQ + tristate + select ASYNC_CORE + diff --git a/crypto/async_tx/Makefile b/crypto/async_tx/Makefile index 27baa7d..1b99265 100644 --- a/crypto/async_tx/Makefile +++ b/crypto/async_tx/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_ASYNC_CORE) += async_tx.o obj-$(CONFIG_ASYNC_MEMCPY) += async_memcpy.o obj-$(CONFIG_ASYNC_MEMSET) += async_memset.o obj-$(CONFIG_ASYNC_XOR) += async_xor.o +obj-$(CONFIG_ASYNC_PQ) += async_pq.o diff --git a/crypto/async_tx/async_pq.c b/crypto/async_tx/async_pq.c new file mode 100644 index 0000000..108b21e --- /dev/null +++ b/crypto/async_tx/async_pq.c @@ -0,0 +1,388 @@ +/* + * Copyright(c) 2007 Yuri Tikhonov + * Copyright(c) 2009 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * The full GNU General Public License is included in this distribution in the + * file called COPYING. + */ +#include +#include +#include +#include +#include + +/** + * scribble - space to hold throwaway P buffer for synchronous gen_syndrome + */ +static struct page *scribble; + +static bool is_raid6_zero_block(struct page *p) +{ + return p == (void *) raid6_empty_zero_page; +} + +/* the struct page *blocks[] parameter passed to async_gen_syndrome() + * and async_syndrome_val() contains the 'P' destination address at + * blocks[disks-2] and the 'Q' destination address at blocks[disks-1] + * + * note: these are macros as they are used as lvalues + */ +#define P(b, d) (b[d-2]) +#define Q(b, d) (b[d-1]) + +/** + * do_async_gen_syndrome - asynchronously calculate P and/or Q + */ +static __async_inline struct dma_async_tx_descriptor * +do_async_gen_syndrome(struct dma_chan *chan, struct page **blocks, + const unsigned char *scfs, unsigned int offset, int disks, + size_t len, dma_addr_t *dma_src, + struct async_submit_ctl *submit) +{ + struct dma_async_tx_descriptor *tx = NULL; + struct dma_device *dma = chan->device; + enum dma_ctrl_flags dma_flags = 0; + enum async_tx_flags flags_orig = submit->flags; + dma_async_tx_callback cb_fn_orig = submit->cb_fn; + dma_async_tx_callback cb_param_orig = submit->cb_param; + int src_cnt = disks - 2; + unsigned char coefs[src_cnt]; + unsigned short pq_src_cnt; + dma_addr_t dma_dest[2]; + int src_off = 0; + int idx; + int i; + + /* DMAs use destinations as sources, so use BIDIRECTIONAL mapping */ + if (P(blocks, disks)) + dma_dest[0] = dma_map_page(dma->dev, P(blocks, disks), offset, + len, DMA_BIDIRECTIONAL); + else + dma_flags |= DMA_PREP_PQ_DISABLE_P; + if (Q(blocks, disks)) + dma_dest[1] = dma_map_page(dma->dev, Q(blocks, disks), offset, + len, DMA_BIDIRECTIONAL); + else + dma_flags |= DMA_PREP_PQ_DISABLE_Q; + + /* convert source addresses being careful to collapse 'empty' + * sources and update the coefficients accordingly + */ + for (i = 0, idx = 0; i < src_cnt; i++) { + if (is_raid6_zero_block(blocks[i])) + continue; + dma_src[idx] = dma_map_page(dma->dev, blocks[i], offset, len, + DMA_TO_DEVICE); + coefs[idx] = scfs[i]; + idx++; + } + src_cnt = idx; + + while (src_cnt > 0) { + submit->flags = flags_orig; + pq_src_cnt = min(src_cnt, dma_maxpq(dma, dma_flags)); + /* if we are submitting additional pqs, leave the chain open, + * clear the callback parameters, and leave the destination + * buffers mapped + */ + if (src_cnt > pq_src_cnt) { + submit->flags &= ~ASYNC_TX_ACK; + dma_flags |= DMA_COMPL_SKIP_DEST_UNMAP; + submit->cb_fn = NULL; + submit->cb_param = NULL; + } else { + dma_flags &= ~DMA_COMPL_SKIP_DEST_UNMAP; + submit->cb_fn = cb_fn_orig; + submit->cb_param = cb_param_orig; + if (cb_fn_orig) + dma_flags |= DMA_PREP_INTERRUPT; + } + + /* Since we have clobbered the src_list we are committed + * to doing this asynchronously. Drivers force forward + * progress in case they can not provide a descriptor + */ + for (;;) { + tx = dma->device_prep_dma_pq(chan, dma_dest, + &dma_src[src_off], + pq_src_cnt, + &coefs[src_off], len, + dma_flags); + if (likely(tx)) + break; + async_tx_quiesce(&submit->depend_tx); + dma_async_issue_pending(chan); + } + + async_tx_submit(chan, tx, submit); + submit->depend_tx = tx; + + /* drop completed sources */ + src_cnt -= pq_src_cnt; + src_off += pq_src_cnt; + + dma_flags |= DMA_PREP_CONTINUE; + } + + return tx; +} + +/** + * do_sync_gen_syndrome - synchronously calculate a raid6 syndrome + */ +static void +do_sync_gen_syndrome(struct page **blocks, unsigned int offset, int disks, + size_t len, struct async_submit_ctl *submit) +{ + void **srcs; + int i; + + if (submit->scribble) + srcs = submit->scribble; + else + srcs = (void **) blocks; + + for (i = 0; i < disks; i++) { + if (is_raid6_zero_block(blocks[i])) { + BUG_ON(i > disks - 3); /* P or Q can't be zero */ + srcs[i] = blocks[i]; + } else + srcs[i] = page_address(blocks[i]) + offset; + } + raid6_call.gen_syndrome(disks, len, srcs); + async_tx_sync_epilog(submit); +} + +/** + * async_gen_syndrome - asynchronously calculate a raid6 syndrome + * @blocks: source blocks from idx 0..disks-3, P @ disks-2 and Q @ disks-1 + * @offset: common offset into each block (src and dest) to start transaction + * @disks: number of blocks (including missing P or Q, see below) + * @len: length of operation in bytes + * @submit: submission/completion modifiers + * + * General note: This routine assumes a field of GF(2^8) with a + * primitive polynomial of 0x11d and a generator of {02}. + * + * 'disks' note: callers can optionally omit either P or Q (but not + * both) from the calculation by setting blocks[disks-2] or + * blocks[disks-1] to NULL. When P or Q is omitted 'len' must be <= + * PAGE_SIZE as a temporary buffer of this size is used in the + * synchronous path. 'disks' always accounts for both destination + * buffers. + * + * 'blocks' note: if submit->scribble is NULL then the contents of + * 'blocks' may be overridden + */ +struct dma_async_tx_descriptor * +async_gen_syndrome(struct page **blocks, unsigned int offset, int disks, + size_t len, struct async_submit_ctl *submit) +{ + int src_cnt = disks - 2; + struct dma_chan *chan = async_tx_find_channel(submit, DMA_PQ, + &P(blocks, disks), 2, + blocks, src_cnt, len); + struct dma_device *device = chan ? chan->device : NULL; + dma_addr_t *dma_src = NULL; + + BUG_ON(disks > 255 || !(P(blocks, disks) || Q(blocks, disks))); + + if (submit->scribble) + dma_src = submit->scribble; + else if (sizeof(dma_addr_t) <= sizeof(struct page *)) + dma_src = (dma_addr_t *) blocks; + + if (dma_src && device && + (src_cnt <= dma_maxpq(device, 0) || + dma_maxpq(device, DMA_PREP_CONTINUE) > 0)) { + /* run the p+q asynchronously */ + pr_debug("%s: (async) disks: %d len: %zu\n", + __func__, disks, len); + return do_async_gen_syndrome(chan, blocks, raid6_gfexp, offset, + disks, len, dma_src, submit); + } + + /* run the pq synchronously */ + pr_debug("%s: (sync) disks: %d len: %zu\n", __func__, disks, len); + + /* wait for any prerequisite operations */ + async_tx_quiesce(&submit->depend_tx); + + if (!P(blocks, disks)) { + P(blocks, disks) = scribble; + BUG_ON(len + offset > PAGE_SIZE); + } + if (!Q(blocks, disks)) { + Q(blocks, disks) = scribble; + BUG_ON(len + offset > PAGE_SIZE); + } + do_sync_gen_syndrome(blocks, offset, disks, len, submit); + + return NULL; +} +EXPORT_SYMBOL_GPL(async_gen_syndrome); + +/** + * async_syndrome_val - asynchronously validate a raid6 syndrome + * @blocks: source blocks from idx 0..disks-3, P @ disks-2 and Q @ disks-1 + * @offset: common offset into each block (src and dest) to start transaction + * @disks: number of blocks (including missing P or Q, see below) + * @len: length of operation in bytes + * @pqres: on val failure SUM_CHECK_P_RESULT and/or SUM_CHECK_Q_RESULT are set + * @spare: temporary result buffer for the synchronous case + * @submit: submission / completion modifiers + * + * The same notes from async_gen_syndrome apply to the 'blocks', + * and 'disks' parameters of this routine. The synchronous path + * requires a temporary result buffer and submit->scribble to be + * specified. + */ +struct dma_async_tx_descriptor * +async_syndrome_val(struct page **blocks, unsigned int offset, int disks, + size_t len, enum sum_check_flags *pqres, struct page *spare, + struct async_submit_ctl *submit) +{ + struct dma_chan *chan = async_tx_find_channel(submit, DMA_PQ_VAL, + NULL, 0, blocks, disks, + len); + struct dma_device *device = chan ? chan->device : NULL; + struct dma_async_tx_descriptor *tx; + enum dma_ctrl_flags dma_flags = submit->cb_fn ? DMA_PREP_INTERRUPT : 0; + dma_addr_t *dma_src = NULL; + + BUG_ON(disks < 4); + + if (submit->scribble) + dma_src = submit->scribble; + else if (sizeof(dma_addr_t) <= sizeof(struct page *)) + dma_src = (dma_addr_t *) blocks; + + if (dma_src && device && disks <= dma_maxpq(device, 0)) { + struct device *dev = device->dev; + dma_addr_t *pq = &dma_src[disks-2]; + int i; + + pr_debug("%s: (async) disks: %d len: %zu\n", + __func__, disks, len); + if (!P(blocks, disks)) + dma_flags |= DMA_PREP_PQ_DISABLE_P; + if (!Q(blocks, disks)) + dma_flags |= DMA_PREP_PQ_DISABLE_Q; + for (i = 0; i < disks; i++) + if (likely(blocks[i])) { + BUG_ON(is_raid6_zero_block(blocks[i])); + dma_src[i] = dma_map_page(dev, blocks[i], + offset, len, + DMA_TO_DEVICE); + } + + for (;;) { + tx = device->device_prep_dma_pq_val(chan, pq, dma_src, + disks - 2, + raid6_gfexp, + len, pqres, + dma_flags); + if (likely(tx)) + break; + async_tx_quiesce(&submit->depend_tx); + dma_async_issue_pending(chan); + } + async_tx_submit(chan, tx, submit); + + return tx; + } else { + struct page *p_src = P(blocks, disks); + struct page *q_src = Q(blocks, disks); + enum async_tx_flags flags_orig = submit->flags; + dma_async_tx_callback cb_fn_orig = submit->cb_fn; + void *scribble = submit->scribble; + void *cb_param_orig = submit->cb_param; + void *p, *q, *s; + + pr_debug("%s: (sync) disks: %d len: %zu\n", + __func__, disks, len); + + /* caller must provide a temporary result buffer and + * allow the input parameters to be preserved + */ + BUG_ON(!spare || !scribble); + + /* wait for any prerequisite operations */ + async_tx_quiesce(&submit->depend_tx); + + /* recompute p and/or q into the temporary buffer and then + * check to see the result matches the current value + */ + tx = NULL; + *pqres = 0; + if (p_src) { + init_async_submit(submit, ASYNC_TX_XOR_ZERO_DST, NULL, + NULL, NULL, scribble); + tx = async_xor(spare, blocks, offset, disks-2, len, submit); + async_tx_quiesce(&tx); + p = page_address(p_src) + offset; + s = page_address(spare) + offset; + *pqres |= !!memcmp(p, s, len) << SUM_CHECK_P; + } + + if (q_src) { + P(blocks, disks) = NULL; + Q(blocks, disks) = spare; + init_async_submit(submit, 0, NULL, NULL, NULL, scribble); + tx = async_gen_syndrome(blocks, offset, disks, len, submit); + async_tx_quiesce(&tx); + q = page_address(q_src) + offset; + s = page_address(spare) + offset; + *pqres |= !!memcmp(q, s, len) << SUM_CHECK_Q; + } + + /* restore P, Q and submit */ + P(blocks, disks) = p_src; + Q(blocks, disks) = q_src; + + submit->cb_fn = cb_fn_orig; + submit->cb_param = cb_param_orig; + submit->flags = flags_orig; + async_tx_sync_epilog(submit); + + return NULL; + } +} +EXPORT_SYMBOL_GPL(async_syndrome_val); + +static int __init async_pq_init(void) +{ + scribble = alloc_page(GFP_KERNEL); + + if (scribble) + return 0; + + pr_err("%s: failed to allocate required spare page\n", __func__); + + return -ENOMEM; +} + +static void __exit async_pq_exit(void) +{ + put_page(scribble); +} + +module_init(async_pq_init); +module_exit(async_pq_exit); + +MODULE_DESCRIPTION("asynchronous raid6 syndrome generation/validation"); +MODULE_LICENSE("GPL"); diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index 78fb778..56b5f98 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c @@ -62,7 +62,7 @@ do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, while (src_cnt) { submit->flags = flags_orig; dma_flags = 0; - xor_src_cnt = min(src_cnt, dma->max_xor); + xor_src_cnt = min(src_cnt, (int)dma->max_xor); /* if we are submitting additional xors, leave the chain open, * clear the callback parameters, and leave the destination * buffer mapped diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index e002e0e..cd5673d 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -646,6 +646,10 @@ int dma_async_device_register(struct dma_device *device) !device->device_prep_dma_xor); BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) && !device->device_prep_dma_xor_val); + BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) && + !device->device_prep_dma_pq); + BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) && + !device->device_prep_dma_pq_val); BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) && !device->device_prep_dma_memset); BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) && diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index 6ff79a6..4496bc6 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c @@ -1257,7 +1257,7 @@ static int __devinit iop_adma_probe(struct platform_device *pdev) dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: " "( %s%s%s%s%s%s%s%s%s%s)\n", - dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "", + dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "", dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "", dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "", dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index 12a2efc..e6ce5f0 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h @@ -185,5 +185,14 @@ async_memset(struct page *dest, int val, unsigned int offset, struct dma_async_tx_descriptor *async_trigger_callback(struct async_submit_ctl *submit); +struct dma_async_tx_descriptor * +async_gen_syndrome(struct page **blocks, unsigned int offset, int src_cnt, + size_t len, struct async_submit_ctl *submit); + +struct dma_async_tx_descriptor * +async_syndrome_val(struct page **blocks, unsigned int offset, int src_cnt, + size_t len, enum sum_check_flags *pqres, struct page *spare, + struct async_submit_ctl *submit); + void async_tx_quiesce(struct dma_async_tx_descriptor **tx); #endif /* _ASYNC_TX_H_ */ diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 02447af..ce010cd9 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -52,7 +52,7 @@ enum dma_status { enum dma_transaction_type { DMA_MEMCPY, DMA_XOR, - DMA_PQ_XOR, + DMA_PQ, DMA_DUAL_XOR, DMA_PQ_UPDATE, DMA_XOR_VAL, @@ -70,20 +70,28 @@ enum dma_transaction_type { /** * enum dma_ctrl_flags - DMA flags to augment operation preparation, - * control completion, and communicate status. + * control completion, and communicate status. * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of - * this transaction + * this transaction * @DMA_CTRL_ACK - the descriptor cannot be reused until the client - * acknowledges receipt, i.e. has has a chance to establish any - * dependency chains + * acknowledges receipt, i.e. has has a chance to establish any dependency + * chains * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) + * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q + * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P + * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as + * sources that were the result of a previous operation, in the case of a PQ + * operation it continues the calculation with new sources */ enum dma_ctrl_flags { DMA_PREP_INTERRUPT = (1 << 0), DMA_CTRL_ACK = (1 << 1), DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), + DMA_PREP_PQ_DISABLE_P = (1 << 4), + DMA_PREP_PQ_DISABLE_Q = (1 << 5), + DMA_PREP_CONTINUE = (1 << 6), }; /** @@ -226,6 +234,7 @@ struct dma_async_tx_descriptor { * @global_node: list_head for global dma_device_list * @cap_mask: one or more dma_capability flags * @max_xor: maximum number of xor sources, 0 if no capability + * @max_pq: maximum number of PQ sources and PQ-continue capability * @dev_id: unique device ID * @dev: struct device reference for dma mapping api * @device_alloc_chan_resources: allocate resources and return the @@ -234,6 +243,8 @@ struct dma_async_tx_descriptor { * @device_prep_dma_memcpy: prepares a memcpy operation * @device_prep_dma_xor: prepares a xor operation * @device_prep_dma_xor_val: prepares a xor validation operation + * @device_prep_dma_pq: prepares a pq operation + * @device_prep_dma_pq_val: prepares a pqzero_sum operation * @device_prep_dma_memset: prepares a memset operation * @device_prep_dma_interrupt: prepares an end of chain interrupt operation * @device_prep_slave_sg: prepares a slave dma operation @@ -248,7 +259,9 @@ struct dma_device { struct list_head channels; struct list_head global_node; dma_cap_mask_t cap_mask; - int max_xor; + unsigned short max_xor; + unsigned short max_pq; + #define DMA_HAS_PQ_CONTINUE (1 << 15) int dev_id; struct device *dev; @@ -265,6 +278,14 @@ struct dma_device { struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, size_t len, enum sum_check_flags *result, unsigned long flags); + struct dma_async_tx_descriptor *(*device_prep_dma_pq)( + struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, + unsigned int src_cnt, const unsigned char *scf, + size_t len, unsigned long flags); + struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( + struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, + unsigned int src_cnt, const unsigned char *scf, size_t len, + enum sum_check_flags *pqres, unsigned long flags); struct dma_async_tx_descriptor *(*device_prep_dma_memset)( struct dma_chan *chan, dma_addr_t dest, int value, size_t len, unsigned long flags); @@ -283,6 +304,60 @@ struct dma_device { void (*device_issue_pending)(struct dma_chan *chan); }; +static inline void +dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) +{ + dma->max_pq = maxpq; + if (has_pq_continue) + dma->max_pq |= DMA_HAS_PQ_CONTINUE; +} + +static inline bool dmaf_continue(enum dma_ctrl_flags flags) +{ + return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; +} + +static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) +{ + enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; + + return (flags & mask) == mask; +} + +static inline bool dma_dev_has_pq_continue(struct dma_device *dma) +{ + return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; +} + +static unsigned short dma_dev_to_maxpq(struct dma_device *dma) +{ + return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; +} + +/* dma_maxpq - reduce maxpq in the face of continued operations + * @dma - dma device with PQ capability + * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set + * + * When an engine does not support native continuation we need 3 extra + * source slots to reuse P and Q with the following coefficients: + * 1/ {00} * P : remove P from Q', but use it as a source for P' + * 2/ {01} * Q : use Q to continue Q' calculation + * 3/ {00} * Q : subtract Q from P' to cancel (2) + * + * In the case where P is disabled we only need 1 extra source: + * 1/ {01} * Q : use Q to continue Q' calculation + */ +static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) +{ + if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) + return dma_dev_to_maxpq(dma); + else if (dmaf_p_disabled_continue(flags)) + return dma_dev_to_maxpq(dma) - 1; + else if (dmaf_continue(flags)) + return dma_dev_to_maxpq(dma) - 3; + BUG(); +} + /* --- public DMA engine API --- */ #ifdef CONFIG_DMA_ENGINE -- cgit v0.10.2 From 0a82a6239beecc95db6e05fe43ee62d16b381d38 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 14 Jul 2009 12:20:37 -0700 Subject: async_tx: add support for asynchronous RAID6 recovery operations async_raid6_2data_recov() recovers two data disk failures async_raid6_datap_recov() recovers a data disk and the P disk These routines are a port of the synchronous versions found in drivers/md/raid6recov.c. The primary difference is breaking out the xor operations into separate calls to async_xor. Two helper routines are introduced to perform scalar multiplication where needed. async_sum_product() multiplies two sources by scalar coefficients and then sums (xor) the result. async_mult() simply multiplies a single source by a scalar. This implemention also includes, in contrast to the original synchronous-only code, special case handling for the 4-disk and 5-disk array cases. In these situations the default N-disk algorithm will present 0-source or 1-source operations to dma devices. To cover for dma devices where the minimum source count is 2 we implement 4-disk and 5-disk handling in the recovery code. [ Impact: asynchronous raid6 recovery routines for 2data and datap cases ] Cc: Yuri Tikhonov Cc: Ilya Yanok Cc: H. Peter Anvin Cc: David Woodhouse Reviewed-by: Andre Noll Acked-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/Documentation/crypto/async-tx-api.txt b/Documentation/crypto/async-tx-api.txt index 0e48e054..ba046b8 100644 --- a/Documentation/crypto/async-tx-api.txt +++ b/Documentation/crypto/async-tx-api.txt @@ -67,6 +67,10 @@ xor_val - xor a series of source buffers and set a flag if the pq - generate the p+q (raid6 syndrome) from a series of source buffers pq_val - validate that a p and or q buffer are in sync with a given series of sources +datap - (raid6_datap_recov) recover a raid6 data block and the p block + from the given sources +2data - (raid6_2data_recov) recover 2 raid6 data blocks from the given + sources 3.3 Descriptor management: The return value is non-NULL and points to a 'descriptor' when the operation diff --git a/crypto/async_tx/Kconfig b/crypto/async_tx/Kconfig index cb6d731..e5aeb2b 100644 --- a/crypto/async_tx/Kconfig +++ b/crypto/async_tx/Kconfig @@ -18,3 +18,8 @@ config ASYNC_PQ tristate select ASYNC_CORE +config ASYNC_RAID6_RECOV + tristate + select ASYNC_CORE + select ASYNC_PQ + diff --git a/crypto/async_tx/Makefile b/crypto/async_tx/Makefile index 1b99265..9a1a768 100644 --- a/crypto/async_tx/Makefile +++ b/crypto/async_tx/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_ASYNC_MEMCPY) += async_memcpy.o obj-$(CONFIG_ASYNC_MEMSET) += async_memset.o obj-$(CONFIG_ASYNC_XOR) += async_xor.o obj-$(CONFIG_ASYNC_PQ) += async_pq.o +obj-$(CONFIG_ASYNC_RAID6_RECOV) += async_raid6_recov.o diff --git a/crypto/async_tx/async_raid6_recov.c b/crypto/async_tx/async_raid6_recov.c new file mode 100644 index 0000000..0c14d48 --- /dev/null +++ b/crypto/async_tx/async_raid6_recov.c @@ -0,0 +1,448 @@ +/* + * Asynchronous RAID-6 recovery calculations ASYNC_TX API. + * Copyright(c) 2009 Intel Corporation + * + * based on raid6recov.c: + * Copyright 2002 H. Peter Anvin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 51 + * Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#include +#include +#include +#include +#include + +static struct dma_async_tx_descriptor * +async_sum_product(struct page *dest, struct page **srcs, unsigned char *coef, + size_t len, struct async_submit_ctl *submit) +{ + struct dma_chan *chan = async_tx_find_channel(submit, DMA_PQ, + &dest, 1, srcs, 2, len); + struct dma_device *dma = chan ? chan->device : NULL; + const u8 *amul, *bmul; + u8 ax, bx; + u8 *a, *b, *c; + + if (dma) { + dma_addr_t dma_dest[2]; + dma_addr_t dma_src[2]; + struct device *dev = dma->dev; + struct dma_async_tx_descriptor *tx; + enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P; + + dma_dest[1] = dma_map_page(dev, dest, 0, len, DMA_BIDIRECTIONAL); + dma_src[0] = dma_map_page(dev, srcs[0], 0, len, DMA_TO_DEVICE); + dma_src[1] = dma_map_page(dev, srcs[1], 0, len, DMA_TO_DEVICE); + tx = dma->device_prep_dma_pq(chan, dma_dest, dma_src, 2, coef, + len, dma_flags); + if (tx) { + async_tx_submit(chan, tx, submit); + return tx; + } + } + + /* run the operation synchronously */ + async_tx_quiesce(&submit->depend_tx); + amul = raid6_gfmul[coef[0]]; + bmul = raid6_gfmul[coef[1]]; + a = page_address(srcs[0]); + b = page_address(srcs[1]); + c = page_address(dest); + + while (len--) { + ax = amul[*a++]; + bx = bmul[*b++]; + *c++ = ax ^ bx; + } + + return NULL; +} + +static struct dma_async_tx_descriptor * +async_mult(struct page *dest, struct page *src, u8 coef, size_t len, + struct async_submit_ctl *submit) +{ + struct dma_chan *chan = async_tx_find_channel(submit, DMA_PQ, + &dest, 1, &src, 1, len); + struct dma_device *dma = chan ? chan->device : NULL; + const u8 *qmul; /* Q multiplier table */ + u8 *d, *s; + + if (dma) { + dma_addr_t dma_dest[2]; + dma_addr_t dma_src[1]; + struct device *dev = dma->dev; + struct dma_async_tx_descriptor *tx; + enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P; + + dma_dest[1] = dma_map_page(dev, dest, 0, len, DMA_BIDIRECTIONAL); + dma_src[0] = dma_map_page(dev, src, 0, len, DMA_TO_DEVICE); + tx = dma->device_prep_dma_pq(chan, dma_dest, dma_src, 1, &coef, + len, dma_flags); + if (tx) { + async_tx_submit(chan, tx, submit); + return tx; + } + } + + /* no channel available, or failed to allocate a descriptor, so + * perform the operation synchronously + */ + async_tx_quiesce(&submit->depend_tx); + qmul = raid6_gfmul[coef]; + d = page_address(dest); + s = page_address(src); + + while (len--) + *d++ = qmul[*s++]; + + return NULL; +} + +static struct dma_async_tx_descriptor * +__2data_recov_4(size_t bytes, int faila, int failb, struct page **blocks, + struct async_submit_ctl *submit) +{ + struct dma_async_tx_descriptor *tx = NULL; + struct page *p, *q, *a, *b; + struct page *srcs[2]; + unsigned char coef[2]; + enum async_tx_flags flags = submit->flags; + dma_async_tx_callback cb_fn = submit->cb_fn; + void *cb_param = submit->cb_param; + void *scribble = submit->scribble; + + p = blocks[4-2]; + q = blocks[4-1]; + + a = blocks[faila]; + b = blocks[failb]; + + /* in the 4 disk case P + Pxy == P and Q + Qxy == Q */ + /* Dx = A*(P+Pxy) + B*(Q+Qxy) */ + srcs[0] = p; + srcs[1] = q; + coef[0] = raid6_gfexi[failb-faila]; + coef[1] = raid6_gfinv[raid6_gfexp[faila]^raid6_gfexp[failb]]; + init_async_submit(submit, 0, tx, NULL, NULL, scribble); + tx = async_sum_product(b, srcs, coef, bytes, submit); + + /* Dy = P+Pxy+Dx */ + srcs[0] = p; + srcs[1] = b; + init_async_submit(submit, flags | ASYNC_TX_XOR_ZERO_DST, tx, cb_fn, + cb_param, scribble); + tx = async_xor(a, srcs, 0, 2, bytes, submit); + + return tx; + +} + +static struct dma_async_tx_descriptor * +__2data_recov_5(size_t bytes, int faila, int failb, struct page **blocks, + struct async_submit_ctl *submit) +{ + struct dma_async_tx_descriptor *tx = NULL; + struct page *p, *q, *g, *dp, *dq; + struct page *srcs[2]; + unsigned char coef[2]; + enum async_tx_flags flags = submit->flags; + dma_async_tx_callback cb_fn = submit->cb_fn; + void *cb_param = submit->cb_param; + void *scribble = submit->scribble; + int uninitialized_var(good); + int i; + + for (i = 0; i < 3; i++) { + if (i == faila || i == failb) + continue; + else { + good = i; + break; + } + } + BUG_ON(i >= 3); + + p = blocks[5-2]; + q = blocks[5-1]; + g = blocks[good]; + + /* Compute syndrome with zero for the missing data pages + * Use the dead data pages as temporary storage for delta p and + * delta q + */ + dp = blocks[faila]; + dq = blocks[failb]; + + init_async_submit(submit, 0, tx, NULL, NULL, scribble); + tx = async_memcpy(dp, g, 0, 0, bytes, submit); + init_async_submit(submit, 0, tx, NULL, NULL, scribble); + tx = async_mult(dq, g, raid6_gfexp[good], bytes, submit); + + /* compute P + Pxy */ + srcs[0] = dp; + srcs[1] = p; + init_async_submit(submit, ASYNC_TX_XOR_DROP_DST, tx, NULL, NULL, + scribble); + tx = async_xor(dp, srcs, 0, 2, bytes, submit); + + /* compute Q + Qxy */ + srcs[0] = dq; + srcs[1] = q; + init_async_submit(submit, ASYNC_TX_XOR_DROP_DST, tx, NULL, NULL, + scribble); + tx = async_xor(dq, srcs, 0, 2, bytes, submit); + + /* Dx = A*(P+Pxy) + B*(Q+Qxy) */ + srcs[0] = dp; + srcs[1] = dq; + coef[0] = raid6_gfexi[failb-faila]; + coef[1] = raid6_gfinv[raid6_gfexp[faila]^raid6_gfexp[failb]]; + init_async_submit(submit, 0, tx, NULL, NULL, scribble); + tx = async_sum_product(dq, srcs, coef, bytes, submit); + + /* Dy = P+Pxy+Dx */ + srcs[0] = dp; + srcs[1] = dq; + init_async_submit(submit, flags | ASYNC_TX_XOR_DROP_DST, tx, cb_fn, + cb_param, scribble); + tx = async_xor(dp, srcs, 0, 2, bytes, submit); + + return tx; +} + +static struct dma_async_tx_descriptor * +__2data_recov_n(int disks, size_t bytes, int faila, int failb, + struct page **blocks, struct async_submit_ctl *submit) +{ + struct dma_async_tx_descriptor *tx = NULL; + struct page *p, *q, *dp, *dq; + struct page *srcs[2]; + unsigned char coef[2]; + enum async_tx_flags flags = submit->flags; + dma_async_tx_callback cb_fn = submit->cb_fn; + void *cb_param = submit->cb_param; + void *scribble = submit->scribble; + + p = blocks[disks-2]; + q = blocks[disks-1]; + + /* Compute syndrome with zero for the missing data pages + * Use the dead data pages as temporary storage for + * delta p and delta q + */ + dp = blocks[faila]; + blocks[faila] = (void *)raid6_empty_zero_page; + blocks[disks-2] = dp; + dq = blocks[failb]; + blocks[failb] = (void *)raid6_empty_zero_page; + blocks[disks-1] = dq; + + init_async_submit(submit, 0, tx, NULL, NULL, scribble); + tx = async_gen_syndrome(blocks, 0, disks, bytes, submit); + + /* Restore pointer table */ + blocks[faila] = dp; + blocks[failb] = dq; + blocks[disks-2] = p; + blocks[disks-1] = q; + + /* compute P + Pxy */ + srcs[0] = dp; + srcs[1] = p; + init_async_submit(submit, ASYNC_TX_XOR_DROP_DST, tx, NULL, NULL, + scribble); + tx = async_xor(dp, srcs, 0, 2, bytes, submit); + + /* compute Q + Qxy */ + srcs[0] = dq; + srcs[1] = q; + init_async_submit(submit, ASYNC_TX_XOR_DROP_DST, tx, NULL, NULL, + scribble); + tx = async_xor(dq, srcs, 0, 2, bytes, submit); + + /* Dx = A*(P+Pxy) + B*(Q+Qxy) */ + srcs[0] = dp; + srcs[1] = dq; + coef[0] = raid6_gfexi[failb-faila]; + coef[1] = raid6_gfinv[raid6_gfexp[faila]^raid6_gfexp[failb]]; + init_async_submit(submit, 0, tx, NULL, NULL, scribble); + tx = async_sum_product(dq, srcs, coef, bytes, submit); + + /* Dy = P+Pxy+Dx */ + srcs[0] = dp; + srcs[1] = dq; + init_async_submit(submit, flags | ASYNC_TX_XOR_DROP_DST, tx, cb_fn, + cb_param, scribble); + tx = async_xor(dp, srcs, 0, 2, bytes, submit); + + return tx; +} + +/** + * async_raid6_2data_recov - asynchronously calculate two missing data blocks + * @disks: number of disks in the RAID-6 array + * @bytes: block size + * @faila: first failed drive index + * @failb: second failed drive index + * @blocks: array of source pointers where the last two entries are p and q + * @submit: submission/completion modifiers + */ +struct dma_async_tx_descriptor * +async_raid6_2data_recov(int disks, size_t bytes, int faila, int failb, + struct page **blocks, struct async_submit_ctl *submit) +{ + BUG_ON(faila == failb); + if (failb < faila) + swap(faila, failb); + + pr_debug("%s: disks: %d len: %zu\n", __func__, disks, bytes); + + /* we need to preserve the contents of 'blocks' for the async + * case, so punt to synchronous if a scribble buffer is not available + */ + if (!submit->scribble) { + void **ptrs = (void **) blocks; + int i; + + async_tx_quiesce(&submit->depend_tx); + for (i = 0; i < disks; i++) + ptrs[i] = page_address(blocks[i]); + + raid6_2data_recov(disks, bytes, faila, failb, ptrs); + + async_tx_sync_epilog(submit); + + return NULL; + } + + switch (disks) { + case 4: + /* dma devices do not uniformly understand a zero source pq + * operation (in contrast to the synchronous case), so + * explicitly handle the 4 disk special case + */ + return __2data_recov_4(bytes, faila, failb, blocks, submit); + case 5: + /* dma devices do not uniformly understand a single + * source pq operation (in contrast to the synchronous + * case), so explicitly handle the 5 disk special case + */ + return __2data_recov_5(bytes, faila, failb, blocks, submit); + default: + return __2data_recov_n(disks, bytes, faila, failb, blocks, submit); + } +} +EXPORT_SYMBOL_GPL(async_raid6_2data_recov); + +/** + * async_raid6_datap_recov - asynchronously calculate a data and the 'p' block + * @disks: number of disks in the RAID-6 array + * @bytes: block size + * @faila: failed drive index + * @blocks: array of source pointers where the last two entries are p and q + * @submit: submission/completion modifiers + */ +struct dma_async_tx_descriptor * +async_raid6_datap_recov(int disks, size_t bytes, int faila, + struct page **blocks, struct async_submit_ctl *submit) +{ + struct dma_async_tx_descriptor *tx = NULL; + struct page *p, *q, *dq; + u8 coef; + enum async_tx_flags flags = submit->flags; + dma_async_tx_callback cb_fn = submit->cb_fn; + void *cb_param = submit->cb_param; + void *scribble = submit->scribble; + struct page *srcs[2]; + + pr_debug("%s: disks: %d len: %zu\n", __func__, disks, bytes); + + /* we need to preserve the contents of 'blocks' for the async + * case, so punt to synchronous if a scribble buffer is not available + */ + if (!scribble) { + void **ptrs = (void **) blocks; + int i; + + async_tx_quiesce(&submit->depend_tx); + for (i = 0; i < disks; i++) + ptrs[i] = page_address(blocks[i]); + + raid6_datap_recov(disks, bytes, faila, ptrs); + + async_tx_sync_epilog(submit); + + return NULL; + } + + p = blocks[disks-2]; + q = blocks[disks-1]; + + /* Compute syndrome with zero for the missing data page + * Use the dead data page as temporary storage for delta q + */ + dq = blocks[faila]; + blocks[faila] = (void *)raid6_empty_zero_page; + blocks[disks-1] = dq; + + /* in the 4 disk case we only need to perform a single source + * multiplication + */ + if (disks == 4) { + int good = faila == 0 ? 1 : 0; + struct page *g = blocks[good]; + + init_async_submit(submit, 0, tx, NULL, NULL, scribble); + tx = async_memcpy(p, g, 0, 0, bytes, submit); + + init_async_submit(submit, 0, tx, NULL, NULL, scribble); + tx = async_mult(dq, g, raid6_gfexp[good], bytes, submit); + } else { + init_async_submit(submit, 0, tx, NULL, NULL, scribble); + tx = async_gen_syndrome(blocks, 0, disks, bytes, submit); + } + + /* Restore pointer table */ + blocks[faila] = dq; + blocks[disks-1] = q; + + /* calculate g^{-faila} */ + coef = raid6_gfinv[raid6_gfexp[faila]]; + + srcs[0] = dq; + srcs[1] = q; + init_async_submit(submit, ASYNC_TX_XOR_DROP_DST, tx, NULL, NULL, + scribble); + tx = async_xor(dq, srcs, 0, 2, bytes, submit); + + init_async_submit(submit, 0, tx, NULL, NULL, scribble); + tx = async_mult(dq, dq, coef, bytes, submit); + + srcs[0] = p; + srcs[1] = dq; + init_async_submit(submit, flags | ASYNC_TX_XOR_DROP_DST, tx, cb_fn, + cb_param, scribble); + tx = async_xor(p, srcs, 0, 2, bytes, submit); + + return tx; +} +EXPORT_SYMBOL_GPL(async_raid6_datap_recov); + +MODULE_AUTHOR("Dan Williams "); +MODULE_DESCRIPTION("asynchronous RAID-6 recovery api"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index e6ce5f0..866e61c 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h @@ -194,5 +194,13 @@ async_syndrome_val(struct page **blocks, unsigned int offset, int src_cnt, size_t len, enum sum_check_flags *pqres, struct page *spare, struct async_submit_ctl *submit); +struct dma_async_tx_descriptor * +async_raid6_2data_recov(int src_num, size_t bytes, int faila, int failb, + struct page **ptrs, struct async_submit_ctl *submit); + +struct dma_async_tx_descriptor * +async_raid6_datap_recov(int src_num, size_t bytes, int faila, + struct page **ptrs, struct async_submit_ctl *submit); + void async_tx_quiesce(struct dma_async_tx_descriptor **tx); #endif /* _ASYNC_TX_H_ */ -- cgit v0.10.2 From 58691d64c44ae41ddf098ecb31e9a994026e3cff Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Sat, 29 Aug 2009 19:09:27 -0700 Subject: dmatest: add pq support Test raid6 p+q operations with a simple "always multiply by 1" q calculation to fit into dmatest's current destination verification scheme. Reviewed-by: Andre Noll Acked-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c index a27c0fb..a5ee541 100644 --- a/drivers/dma/dmatest.c +++ b/drivers/dma/dmatest.c @@ -43,6 +43,11 @@ module_param(xor_sources, uint, S_IRUGO); MODULE_PARM_DESC(xor_sources, "Number of xor source buffers (default: 3)"); +static unsigned int pq_sources = 3; +module_param(pq_sources, uint, S_IRUGO); +MODULE_PARM_DESC(pq_sources, + "Number of p+q source buffers (default: 3)"); + /* * Initialization patterns. All bytes in the source buffer has bit 7 * set, all bytes in the destination buffer has bit 7 cleared. @@ -227,6 +232,7 @@ static int dmatest_func(void *data) dma_cookie_t cookie; enum dma_status status; enum dma_ctrl_flags flags; + u8 pq_coefs[pq_sources]; int ret; int src_cnt; int dst_cnt; @@ -243,6 +249,11 @@ static int dmatest_func(void *data) else if (thread->type == DMA_XOR) { src_cnt = xor_sources | 1; /* force odd to ensure dst = src */ dst_cnt = 1; + } else if (thread->type == DMA_PQ) { + src_cnt = pq_sources | 1; /* force odd to ensure dst = src */ + dst_cnt = 2; + for (i = 0; i < pq_sources; i++) + pq_coefs[i] = 1; } else goto err_srcs; @@ -310,6 +321,15 @@ static int dmatest_func(void *data) dma_dsts[0] + dst_off, dma_srcs, xor_sources, len, flags); + else if (thread->type == DMA_PQ) { + dma_addr_t dma_pq[dst_cnt]; + + for (i = 0; i < dst_cnt; i++) + dma_pq[i] = dma_dsts[i] + dst_off; + tx = dev->device_prep_dma_pq(chan, dma_pq, dma_srcs, + pq_sources, pq_coefs, + len, flags); + } if (!tx) { for (i = 0; i < src_cnt; i++) @@ -446,6 +466,8 @@ static int dmatest_add_threads(struct dmatest_chan *dtc, enum dma_transaction_ty op = "copy"; else if (type == DMA_XOR) op = "xor"; + else if (type == DMA_PQ) + op = "pq"; else return -EINVAL; @@ -501,6 +523,10 @@ static int dmatest_add_channel(struct dma_chan *chan) cnt = dmatest_add_threads(dtc, DMA_XOR); thread_count += cnt > 0 ?: 0; } + if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { + cnt = dmatest_add_threads(dtc, DMA_PQ); + thread_count += cnt > 0 ?: 0; + } pr_info("dmatest: Started %u threads using %s\n", thread_count, dma_chan_name(chan)); -- cgit v0.10.2 From cb3c82992f62f838e6476a0bff12909158007fc6 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 14 Jul 2009 12:20:37 -0700 Subject: async_tx: raid6 recovery self test Port drivers/md/raid6test/test.c to use the async raid6 recovery routines. This is meant as a unit test for raid6 acceleration drivers. In addition to the 16-drive test case this implements tests for the 4-disk and 5-disk special cases (dma devices can not generically handle less than 2 sources), and adds a test for the D+Q case. Reviewed-by: Andre Noll Acked-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/crypto/async_tx/Makefile b/crypto/async_tx/Makefile index 9a1a768..d1e0e6f 100644 --- a/crypto/async_tx/Makefile +++ b/crypto/async_tx/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_ASYNC_MEMSET) += async_memset.o obj-$(CONFIG_ASYNC_XOR) += async_xor.o obj-$(CONFIG_ASYNC_PQ) += async_pq.o obj-$(CONFIG_ASYNC_RAID6_RECOV) += async_raid6_recov.o +obj-$(CONFIG_ASYNC_RAID6_TEST) += raid6test.o diff --git a/crypto/async_tx/raid6test.c b/crypto/async_tx/raid6test.c new file mode 100644 index 0000000..98c83ca --- /dev/null +++ b/crypto/async_tx/raid6test.c @@ -0,0 +1,241 @@ +/* + * asynchronous raid6 recovery self test + * Copyright (c) 2009, Intel Corporation. + * + * based on drivers/md/raid6test/test.c: + * Copyright 2002-2007 H. Peter Anvin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#include +#include + +#undef pr +#define pr(fmt, args...) pr_info("raid6test: " fmt, ##args) + +#define NDISKS 16 /* Including P and Q */ + +static struct page *dataptrs[NDISKS]; +static struct page *data[NDISKS+3]; +static struct page *spare; +static struct page *recovi; +static struct page *recovj; + +static void callback(void *param) +{ + struct completion *cmp = param; + + complete(cmp); +} + +static void makedata(int disks) +{ + int i, j; + + for (i = 0; i < disks; i++) { + for (j = 0; j < PAGE_SIZE/sizeof(u32); j += sizeof(u32)) { + u32 *p = page_address(data[i]) + j; + + *p = random32(); + } + + dataptrs[i] = data[i]; + } +} + +static char disk_type(int d, int disks) +{ + if (d == disks - 2) + return 'P'; + else if (d == disks - 1) + return 'Q'; + else + return 'D'; +} + +/* Recover two failed blocks. */ +static void raid6_dual_recov(int disks, size_t bytes, int faila, int failb, struct page **ptrs) +{ + struct async_submit_ctl submit; + addr_conv_t addr_conv[disks]; + struct completion cmp; + struct dma_async_tx_descriptor *tx = NULL; + enum sum_check_flags result = ~0; + + if (faila > failb) + swap(faila, failb); + + if (failb == disks-1) { + if (faila == disks-2) { + /* P+Q failure. Just rebuild the syndrome. */ + init_async_submit(&submit, 0, NULL, NULL, NULL, addr_conv); + tx = async_gen_syndrome(ptrs, 0, disks, bytes, &submit); + } else { + struct page *blocks[disks]; + struct page *dest; + int count = 0; + int i; + + /* data+Q failure. Reconstruct data from P, + * then rebuild syndrome + */ + for (i = disks; i-- ; ) { + if (i == faila || i == failb) + continue; + blocks[count++] = ptrs[i]; + } + dest = ptrs[faila]; + init_async_submit(&submit, ASYNC_TX_XOR_ZERO_DST, NULL, + NULL, NULL, addr_conv); + tx = async_xor(dest, blocks, 0, count, bytes, &submit); + + init_async_submit(&submit, 0, tx, NULL, NULL, addr_conv); + tx = async_gen_syndrome(ptrs, 0, disks, bytes, &submit); + } + } else { + if (failb == disks-2) { + /* data+P failure. */ + init_async_submit(&submit, 0, NULL, NULL, NULL, addr_conv); + tx = async_raid6_datap_recov(disks, bytes, faila, ptrs, &submit); + } else { + /* data+data failure. */ + init_async_submit(&submit, 0, NULL, NULL, NULL, addr_conv); + tx = async_raid6_2data_recov(disks, bytes, faila, failb, ptrs, &submit); + } + } + init_completion(&cmp); + init_async_submit(&submit, ASYNC_TX_ACK, tx, callback, &cmp, addr_conv); + tx = async_syndrome_val(ptrs, 0, disks, bytes, &result, spare, &submit); + async_tx_issue_pending(tx); + + if (wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)) == 0) + pr("%s: timeout! (faila: %d failb: %d disks: %d)\n", + __func__, faila, failb, disks); + + if (result != 0) + pr("%s: validation failure! faila: %d failb: %d sum_check_flags: %x\n", + __func__, faila, failb, result); +} + +static int test_disks(int i, int j, int disks) +{ + int erra, errb; + + memset(page_address(recovi), 0xf0, PAGE_SIZE); + memset(page_address(recovj), 0xba, PAGE_SIZE); + + dataptrs[i] = recovi; + dataptrs[j] = recovj; + + raid6_dual_recov(disks, PAGE_SIZE, i, j, dataptrs); + + erra = memcmp(page_address(data[i]), page_address(recovi), PAGE_SIZE); + errb = memcmp(page_address(data[j]), page_address(recovj), PAGE_SIZE); + + pr("%s(%d, %d): faila=%3d(%c) failb=%3d(%c) %s\n", + __func__, i, j, i, disk_type(i, disks), j, disk_type(j, disks), + (!erra && !errb) ? "OK" : !erra ? "ERRB" : !errb ? "ERRA" : "ERRAB"); + + dataptrs[i] = data[i]; + dataptrs[j] = data[j]; + + return erra || errb; +} + +static int test(int disks, int *tests) +{ + addr_conv_t addr_conv[disks]; + struct dma_async_tx_descriptor *tx; + struct async_submit_ctl submit; + struct completion cmp; + int err = 0; + int i, j; + + recovi = data[disks]; + recovj = data[disks+1]; + spare = data[disks+2]; + + makedata(disks); + + /* Nuke syndromes */ + memset(page_address(data[disks-2]), 0xee, PAGE_SIZE); + memset(page_address(data[disks-1]), 0xee, PAGE_SIZE); + + /* Generate assumed good syndrome */ + init_completion(&cmp); + init_async_submit(&submit, ASYNC_TX_ACK, NULL, callback, &cmp, addr_conv); + tx = async_gen_syndrome(dataptrs, 0, disks, PAGE_SIZE, &submit); + async_tx_issue_pending(tx); + + if (wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)) == 0) { + pr("error: initial gen_syndrome(%d) timed out\n", disks); + return 1; + } + + pr("testing the %d-disk case...\n", disks); + for (i = 0; i < disks-1; i++) + for (j = i+1; j < disks; j++) { + (*tests)++; + err += test_disks(i, j, disks); + } + + return err; +} + + +static int raid6_test(void) +{ + int err = 0; + int tests = 0; + int i; + + for (i = 0; i < NDISKS+3; i++) { + data[i] = alloc_page(GFP_KERNEL); + if (!data[i]) { + while (i--) + put_page(data[i]); + return -ENOMEM; + } + } + + /* the 4-disk and 5-disk cases are special for the recovery code */ + if (NDISKS > 4) + err += test(4, &tests); + if (NDISKS > 5) + err += test(5, &tests); + err += test(NDISKS, &tests); + + pr("\n"); + pr("complete (%d tests, %d failure%s)\n", + tests, err, err == 1 ? "" : "s"); + + for (i = 0; i < NDISKS+3; i++) + put_page(data[i]); + + return 0; +} + +static void raid6_test_exit(void) +{ +} + +/* when compiled-in wait for drivers to load first (assumes dma drivers + * are also compliled-in) + */ +late_initcall(raid6_test); +module_exit(raid6_test_exit); +MODULE_AUTHOR("Dan Williams "); +MODULE_DESCRIPTION("asynchronous RAID-6 recovery self tests"); +MODULE_LICENSE("GPL"); diff --git a/drivers/md/Kconfig b/drivers/md/Kconfig index 36e0675..41b3ae2 100644 --- a/drivers/md/Kconfig +++ b/drivers/md/Kconfig @@ -155,6 +155,19 @@ config MD_RAID456 config MD_RAID6_PQ tristate +config ASYNC_RAID6_TEST + tristate "Self test for hardware accelerated raid6 recovery" + depends on MD_RAID6_PQ + select ASYNC_RAID6_RECOV + ---help--- + This is a one-shot self test that permutes through the + recovery of all the possible two disk failure scenarios for a + N-disk array. Recovery is performed with the asynchronous + raid6 recovery routines, and will optionally use an offload + engine if one is available. + + If unsure, say N. + config MD_MULTIPATH tristate "Multipath I/O support" depends on BLK_DEV_MD -- cgit v0.10.2 From 507fbec4cff442ebce6706db34603bfb9cc3b5a9 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Sat, 29 Aug 2009 19:12:39 -0700 Subject: iop-adma: cleanup iop_adma_run_tx_complete_actions Replace 'desc->async_tx.' with 'tx->' [ Impact: pure cleanup ] Signed-off-by: Dan Williams diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index 4496bc6..ce45f3f 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c @@ -61,17 +61,18 @@ static dma_cookie_t iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc, struct iop_adma_chan *iop_chan, dma_cookie_t cookie) { - BUG_ON(desc->async_tx.cookie < 0); - if (desc->async_tx.cookie > 0) { - cookie = desc->async_tx.cookie; - desc->async_tx.cookie = 0; + struct dma_async_tx_descriptor *tx = &desc->async_tx; + + BUG_ON(tx->cookie < 0); + if (tx->cookie > 0) { + cookie = tx->cookie; + tx->cookie = 0; /* call the callback (must not sleep or submit new * operations to this channel) */ - if (desc->async_tx.callback) - desc->async_tx.callback( - desc->async_tx.callback_param); + if (tx->callback) + tx->callback(tx->callback_param); /* unmap dma addresses * (unmap_single vs unmap_page?) @@ -81,7 +82,7 @@ iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc, struct device *dev = &iop_chan->device->pdev->dev; u32 len = unmap->unmap_len; - enum dma_ctrl_flags flags = desc->async_tx.flags; + enum dma_ctrl_flags flags = tx->flags; u32 src_cnt; dma_addr_t addr; dma_addr_t dest; @@ -115,7 +116,7 @@ iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc, } /* run dependent operations */ - dma_run_dependencies(&desc->async_tx); + dma_run_dependencies(tx); return cookie; } -- cgit v0.10.2 From 72be12f0c39df46832403cbfd82e132a883f5ddc Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 14 Jul 2009 13:38:29 -0700 Subject: iop-adma: fix lockdep false positive lockdep correctly identifies a potential recursive locking case for iop_chan->lock, but in the dependency submission case we expect that the same class will be acquired for both the parent dependency and the child channel. Signed-off-by: Dan Williams diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index ce45f3f..9c752bd 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c @@ -288,7 +288,12 @@ static void iop_adma_tasklet(unsigned long data) { struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data; - spin_lock(&iop_chan->lock); + /* lockdep will flag depedency submissions as potentially + * recursive locking, this is not the case as a dependency + * submission will never recurse a channels submit routine. + * There are checks in async_tx.c to prevent this. + */ + spin_lock_nested(&iop_chan->lock, SINGLE_DEPTH_NESTING); __iop_adma_slot_cleanup(iop_chan); spin_unlock(&iop_chan->lock); } -- cgit v0.10.2 From 7bf649aee8ac93ecc280f8745dcf8ec19d7b9fb1 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Fri, 28 Aug 2009 14:32:04 -0700 Subject: iop-adma: P+Q support for iop13xx adma engines iop33x support is not included because that engine is a bit more awkward to handle in that it can either be in xor mode or pq mode. The dmaengine/async_tx layers currently only comprehend static capabilities. Note iop13xx does not support hardware PQ continuation so the driver must handle the DMA_PREP_CONTINUE flag for operations across > 16 sources. From the comment for dma_maxpq: /* When an engine does not support native continuation we need 3 extra * source slots to reuse P and Q with the following coefficients: * 1/ {00} * P : remove P from Q', but use it as a source for P' * 2/ {01} * Q : use Q to continue Q' calculation * 3/ {00} * Q : subtract Q from P' to cancel (2) */ Signed-off-by: Dan Williams diff --git a/arch/arm/include/asm/hardware/iop3xx-adma.h b/arch/arm/include/asm/hardware/iop3xx-adma.h index 26eefea..1a8c727 100644 --- a/arch/arm/include/asm/hardware/iop3xx-adma.h +++ b/arch/arm/include/asm/hardware/iop3xx-adma.h @@ -187,11 +187,74 @@ union iop3xx_desc { void *ptr; }; +/* No support for p+q operations */ +static inline int +iop_chan_pq_slot_count(size_t len, int src_cnt, int *slots_per_op) +{ + BUG(); + return 0; +} + +static inline void +iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + BUG(); +} + +static inline void +iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr) +{ + BUG(); +} + +static inline void +iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx, + dma_addr_t addr, unsigned char coef) +{ + BUG(); +} + +static inline int +iop_chan_pq_zero_sum_slot_count(size_t len, int src_cnt, int *slots_per_op) +{ + BUG(); + return 0; +} + +static inline void +iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + BUG(); +} + +static inline void +iop_desc_set_pq_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) +{ + BUG(); +} + +#define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr + +static inline void +iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx, + dma_addr_t *src) +{ + BUG(); +} + static inline int iop_adma_get_max_xor(void) { return 32; } +static inline int iop_adma_get_max_pq(void) +{ + BUG(); + return 0; +} + static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) { int id = chan->device->id; @@ -332,6 +395,11 @@ static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt, return slot_cnt; } +static inline int iop_desc_is_pq(struct iop_adma_desc_slot *desc) +{ + return 0; +} + static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, struct iop_adma_chan *chan) { @@ -349,6 +417,14 @@ static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, return 0; } + +static inline u32 iop_desc_get_qdest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + BUG(); + return 0; +} + static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, struct iop_adma_chan *chan) { diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h index 385c6e8..bbe8a04 100644 --- a/arch/arm/include/asm/hardware/iop_adma.h +++ b/arch/arm/include/asm/hardware/iop_adma.h @@ -106,6 +106,7 @@ struct iop_adma_desc_slot { union { u32 *xor_check_result; u32 *crc32_result; + u32 *pq_check_result; }; }; diff --git a/arch/arm/mach-iop13xx/include/mach/adma.h b/arch/arm/mach-iop13xx/include/mach/adma.h index 1cd31df8..6d3782d 100644 --- a/arch/arm/mach-iop13xx/include/mach/adma.h +++ b/arch/arm/mach-iop13xx/include/mach/adma.h @@ -150,6 +150,8 @@ static inline int iop_adma_get_max_xor(void) return 16; } +#define iop_adma_get_max_pq iop_adma_get_max_xor + static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) { return __raw_readl(ADMA_ADAR(chan)); @@ -211,7 +213,10 @@ iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op) #define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT #define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT #define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT +#define IOP_ADMA_PQ_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT #define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o) +#define iop_chan_pq_slot_count iop_chan_xor_slot_count +#define iop_chan_pq_zero_sum_slot_count iop_chan_xor_slot_count static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, struct iop_adma_chan *chan) @@ -220,6 +225,13 @@ static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, return hw_desc->dest_addr; } +static inline u32 iop_desc_get_qdest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->q_dest_addr; +} + static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, struct iop_adma_chan *chan) { @@ -319,6 +331,58 @@ iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, return 1; } +static inline void +iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.src_select = src_cnt - 1; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.pq_xfer_en = 1; + u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P); + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + hw_desc->desc_ctrl = u_desc_ctrl.value; +} + +static inline int iop_desc_is_pq(struct iop_adma_desc_slot *desc) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = hw_desc->desc_ctrl; + return u_desc_ctrl.field.pq_xfer_en; +} + +static inline void +iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.src_select = src_cnt - 1; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.zero_result = 1; + u_desc_ctrl.field.status_write_back_en = 1; + u_desc_ctrl.field.pq_xfer_en = 1; + u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P); + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; + hw_desc->desc_ctrl = u_desc_ctrl.value; +} + static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, struct iop_adma_chan *chan, u32 byte_count) @@ -351,6 +415,7 @@ iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) } } +#define iop_desc_set_pq_zero_sum_byte_count iop_desc_set_zero_sum_byte_count static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, struct iop_adma_chan *chan, @@ -361,6 +426,16 @@ static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, hw_desc->upper_dest_addr = 0; } +static inline void +iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + + hw_desc->dest_addr = addr[0]; + hw_desc->q_dest_addr = addr[1]; + hw_desc->upper_dest_addr = 0; +} + static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, dma_addr_t addr) { @@ -389,6 +464,29 @@ static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, } static inline void +iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx, + dma_addr_t addr, unsigned char coef) +{ + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; + struct iop13xx_adma_src *src; + int i = 0; + + do { + iter = iop_hw_desc_slot_idx(hw_desc, i); + src = &iter->src[src_idx]; + src->src_addr = addr; + src->pq_upper_src_addr = 0; + src->pq_dmlt = coef; + slot_cnt -= slots_per_op; + if (slot_cnt) { + i += slots_per_op; + addr += IOP_ADMA_PQ_MAX_BYTE_COUNT; + } + } while (slot_cnt); +} + +static inline void iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, struct iop_adma_chan *chan) { @@ -399,6 +497,15 @@ iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, } #define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr +#define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr + +static inline void +iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx, + dma_addr_t *src) +{ + iop_desc_set_xor_src_addr(desc, pq_idx, src[pq_idx]); + iop_desc_set_xor_src_addr(desc, pq_idx+1, src[pq_idx+1]); +} static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, u32 next_desc_addr) diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index 9c752bd..5a0f4fe 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c @@ -57,6 +57,80 @@ static void iop_adma_free_slots(struct iop_adma_desc_slot *slot) } } +static void +iop_desc_unmap(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc) +{ + struct dma_async_tx_descriptor *tx = &desc->async_tx; + struct iop_adma_desc_slot *unmap = desc->group_head; + struct device *dev = &iop_chan->device->pdev->dev; + u32 len = unmap->unmap_len; + enum dma_ctrl_flags flags = tx->flags; + u32 src_cnt; + dma_addr_t addr; + dma_addr_t dest; + + src_cnt = unmap->unmap_src_cnt; + dest = iop_desc_get_dest_addr(unmap, iop_chan); + if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { + enum dma_data_direction dir; + + if (src_cnt > 1) /* is xor? */ + dir = DMA_BIDIRECTIONAL; + else + dir = DMA_FROM_DEVICE; + + dma_unmap_page(dev, dest, len, dir); + } + + if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { + while (src_cnt--) { + addr = iop_desc_get_src_addr(unmap, iop_chan, src_cnt); + if (addr == dest) + continue; + dma_unmap_page(dev, addr, len, DMA_TO_DEVICE); + } + } + desc->group_head = NULL; +} + +static void +iop_desc_unmap_pq(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc) +{ + struct dma_async_tx_descriptor *tx = &desc->async_tx; + struct iop_adma_desc_slot *unmap = desc->group_head; + struct device *dev = &iop_chan->device->pdev->dev; + u32 len = unmap->unmap_len; + enum dma_ctrl_flags flags = tx->flags; + u32 src_cnt = unmap->unmap_src_cnt; + dma_addr_t pdest = iop_desc_get_dest_addr(unmap, iop_chan); + dma_addr_t qdest = iop_desc_get_qdest_addr(unmap, iop_chan); + int i; + + if (tx->flags & DMA_PREP_CONTINUE) + src_cnt -= 3; + + if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP) && !desc->pq_check_result) { + dma_unmap_page(dev, pdest, len, DMA_BIDIRECTIONAL); + dma_unmap_page(dev, qdest, len, DMA_BIDIRECTIONAL); + } + + if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { + dma_addr_t addr; + + for (i = 0; i < src_cnt; i++) { + addr = iop_desc_get_src_addr(unmap, iop_chan, i); + dma_unmap_page(dev, addr, len, DMA_TO_DEVICE); + } + if (desc->pq_check_result) { + dma_unmap_page(dev, pdest, len, DMA_TO_DEVICE); + dma_unmap_page(dev, qdest, len, DMA_TO_DEVICE); + } + } + + desc->group_head = NULL; +} + + static dma_cookie_t iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc, struct iop_adma_chan *iop_chan, dma_cookie_t cookie) @@ -78,40 +152,10 @@ iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc, * (unmap_single vs unmap_page?) */ if (desc->group_head && desc->unmap_len) { - struct iop_adma_desc_slot *unmap = desc->group_head; - struct device *dev = - &iop_chan->device->pdev->dev; - u32 len = unmap->unmap_len; - enum dma_ctrl_flags flags = tx->flags; - u32 src_cnt; - dma_addr_t addr; - dma_addr_t dest; - - src_cnt = unmap->unmap_src_cnt; - dest = iop_desc_get_dest_addr(unmap, iop_chan); - if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { - enum dma_data_direction dir; - - if (src_cnt > 1) /* is xor? */ - dir = DMA_BIDIRECTIONAL; - else - dir = DMA_FROM_DEVICE; - - dma_unmap_page(dev, dest, len, dir); - } - - if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { - while (src_cnt--) { - addr = iop_desc_get_src_addr(unmap, - iop_chan, - src_cnt); - if (addr == dest) - continue; - dma_unmap_page(dev, addr, len, - DMA_TO_DEVICE); - } - } - desc->group_head = NULL; + if (iop_desc_is_pq(desc)) + iop_desc_unmap_pq(iop_chan, desc); + else + iop_desc_unmap(iop_chan, desc); } } @@ -702,6 +746,118 @@ iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src, return sw_desc ? &sw_desc->async_tx : NULL; } +static struct dma_async_tx_descriptor * +iop_adma_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, + unsigned int src_cnt, const unsigned char *scf, size_t len, + unsigned long flags) +{ + struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); + struct iop_adma_desc_slot *sw_desc, *g; + int slot_cnt, slots_per_op; + int continue_srcs; + + if (unlikely(!len)) + return NULL; + BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); + + dev_dbg(iop_chan->device->common.dev, + "%s src_cnt: %d len: %u flags: %lx\n", + __func__, src_cnt, len, flags); + + if (dmaf_p_disabled_continue(flags)) + continue_srcs = 1+src_cnt; + else if (dmaf_continue(flags)) + continue_srcs = 3+src_cnt; + else + continue_srcs = 0+src_cnt; + + spin_lock_bh(&iop_chan->lock); + slot_cnt = iop_chan_pq_slot_count(len, continue_srcs, &slots_per_op); + sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); + if (sw_desc) { + int i; + + g = sw_desc->group_head; + iop_desc_set_byte_count(g, iop_chan, len); + + /* even if P is disabled its destination address (bits + * [3:0]) must match Q. It is ok if P points to an + * invalid address, it won't be written. + */ + if (flags & DMA_PREP_PQ_DISABLE_P) + dst[0] = dst[1] & 0x7; + + iop_desc_set_pq_addr(g, dst); + sw_desc->unmap_src_cnt = src_cnt; + sw_desc->unmap_len = len; + sw_desc->async_tx.flags = flags; + for (i = 0; i < src_cnt; i++) + iop_desc_set_pq_src_addr(g, i, src[i], scf[i]); + + /* if we are continuing a previous operation factor in + * the old p and q values, see the comment for dma_maxpq + * in include/linux/dmaengine.h + */ + if (dmaf_p_disabled_continue(flags)) + iop_desc_set_pq_src_addr(g, i++, dst[1], 1); + else if (dmaf_continue(flags)) { + iop_desc_set_pq_src_addr(g, i++, dst[0], 0); + iop_desc_set_pq_src_addr(g, i++, dst[1], 1); + iop_desc_set_pq_src_addr(g, i++, dst[1], 0); + } + iop_desc_init_pq(g, i, flags); + } + spin_unlock_bh(&iop_chan->lock); + + return sw_desc ? &sw_desc->async_tx : NULL; +} + +static struct dma_async_tx_descriptor * +iop_adma_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, + unsigned int src_cnt, const unsigned char *scf, + size_t len, enum sum_check_flags *pqres, + unsigned long flags) +{ + struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); + struct iop_adma_desc_slot *sw_desc, *g; + int slot_cnt, slots_per_op; + + if (unlikely(!len)) + return NULL; + BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); + + dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n", + __func__, src_cnt, len); + + spin_lock_bh(&iop_chan->lock); + slot_cnt = iop_chan_pq_zero_sum_slot_count(len, src_cnt + 2, &slots_per_op); + sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); + if (sw_desc) { + /* for validate operations p and q are tagged onto the + * end of the source list + */ + int pq_idx = src_cnt; + + g = sw_desc->group_head; + iop_desc_init_pq_zero_sum(g, src_cnt+2, flags); + iop_desc_set_pq_zero_sum_byte_count(g, len); + g->pq_check_result = pqres; + pr_debug("\t%s: g->pq_check_result: %p\n", + __func__, g->pq_check_result); + sw_desc->unmap_src_cnt = src_cnt+2; + sw_desc->unmap_len = len; + sw_desc->async_tx.flags = flags; + while (src_cnt--) + iop_desc_set_pq_zero_sum_src_addr(g, src_cnt, + src[src_cnt], + scf[src_cnt]); + iop_desc_set_pq_zero_sum_addr(g, pq_idx, src); + } + spin_unlock_bh(&iop_chan->lock); + + return sw_desc ? &sw_desc->async_tx : NULL; +} + static void iop_adma_free_chan_resources(struct dma_chan *chan) { struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); @@ -1201,6 +1357,13 @@ static int __devinit iop_adma_probe(struct platform_device *pdev) if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask)) dma_dev->device_prep_dma_xor_val = iop_adma_prep_dma_xor_val; + if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { + dma_set_maxpq(dma_dev, iop_adma_get_max_pq(), 0); + dma_dev->device_prep_dma_pq = iop_adma_prep_dma_pq; + } + if (dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) + dma_dev->device_prep_dma_pq_val = + iop_adma_prep_dma_pq_val; if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) dma_dev->device_prep_dma_interrupt = iop_adma_prep_dma_interrupt; -- cgit v0.10.2 From f6dbf651615900646fe0ba1ef5ce1027e5b4748d Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Sat, 29 Aug 2009 19:12:40 -0700 Subject: iop-adma: P+Q self test Even though the intent is to extend dmatest with P+Q tests there is still value in having an always-on sanity check to prevent an unintentionally broken driver from registering. This depends on raid6_pq.ko for verification, the side effect being that PQ capable channels will fail to register when raid6 is disabled. Signed-off-by: Dan Williams diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index 5a0f4fe..f4c59e5 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c @@ -31,6 +31,7 @@ #include #include #include +#include #include @@ -1267,6 +1268,170 @@ out: return err; } +#ifdef CONFIG_MD_RAID6_PQ +static int __devinit +iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device) +{ + /* combined sources, software pq results, and extra hw pq results */ + struct page *pq[IOP_ADMA_NUM_SRC_TEST+2+2]; + /* ptr to the extra hw pq buffers defined above */ + struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2]; + /* address conversion buffers (dma_map / page_address) */ + void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2]; + dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST]; + dma_addr_t pq_dest[2]; + + int i; + struct dma_async_tx_descriptor *tx; + struct dma_chan *dma_chan; + dma_cookie_t cookie; + u32 zero_sum_result; + int err = 0; + struct device *dev; + + dev_dbg(device->common.dev, "%s\n", __func__); + + for (i = 0; i < ARRAY_SIZE(pq); i++) { + pq[i] = alloc_page(GFP_KERNEL); + if (!pq[i]) { + while (i--) + __free_page(pq[i]); + return -ENOMEM; + } + } + + /* Fill in src buffers */ + for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) { + pq_sw[i] = page_address(pq[i]); + memset(pq_sw[i], 0x11111111 * (1<common.channels.next, + struct dma_chan, + device_node); + if (iop_adma_alloc_chan_resources(dma_chan) < 1) { + err = -ENODEV; + goto out; + } + + dev = dma_chan->device->dev; + + /* initialize the dests */ + memset(page_address(pq_hw[0]), 0 , PAGE_SIZE); + memset(page_address(pq_hw[1]), 0 , PAGE_SIZE); + + /* test pq */ + pq_dest[0] = dma_map_page(dev, pq_hw[0], 0, PAGE_SIZE, DMA_FROM_DEVICE); + pq_dest[1] = dma_map_page(dev, pq_hw[1], 0, PAGE_SIZE, DMA_FROM_DEVICE); + for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) + pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, + DMA_TO_DEVICE); + + tx = iop_adma_prep_dma_pq(dma_chan, pq_dest, pq_src, + IOP_ADMA_NUM_SRC_TEST, (u8 *)raid6_gfexp, + PAGE_SIZE, + DMA_PREP_INTERRUPT | + DMA_CTRL_ACK); + + cookie = iop_adma_tx_submit(tx); + iop_adma_issue_pending(dma_chan); + msleep(8); + + if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != + DMA_SUCCESS) { + dev_err(dev, "Self-test pq timed out, disabling\n"); + err = -ENODEV; + goto free_resources; + } + + raid6_call.gen_syndrome(IOP_ADMA_NUM_SRC_TEST+2, PAGE_SIZE, pq_sw); + + if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST], + page_address(pq_hw[0]), PAGE_SIZE) != 0) { + dev_err(dev, "Self-test p failed compare, disabling\n"); + err = -ENODEV; + goto free_resources; + } + if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST+1], + page_address(pq_hw[1]), PAGE_SIZE) != 0) { + dev_err(dev, "Self-test q failed compare, disabling\n"); + err = -ENODEV; + goto free_resources; + } + + /* test correct zero sum using the software generated pq values */ + for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++) + pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, + DMA_TO_DEVICE); + + zero_sum_result = ~0; + tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST], + pq_src, IOP_ADMA_NUM_SRC_TEST, + raid6_gfexp, PAGE_SIZE, &zero_sum_result, + DMA_PREP_INTERRUPT|DMA_CTRL_ACK); + + cookie = iop_adma_tx_submit(tx); + iop_adma_issue_pending(dma_chan); + msleep(8); + + if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != + DMA_SUCCESS) { + dev_err(dev, "Self-test pq-zero-sum timed out, disabling\n"); + err = -ENODEV; + goto free_resources; + } + + if (zero_sum_result != 0) { + dev_err(dev, "Self-test pq-zero-sum failed to validate: %x\n", + zero_sum_result); + err = -ENODEV; + goto free_resources; + } + + /* test incorrect zero sum */ + i = IOP_ADMA_NUM_SRC_TEST; + memset(pq_sw[i] + 100, 0, 100); + memset(pq_sw[i+1] + 200, 0, 200); + for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++) + pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, + DMA_TO_DEVICE); + + zero_sum_result = 0; + tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST], + pq_src, IOP_ADMA_NUM_SRC_TEST, + raid6_gfexp, PAGE_SIZE, &zero_sum_result, + DMA_PREP_INTERRUPT|DMA_CTRL_ACK); + + cookie = iop_adma_tx_submit(tx); + iop_adma_issue_pending(dma_chan); + msleep(8); + + if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != + DMA_SUCCESS) { + dev_err(dev, "Self-test !pq-zero-sum timed out, disabling\n"); + err = -ENODEV; + goto free_resources; + } + + if (zero_sum_result != (SUM_CHECK_P_RESULT | SUM_CHECK_Q_RESULT)) { + dev_err(dev, "Self-test !pq-zero-sum failed to validate: %x\n", + zero_sum_result); + err = -ENODEV; + goto free_resources; + } + +free_resources: + iop_adma_free_chan_resources(dma_chan); +out: + i = ARRAY_SIZE(pq); + while (i--) + __free_page(pq[i]); + return err; +} +#endif + static int __devexit iop_adma_remove(struct platform_device *dev) { struct iop_adma_device *device = platform_get_drvdata(dev); @@ -1417,13 +1582,28 @@ static int __devinit iop_adma_probe(struct platform_device *pdev) } if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) || - dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) { + dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) { ret = iop_adma_xor_val_self_test(adev); dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); if (ret) goto err_free_iop_chan; } + if (dma_has_cap(DMA_PQ, dma_dev->cap_mask) && + dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) { + #ifdef CONFIG_MD_RAID6_PQ + ret = iop_adma_pq_zero_sum_self_test(adev); + dev_dbg(&pdev->dev, "pq self test returned %d\n", ret); + #else + /* can not test raid6, so do not publish capability */ + dma_cap_clear(DMA_PQ, dma_dev->cap_mask); + dma_cap_clear(DMA_PQ_VAL, dma_dev->cap_mask); + ret = 0; + #endif + if (ret) + goto err_free_iop_chan; + } + dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: " "( %s%s%s%s%s%s%s%s%s%s)\n", dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "", -- cgit v0.10.2 From 4e7d2c0aefb77f7b24942e5af042a083be4d60bb Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Sat, 29 Aug 2009 19:13:11 -0700 Subject: md/raid5: factor out mark_uptodate from ops_complete_compute5 ops_complete_compute5 can be reused in the raid6 path if it is updated to generically handle a second target. Signed-off-by: Dan Williams diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 1f2a266..e3a2990 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -623,18 +623,29 @@ static void ops_run_biofill(struct stripe_head *sh) async_trigger_callback(&submit); } +static void mark_target_uptodate(struct stripe_head *sh, int target) +{ + struct r5dev *tgt; + + if (target < 0) + return; + + tgt = &sh->dev[target]; + set_bit(R5_UPTODATE, &tgt->flags); + BUG_ON(!test_bit(R5_Wantcompute, &tgt->flags)); + clear_bit(R5_Wantcompute, &tgt->flags); +} + static void ops_complete_compute5(void *stripe_head_ref) { struct stripe_head *sh = stripe_head_ref; - int target = sh->ops.target; - struct r5dev *tgt = &sh->dev[target]; pr_debug("%s: stripe %llu\n", __func__, (unsigned long long)sh->sector); - set_bit(R5_UPTODATE, &tgt->flags); - BUG_ON(!test_bit(R5_Wantcompute, &tgt->flags)); - clear_bit(R5_Wantcompute, &tgt->flags); + /* mark the computed target as uptodate */ + mark_target_uptodate(sh, sh->ops.target); + clear_bit(STRIPE_COMPUTE_RUN, &sh->state); if (sh->check_state == check_state_compute_run) sh->check_state = check_state_compute_result; -- cgit v0.10.2 From ac6b53b6e6acab27e4f3e2383f9ac1f0d7c6200b Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 14 Jul 2009 13:40:19 -0700 Subject: md/raid6: asynchronous raid6 operations [ Based on an original patch by Yuri Tikhonov ] The raid_run_ops routine uses the asynchronous offload api and the stripe_operations member of a stripe_head to carry out xor+pq+copy operations asynchronously, outside the lock. The operations performed by RAID-6 are the same as in the RAID-5 case except for no support of STRIPE_OP_PREXOR operations. All the others are supported: STRIPE_OP_BIOFILL - copy data into request buffers to satisfy a read request STRIPE_OP_COMPUTE_BLK - generate missing blocks (1 or 2) in the cache from the other blocks STRIPE_OP_BIODRAIN - copy data out of request buffers to satisfy a write request STRIPE_OP_RECONSTRUCT - recalculate parity for new data that has entered the cache STRIPE_OP_CHECK - verify that the parity is correct The flow is the same as in the RAID-5 case, and reuses some routines, namely: 1/ ops_complete_postxor (renamed to ops_complete_reconstruct) 2/ ops_complete_compute (updated to set up to 2 targets uptodate) 3/ ops_run_check (renamed to ops_run_check_p for xor parity checks) [neilb@suse.de: fixes to get it to pass mdadm regression suite] Reviewed-by: Andre Noll Signed-off-by: Yuri Tikhonov Signed-off-by: Ilya Yanok Signed-off-by: Dan Williams diff --git a/drivers/md/Kconfig b/drivers/md/Kconfig index 41b3ae2..abb8636 100644 --- a/drivers/md/Kconfig +++ b/drivers/md/Kconfig @@ -124,6 +124,8 @@ config MD_RAID456 select MD_RAID6_PQ select ASYNC_MEMCPY select ASYNC_XOR + select ASYNC_PQ + select ASYNC_RAID6_RECOV ---help--- A RAID-5 set of N drives with a capacity of C MB per drive provides the capacity of C * (N - 1) MB, and protects against a failure diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index e3a2990..e68616e 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -636,15 +636,16 @@ static void mark_target_uptodate(struct stripe_head *sh, int target) clear_bit(R5_Wantcompute, &tgt->flags); } -static void ops_complete_compute5(void *stripe_head_ref) +static void ops_complete_compute(void *stripe_head_ref) { struct stripe_head *sh = stripe_head_ref; pr_debug("%s: stripe %llu\n", __func__, (unsigned long long)sh->sector); - /* mark the computed target as uptodate */ + /* mark the computed target(s) as uptodate */ mark_target_uptodate(sh, sh->ops.target); + mark_target_uptodate(sh, sh->ops.target2); clear_bit(STRIPE_COMPUTE_RUN, &sh->state); if (sh->check_state == check_state_compute_run) @@ -684,7 +685,7 @@ ops_run_compute5(struct stripe_head *sh, struct raid5_percpu *percpu) atomic_inc(&sh->count); init_async_submit(&submit, ASYNC_TX_XOR_ZERO_DST, NULL, - ops_complete_compute5, sh, to_addr_conv(sh, percpu)); + ops_complete_compute, sh, to_addr_conv(sh, percpu)); if (unlikely(count == 1)) tx = async_memcpy(xor_dest, xor_srcs[0], 0, 0, STRIPE_SIZE, &submit); else @@ -693,6 +694,197 @@ ops_run_compute5(struct stripe_head *sh, struct raid5_percpu *percpu) return tx; } +/* set_syndrome_sources - populate source buffers for gen_syndrome + * @srcs - (struct page *) array of size sh->disks + * @sh - stripe_head to parse + * + * Populates srcs in proper layout order for the stripe and returns the + * 'count' of sources to be used in a call to async_gen_syndrome. The P + * destination buffer is recorded in srcs[count] and the Q destination + * is recorded in srcs[count+1]]. + */ +static int set_syndrome_sources(struct page **srcs, struct stripe_head *sh) +{ + int disks = sh->disks; + int syndrome_disks = sh->ddf_layout ? disks : (disks - 2); + int d0_idx = raid6_d0(sh); + int count; + int i; + + for (i = 0; i < disks; i++) + srcs[i] = (void *)raid6_empty_zero_page; + + count = 0; + i = d0_idx; + do { + int slot = raid6_idx_to_slot(i, sh, &count, syndrome_disks); + + srcs[slot] = sh->dev[i].page; + i = raid6_next_disk(i, disks); + } while (i != d0_idx); + BUG_ON(count != syndrome_disks); + + return count; +} + +static struct dma_async_tx_descriptor * +ops_run_compute6_1(struct stripe_head *sh, struct raid5_percpu *percpu) +{ + int disks = sh->disks; + struct page **blocks = percpu->scribble; + int target; + int qd_idx = sh->qd_idx; + struct dma_async_tx_descriptor *tx; + struct async_submit_ctl submit; + struct r5dev *tgt; + struct page *dest; + int i; + int count; + + if (sh->ops.target < 0) + target = sh->ops.target2; + else if (sh->ops.target2 < 0) + target = sh->ops.target; + else + /* we should only have one valid target */ + BUG(); + BUG_ON(target < 0); + pr_debug("%s: stripe %llu block: %d\n", + __func__, (unsigned long long)sh->sector, target); + + tgt = &sh->dev[target]; + BUG_ON(!test_bit(R5_Wantcompute, &tgt->flags)); + dest = tgt->page; + + atomic_inc(&sh->count); + + if (target == qd_idx) { + count = set_syndrome_sources(blocks, sh); + blocks[count] = NULL; /* regenerating p is not necessary */ + BUG_ON(blocks[count+1] != dest); /* q should already be set */ + init_async_submit(&submit, 0, NULL, ops_complete_compute, sh, + to_addr_conv(sh, percpu)); + tx = async_gen_syndrome(blocks, 0, count+2, STRIPE_SIZE, &submit); + } else { + /* Compute any data- or p-drive using XOR */ + count = 0; + for (i = disks; i-- ; ) { + if (i == target || i == qd_idx) + continue; + blocks[count++] = sh->dev[i].page; + } + + init_async_submit(&submit, ASYNC_TX_XOR_ZERO_DST, NULL, + ops_complete_compute, sh, + to_addr_conv(sh, percpu)); + tx = async_xor(dest, blocks, 0, count, STRIPE_SIZE, &submit); + } + + return tx; +} + +static struct dma_async_tx_descriptor * +ops_run_compute6_2(struct stripe_head *sh, struct raid5_percpu *percpu) +{ + int i, count, disks = sh->disks; + int syndrome_disks = sh->ddf_layout ? disks : disks-2; + int d0_idx = raid6_d0(sh); + int faila = -1, failb = -1; + int target = sh->ops.target; + int target2 = sh->ops.target2; + struct r5dev *tgt = &sh->dev[target]; + struct r5dev *tgt2 = &sh->dev[target2]; + struct dma_async_tx_descriptor *tx; + struct page **blocks = percpu->scribble; + struct async_submit_ctl submit; + + pr_debug("%s: stripe %llu block1: %d block2: %d\n", + __func__, (unsigned long long)sh->sector, target, target2); + BUG_ON(target < 0 || target2 < 0); + BUG_ON(!test_bit(R5_Wantcompute, &tgt->flags)); + BUG_ON(!test_bit(R5_Wantcompute, &tgt2->flags)); + + /* we need to open-code set_syndrome_sources to handle to the + * slot number conversion for 'faila' and 'failb' + */ + for (i = 0; i < disks ; i++) + blocks[i] = (void *)raid6_empty_zero_page; + count = 0; + i = d0_idx; + do { + int slot = raid6_idx_to_slot(i, sh, &count, syndrome_disks); + + blocks[slot] = sh->dev[i].page; + + if (i == target) + faila = slot; + if (i == target2) + failb = slot; + i = raid6_next_disk(i, disks); + } while (i != d0_idx); + BUG_ON(count != syndrome_disks); + + BUG_ON(faila == failb); + if (failb < faila) + swap(faila, failb); + pr_debug("%s: stripe: %llu faila: %d failb: %d\n", + __func__, (unsigned long long)sh->sector, faila, failb); + + atomic_inc(&sh->count); + + if (failb == syndrome_disks+1) { + /* Q disk is one of the missing disks */ + if (faila == syndrome_disks) { + /* Missing P+Q, just recompute */ + init_async_submit(&submit, 0, NULL, ops_complete_compute, + sh, to_addr_conv(sh, percpu)); + return async_gen_syndrome(blocks, 0, count+2, + STRIPE_SIZE, &submit); + } else { + struct page *dest; + int data_target; + int qd_idx = sh->qd_idx; + + /* Missing D+Q: recompute D from P, then recompute Q */ + if (target == qd_idx) + data_target = target2; + else + data_target = target; + + count = 0; + for (i = disks; i-- ; ) { + if (i == data_target || i == qd_idx) + continue; + blocks[count++] = sh->dev[i].page; + } + dest = sh->dev[data_target].page; + init_async_submit(&submit, ASYNC_TX_XOR_ZERO_DST, NULL, + NULL, NULL, to_addr_conv(sh, percpu)); + tx = async_xor(dest, blocks, 0, count, STRIPE_SIZE, + &submit); + + count = set_syndrome_sources(blocks, sh); + init_async_submit(&submit, 0, tx, ops_complete_compute, + sh, to_addr_conv(sh, percpu)); + return async_gen_syndrome(blocks, 0, count+2, + STRIPE_SIZE, &submit); + } + } + + init_async_submit(&submit, 0, NULL, ops_complete_compute, sh, + to_addr_conv(sh, percpu)); + if (failb == syndrome_disks) { + /* We're missing D+P. */ + return async_raid6_datap_recov(syndrome_disks+2, STRIPE_SIZE, + faila, blocks, &submit); + } else { + /* We're missing D+D. */ + return async_raid6_2data_recov(syndrome_disks+2, STRIPE_SIZE, + faila, failb, blocks, &submit); + } +} + + static void ops_complete_prexor(void *stripe_head_ref) { struct stripe_head *sh = stripe_head_ref; @@ -765,17 +957,21 @@ ops_run_biodrain(struct stripe_head *sh, struct dma_async_tx_descriptor *tx) return tx; } -static void ops_complete_postxor(void *stripe_head_ref) +static void ops_complete_reconstruct(void *stripe_head_ref) { struct stripe_head *sh = stripe_head_ref; - int disks = sh->disks, i, pd_idx = sh->pd_idx; + int disks = sh->disks; + int pd_idx = sh->pd_idx; + int qd_idx = sh->qd_idx; + int i; pr_debug("%s: stripe %llu\n", __func__, (unsigned long long)sh->sector); for (i = disks; i--; ) { struct r5dev *dev = &sh->dev[i]; - if (dev->written || i == pd_idx) + + if (dev->written || i == pd_idx || i == qd_idx) set_bit(R5_UPTODATE, &dev->flags); } @@ -793,8 +989,8 @@ static void ops_complete_postxor(void *stripe_head_ref) } static void -ops_run_postxor(struct stripe_head *sh, struct raid5_percpu *percpu, - struct dma_async_tx_descriptor *tx) +ops_run_reconstruct5(struct stripe_head *sh, struct raid5_percpu *percpu, + struct dma_async_tx_descriptor *tx) { int disks = sh->disks; struct page **xor_srcs = percpu->scribble; @@ -837,7 +1033,7 @@ ops_run_postxor(struct stripe_head *sh, struct raid5_percpu *percpu, atomic_inc(&sh->count); - init_async_submit(&submit, flags, tx, ops_complete_postxor, sh, + init_async_submit(&submit, flags, tx, ops_complete_reconstruct, sh, to_addr_conv(sh, percpu)); if (unlikely(count == 1)) tx = async_memcpy(xor_dest, xor_srcs[0], 0, 0, STRIPE_SIZE, &submit); @@ -845,6 +1041,25 @@ ops_run_postxor(struct stripe_head *sh, struct raid5_percpu *percpu, tx = async_xor(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, &submit); } +static void +ops_run_reconstruct6(struct stripe_head *sh, struct raid5_percpu *percpu, + struct dma_async_tx_descriptor *tx) +{ + struct async_submit_ctl submit; + struct page **blocks = percpu->scribble; + int count; + + pr_debug("%s: stripe %llu\n", __func__, (unsigned long long)sh->sector); + + count = set_syndrome_sources(blocks, sh); + + atomic_inc(&sh->count); + + init_async_submit(&submit, ASYNC_TX_ACK, tx, ops_complete_reconstruct, + sh, to_addr_conv(sh, percpu)); + async_gen_syndrome(blocks, 0, count+2, STRIPE_SIZE, &submit); +} + static void ops_complete_check(void *stripe_head_ref) { struct stripe_head *sh = stripe_head_ref; @@ -857,23 +1072,28 @@ static void ops_complete_check(void *stripe_head_ref) release_stripe(sh); } -static void ops_run_check(struct stripe_head *sh, struct raid5_percpu *percpu) +static void ops_run_check_p(struct stripe_head *sh, struct raid5_percpu *percpu) { int disks = sh->disks; + int pd_idx = sh->pd_idx; + int qd_idx = sh->qd_idx; + struct page *xor_dest; struct page **xor_srcs = percpu->scribble; struct dma_async_tx_descriptor *tx; struct async_submit_ctl submit; - - int count = 0, pd_idx = sh->pd_idx, i; - struct page *xor_dest = xor_srcs[count++] = sh->dev[pd_idx].page; + int count; + int i; pr_debug("%s: stripe %llu\n", __func__, (unsigned long long)sh->sector); + count = 0; + xor_dest = sh->dev[pd_idx].page; + xor_srcs[count++] = xor_dest; for (i = disks; i--; ) { - struct r5dev *dev = &sh->dev[i]; - if (i != pd_idx) - xor_srcs[count++] = dev->page; + if (i == pd_idx || i == qd_idx) + continue; + xor_srcs[count++] = sh->dev[i].page; } init_async_submit(&submit, 0, NULL, NULL, NULL, @@ -886,11 +1106,32 @@ static void ops_run_check(struct stripe_head *sh, struct raid5_percpu *percpu) tx = async_trigger_callback(&submit); } -static void raid5_run_ops(struct stripe_head *sh, unsigned long ops_request) +static void ops_run_check_pq(struct stripe_head *sh, struct raid5_percpu *percpu, int checkp) +{ + struct page **srcs = percpu->scribble; + struct async_submit_ctl submit; + int count; + + pr_debug("%s: stripe %llu checkp: %d\n", __func__, + (unsigned long long)sh->sector, checkp); + + count = set_syndrome_sources(srcs, sh); + if (!checkp) + srcs[count] = NULL; + + atomic_inc(&sh->count); + init_async_submit(&submit, ASYNC_TX_ACK, NULL, ops_complete_check, + sh, to_addr_conv(sh, percpu)); + async_syndrome_val(srcs, 0, count+2, STRIPE_SIZE, + &sh->ops.zero_sum_result, percpu->spare_page, &submit); +} + +static void raid_run_ops(struct stripe_head *sh, unsigned long ops_request) { int overlap_clear = 0, i, disks = sh->disks; struct dma_async_tx_descriptor *tx = NULL; raid5_conf_t *conf = sh->raid_conf; + int level = conf->level; struct raid5_percpu *percpu; unsigned long cpu; @@ -902,9 +1143,16 @@ static void raid5_run_ops(struct stripe_head *sh, unsigned long ops_request) } if (test_bit(STRIPE_OP_COMPUTE_BLK, &ops_request)) { - tx = ops_run_compute5(sh, percpu); - /* terminate the chain if postxor is not set to be run */ - if (tx && !test_bit(STRIPE_OP_POSTXOR, &ops_request)) + if (level < 6) + tx = ops_run_compute5(sh, percpu); + else { + if (sh->ops.target2 < 0 || sh->ops.target < 0) + tx = ops_run_compute6_1(sh, percpu); + else + tx = ops_run_compute6_2(sh, percpu); + } + /* terminate the chain if reconstruct is not set to be run */ + if (tx && !test_bit(STRIPE_OP_RECONSTRUCT, &ops_request)) async_tx_ack(tx); } @@ -916,11 +1164,23 @@ static void raid5_run_ops(struct stripe_head *sh, unsigned long ops_request) overlap_clear++; } - if (test_bit(STRIPE_OP_POSTXOR, &ops_request)) - ops_run_postxor(sh, percpu, tx); + if (test_bit(STRIPE_OP_RECONSTRUCT, &ops_request)) { + if (level < 6) + ops_run_reconstruct5(sh, percpu, tx); + else + ops_run_reconstruct6(sh, percpu, tx); + } - if (test_bit(STRIPE_OP_CHECK, &ops_request)) - ops_run_check(sh, percpu); + if (test_bit(STRIPE_OP_CHECK, &ops_request)) { + if (sh->check_state == check_state_run) + ops_run_check_p(sh, percpu); + else if (sh->check_state == check_state_run_q) + ops_run_check_pq(sh, percpu, 0); + else if (sh->check_state == check_state_run_pq) + ops_run_check_pq(sh, percpu, 1); + else + BUG(); + } if (overlap_clear) for (i = disks; i--; ) { @@ -1931,7 +2191,7 @@ schedule_reconstruction5(struct stripe_head *sh, struct stripe_head_state *s, } else sh->reconstruct_state = reconstruct_state_run; - set_bit(STRIPE_OP_POSTXOR, &s->ops_request); + set_bit(STRIPE_OP_RECONSTRUCT, &s->ops_request); for (i = disks; i--; ) { struct r5dev *dev = &sh->dev[i]; @@ -1954,7 +2214,7 @@ schedule_reconstruction5(struct stripe_head *sh, struct stripe_head_state *s, sh->reconstruct_state = reconstruct_state_prexor_drain_run; set_bit(STRIPE_OP_PREXOR, &s->ops_request); set_bit(STRIPE_OP_BIODRAIN, &s->ops_request); - set_bit(STRIPE_OP_POSTXOR, &s->ops_request); + set_bit(STRIPE_OP_RECONSTRUCT, &s->ops_request); for (i = disks; i--; ) { struct r5dev *dev = &sh->dev[i]; @@ -2206,9 +2466,10 @@ static int fetch_block5(struct stripe_head *sh, struct stripe_head_state *s, set_bit(STRIPE_OP_COMPUTE_BLK, &s->ops_request); set_bit(R5_Wantcompute, &dev->flags); sh->ops.target = disk_idx; + sh->ops.target2 = -1; s->req_compute = 1; /* Careful: from this point on 'uptodate' is in the eye - * of raid5_run_ops which services 'compute' operations + * of raid_run_ops which services 'compute' operations * before writes. R5_Wantcompute flags a block that will * be R5_UPTODATE by the time it is needed for a * subsequent operation. @@ -2435,8 +2696,8 @@ static void handle_stripe_dirtying5(raid5_conf_t *conf, */ /* since handle_stripe can be called at any time we need to handle the * case where a compute block operation has been submitted and then a - * subsequent call wants to start a write request. raid5_run_ops only - * handles the case where compute block and postxor are requested + * subsequent call wants to start a write request. raid_run_ops only + * handles the case where compute block and reconstruct are requested * simultaneously. If this is not the case then new writes need to be * held off until the compute completes. */ @@ -2618,6 +2879,7 @@ static void handle_parity_checks5(raid5_conf_t *conf, struct stripe_head *sh, set_bit(R5_Wantcompute, &sh->dev[sh->pd_idx].flags); sh->ops.target = sh->pd_idx; + sh->ops.target2 = -1; s->uptodate++; } } @@ -3067,7 +3329,7 @@ static bool handle_stripe5(struct stripe_head *sh) md_wait_for_blocked_rdev(blocked_rdev, conf->mddev); if (s.ops_request) - raid5_run_ops(sh, s.ops_request); + raid_run_ops(sh, s.ops_request); ops_run_io(sh, &s); diff --git a/drivers/md/raid5.h b/drivers/md/raid5.h index 75f2c6c..116d0b4 100644 --- a/drivers/md/raid5.h +++ b/drivers/md/raid5.h @@ -176,7 +176,9 @@ */ enum check_states { check_state_idle = 0, - check_state_run, /* parity check */ + check_state_run, /* xor parity check */ + check_state_run_q, /* q-parity check */ + check_state_run_pq, /* pq dual parity check */ check_state_check_result, check_state_compute_run, /* parity repair */ check_state_compute_result, @@ -216,7 +218,7 @@ struct stripe_head { * @target - STRIPE_OP_COMPUTE_BLK target */ struct stripe_operations { - int target; + int target, target2; enum sum_check_flags zero_sum_result; } ops; struct r5dev { @@ -299,7 +301,7 @@ struct r6_state { #define STRIPE_OP_COMPUTE_BLK 1 #define STRIPE_OP_PREXOR 2 #define STRIPE_OP_BIODRAIN 3 -#define STRIPE_OP_POSTXOR 4 +#define STRIPE_OP_RECONSTRUCT 4 #define STRIPE_OP_CHECK 5 /* -- cgit v0.10.2 From c0f7bddbe60f43578dccf4ffb8d4bff88f625ea7 Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Sat, 29 Aug 2009 19:13:12 -0700 Subject: md/raid5,6: common schedule_reconstruction for raid5/6 Extend schedule_reconstruction5 for reuse by the raid6 path. Add support for generating Q and BUG() if a request is made to perform 'prexor'. Signed-off-by: Yuri Tikhonov Signed-off-by: Ilya Yanok Signed-off-by: Dan Williams diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index e68616e..a1245cf 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -2175,10 +2175,12 @@ static void compute_block_2(struct stripe_head *sh, int dd_idx1, int dd_idx2) } static void -schedule_reconstruction5(struct stripe_head *sh, struct stripe_head_state *s, +schedule_reconstruction(struct stripe_head *sh, struct stripe_head_state *s, int rcw, int expand) { int i, pd_idx = sh->pd_idx, disks = sh->disks; + raid5_conf_t *conf = sh->raid_conf; + int level = conf->level; if (rcw) { /* if we are not expanding this is a proper write request, and @@ -2204,10 +2206,11 @@ schedule_reconstruction5(struct stripe_head *sh, struct stripe_head_state *s, s->locked++; } } - if (s->locked + 1 == disks) + if (s->locked + conf->max_degraded == disks) if (!test_and_set_bit(STRIPE_FULL_WRITE, &sh->state)) - atomic_inc(&sh->raid_conf->pending_full_writes); + atomic_inc(&conf->pending_full_writes); } else { + BUG_ON(level == 6); BUG_ON(!(test_bit(R5_UPTODATE, &sh->dev[pd_idx].flags) || test_bit(R5_Wantcompute, &sh->dev[pd_idx].flags))); @@ -2232,13 +2235,22 @@ schedule_reconstruction5(struct stripe_head *sh, struct stripe_head_state *s, } } - /* keep the parity disk locked while asynchronous operations + /* keep the parity disk(s) locked while asynchronous operations * are in flight */ set_bit(R5_LOCKED, &sh->dev[pd_idx].flags); clear_bit(R5_UPTODATE, &sh->dev[pd_idx].flags); s->locked++; + if (level == 6) { + int qd_idx = sh->qd_idx; + struct r5dev *dev = &sh->dev[qd_idx]; + + set_bit(R5_LOCKED, &dev->flags); + clear_bit(R5_UPTODATE, &dev->flags); + s->locked++; + } + pr_debug("%s: stripe %llu locked: %d ops_request: %lx\n", __func__, (unsigned long long)sh->sector, s->locked, s->ops_request); @@ -2704,7 +2716,7 @@ static void handle_stripe_dirtying5(raid5_conf_t *conf, if ((s->req_compute || !test_bit(STRIPE_COMPUTE_RUN, &sh->state)) && (s->locked == 0 && (rcw == 0 || rmw == 0) && !test_bit(STRIPE_BIT_DELAY, &sh->state))) - schedule_reconstruction5(sh, s, rcw == 0, 0); + schedule_reconstruction(sh, s, rcw == 0, 0); } static void handle_stripe_dirtying6(raid5_conf_t *conf, @@ -3309,7 +3321,7 @@ static bool handle_stripe5(struct stripe_head *sh) /* Need to write out all blocks after computing parity */ sh->disks = conf->raid_disks; stripe_set_idx(sh->sector, conf, 0, sh); - schedule_reconstruction5(sh, &s, 1, 1); + schedule_reconstruction(sh, &s, 1, 1); } else if (s.expanded && !sh->reconstruct_state && s.locked == 0) { clear_bit(STRIPE_EXPAND_READY, &sh->state); atomic_dec(&conf->reshape_stripes); -- cgit v0.10.2 From 5599becca4bee7badf605e41fd5bcde76d51f2a4 Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Sat, 29 Aug 2009 19:13:12 -0700 Subject: md/raid6: asynchronous handle_stripe_fill6 Modify handle_stripe_fill6 to work asynchronously by introducing fetch_block6 as the raid6 analog of fetch_block5 (schedule compute operations for missing/out-of-sync disks). [dan.j.williams@intel.com: compute D+Q in one pass] Signed-off-by: Yuri Tikhonov Signed-off-by: Ilya Yanok Signed-off-by: Dan Williams diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index a1245cf..49da6f7 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -2520,61 +2520,104 @@ static void handle_stripe_fill5(struct stripe_head *sh, set_bit(STRIPE_HANDLE, &sh->state); } -static void handle_stripe_fill6(struct stripe_head *sh, - struct stripe_head_state *s, struct r6_state *r6s, - int disks) +/* fetch_block6 - checks the given member device to see if its data needs + * to be read or computed to satisfy a request. + * + * Returns 1 when no more member devices need to be checked, otherwise returns + * 0 to tell the loop in handle_stripe_fill6 to continue + */ +static int fetch_block6(struct stripe_head *sh, struct stripe_head_state *s, + struct r6_state *r6s, int disk_idx, int disks) { - int i; - for (i = disks; i--; ) { - struct r5dev *dev = &sh->dev[i]; - if (!test_bit(R5_LOCKED, &dev->flags) && - !test_bit(R5_UPTODATE, &dev->flags) && - (dev->toread || (dev->towrite && - !test_bit(R5_OVERWRITE, &dev->flags)) || - s->syncing || s->expanding || - (s->failed >= 1 && - (sh->dev[r6s->failed_num[0]].toread || - s->to_write)) || - (s->failed >= 2 && - (sh->dev[r6s->failed_num[1]].toread || - s->to_write)))) { - /* we would like to get this block, possibly - * by computing it, but we might not be able to + struct r5dev *dev = &sh->dev[disk_idx]; + struct r5dev *fdev[2] = { &sh->dev[r6s->failed_num[0]], + &sh->dev[r6s->failed_num[1]] }; + + if (!test_bit(R5_LOCKED, &dev->flags) && + !test_bit(R5_UPTODATE, &dev->flags) && + (dev->toread || + (dev->towrite && !test_bit(R5_OVERWRITE, &dev->flags)) || + s->syncing || s->expanding || + (s->failed >= 1 && + (fdev[0]->toread || s->to_write)) || + (s->failed >= 2 && + (fdev[1]->toread || s->to_write)))) { + /* we would like to get this block, possibly by computing it, + * otherwise read it if the backing disk is insync + */ + BUG_ON(test_bit(R5_Wantcompute, &dev->flags)); + BUG_ON(test_bit(R5_Wantread, &dev->flags)); + if ((s->uptodate == disks - 1) && + (s->failed && (disk_idx == r6s->failed_num[0] || + disk_idx == r6s->failed_num[1]))) { + /* have disk failed, and we're requested to fetch it; + * do compute it */ - if ((s->uptodate == disks - 1) && - (s->failed && (i == r6s->failed_num[0] || - i == r6s->failed_num[1]))) { - pr_debug("Computing stripe %llu block %d\n", - (unsigned long long)sh->sector, i); - compute_block_1(sh, i, 0); - s->uptodate++; - } else if ( s->uptodate == disks-2 && s->failed >= 2 ) { - /* Computing 2-failure is *very* expensive; only - * do it if failed >= 2 - */ - int other; - for (other = disks; other--; ) { - if (other == i) - continue; - if (!test_bit(R5_UPTODATE, - &sh->dev[other].flags)) - break; - } - BUG_ON(other < 0); - pr_debug("Computing stripe %llu blocks %d,%d\n", - (unsigned long long)sh->sector, - i, other); - compute_block_2(sh, i, other); - s->uptodate += 2; - } else if (test_bit(R5_Insync, &dev->flags)) { - set_bit(R5_LOCKED, &dev->flags); - set_bit(R5_Wantread, &dev->flags); - s->locked++; - pr_debug("Reading block %d (sync=%d)\n", - i, s->syncing); + pr_debug("Computing stripe %llu block %d\n", + (unsigned long long)sh->sector, disk_idx); + set_bit(STRIPE_COMPUTE_RUN, &sh->state); + set_bit(STRIPE_OP_COMPUTE_BLK, &s->ops_request); + set_bit(R5_Wantcompute, &dev->flags); + sh->ops.target = disk_idx; + sh->ops.target2 = -1; /* no 2nd target */ + s->req_compute = 1; + s->uptodate++; + return 1; + } else if (s->uptodate == disks-2 && s->failed >= 2) { + /* Computing 2-failure is *very* expensive; only + * do it if failed >= 2 + */ + int other; + for (other = disks; other--; ) { + if (other == disk_idx) + continue; + if (!test_bit(R5_UPTODATE, + &sh->dev[other].flags)) + break; } + BUG_ON(other < 0); + pr_debug("Computing stripe %llu blocks %d,%d\n", + (unsigned long long)sh->sector, + disk_idx, other); + set_bit(STRIPE_COMPUTE_RUN, &sh->state); + set_bit(STRIPE_OP_COMPUTE_BLK, &s->ops_request); + set_bit(R5_Wantcompute, &sh->dev[disk_idx].flags); + set_bit(R5_Wantcompute, &sh->dev[other].flags); + sh->ops.target = disk_idx; + sh->ops.target2 = other; + s->uptodate += 2; + s->req_compute = 1; + return 1; + } else if (test_bit(R5_Insync, &dev->flags)) { + set_bit(R5_LOCKED, &dev->flags); + set_bit(R5_Wantread, &dev->flags); + s->locked++; + pr_debug("Reading block %d (sync=%d)\n", + disk_idx, s->syncing); } } + + return 0; +} + +/** + * handle_stripe_fill6 - read or compute data to satisfy pending requests. + */ +static void handle_stripe_fill6(struct stripe_head *sh, + struct stripe_head_state *s, struct r6_state *r6s, + int disks) +{ + int i; + + /* look for blocks to read/compute, skip this if a compute + * is already in flight, or if the stripe contents are in the + * midst of changing due to a write + */ + if (!test_bit(STRIPE_COMPUTE_RUN, &sh->state) && !sh->check_state && + !sh->reconstruct_state) + for (i = disks; i--; ) + if (fetch_block6(sh, s, r6s, i, disks)) + break; set_bit(STRIPE_HANDLE, &sh->state); } -- cgit v0.10.2 From a9b39a741a7e3b262b9f51fefb68e17b32756999 Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Sat, 29 Aug 2009 19:13:12 -0700 Subject: md/raid6: asynchronous handle_stripe_dirtying6 In the synchronous implementation of stripe dirtying we processed a degraded stripe with one call to handle_stripe_dirtying6(). I.e. compute the missing blocks from the other drives, then copy in the new data and reconstruct the parities. In the asynchronous case we do not perform stripe operations directly. Instead, operations are scheduled with flags to be later serviced by raid_run_ops. So, for the degraded case the final reconstruction step can only be carried out after all blocks have been brought up to date by being read, or computed. Like the raid5 case schedule_reconstruction() sets STRIPE_OP_RECONSTRUCT to request a parity generation pass and through operation chaining can handle compute and reconstruct in a single raid_run_ops pass. [dan.j.williams@intel.com: fixup handle_stripe_dirtying6 gating] Signed-off-by: Yuri Tikhonov Signed-off-by: Ilya Yanok Signed-off-by: Dan Williams diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 49da6f7..08f8063 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -2766,99 +2766,46 @@ static void handle_stripe_dirtying6(raid5_conf_t *conf, struct stripe_head *sh, struct stripe_head_state *s, struct r6_state *r6s, int disks) { - int rcw = 0, must_compute = 0, pd_idx = sh->pd_idx, i; + int rcw = 0, pd_idx = sh->pd_idx, i; int qd_idx = sh->qd_idx; + + set_bit(STRIPE_HANDLE, &sh->state); for (i = disks; i--; ) { struct r5dev *dev = &sh->dev[i]; - /* Would I have to read this buffer for reconstruct_write */ - if (!test_bit(R5_OVERWRITE, &dev->flags) - && i != pd_idx && i != qd_idx - && (!test_bit(R5_LOCKED, &dev->flags) - ) && - !test_bit(R5_UPTODATE, &dev->flags)) { - if (test_bit(R5_Insync, &dev->flags)) rcw++; - else { - pr_debug("raid6: must_compute: " - "disk %d flags=%#lx\n", i, dev->flags); - must_compute++; + /* check if we haven't enough data */ + if (!test_bit(R5_OVERWRITE, &dev->flags) && + i != pd_idx && i != qd_idx && + !test_bit(R5_LOCKED, &dev->flags) && + !(test_bit(R5_UPTODATE, &dev->flags) || + test_bit(R5_Wantcompute, &dev->flags))) { + rcw++; + if (!test_bit(R5_Insync, &dev->flags)) + continue; /* it's a failed drive */ + + if ( + test_bit(STRIPE_PREREAD_ACTIVE, &sh->state)) { + pr_debug("Read_old stripe %llu " + "block %d for Reconstruct\n", + (unsigned long long)sh->sector, i); + set_bit(R5_LOCKED, &dev->flags); + set_bit(R5_Wantread, &dev->flags); + s->locked++; + } else { + pr_debug("Request delayed stripe %llu " + "block %d for Reconstruct\n", + (unsigned long long)sh->sector, i); + set_bit(STRIPE_DELAYED, &sh->state); + set_bit(STRIPE_HANDLE, &sh->state); } } } - pr_debug("for sector %llu, rcw=%d, must_compute=%d\n", - (unsigned long long)sh->sector, rcw, must_compute); - set_bit(STRIPE_HANDLE, &sh->state); - - if (rcw > 0) - /* want reconstruct write, but need to get some data */ - for (i = disks; i--; ) { - struct r5dev *dev = &sh->dev[i]; - if (!test_bit(R5_OVERWRITE, &dev->flags) - && !(s->failed == 0 && (i == pd_idx || i == qd_idx)) - && !test_bit(R5_LOCKED, &dev->flags) && - !test_bit(R5_UPTODATE, &dev->flags) && - test_bit(R5_Insync, &dev->flags)) { - if ( - test_bit(STRIPE_PREREAD_ACTIVE, &sh->state)) { - pr_debug("Read_old stripe %llu " - "block %d for Reconstruct\n", - (unsigned long long)sh->sector, i); - set_bit(R5_LOCKED, &dev->flags); - set_bit(R5_Wantread, &dev->flags); - s->locked++; - } else { - pr_debug("Request delayed stripe %llu " - "block %d for Reconstruct\n", - (unsigned long long)sh->sector, i); - set_bit(STRIPE_DELAYED, &sh->state); - set_bit(STRIPE_HANDLE, &sh->state); - } - } - } /* now if nothing is locked, and if we have enough data, we can start a * write request */ - if (s->locked == 0 && rcw == 0 && + if ((s->req_compute || !test_bit(STRIPE_COMPUTE_RUN, &sh->state)) && + s->locked == 0 && rcw == 0 && !test_bit(STRIPE_BIT_DELAY, &sh->state)) { - if (must_compute > 0) { - /* We have failed blocks and need to compute them */ - switch (s->failed) { - case 0: - BUG(); - case 1: - compute_block_1(sh, r6s->failed_num[0], 0); - break; - case 2: - compute_block_2(sh, r6s->failed_num[0], - r6s->failed_num[1]); - break; - default: /* This request should have been failed? */ - BUG(); - } - } - - pr_debug("Computing parity for stripe %llu\n", - (unsigned long long)sh->sector); - compute_parity6(sh, RECONSTRUCT_WRITE); - /* now every locked buffer is ready to be written */ - for (i = disks; i--; ) - if (test_bit(R5_LOCKED, &sh->dev[i].flags)) { - pr_debug("Writing stripe %llu block %d\n", - (unsigned long long)sh->sector, i); - s->locked++; - set_bit(R5_Wantwrite, &sh->dev[i].flags); - } - if (s->locked == disks) - if (!test_and_set_bit(STRIPE_FULL_WRITE, &sh->state)) - atomic_inc(&conf->pending_full_writes); - /* after a RECONSTRUCT_WRITE, the stripe MUST be in-sync */ - set_bit(STRIPE_INSYNC, &sh->state); - - if (test_and_clear_bit(STRIPE_PREREAD_ACTIVE, &sh->state)) { - atomic_dec(&conf->preread_active_stripes); - if (atomic_read(&conf->preread_active_stripes) < - IO_THRESHOLD) - md_wakeup_thread(conf->mddev->thread); - } + schedule_reconstruction(sh, s, 1, 0); } } @@ -3539,8 +3486,13 @@ static bool handle_stripe6(struct stripe_head *sh) (s.syncing && (s.uptodate < disks)) || s.expanding) handle_stripe_fill6(sh, &s, &r6s, disks); - /* now to consider writing and what else, if anything should be read */ - if (s.to_write) + /* Now to consider new write requests and what else, if anything + * should be read. We do not handle new writes when: + * 1/ A 'write' operation (copy+gen_syndrome) is already in flight. + * 2/ A 'check' operation is in flight, as it may clobber the parity + * block. + */ + if (s.to_write && !sh->reconstruct_state && !sh->check_state) handle_stripe_dirtying6(conf, sh, &s, &r6s, disks); /* maybe we need to check and possibly fix the parity for this stripe -- cgit v0.10.2 From d82dfee0ad8f240fef1b28e2258891c07da57367 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 14 Jul 2009 13:40:57 -0700 Subject: md/raid6: asynchronous handle_parity_check6 [ Based on an original patch by Yuri Tikhonov ] Implement the state machine for handling the RAID-6 parities check and repair functionality. Note that the raid6 case does not need to check for new failures, like raid5, as it will always writeback the correct disks. The raid5 case can be updated to check zero_sum_result to avoid getting confused by new failures rather than retrying the entire check operation. Signed-off-by: Yuri Tikhonov Signed-off-by: Ilya Yanok Signed-off-by: Dan Williams diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 08f8063..3c31f7f 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -2901,91 +2901,163 @@ static void handle_parity_checks6(raid5_conf_t *conf, struct stripe_head *sh, struct stripe_head_state *s, struct r6_state *r6s, int disks) { - int update_p = 0, update_q = 0; - struct r5dev *dev; int pd_idx = sh->pd_idx; int qd_idx = sh->qd_idx; - unsigned long cpu; - struct page *tmp_page; + struct r5dev *dev; set_bit(STRIPE_HANDLE, &sh->state); BUG_ON(s->failed > 2); - BUG_ON(s->uptodate < disks); + /* Want to check and possibly repair P and Q. * However there could be one 'failed' device, in which * case we can only check one of them, possibly using the * other to generate missing data */ - cpu = get_cpu(); - tmp_page = per_cpu_ptr(conf->percpu, cpu)->spare_page; - if (s->failed == r6s->q_failed) { - /* The only possible failed device holds 'Q', so it - * makes sense to check P (If anything else were failed, - * we would have used P to recreate it). - */ - compute_block_1(sh, pd_idx, 1); - if (!page_is_zero(sh->dev[pd_idx].page)) { - compute_block_1(sh, pd_idx, 0); - update_p = 1; + + switch (sh->check_state) { + case check_state_idle: + /* start a new check operation if there are < 2 failures */ + if (s->failed == r6s->q_failed) { + /* The only possible failed device holds Q, so it + * makes sense to check P (If anything else were failed, + * we would have used P to recreate it). + */ + sh->check_state = check_state_run; } - } - if (!r6s->q_failed && s->failed < 2) { - /* q is not failed, and we didn't use it to generate - * anything, so it makes sense to check it - */ - memcpy(page_address(tmp_page), - page_address(sh->dev[qd_idx].page), - STRIPE_SIZE); - compute_parity6(sh, UPDATE_PARITY); - if (memcmp(page_address(tmp_page), - page_address(sh->dev[qd_idx].page), - STRIPE_SIZE) != 0) { - clear_bit(STRIPE_INSYNC, &sh->state); - update_q = 1; + if (!r6s->q_failed && s->failed < 2) { + /* Q is not failed, and we didn't use it to generate + * anything, so it makes sense to check it + */ + if (sh->check_state == check_state_run) + sh->check_state = check_state_run_pq; + else + sh->check_state = check_state_run_q; } - } - put_cpu(); - if (update_p || update_q) { - conf->mddev->resync_mismatches += STRIPE_SECTORS; - if (test_bit(MD_RECOVERY_CHECK, &conf->mddev->recovery)) - /* don't try to repair!! */ - update_p = update_q = 0; - } + /* discard potentially stale zero_sum_result */ + sh->ops.zero_sum_result = 0; - /* now write out any block on a failed drive, - * or P or Q if they need it - */ + if (sh->check_state == check_state_run) { + /* async_xor_zero_sum destroys the contents of P */ + clear_bit(R5_UPTODATE, &sh->dev[pd_idx].flags); + s->uptodate--; + } + if (sh->check_state >= check_state_run && + sh->check_state <= check_state_run_pq) { + /* async_syndrome_zero_sum preserves P and Q, so + * no need to mark them !uptodate here + */ + set_bit(STRIPE_OP_CHECK, &s->ops_request); + break; + } - if (s->failed == 2) { - dev = &sh->dev[r6s->failed_num[1]]; - s->locked++; - set_bit(R5_LOCKED, &dev->flags); - set_bit(R5_Wantwrite, &dev->flags); - } - if (s->failed >= 1) { - dev = &sh->dev[r6s->failed_num[0]]; - s->locked++; - set_bit(R5_LOCKED, &dev->flags); - set_bit(R5_Wantwrite, &dev->flags); - } + /* we have 2-disk failure */ + BUG_ON(s->failed != 2); + /* fall through */ + case check_state_compute_result: + sh->check_state = check_state_idle; - if (update_p) { - dev = &sh->dev[pd_idx]; - s->locked++; - set_bit(R5_LOCKED, &dev->flags); - set_bit(R5_Wantwrite, &dev->flags); - } - if (update_q) { - dev = &sh->dev[qd_idx]; - s->locked++; - set_bit(R5_LOCKED, &dev->flags); - set_bit(R5_Wantwrite, &dev->flags); - } - clear_bit(STRIPE_DEGRADED, &sh->state); + /* check that a write has not made the stripe insync */ + if (test_bit(STRIPE_INSYNC, &sh->state)) + break; - set_bit(STRIPE_INSYNC, &sh->state); + /* now write out any block on a failed drive, + * or P or Q if they were recomputed + */ + BUG_ON(s->uptodate < disks - 1); /* We don't need Q to recover */ + if (s->failed == 2) { + dev = &sh->dev[r6s->failed_num[1]]; + s->locked++; + set_bit(R5_LOCKED, &dev->flags); + set_bit(R5_Wantwrite, &dev->flags); + } + if (s->failed >= 1) { + dev = &sh->dev[r6s->failed_num[0]]; + s->locked++; + set_bit(R5_LOCKED, &dev->flags); + set_bit(R5_Wantwrite, &dev->flags); + } + if (sh->ops.zero_sum_result & SUM_CHECK_P_RESULT) { + dev = &sh->dev[pd_idx]; + s->locked++; + set_bit(R5_LOCKED, &dev->flags); + set_bit(R5_Wantwrite, &dev->flags); + } + if (sh->ops.zero_sum_result & SUM_CHECK_Q_RESULT) { + dev = &sh->dev[qd_idx]; + s->locked++; + set_bit(R5_LOCKED, &dev->flags); + set_bit(R5_Wantwrite, &dev->flags); + } + clear_bit(STRIPE_DEGRADED, &sh->state); + + set_bit(STRIPE_INSYNC, &sh->state); + break; + case check_state_run: + case check_state_run_q: + case check_state_run_pq: + break; /* we will be called again upon completion */ + case check_state_check_result: + sh->check_state = check_state_idle; + + /* handle a successful check operation, if parity is correct + * we are done. Otherwise update the mismatch count and repair + * parity if !MD_RECOVERY_CHECK + */ + if (sh->ops.zero_sum_result == 0) { + /* both parities are correct */ + if (!s->failed) + set_bit(STRIPE_INSYNC, &sh->state); + else { + /* in contrast to the raid5 case we can validate + * parity, but still have a failure to write + * back + */ + sh->check_state = check_state_compute_result; + /* Returning at this point means that we may go + * off and bring p and/or q uptodate again so + * we make sure to check zero_sum_result again + * to verify if p or q need writeback + */ + } + } else { + conf->mddev->resync_mismatches += STRIPE_SECTORS; + if (test_bit(MD_RECOVERY_CHECK, &conf->mddev->recovery)) + /* don't try to repair!! */ + set_bit(STRIPE_INSYNC, &sh->state); + else { + int *target = &sh->ops.target; + + sh->ops.target = -1; + sh->ops.target2 = -1; + sh->check_state = check_state_compute_run; + set_bit(STRIPE_COMPUTE_RUN, &sh->state); + set_bit(STRIPE_OP_COMPUTE_BLK, &s->ops_request); + if (sh->ops.zero_sum_result & SUM_CHECK_P_RESULT) { + set_bit(R5_Wantcompute, + &sh->dev[pd_idx].flags); + *target = pd_idx; + target = &sh->ops.target2; + s->uptodate++; + } + if (sh->ops.zero_sum_result & SUM_CHECK_Q_RESULT) { + set_bit(R5_Wantcompute, + &sh->dev[qd_idx].flags); + *target = qd_idx; + s->uptodate++; + } + } + } + break; + case check_state_compute_run: + break; + default: + printk(KERN_ERR "%s: unknown check_state: %d sector: %llu\n", + __func__, sh->check_state, + (unsigned long long) sh->sector); + BUG(); + } } static void handle_stripe_expansion(raid5_conf_t *conf, struct stripe_head *sh, -- cgit v0.10.2 From 6c0069c0ae9659e3a91b68eaed06a5c6c37f45c8 Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Sat, 29 Aug 2009 19:13:13 -0700 Subject: md/raid6: asynchronous handle_stripe6 1/ Use STRIPE_OP_BIOFILL to offload completion of read requests to raid_run_ops 2/ Implement a handler for sh->reconstruct_state similar to the raid5 case (adds handling of Q parity) 3/ Prevent handle_parity_checks6 from running concurrently with 'compute' operations 4/ Hook up raid_run_ops Signed-off-by: Yuri Tikhonov Signed-off-by: Ilya Yanok Signed-off-by: Dan Williams diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 3c31f7f..a833de1 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -3424,9 +3424,10 @@ static bool handle_stripe6(struct stripe_head *sh) mdk_rdev_t *blocked_rdev = NULL; pr_debug("handling stripe %llu, state=%#lx cnt=%d, " - "pd_idx=%d, qd_idx=%d\n", + "pd_idx=%d, qd_idx=%d\n, check:%d, reconstruct:%d\n", (unsigned long long)sh->sector, sh->state, - atomic_read(&sh->count), pd_idx, qd_idx); + atomic_read(&sh->count), pd_idx, qd_idx, + sh->check_state, sh->reconstruct_state); memset(&s, 0, sizeof(s)); spin_lock(&sh->lock); @@ -3446,35 +3447,24 @@ static bool handle_stripe6(struct stripe_head *sh) pr_debug("check %d: state 0x%lx read %p write %p written %p\n", i, dev->flags, dev->toread, dev->towrite, dev->written); - /* maybe we can reply to a read */ - if (test_bit(R5_UPTODATE, &dev->flags) && dev->toread) { - struct bio *rbi, *rbi2; - pr_debug("Return read for disc %d\n", i); - spin_lock_irq(&conf->device_lock); - rbi = dev->toread; - dev->toread = NULL; - if (test_and_clear_bit(R5_Overlap, &dev->flags)) - wake_up(&conf->wait_for_overlap); - spin_unlock_irq(&conf->device_lock); - while (rbi && rbi->bi_sector < dev->sector + STRIPE_SECTORS) { - copy_data(0, rbi, dev->page, dev->sector); - rbi2 = r5_next_bio(rbi, dev->sector); - spin_lock_irq(&conf->device_lock); - if (!raid5_dec_bi_phys_segments(rbi)) { - rbi->bi_next = return_bi; - return_bi = rbi; - } - spin_unlock_irq(&conf->device_lock); - rbi = rbi2; - } - } + /* maybe we can reply to a read + * + * new wantfill requests are only permitted while + * ops_complete_biofill is guaranteed to be inactive + */ + if (test_bit(R5_UPTODATE, &dev->flags) && dev->toread && + !test_bit(STRIPE_BIOFILL_RUN, &sh->state)) + set_bit(R5_Wantfill, &dev->flags); /* now count some things */ if (test_bit(R5_LOCKED, &dev->flags)) s.locked++; if (test_bit(R5_UPTODATE, &dev->flags)) s.uptodate++; + if (test_bit(R5_Wantcompute, &dev->flags)) + BUG_ON(++s.compute > 2); - - if (dev->toread) + if (test_bit(R5_Wantfill, &dev->flags)) { + s.to_fill++; + } else if (dev->toread) s.to_read++; if (dev->towrite) { s.to_write++; @@ -3515,6 +3505,11 @@ static bool handle_stripe6(struct stripe_head *sh) blocked_rdev = NULL; } + if (s.to_fill && !test_bit(STRIPE_BIOFILL_RUN, &sh->state)) { + set_bit(STRIPE_OP_BIOFILL, &s.ops_request); + set_bit(STRIPE_BIOFILL_RUN, &sh->state); + } + pr_debug("locked=%d uptodate=%d to_read=%d" " to_write=%d failed=%d failed_num=%d,%d\n", s.locked, s.uptodate, s.to_read, s.to_write, s.failed, @@ -3555,9 +3550,43 @@ static bool handle_stripe6(struct stripe_head *sh) * or to load a block that is being partially written. */ if (s.to_read || s.non_overwrite || (s.to_write && s.failed) || - (s.syncing && (s.uptodate < disks)) || s.expanding) + (s.syncing && (s.uptodate + s.compute < disks)) || s.expanding) handle_stripe_fill6(sh, &s, &r6s, disks); + /* Now we check to see if any write operations have recently + * completed + */ + if (sh->reconstruct_state == reconstruct_state_drain_result) { + int qd_idx = sh->qd_idx; + + sh->reconstruct_state = reconstruct_state_idle; + /* All the 'written' buffers and the parity blocks are ready to + * be written back to disk + */ + BUG_ON(!test_bit(R5_UPTODATE, &sh->dev[sh->pd_idx].flags)); + BUG_ON(!test_bit(R5_UPTODATE, &sh->dev[qd_idx].flags)); + for (i = disks; i--; ) { + dev = &sh->dev[i]; + if (test_bit(R5_LOCKED, &dev->flags) && + (i == sh->pd_idx || i == qd_idx || + dev->written)) { + pr_debug("Writing block %d\n", i); + BUG_ON(!test_bit(R5_UPTODATE, &dev->flags)); + set_bit(R5_Wantwrite, &dev->flags); + if (!test_bit(R5_Insync, &dev->flags) || + ((i == sh->pd_idx || i == qd_idx) && + s.failed == 0)) + set_bit(STRIPE_INSYNC, &sh->state); + } + } + if (test_and_clear_bit(STRIPE_PREREAD_ACTIVE, &sh->state)) { + atomic_dec(&conf->preread_active_stripes); + if (atomic_read(&conf->preread_active_stripes) < + IO_THRESHOLD) + md_wakeup_thread(conf->mddev->thread); + } + } + /* Now to consider new write requests and what else, if anything * should be read. We do not handle new writes when: * 1/ A 'write' operation (copy+gen_syndrome) is already in flight. @@ -3569,9 +3598,13 @@ static bool handle_stripe6(struct stripe_head *sh) /* maybe we need to check and possibly fix the parity for this stripe * Any reads will already have been scheduled, so we just see if enough - * data is available + * data is available. The parity check is held off while parity + * dependent operations are in flight. */ - if (s.syncing && s.locked == 0 && !test_bit(STRIPE_INSYNC, &sh->state)) + if (sh->check_state || + (s.syncing && s.locked == 0 && + !test_bit(STRIPE_COMPUTE_RUN, &sh->state) && + !test_bit(STRIPE_INSYNC, &sh->state))) handle_parity_checks6(conf, sh, &s, &r6s, disks); if (s.syncing && s.locked == 0 && test_bit(STRIPE_INSYNC, &sh->state)) { @@ -3593,15 +3626,29 @@ static bool handle_stripe6(struct stripe_head *sh) set_bit(R5_Wantwrite, &dev->flags); set_bit(R5_ReWrite, &dev->flags); set_bit(R5_LOCKED, &dev->flags); + s.locked++; } else { /* let's read it back */ set_bit(R5_Wantread, &dev->flags); set_bit(R5_LOCKED, &dev->flags); + s.locked++; } } } - if (s.expanded && test_bit(STRIPE_EXPANDING, &sh->state)) { + /* Finish reconstruct operations initiated by the expansion process */ + if (sh->reconstruct_state == reconstruct_state_result) { + sh->reconstruct_state = reconstruct_state_idle; + clear_bit(STRIPE_EXPANDING, &sh->state); + for (i = conf->raid_disks; i--; ) { + set_bit(R5_Wantwrite, &sh->dev[i].flags); + set_bit(R5_LOCKED, &sh->dev[i].flags); + s.locked++; + } + } + + if (s.expanded && test_bit(STRIPE_EXPANDING, &sh->state) && + !sh->reconstruct_state) { struct stripe_head *sh2 = get_active_stripe(conf, sh->sector, 1, 1); if (sh2 && test_bit(STRIPE_EXPAND_SOURCE, &sh2->state)) { @@ -3622,14 +3669,8 @@ static bool handle_stripe6(struct stripe_head *sh) /* Need to write out all blocks after computing P&Q */ sh->disks = conf->raid_disks; stripe_set_idx(sh->sector, conf, 0, sh); - compute_parity6(sh, RECONSTRUCT_WRITE); - for (i = conf->raid_disks ; i-- ; ) { - set_bit(R5_LOCKED, &sh->dev[i].flags); - s.locked++; - set_bit(R5_Wantwrite, &sh->dev[i].flags); - } - clear_bit(STRIPE_EXPANDING, &sh->state); - } else if (s.expanded) { + schedule_reconstruction(sh, &s, 1, 1); + } else if (s.expanded && !sh->reconstruct_state && s.locked == 0) { clear_bit(STRIPE_EXPAND_READY, &sh->state); atomic_dec(&conf->reshape_stripes); wake_up(&conf->wait_for_overlap); @@ -3647,6 +3688,9 @@ static bool handle_stripe6(struct stripe_head *sh) if (unlikely(blocked_rdev)) md_wait_for_blocked_rdev(blocked_rdev, conf->mddev); + if (s.ops_request) + raid_run_ops(sh, s.ops_request); + ops_run_io(sh, &s); return_io(return_bi); -- cgit v0.10.2 From b774ef491b4edf6876077014ecbb87f10c69c10f Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Sat, 29 Aug 2009 19:13:13 -0700 Subject: md/raid6: remove synchronous infrastructure These routines have been replaced by there asynchronous counterparts. Signed-off-by: Yuri Tikhonov Signed-off-by: Ilya Yanok Signed-off-by: Dan Williams diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index a833de1..7c22e19 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -1927,253 +1927,6 @@ static sector_t compute_blocknr(struct stripe_head *sh, int i, int previous) } - -/* - * Copy data between a page in the stripe cache, and one or more bion - * The page could align with the middle of the bio, or there could be - * several bion, each with several bio_vecs, which cover part of the page - * Multiple bion are linked together on bi_next. There may be extras - * at the end of this list. We ignore them. - */ -static void copy_data(int frombio, struct bio *bio, - struct page *page, - sector_t sector) -{ - char *pa = page_address(page); - struct bio_vec *bvl; - int i; - int page_offset; - - if (bio->bi_sector >= sector) - page_offset = (signed)(bio->bi_sector - sector) * 512; - else - page_offset = (signed)(sector - bio->bi_sector) * -512; - bio_for_each_segment(bvl, bio, i) { - int len = bio_iovec_idx(bio,i)->bv_len; - int clen; - int b_offset = 0; - - if (page_offset < 0) { - b_offset = -page_offset; - page_offset += b_offset; - len -= b_offset; - } - - if (len > 0 && page_offset + len > STRIPE_SIZE) - clen = STRIPE_SIZE - page_offset; - else clen = len; - - if (clen > 0) { - char *ba = __bio_kmap_atomic(bio, i, KM_USER0); - if (frombio) - memcpy(pa+page_offset, ba+b_offset, clen); - else - memcpy(ba+b_offset, pa+page_offset, clen); - __bio_kunmap_atomic(ba, KM_USER0); - } - if (clen < len) /* hit end of page */ - break; - page_offset += len; - } -} - -#define check_xor() do { \ - if (count == MAX_XOR_BLOCKS) { \ - xor_blocks(count, STRIPE_SIZE, dest, ptr);\ - count = 0; \ - } \ - } while(0) - -static void compute_parity6(struct stripe_head *sh, int method) -{ - raid5_conf_t *conf = sh->raid_conf; - int i, pd_idx, qd_idx, d0_idx, disks = sh->disks, count; - int syndrome_disks = sh->ddf_layout ? disks : (disks - 2); - struct bio *chosen; - /**** FIX THIS: This could be very bad if disks is close to 256 ****/ - void *ptrs[syndrome_disks+2]; - - pd_idx = sh->pd_idx; - qd_idx = sh->qd_idx; - d0_idx = raid6_d0(sh); - - pr_debug("compute_parity, stripe %llu, method %d\n", - (unsigned long long)sh->sector, method); - - switch(method) { - case READ_MODIFY_WRITE: - BUG(); /* READ_MODIFY_WRITE N/A for RAID-6 */ - case RECONSTRUCT_WRITE: - for (i= disks; i-- ;) - if ( i != pd_idx && i != qd_idx && sh->dev[i].towrite ) { - chosen = sh->dev[i].towrite; - sh->dev[i].towrite = NULL; - - if (test_and_clear_bit(R5_Overlap, &sh->dev[i].flags)) - wake_up(&conf->wait_for_overlap); - - BUG_ON(sh->dev[i].written); - sh->dev[i].written = chosen; - } - break; - case CHECK_PARITY: - BUG(); /* Not implemented yet */ - } - - for (i = disks; i--;) - if (sh->dev[i].written) { - sector_t sector = sh->dev[i].sector; - struct bio *wbi = sh->dev[i].written; - while (wbi && wbi->bi_sector < sector + STRIPE_SECTORS) { - copy_data(1, wbi, sh->dev[i].page, sector); - wbi = r5_next_bio(wbi, sector); - } - - set_bit(R5_LOCKED, &sh->dev[i].flags); - set_bit(R5_UPTODATE, &sh->dev[i].flags); - } - - /* Note that unlike RAID-5, the ordering of the disks matters greatly.*/ - - for (i = 0; i < disks; i++) - ptrs[i] = (void *)raid6_empty_zero_page; - - count = 0; - i = d0_idx; - do { - int slot = raid6_idx_to_slot(i, sh, &count, syndrome_disks); - - ptrs[slot] = page_address(sh->dev[i].page); - if (slot < syndrome_disks && - !test_bit(R5_UPTODATE, &sh->dev[i].flags)) { - printk(KERN_ERR "block %d/%d not uptodate " - "on parity calc\n", i, count); - BUG(); - } - - i = raid6_next_disk(i, disks); - } while (i != d0_idx); - BUG_ON(count != syndrome_disks); - - raid6_call.gen_syndrome(syndrome_disks+2, STRIPE_SIZE, ptrs); - - switch(method) { - case RECONSTRUCT_WRITE: - set_bit(R5_UPTODATE, &sh->dev[pd_idx].flags); - set_bit(R5_UPTODATE, &sh->dev[qd_idx].flags); - set_bit(R5_LOCKED, &sh->dev[pd_idx].flags); - set_bit(R5_LOCKED, &sh->dev[qd_idx].flags); - break; - case UPDATE_PARITY: - set_bit(R5_UPTODATE, &sh->dev[pd_idx].flags); - set_bit(R5_UPTODATE, &sh->dev[qd_idx].flags); - break; - } -} - - -/* Compute one missing block */ -static void compute_block_1(struct stripe_head *sh, int dd_idx, int nozero) -{ - int i, count, disks = sh->disks; - void *ptr[MAX_XOR_BLOCKS], *dest, *p; - int qd_idx = sh->qd_idx; - - pr_debug("compute_block_1, stripe %llu, idx %d\n", - (unsigned long long)sh->sector, dd_idx); - - if ( dd_idx == qd_idx ) { - /* We're actually computing the Q drive */ - compute_parity6(sh, UPDATE_PARITY); - } else { - dest = page_address(sh->dev[dd_idx].page); - if (!nozero) memset(dest, 0, STRIPE_SIZE); - count = 0; - for (i = disks ; i--; ) { - if (i == dd_idx || i == qd_idx) - continue; - p = page_address(sh->dev[i].page); - if (test_bit(R5_UPTODATE, &sh->dev[i].flags)) - ptr[count++] = p; - else - printk("compute_block() %d, stripe %llu, %d" - " not present\n", dd_idx, - (unsigned long long)sh->sector, i); - - check_xor(); - } - if (count) - xor_blocks(count, STRIPE_SIZE, dest, ptr); - if (!nozero) set_bit(R5_UPTODATE, &sh->dev[dd_idx].flags); - else clear_bit(R5_UPTODATE, &sh->dev[dd_idx].flags); - } -} - -/* Compute two missing blocks */ -static void compute_block_2(struct stripe_head *sh, int dd_idx1, int dd_idx2) -{ - int i, count, disks = sh->disks; - int syndrome_disks = sh->ddf_layout ? disks : disks-2; - int d0_idx = raid6_d0(sh); - int faila = -1, failb = -1; - /**** FIX THIS: This could be very bad if disks is close to 256 ****/ - void *ptrs[syndrome_disks+2]; - - for (i = 0; i < disks ; i++) - ptrs[i] = (void *)raid6_empty_zero_page; - count = 0; - i = d0_idx; - do { - int slot = raid6_idx_to_slot(i, sh, &count, syndrome_disks); - - ptrs[slot] = page_address(sh->dev[i].page); - - if (i == dd_idx1) - faila = slot; - if (i == dd_idx2) - failb = slot; - i = raid6_next_disk(i, disks); - } while (i != d0_idx); - BUG_ON(count != syndrome_disks); - - BUG_ON(faila == failb); - if ( failb < faila ) { int tmp = faila; faila = failb; failb = tmp; } - - pr_debug("compute_block_2, stripe %llu, idx %d,%d (%d,%d)\n", - (unsigned long long)sh->sector, dd_idx1, dd_idx2, - faila, failb); - - if (failb == syndrome_disks+1) { - /* Q disk is one of the missing disks */ - if (faila == syndrome_disks) { - /* Missing P+Q, just recompute */ - compute_parity6(sh, UPDATE_PARITY); - return; - } else { - /* We're missing D+Q; recompute D from P */ - compute_block_1(sh, ((dd_idx1 == sh->qd_idx) ? - dd_idx2 : dd_idx1), - 0); - compute_parity6(sh, UPDATE_PARITY); /* Is this necessary? */ - return; - } - } - - /* We're missing D+P or D+D; */ - if (failb == syndrome_disks) { - /* We're missing D+P. */ - raid6_datap_recov(syndrome_disks+2, STRIPE_SIZE, faila, ptrs); - } else { - /* We're missing D+D. */ - raid6_2data_recov(syndrome_disks+2, STRIPE_SIZE, faila, failb, - ptrs); - } - - /* Both the above update both missing blocks */ - set_bit(R5_UPTODATE, &sh->dev[dd_idx1].flags); - set_bit(R5_UPTODATE, &sh->dev[dd_idx2].flags); -} - static void schedule_reconstruction(struct stripe_head *sh, struct stripe_head_state *s, int rcw, int expand) @@ -2331,13 +2084,6 @@ static int add_stripe_bio(struct stripe_head *sh, struct bio *bi, int dd_idx, in static void end_reshape(raid5_conf_t *conf); -static int page_is_zero(struct page *p) -{ - char *a = page_address(p); - return ((*(u32*)a) == 0 && - memcmp(a, a+4, STRIPE_SIZE-4)==0); -} - static void stripe_set_idx(sector_t stripe, raid5_conf_t *conf, int previous, struct stripe_head *sh) { -- cgit v0.10.2 From 07a3b417dc3d00802bd7b4874c3e811f0b015a7d Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Sat, 29 Aug 2009 19:13:13 -0700 Subject: md/raid456: distribute raid processing over multiple cores Now that the resources to handle stripe_head operations are allocated percpu it is possible for raid5d to distribute stripe handling over multiple cores. This conversion also adds a call to cond_resched() in the non-multicore case to prevent one core from getting monopolized for raid operations. Cc: Arjan van de Ven Signed-off-by: Dan Williams diff --git a/drivers/md/Kconfig b/drivers/md/Kconfig index abb8636..09c0c6e 100644 --- a/drivers/md/Kconfig +++ b/drivers/md/Kconfig @@ -154,6 +154,17 @@ config MD_RAID456 If unsure, say Y. +config MULTICORE_RAID456 + bool "RAID-4/RAID-5/RAID-6 Multicore processing (EXPERIMENTAL)" + depends on MD_RAID456 + depends on SMP + depends on EXPERIMENTAL + ---help--- + Enable the raid456 module to dispatch per-stripe raid operations to a + thread pool. + + If unsure, say N. + config MD_RAID6_PQ tristate diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 7c22e19..364ea37 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include #include "md.h" @@ -4314,6 +4315,36 @@ static int retry_aligned_read(raid5_conf_t *conf, struct bio *raid_bio) return handled; } +#ifdef CONFIG_MULTICORE_RAID456 +static void __process_stripe(void *param, async_cookie_t cookie) +{ + struct stripe_head *sh = param; + + handle_stripe(sh); + release_stripe(sh); +} + +static void process_stripe(struct stripe_head *sh, struct list_head *domain) +{ + async_schedule_domain(__process_stripe, sh, domain); +} + +static void synchronize_stripe_processing(struct list_head *domain) +{ + async_synchronize_full_domain(domain); +} +#else +static void process_stripe(struct stripe_head *sh, struct list_head *domain) +{ + handle_stripe(sh); + release_stripe(sh); + cond_resched(); +} + +static void synchronize_stripe_processing(struct list_head *domain) +{ +} +#endif /* @@ -4328,6 +4359,7 @@ static void raid5d(mddev_t *mddev) struct stripe_head *sh; raid5_conf_t *conf = mddev_to_conf(mddev); int handled; + LIST_HEAD(raid_domain); pr_debug("+++ raid5d active\n"); @@ -4364,8 +4396,7 @@ static void raid5d(mddev_t *mddev) spin_unlock_irq(&conf->device_lock); handled++; - handle_stripe(sh); - release_stripe(sh); + process_stripe(sh, &raid_domain); spin_lock_irq(&conf->device_lock); } @@ -4373,6 +4404,7 @@ static void raid5d(mddev_t *mddev) spin_unlock_irq(&conf->device_lock); + synchronize_stripe_processing(&raid_domain); async_tx_issue_pending_all(); unplug_slaves(mddev); -- cgit v0.10.2 From eb0ca849863ecdc593ba7faa95fda5695af891c8 Mon Sep 17 00:00:00 2001 From: Len Brown Date: Sat, 29 Aug 2009 22:39:06 -0400 Subject: ACPI: sleep: another HP DMI entry for init_set_sci_en_on_resume DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion dv3 Notebook PC") http://bugzilla.kernel.org/show_bug.cgi?id=13745 Signed-off-by: Len Brown diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c index 42159a2..e0a7409 100644 --- a/drivers/acpi/sleep.c +++ b/drivers/acpi/sleep.c @@ -405,6 +405,14 @@ static struct dmi_system_id __initdata acpisleep_dmi_table[] = { }, }, { + .callback = init_set_sci_en_on_resume, + .ident = "Hewlett-Packard HP Pavilion dv3 Notebook PC", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), + DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion dv3 Notebook PC"), + }, + }, + { .callback = init_old_suspend_ordering, .ident = "Panasonic CF51-2L", .matches = { -- cgit v0.10.2 From 4b4fe3b62e8d88068083218d3e42c45223b51d29 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Sat, 8 Aug 2009 00:26:25 -0700 Subject: ACPI: video - fix potential crash when unloading thermal_cooling_device_register() returns error encoded in a pointer when it fails in which case we need to explictly set device->cdev to NULL so we don't try to unregister it when unloading. Signed-off-by: Dmitry Torokhov Acked-by: Zhang Rui Signed-off-by: Len Brown diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c index 2020907..aab3851 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c @@ -997,8 +997,18 @@ static void acpi_video_device_find_cap(struct acpi_video_device *device) device->cdev = thermal_cooling_device_register("LCD", device->dev, &video_cooling_ops); - if (IS_ERR(device->cdev)) + if (IS_ERR(device->cdev)) { + /* + * Set cdev to NULL so we don't crash trying to + * free it. + * Also, why the hell we are returning early and + * not attempt to register video output if cooling + * device registration failed? + * -- dtor + */ + device->cdev = NULL; return; + } dev_info(&device->dev->dev, "registered as cooling_device%d\n", device->cdev->id); -- cgit v0.10.2 From 4a703a8fe562824f269943d995ddff35077253a9 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Sat, 29 Aug 2009 23:03:16 -0400 Subject: ACPI: video - rename cdev to cooling_dev -- syntax only Cdev name is normally used for ether class devices or character devices so rename member to avoid confusion for casual reader of the code. Signed-off-by: Dmitry Torokhov Signed-off-by: Len Brown diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c index aab3851..a8432c2 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c @@ -198,7 +198,7 @@ struct acpi_video_device { struct acpi_device *dev; struct acpi_video_device_brightness *brightness; struct backlight_device *backlight; - struct thermal_cooling_device *cdev; + struct thermal_cooling_device *cooling_dev; struct output_device *output_dev; }; @@ -387,20 +387,20 @@ static struct output_properties acpi_output_properties = { /* thermal cooling device callbacks */ -static int video_get_max_state(struct thermal_cooling_device *cdev, unsigned +static int video_get_max_state(struct thermal_cooling_device *cooling_dev, unsigned long *state) { - struct acpi_device *device = cdev->devdata; + struct acpi_device *device = cooling_dev->devdata; struct acpi_video_device *video = acpi_driver_data(device); *state = video->brightness->count - 3; return 0; } -static int video_get_cur_state(struct thermal_cooling_device *cdev, unsigned +static int video_get_cur_state(struct thermal_cooling_device *cooling_dev, unsigned long *state) { - struct acpi_device *device = cdev->devdata; + struct acpi_device *device = cooling_dev->devdata; struct acpi_video_device *video = acpi_driver_data(device); unsigned long long level; int offset; @@ -417,9 +417,9 @@ static int video_get_cur_state(struct thermal_cooling_device *cdev, unsigned } static int -video_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state) +video_set_cur_state(struct thermal_cooling_device *cooling_dev, unsigned long state) { - struct acpi_device *device = cdev->devdata; + struct acpi_device *device = cooling_dev->devdata; struct acpi_video_device *video = acpi_driver_data(device); int level; @@ -995,29 +995,29 @@ static void acpi_video_device_find_cap(struct acpi_video_device *device) if (result) printk(KERN_ERR PREFIX "Create sysfs link\n"); - device->cdev = thermal_cooling_device_register("LCD", + device->cooling_dev = thermal_cooling_device_register("LCD", device->dev, &video_cooling_ops); - if (IS_ERR(device->cdev)) { + if (IS_ERR(device->cooling_dev)) { /* - * Set cdev to NULL so we don't crash trying to + * Set cooling_dev to NULL so we don't crash trying to * free it. * Also, why the hell we are returning early and * not attempt to register video output if cooling * device registration failed? * -- dtor */ - device->cdev = NULL; + device->cooling_dev = NULL; return; } dev_info(&device->dev->dev, "registered as cooling_device%d\n", - device->cdev->id); + device->cooling_dev->id); result = sysfs_create_link(&device->dev->dev.kobj, - &device->cdev->device.kobj, + &device->cooling_dev->device.kobj, "thermal_cooling"); if (result) printk(KERN_ERR PREFIX "Create sysfs link\n"); - result = sysfs_create_link(&device->cdev->device.kobj, + result = sysfs_create_link(&device->cooling_dev->device.kobj, &device->dev->dev.kobj, "device"); if (result) printk(KERN_ERR PREFIX "Create sysfs link\n"); @@ -2020,13 +2020,13 @@ static int acpi_video_bus_put_one_device(struct acpi_video_device *device) acpi_video_device_notify); sysfs_remove_link(&device->backlight->dev.kobj, "device"); backlight_device_unregister(device->backlight); - if (device->cdev) { + if (device->cooling_dev) { sysfs_remove_link(&device->dev->dev.kobj, "thermal_cooling"); - sysfs_remove_link(&device->cdev->device.kobj, + sysfs_remove_link(&device->cooling_dev->device.kobj, "device"); - thermal_cooling_device_unregister(device->cdev); - device->cdev = NULL; + thermal_cooling_device_unregister(device->cooling_dev); + device->cooling_dev = NULL; } video_output_unregister(device->output_dev); -- cgit v0.10.2 From 8211a7b5857914058c52ae977c96463e419b37ab Mon Sep 17 00:00:00 2001 From: Troy Heber Date: Wed, 19 Aug 2009 15:26:11 -0600 Subject: pci/dmar: correct off-by-one error in dmar_fault() DMAR faults are recorded into a ring of "fault recording registers". fault_index is a 0-based index into the ring. The code allows the 0-based fault_index to be equal to the total number of fault registers available from the cap_num_fault_regs() macro, which causes access beyond the last available register. Signed-off-by Troy Heber Signed-off-by: David Woodhouse diff --git a/drivers/pci/dmar.c b/drivers/pci/dmar.c index 380b60e..3264b62 100644 --- a/drivers/pci/dmar.c +++ b/drivers/pci/dmar.c @@ -1226,7 +1226,7 @@ irqreturn_t dmar_fault(int irq, void *dev_id) source_id, guest_addr); fault_index++; - if (fault_index > cap_num_fault_regs(iommu->cap)) + if (fault_index >= cap_num_fault_regs(iommu->cap)) fault_index = 0; spin_lock_irqsave(&iommu->register_lock, flag); } -- cgit v0.10.2 From 689d7c2a1127378854c7d7ea8d7c81238a824240 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 27 Aug 2009 11:51:23 +1000 Subject: drm/radeon: cleanup mkregtable.c This cleans up the code in mkregtable.c to be more kernel style. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c index 0acd1cf..fb211e5 100644 --- a/drivers/gpu/drm/radeon/mkregtable.c +++ b/drivers/gpu/drm/radeon/mkregtable.c @@ -25,10 +25,8 @@ * */ #define container_of(ptr, type, member) ({ \ - const typeof( ((type *)0)->member ) *__mptr = (ptr); \ - (type *)( (char *)__mptr - offsetof(type,member) );}) - - + const typeof(((type *)0)->member)*__mptr = (ptr); \ + (type *)((char *)__mptr - offsetof(type, member)); }) /* * Simple doubly linked list implementation. @@ -63,8 +61,7 @@ static inline void INIT_LIST_HEAD(struct list_head *list) */ #ifndef CONFIG_DEBUG_LIST static inline void __list_add(struct list_head *new, - struct list_head *prev, - struct list_head *next) + struct list_head *prev, struct list_head *next) { next->prev = new; new->next = next; @@ -73,8 +70,7 @@ static inline void __list_add(struct list_head *new, } #else extern void __list_add(struct list_head *new, - struct list_head *prev, - struct list_head *next); + struct list_head *prev, struct list_head *next); #endif /** @@ -90,7 +86,6 @@ static inline void list_add(struct list_head *new, struct list_head *head) __list_add(new, head, head->next); } - /** * list_add_tail - add a new entry * @new: new entry to be added @@ -111,7 +106,7 @@ static inline void list_add_tail(struct list_head *new, struct list_head *head) * This is only for internal list manipulation where we know * the prev/next entries already! */ -static inline void __list_del(struct list_head * prev, struct list_head * next) +static inline void __list_del(struct list_head *prev, struct list_head *next) { next->prev = prev; prev->next = next; @@ -127,8 +122,8 @@ static inline void __list_del(struct list_head * prev, struct list_head * next) static inline void list_del(struct list_head *entry) { __list_del(entry->prev, entry->next); - entry->next = (void*)0xDEADBEEF; - entry->prev = (void*)0xBEEFDEAD; + entry->next = (void *)0xDEADBEEF; + entry->prev = (void *)0xBEEFDEAD; } #else extern void list_del(struct list_head *entry); @@ -141,8 +136,7 @@ extern void list_del(struct list_head *entry); * * If @old was empty, it will be overwritten. */ -static inline void list_replace(struct list_head *old, - struct list_head *new) +static inline void list_replace(struct list_head *old, struct list_head *new) { new->next = old->next; new->next->prev = new; @@ -151,7 +145,7 @@ static inline void list_replace(struct list_head *old, } static inline void list_replace_init(struct list_head *old, - struct list_head *new) + struct list_head *new) { list_replace(old, new); INIT_LIST_HEAD(old); @@ -196,7 +190,7 @@ static inline void list_move_tail(struct list_head *list, * @head: the head of the list */ static inline int list_is_last(const struct list_head *list, - const struct list_head *head) + const struct list_head *head) { return list->next == head; } @@ -239,7 +233,8 @@ static inline int list_is_singular(const struct list_head *head) } static inline void __list_cut_position(struct list_head *list, - struct list_head *head, struct list_head *entry) + struct list_head *head, + struct list_head *entry) { struct list_head *new_first = entry->next; list->next = head->next; @@ -265,12 +260,12 @@ static inline void __list_cut_position(struct list_head *list, * */ static inline void list_cut_position(struct list_head *list, - struct list_head *head, struct list_head *entry) + struct list_head *head, + struct list_head *entry) { if (list_empty(head)) return; - if (list_is_singular(head) && - (head->next != entry && head != entry)) + if (list_is_singular(head) && (head->next != entry && head != entry)) return; if (entry == head) INIT_LIST_HEAD(list); @@ -279,8 +274,7 @@ static inline void list_cut_position(struct list_head *list, } static inline void __list_splice(const struct list_head *list, - struct list_head *prev, - struct list_head *next) + struct list_head *prev, struct list_head *next) { struct list_head *first = list->next; struct list_head *last = list->prev; @@ -298,7 +292,7 @@ static inline void __list_splice(const struct list_head *list, * @head: the place to add it in the first list. */ static inline void list_splice(const struct list_head *list, - struct list_head *head) + struct list_head *head) { if (!list_empty(list)) __list_splice(list, head, head->next); @@ -310,7 +304,7 @@ static inline void list_splice(const struct list_head *list, * @head: the place to add it in the first list. */ static inline void list_splice_tail(struct list_head *list, - struct list_head *head) + struct list_head *head) { if (!list_empty(list)) __list_splice(list, head->prev, head); @@ -376,7 +370,7 @@ static inline void list_splice_tail_init(struct list_head *list, */ #define list_for_each(pos, head) \ for (pos = (head)->next; prefetch(pos->next), pos != (head); \ - pos = pos->next) + pos = pos->next) /** * __list_for_each - iterate over a list @@ -398,7 +392,7 @@ static inline void list_splice_tail_init(struct list_head *list, */ #define list_for_each_prev(pos, head) \ for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \ - pos = pos->prev) + pos = pos->prev) /** * list_for_each_safe - iterate over a list safe against removal of list entry @@ -555,172 +549,172 @@ static inline void list_splice_tail_init(struct list_head *list, pos = n, n = list_entry(n->member.prev, typeof(*n), member)) struct offset { - struct list_head list; - unsigned offset; + struct list_head list; + unsigned offset; }; struct table { - struct list_head offsets; - unsigned offset_max; - unsigned nentry; - unsigned *table; - char *gpu_prefix; + struct list_head offsets; + unsigned offset_max; + unsigned nentry; + unsigned *table; + char *gpu_prefix; }; -struct offset* offset_new(unsigned o) +struct offset *offset_new(unsigned o) { - struct offset *offset; - - offset = (struct offset*)malloc(sizeof(struct offset)); - if (offset) { - INIT_LIST_HEAD(&offset->list); - offset->offset = o; - } - return offset; + struct offset *offset; + + offset = (struct offset *)malloc(sizeof(struct offset)); + if (offset) { + INIT_LIST_HEAD(&offset->list); + offset->offset = o; + } + return offset; } void table_offset_add(struct table *t, struct offset *offset) { - list_add_tail(&offset->list, &t->offsets); + list_add_tail(&offset->list, &t->offsets); } void table_init(struct table *t) { - INIT_LIST_HEAD(&t->offsets); - t->offset_max = 0; - t->nentry = 0; - t->table = NULL; + INIT_LIST_HEAD(&t->offsets); + t->offset_max = 0; + t->nentry = 0; + t->table = NULL; } void table_print(struct table *t) { - unsigned nlloop, i, j, n, c, id; - - nlloop = (t->nentry + 3) / 4; - c = t->nentry; - printf("static const unsigned %s_reg_safe_bm[%d] = {\n", t->gpu_prefix, t->nentry); - for(i = 0, id = 0; i < nlloop; i++) { - n = 4; - if (n > c) { - n = c; - } - c -= n; - for(j = 0; j < n; j++) { - if (j == 0) printf("\t"); - else printf(" "); - printf("0x%08X,", t->table[id++]); - } - printf("\n"); - } - printf("};\n"); + unsigned nlloop, i, j, n, c, id; + + nlloop = (t->nentry + 3) / 4; + c = t->nentry; + printf("static const unsigned %s_reg_safe_bm[%d] = {\n", t->gpu_prefix, + t->nentry); + for (i = 0, id = 0; i < nlloop; i++) { + n = 4; + if (n > c) + n = c; + c -= n; + for (j = 0; j < n; j++) { + if (j == 0) + printf("\t"); + else + printf(" "); + printf("0x%08X,", t->table[id++]); + } + printf("\n"); + } + printf("};\n"); } int table_build(struct table *t) { - struct offset *offset; - unsigned i, m; - - t->nentry = ((t->offset_max >> 2) + 31) / 32; - t->table = (unsigned*)malloc(sizeof(unsigned) * t->nentry); - if (t->table == NULL) { - return -1; - } - memset(t->table, 0xff, sizeof(unsigned) * t->nentry); - list_for_each_entry(offset, &t->offsets, list) { - i = (offset->offset >> 2) / 32; - m = (offset->offset >> 2) & 31; - m = 1 << m; - t->table[i] ^= m; - } - return 0; + struct offset *offset; + unsigned i, m; + + t->nentry = ((t->offset_max >> 2) + 31) / 32; + t->table = (unsigned *)malloc(sizeof(unsigned) * t->nentry); + if (t->table == NULL) + return -1; + memset(t->table, 0xff, sizeof(unsigned) * t->nentry); + list_for_each_entry(offset, &t->offsets, list) { + i = (offset->offset >> 2) / 32; + m = (offset->offset >> 2) & 31; + m = 1 << m; + t->table[i] ^= m; + } + return 0; } static char gpu_name[10]; int parser_auth(struct table *t, const char *filename) { - FILE *file; - regex_t mask_rex; - regmatch_t match[4]; - char buf[1024]; - size_t end; - int len; - int done = 0; - int r; - unsigned o; - struct offset *offset; - char last_reg_s[10]; - int last_reg; - - if (regcomp(&mask_rex, "(0x[0-9a-fA-F]*) *([_a-zA-Z0-9]*)", REG_EXTENDED)) { - fprintf(stderr, "Failed to compile regular expression\n"); - return -1; - } - file = fopen(filename, "r"); - if (file == NULL) { - fprintf(stderr, "Failed to open: %s\n", filename); - return -1; - } - fseek(file, 0, SEEK_END); - end = ftell(file); - fseek(file, 0, SEEK_SET); - - /* get header */ - if (fgets(buf, 1024, file) == NULL) - return -1; - - /* first line will contain the last register - * and gpu name */ - sscanf(buf, "%s %s", gpu_name, last_reg_s); - t->gpu_prefix = gpu_name; - last_reg = strtol(last_reg_s, NULL, 16); - - do { - if (fgets(buf, 1024, file) == NULL) - return -1; - len = strlen(buf); - if (ftell(file) == end) { - done = 1; - } - if (len) { - r = regexec(&mask_rex, buf, 4, match, 0); - if (r == REG_NOMATCH) { - } else if (r) { - fprintf(stderr, "Error matching regular expression %d in %s\n", - r, filename); - return -1; - } else { - buf[match[0].rm_eo] = 0; - buf[match[1].rm_eo] = 0; - buf[match[2].rm_eo] = 0; - o = strtol(&buf[match[1].rm_so], NULL, 16); - offset = offset_new(o); - table_offset_add(t, offset); - if (o > t->offset_max) { - t->offset_max = o; - } - } - } - } while (!done); - fclose(file); - if (t->offset_max < last_reg) - t->offset_max = last_reg; - return table_build(t); + FILE *file; + regex_t mask_rex; + regmatch_t match[4]; + char buf[1024]; + size_t end; + int len; + int done = 0; + int r; + unsigned o; + struct offset *offset; + char last_reg_s[10]; + int last_reg; + + if (regcomp + (&mask_rex, "(0x[0-9a-fA-F]*) *([_a-zA-Z0-9]*)", REG_EXTENDED)) { + fprintf(stderr, "Failed to compile regular expression\n"); + return -1; + } + file = fopen(filename, "r"); + if (file == NULL) { + fprintf(stderr, "Failed to open: %s\n", filename); + return -1; + } + fseek(file, 0, SEEK_END); + end = ftell(file); + fseek(file, 0, SEEK_SET); + + /* get header */ + if (fgets(buf, 1024, file) == NULL) + return -1; + + /* first line will contain the last register + * and gpu name */ + sscanf(buf, "%s %s", gpu_name, last_reg_s); + t->gpu_prefix = gpu_name; + last_reg = strtol(last_reg_s, NULL, 16); + + do { + if (fgets(buf, 1024, file) == NULL) + return -1; + len = strlen(buf); + if (ftell(file) == end) + done = 1; + if (len) { + r = regexec(&mask_rex, buf, 4, match, 0); + if (r == REG_NOMATCH) { + } else if (r) { + fprintf(stderr, + "Error matching regular expression %d in %s\n", + r, filename); + return -1; + } else { + buf[match[0].rm_eo] = 0; + buf[match[1].rm_eo] = 0; + buf[match[2].rm_eo] = 0; + o = strtol(&buf[match[1].rm_so], NULL, 16); + offset = offset_new(o); + table_offset_add(t, offset); + if (o > t->offset_max) + t->offset_max = o; + } + } + } while (!done); + fclose(file); + if (t->offset_max < last_reg) + t->offset_max = last_reg; + return table_build(t); } int main(int argc, char *argv[]) { - struct table t; - - if (argc != 2) { - fprintf(stderr, "Usage: %s \n", - argv[0]); - exit(1); - } - table_init(&t); - if (parser_auth(&t, argv[1])) { - fprintf(stderr, "Failed to parse file %s\n", argv[1]); - return -1; - } - table_print(&t); - return 0; + struct table t; + + if (argc != 2) { + fprintf(stderr, "Usage: %s \n", argv[0]); + exit(1); + } + table_init(&t); + if (parser_auth(&t, argv[1])) { + fprintf(stderr, "Failed to parse file %s\n", argv[1]); + return -1; + } + table_print(&t); + return 0; } diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300 index b4bd5b6..16f8f38 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/r300 +++ b/drivers/gpu/drm/radeon/reg_srcs/r300 @@ -153,7 +153,7 @@ r300 0x4f60 0x42A4 SU_POLY_OFFSET_FRONT_SCALE 0x42A8 SU_POLY_OFFSET_FRONT_OFFSET 0x42AC SU_POLY_OFFSET_BACK_SCALE -0x42B0 SU_POLY_OFFSET_BACK_OFFSET +0x42B0 SU_POLY_OFFSET_BACK_OFFSET 0x42B4 SU_POLY_OFFSET_ENABLE 0x42B8 SU_CULL_MODE 0x42C0 SU_DEPTH_SCALE diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515 index d1fcf38..7432df7 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/rv515 +++ b/drivers/gpu/drm/radeon/reg_srcs/rv515 @@ -186,7 +186,7 @@ rv515 0x6d40 0x42A4 SU_POLY_OFFSET_FRONT_SCALE 0x42A8 SU_POLY_OFFSET_FRONT_OFFSET 0x42AC SU_POLY_OFFSET_BACK_SCALE -0x42B0 SU_POLY_OFFSET_BACK_OFFSET +0x42B0 SU_POLY_OFFSET_BACK_OFFSET 0x42B4 SU_POLY_OFFSET_ENABLE 0x42B8 SU_CULL_MODE 0x42C0 SU_DEPTH_SCALE -- cgit v0.10.2 From e67aae79f93d9584aaa24d2a2c76383e9d588f98 Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Thu, 27 Aug 2009 10:18:29 +0200 Subject: drm/crtc_helper: replace modeset fail path with something simpler - The previous system was not very transparent, nor flexible. - This is needed to be able to fix a few bugs in the mechanism. Signed-off-by: Maarten Maathuis Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index a06c5f5..a3837b3 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -704,13 +704,12 @@ EXPORT_SYMBOL(drm_crtc_helper_set_mode); int drm_crtc_helper_set_config(struct drm_mode_set *set) { struct drm_device *dev; - struct drm_crtc **save_crtcs, *new_crtc; - struct drm_encoder **save_encoders, *new_encoder; + struct drm_crtc *save_crtcs, *new_crtc, *crtc; + struct drm_encoder *save_encoders, *new_encoder, *encoder; struct drm_framebuffer *old_fb = NULL; - bool save_enabled; bool mode_changed = false; /* if true do a full mode set */ bool fb_changed = false; /* if true and !mode_changed just do a flip */ - struct drm_connector *connector; + struct drm_connector *save_connectors, *connector; int count = 0, ro, fail = 0; struct drm_crtc_helper_funcs *crtc_funcs; int ret = 0; @@ -735,25 +734,47 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) dev = set->crtc->dev; - /* save previous config */ - save_enabled = set->crtc->enabled; - - /* - * We do mode_config.num_connectors here since we'll look at the - * CRTC and encoder associated with each connector later. - */ - save_crtcs = kzalloc(dev->mode_config.num_connector * - sizeof(struct drm_crtc *), GFP_KERNEL); + /* Allocate space for the backup of all (non-pointer) crtc, encoder and + * connector data. */ + save_crtcs = kzalloc(dev->mode_config.num_crtc * + sizeof(struct drm_crtc), GFP_KERNEL); if (!save_crtcs) return -ENOMEM; - save_encoders = kzalloc(dev->mode_config.num_connector * - sizeof(struct drm_encoders *), GFP_KERNEL); + save_encoders = kzalloc(dev->mode_config.num_encoder * + sizeof(struct drm_encoder), GFP_KERNEL); if (!save_encoders) { kfree(save_crtcs); return -ENOMEM; } + save_connectors = kzalloc(dev->mode_config.num_connector * + sizeof(struct drm_connector), GFP_KERNEL); + if (!save_connectors) { + kfree(save_crtcs); + kfree(save_encoders); + return -ENOMEM; + } + + /* Copy data. Note that driver private data is not affected. + * Should anything bad happen only the expected state is + * restored, not the drivers personal bookkeeping. + */ + count = 0; + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + save_crtcs[count++] = *crtc; + } + + count = 0; + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + save_encoders[count++] = *encoder; + } + + count = 0; + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + save_connectors[count++] = *connector; + } + /* We should be able to check here if the fb has the same properties * and then just flip_or_move it */ if (set->crtc->fb != set->fb) { @@ -786,7 +807,6 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) list_for_each_entry(connector, &dev->mode_config.connector_list, head) { struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; - save_encoders[count++] = connector->encoder; new_encoder = connector->encoder; for (ro = 0; ro < set->num_connectors; ro++) { if (set->connectors[ro] == connector) { @@ -809,7 +829,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) if (fail) { ret = -EINVAL; - goto fail_no_encoder; + goto fail; } count = 0; @@ -817,8 +837,6 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) if (!connector->encoder) continue; - save_crtcs[count++] = connector->encoder->crtc; - if (connector->encoder->crtc == set->crtc) new_crtc = NULL; else @@ -833,7 +851,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) if (new_crtc && !drm_encoder_crtc_ok(connector->encoder, new_crtc)) { ret = -EINVAL; - goto fail_set_mode; + goto fail; } if (new_crtc != connector->encoder->crtc) { DRM_DEBUG_KMS("crtc changed, full mode switch\n"); @@ -862,7 +880,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) DRM_ERROR("failed to set mode on crtc %p\n", set->crtc); ret = -EINVAL; - goto fail_set_mode; + goto fail; } /* TODO are these needed? */ set->crtc->desired_x = set->x; @@ -877,30 +895,34 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) ret = crtc_funcs->mode_set_base(set->crtc, set->x, set->y, old_fb); if (ret != 0) - goto fail_set_mode; + goto fail; } + kfree(save_connectors); kfree(save_encoders); kfree(save_crtcs); return 0; -fail_set_mode: - set->crtc->enabled = save_enabled; - set->crtc->fb = old_fb; +fail: + /* Restore all previous data. */ count = 0; - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - if (!connector->encoder) - continue; + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + *crtc = save_crtcs[count++]; + } - connector->encoder->crtc = save_crtcs[count++]; + count = 0; + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + *encoder = save_encoders[count++]; } -fail_no_encoder: - kfree(save_crtcs); + count = 0; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - connector->encoder = save_encoders[count++]; + *connector = save_connectors[count++]; } + + kfree(save_connectors); kfree(save_encoders); + kfree(save_crtcs); return ret; } EXPORT_SYMBOL(drm_crtc_helper_set_config); -- cgit v0.10.2 From f380ef86916904e4b79f7bec599deb51057b2d0c Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Wed, 19 Aug 2009 00:56:44 +0200 Subject: drm/crtc_helper: place drm_helper_encoder_in_use() in the header file - The symbol was already exported. Signed-off-by: Maarten Maathuis Signed-off-by: Dave Airlie diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h index 6769ff6..e44a4f8 100644 --- a/include/drm/drm_crtc_helper.h +++ b/include/drm/drm_crtc_helper.h @@ -98,6 +98,7 @@ extern bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb); extern bool drm_helper_crtc_in_use(struct drm_crtc *crtc); +extern bool drm_helper_encoder_in_use(struct drm_encoder *encoder); extern void drm_helper_connector_dpms(struct drm_connector *connector, int mode); -- cgit v0.10.2 From ff846ab7f76ffecba4f0bef026163d2a2364d7d0 Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Wed, 19 Aug 2009 00:56:45 +0200 Subject: drm/crtc_helper: NULL encoder->crtc when switching encoders - Previously the old encoder would be called during modeset and without a connector bad things happened. Signed-off-by: Maarten Maathuis Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index a3837b3..205349e 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -823,6 +823,10 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) if (new_encoder != connector->encoder) { DRM_DEBUG_KMS("encoder changed, full mode switch\n"); mode_changed = true; + /* If the encoder is reused for another connector, then + * the appropriate crtc will be set later. + */ + connector->encoder->crtc = NULL; connector->encoder = new_encoder; } } -- cgit v0.10.2 From 1ae70072f0699916c1a77a9bacad958ee46f7395 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Sat, 29 Aug 2009 22:20:34 +0200 Subject: drm: dereference of tmp in drm_proc_create_files() tmp allocation may fail, prevent a dereference. Signed-off-by: Roel Kluin Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_proc.c b/drivers/gpu/drm/drm_proc.c index bbd4b3d..dc967af 100644 --- a/drivers/gpu/drm/drm_proc.c +++ b/drivers/gpu/drm/drm_proc.c @@ -106,6 +106,10 @@ int drm_proc_create_files(struct drm_info_list *files, int count, continue; tmp = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); + if (tmp == NULL) { + ret = -1; + goto fail; + } ent = create_proc_entry(files[i].name, S_IFREG | S_IRUGO, root); if (!ent) { DRM_ERROR("Cannot create /proc/dri/%s/%s\n", -- cgit v0.10.2 From 70967ab9c0c9017645d167d33675eab996633631 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Sat, 29 Aug 2009 14:53:51 +0100 Subject: radeon: Use request_firmware() Loosely based on a patch by Jaswinder Singh Rajput . KMS support by Dave Airlie . For Radeon 100- to 500-series, firmware blobs look like: struct { __be32 datah; __be32 datal; } cp_ucode[256]; For Radeon 600-series, there are two separate firmware blobs: __be32 me_ucode[PM4_UCODE_SIZE * 3]; __be32 pfp_ucode[PFP_UCODE_SIZE]; For Radeon 700-series, likewise: __be32 me_ucode[R700_PM4_UCODE_SIZE]; __be32 pfp_ucode[R700_PFP_UCODE_SIZE]; Signed-off-by: Ben Hutchings Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index a07abb8..ebafad1 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -50,6 +50,7 @@ config DRM_RADEON select FB_CFB_IMAGEBLIT select FB select FRAMEBUFFER_CONSOLE if !EMBEDDED + select FW_LOADER help Choose this option if you have an ATI Radeon graphics card. There are both PCI and AGP versions. You don't need to choose this to diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 90ff8e0..639d5b2 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -29,9 +29,27 @@ #include "drmP.h" #include "drm.h" #include "radeon_drm.h" -#include "radeon_microcode.h" #include "radeon_reg.h" #include "radeon.h" +#include +#include + +/* Firmware Names */ +#define FIRMWARE_R100 "radeon/R100_cp.bin" +#define FIRMWARE_R200 "radeon/R200_cp.bin" +#define FIRMWARE_R300 "radeon/R300_cp.bin" +#define FIRMWARE_R420 "radeon/R420_cp.bin" +#define FIRMWARE_RS690 "radeon/RS690_cp.bin" +#define FIRMWARE_RS600 "radeon/RS600_cp.bin" +#define FIRMWARE_R520 "radeon/R520_cp.bin" + +MODULE_FIRMWARE(FIRMWARE_R100); +MODULE_FIRMWARE(FIRMWARE_R200); +MODULE_FIRMWARE(FIRMWARE_R300); +MODULE_FIRMWARE(FIRMWARE_R420); +MODULE_FIRMWARE(FIRMWARE_RS690); +MODULE_FIRMWARE(FIRMWARE_RS600); +MODULE_FIRMWARE(FIRMWARE_R520); /* This files gather functions specifics to: * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 @@ -478,33 +496,33 @@ void r100_ring_start(struct radeon_device *rdev) radeon_ring_unlock_commit(rdev); } -static void r100_cp_load_microcode(struct radeon_device *rdev) + +/* Load the microcode for the CP */ +static int r100_cp_init_microcode(struct radeon_device *rdev) { - int i; + struct platform_device *pdev; + const char *fw_name = NULL; + int err; - if (r100_gui_wait_for_idle(rdev)) { - printk(KERN_WARNING "Failed to wait GUI idle while " - "programming pipes. Bad things might happen.\n"); - } + DRM_DEBUG("\n"); - WREG32(RADEON_CP_ME_RAM_ADDR, 0); + pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); + err = IS_ERR(pdev); + if (err) { + printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); + return -EINVAL; + } if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || (rdev->family == CHIP_RS200)) { DRM_INFO("Loading R100 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R100; } else if ((rdev->family == CHIP_R200) || (rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280) || (rdev->family == CHIP_RS300)) { DRM_INFO("Loading R200 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R200; } else if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350) || (rdev->family == CHIP_RV350) || @@ -512,31 +530,19 @@ static void r100_cp_load_microcode(struct radeon_device *rdev) (rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) { DRM_INFO("Loading R300 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R300; } else if ((rdev->family == CHIP_R420) || (rdev->family == CHIP_R423) || (rdev->family == CHIP_RV410)) { DRM_INFO("Loading R400 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R420; } else if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { DRM_INFO("Loading RS690/RS740 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]); - } + fw_name = FIRMWARE_RS690; } else if (rdev->family == CHIP_RS600) { DRM_INFO("Loading RS600 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]); - } + fw_name = FIRMWARE_RS600; } else if ((rdev->family == CHIP_RV515) || (rdev->family == CHIP_R520) || (rdev->family == CHIP_RV530) || @@ -544,9 +550,43 @@ static void r100_cp_load_microcode(struct radeon_device *rdev) (rdev->family == CHIP_RV560) || (rdev->family == CHIP_RV570)) { DRM_INFO("Loading R500 Microcode\n"); - for (i = 0; i < 256; i++) { - WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]); - WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]); + fw_name = FIRMWARE_R520; + } + + err = request_firmware(&rdev->fw, fw_name, &pdev->dev); + platform_device_unregister(pdev); + if (err) { + printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", + fw_name); + } else if (rdev->fw->size % 8) { + printk(KERN_ERR + "radeon_cp: Bogus length %zu in firmware \"%s\"\n", + rdev->fw->size, fw_name); + err = -EINVAL; + release_firmware(rdev->fw); + rdev->fw = NULL; + } + return err; +} +static void r100_cp_load_microcode(struct radeon_device *rdev) +{ + const __be32 *fw_data; + int i, size; + + if (r100_gui_wait_for_idle(rdev)) { + printk(KERN_WARNING "Failed to wait GUI idle while " + "programming pipes. Bad things might happen.\n"); + } + + if (rdev->fw) { + size = rdev->fw->size / 4; + fw_data = (const __be32 *)&rdev->fw->data[0]; + WREG32(RADEON_CP_ME_RAM_ADDR, 0); + for (i = 0; i < size; i += 2) { + WREG32(RADEON_CP_ME_RAM_DATAH, + be32_to_cpup(&fw_data[i])); + WREG32(RADEON_CP_ME_RAM_DATAL, + be32_to_cpup(&fw_data[i + 1])); } } } @@ -585,6 +625,15 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) } else { DRM_INFO("radeon: cp idle (0x%08X)\n", tmp); } + + if (!rdev->fw) { + r = r100_cp_init_microcode(rdev); + if (r) { + DRM_ERROR("Failed to load firmware!\n"); + return r; + } + } + /* Align ring size */ rb_bufsz = drm_order(ring_size / 8); ring_size = (1 << (rb_bufsz + 1)) * 4; diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c index 20f1790..8327912 100644 --- a/drivers/gpu/drm/radeon/r600_cp.c +++ b/drivers/gpu/drm/radeon/r600_cp.c @@ -31,7 +31,32 @@ #include "radeon_drm.h" #include "radeon_drv.h" -#include "r600_microcode.h" +#define PFP_UCODE_SIZE 576 +#define PM4_UCODE_SIZE 1792 +#define R700_PFP_UCODE_SIZE 848 +#define R700_PM4_UCODE_SIZE 1360 + +/* Firmware Names */ +MODULE_FIRMWARE("radeon/R600_pfp.bin"); +MODULE_FIRMWARE("radeon/R600_me.bin"); +MODULE_FIRMWARE("radeon/RV610_pfp.bin"); +MODULE_FIRMWARE("radeon/RV610_me.bin"); +MODULE_FIRMWARE("radeon/RV630_pfp.bin"); +MODULE_FIRMWARE("radeon/RV630_me.bin"); +MODULE_FIRMWARE("radeon/RV620_pfp.bin"); +MODULE_FIRMWARE("radeon/RV620_me.bin"); +MODULE_FIRMWARE("radeon/RV635_pfp.bin"); +MODULE_FIRMWARE("radeon/RV635_me.bin"); +MODULE_FIRMWARE("radeon/RV670_pfp.bin"); +MODULE_FIRMWARE("radeon/RV670_me.bin"); +MODULE_FIRMWARE("radeon/RS780_pfp.bin"); +MODULE_FIRMWARE("radeon/RS780_me.bin"); +MODULE_FIRMWARE("radeon/RV770_pfp.bin"); +MODULE_FIRMWARE("radeon/RV770_me.bin"); +MODULE_FIRMWARE("radeon/RV730_pfp.bin"); +MODULE_FIRMWARE("radeon/RV730_me.bin"); +MODULE_FIRMWARE("radeon/RV710_pfp.bin"); +MODULE_FIRMWARE("radeon/RV710_me.bin"); # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) @@ -275,11 +300,93 @@ static void r600_vm_init(struct drm_device *dev) r600_vm_flush_gart_range(dev); } -/* load r600 microcode */ +static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv) +{ + struct platform_device *pdev; + const char *chip_name; + size_t pfp_req_size, me_req_size; + char fw_name[30]; + int err; + + pdev = platform_device_register_simple("r600_cp", 0, NULL, 0); + err = IS_ERR(pdev); + if (err) { + printk(KERN_ERR "r600_cp: Failed to register firmware\n"); + return -EINVAL; + } + + switch (dev_priv->flags & RADEON_FAMILY_MASK) { + case CHIP_R600: chip_name = "R600"; break; + case CHIP_RV610: chip_name = "RV610"; break; + case CHIP_RV630: chip_name = "RV630"; break; + case CHIP_RV620: chip_name = "RV620"; break; + case CHIP_RV635: chip_name = "RV635"; break; + case CHIP_RV670: chip_name = "RV670"; break; + case CHIP_RS780: + case CHIP_RS880: chip_name = "RS780"; break; + case CHIP_RV770: chip_name = "RV770"; break; + case CHIP_RV730: + case CHIP_RV740: chip_name = "RV730"; break; + case CHIP_RV710: chip_name = "RV710"; break; + default: BUG(); + } + + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { + pfp_req_size = R700_PFP_UCODE_SIZE * 4; + me_req_size = R700_PM4_UCODE_SIZE * 4; + } else { + pfp_req_size = PFP_UCODE_SIZE * 4; + me_req_size = PM4_UCODE_SIZE * 12; + } + + DRM_INFO("Loading %s CP Microcode\n", chip_name); + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); + err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev); + if (err) + goto out; + if (dev_priv->pfp_fw->size != pfp_req_size) { + printk(KERN_ERR + "r600_cp: Bogus length %zu in firmware \"%s\"\n", + dev_priv->pfp_fw->size, fw_name); + err = -EINVAL; + goto out; + } + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); + err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); + if (err) + goto out; + if (dev_priv->me_fw->size != me_req_size) { + printk(KERN_ERR + "r600_cp: Bogus length %zu in firmware \"%s\"\n", + dev_priv->me_fw->size, fw_name); + err = -EINVAL; + } +out: + platform_device_unregister(pdev); + + if (err) { + if (err != -EINVAL) + printk(KERN_ERR + "r600_cp: Failed to load firmware \"%s\"\n", + fw_name); + release_firmware(dev_priv->pfp_fw); + dev_priv->pfp_fw = NULL; + release_firmware(dev_priv->me_fw); + dev_priv->me_fw = NULL; + } + return err; +} + static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) { + const __be32 *fw_data; int i; + if (!dev_priv->me_fw || !dev_priv->pfp_fw) + return; + r600_do_cp_stop(dev_priv); RADEON_WRITE(R600_CP_RB_CNTL, @@ -292,115 +399,18 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) DRM_UDELAY(15000); RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); + fw_data = (const __be32 *)dev_priv->me_fw->data; RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); + for (i = 0; i < PM4_UCODE_SIZE * 3; i++) + RADEON_WRITE(R600_CP_ME_RAM_DATA, + be32_to_cpup(fw_data++)); - if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) { - DRM_INFO("Loading R600 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - R600_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - R600_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - R600_cp_microcode[i][2]); - } - - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading R600 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) { - DRM_INFO("Loading RV610 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV610_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV610_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV610_cp_microcode[i][2]); - } - - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV610 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { - DRM_INFO("Loading RV630 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV630_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV630_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV630_cp_microcode[i][2]); - } - - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV630 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) { - DRM_INFO("Loading RV620 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV620_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV620_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV620_cp_microcode[i][2]); - } - - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV620 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { - DRM_INFO("Loading RV635 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV635_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV635_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV635_cp_microcode[i][2]); - } - - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV635 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) { - DRM_INFO("Loading RV670 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV670_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV670_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RV670_cp_microcode[i][2]); - } - - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV670 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { - DRM_INFO("Loading RS780/RS880 CP Microcode\n"); - for (i = 0; i < PM4_UCODE_SIZE; i++) { - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RS780_cp_microcode[i][0]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RS780_cp_microcode[i][1]); - RADEON_WRITE(R600_CP_ME_RAM_DATA, - RS780_cp_microcode[i][2]); - } + fw_data = (const __be32 *)dev_priv->pfp_fw->data; + RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); + for (i = 0; i < PFP_UCODE_SIZE; i++) + RADEON_WRITE(R600_CP_PFP_UCODE_DATA, + be32_to_cpup(fw_data++)); - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RS780/RS880 PFP Microcode\n"); - for (i = 0; i < PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]); - } RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); @@ -459,11 +469,14 @@ static void r700_vm_init(struct drm_device *dev) r600_vm_flush_gart_range(dev); } -/* load r600 microcode */ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) { + const __be32 *fw_data; int i; + if (!dev_priv->me_fw || !dev_priv->pfp_fw) + return; + r600_do_cp_stop(dev_priv); RADEON_WRITE(R600_CP_RB_CNTL, @@ -476,48 +489,18 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) DRM_UDELAY(15000); RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); + fw_data = (const __be32 *)dev_priv->pfp_fw->data; + RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); + for (i = 0; i < R700_PFP_UCODE_SIZE; i++) + RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); + RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) { - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV770/RV790 PFP Microcode\n"); - for (i = 0; i < R700_PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]); - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - DRM_INFO("Loading RV770/RV790 CP Microcode\n"); - for (i = 0; i < R700_PM4_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]); - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) || - ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) { - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV730/RV740 PFP Microcode\n"); - for (i = 0; i < R700_PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]); - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - DRM_INFO("Loading RV730/RV740 CP Microcode\n"); - for (i = 0; i < R700_PM4_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]); - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) { - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV710 PFP Microcode\n"); - for (i = 0; i < R700_PFP_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]); - RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - DRM_INFO("Loading RV710 CP Microcode\n"); - for (i = 0; i < R700_PM4_UCODE_SIZE; i++) - RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]); - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); + fw_data = (const __be32 *)dev_priv->me_fw->data; + RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); + for (i = 0; i < R700_PM4_UCODE_SIZE; i++) + RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); + RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - } RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); @@ -2147,6 +2130,14 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, r600_vm_init(dev); } + if (!dev_priv->me_fw || !dev_priv->pfp_fw) { + int err = r600_cp_init_microcode(dev_priv); + if (err) { + DRM_ERROR("Failed to load firmware!\n"); + r600_do_cleanup_cp(dev); + return err; + } + } if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) r700_cp_load_microcode(dev_priv); else diff --git a/drivers/gpu/drm/radeon/r600_microcode.h b/drivers/gpu/drm/radeon/r600_microcode.h deleted file mode 100644 index 778c8b4..0000000 --- a/drivers/gpu/drm/radeon/r600_microcode.h +++ /dev/null @@ -1,23297 +0,0 @@ -/* - * Copyright 2008-2009 Advanced Micro Devices, Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef R600_MICROCODE_H -#define R600_MICROCODE_H - -static const int ME_JUMP_TABLE_START = 1764; -static const int ME_JUMP_TABLE_END = 1792; - -#define PFP_UCODE_SIZE 576 -#define PM4_UCODE_SIZE 1792 -#define R700_PFP_UCODE_SIZE 848 -#define R700_PM4_UCODE_SIZE 1360 - -static const u32 R600_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x614 }, - { 0x00000000, 0x00600000, 0x5b2 }, - { 0x00000000, 0x00600000, 0x5c5 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000020, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000021, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x0000001d, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x0000001d, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000030, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x00000010, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000030, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000032, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x0000002d, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x080 }, - { 0x0000002e, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x081 }, - { 0x00000000, 0x00400000, 0x087 }, - { 0x0000002d, 0x00203623, 0x000 }, - { 0x0000002e, 0x00203624, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x087 }, - { 0x00000000, 0x00600000, 0x5ed }, - { 0x00000000, 0x00600000, 0x5e1 }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08a }, - { 0x00000018, 0xc0403620, 0x090 }, - { 0x00000000, 0x2ee00000, 0x08e }, - { 0x00000000, 0x2ce00000, 0x08d }, - { 0x00000002, 0x00400e2d, 0x08f }, - { 0x00000003, 0x00400e2d, 0x08f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000018, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x095 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x09d }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09b }, - { 0x00000000, 0x2ce00000, 0x09a }, - { 0x00000002, 0x00400e2d, 0x09c }, - { 0x00000003, 0x00400e2d, 0x09c }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a4 }, - { 0x0000001c, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x0000001b, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0db }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x28c }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x128 }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0c5 }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0d6 }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0d4 }, - { 0x00000013, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0cf }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ce }, - { 0x00003f00, 0x00400c11, 0x0d0 }, - { 0x00001f00, 0x00400c11, 0x0d0 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0d6 }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00284a22, 0x000 }, - { 0x00000030, 0x00200e2d, 0x000 }, - { 0x0000002e, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e3 }, - { 0x00000000, 0x00600000, 0x5e7 }, - { 0x00000000, 0x00400000, 0x0e4 }, - { 0x00000000, 0x00600000, 0x5ea }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x0000001d, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f1 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f1 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x0000001a, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f6 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x104 }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000013, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0fd }, - { 0xffffffff, 0x00404811, 0x104 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x100 }, - { 0x0000ffff, 0x00404811, 0x104 }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x103 }, - { 0x000000ff, 0x00404811, 0x104 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000019, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x10d }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000019, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x114 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x110 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x127 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x614 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x00000004, 0x00404c11, 0x12e }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x2fe }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x00000000, 0x00600000, 0x151 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2a4 }, - { 0x0001a1fd, 0x00604411, 0x2c9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x138 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x2fe }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x151 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2a4 }, - { 0x0001a1fd, 0x00604411, 0x2c9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x149 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x17c }, - { 0x00000000, 0x00600000, 0x18d }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x189 }, - { 0x00000000, 0x00600000, 0x2a4 }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x28c }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x173 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x16f }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x184 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000013, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2e4 }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x165 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x2fe }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x181 }, - { 0x0000001b, 0xc0203620, 0x000 }, - { 0x0000001c, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x19f }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x188 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000032, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x00000011, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x128 }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x0000001b, 0x00600e2d, 0x1aa }, - { 0x0000001c, 0x00600e2d, 0x1aa }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x0000001d, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1a6 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000020, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x2fe }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000019, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1cd }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1c9 }, - { 0x00000000, 0x00600000, 0x1d6 }, - { 0x00000001, 0x00531e27, 0x1c5 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1be }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1d6 }, - { 0x00000001, 0x00531e27, 0x1d2 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2a4 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e5 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x1f2 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x1f2 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x2fe }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2a4 }, - { 0x0001a1fd, 0x00604411, 0x2c9 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x206 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x1ff }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x5c5 }, - { 0x00000000, 0x0040040f, 0x200 }, - { 0x00000000, 0x00600000, 0x5b2 }, - { 0x00000000, 0x00600000, 0x5c5 }, - { 0x00000210, 0x00600411, 0x2fe }, - { 0x00000000, 0x00600000, 0x18d }, - { 0x00000000, 0x00600000, 0x189 }, - { 0x00000000, 0x00600000, 0x2a4 }, - { 0x00000000, 0x00600000, 0x28c }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x21f }, - { 0x00000000, 0xc0404800, 0x21c }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2e4 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x5b2 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x235 }, - { 0x0000001a, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x0000001a, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x23a }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x2fe }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x265 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x253 }, - { 0x00000018, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x248 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x24b }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000018, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x250 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x253 }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2aa }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x25b }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x25a }, - { 0x00000016, 0x00404811, 0x25f }, - { 0x00000018, 0x00404811, 0x25f }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x25e }, - { 0x00000017, 0x00404811, 0x25f }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2d2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x23f }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x614 }, - { 0x00000000, 0x00600000, 0x5b2 }, - { 0x00000000, 0xc0600000, 0x28c }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x00000034, 0x00201a2d, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x00000033, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x27b }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000034, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x128 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x286 }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000024, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000032, 0x00203622, 0x000 }, - { 0x00000031, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000029, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000029, 0x00203627, 0x000 }, - { 0x0000002a, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x0000002a, 0x00203627, 0x000 }, - { 0x0000002b, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x0000002b, 0x00203627, 0x000 }, - { 0x0000002c, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x0000002c, 0x00803627, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x0000002a, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x0000002b, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x0000002c, 0x00803627, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00203628, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2c5 }, - { 0x00000000, 0x00400000, 0x2c2 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00203628, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2c2 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2c5 }, - { 0x0000002b, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2c5 }, - { 0x00000029, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2c5 }, - { 0x0000002c, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2c5 }, - { 0x0000002a, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2c5 }, - { 0x00000000, 0x00600000, 0x5ed }, - { 0x00000000, 0x00600000, 0x29e }, - { 0x00000000, 0x00400000, 0x2c7 }, - { 0x00000000, 0x00600000, 0x29e }, - { 0x00000000, 0x00600000, 0x5e4 }, - { 0x00000000, 0x00400000, 0x2c7 }, - { 0x00000000, 0x00600000, 0x290 }, - { 0x00000000, 0x00400000, 0x2c7 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000023, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x0000001d, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x301 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x0000001a, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x5c5 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x334 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x614 }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x33d }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x351 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000016, 0x00604811, 0x35e }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x355 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00404811, 0x349 }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x349 }, - { 0x00002104, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x00000035, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x360 }, - { 0x00000035, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x376 }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x380 }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x38c }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x398 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x398 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x39a }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x39f }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000015, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x614 }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x382 }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x614 }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x38e }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00404811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000016, 0x00604811, 0x35e }, - { 0x00000016, 0x00404811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3b9 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x614 }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3ab }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3be }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x614 }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3cc }, - { 0x00000000, 0xc0401800, 0x3cf }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x614 }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3d2 }, - { 0x00000000, 0xc0401c00, 0x3d5 }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x614 }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x3fd }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3e2 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3ea }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x3fd }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x3fd }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3e5 }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3e5 }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3e5 }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3e5 }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3e5 }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3e5 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0018f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x614 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x42e }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x43c }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x444 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x614 }, - { 0x00000000, 0x00400000, 0x44d }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x1ac00000, 0x449 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x44c }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x454 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x46d }, - { 0x00000000, 0x00400000, 0x47a }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x459 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x46d }, - { 0x00000000, 0x00400000, 0x47a }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x45e }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x46d }, - { 0x00000000, 0x00400000, 0x47a }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x463 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46d }, - { 0x00000000, 0x00400000, 0x47a }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x468 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x46d }, - { 0x00000000, 0x00400000, 0x47a }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46d }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x46d }, - { 0x00000000, 0x00400000, 0x47a }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x477 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x480 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x43c }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x48a }, - { 0x00040000, 0xc0494a20, 0x48b }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x497 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x493 }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x491 }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4ae }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1ac00000, 0x4a9 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x4ac }, - { 0x00000000, 0x00400000, 0x4b2 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x614 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4b9 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x614 }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4bb }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x4eb }, - { 0x00000035, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4da }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4ce }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000036, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x491 }, - { 0x00000035, 0xc0203620, 0x000 }, - { 0x00000036, 0xc0403620, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0xe0000000, 0xc0484a20, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x4f2 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x4f6 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x50b }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0x00000034, 0x00203623, 0x000 }, - { 0x00000032, 0x00203623, 0x000 }, - { 0x00000031, 0x00203623, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x0000002d, 0x00203623, 0x000 }, - { 0x0000002e, 0x00203623, 0x000 }, - { 0x0000001b, 0x00203623, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x0000002a, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x0000002c, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000033, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000027, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000028, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x00000026, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x602 }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x541 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x614 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x549 }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x55b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x549 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x614 }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x55b }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x54d }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x55b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x559 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1ac00000, 0x554 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x557 }, - { 0x00000000, 0x00401c10, 0x55b }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x55d }, - { 0x00000000, 0x00600000, 0x5a4 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56d }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x614 }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x56b }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x57d }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x614 }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x57b }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58d }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x614 }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58b }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x614 }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x599 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x59f }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5a4 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x5b7 }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x00000034, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x5bb }, - { 0x00000000, 0x00600000, 0x5a4 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x5bb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x0000217a, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x5e1 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000016, 0x00604811, 0x35e }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x614 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x5dc }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x0000001d, 0x00803627, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x0000001d, 0x00803627, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x0000001d, 0x00803627, 0x000 }, - { 0x0000001d, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x0000001d, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000016, 0x00604811, 0x35e }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0x00ffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x614 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x00000010, 0x00404c11, 0x5f9 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x00000025, 0x00200a2d, 0x000 }, - { 0x00000026, 0x00200e2d, 0x000 }, - { 0x00000027, 0x0020122d, 0x000 }, - { 0x00000028, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x612 }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x00000027, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x614 }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x617 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x2fe }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x19f }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000029, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x0000002c, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000002a, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000002b, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x013304ef, 0x059b0239, 0x000 }, - { 0x01b00159, 0x0425059b, 0x000 }, - { 0x021201f6, 0x02390142, 0x000 }, - { 0x0210022e, 0x0289022a, 0x000 }, - { 0x03c2059b, 0x059b059b, 0x000 }, - { 0x05cd05ce, 0x0308059b, 0x000 }, - { 0x059b05a0, 0x03090329, 0x000 }, - { 0x0313026b, 0x032b031d, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b052c, 0x059b059b, 0x000 }, - { 0x03a5059b, 0x04a2032d, 0x000 }, - { 0x04810433, 0x0423059b, 0x000 }, - { 0x04bb04ed, 0x042704c8, 0x000 }, - { 0x043304f4, 0x033a0365, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x05b905a2, 0x000 }, - { 0x059b059b, 0x0007059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x03e303d8, 0x03f303f1, 0x000 }, - { 0x03f903f5, 0x03f703fb, 0x000 }, - { 0x04070403, 0x040f040b, 0x000 }, - { 0x04170413, 0x041f041b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x059b059b, 0x059b059b, 0x000 }, - { 0x00020600, 0x06190006, 0x000 }, -}; - -static const u32 R600_pfp_microcode[] = { -0xd40071, -0xd40072, -0xca0400, -0xa00000, -0x7e828b, -0x800003, -0xca0400, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d4, -0xd5c01e, -0xca0800, -0x80001b, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000d, -0xc41838, -0xe4013e, -0xd4001e, -0x80000d, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800054, -0xd40073, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800002, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800002, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b9, -0xd4c01e, -0xc6083e, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800002, -0x062001, -0xc6083e, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x80007a, -0xd42013, -0xc6083e, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008e, -0x000000, -0xc41432, -0xc6183e, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800002, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xd40073, -0xe4015e, -0xd4001e, -0x8001b9, -0x062001, -0x0a2001, -0xd60074, -0xc40836, -0xc61040, -0x988007, -0xcc3835, -0x95010f, -0xd4001f, -0xd46062, -0x800002, -0xd42062, -0xcc1433, -0x8401bc, -0xd40070, -0xd5401e, -0x800002, -0xee001e, -0xca0c00, -0xca1000, -0xd4c01a, -0x8401bc, -0xd5001a, -0xcc0443, -0x35101f, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b9, -0xd4006d, -0x344401, -0xcc0c44, -0x98403a, -0xcc2c46, -0x958004, -0xcc0445, -0x8001b9, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f3, -0xcc1003, -0x98801b, -0x04380c, -0x8400f3, -0xcc1003, -0x988017, -0x043808, -0x8400f3, -0xcc1003, -0x988013, -0x043804, -0x8400f3, -0xcc1003, -0x988014, -0xcc1047, -0x9a8009, -0xcc1448, -0x9840da, -0xd4006d, -0xcc1844, -0xd5001a, -0xd5401a, -0x8000cc, -0xd5801a, -0x96c0d3, -0xd4006d, -0x8001b9, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800002, -0xec007f, -0x9ac0ca, -0xd4006d, -0x8001b9, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b9, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809c, -0xd4006d, -0x98409a, -0xd4006e, -0xcc0847, -0xcc0c48, -0xcc1044, -0xd4801a, -0xd4c01a, -0x800104, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d8, -0xca0c00, -0xd4401e, -0x800002, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800002, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bc, -0x000000, -0x8401bc, -0xd7806f, -0x800002, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902af, -0x7c738b, -0x8401bc, -0xd7806f, -0x800002, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984296, -0x000000, -0x800164, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800002, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc1049, -0x990004, -0xd40071, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800002, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x95001f, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x7d8380, -0xd5806f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0x8001b9, -0xd60074, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800002, -0xee001e, -0x800002, -0xee001f, -0xd4001f, -0x800002, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010174, -0x02017b, -0x030090, -0x040080, -0x050005, -0x060040, -0x070033, -0x08012f, -0x090047, -0x0a0037, -0x1001b7, -0x1700a4, -0x22013d, -0x23014c, -0x2000b5, -0x240128, -0x27004e, -0x28006b, -0x2a0061, -0x2b0053, -0x2f0066, -0x320088, -0x340182, -0x3c0159, -0x3f0073, -0x41018f, -0x440131, -0x550176, -0x56017d, -0x60000c, -0x610035, -0x620039, -0x630039, -0x640039, -0x650039, -0x660039, -0x670039, -0x68003b, -0x690042, -0x6a0049, -0x6b0049, -0x6c0049, -0x6d0049, -0x6e0049, -0x6f0049, -0x7301b7, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -0x000007, -}; - -static const u32 RV610_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x668 }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x662 }, - { 0x00000000, 0x00400000, 0x0eb }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f8 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f8 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0fd }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x104 }, - { 0xffffffff, 0x00404811, 0x10b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x107 }, - { 0x0000ffff, 0x00404811, 0x10b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x10a }, - { 0x000000ff, 0x00404811, 0x10b }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x112 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x114 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x11b }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x117 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x12e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000004, 0x00404c11, 0x135 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000001c, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x13c }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x147 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x158 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x18f }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ae00000, 0x181 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x186 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x186 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x182 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x197 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000011, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2fb }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x174 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x194 }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x19b }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000029, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x0000000f, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x12f }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x00000015, 0x00600e2d, 0x1bd }, - { 0x00000016, 0x00600e2d, 0x1bd }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b9 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000018, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000013, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e0 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1dc }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1d8 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1d1 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1e5 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2bb }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x205 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x205 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x219 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x212 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0x0040040f, 0x213 }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00000000, 0x00600000, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ae00000, 0x232 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x236 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x236 }, - { 0x00000000, 0xc0404800, 0x233 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2fb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24c }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x251 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x315 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x27c }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x26a }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x25f }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x262 }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x267 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x26a }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2c1 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x272 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x271 }, - { 0x00000016, 0x00404811, 0x276 }, - { 0x00000018, 0x00404811, 0x276 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x275 }, - { 0x00000017, 0x00404811, 0x276 }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2e9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x256 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0xc0600000, 0x2a3 }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x0000002b, 0x00201a2d, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x0000002a, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x292 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x12f }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x29d }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000001c, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000029, 0x00203622, 0x000 }, - { 0x00000028, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000021, 0x00203627, 0x000 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2dc }, - { 0x00000000, 0x00400000, 0x2d9 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2d9 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2dc }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000000, 0x00600000, 0x668 }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00600000, 0x65f }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2a7 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x0000001a, 0x00201e2d, 0x000 }, - { 0x0000001b, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000017, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x318 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x34b }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x354 }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x364 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00604802, 0x36e }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5c0 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x0000002c, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x370 }, - { 0x0000002c, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x386 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b1 }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b5 }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x39c }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x390 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x392 }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x39e }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x80000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000010, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3ae }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3ce }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3c0 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3d3 }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e1 }, - { 0x00000000, 0xc0401800, 0x3e4 }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x68d }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e7 }, - { 0x00000000, 0xc0401c00, 0x3ea }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x68d }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3f7 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3ff }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3fa }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3fa }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3fa }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3fa }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3fa }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3fa }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x01182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0218a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0318c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0418f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0518f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0618e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0718f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0818f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000030, 0x00200a2d, 0x000 }, - { 0x00000000, 0xc0290c40, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000018, 0x40210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x445 }, - { 0x00800000, 0xc0494a20, 0x446 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x44b }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x459 }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x461 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x68d }, - { 0x00000000, 0x00400000, 0x466 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00604805, 0x692 }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46d }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x472 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x477 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x47c }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x481 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x486 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x490 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x499 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x459 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x4a3 }, - { 0x00040000, 0xc0494a20, 0x4a4 }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x4b0 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x4ac }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4aa }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4c3 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x692 }, - { 0x00000000, 0x00400000, 0x4c7 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x68d }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4ce }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4d0 }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x500 }, - { 0x0000002c, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4ef }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4e3 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000002d, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4aa }, - { 0x0000002c, 0xc0203620, 0x000 }, - { 0x0000002d, 0xc0403620, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x505 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xb5000000, 0x00204411, 0x000 }, - { 0x00002000, 0x00204811, 0x000 }, - { 0xb6000000, 0x00204411, 0x000 }, - { 0x0000a000, 0x00204811, 0x000 }, - { 0xb7000000, 0x00204411, 0x000 }, - { 0x0000c000, 0x00204811, 0x000 }, - { 0xb8000000, 0x00204411, 0x000 }, - { 0x0000f8e0, 0x00204811, 0x000 }, - { 0xb9000000, 0x00204411, 0x000 }, - { 0x0000f880, 0x00204811, 0x000 }, - { 0xba000000, 0x00204411, 0x000 }, - { 0x0000e000, 0x00204811, 0x000 }, - { 0xbb000000, 0x00204411, 0x000 }, - { 0x0000f000, 0x00204811, 0x000 }, - { 0xbc000000, 0x00204411, 0x000 }, - { 0x0000f3fc, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x519 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x52e }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x00000028, 0x00203623, 0x000 }, - { 0x00000017, 0x00203623, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203623, 0x000 }, - { 0x00000015, 0x00203623, 0x000 }, - { 0x00000016, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x00000023, 0x00203623, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000002a, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x0000001f, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000020, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x0000001e, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x67b }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x566 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56e }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x572 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x57a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x692 }, - { 0x00000000, 0x00401c10, 0x57c }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x57e }, - { 0x00000000, 0x00600000, 0x5c9 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58f }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58d }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5a0 }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59e }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5b1 }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5af }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5be }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5c4 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c9 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5d0 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5e3 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5e3 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x68d }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x68d }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68d }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68d }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68d }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68d }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62c }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62c }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x605 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62b }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x60e }, - { 0x0004a003, 0x00604411, 0x68d }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x0004a010, 0x00604411, 0x68d }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62b }, - { 0x0004a011, 0x00604411, 0x68d }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x68d }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x68d }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x68d }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x68d }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x68d }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x68d }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x63d }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x63b }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x641 }, - { 0x00000000, 0x00600000, 0x5c9 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x641 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x62d }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x62d }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x656 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000010, 0x00404c11, 0x672 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x68b }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68d }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x690 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x692 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x695 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x01420502, 0x05c00250, 0x000 }, - { 0x01c30168, 0x043f05c0, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705c0, 0x05c005c0, 0x000 }, - { 0x0649064a, 0x031f05c0, 0x000 }, - { 0x05c005c5, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c00551, 0x05c005c0, 0x000 }, - { 0x03ba05c0, 0x04bb0344, 0x000 }, - { 0x049a0450, 0x043d05c0, 0x000 }, - { 0x04d005c0, 0x044104dd, 0x000 }, - { 0x04500507, 0x03510375, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x063f05c7, 0x000 }, - { 0x05c005c0, 0x000705c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05c005c0, 0x043805c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x00020679, 0x06970006, 0x000 }, -}; - -static const u32 RV610_pfp_microcode[] = { -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV620_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x668 }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x662 }, - { 0x00000000, 0x00400000, 0x0eb }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f8 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f8 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0fd }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x104 }, - { 0xffffffff, 0x00404811, 0x10b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x107 }, - { 0x0000ffff, 0x00404811, 0x10b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x10a }, - { 0x000000ff, 0x00404811, 0x10b }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x112 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x114 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x11b }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x117 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x12e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000004, 0x00404c11, 0x135 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000001c, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x13c }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x147 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x158 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x18f }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ae00000, 0x181 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x186 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x186 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x182 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x197 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000011, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2fb }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x174 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x194 }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x19b }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000029, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x0000000f, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x12f }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x00000015, 0x00600e2d, 0x1bd }, - { 0x00000016, 0x00600e2d, 0x1bd }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b9 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000018, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000013, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e0 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1dc }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1d8 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1d1 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1e5 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2bb }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x205 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x205 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x219 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x212 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0x0040040f, 0x213 }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00000000, 0x00600000, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ae00000, 0x232 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x236 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x236 }, - { 0x00000000, 0xc0404800, 0x233 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2fb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24c }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x251 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x315 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x27c }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x26a }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x25f }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x262 }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x267 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x26a }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2c1 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x272 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x271 }, - { 0x00000016, 0x00404811, 0x276 }, - { 0x00000018, 0x00404811, 0x276 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x275 }, - { 0x00000017, 0x00404811, 0x276 }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2e9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x256 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00000000, 0x00600000, 0x631 }, - { 0x00000000, 0xc0600000, 0x2a3 }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x0000002b, 0x00201a2d, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x0000002a, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x292 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x12f }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x29d }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000001c, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000029, 0x00203622, 0x000 }, - { 0x00000028, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000021, 0x00203627, 0x000 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2dc }, - { 0x00000000, 0x00400000, 0x2d9 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2d9 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2dc }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000000, 0x00600000, 0x668 }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00600000, 0x65f }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2a7 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x0000001a, 0x00201e2d, 0x000 }, - { 0x0000001b, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000017, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x318 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x645 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x34b }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x354 }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x364 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00604802, 0x36e }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5c0 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x0000002c, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x370 }, - { 0x0000002c, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x386 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b1 }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b5 }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x39c }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x390 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x392 }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x39e }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x80000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000010, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3ae }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3ce }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3c0 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3d3 }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e1 }, - { 0x00000000, 0xc0401800, 0x3e4 }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x68d }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e7 }, - { 0x00000000, 0xc0401c00, 0x3ea }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x68d }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3f7 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3ff }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3fa }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3fa }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3fa }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3fa }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3fa }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3fa }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x01182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0218a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0318c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0418f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0518f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0618e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0718f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0818f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000030, 0x00200a2d, 0x000 }, - { 0x00000000, 0xc0290c40, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000018, 0x40210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x445 }, - { 0x00800000, 0xc0494a20, 0x446 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x44b }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x459 }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x461 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x68d }, - { 0x00000000, 0x00400000, 0x466 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00604805, 0x692 }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46d }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x472 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x477 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x47c }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x481 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x486 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x486 }, - { 0x00000000, 0x00400000, 0x493 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x490 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x499 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x459 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x4a3 }, - { 0x00040000, 0xc0494a20, 0x4a4 }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x4b0 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x4ac }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4aa }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4c3 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x692 }, - { 0x00000000, 0x00400000, 0x4c7 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x68d }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4ce }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68d }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4d0 }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x500 }, - { 0x0000002c, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4ef }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4e3 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000002d, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4aa }, - { 0x0000002c, 0xc0203620, 0x000 }, - { 0x0000002d, 0xc0403620, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x505 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xb5000000, 0x00204411, 0x000 }, - { 0x00002000, 0x00204811, 0x000 }, - { 0xb6000000, 0x00204411, 0x000 }, - { 0x0000a000, 0x00204811, 0x000 }, - { 0xb7000000, 0x00204411, 0x000 }, - { 0x0000c000, 0x00204811, 0x000 }, - { 0xb8000000, 0x00204411, 0x000 }, - { 0x0000f8e0, 0x00204811, 0x000 }, - { 0xb9000000, 0x00204411, 0x000 }, - { 0x0000f880, 0x00204811, 0x000 }, - { 0xba000000, 0x00204411, 0x000 }, - { 0x0000e000, 0x00204811, 0x000 }, - { 0xbb000000, 0x00204411, 0x000 }, - { 0x0000f000, 0x00204811, 0x000 }, - { 0xbc000000, 0x00204411, 0x000 }, - { 0x0000f3fc, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x519 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x52e }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x00000028, 0x00203623, 0x000 }, - { 0x00000017, 0x00203623, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203623, 0x000 }, - { 0x00000015, 0x00203623, 0x000 }, - { 0x00000016, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x00000023, 0x00203623, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000002a, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x0000001f, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000020, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x0000001e, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x67b }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x566 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56e }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68d }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x572 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x57c }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x57a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x692 }, - { 0x00000000, 0x00401c10, 0x57c }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x57e }, - { 0x00000000, 0x00600000, 0x5c9 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58f }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58d }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5a0 }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59e }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5b1 }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5af }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68d }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5be }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5c4 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c9 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5d0 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5e3 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5e3 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x68d }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x68d }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68d }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68d }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68d }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68d }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62c }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62c }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x605 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62b }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x60e }, - { 0x0004a003, 0x00604411, 0x68d }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x613 }, - { 0x0004a010, 0x00604411, 0x68d }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62b }, - { 0x0004a011, 0x00604411, 0x68d }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x68d }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x68d }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x68d }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x68d }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x68d }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x68d }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x63d }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x63b }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68d }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x641 }, - { 0x00000000, 0x00600000, 0x5c9 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x641 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x62d }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x62d }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x656 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x68d }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x68c }, - { 0x00000010, 0x00404c11, 0x672 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x68b }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68d }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x690 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x692 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x695 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x01420502, 0x05c00250, 0x000 }, - { 0x01c30168, 0x043f05c0, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705c0, 0x05c005c0, 0x000 }, - { 0x0649064a, 0x031f05c0, 0x000 }, - { 0x05c005c5, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c00551, 0x05c005c0, 0x000 }, - { 0x03ba05c0, 0x04bb0344, 0x000 }, - { 0x049a0450, 0x043d05c0, 0x000 }, - { 0x04d005c0, 0x044104dd, 0x000 }, - { 0x04500507, 0x03510375, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x063f05c7, 0x000 }, - { 0x05c005c0, 0x000705c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05c005c0, 0x043805c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x05c005c0, 0x05c005c0, 0x000 }, - { 0x00020679, 0x06970006, 0x000 }, -}; - -static const u32 RV620_pfp_microcode[] = { -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV630_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x65f }, - { 0x00000000, 0x00400000, 0x0eb }, - { 0x00000000, 0x00600000, 0x662 }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f8 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f8 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0fd }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x104 }, - { 0xffffffff, 0x00404811, 0x10b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x107 }, - { 0x0000ffff, 0x00404811, 0x10b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x10a }, - { 0x000000ff, 0x00404811, 0x10b }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x112 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x114 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x11b }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x117 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x12e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000004, 0x00404c11, 0x135 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000001c, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x13c }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x147 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x158 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x18f }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ae00000, 0x181 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x186 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x186 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x182 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x197 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000011, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2fb }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x174 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x194 }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x19b }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000029, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x0000000f, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x12f }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x00000015, 0x00600e2d, 0x1bd }, - { 0x00000016, 0x00600e2d, 0x1bd }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b9 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000018, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000013, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e0 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1dc }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1d8 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1d1 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1e5 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2bb }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x205 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x205 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x219 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x212 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0x0040040f, 0x213 }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00000000, 0x00600000, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ae00000, 0x232 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x236 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x236 }, - { 0x00000000, 0xc0404800, 0x233 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2fb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24c }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x251 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x315 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x27c }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x26a }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x25f }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x262 }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x267 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x26a }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2c1 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x272 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x271 }, - { 0x00000016, 0x00404811, 0x276 }, - { 0x00000018, 0x00404811, 0x276 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x275 }, - { 0x00000017, 0x00404811, 0x276 }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2e9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x256 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0xc0600000, 0x2a3 }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x0000002b, 0x00201a2d, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x0000002a, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x292 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x12f }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x29d }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000001c, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000029, 0x00203622, 0x000 }, - { 0x00000028, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000021, 0x00203627, 0x000 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2dc }, - { 0x00000000, 0x00400000, 0x2d9 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2d9 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2dc }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2a7 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x0000001a, 0x00201e2d, 0x000 }, - { 0x0000001b, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000017, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x318 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x34b }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x354 }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x364 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00604802, 0x36e }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5bd }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x0000002c, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x370 }, - { 0x0000002c, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x386 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b1 }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b5 }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x39c }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x390 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x392 }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x39e }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x80000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000010, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3ae }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3ce }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3c0 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3d3 }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e1 }, - { 0x00000000, 0xc0401800, 0x3e4 }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x68a }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e7 }, - { 0x00000000, 0xc0401c00, 0x3ea }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x68a }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3f7 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3ff }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3fa }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3fa }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3fa }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3fa }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3fa }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3fa }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x01182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0218a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0318c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0418f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0518f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0618e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0718f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0818f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000030, 0x00200a2d, 0x000 }, - { 0x00000000, 0xc0290c40, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x448 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x456 }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x45e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x68a }, - { 0x00000000, 0x00400000, 0x463 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00604805, 0x68f }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46a }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46f }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x474 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x479 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x47e }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x483 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x48d }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x496 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x456 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x4a0 }, - { 0x00040000, 0xc0494a20, 0x4a1 }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x4ad }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x4a9 }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4a7 }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4c0 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x68f }, - { 0x00000000, 0x00400000, 0x4c4 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x68a }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4cb }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4cd }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x4fd }, - { 0x0000002c, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4ec }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4e0 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000002d, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4a7 }, - { 0x0000002c, 0xc0203620, 0x000 }, - { 0x0000002d, 0xc0403620, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x502 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xb5000000, 0x00204411, 0x000 }, - { 0x00002000, 0x00204811, 0x000 }, - { 0xb6000000, 0x00204411, 0x000 }, - { 0x0000a000, 0x00204811, 0x000 }, - { 0xb7000000, 0x00204411, 0x000 }, - { 0x0000c000, 0x00204811, 0x000 }, - { 0xb8000000, 0x00204411, 0x000 }, - { 0x0000f8e0, 0x00204811, 0x000 }, - { 0xb9000000, 0x00204411, 0x000 }, - { 0x0000f880, 0x00204811, 0x000 }, - { 0xba000000, 0x00204411, 0x000 }, - { 0x0000e000, 0x00204811, 0x000 }, - { 0xbb000000, 0x00204411, 0x000 }, - { 0x0000f000, 0x00204811, 0x000 }, - { 0xbc000000, 0x00204411, 0x000 }, - { 0x0000f3fc, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x516 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x52b }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x00000028, 0x00203623, 0x000 }, - { 0x00000017, 0x00203623, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203623, 0x000 }, - { 0x00000015, 0x00203623, 0x000 }, - { 0x00000016, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x00000023, 0x00203623, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000002a, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x0000001f, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000020, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x0000001e, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x678 }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x563 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56b }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56b }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56f }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x577 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x68f }, - { 0x00000000, 0x00401c10, 0x579 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x57b }, - { 0x00000000, 0x00600000, 0x5c6 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58c }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58a }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x59d }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59b }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5ae }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5ac }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5bb }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5c1 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c6 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5cd }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5e0 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5e0 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x68a }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x68a }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68a }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68a }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68a }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68a }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x629 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x629 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x602 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x628 }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x60b }, - { 0x0004a003, 0x00604411, 0x68a }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x610 }, - { 0x0004a010, 0x00604411, 0x68a }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x628 }, - { 0x0004a011, 0x00604411, 0x68a }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x68a }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x68a }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x68a }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x68a }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x68a }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x68a }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x63a }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x638 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x63e }, - { 0x00000000, 0x00600000, 0x5c6 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x63e }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x62a }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x62a }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x653 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000010, 0x00404c11, 0x66f }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x688 }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68a }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x68d }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68f }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x692 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x014204ff, 0x05bd0250, 0x000 }, - { 0x01c30168, 0x043f05bd, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705bd, 0x05bd05bd, 0x000 }, - { 0x06460647, 0x031f05bd, 0x000 }, - { 0x05bd05c2, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd054e, 0x05bd05bd, 0x000 }, - { 0x03ba05bd, 0x04b80344, 0x000 }, - { 0x0497044d, 0x043d05bd, 0x000 }, - { 0x04cd05bd, 0x044104da, 0x000 }, - { 0x044d0504, 0x03510375, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x063c05c4, 0x000 }, - { 0x05bd05bd, 0x000705bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05bd05bd, 0x043805bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x00020676, 0x06940006, 0x000 }, -}; - -static const u32 RV630_pfp_microcode[] = { -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV635_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x65f }, - { 0x00000000, 0x00400000, 0x0eb }, - { 0x00000000, 0x00600000, 0x662 }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f8 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f8 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0fd }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x104 }, - { 0xffffffff, 0x00404811, 0x10b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x107 }, - { 0x0000ffff, 0x00404811, 0x10b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x10a }, - { 0x000000ff, 0x00404811, 0x10b }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x112 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x114 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x11b }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x117 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x12e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000004, 0x00404c11, 0x135 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000001c, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x13c }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x147 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x158 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x18f }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ae00000, 0x181 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x186 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x186 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x182 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x197 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000011, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2fb }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x174 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x194 }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x19b }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000029, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x0000000f, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x12f }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x00000015, 0x00600e2d, 0x1bd }, - { 0x00000016, 0x00600e2d, 0x1bd }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b9 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000018, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000013, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e0 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1dc }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1d8 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1d1 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1e5 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2bb }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x205 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x205 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x219 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x212 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0x0040040f, 0x213 }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00000000, 0x00600000, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ae00000, 0x232 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x236 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x236 }, - { 0x00000000, 0xc0404800, 0x233 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2fb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24c }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x251 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x315 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x27c }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x26a }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x25f }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x262 }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x267 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x26a }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2c1 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x272 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x271 }, - { 0x00000016, 0x00404811, 0x276 }, - { 0x00000018, 0x00404811, 0x276 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x275 }, - { 0x00000017, 0x00404811, 0x276 }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2e9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x256 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00000000, 0x00600000, 0x62e }, - { 0x00000000, 0xc0600000, 0x2a3 }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x0000002b, 0x00201a2d, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x0000002a, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x292 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x12f }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x29d }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000001c, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000029, 0x00203622, 0x000 }, - { 0x00000028, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000021, 0x00203627, 0x000 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2dc }, - { 0x00000000, 0x00400000, 0x2d9 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2d9 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2dc }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000000, 0x00600000, 0x665 }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00600000, 0x65c }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2a7 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x0000001a, 0x00201e2d, 0x000 }, - { 0x0000001b, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000017, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x318 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x642 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x34b }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x354 }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x364 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00604802, 0x36e }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5bd }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35f }, - { 0x0000002c, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x370 }, - { 0x0000002c, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x386 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b1 }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b5 }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x39c }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a8 }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x390 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x392 }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x39e }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x80000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000010, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3ae }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3ce }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3c0 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3d3 }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e1 }, - { 0x00000000, 0xc0401800, 0x3e4 }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x68a }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e7 }, - { 0x00000000, 0xc0401c00, 0x3ea }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x68a }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3f7 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3ff }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3fa }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3fa }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3fa }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3fa }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3fa }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3fa }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x01182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0218a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0318c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0418f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0518f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0618e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0718f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0818f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000030, 0x00200a2d, 0x000 }, - { 0x00000000, 0xc0290c40, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x448 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x456 }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x45e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x68a }, - { 0x00000000, 0x00400000, 0x463 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00604805, 0x68f }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46a }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46f }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x474 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x479 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x47e }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x483 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x483 }, - { 0x00000000, 0x00400000, 0x490 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x48d }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x496 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x456 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x4a0 }, - { 0x00040000, 0xc0494a20, 0x4a1 }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x4ad }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x4a9 }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4a7 }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4c0 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x68f }, - { 0x00000000, 0x00400000, 0x4c4 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x68a }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4cb }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x68a }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4cd }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x4fd }, - { 0x0000002c, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4ec }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4e0 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000002d, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4a7 }, - { 0x0000002c, 0xc0203620, 0x000 }, - { 0x0000002d, 0xc0403620, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x502 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xb5000000, 0x00204411, 0x000 }, - { 0x00002000, 0x00204811, 0x000 }, - { 0xb6000000, 0x00204411, 0x000 }, - { 0x0000a000, 0x00204811, 0x000 }, - { 0xb7000000, 0x00204411, 0x000 }, - { 0x0000c000, 0x00204811, 0x000 }, - { 0xb8000000, 0x00204411, 0x000 }, - { 0x0000f8e0, 0x00204811, 0x000 }, - { 0xb9000000, 0x00204411, 0x000 }, - { 0x0000f880, 0x00204811, 0x000 }, - { 0xba000000, 0x00204411, 0x000 }, - { 0x0000e000, 0x00204811, 0x000 }, - { 0xbb000000, 0x00204411, 0x000 }, - { 0x0000f000, 0x00204811, 0x000 }, - { 0xbc000000, 0x00204411, 0x000 }, - { 0x0000f3fc, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x516 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x52b }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x00000028, 0x00203623, 0x000 }, - { 0x00000017, 0x00203623, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203623, 0x000 }, - { 0x00000015, 0x00203623, 0x000 }, - { 0x00000016, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x00000023, 0x00203623, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000002a, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x0000001f, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000020, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x0000001e, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x678 }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x563 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56b }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56b }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x68a }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56f }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x579 }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x577 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x68f }, - { 0x00000000, 0x00401c10, 0x579 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x57b }, - { 0x00000000, 0x00600000, 0x5c6 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x58c }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x58a }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x59d }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59b }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5ae }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5ac }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68a }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5bb }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5c1 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c6 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5cd }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5e0 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5e0 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x68a }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x68a }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x68a }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x68a }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x68a }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x68a }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x629 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x629 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x602 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x628 }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x60b }, - { 0x0004a003, 0x00604411, 0x68a }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x610 }, - { 0x0004a010, 0x00604411, 0x68a }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x628 }, - { 0x0004a011, 0x00604411, 0x68a }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x68a }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x68a }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x68a }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x68a }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x68a }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x68a }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x63a }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x638 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x68a }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x63e }, - { 0x00000000, 0x00600000, 0x5c6 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x63e }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x62a }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x62a }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x653 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36e }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x68a }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x689 }, - { 0x00000010, 0x00404c11, 0x66f }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x688 }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68a }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x68d }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x68f }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x692 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x014204ff, 0x05bd0250, 0x000 }, - { 0x01c30168, 0x043f05bd, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705bd, 0x05bd05bd, 0x000 }, - { 0x06460647, 0x031f05bd, 0x000 }, - { 0x05bd05c2, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd054e, 0x05bd05bd, 0x000 }, - { 0x03ba05bd, 0x04b80344, 0x000 }, - { 0x0497044d, 0x043d05bd, 0x000 }, - { 0x04cd05bd, 0x044104da, 0x000 }, - { 0x044d0504, 0x03510375, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x063c05c4, 0x000 }, - { 0x05bd05bd, 0x000705bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05bd05bd, 0x043805bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x05bd05bd, 0x05bd05bd, 0x000 }, - { 0x00020676, 0x06940006, 0x000 }, -}; - -static const u32 RV635_pfp_microcode[] = { -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV670_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x00000000, 0x00600000, 0x624 }, - { 0x00000000, 0x00600000, 0x638 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00000000, 0x00600000, 0x64d }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x653 }, - { 0x00000000, 0x00400000, 0x0eb }, - { 0x00000000, 0x00600000, 0x656 }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f8 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f8 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0fd }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x104 }, - { 0xffffffff, 0x00404811, 0x10b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x107 }, - { 0x0000ffff, 0x00404811, 0x10b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x10a }, - { 0x000000ff, 0x00404811, 0x10b }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x112 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x114 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x11b }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x117 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x12e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x67c }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x67b }, - { 0x00000004, 0x00404c11, 0x135 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000001c, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x67c }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x13c }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x147 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x158 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x18f }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ae00000, 0x181 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x186 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x186 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x182 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x197 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000011, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2fb }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x174 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x194 }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x19b }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000029, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x0000000f, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x12f }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x00000015, 0x00600e2d, 0x1bd }, - { 0x00000016, 0x00600e2d, 0x1bd }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b9 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000018, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000013, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e0 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1dc }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1d8 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1d1 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1e5 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2bb }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x205 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x205 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x67b }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x219 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x212 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x638 }, - { 0x00000000, 0x0040040f, 0x213 }, - { 0x00000000, 0x00600000, 0x624 }, - { 0x00000000, 0x00600000, 0x638 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00000000, 0x00600000, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ae00000, 0x232 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x236 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x236 }, - { 0x00000000, 0xc0404800, 0x233 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2fb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x624 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24c }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x251 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x315 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x27c }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x26a }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x25f }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x262 }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x267 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x26a }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2c1 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x272 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x271 }, - { 0x00000016, 0x00404811, 0x276 }, - { 0x00000018, 0x00404811, 0x276 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x275 }, - { 0x00000017, 0x00404811, 0x276 }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2e9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x256 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x00000000, 0x00600000, 0x624 }, - { 0x00000000, 0xc0600000, 0x2a3 }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x0000002b, 0x00201a2d, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x0000002a, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x292 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x12f }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x29d }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000001c, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000029, 0x00203622, 0x000 }, - { 0x00000028, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000021, 0x00203627, 0x000 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2dc }, - { 0x00000000, 0x00400000, 0x2d9 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2d9 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2dc }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000000, 0x00600000, 0x659 }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00600000, 0x650 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2a7 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x0000001a, 0x00201e2d, 0x000 }, - { 0x0000001b, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000017, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x318 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x638 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x34b }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x67c }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x354 }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x362 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00604802, 0x36a }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x366 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35d }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5b3 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x35d }, - { 0x0000002c, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x36c }, - { 0x0000002c, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x382 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3ad }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3af }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x398 }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a4 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a4 }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x38c }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x67c }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x38e }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x67c }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x39a }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x80000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000010, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3aa }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36a }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3c4 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x67c }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3b8 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3c9 }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x67c }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3d7 }, - { 0x00000000, 0xc0401800, 0x3da }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x67c }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3dd }, - { 0x00000000, 0xc0401c00, 0x3e0 }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x67c }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x408 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3ed }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3f5 }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x408 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x408 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3f0 }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3f0 }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3f0 }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3f0 }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3f0 }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3f0 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x01182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0218a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0318c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0418f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0518f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0618e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0718f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0818f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000030, 0x00200a2d, 0x000 }, - { 0x00000000, 0xc0290c40, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x67c }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x43e }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x44c }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x454 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x67c }, - { 0x00000000, 0x00400000, 0x459 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00604805, 0x681 }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x460 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x479 }, - { 0x00000000, 0x00400000, 0x486 }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x465 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x479 }, - { 0x00000000, 0x00400000, 0x486 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46a }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x479 }, - { 0x00000000, 0x00400000, 0x486 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x46f }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x479 }, - { 0x00000000, 0x00400000, 0x486 }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x474 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x479 }, - { 0x00000000, 0x00400000, 0x486 }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x479 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x479 }, - { 0x00000000, 0x00400000, 0x486 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x483 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x48c }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x44c }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x496 }, - { 0x00040000, 0xc0494a20, 0x497 }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x4a3 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x49f }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x49d }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4b6 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x681 }, - { 0x00000000, 0x00400000, 0x4ba }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x67c }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4c1 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x67c }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4c3 }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x4f3 }, - { 0x0000002c, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4e2 }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4d6 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000002d, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x49d }, - { 0x0000002c, 0xc0203620, 0x000 }, - { 0x0000002d, 0xc0403620, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x4f8 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xb5000000, 0x00204411, 0x000 }, - { 0x00002000, 0x00204811, 0x000 }, - { 0xb6000000, 0x00204411, 0x000 }, - { 0x0000a000, 0x00204811, 0x000 }, - { 0xb7000000, 0x00204411, 0x000 }, - { 0x0000c000, 0x00204811, 0x000 }, - { 0xb8000000, 0x00204411, 0x000 }, - { 0x0000f8e0, 0x00204811, 0x000 }, - { 0xb9000000, 0x00204411, 0x000 }, - { 0x0000f880, 0x00204811, 0x000 }, - { 0xba000000, 0x00204411, 0x000 }, - { 0x0000e000, 0x00204811, 0x000 }, - { 0xbb000000, 0x00204411, 0x000 }, - { 0x0000f000, 0x00204811, 0x000 }, - { 0xbc000000, 0x00204411, 0x000 }, - { 0x0000f3fc, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x50c }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x521 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x00000028, 0x00203623, 0x000 }, - { 0x00000017, 0x00203623, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203623, 0x000 }, - { 0x00000015, 0x00203623, 0x000 }, - { 0x00000016, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x00000023, 0x00203623, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000002a, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x0000001f, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000020, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x0000001e, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x66a }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x559 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x67c }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x561 }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x56f }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x561 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x67c }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x56f }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x565 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x56f }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x56d }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x681 }, - { 0x00000000, 0x00401c10, 0x56f }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x571 }, - { 0x00000000, 0x00600000, 0x5bc }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x582 }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x67c }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x580 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x593 }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x67c }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x591 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5a4 }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2be, 0x00604411, 0x67c }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5a2 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x67c }, - { 0x0000001a, 0x00212230, 0x000 }, - { 0x00000006, 0x00222630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5b1 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5b7 }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5bc }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000002c, 0x00203621, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0230, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5c3 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000030, 0x00403621, 0x5d6 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5d6 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004a092, 0x00604411, 0x67c }, - { 0x00000031, 0x00203630, 0x000 }, - { 0x0004a093, 0x00604411, 0x67c }, - { 0x00000032, 0x00203630, 0x000 }, - { 0x0004a2b6, 0x00604411, 0x67c }, - { 0x00000033, 0x00203630, 0x000 }, - { 0x0004a2ba, 0x00604411, 0x67c }, - { 0x00000034, 0x00203630, 0x000 }, - { 0x0004a2be, 0x00604411, 0x67c }, - { 0x00000035, 0x00203630, 0x000 }, - { 0x0004a2c2, 0x00604411, 0x67c }, - { 0x00000036, 0x00203630, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000001, 0x002f0230, 0x000 }, - { 0x00000000, 0x0ce00000, 0x61f }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x61f }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00007e00, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x5f8 }, - { 0x0000a092, 0x00204411, 0x000 }, - { 0x00000031, 0x00204a2d, 0x000 }, - { 0x0000a093, 0x00204411, 0x000 }, - { 0x00000032, 0x00204a2d, 0x000 }, - { 0x0000a2b6, 0x00204411, 0x000 }, - { 0x00000033, 0x00204a2d, 0x000 }, - { 0x0000a2ba, 0x00204411, 0x000 }, - { 0x00000034, 0x00204a2d, 0x000 }, - { 0x0000a2be, 0x00204411, 0x000 }, - { 0x00000035, 0x00204a2d, 0x000 }, - { 0x0000a2c2, 0x00204411, 0x000 }, - { 0x00000036, 0x00204a2d, 0x000 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x000001ff, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x61e }, - { 0x00000000, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x601 }, - { 0x0004a003, 0x00604411, 0x67c }, - { 0x0000a003, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x14c00000, 0x606 }, - { 0x0004a010, 0x00604411, 0x67c }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00000001, 0x00210621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x61e }, - { 0x0004a011, 0x00604411, 0x67c }, - { 0x0000a011, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a012, 0x00604411, 0x67c }, - { 0x0000a012, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a013, 0x00604411, 0x67c }, - { 0x0000a013, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a014, 0x00604411, 0x67c }, - { 0x0000a014, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a015, 0x00604411, 0x67c }, - { 0x0000a015, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a016, 0x00604411, 0x67c }, - { 0x0000a016, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x0004a017, 0x00604411, 0x67c }, - { 0x0000a017, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x0000002c, 0x0080062d, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x630 }, - { 0x00000030, 0x0020062d, 0x000 }, - { 0x00000002, 0x00280621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x62e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x67c }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x634 }, - { 0x00000000, 0x00600000, 0x5bc }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x634 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x620 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x620 }, - { 0x00000000, 0x00600000, 0x64d }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x67c }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x647 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x36a }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x67c }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x67b }, - { 0x00000010, 0x00404c11, 0x661 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x67a }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x67c }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x67f }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x681 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x684 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x014204f5, 0x05b30250, 0x000 }, - { 0x01c30168, 0x043505b3, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03cd05b3, 0x05b305b3, 0x000 }, - { 0x063c063d, 0x031f05b3, 0x000 }, - { 0x05b305b8, 0x03200340, 0x000 }, - { 0x032a0282, 0x03420334, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b30544, 0x05b305b3, 0x000 }, - { 0x03b205b3, 0x04ae0344, 0x000 }, - { 0x048d0443, 0x043305b3, 0x000 }, - { 0x04c305b3, 0x043704d0, 0x000 }, - { 0x044304fa, 0x03510371, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b305b3, 0x063205ba, 0x000 }, - { 0x05b305b3, 0x000705b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x03ee03e3, 0x03fe03fc, 0x000 }, - { 0x04040400, 0x04020406, 0x000 }, - { 0x0412040e, 0x041a0416, 0x000 }, - { 0x0422041e, 0x042a0426, 0x000 }, - { 0x05b305b3, 0x042e05b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x05b305b3, 0x05b305b3, 0x000 }, - { 0x00020668, 0x06860006, 0x000 }, -}; - -static const u32 RV670_pfp_microcode[] = { -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001b8, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581a8, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0fff0, -0x042c04, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255403, -0x7cd580, -0x259c03, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca1800, -0xd4401e, -0xd5801e, -0x800053, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xd48060, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001b8, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x800079, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x80008d, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401bb, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401bb, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001b8, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001b8, -0xd4001a, -0xd4c01a, -0x282801, -0x8400f0, -0xcc1003, -0x98801b, -0x04380c, -0x8400f0, -0xcc1003, -0x988017, -0x043808, -0x8400f0, -0xcc1003, -0x988013, -0x043804, -0x8400f0, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000c9, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001b8, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001b8, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001b8, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800101, -0xd5001a, -0xcc0832, -0xd40032, -0x9482d9, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x9882bd, -0x000000, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x9902b0, -0x7c738b, -0x8401bb, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984297, -0x000000, -0x800161, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001b8, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010171, -0x020178, -0x03008f, -0x04007f, -0x050003, -0x06003f, -0x070032, -0x08012c, -0x090046, -0x0a0036, -0x1001b6, -0x1700a2, -0x22013a, -0x230149, -0x2000b4, -0x240125, -0x27004d, -0x28006a, -0x2a0060, -0x2b0052, -0x2f0065, -0x320087, -0x34017f, -0x3c0156, -0x3f0072, -0x41018c, -0x44012e, -0x550173, -0x56017a, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RS780_cp_microcode[][3] = { - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0000ffff, 0x00284621, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000000, 0x00e00000, 0x000 }, - { 0x00010000, 0xc0294620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x622 }, - { 0x00000000, 0x00600000, 0x5d1 }, - { 0x00000000, 0x00600000, 0x5de }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000f00, 0x00281622, 0x000 }, - { 0x00000008, 0x00211625, 0x000 }, - { 0x00000018, 0x00203625, 0x000 }, - { 0x8d000000, 0x00204411, 0x000 }, - { 0x00000004, 0x002f0225, 0x000 }, - { 0x00000000, 0x0ce00000, 0x018 }, - { 0x00412000, 0x00404811, 0x019 }, - { 0x00422000, 0x00204811, 0x000 }, - { 0x8e000000, 0x00204411, 0x000 }, - { 0x00000028, 0x00204a2d, 0x000 }, - { 0x90000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x0000000c, 0x00211622, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000019, 0x00211a22, 0x000 }, - { 0x00000004, 0x00281a26, 0x000 }, - { 0x00000000, 0x002914c5, 0x000 }, - { 0x00000019, 0x00203625, 0x000 }, - { 0x00000000, 0x003a1402, 0x000 }, - { 0x00000016, 0x00211625, 0x000 }, - { 0x00000003, 0x00281625, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0xfffffffc, 0x00280e23, 0x000 }, - { 0x00000000, 0x002914a3, 0x000 }, - { 0x00000017, 0x00203625, 0x000 }, - { 0x00008000, 0x00280e22, 0x000 }, - { 0x00000007, 0x00220e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x20000000, 0x00280e22, 0x000 }, - { 0x00000006, 0x00210e23, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x00000000, 0x00220222, 0x000 }, - { 0x00000000, 0x14e00000, 0x038 }, - { 0x00000000, 0x2ee00000, 0x035 }, - { 0x00000000, 0x2ce00000, 0x037 }, - { 0x00000000, 0x00400e2d, 0x039 }, - { 0x00000008, 0x00200e2d, 0x000 }, - { 0x00000009, 0x0040122d, 0x046 }, - { 0x00000001, 0x00400e2d, 0x039 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x03e }, - { 0x00000008, 0x00401c11, 0x041 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x0000000f, 0x00281e27, 0x000 }, - { 0x00000003, 0x00221e27, 0x000 }, - { 0x7fc00000, 0x00281a23, 0x000 }, - { 0x00000014, 0x00211a26, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000008, 0x00221a26, 0x000 }, - { 0x00000000, 0x00290cc7, 0x000 }, - { 0x00000027, 0x00203624, 0x000 }, - { 0x00007f00, 0x00281221, 0x000 }, - { 0x00001400, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x04b }, - { 0x00000001, 0x00290e23, 0x000 }, - { 0x0000000e, 0x00203623, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfff80000, 0x00294a23, 0x000 }, - { 0x00000000, 0x003a2c02, 0x000 }, - { 0x00000002, 0x00220e2b, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x0000000f, 0x00203623, 0x000 }, - { 0x00001fff, 0x00294a23, 0x000 }, - { 0x00000027, 0x00204a2d, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000029, 0x00200e2d, 0x000 }, - { 0x060a0200, 0x00294a23, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14e00000, 0x061 }, - { 0x00000000, 0x2ee00000, 0x05f }, - { 0x00000000, 0x2ce00000, 0x05e }, - { 0x00000000, 0x00400e2d, 0x062 }, - { 0x00000001, 0x00400e2d, 0x062 }, - { 0x0000000a, 0x00200e2d, 0x000 }, - { 0x0000000b, 0x0040122d, 0x06a }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x003ffffc, 0x00281223, 0x000 }, - { 0x00000002, 0x00221224, 0x000 }, - { 0x7fc00000, 0x00281623, 0x000 }, - { 0x00000014, 0x00211625, 0x000 }, - { 0x00000001, 0x00331625, 0x000 }, - { 0x80000000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00290ca3, 0x000 }, - { 0x3ffffc00, 0x00290e23, 0x000 }, - { 0x0000001f, 0x00211e23, 0x000 }, - { 0x00000000, 0x14e00000, 0x06d }, - { 0x00000100, 0x00401c11, 0x070 }, - { 0x0000000d, 0x00201e2d, 0x000 }, - { 0x000000f0, 0x00281e27, 0x000 }, - { 0x00000004, 0x00221e27, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0xfffff0ff, 0x00281a30, 0x000 }, - { 0x0000a028, 0x00204411, 0x000 }, - { 0x00000000, 0x002948e6, 0x000 }, - { 0x0000a018, 0x00204411, 0x000 }, - { 0x3fffffff, 0x00284a23, 0x000 }, - { 0x0000a010, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000030, 0x0020162d, 0x000 }, - { 0x00000002, 0x00291625, 0x000 }, - { 0x00000030, 0x00203625, 0x000 }, - { 0x00000025, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a3, 0x000 }, - { 0x00000000, 0x0cc00000, 0x083 }, - { 0x00000026, 0x0020162d, 0x000 }, - { 0x00000000, 0x002f00a4, 0x000 }, - { 0x00000000, 0x0cc00000, 0x084 }, - { 0x00000000, 0x00400000, 0x08a }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203624, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x08a }, - { 0x00000000, 0x00600000, 0x5ff }, - { 0x00000000, 0x00600000, 0x5f3 }, - { 0x00000002, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x08d }, - { 0x00000012, 0xc0403620, 0x093 }, - { 0x00000000, 0x2ee00000, 0x091 }, - { 0x00000000, 0x2ce00000, 0x090 }, - { 0x00000002, 0x00400e2d, 0x092 }, - { 0x00000003, 0x00400e2d, 0x092 }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000012, 0x00203623, 0x000 }, - { 0x00000003, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x098 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x0a0 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x2ee00000, 0x09e }, - { 0x00000000, 0x2ce00000, 0x09d }, - { 0x00000002, 0x00400e2d, 0x09f }, - { 0x00000003, 0x00400e2d, 0x09f }, - { 0x0000000c, 0x00200e2d, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x003f0000, 0x00280e23, 0x000 }, - { 0x00000010, 0x00210e23, 0x000 }, - { 0x00000011, 0x00203623, 0x000 }, - { 0x0000001e, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0a7 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x0000001f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0aa }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000008, 0x00210e2b, 0x000 }, - { 0x0000007f, 0x00280e23, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0e1 }, - { 0x00000000, 0x27000000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ae00000, 0x0b3 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000000c, 0x00221e30, 0x000 }, - { 0x99800000, 0x00204411, 0x000 }, - { 0x00000004, 0x0020122d, 0x000 }, - { 0x00000008, 0x00221224, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00291ce4, 0x000 }, - { 0x00000000, 0x00604807, 0x12f }, - { 0x9b000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x9c000000, 0x00204411, 0x000 }, - { 0x00000000, 0x0033146f, 0x000 }, - { 0x00000001, 0x00333e23, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0x00203c05, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e007, 0x00204411, 0x000 }, - { 0x0000000f, 0x0021022b, 0x000 }, - { 0x00000000, 0x14c00000, 0x0cb }, - { 0x00f8ff08, 0x00204811, 0x000 }, - { 0x98000000, 0x00404811, 0x0dc }, - { 0x000000f0, 0x00280e22, 0x000 }, - { 0x000000a0, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x0da }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d5 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0d4 }, - { 0x00003f00, 0x00400c11, 0x0d6 }, - { 0x00001f00, 0x00400c11, 0x0d6 }, - { 0x00000f00, 0x00200c11, 0x000 }, - { 0x00380009, 0x00294a23, 0x000 }, - { 0x3f000000, 0x00280e2b, 0x000 }, - { 0x00000002, 0x00220e23, 0x000 }, - { 0x00000007, 0x00494a23, 0x0dc }, - { 0x00380f09, 0x00204811, 0x000 }, - { 0x68000007, 0x00204811, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000a202, 0x00204411, 0x000 }, - { 0x00ff0000, 0x00280e22, 0x000 }, - { 0x00000080, 0x00294a23, 0x000 }, - { 0x00000027, 0x00200e2d, 0x000 }, - { 0x00000026, 0x0020122d, 0x000 }, - { 0x00000000, 0x002f0083, 0x000 }, - { 0x00000000, 0x0ce00000, 0x0ea }, - { 0x00000000, 0x00600000, 0x5f9 }, - { 0x00000000, 0x00400000, 0x0eb }, - { 0x00000000, 0x00600000, 0x5fc }, - { 0x00000007, 0x0020222d, 0x000 }, - { 0x00000005, 0x00220e22, 0x000 }, - { 0x00100000, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000000, 0x003a0c02, 0x000 }, - { 0x000000ef, 0x00280e23, 0x000 }, - { 0x00000000, 0x00292068, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000003, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x0f8 }, - { 0x0000000b, 0x00210228, 0x000 }, - { 0x00000000, 0x14c00000, 0x0f8 }, - { 0x00000400, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000001c, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x0fd }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000001e, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x10b }, - { 0x0000a30f, 0x00204411, 0x000 }, - { 0x00000011, 0x00200e2d, 0x000 }, - { 0x00000001, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x104 }, - { 0xffffffff, 0x00404811, 0x10b }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x107 }, - { 0x0000ffff, 0x00404811, 0x10b }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x10a }, - { 0x000000ff, 0x00404811, 0x10b }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0002c400, 0x00204411, 0x000 }, - { 0x0000001f, 0x00210e22, 0x000 }, - { 0x00000000, 0x14c00000, 0x112 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000018, 0x40224a20, 0x000 }, - { 0x00000010, 0xc0424a20, 0x114 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x00000013, 0x00203623, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000000a, 0x00201011, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x11b }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00531224, 0x117 }, - { 0xffbfffff, 0x00283a2e, 0x000 }, - { 0x0000001b, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x12e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000d, 0x00204811, 0x000 }, - { 0x00000018, 0x00220e30, 0x000 }, - { 0xfc000000, 0x00280e23, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x00000000, 0x00201010, 0x000 }, - { 0x0000e00e, 0x00204411, 0x000 }, - { 0x07f8ff08, 0x00204811, 0x000 }, - { 0x00000000, 0x00294a23, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a24, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00800000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204806, 0x000 }, - { 0x00000008, 0x00214a27, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x622 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x621 }, - { 0x00000004, 0x00404c11, 0x135 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000001c, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x622 }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x13c }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40280620, 0x000 }, - { 0x00000010, 0xc0210a20, 0x000 }, - { 0x00000000, 0x00341461, 0x000 }, - { 0x00000000, 0x00741882, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x147 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x160 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0681a20, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x158 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000001, 0x00300a2f, 0x000 }, - { 0x00000001, 0x00210a22, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600000, 0x18f }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00202c08, 0x000 }, - { 0x00000000, 0x00202411, 0x000 }, - { 0x00000000, 0x00202811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000002, 0x00221e29, 0x000 }, - { 0x00000000, 0x007048eb, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000001, 0x40330620, 0x000 }, - { 0x00000000, 0xc0302409, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ae00000, 0x181 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x186 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x186 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000001, 0x00530621, 0x182 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0604800, 0x197 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000011, 0x0020062d, 0x000 }, - { 0x00000000, 0x0078042a, 0x2fb }, - { 0x00000000, 0x00202809, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x174 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x194 }, - { 0x00000015, 0xc0203620, 0x000 }, - { 0x00000016, 0xc0203620, 0x000 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x46000000, 0x00600811, 0x1b2 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x19b }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00804811, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000ffff, 0x40281620, 0x000 }, - { 0x00000010, 0xc0811a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x00000008, 0x00221e30, 0x000 }, - { 0x00000029, 0x00201a2d, 0x000 }, - { 0x0000e000, 0x00204411, 0x000 }, - { 0xfffbff09, 0x00204811, 0x000 }, - { 0x0000000f, 0x0020222d, 0x000 }, - { 0x00001fff, 0x00294a28, 0x000 }, - { 0x00000006, 0x0020222d, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000100, 0x00201811, 0x000 }, - { 0x00000008, 0x00621e28, 0x12f }, - { 0x00000008, 0x00822228, 0x000 }, - { 0x0002c000, 0x00204411, 0x000 }, - { 0x00000015, 0x00600e2d, 0x1bd }, - { 0x00000016, 0x00600e2d, 0x1bd }, - { 0x0000c008, 0x00204411, 0x000 }, - { 0x00000017, 0x00200e2d, 0x000 }, - { 0x00000000, 0x14c00000, 0x1b9 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x39000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00804802, 0x000 }, - { 0x00000018, 0x00202e2d, 0x000 }, - { 0x00000000, 0x003b0d63, 0x000 }, - { 0x00000008, 0x00224a23, 0x000 }, - { 0x00000010, 0x00224a23, 0x000 }, - { 0x00000018, 0x00224a23, 0x000 }, - { 0x00000000, 0x00804803, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00000007, 0x0021062f, 0x000 }, - { 0x00000013, 0x00200a2d, 0x000 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000ffff, 0x40282220, 0x000 }, - { 0x0000000f, 0x00262228, 0x000 }, - { 0x00000010, 0x40212620, 0x000 }, - { 0x0000000f, 0x00262629, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1e0 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000081, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000080, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1dc }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1d8 }, - { 0x00000001, 0x00202c11, 0x000 }, - { 0x0000001f, 0x00280a22, 0x000 }, - { 0x0000001f, 0x00282a2a, 0x000 }, - { 0x00000001, 0x00530621, 0x1d1 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000002, 0x00304a2f, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000001, 0x00301e2f, 0x000 }, - { 0x00000000, 0x002f0227, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00600000, 0x1e9 }, - { 0x00000001, 0x00531e27, 0x1e5 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x0000000f, 0x00260e23, 0x000 }, - { 0x00000010, 0xc0211220, 0x000 }, - { 0x0000000f, 0x00261224, 0x000 }, - { 0x00000000, 0x00201411, 0x000 }, - { 0x00000000, 0x00601811, 0x2bb }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022b, 0x000 }, - { 0x00000000, 0x0ce00000, 0x1f8 }, - { 0x00000010, 0x00221628, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a29, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x0020480a, 0x000 }, - { 0x00000000, 0x00202c11, 0x000 }, - { 0x00000010, 0x00221623, 0x000 }, - { 0xffff0000, 0x00281625, 0x000 }, - { 0x0000ffff, 0x00281a24, 0x000 }, - { 0x00000000, 0x002948c5, 0x000 }, - { 0x00000000, 0x00731503, 0x205 }, - { 0x00000000, 0x00201805, 0x000 }, - { 0x00000000, 0x00731524, 0x205 }, - { 0x00000000, 0x002d14c5, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00202802, 0x000 }, - { 0x00000000, 0x00202003, 0x000 }, - { 0x00000000, 0x00802404, 0x000 }, - { 0x0000000f, 0x00210225, 0x000 }, - { 0x00000000, 0x14c00000, 0x621 }, - { 0x00000000, 0x002b1405, 0x000 }, - { 0x00000001, 0x00901625, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001a, 0x00294a22, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a21, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000ffff, 0x40281220, 0x000 }, - { 0x00000010, 0xc0211a20, 0x000 }, - { 0x0000ffff, 0x40280e20, 0x000 }, - { 0x00000010, 0xc0211620, 0x000 }, - { 0x00000000, 0x00741465, 0x2bb }, - { 0x0001a1fd, 0x00604411, 0x2e0 }, - { 0x00000001, 0x00330621, 0x000 }, - { 0x00000000, 0x002f0221, 0x000 }, - { 0x00000000, 0x0cc00000, 0x219 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x212 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x5de }, - { 0x00000000, 0x0040040f, 0x213 }, - { 0x00000000, 0x00600000, 0x5d1 }, - { 0x00000000, 0x00600000, 0x5de }, - { 0x00000210, 0x00600411, 0x315 }, - { 0x00000000, 0x00600000, 0x1a0 }, - { 0x00000000, 0x00600000, 0x19c }, - { 0x00000000, 0x00600000, 0x2bb }, - { 0x00000000, 0x00600000, 0x2a3 }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204808, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ae00000, 0x232 }, - { 0x00000000, 0x00600000, 0x13a }, - { 0x00000000, 0x00400000, 0x236 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x236 }, - { 0x00000000, 0xc0404800, 0x233 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x00600411, 0x2fb }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000000, 0x00600000, 0x5d1 }, - { 0x0000a00c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000018, 0x40210a20, 0x000 }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x24c }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x00080101, 0x00292228, 0x000 }, - { 0x00000014, 0x00203628, 0x000 }, - { 0x0000a30c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x251 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000010, 0x00600411, 0x315 }, - { 0x3f800000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00000000, 0x00600000, 0x27c }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000001, 0x00211e27, 0x000 }, - { 0x00000000, 0x14e00000, 0x26a }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x0000ffff, 0x00281e27, 0x000 }, - { 0x00000000, 0x00341c27, 0x000 }, - { 0x00000000, 0x12c00000, 0x25f }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e5, 0x000 }, - { 0x00000000, 0x08c00000, 0x262 }, - { 0x00000000, 0x00201407, 0x000 }, - { 0x00000012, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00211e27, 0x000 }, - { 0x00000000, 0x00341c47, 0x000 }, - { 0x00000000, 0x12c00000, 0x267 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x08c00000, 0x26a }, - { 0x00000000, 0x00201807, 0x000 }, - { 0x00000000, 0x00600000, 0x2c1 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x00000000, 0x00342023, 0x000 }, - { 0x00000000, 0x12c00000, 0x272 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x271 }, - { 0x00000016, 0x00404811, 0x276 }, - { 0x00000018, 0x00404811, 0x276 }, - { 0x00000000, 0x00342044, 0x000 }, - { 0x00000000, 0x12c00000, 0x275 }, - { 0x00000017, 0x00404811, 0x276 }, - { 0x00000019, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0x00604411, 0x2e9 }, - { 0x00003fff, 0x002f022f, 0x000 }, - { 0x00000000, 0x0cc00000, 0x256 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x00000010, 0x40210620, 0x000 }, - { 0x0000ffff, 0xc0280a20, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x00000010, 0x40211620, 0x000 }, - { 0x0000ffff, 0xc0881a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00042004, 0x00604411, 0x622 }, - { 0x00000000, 0x00600000, 0x5d1 }, - { 0x00000000, 0xc0600000, 0x2a3 }, - { 0x00000005, 0x00200a2d, 0x000 }, - { 0x00000008, 0x00220a22, 0x000 }, - { 0x0000002b, 0x00201a2d, 0x000 }, - { 0x0000001c, 0x00201e2d, 0x000 }, - { 0x00007000, 0x00281e27, 0x000 }, - { 0x00000000, 0x00311ce6, 0x000 }, - { 0x0000002a, 0x00201a2d, 0x000 }, - { 0x0000000c, 0x00221a26, 0x000 }, - { 0x00000000, 0x002f00e6, 0x000 }, - { 0x00000000, 0x06e00000, 0x292 }, - { 0x00000000, 0x00201c11, 0x000 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000010, 0x00201811, 0x000 }, - { 0x00000000, 0x00691ce2, 0x12f }, - { 0x93800000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x95000000, 0x00204411, 0x000 }, - { 0x00000000, 0x002f022f, 0x000 }, - { 0x00000000, 0x0ce00000, 0x29d }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x92000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000001c, 0x00403627, 0x000 }, - { 0x0000000c, 0xc0220a20, 0x000 }, - { 0x00000029, 0x00203622, 0x000 }, - { 0x00000028, 0xc0403620, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000009, 0x00204811, 0x000 }, - { 0xa1000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00804811, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce3, 0x000 }, - { 0x00000021, 0x00203627, 0x000 }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002c1ce4, 0x000 }, - { 0x00000022, 0x00203627, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a3, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x00000000, 0x002d1d07, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203624, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000023, 0x00203627, 0x000 }, - { 0x00000000, 0x00311cc4, 0x000 }, - { 0x00000024, 0x00803627, 0x000 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14c00000, 0x2dc }, - { 0x00000000, 0x00400000, 0x2d9 }, - { 0x0000001a, 0x00203627, 0x000 }, - { 0x0000001b, 0x00203628, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000002, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2d9 }, - { 0x00000003, 0x00210227, 0x000 }, - { 0x00000000, 0x14e00000, 0x2dc }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e1, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120a1, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000024, 0x00201e2d, 0x000 }, - { 0x00000000, 0x002e00e2, 0x000 }, - { 0x00000000, 0x02c00000, 0x2dc }, - { 0x00000022, 0x00201e2d, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x00000000, 0x002e00e8, 0x000 }, - { 0x00000000, 0x06c00000, 0x2dc }, - { 0x00000000, 0x00600000, 0x5ff }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2b5 }, - { 0x00000000, 0x00600000, 0x5f6 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x00000000, 0x00600000, 0x2a7 }, - { 0x00000000, 0x00400000, 0x2de }, - { 0x0000001a, 0x00201e2d, 0x000 }, - { 0x0000001b, 0x0080222d, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000000, 0x00311ca1, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294847, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e21, 0x000 }, - { 0x00000000, 0x003120c2, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00311ca3, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294887, 0x000 }, - { 0x00000001, 0x00220a21, 0x000 }, - { 0x00000000, 0x003008a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000010, 0x00221e23, 0x000 }, - { 0x00000000, 0x003120c4, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x003808c5, 0x000 }, - { 0x00000000, 0x00300841, 0x000 }, - { 0x00000001, 0x00220a22, 0x000 }, - { 0x00000000, 0x003308a2, 0x000 }, - { 0x00000010, 0x00221e22, 0x000 }, - { 0x00000010, 0x00212222, 0x000 }, - { 0x00000000, 0x00894907, 0x000 }, - { 0x00000017, 0x0020222d, 0x000 }, - { 0x00000000, 0x14c00000, 0x318 }, - { 0xffffffef, 0x00280621, 0x000 }, - { 0x00000014, 0x0020222d, 0x000 }, - { 0x0000f8e0, 0x00204411, 0x000 }, - { 0x00000000, 0x00294901, 0x000 }, - { 0x00000000, 0x00894901, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x060a0200, 0x00804811, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0204811, 0x000 }, - { 0x8a000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00002257, 0x00204411, 0x000 }, - { 0x00000003, 0xc0484a20, 0x000 }, - { 0x0000225d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0x00600000, 0x5de }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00384a22, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0001a1fd, 0x00204411, 0x000 }, - { 0x00000000, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x00000001, 0x40304a20, 0x000 }, - { 0x00000002, 0xc0304a20, 0x000 }, - { 0x00000001, 0x00530a22, 0x355 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x622 }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x35e }, - { 0x00000014, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x36c }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00604802, 0x374 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x370 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x367 }, - { 0x00000028, 0x002f0222, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5ba }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x367 }, - { 0x0000002c, 0x00203626, 0x000 }, - { 0x00000049, 0x00201811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000001, 0x00331a26, 0x000 }, - { 0x00000000, 0x002f0226, 0x000 }, - { 0x00000000, 0x0cc00000, 0x376 }, - { 0x0000002c, 0x00801a2d, 0x000 }, - { 0x0000003f, 0xc0280a20, 0x000 }, - { 0x00000015, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x38c }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b7 }, - { 0x00000016, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3b9 }, - { 0x00000020, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3a2 }, - { 0x0000000f, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3ae }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x3ae }, - { 0x0000001e, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x396 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x08000000, 0x00290a22, 0x000 }, - { 0x00000003, 0x40210e20, 0x000 }, - { 0x0000000c, 0xc0211220, 0x000 }, - { 0x00080000, 0x00281224, 0x000 }, - { 0x00000014, 0xc0221620, 0x000 }, - { 0x00000000, 0x002914a4, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x002948a2, 0x000 }, - { 0x0000a1fe, 0x00204411, 0x000 }, - { 0x00000000, 0x00404803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000016, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x622 }, - { 0x00000015, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x398 }, - { 0x0000210e, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000017, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x622 }, - { 0x00000003, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3a4 }, - { 0x00002108, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404802, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x80000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000010, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3b4 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000006, 0x00404811, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x374 }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x0000001d, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x3ce }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x00000018, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x622 }, - { 0x00000011, 0x00210230, 0x000 }, - { 0x00000000, 0x14e00000, 0x3c2 }, - { 0x00002100, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0xbabecafe, 0x00204811, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000004, 0x00404811, 0x000 }, - { 0x00002170, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000a, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x3d3 }, - { 0x8c000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00003fff, 0x40280a20, 0x000 }, - { 0x80000000, 0x40280e20, 0x000 }, - { 0x40000000, 0xc0281220, 0x000 }, - { 0x00040000, 0x00694622, 0x622 }, - { 0x00000000, 0x00201410, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e1 }, - { 0x00000000, 0xc0401800, 0x3e4 }, - { 0x00003fff, 0xc0281a20, 0x000 }, - { 0x00040000, 0x00694626, 0x622 }, - { 0x00000000, 0x00201810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x3e7 }, - { 0x00000000, 0xc0401c00, 0x3ea }, - { 0x00003fff, 0xc0281e20, 0x000 }, - { 0x00040000, 0x00694627, 0x622 }, - { 0x00000000, 0x00201c10, 0x000 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0x002820c5, 0x000 }, - { 0x00000000, 0x004948e8, 0x000 }, - { 0xa5800000, 0x00200811, 0x000 }, - { 0x00002000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x40204800, 0x000 }, - { 0x0000001f, 0xc0210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x3f7 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00008000, 0x00204811, 0x000 }, - { 0x0000ffff, 0xc0481220, 0x3ff }, - { 0xa7800000, 0x00200811, 0x000 }, - { 0x0000a000, 0x00200c11, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0x00204402, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000ffff, 0xc0281220, 0x000 }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00304883, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x83000000, 0x00604411, 0x412 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xa9800000, 0x00200811, 0x000 }, - { 0x0000c000, 0x00400c11, 0x3fa }, - { 0xab800000, 0x00200811, 0x000 }, - { 0x0000f8e0, 0x00400c11, 0x3fa }, - { 0xad800000, 0x00200811, 0x000 }, - { 0x0000f880, 0x00400c11, 0x3fa }, - { 0xb3800000, 0x00200811, 0x000 }, - { 0x0000f3fc, 0x00400c11, 0x3fa }, - { 0xaf800000, 0x00200811, 0x000 }, - { 0x0000e000, 0x00400c11, 0x3fa }, - { 0xb1800000, 0x00200811, 0x000 }, - { 0x0000f000, 0x00400c11, 0x3fa }, - { 0x83000000, 0x00204411, 0x000 }, - { 0x00002148, 0x00204811, 0x000 }, - { 0x84000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x1d000000, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x01182000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0218a000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0318c000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0418f8e0, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0518f880, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0618e000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0718f000, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x0818f3fc, 0xc0304620, 0x000 }, - { 0x00000000, 0xd9004800, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x00000033, 0xc0300a20, 0x000 }, - { 0x00000000, 0xc0403440, 0x000 }, - { 0x00000030, 0x00200a2d, 0x000 }, - { 0x00000000, 0xc0290c40, 0x000 }, - { 0x00000030, 0x00203623, 0x000 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x00a0000a, 0x000 }, - { 0x86000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x85000000, 0xc0204411, 0x000 }, - { 0x00000000, 0x00404801, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x00000018, 0x40210220, 0x000 }, - { 0x00000000, 0x14c00000, 0x447 }, - { 0x00800000, 0xc0494a20, 0x448 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x06e00000, 0x450 }, - { 0x00000004, 0x00200811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x622 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00404c02, 0x450 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x00000000, 0xc0201400, 0x000 }, - { 0x00000000, 0xc0201800, 0x000 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x461 }, - { 0x00000000, 0xc0202000, 0x000 }, - { 0x00000004, 0x002f0228, 0x000 }, - { 0x00000000, 0x06e00000, 0x461 }, - { 0x00000004, 0x00202011, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x00000010, 0x00280a23, 0x000 }, - { 0x00000010, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ce00000, 0x469 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0x00694624, 0x622 }, - { 0x00000000, 0x00400000, 0x46e }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00604805, 0x627 }, - { 0x00000000, 0x002824f0, 0x000 }, - { 0x00000007, 0x00280a23, 0x000 }, - { 0x00000001, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x475 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x04e00000, 0x48e }, - { 0x00000000, 0x00400000, 0x49b }, - { 0x00000002, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x47a }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x02e00000, 0x48e }, - { 0x00000000, 0x00400000, 0x49b }, - { 0x00000003, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x47f }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ce00000, 0x48e }, - { 0x00000000, 0x00400000, 0x49b }, - { 0x00000004, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x484 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x0ae00000, 0x48e }, - { 0x00000000, 0x00400000, 0x49b }, - { 0x00000005, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x489 }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x06e00000, 0x48e }, - { 0x00000000, 0x00400000, 0x49b }, - { 0x00000006, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x48e }, - { 0x00000000, 0x002f00c9, 0x000 }, - { 0x00000000, 0x08e00000, 0x48e }, - { 0x00000000, 0x00400000, 0x49b }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x000 }, - { 0x00000008, 0x00210a23, 0x000 }, - { 0x00000000, 0x14c00000, 0x498 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00007f00, 0x00280a21, 0x000 }, - { 0x00004500, 0x002f0222, 0x000 }, - { 0x00000000, 0x0ae00000, 0x4a1 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x00404c08, 0x461 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000010, 0x40210e20, 0x000 }, - { 0x00000011, 0x40211220, 0x000 }, - { 0x00000012, 0x40211620, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00210225, 0x000 }, - { 0x00000000, 0x14e00000, 0x4ab }, - { 0x00040000, 0xc0494a20, 0x4ac }, - { 0xfffbffff, 0xc0284a20, 0x000 }, - { 0x00000000, 0x00210223, 0x000 }, - { 0x00000000, 0x14e00000, 0x4b8 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x0000000c, 0x00204811, 0x000 }, - { 0x00000000, 0x00200010, 0x000 }, - { 0x00000000, 0x14c00000, 0x4b4 }, - { 0xa0000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000004, 0x00204811, 0x000 }, - { 0x0000216b, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000216c, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204810, 0x000 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0ce00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4b2 }, - { 0x00000000, 0xc0210a20, 0x000 }, - { 0x00000000, 0x14c00000, 0x4cb }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x627 }, - { 0x00000000, 0x00400000, 0x4cf }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00040000, 0xc0294620, 0x000 }, - { 0x00000000, 0xc0600000, 0x622 }, - { 0x00000001, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x4d6 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00404811, 0x000 }, - { 0x00000000, 0xc0204400, 0x000 }, - { 0x00000000, 0xc0404810, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x000021f8, 0x00204411, 0x000 }, - { 0x0000000e, 0x00204811, 0x000 }, - { 0x000421f9, 0x00604411, 0x622 }, - { 0x00000000, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x4d8 }, - { 0x00002180, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000003, 0x00333e2f, 0x000 }, - { 0x00000001, 0x00210221, 0x000 }, - { 0x00000000, 0x14e00000, 0x508 }, - { 0x0000002c, 0x00200a2d, 0x000 }, - { 0x00040000, 0x18e00c11, 0x4f7 }, - { 0x00000001, 0x00333e2f, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xd8c04800, 0x4eb }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000002d, 0x0020122d, 0x000 }, - { 0x00000000, 0x00290c83, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204802, 0x000 }, - { 0x00000000, 0x00204803, 0x000 }, - { 0x00000008, 0x00300a22, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000011, 0x00210224, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000000, 0x00400000, 0x4b2 }, - { 0x0000002c, 0xc0203620, 0x000 }, - { 0x0000002d, 0xc0403620, 0x000 }, - { 0x0000000f, 0x00210221, 0x000 }, - { 0x00000000, 0x14c00000, 0x50d }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00000000, 0xd9000000, 0x000 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0xb5000000, 0x00204411, 0x000 }, - { 0x00002000, 0x00204811, 0x000 }, - { 0xb6000000, 0x00204411, 0x000 }, - { 0x0000a000, 0x00204811, 0x000 }, - { 0xb7000000, 0x00204411, 0x000 }, - { 0x0000c000, 0x00204811, 0x000 }, - { 0xb8000000, 0x00204411, 0x000 }, - { 0x0000f8e0, 0x00204811, 0x000 }, - { 0xb9000000, 0x00204411, 0x000 }, - { 0x0000f880, 0x00204811, 0x000 }, - { 0xba000000, 0x00204411, 0x000 }, - { 0x0000e000, 0x00204811, 0x000 }, - { 0xbb000000, 0x00204411, 0x000 }, - { 0x0000f000, 0x00204811, 0x000 }, - { 0xbc000000, 0x00204411, 0x000 }, - { 0x0000f3fc, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000002, 0x00204811, 0x000 }, - { 0x000000ff, 0x00280e30, 0x000 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x521 }, - { 0x00000000, 0xc0200800, 0x000 }, - { 0x00000000, 0x14c00000, 0x536 }, - { 0x00000000, 0x00200c11, 0x000 }, - { 0x0000001c, 0x00203623, 0x000 }, - { 0x0000002b, 0x00203623, 0x000 }, - { 0x00000029, 0x00203623, 0x000 }, - { 0x00000028, 0x00203623, 0x000 }, - { 0x00000017, 0x00203623, 0x000 }, - { 0x00000025, 0x00203623, 0x000 }, - { 0x00000026, 0x00203623, 0x000 }, - { 0x00000015, 0x00203623, 0x000 }, - { 0x00000016, 0x00203623, 0x000 }, - { 0xffffe000, 0x00200c11, 0x000 }, - { 0x00000021, 0x00203623, 0x000 }, - { 0x00000022, 0x00203623, 0x000 }, - { 0x00001fff, 0x00200c11, 0x000 }, - { 0x00000023, 0x00203623, 0x000 }, - { 0x00000024, 0x00203623, 0x000 }, - { 0xf1ffffff, 0x00283a2e, 0x000 }, - { 0x0000001a, 0xc0220e20, 0x000 }, - { 0x00000000, 0x0029386e, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000006, 0x00204811, 0x000 }, - { 0x0000002a, 0x40203620, 0x000 }, - { 0x87000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0x9d000000, 0x00204411, 0x000 }, - { 0x0000001f, 0x40214a20, 0x000 }, - { 0x96000000, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0200c00, 0x000 }, - { 0x00000000, 0xc0201000, 0x000 }, - { 0x0000001f, 0x00211624, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x0000001d, 0x00203623, 0x000 }, - { 0x00000003, 0x00281e23, 0x000 }, - { 0x00000008, 0x00222223, 0x000 }, - { 0xfffff000, 0x00282228, 0x000 }, - { 0x00000000, 0x002920e8, 0x000 }, - { 0x0000001f, 0x00203628, 0x000 }, - { 0x00000018, 0x00211e23, 0x000 }, - { 0x00000020, 0x00203627, 0x000 }, - { 0x00000002, 0x00221624, 0x000 }, - { 0x00000000, 0x003014a8, 0x000 }, - { 0x0000001e, 0x00203625, 0x000 }, - { 0x00000003, 0x00211a24, 0x000 }, - { 0x10000000, 0x00281a26, 0x000 }, - { 0xefffffff, 0x00283a2e, 0x000 }, - { 0x00000000, 0x004938ce, 0x610 }, - { 0x00000001, 0x40280a20, 0x000 }, - { 0x00000006, 0x40280e20, 0x000 }, - { 0x00000300, 0xc0281220, 0x000 }, - { 0x00000008, 0x00211224, 0x000 }, - { 0x00000000, 0xc0201620, 0x000 }, - { 0x00000000, 0xc0201a20, 0x000 }, - { 0x00000000, 0x00210222, 0x000 }, - { 0x00000000, 0x14c00000, 0x56c }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x622 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00020000, 0x00294a26, 0x000 }, - { 0x00000000, 0x00204810, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x574 }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x582 }, - { 0x00000002, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x574 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00002258, 0x00300a24, 0x000 }, - { 0x00040000, 0x00694622, 0x622 }, - { 0x00000000, 0xc0201c10, 0x000 }, - { 0x00000000, 0xc0400000, 0x582 }, - { 0x00000000, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x578 }, - { 0x00000000, 0xc0201c00, 0x000 }, - { 0x00000000, 0xc0400000, 0x582 }, - { 0x00000004, 0x002f0223, 0x000 }, - { 0x00000000, 0x0cc00000, 0x580 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x0000216d, 0x00204411, 0x000 }, - { 0x00000000, 0xc0204800, 0x000 }, - { 0x00000000, 0xc0604800, 0x627 }, - { 0x00000000, 0x00401c10, 0x582 }, - { 0x00000000, 0xc0200000, 0x000 }, - { 0x00000000, 0xc0400000, 0x000 }, - { 0x00000000, 0x0ee00000, 0x584 }, - { 0x00000000, 0x00600000, 0x5c3 }, - { 0x00000000, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x592 }, - { 0x0000a2b7, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x00000033, 0x0020262d, 0x000 }, - { 0x0000001a, 0x00212229, 0x000 }, - { 0x00000006, 0x00222629, 0x000 }, - { 0x0000a2c4, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x590 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d1, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000001, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5a0 }, - { 0x0000a2bb, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x00000034, 0x0020262d, 0x000 }, - { 0x0000001a, 0x00212229, 0x000 }, - { 0x00000006, 0x00222629, 0x000 }, - { 0x0000a2c5, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x59e }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d2, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x00000002, 0x002f0224, 0x000 }, - { 0x00000000, 0x0cc00000, 0x5ae }, - { 0x0000a2bf, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x00000035, 0x0020262d, 0x000 }, - { 0x0000001a, 0x00212229, 0x000 }, - { 0x00000006, 0x00222629, 0x000 }, - { 0x0000a2c6, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5ac }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d3, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x0000a2c3, 0x00204411, 0x000 }, - { 0x00000000, 0x00204807, 0x000 }, - { 0x00000036, 0x0020262d, 0x000 }, - { 0x0000001a, 0x00212229, 0x000 }, - { 0x00000006, 0x00222629, 0x000 }, - { 0x0000a2c7, 0x00204411, 0x000 }, - { 0x00000000, 0x003048e9, 0x000 }, - { 0x00000000, 0x00e00000, 0x5b8 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000000, 0x00404808, 0x000 }, - { 0x0000a2d4, 0x00204411, 0x000 }, - { 0x00000001, 0x00504a28, 0x000 }, - { 0x85000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0x0000304a, 0x00204411, 0x000 }, - { 0x01000000, 0x00204811, 0x000 }, - { 0x00000000, 0x00400000, 0x5be }, - { 0xa4000000, 0xc0204411, 0x000 }, - { 0x00000000, 0xc0404800, 0x000 }, - { 0x00000000, 0xc0600000, 0x5c3 }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x0000003f, 0x00204811, 0x000 }, - { 0x00000005, 0x00204811, 0x000 }, - { 0x0000a1f4, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x88000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0xff000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x00000002, 0x00804811, 0x000 }, - { 0x00000000, 0x0ee00000, 0x5d6 }, - { 0x00001000, 0x00200811, 0x000 }, - { 0x0000002b, 0x00203622, 0x000 }, - { 0x00000000, 0x00600000, 0x5da }, - { 0x00000000, 0x00600000, 0x5c3 }, - { 0x98000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00804811, 0x000 }, - { 0x00000000, 0xc0600000, 0x5da }, - { 0x00000000, 0xc0400400, 0x001 }, - { 0x0000a2a4, 0x00204411, 0x000 }, - { 0x00000022, 0x00204811, 0x000 }, - { 0x89000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00404811, 0x5cd }, - { 0x97000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x8a000000, 0x00204411, 0x000 }, - { 0x00000000, 0x00404811, 0x5cd }, - { 0x00000000, 0x00600000, 0x5f3 }, - { 0x0001a2a4, 0xc0204411, 0x000 }, - { 0x00000016, 0x00604811, 0x374 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x09800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x0004217f, 0x00604411, 0x622 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x000 }, - { 0x00000004, 0x00404c11, 0x5ed }, - { 0x00000000, 0x00400000, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000004, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffffb, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0x00000008, 0x00291e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x00000017, 0x00201e2d, 0x000 }, - { 0xfffffff7, 0x00281e27, 0x000 }, - { 0x00000017, 0x00803627, 0x000 }, - { 0x0001a2a4, 0x00204411, 0x000 }, - { 0x00000016, 0x00604811, 0x374 }, - { 0x00002010, 0x00204411, 0x000 }, - { 0x00010000, 0x00204811, 0x000 }, - { 0x0000217c, 0x00204411, 0x000 }, - { 0x01800000, 0x00204811, 0x000 }, - { 0xffffffff, 0x00204811, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000000, 0x17000000, 0x000 }, - { 0x81000000, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0004217f, 0x00604411, 0x622 }, - { 0x0000001f, 0x00210230, 0x000 }, - { 0x00000000, 0x14c00000, 0x621 }, - { 0x00000010, 0x00404c11, 0x607 }, - { 0x00000000, 0xc0200400, 0x000 }, - { 0x00000000, 0x38c00000, 0x000 }, - { 0x0000001d, 0x00200a2d, 0x000 }, - { 0x0000001e, 0x00200e2d, 0x000 }, - { 0x0000001f, 0x0020122d, 0x000 }, - { 0x00000020, 0x0020162d, 0x000 }, - { 0x00002169, 0x00204411, 0x000 }, - { 0x00000000, 0x00204804, 0x000 }, - { 0x00000000, 0x00204805, 0x000 }, - { 0x00000000, 0x00204801, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000004, 0x00301224, 0x000 }, - { 0x00000000, 0x002f0064, 0x000 }, - { 0x00000000, 0x0cc00000, 0x620 }, - { 0x00000003, 0x00281a22, 0x000 }, - { 0x00000008, 0x00221222, 0x000 }, - { 0xfffff000, 0x00281224, 0x000 }, - { 0x00000000, 0x002910c4, 0x000 }, - { 0x0000001f, 0x00403624, 0x000 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x622 }, - { 0x9f000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x625 }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x1ac00000, 0x627 }, - { 0x9e000000, 0x00204411, 0x000 }, - { 0xcafebabe, 0x00204811, 0x000 }, - { 0x00000000, 0x1ae00000, 0x62a }, - { 0x00000000, 0x00800000, 0x000 }, - { 0x00000000, 0x00600000, 0x00b }, - { 0x00001000, 0x00600411, 0x315 }, - { 0x00000000, 0x00200411, 0x000 }, - { 0x00000000, 0x00600811, 0x1b2 }, - { 0x0000225c, 0x00204411, 0x000 }, - { 0x00000003, 0x00204811, 0x000 }, - { 0x00002256, 0x00204411, 0x000 }, - { 0x0000001b, 0x00204811, 0x000 }, - { 0x0000a1fc, 0x00204411, 0x000 }, - { 0x00000001, 0x00204811, 0x000 }, - { 0x0001a1fd, 0xc0204411, 0x000 }, - { 0x00000021, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000024, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000022, 0x0020222d, 0x000 }, - { 0x0000ffff, 0x00282228, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00204811, 0x000 }, - { 0x00000023, 0x00201e2d, 0x000 }, - { 0x00000010, 0x00221e27, 0x000 }, - { 0x00000000, 0x00294907, 0x000 }, - { 0x00000000, 0x00404811, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x00000000, 0x00000000, 0x000 }, - { 0x0142050a, 0x05ba0250, 0x000 }, - { 0x01c30168, 0x044105ba, 0x000 }, - { 0x02250209, 0x02500151, 0x000 }, - { 0x02230245, 0x02a00241, 0x000 }, - { 0x03d705ba, 0x05ba05ba, 0x000 }, - { 0x05e205e3, 0x031f05ba, 0x000 }, - { 0x032005bf, 0x0320034a, 0x000 }, - { 0x03340282, 0x034c033e, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x05ba0557, 0x05ba032a, 0x000 }, - { 0x03bc05ba, 0x04c3034e, 0x000 }, - { 0x04a20455, 0x043f05ba, 0x000 }, - { 0x04d805ba, 0x044304e5, 0x000 }, - { 0x0455050f, 0x035b037b, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x05ba05ba, 0x05d805c1, 0x000 }, - { 0x05ba05ba, 0x000705ba, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x03f803ed, 0x04080406, 0x000 }, - { 0x040e040a, 0x040c0410, 0x000 }, - { 0x041c0418, 0x04240420, 0x000 }, - { 0x042c0428, 0x04340430, 0x000 }, - { 0x05ba05ba, 0x043a0438, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x05ba05ba, 0x05ba05ba, 0x000 }, - { 0x0002060e, 0x062c0006, 0x000 }, -}; - -static const u32 RS780_pfp_microcode[] = { -0xca0400, -0xa00000, -0x7e828b, -0x7c038b, -0x8001db, -0x7c038b, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xc41838, -0xca2400, -0xca2800, -0x9581cb, -0xc41c3a, -0xc3c000, -0xca0800, -0xca0c00, -0x7c744b, -0xc20005, -0x99c000, -0xc41c3a, -0x7c744c, -0xc0ffe0, -0x042c08, -0x309002, -0x7d2500, -0x351402, -0x7d350b, -0x255407, -0x7cd580, -0x259c07, -0x95c004, -0xd5001b, -0x7eddc1, -0x7d9d80, -0xd6801b, -0xd5801b, -0xd4401e, -0xd5401e, -0xd6401e, -0xd6801e, -0xd4801e, -0xd4c01e, -0x9783d3, -0xd5c01e, -0xca0800, -0x80001a, -0xca0c00, -0xe4011e, -0xd4001e, -0x80000c, -0xc41838, -0xe4013e, -0xd4001e, -0x80000c, -0xc41838, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0xca0c00, -0x8001db, -0xd48024, -0xca0800, -0x7c00c0, -0xc81425, -0xc81824, -0x7c9488, -0x7c9880, -0xc20003, -0xd40075, -0x7c744c, -0x800064, -0xd4401e, -0xca1800, -0xd4401e, -0xd5801e, -0x800062, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xe2001e, -0xca0400, -0xa00000, -0x7e828b, -0xd40075, -0xd4401e, -0xca0800, -0xca0c00, -0xca1000, -0xd48019, -0xd4c018, -0xd50017, -0xd4801e, -0xd4c01e, -0xd5001e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c01, -0xd48060, -0x94c003, -0x041001, -0x041002, -0xd50025, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xd48061, -0xd4401e, -0x800000, -0xd4801e, -0xca0800, -0xca0c00, -0xd4401e, -0xd48016, -0xd4c016, -0xd4801e, -0x8001db, -0xd4c01e, -0xc60843, -0xca0c00, -0xca1000, -0x948004, -0xca1400, -0xe420f3, -0xd42013, -0xd56065, -0xd4e01c, -0xd5201c, -0xd5601c, -0x800000, -0x062001, -0xc60843, -0xca0c00, -0xca1000, -0x9483f7, -0xca1400, -0xe420f3, -0x80009c, -0xd42013, -0xc60843, -0xca0c00, -0xca1000, -0x9883ef, -0xca1400, -0xd40064, -0x8000b0, -0x000000, -0xc41432, -0xc61843, -0xc4082f, -0x954005, -0xc40c30, -0xd4401e, -0x800000, -0xee001e, -0x9583f5, -0xc41031, -0xd44033, -0xd52065, -0xd4a01c, -0xd4e01c, -0xd5201c, -0xe4015e, -0xd4001e, -0x800000, -0x062001, -0xca1800, -0x0a2001, -0xd60076, -0xc40836, -0x988007, -0xc61045, -0x950110, -0xd4001f, -0xd46062, -0x800000, -0xd42062, -0xcc3835, -0xcc1433, -0x8401de, -0xd40072, -0xd5401e, -0x800000, -0xee001e, -0xe2001a, -0x8401de, -0xe2001a, -0xcc104b, -0xcc0447, -0x2c9401, -0x7d098b, -0x984005, -0x7d15cb, -0xd4001a, -0x8001db, -0xd4006d, -0x344401, -0xcc0c48, -0x98403a, -0xcc2c4a, -0x958004, -0xcc0449, -0x8001db, -0xd4001a, -0xd4c01a, -0x282801, -0x840113, -0xcc1003, -0x98801b, -0x04380c, -0x840113, -0xcc1003, -0x988017, -0x043808, -0x840113, -0xcc1003, -0x988013, -0x043804, -0x840113, -0xcc1003, -0x988014, -0xcc104c, -0x9a8009, -0xcc144d, -0x9840dc, -0xd4006d, -0xcc1848, -0xd5001a, -0xd5401a, -0x8000ec, -0xd5801a, -0x96c0d5, -0xd4006d, -0x8001db, -0xd4006e, -0x9ac003, -0xd4006d, -0xd4006e, -0x800000, -0xec007f, -0x9ac0cc, -0xd4006d, -0x8001db, -0xd4006e, -0xcc1403, -0xcc1803, -0xcc1c03, -0x7d9103, -0x7dd583, -0x7d190c, -0x35cc1f, -0x35701f, -0x7cf0cb, -0x7cd08b, -0x880000, -0x7e8e8b, -0x95c004, -0xd4006e, -0x8001db, -0xd4001a, -0xd4c01a, -0xcc0803, -0xcc0c03, -0xcc1003, -0xcc1403, -0xcc1803, -0xcc1c03, -0xcc2403, -0xcc2803, -0x35c41f, -0x36b01f, -0x7c704b, -0x34f01f, -0x7c704b, -0x35701f, -0x7c704b, -0x7d8881, -0x7dccc1, -0x7e5101, -0x7e9541, -0x7c9082, -0x7cd4c2, -0x7c848b, -0x9ac003, -0x7c8c8b, -0x2c8801, -0x98809e, -0xd4006d, -0x98409c, -0xd4006e, -0xcc084c, -0xcc0c4d, -0xcc1048, -0xd4801a, -0xd4c01a, -0x800124, -0xd5001a, -0xcc0832, -0xd40032, -0x9482b6, -0xca0c00, -0xd4401e, -0x800000, -0xd4001e, -0xe4011e, -0xd4001e, -0xca0800, -0xca0c00, -0xca1000, -0xd4401e, -0xca1400, -0xd4801e, -0xd4c01e, -0xd5001e, -0xd5401e, -0xd54034, -0x800000, -0xee001e, -0x280404, -0xe2001a, -0xe2001a, -0xd4401a, -0xca3800, -0xcc0803, -0xcc0c03, -0xcc0c03, -0xcc0c03, -0x98829a, -0x000000, -0x8401de, -0xd7a06f, -0x800000, -0xee001f, -0xca0400, -0xc2ff00, -0xcc0834, -0xc13fff, -0x7c74cb, -0x7cc90b, -0x7d010f, -0x99028d, -0x7c738b, -0x8401de, -0xd7a06f, -0x800000, -0xee001f, -0xca0800, -0x281900, -0x7d898b, -0x958014, -0x281404, -0xca0c00, -0xca1000, -0xca1c00, -0xca2400, -0xe2001f, -0xd4c01a, -0xd5001a, -0xd5401a, -0xcc1803, -0xcc2c03, -0xcc2c03, -0xcc2c03, -0x7da58b, -0x7d9c47, -0x984274, -0x000000, -0x800184, -0xd4c01a, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xe4011e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xe4013e, -0xd4001e, -0xd4401e, -0xee001e, -0xca0400, -0xa00000, -0x7e828b, -0xca0800, -0x248c06, -0x0ccc06, -0x98c006, -0xcc104e, -0x990004, -0xd40073, -0xe4011e, -0xd4001e, -0xd4401e, -0xd4801e, -0x800000, -0xee001e, -0xca0800, -0xca0c00, -0x34d018, -0x251001, -0x950021, -0xc17fff, -0xca1000, -0xca1400, -0xca1800, -0xd4801d, -0xd4c01d, -0x7db18b, -0xc14202, -0xc2c001, -0xd5801d, -0x34dc0e, -0x7d5d4c, -0x7f734c, -0xd7401e, -0xd5001e, -0xd5401e, -0xc14200, -0xc2c000, -0x099c01, -0x31dc10, -0x7f5f4c, -0x7f734c, -0x042802, -0x7d8380, -0xd5a86f, -0xd58066, -0xd7401e, -0xec005e, -0xc82402, -0xc82402, -0x8001db, -0xd60076, -0xd4401e, -0xd4801e, -0xd4c01e, -0x800000, -0xee001e, -0x800000, -0xee001f, -0xd4001f, -0x800000, -0xd4001f, -0xd4001f, -0x880000, -0xd4001f, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x000000, -0x010194, -0x02019b, -0x0300b2, -0x0400a2, -0x050003, -0x06003f, -0x070032, -0x08014f, -0x090046, -0x0a0036, -0x1001d9, -0x1700c5, -0x22015d, -0x23016c, -0x2000d7, -0x240148, -0x26004d, -0x27005c, -0x28008d, -0x290051, -0x2a007e, -0x2b0061, -0x2f0088, -0x3200aa, -0x3401a2, -0x36006f, -0x3c0179, -0x3f0095, -0x4101af, -0x440151, -0x550196, -0x56019d, -0x60000b, -0x610034, -0x620038, -0x630038, -0x640038, -0x650038, -0x660038, -0x670038, -0x68003a, -0x690041, -0x6a0048, -0x6b0048, -0x6c0048, -0x6d0048, -0x6e0048, -0x6f0048, -0x7301d9, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -0x000006, -}; - -static const u32 RV770_cp_microcode[] = { -0xcc0003ea, -0x7c408000, -0xa0000000, -0xcc800062, -0x80000001, -0xd040007f, -0x80000001, -0xcc400041, -0x7c40c000, -0xc0160004, -0x30d03fff, -0x7d15000c, -0xcc110000, -0x28d8001e, -0x31980001, -0x28dc001f, -0xc8200004, -0x95c00006, -0x7c424000, -0xcc000062, -0x7e56800c, -0xcc290000, -0xc8240004, -0x7e26000b, -0x95800006, -0x7c42c000, -0xcc000062, -0x7ed7000c, -0xcc310000, -0xc82c0004, -0x7e2e000c, -0xcc000062, -0x31103fff, -0x80000001, -0xce110000, -0x7c40c000, -0x80000001, -0xcc400040, -0x80000001, -0xcc412257, -0x7c418000, -0xcc400045, -0xcc400048, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xcc400045, -0xcc400048, -0x7c40c000, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xcc000045, -0xcc000048, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0x040ca1fd, -0xc0120001, -0xcc000045, -0xcc000048, -0x7cd0c00c, -0xcc41225c, -0xcc41a1fc, -0xd04d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x80000001, -0xcc41225d, -0x7c408000, -0x7c40c000, -0xc02a0002, -0x7c410000, -0x7d29000c, -0x30940001, -0x30980006, -0x309c0300, -0x29dc0008, -0x7c420000, -0x7c424000, -0x9540000f, -0xc02e0004, -0x05f02258, -0x7f2f000c, -0xcc310000, -0xc8280004, -0xccc12169, -0xcd01216a, -0xce81216b, -0x0db40002, -0xcc01216c, -0x9740000e, -0x0db40000, -0x8000007b, -0xc834000a, -0x0db40002, -0x97400009, -0x0db40000, -0xc02e0004, -0x05f02258, -0x7f2f000c, -0xcc310000, -0xc8280004, -0x8000007b, -0xc834000a, -0x97400004, -0x7e028000, -0x8000007b, -0xc834000a, -0x0db40004, -0x9740ff8c, -0x00000000, -0xce01216d, -0xce41216e, -0xc8280003, -0xc834000a, -0x9b400004, -0x043c0005, -0x8400026d, -0xcc000062, -0x0df40000, -0x9740000b, -0xc82c03e6, -0xce81a2b7, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c4, -0x80000001, -0xcfc1a2d1, -0x0df40001, -0x9740000b, -0xc82c03e7, -0xce81a2bb, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c5, -0x80000001, -0xcfc1a2d2, -0x0df40002, -0x9740000b, -0xc82c03e8, -0xce81a2bf, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c6, -0x80000001, -0xcfc1a2d3, -0xc82c03e9, -0xce81a2c3, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c7, -0x80000001, -0xcfc1a2d4, -0x80000001, -0xcc400042, -0x7c40c000, -0x7c410000, -0x2914001d, -0x31540001, -0x9940000d, -0x31181000, -0xc81c0011, -0x09dc0001, -0x95c0ffff, -0xc81c0011, -0xccc12100, -0xcd012101, -0xccc12102, -0xcd012103, -0x04180004, -0x8000039f, -0xcd81a2a4, -0xc02a0004, -0x95800008, -0x36a821a3, -0xcc290000, -0xc8280004, -0xc81c0011, -0x0de40040, -0x9640ffff, -0xc81c0011, -0xccc12170, -0xcd012171, -0xc8200012, -0x96000000, -0xc8200012, -0x8000039f, -0xcc000064, -0x7c40c000, -0x7c410000, -0xcc000045, -0xcc000048, -0x40d40003, -0xcd41225c, -0xcd01a1fc, -0xc01a0001, -0x041ca1fd, -0x7dd9c00c, -0x7c420000, -0x08cc0001, -0x06240001, -0x06280002, -0xce1d0000, -0xce5d0000, -0x98c0fffa, -0xce9d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0x30d00001, -0x28cc0001, -0x7c414000, -0x95000006, -0x7c418000, -0xcd41216d, -0xcd81216e, -0x800000f3, -0xc81c0003, -0xc0220004, -0x7e16000c, -0xcc210000, -0xc81c0004, -0x7c424000, -0x98c00004, -0x7c428000, -0x80000001, -0xcde50000, -0xce412169, -0xce81216a, -0xcdc1216b, -0x80000001, -0xcc01216c, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0x7c41c000, -0x28a40008, -0x326400ff, -0x0e68003c, -0x9680000a, -0x7c020000, -0x7c420000, -0x1e300003, -0xcc00006a, -0x9b000003, -0x42200005, -0x04200040, -0x80000110, -0x7c024000, -0x7e024000, -0x9a400000, -0x0a640001, -0x30ec0010, -0x9ac0000a, -0xcc000062, -0xc02a0004, -0xc82c0021, -0x7e92800c, -0xcc000041, -0xcc290000, -0xcec00021, -0x80000120, -0xc8300004, -0xcd01216d, -0xcd41216e, -0xc8300003, -0x7f1f000b, -0x30f40007, -0x27780001, -0x9740002a, -0x07b80125, -0x9f800000, -0x00000000, -0x80000135, -0x7f1b8004, -0x80000139, -0x7f1b8005, -0x8000013d, -0x7f1b8002, -0x80000141, -0x7f1b8003, -0x80000145, -0x7f1b8007, -0x80000149, -0x7f1b8006, -0x8000014e, -0x28a40008, -0x9b800019, -0x28a40008, -0x8000015e, -0x326400ff, -0x9b800015, -0x28a40008, -0x8000015e, -0x326400ff, -0x9b800011, -0x28a40008, -0x8000015e, -0x326400ff, -0x9b80000d, -0x28a40008, -0x8000015e, -0x326400ff, -0x9b800009, -0x28a40008, -0x8000015e, -0x326400ff, -0x9b800005, -0x28a40008, -0x8000015e, -0x326400ff, -0x28a40008, -0x326400ff, -0x0e68003c, -0x9a80feb1, -0x28ec0008, -0x7c434000, -0x7c438000, -0x7c43c000, -0x96c00007, -0xcc000062, -0xcf412169, -0xcf81216a, -0xcfc1216b, -0x80000001, -0xcc01216c, -0x80000001, -0xcff50000, -0xcc00006b, -0x840003a2, -0x0e68003c, -0x9a800004, -0xc8280015, -0x80000001, -0xd040007f, -0x9680ffab, -0x7e024000, -0x8400023b, -0xc00e0002, -0xcc000041, -0x80000239, -0xccc1304a, -0x7c40c000, -0x7c410000, -0xc01e0001, -0x29240012, -0xc0220002, -0x96400005, -0xc0260004, -0xc027fffb, -0x7d25000b, -0xc0260000, -0x7dd2800b, -0x7e12c00b, -0x7d25000c, -0x7c414000, -0x7c418000, -0xccc12169, -0x9a80000a, -0xcd01216a, -0xcd41216b, -0x96c0fe82, -0xcd81216c, -0xc8300018, -0x97000000, -0xc8300018, -0x80000001, -0xcc000018, -0x840003a2, -0xcc00007f, -0xc8140013, -0xc8180014, -0xcd41216b, -0x96c0fe76, -0xcd81216c, -0x80000182, -0xc8300018, -0xc80c0008, -0x98c00000, -0xc80c0008, -0x7c410000, -0x95000002, -0x00000000, -0x7c414000, -0xc8200009, -0xcc400043, -0xce01a1f4, -0xcc400044, -0xc00e8000, -0x7c424000, -0x7c428000, -0x2aac001f, -0x96c0fe63, -0xc035f000, -0xce4003e2, -0x32780003, -0x267c0008, -0x7ff7c00b, -0x7ffbc00c, -0x2a780018, -0xcfc003e3, -0xcf8003e4, -0x26b00002, -0x7f3f0000, -0xcf0003e5, -0x8000031f, -0x7c80c000, -0x7c40c000, -0x28d00008, -0x3110000f, -0x9500000f, -0x25280001, -0x06a801b3, -0x9e800000, -0x00000000, -0x800001d4, -0xc0120800, -0x800001e2, -0xc814000f, -0x800001e9, -0xc8140010, -0x800001f0, -0xccc1a2a4, -0x800001f9, -0xc8140011, -0x30d0003f, -0x0d280015, -0x9a800012, -0x0d28001e, -0x9a80001e, -0x0d280020, -0x9a800023, -0x0d24000f, -0x0d280010, -0x7e6a800c, -0x9a800026, -0x0d200004, -0x0d240014, -0x0d280028, -0x7e62400c, -0x7ea6800c, -0x9a80002a, -0xc8140011, -0x80000001, -0xccc1a2a4, -0xc0120800, -0x7c414000, -0x7d0cc00c, -0xc0120008, -0x29580003, -0x295c000c, -0x7c420000, -0x7dd1c00b, -0x26200014, -0x7e1e400c, -0x7e4e800c, -0xce81a2a4, -0x80000001, -0xcd81a1fe, -0xc814000f, -0x0410210e, -0x95400000, -0xc814000f, -0xd0510000, -0x80000001, -0xccc1a2a4, -0xc8140010, -0x04102108, -0x95400000, -0xc8140010, -0xd0510000, -0x80000001, -0xccc1a2a4, -0xccc1a2a4, -0x04100001, -0xcd000019, -0x840003a2, -0xcc00007f, -0xc8100019, -0x99000000, -0xc8100019, -0x80000002, -0x7c408000, -0x04102100, -0x09540001, -0x9540ffff, -0xc8140011, -0xd0510000, -0x8000039f, -0xccc1a2a4, -0x7c40c000, -0xcc40000d, -0x94c0fdff, -0xcc40000e, -0x7c410000, -0x95000005, -0x08cc0001, -0xc8140005, -0x99400014, -0x00000000, -0x98c0fffb, -0x7c410000, -0x80000002, -0x7d008000, -0xc8140005, -0x7c40c000, -0x9940000c, -0xc818000c, -0x7c410000, -0x9580fdee, -0xc820000e, -0xc81c000d, -0x66200020, -0x7e1e002c, -0x25240002, -0x7e624020, -0x80000001, -0xcce60000, -0x7c410000, -0xcc00006c, -0xcc00006d, -0xc818001f, -0xc81c001e, -0x65980020, -0x7dd9c02c, -0x7cd4c00c, -0xccde0000, -0x45dc0004, -0xc8280017, -0x9680000f, -0xc00e0001, -0x28680008, -0x2aac0016, -0x32a800ff, -0x0eb00049, -0x7f2f000b, -0x97000006, -0x00000000, -0xc8140005, -0x7c40c000, -0x80000223, -0x7c410000, -0x80000226, -0xd040007f, -0x8400023b, -0xcc000041, -0xccc1304a, -0x94000000, -0xc83c001a, -0x043c0005, -0xcfc1a2a4, -0xc0361f90, -0xc0387fff, -0x7c03c010, -0x7f7b400c, -0xcf41217c, -0xcfc1217d, -0xcc01217e, -0xc03a0004, -0x0434217f, -0x7f7b400c, -0xcc350000, -0xc83c0004, -0x2bfc001f, -0x04380020, -0x97c00005, -0xcc000062, -0x9b800000, -0x0bb80001, -0x80000247, -0xcc000071, -0xcc01a1f4, -0x04380016, -0xc0360002, -0xcf81a2a4, -0x88000000, -0xcf412010, -0x7c40c000, -0x28d0001c, -0x95000005, -0x04d40001, -0xcd400065, -0x80000001, -0xcd400068, -0x09540002, -0x80000001, -0xcd400066, -0x8400026c, -0xc81803ea, -0x7c40c000, -0x9980fd9d, -0xc8140016, -0x08d00001, -0x9940002b, -0xcd000068, -0x7c408000, -0xa0000000, -0xcc800062, -0x043c0005, -0xcfc1a2a4, -0xcc01a1f4, -0x840003a2, -0xcc000046, -0x88000000, -0xcc00007f, -0x8400027e, -0xc81803ea, -0x7c40c000, -0x9980fd8b, -0xc8140016, -0x08d00001, -0x99400019, -0xcd000068, -0x7c408000, -0xa0000000, -0xcc800062, -0x043c0022, -0xcfc1a2a4, -0x840003a2, -0xcc000047, -0x88000000, -0xcc00007f, -0xc8100016, -0x9900000d, -0xcc400067, -0x80000002, -0x7c408000, -0xc81803ea, -0x9980fd77, -0x7c40c000, -0x94c00003, -0xc8100016, -0x99000004, -0xccc00068, -0x80000002, -0x7c408000, -0x8400023b, -0xc0148000, -0xcc000041, -0xcd41304a, -0xc0148000, -0x99000000, -0xc8100016, -0x80000002, -0x7c408000, -0xc0120001, -0x7c51400c, -0x80000001, -0xd0550000, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0x291c001f, -0xccc0004a, -0xcd00004b, -0x95c00003, -0xc01c8000, -0xcdc12010, -0xdd830000, -0x055c2000, -0xcc000062, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc0004c, -0xcd00004d, -0xdd830000, -0x055ca000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc0004e, -0xcd00004f, -0xdd830000, -0x055cc000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00050, -0xcd000051, -0xdd830000, -0x055cf8e0, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00052, -0xcd000053, -0xdd830000, -0x055cf880, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00054, -0xcd000055, -0xdd830000, -0x055ce000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00056, -0xcd000057, -0xdd830000, -0x055cf000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00058, -0xcd000059, -0xdd830000, -0x055cf3fc, -0x80000001, -0xd81f4100, -0xd0432000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043a000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043c000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f8e0, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f880, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043e000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f3fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xc81403e0, -0xcc430000, -0xcc430000, -0xcc430000, -0x7d45c000, -0xcdc30000, -0xd0430000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0xc81003e2, -0xc81403e5, -0xc81803e3, -0xc81c03e4, -0xcd812169, -0xcdc1216a, -0xccc1216b, -0xcc01216c, -0x04200004, -0x7da18000, -0x7d964002, -0x9640fcd7, -0xcd8003e3, -0x31280003, -0xc02df000, -0x25180008, -0x7dad800b, -0x7da9800c, -0x80000001, -0xcd8003e3, -0x308cffff, -0xd04d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0x7c410000, -0x29240018, -0x32640001, -0x9a400013, -0xc8140020, -0x15580002, -0x9580ffff, -0xc8140020, -0xcc00006e, -0xccc12180, -0xcd01218d, -0xcc412181, -0x2914001f, -0x34588000, -0xcd81218c, -0x9540fcb9, -0xcc412182, -0xc8140020, -0x9940ffff, -0xc8140020, -0x80000002, -0x7c408000, -0x7c414000, -0x7c418000, -0x7c41c000, -0x65b40020, -0x7f57402c, -0xd4378100, -0x47740004, -0xd4378100, -0x47740004, -0xd4378100, -0x47740004, -0x09dc0004, -0xd4378100, -0x99c0fff8, -0x47740004, -0x2924001f, -0xc0380019, -0x9640fca1, -0xc03e0004, -0xcf8121f8, -0x37e021f9, -0xcc210000, -0xc8200004, -0x2a200018, -0x32200001, -0x9a00fffb, -0xcf8121f8, -0x80000002, -0x7c408000, -0x7c40c000, -0x28d00018, -0x31100001, -0xc0160080, -0x95000003, -0xc02a0004, -0x7cd4c00c, -0xccc1217c, -0xcc41217d, -0xcc41217e, -0x7c418000, -0x1db00003, -0x36a0217f, -0x9b000003, -0x419c0005, -0x041c0040, -0x99c00000, -0x09dc0001, -0xcc210000, -0xc8240004, -0x2a6c001f, -0x419c0005, -0x9ac0fffa, -0xcc800062, -0x80000002, -0x7c408000, -0x7c40c000, -0x04d403e6, -0x80000001, -0xcc540000, -0x8000039f, -0xcc4003ea, -0xc01c8000, -0x044ca000, -0xcdc12010, -0x7c410000, -0xc8140009, -0x04180000, -0x041c0008, -0xcd800071, -0x09dc0001, -0x05980001, -0xcd0d0000, -0x99c0fffc, -0xcc800062, -0x8000039f, -0xcd400071, -0xc00e0100, -0xcc000041, -0xccc1304a, -0xc83c007f, -0xcc00007f, -0x80000001, -0xcc00007f, -0xcc00007f, -0x88000000, -0xcc00007f, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00010333, -0x00100004, -0x00170006, -0x00210008, -0x00270028, -0x00280023, -0x00290029, -0x002a0026, -0x002b0029, -0x002d0038, -0x002e003f, -0x002f004a, -0x0034004c, -0x00360030, -0x003900af, -0x003a00d0, -0x003b00e5, -0x003c00fd, -0x003d016c, -0x003f00ad, -0x00410338, -0x0043036c, -0x0044018f, -0x004500fd, -0x004601ad, -0x004701ad, -0x00480200, -0x0049020e, -0x004a0257, -0x004b0284, -0x00520261, -0x00530273, -0x00540289, -0x0057029b, -0x0060029f, -0x006102ae, -0x006202b8, -0x006302c2, -0x006402cc, -0x006502d6, -0x006602e0, -0x006702ea, -0x006802f4, -0x006902f8, -0x006a02fc, -0x006b0300, -0x006c0304, -0x006d0308, -0x006e030c, -0x006f0310, -0x00700314, -0x00720386, -0x0074038c, -0x0079038a, -0x007c031e, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -0x000f039b, -}; - -static const u32 RV770_pfp_microcode[] = { -0x7c408000, -0xa0000000, -0x7e82800b, -0x80000000, -0xdc030000, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xc818000e, -0x31980001, -0x7c424000, -0x95800252, -0x7c428000, -0xc81c001c, -0xc037c000, -0x7c40c000, -0x7c410000, -0x7cb4800b, -0xc0360003, -0x99c00000, -0xc81c001c, -0x7cb4800c, -0x24d40002, -0x7d654000, -0xcd400043, -0xce800043, -0xcd000043, -0xcc800040, -0xce400040, -0xce800040, -0xccc00040, -0xdc3a0000, -0x9780ffde, -0xcd000040, -0x7c40c000, -0x80000018, -0x7c410000, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xc818000e, -0x8000000c, -0x31980002, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xc818000e, -0x288c0008, -0x30cc000f, -0x34100001, -0x7d0d0008, -0x8000000c, -0x7d91800b, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xcc4003f9, -0x80000261, -0xcc4003f8, -0xc82003f8, -0xc81c03f9, -0xc81803fb, -0xc037ffff, -0x7c414000, -0xcf41a29e, -0x66200020, -0x7de1c02c, -0x7d58c008, -0x7cdcc020, -0x68d00020, -0xc0360003, -0xcc000054, -0x7cb4800c, -0x8000006a, -0xcc800040, -0x7c418000, -0xcd81a29e, -0xcc800040, -0xcd800040, -0x80000068, -0xcc000054, -0xc019ffff, -0xcc800040, -0xcd81a29e, -0x7c40c000, -0x7c410000, -0x7c414000, -0xccc1a1fa, -0xcd01a1f9, -0xcd41a29d, -0xccc00040, -0xcd000040, -0xcd400040, -0xcc400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xcc000054, -0xcc800040, -0x7c40c000, -0x7c410000, -0x7c414000, -0xccc1a1fa, -0xcd01a1f9, -0xcd41a29d, -0xccc00040, -0xcd000040, -0xcd400040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0x7c40c000, -0x30d00001, -0xccc1a29f, -0x95000003, -0x04140001, -0x04140002, -0xcd4003fb, -0xcc800040, -0x80000000, -0xccc00040, -0x7c40c000, -0xcc800040, -0xccc1a2a2, -0x80000000, -0xccc00040, -0x7c40c000, -0x28d4001f, -0xcc800040, -0x95400003, -0x7c410000, -0xccc00057, -0x2918001f, -0xccc00040, -0x95800003, -0xcd000040, -0xcd000058, -0x80000261, -0xcc00007f, -0xc8200017, -0xc8300022, -0x9a000006, -0x0e280001, -0xc824001e, -0x0a640001, -0xd4001240, -0xce400040, -0xc036c000, -0x96800007, -0x37747900, -0x041c0001, -0xcf400040, -0xcdc00040, -0xcf0003fa, -0x7c030000, -0xca0c0010, -0x7c410000, -0x94c00004, -0x7c414000, -0xd42002c4, -0xcde00044, -0x9b00000b, -0x7c418000, -0xcc00004b, -0xcda00049, -0xcd200041, -0xcd600041, -0xcda00041, -0x06200001, -0xce000056, -0x80000261, -0xcc00007f, -0xc8280020, -0xc82c0021, -0xcc000063, -0x7eea4001, -0x65740020, -0x7f53402c, -0x269c0002, -0x7df5c020, -0x69f80020, -0xce80004b, -0xce600049, -0xcde00041, -0xcfa00041, -0xce600041, -0x271c0002, -0x7df5c020, -0x69f80020, -0x7db24001, -0xcf00004b, -0xce600049, -0xcde00041, -0xcfa00041, -0x800000bd, -0xce600041, -0xc8200017, -0xc8300022, -0x9a000006, -0x0e280001, -0xc824001e, -0x0a640001, -0xd4001240, -0xce400040, -0xca0c0010, -0x7c410000, -0x94c0000b, -0xc036c000, -0x96800007, -0x37747900, -0x041c0001, -0xcf400040, -0xcdc00040, -0xcf0003fa, -0x7c030000, -0x800000b6, -0x7c414000, -0xcc000048, -0x800000ef, -0x00000000, -0xc8200017, -0xc81c0023, -0x0e240002, -0x99c00015, -0x7c418000, -0x0a200001, -0xce000056, -0xd4000440, -0xcc000040, -0xc036c000, -0xca140013, -0x96400007, -0x37747900, -0xcf400040, -0xcc000040, -0xc83003fa, -0x80000104, -0xcf000022, -0xcc000022, -0x9540015d, -0xcc00007f, -0xcca00046, -0x80000000, -0xcc200046, -0x80000261, -0xcc000064, -0xc8200017, -0xc810001f, -0x96000005, -0x09100001, -0xd4000440, -0xcd000040, -0xcd000022, -0xcc800040, -0xd0400040, -0xc80c0025, -0x94c0feeb, -0xc8100008, -0xcd000040, -0xd4000fc0, -0x80000000, -0xd4000fa2, -0x7c40c000, -0x7c410000, -0xccc003fd, -0xcd0003fc, -0xccc00042, -0xcd000042, -0x2914001f, -0x29180010, -0x31980007, -0x3b5c0001, -0x7d76000b, -0x99800005, -0x7d5e400b, -0xcc000042, -0x80000261, -0xcc00004d, -0x29980001, -0x292c0008, -0x9980003d, -0x32ec0001, -0x96000004, -0x2930000c, -0x80000261, -0xcc000042, -0x04140010, -0xcd400042, -0x33300001, -0x34280001, -0x8400015e, -0xc8140003, -0x9b40001b, -0x0438000c, -0x8400015e, -0xc8140003, -0x9b400017, -0x04380008, -0x8400015e, -0xc8140003, -0x9b400013, -0x04380004, -0x8400015e, -0xc8140003, -0x9b400015, -0xc80c03fd, -0x9a800009, -0xc81003fc, -0x9b000118, -0xcc00004d, -0x04140010, -0xccc00042, -0xcd000042, -0x80000136, -0xcd400042, -0x96c00111, -0xcc00004d, -0x80000261, -0xcc00004e, -0x9ac00003, -0xcc00004d, -0xcc00004e, -0xdf830000, -0x80000000, -0xd80301ff, -0x9ac00107, -0xcc00004d, -0x80000261, -0xcc00004e, -0xc8180003, -0xc81c0003, -0xc8200003, -0x7d5d4003, -0x7da1c003, -0x7d5d400c, -0x2a10001f, -0x299c001f, -0x7d1d000b, -0x7d17400b, -0x88000000, -0x7e92800b, -0x96400004, -0xcc00004e, -0x80000261, -0xcc000042, -0x04380008, -0xcf800042, -0xc8080003, -0xc80c0003, -0xc8100003, -0xc8140003, -0xc8180003, -0xc81c0003, -0xc8240003, -0xc8280003, -0x29fc001f, -0x2ab0001f, -0x7ff3c00b, -0x28f0001f, -0x7ff3c00b, -0x2970001f, -0x7ff3c00b, -0x7d888001, -0x7dccc001, -0x7e510001, -0x7e954001, -0x7c908002, -0x7cd4c002, -0x7cbc800b, -0x9ac00003, -0x7c8f400b, -0x38b40001, -0x9b4000d8, -0xcc00004d, -0x9bc000d6, -0xcc00004e, -0xc80c03fd, -0xc81003fc, -0xccc00042, -0x8000016f, -0xcd000042, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xcc400040, -0xcc400040, -0xcc400040, -0x7c40c000, -0xccc00040, -0xccc0000d, -0x80000000, -0xd0400040, -0x7c40c000, -0x7c410000, -0x65140020, -0x7d4d402c, -0x24580002, -0x7d598020, -0x7c41c000, -0xcd800042, -0x69980020, -0xcd800042, -0xcdc00042, -0xc023c000, -0x05e40002, -0x7ca0800b, -0x26640010, -0x7ca4800c, -0xcc800040, -0xcdc00040, -0xccc00040, -0x95c0000e, -0xcd000040, -0x09dc0001, -0xc8280003, -0x96800008, -0xce800040, -0xc834001d, -0x97400000, -0xc834001d, -0x26a80008, -0x84000264, -0xcc2b0000, -0x99c0fff7, -0x09dc0001, -0xdc3a0000, -0x97800004, -0x7c418000, -0x800001a3, -0x25980002, -0xa0000000, -0x7d808000, -0xc818001d, -0x7c40c000, -0x64d00008, -0x95800000, -0xc818001d, -0xcc130000, -0xcc800040, -0xccc00040, -0x80000000, -0xcc400040, -0xc810001f, -0x7c40c000, -0xcc800040, -0x7cd1400c, -0xcd400040, -0x05180001, -0x80000000, -0xcd800022, -0x7c40c000, -0x64500020, -0x84000264, -0xcc000061, -0x7cd0c02c, -0xc8200017, -0xc8d60000, -0x99400008, -0x7c438000, -0xdf830000, -0xcfa0004f, -0x84000264, -0xcc000062, -0x80000000, -0xd040007f, -0x80000261, -0xcc000062, -0x84000264, -0xcc000061, -0xc8200017, -0x7c40c000, -0xc036ff00, -0xc810000d, -0xc0303fff, -0x7cf5400b, -0x7d51800b, -0x7d81800f, -0x99800008, -0x7cf3800b, -0xdf830000, -0xcfa0004f, -0x84000264, -0xcc000062, -0x80000000, -0xd040007f, -0x80000261, -0xcc000062, -0x84000264, -0x7c40c000, -0x28dc0008, -0x95c00019, -0x30dc0010, -0x7c410000, -0x99c00004, -0x64540020, -0x80000209, -0xc91d0000, -0x7d15002c, -0xc91e0000, -0x7c420000, -0x7c424000, -0x7c418000, -0x7de5c00b, -0x7de28007, -0x9a80000e, -0x41ac0005, -0x9ac00000, -0x0aec0001, -0x30dc0010, -0x99c00004, -0x00000000, -0x8000020c, -0xc91d0000, -0x8000020c, -0xc91e0000, -0xcc800040, -0xccc00040, -0xd0400040, -0xc80c0025, -0x94c0fde3, -0xc8100008, -0xcd000040, -0xd4000fc0, -0x80000000, -0xd4000fa2, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0x7c40c000, -0x30d00006, -0x0d100006, -0x99000007, -0xc8140015, -0x99400005, -0xcc000052, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xccc00040, -0x80000000, -0xd0400040, -0x7c40c000, -0xcc4d0000, -0xdc3a0000, -0x9780fdbc, -0x04cc0001, -0x80000243, -0xcc4d0000, -0x7c40c000, -0x7c410000, -0x29240018, -0x32640001, -0x9640000f, -0xcc800040, -0x7c414000, -0x7c418000, -0x7c41c000, -0xccc00043, -0xcd000043, -0x31dc7fff, -0xcdc00043, -0xccc00040, -0xcd000040, -0xcd400040, -0xcd800040, -0x80000000, -0xcdc00040, -0xccc00040, -0xcd000040, -0x80000000, -0xd0400040, -0x80000000, -0xd040007f, -0xcc00007f, -0x80000000, -0xcc00007f, -0xcc00007f, -0x88000000, -0xcc00007f, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00030223, -0x0004022b, -0x000500a0, -0x00020003, -0x0006003c, -0x00070027, -0x00080192, -0x00090044, -0x000a002d, -0x0010025f, -0x001700f1, -0x002201d8, -0x002301e9, -0x0026004c, -0x0027005f, -0x0020011b, -0x00280093, -0x0029004f, -0x002a0084, -0x002b0065, -0x002f008e, -0x003200d9, -0x00340233, -0x00360075, -0x0039010b, -0x003c01fd, -0x003f00a0, -0x00410248, -0x00440195, -0x0048019e, -0x004901c6, -0x004a01d0, -0x00550226, -0x0056022e, -0x0060000a, -0x0061002a, -0x00620030, -0x00630030, -0x00640030, -0x00650030, -0x00660030, -0x00670030, -0x00680037, -0x0069003f, -0x006a0047, -0x006b0047, -0x006c0047, -0x006d0047, -0x006e0047, -0x006f0047, -0x00700047, -0x0073025f, -0x007b0241, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -}; - -static const u32 RV730_pfp_microcode[] = { -0x7c408000, -0xa0000000, -0x7e82800b, -0x80000000, -0xdc030000, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xc818000e, -0x31980001, -0x7c424000, -0x9580023a, -0x7c428000, -0xc81c001c, -0xc037c000, -0x7c40c000, -0x7c410000, -0x7cb4800b, -0xc0360003, -0x99c00000, -0xc81c001c, -0x7cb4800c, -0x24d40002, -0x7d654000, -0xcd400043, -0xce800043, -0xcd000043, -0xcc800040, -0xce400040, -0xce800040, -0xccc00040, -0xdc3a0000, -0x9780ffde, -0xcd000040, -0x7c40c000, -0x80000018, -0x7c410000, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xc818000e, -0x8000000c, -0x31980002, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xc818000e, -0x288c0008, -0x30cc000f, -0x34100001, -0x7d0d0008, -0x8000000c, -0x7d91800b, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xcc4003f9, -0x80000249, -0xcc4003f8, -0xc037ffff, -0x7c414000, -0xcf41a29e, -0xc82003f8, -0xc81c03f9, -0x66200020, -0xc81803fb, -0x7de1c02c, -0x7d58c008, -0x7cdcc020, -0x69100020, -0xc0360003, -0xcc000054, -0x7cb4800c, -0x80000069, -0xcc800040, -0x7c418000, -0xcd81a29e, -0xcc800040, -0x80000067, -0xcd800040, -0xc019ffff, -0xcc800040, -0xcd81a29e, -0x7c40c000, -0x7c410000, -0x7c414000, -0xccc1a1fa, -0xcd01a1f9, -0xcd41a29d, -0xccc00040, -0xcd000040, -0xcd400040, -0xcc400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xcc000054, -0xcc800040, -0x7c40c000, -0x7c410000, -0x7c414000, -0xccc1a1fa, -0xcd01a1f9, -0xcd41a29d, -0xccc00040, -0xcd000040, -0xcd400040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0x7c40c000, -0x30d00001, -0xccc1a29f, -0x95000003, -0x04140001, -0x04140002, -0xcd4003fb, -0xcc800040, -0x80000000, -0xccc00040, -0x7c40c000, -0xcc800040, -0xccc1a2a2, -0x80000000, -0xccc00040, -0x7c40c000, -0x28d4001f, -0xcc800040, -0x95400003, -0x7c410000, -0xccc00057, -0x2918001f, -0xccc00040, -0x95800003, -0xcd000040, -0xcd000058, -0x80000249, -0xcc00007f, -0xc8200017, -0xc8300022, -0x9a000006, -0x0e280001, -0xc824001e, -0x0a640001, -0xd4001240, -0xce400040, -0xc036c000, -0x96800007, -0x37747900, -0x041c0001, -0xcf400040, -0xcdc00040, -0xcf0003fa, -0x7c030000, -0xca0c0010, -0x7c410000, -0x94c00004, -0x7c414000, -0xd42002c4, -0xcde00044, -0x9b00000b, -0x7c418000, -0xcc00004b, -0xcda00049, -0xcd200041, -0xcd600041, -0xcda00041, -0x06200001, -0xce000056, -0x80000249, -0xcc00007f, -0xc8280020, -0xc82c0021, -0xcc000063, -0x7eea4001, -0x65740020, -0x7f53402c, -0x269c0002, -0x7df5c020, -0x69f80020, -0xce80004b, -0xce600049, -0xcde00041, -0xcfa00041, -0xce600041, -0x271c0002, -0x7df5c020, -0x69f80020, -0x7db24001, -0xcf00004b, -0xce600049, -0xcde00041, -0xcfa00041, -0x800000bc, -0xce600041, -0xc8200017, -0xc8300022, -0x9a000006, -0x0e280001, -0xc824001e, -0x0a640001, -0xd4001240, -0xce400040, -0xca0c0010, -0x7c410000, -0x94c0000b, -0xc036c000, -0x96800007, -0x37747900, -0x041c0001, -0xcf400040, -0xcdc00040, -0xcf0003fa, -0x7c030000, -0x800000b5, -0x7c414000, -0xcc000048, -0x800000ee, -0x00000000, -0xc8200017, -0xc81c0023, -0x0e240002, -0x99c00015, -0x7c418000, -0x0a200001, -0xce000056, -0xd4000440, -0xcc000040, -0xc036c000, -0xca140013, -0x96400007, -0x37747900, -0xcf400040, -0xcc000040, -0xc83003fa, -0x80000103, -0xcf000022, -0xcc000022, -0x95400146, -0xcc00007f, -0xcca00046, -0x80000000, -0xcc200046, -0x80000249, -0xcc000064, -0xc8200017, -0xc810001f, -0x96000005, -0x09100001, -0xd4000440, -0xcd000040, -0xcd000022, -0xcc800040, -0xd0400040, -0xc80c0025, -0x94c0feec, -0xc8100008, -0xcd000040, -0xd4000fc0, -0x80000000, -0xd4000fa2, -0x7c40c000, -0x7c410000, -0xccc003fd, -0xcd0003fc, -0xccc00042, -0xcd000042, -0x2914001f, -0x29180010, -0x31980007, -0x3b5c0001, -0x7d76000b, -0x99800005, -0x7d5e400b, -0xcc000042, -0x80000249, -0xcc00004d, -0x29980001, -0x292c0008, -0x9980003d, -0x32ec0001, -0x96000004, -0x2930000c, -0x80000249, -0xcc000042, -0x04140010, -0xcd400042, -0x33300001, -0x34280001, -0x8400015d, -0xc8140003, -0x9b40001b, -0x0438000c, -0x8400015d, -0xc8140003, -0x9b400017, -0x04380008, -0x8400015d, -0xc8140003, -0x9b400013, -0x04380004, -0x8400015d, -0xc8140003, -0x9b400015, -0xc80c03fd, -0x9a800009, -0xc81003fc, -0x9b000101, -0xcc00004d, -0x04140010, -0xccc00042, -0xcd000042, -0x80000135, -0xcd400042, -0x96c000fa, -0xcc00004d, -0x80000249, -0xcc00004e, -0x9ac00003, -0xcc00004d, -0xcc00004e, -0xdf830000, -0x80000000, -0xd80301ff, -0x9ac000f0, -0xcc00004d, -0x80000249, -0xcc00004e, -0xc8180003, -0xc81c0003, -0xc8200003, -0x7d5d4003, -0x7da1c003, -0x7d5d400c, -0x2a10001f, -0x299c001f, -0x7d1d000b, -0x7d17400b, -0x88000000, -0x7e92800b, -0x96400004, -0xcc00004e, -0x80000249, -0xcc000042, -0x04380008, -0xcf800042, -0xc8080003, -0xc80c0003, -0xc8100003, -0xc8140003, -0xc8180003, -0xc81c0003, -0xc8240003, -0xc8280003, -0x29fc001f, -0x2ab0001f, -0x7ff3c00b, -0x28f0001f, -0x7ff3c00b, -0x2970001f, -0x7ff3c00b, -0x7d888001, -0x7dccc001, -0x7e510001, -0x7e954001, -0x7c908002, -0x7cd4c002, -0x7cbc800b, -0x9ac00003, -0x7c8f400b, -0x38b40001, -0x9b4000c1, -0xcc00004d, -0x9bc000bf, -0xcc00004e, -0xc80c03fd, -0xc81003fc, -0xccc00042, -0x8000016e, -0xcd000042, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xcc400040, -0xcc400040, -0xcc400040, -0x7c40c000, -0xccc00040, -0xccc0000d, -0x80000000, -0xd0400040, -0x7c40c000, -0x7c410000, -0x65140020, -0x7d4d402c, -0x24580002, -0x7d598020, -0x7c41c000, -0xcd800042, -0x69980020, -0xcd800042, -0xcdc00042, -0xc023c000, -0x05e40002, -0x7ca0800b, -0x26640010, -0x7ca4800c, -0xcc800040, -0xcdc00040, -0xccc00040, -0x95c0000e, -0xcd000040, -0x09dc0001, -0xc8280003, -0x96800008, -0xce800040, -0xc834001d, -0x97400000, -0xc834001d, -0x26a80008, -0x8400024c, -0xcc2b0000, -0x99c0fff7, -0x09dc0001, -0xdc3a0000, -0x97800004, -0x7c418000, -0x800001a2, -0x25980002, -0xa0000000, -0x7d808000, -0xc818001d, -0x7c40c000, -0x64d00008, -0x95800000, -0xc818001d, -0xcc130000, -0xcc800040, -0xccc00040, -0x80000000, -0xcc400040, -0xc810001f, -0x7c40c000, -0xcc800040, -0x7cd1400c, -0xcd400040, -0x05180001, -0x80000000, -0xcd800022, -0x7c40c000, -0x64500020, -0x8400024c, -0xcc000061, -0x7cd0c02c, -0xc8200017, -0xc8d60000, -0x99400008, -0x7c438000, -0xdf830000, -0xcfa0004f, -0x8400024c, -0xcc000062, -0x80000000, -0xd040007f, -0x80000249, -0xcc000062, -0x8400024c, -0xcc000061, -0xc8200017, -0x7c40c000, -0xc036ff00, -0xc810000d, -0xc0303fff, -0x7cf5400b, -0x7d51800b, -0x7d81800f, -0x99800008, -0x7cf3800b, -0xdf830000, -0xcfa0004f, -0x8400024c, -0xcc000062, -0x80000000, -0xd040007f, -0x80000249, -0xcc000062, -0x8400024c, -0x7c40c000, -0x28dc0008, -0x95c00019, -0x30dc0010, -0x7c410000, -0x99c00004, -0x64540020, -0x80000208, -0xc91d0000, -0x7d15002c, -0xc91e0000, -0x7c420000, -0x7c424000, -0x7c418000, -0x7de5c00b, -0x7de28007, -0x9a80000e, -0x41ac0005, -0x9ac00000, -0x0aec0001, -0x30dc0010, -0x99c00004, -0x00000000, -0x8000020b, -0xc91d0000, -0x8000020b, -0xc91e0000, -0xcc800040, -0xccc00040, -0xd0400040, -0xc80c0025, -0x94c0fde4, -0xc8100008, -0xcd000040, -0xd4000fc0, -0x80000000, -0xd4000fa2, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0x7c40c000, -0x30d00006, -0x0d100006, -0x99000007, -0xc8140015, -0x99400005, -0xcc000052, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xccc00040, -0x80000000, -0xd0400040, -0x7c40c000, -0xcc4d0000, -0xdc3a0000, -0x9780fdbd, -0x04cc0001, -0x80000242, -0xcc4d0000, -0x80000000, -0xd040007f, -0xcc00007f, -0x80000000, -0xcc00007f, -0xcc00007f, -0x88000000, -0xcc00007f, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00030222, -0x0004022a, -0x0005009f, -0x00020003, -0x0006003c, -0x00070027, -0x00080191, -0x00090044, -0x000a002d, -0x00100247, -0x001700f0, -0x002201d7, -0x002301e8, -0x0026004c, -0x0027005f, -0x0020011a, -0x00280092, -0x0029004f, -0x002a0083, -0x002b0064, -0x002f008d, -0x003200d8, -0x00340232, -0x00360074, -0x0039010a, -0x003c01fc, -0x003f009f, -0x00410005, -0x00440194, -0x0048019d, -0x004901c5, -0x004a01cf, -0x00550225, -0x0056022d, -0x0060000a, -0x0061002a, -0x00620030, -0x00630030, -0x00640030, -0x00650030, -0x00660030, -0x00670030, -0x00680037, -0x0069003f, -0x006a0047, -0x006b0047, -0x006c0047, -0x006d0047, -0x006e0047, -0x006f0047, -0x00700047, -0x00730247, -0x007b0240, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -}; - -static const u32 RV730_cp_microcode[] = { -0xcc0003ea, -0x7c408000, -0xa0000000, -0xcc800062, -0x80000001, -0xd040007f, -0x80000001, -0xcc400041, -0x7c40c000, -0xc0160004, -0x30d03fff, -0x7d15000c, -0xcc110000, -0x28d8001e, -0x31980001, -0x28dc001f, -0xc8200004, -0x95c00006, -0x7c424000, -0xcc000062, -0x7e56800c, -0xcc290000, -0xc8240004, -0x7e26000b, -0x95800006, -0x7c42c000, -0xcc000062, -0x7ed7000c, -0xcc310000, -0xc82c0004, -0x7e2e000c, -0xcc000062, -0x31103fff, -0x80000001, -0xce110000, -0x7c40c000, -0x80000001, -0xcc400040, -0x80000001, -0xcc412257, -0x7c418000, -0xcc400045, -0xcc400048, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xcc400045, -0xcc400048, -0x7c40c000, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xcc000045, -0xcc000048, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0x040ca1fd, -0xc0120001, -0xcc000045, -0xcc000048, -0x7cd0c00c, -0xcc41225c, -0xcc41a1fc, -0xd04d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x80000001, -0xcc41225d, -0x7c408000, -0x7c40c000, -0xc02a0002, -0x7c410000, -0x7d29000c, -0x30940001, -0x30980006, -0x309c0300, -0x29dc0008, -0x7c420000, -0x7c424000, -0x9540000f, -0xc02e0004, -0x05f02258, -0x7f2f000c, -0xcc310000, -0xc8280004, -0xccc12169, -0xcd01216a, -0xce81216b, -0x0db40002, -0xcc01216c, -0x9740000e, -0x0db40000, -0x8000007b, -0xc834000a, -0x0db40002, -0x97400009, -0x0db40000, -0xc02e0004, -0x05f02258, -0x7f2f000c, -0xcc310000, -0xc8280004, -0x8000007b, -0xc834000a, -0x97400004, -0x7e028000, -0x8000007b, -0xc834000a, -0x0db40004, -0x9740ff8c, -0x00000000, -0xce01216d, -0xce41216e, -0xc8280003, -0xc834000a, -0x9b400004, -0x043c0005, -0x8400026b, -0xcc000062, -0x0df40000, -0x9740000b, -0xc82c03e6, -0xce81a2b7, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c4, -0x80000001, -0xcfc1a2d1, -0x0df40001, -0x9740000b, -0xc82c03e7, -0xce81a2bb, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c5, -0x80000001, -0xcfc1a2d2, -0x0df40002, -0x9740000b, -0xc82c03e8, -0xce81a2bf, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c6, -0x80000001, -0xcfc1a2d3, -0xc82c03e9, -0xce81a2c3, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c7, -0x80000001, -0xcfc1a2d4, -0x80000001, -0xcc400042, -0x7c40c000, -0x7c410000, -0x2914001d, -0x31540001, -0x9940000c, -0x31181000, -0xc81c0011, -0x95c00000, -0xc81c0011, -0xccc12100, -0xcd012101, -0xccc12102, -0xcd012103, -0x04180004, -0x8000037c, -0xcd81a2a4, -0xc02a0004, -0x95800008, -0x36a821a3, -0xcc290000, -0xc8280004, -0xc81c0011, -0x0de40040, -0x9640ffff, -0xc81c0011, -0xccc12170, -0xcd012171, -0xc8200012, -0x96000000, -0xc8200012, -0x8000037c, -0xcc000064, -0x7c40c000, -0x7c410000, -0xcc000045, -0xcc000048, -0x40d40003, -0xcd41225c, -0xcd01a1fc, -0xc01a0001, -0x041ca1fd, -0x7dd9c00c, -0x7c420000, -0x08cc0001, -0x06240001, -0x06280002, -0xce1d0000, -0xce5d0000, -0x98c0fffa, -0xce9d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0x30d00001, -0x28cc0001, -0x7c414000, -0x95000006, -0x7c418000, -0xcd41216d, -0xcd81216e, -0x800000f2, -0xc81c0003, -0xc0220004, -0x7e16000c, -0xcc210000, -0xc81c0004, -0x7c424000, -0x98c00004, -0x7c428000, -0x80000001, -0xcde50000, -0xce412169, -0xce81216a, -0xcdc1216b, -0x80000001, -0xcc01216c, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0x7c41c000, -0x28a40008, -0x326400ff, -0x0e68003c, -0x9680000a, -0x7c020000, -0x7c420000, -0x1e300003, -0xcc00006a, -0x9b000003, -0x42200005, -0x04200040, -0x8000010f, -0x7c024000, -0x7e024000, -0x9a400000, -0x0a640001, -0x30ec0010, -0x9ac0000a, -0xcc000062, -0xc02a0004, -0xc82c0021, -0x7e92800c, -0xcc000041, -0xcc290000, -0xcec00021, -0x8000011f, -0xc8300004, -0xcd01216d, -0xcd41216e, -0xc8300003, -0x7f1f000b, -0x30f40007, -0x27780001, -0x9740002a, -0x07b80124, -0x9f800000, -0x00000000, -0x80000134, -0x7f1b8004, -0x80000138, -0x7f1b8005, -0x8000013c, -0x7f1b8002, -0x80000140, -0x7f1b8003, -0x80000144, -0x7f1b8007, -0x80000148, -0x7f1b8006, -0x8000014d, -0x28a40008, -0x9b800019, -0x28a40008, -0x8000015d, -0x326400ff, -0x9b800015, -0x28a40008, -0x8000015d, -0x326400ff, -0x9b800011, -0x28a40008, -0x8000015d, -0x326400ff, -0x9b80000d, -0x28a40008, -0x8000015d, -0x326400ff, -0x9b800009, -0x28a40008, -0x8000015d, -0x326400ff, -0x9b800005, -0x28a40008, -0x8000015d, -0x326400ff, -0x28a40008, -0x326400ff, -0x0e68003c, -0x9a80feb2, -0x28ec0008, -0x7c434000, -0x7c438000, -0x7c43c000, -0x96c00007, -0xcc000062, -0xcf412169, -0xcf81216a, -0xcfc1216b, -0x80000001, -0xcc01216c, -0x80000001, -0xcff50000, -0xcc00006b, -0x8400037f, -0x0e68003c, -0x9a800004, -0xc8280015, -0x80000001, -0xd040007f, -0x9680ffab, -0x7e024000, -0x84000239, -0xc00e0002, -0xcc000041, -0x80000237, -0xccc1304a, -0x7c40c000, -0x7c410000, -0xc01e0001, -0x29240012, -0xc0220002, -0x96400005, -0xc0260004, -0xc027fffb, -0x7d25000b, -0xc0260000, -0x7dd2800b, -0x7e12c00b, -0x7d25000c, -0x7c414000, -0x7c418000, -0xccc12169, -0x9a80000a, -0xcd01216a, -0xcd41216b, -0x96c0fe83, -0xcd81216c, -0xc8300018, -0x97000000, -0xc8300018, -0x80000001, -0xcc000018, -0x8400037f, -0xcc00007f, -0xc8140013, -0xc8180014, -0xcd41216b, -0x96c0fe77, -0xcd81216c, -0x80000181, -0xc8300018, -0xc80c0008, -0x98c00000, -0xc80c0008, -0x7c410000, -0x95000002, -0x00000000, -0x7c414000, -0xc8200009, -0xcc400043, -0xce01a1f4, -0xcc400044, -0xc00e8000, -0x7c424000, -0x7c428000, -0x2aac001f, -0x96c0fe64, -0xc035f000, -0xce4003e2, -0x32780003, -0x267c0008, -0x7ff7c00b, -0x7ffbc00c, -0x2a780018, -0xcfc003e3, -0xcf8003e4, -0x26b00002, -0x7f3f0000, -0xcf0003e5, -0x8000031d, -0x7c80c000, -0x7c40c000, -0x28d00008, -0x3110000f, -0x9500000f, -0x25280001, -0x06a801b2, -0x9e800000, -0x00000000, -0x800001d3, -0xc0120800, -0x800001e1, -0xc814000f, -0x800001e8, -0xc8140010, -0x800001ef, -0xccc1a2a4, -0x800001f8, -0xc8140011, -0x30d0003f, -0x0d280015, -0x9a800012, -0x0d28001e, -0x9a80001e, -0x0d280020, -0x9a800023, -0x0d24000f, -0x0d280010, -0x7e6a800c, -0x9a800026, -0x0d200004, -0x0d240014, -0x0d280028, -0x7e62400c, -0x7ea6800c, -0x9a80002a, -0xc8140011, -0x80000001, -0xccc1a2a4, -0xc0120800, -0x7c414000, -0x7d0cc00c, -0xc0120008, -0x29580003, -0x295c000c, -0x7c420000, -0x7dd1c00b, -0x26200014, -0x7e1e400c, -0x7e4e800c, -0xce81a2a4, -0x80000001, -0xcd81a1fe, -0xc814000f, -0x0410210e, -0x95400000, -0xc814000f, -0xd0510000, -0x80000001, -0xccc1a2a4, -0xc8140010, -0x04102108, -0x95400000, -0xc8140010, -0xd0510000, -0x80000001, -0xccc1a2a4, -0xccc1a2a4, -0x04100001, -0xcd000019, -0x8400037f, -0xcc00007f, -0xc8100019, -0x99000000, -0xc8100019, -0x80000002, -0x7c408000, -0x04102100, -0x95400000, -0xc8140011, -0xd0510000, -0x8000037c, -0xccc1a2a4, -0x7c40c000, -0xcc40000d, -0x94c0fe01, -0xcc40000e, -0x7c410000, -0x95000005, -0x08cc0001, -0xc8140005, -0x99400014, -0x00000000, -0x98c0fffb, -0x7c410000, -0x80000002, -0x7d008000, -0xc8140005, -0x7c40c000, -0x9940000c, -0xc818000c, -0x7c410000, -0x9580fdf0, -0xc820000e, -0xc81c000d, -0x66200020, -0x7e1e002c, -0x25240002, -0x7e624020, -0x80000001, -0xcce60000, -0x7c410000, -0xcc00006c, -0xcc00006d, -0xc818001f, -0xc81c001e, -0x65980020, -0x7dd9c02c, -0x7cd4c00c, -0xccde0000, -0x45dc0004, -0xc8280017, -0x9680000f, -0xc00e0001, -0x28680008, -0x2aac0016, -0x32a800ff, -0x0eb00049, -0x7f2f000b, -0x97000006, -0x00000000, -0xc8140005, -0x7c40c000, -0x80000221, -0x7c410000, -0x80000224, -0xd040007f, -0x84000239, -0xcc000041, -0xccc1304a, -0x94000000, -0xc83c001a, -0x043c0005, -0xcfc1a2a4, -0xc0361f90, -0xc0387fff, -0x7c03c010, -0x7f7b400c, -0xcf41217c, -0xcfc1217d, -0xcc01217e, -0xc03a0004, -0x0434217f, -0x7f7b400c, -0xcc350000, -0xc83c0004, -0x2bfc001f, -0x04380020, -0x97c00005, -0xcc000062, -0x9b800000, -0x0bb80001, -0x80000245, -0xcc000071, -0xcc01a1f4, -0x04380016, -0xc0360002, -0xcf81a2a4, -0x88000000, -0xcf412010, -0x7c40c000, -0x28d0001c, -0x95000005, -0x04d40001, -0xcd400065, -0x80000001, -0xcd400068, -0x09540002, -0x80000001, -0xcd400066, -0x8400026a, -0xc81803ea, -0x7c40c000, -0x9980fd9f, -0xc8140016, -0x08d00001, -0x9940002b, -0xcd000068, -0x7c408000, -0xa0000000, -0xcc800062, -0x043c0005, -0xcfc1a2a4, -0xcc01a1f4, -0x8400037f, -0xcc000046, -0x88000000, -0xcc00007f, -0x8400027c, -0xc81803ea, -0x7c40c000, -0x9980fd8d, -0xc8140016, -0x08d00001, -0x99400019, -0xcd000068, -0x7c408000, -0xa0000000, -0xcc800062, -0x043c0022, -0xcfc1a2a4, -0x8400037f, -0xcc000047, -0x88000000, -0xcc00007f, -0xc8100016, -0x9900000d, -0xcc400067, -0x80000002, -0x7c408000, -0xc81803ea, -0x9980fd79, -0x7c40c000, -0x94c00003, -0xc8100016, -0x99000004, -0xccc00068, -0x80000002, -0x7c408000, -0x84000239, -0xc0148000, -0xcc000041, -0xcd41304a, -0xc0148000, -0x99000000, -0xc8100016, -0x80000002, -0x7c408000, -0xc0120001, -0x7c51400c, -0x80000001, -0xd0550000, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0x291c001f, -0xccc0004a, -0xcd00004b, -0x95c00003, -0xc01c8000, -0xcdc12010, -0xdd830000, -0x055c2000, -0xcc000062, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc0004c, -0xcd00004d, -0xdd830000, -0x055ca000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc0004e, -0xcd00004f, -0xdd830000, -0x055cc000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00050, -0xcd000051, -0xdd830000, -0x055cf8e0, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00052, -0xcd000053, -0xdd830000, -0x055cf880, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00054, -0xcd000055, -0xdd830000, -0x055ce000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00056, -0xcd000057, -0xdd830000, -0x055cf000, -0x80000001, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00058, -0xcd000059, -0xdd830000, -0x055cf3fc, -0x80000001, -0xd81f4100, -0xd0432000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043a000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043c000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f8e0, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f880, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043e000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f3fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xc81403e0, -0xcc430000, -0xcc430000, -0xcc430000, -0x7d45c000, -0xcdc30000, -0xd0430000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0xc81003e2, -0xc81403e5, -0xc81803e3, -0xc81c03e4, -0xcd812169, -0xcdc1216a, -0xccc1216b, -0xcc01216c, -0x04200004, -0x7da18000, -0x7d964002, -0x9640fcd9, -0xcd8003e3, -0x31280003, -0xc02df000, -0x25180008, -0x7dad800b, -0x7da9800c, -0x80000001, -0xcd8003e3, -0x308cffff, -0xd04d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0xc8140020, -0x15580002, -0x9580ffff, -0xc8140020, -0xcc00006e, -0xcc412180, -0x7c40c000, -0xccc1218d, -0xcc412181, -0x28d0001f, -0x34588000, -0xcd81218c, -0x9500fcbf, -0xcc412182, -0xc8140020, -0x9940ffff, -0xc8140020, -0x80000002, -0x7c408000, -0x7c40c000, -0x28d00018, -0x31100001, -0xc0160080, -0x95000003, -0xc02a0004, -0x7cd4c00c, -0xccc1217c, -0xcc41217d, -0xcc41217e, -0x7c418000, -0x1db00003, -0x36a0217f, -0x9b000003, -0x419c0005, -0x041c0040, -0x99c00000, -0x09dc0001, -0xcc210000, -0xc8240004, -0x2a6c001f, -0x419c0005, -0x9ac0fffa, -0xcc800062, -0x80000002, -0x7c408000, -0x7c40c000, -0x04d403e6, -0x80000001, -0xcc540000, -0x8000037c, -0xcc4003ea, -0xc01c8000, -0x044ca000, -0xcdc12010, -0x7c410000, -0xc8140009, -0x04180000, -0x041c0008, -0xcd800071, -0x09dc0001, -0x05980001, -0xcd0d0000, -0x99c0fffc, -0xcc800062, -0x8000037c, -0xcd400071, -0xc00e0100, -0xcc000041, -0xccc1304a, -0xc83c007f, -0xcc00007f, -0x80000001, -0xcc00007f, -0xcc00007f, -0x88000000, -0xcc00007f, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00010331, -0x00100004, -0x00170006, -0x00210008, -0x00270028, -0x00280023, -0x00290029, -0x002a0026, -0x002b0029, -0x002d0038, -0x002e003f, -0x002f004a, -0x0034004c, -0x00360030, -0x003900af, -0x003a00cf, -0x003b00e4, -0x003c00fc, -0x003d016b, -0x003f00ad, -0x00410336, -0x00430349, -0x0044018e, -0x004500fc, -0x004601ac, -0x004701ac, -0x004801fe, -0x0049020c, -0x004a0255, -0x004b0282, -0x0052025f, -0x00530271, -0x00540287, -0x00570299, -0x0060029d, -0x006102ac, -0x006202b6, -0x006302c0, -0x006402ca, -0x006502d4, -0x006602de, -0x006702e8, -0x006802f2, -0x006902f6, -0x006a02fa, -0x006b02fe, -0x006c0302, -0x006d0306, -0x006e030a, -0x006f030e, -0x00700312, -0x00720363, -0x00740369, -0x00790367, -0x007c031c, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -0x000f0378, -}; - -static const u32 RV710_pfp_microcode[] = { -0x7c408000, -0xa0000000, -0x7e82800b, -0x80000000, -0xdc030000, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xc818000e, -0x31980001, -0x7c424000, -0x9580023a, -0x7c428000, -0xc81c001c, -0xc037c000, -0x7c40c000, -0x7c410000, -0x7cb4800b, -0xc0360003, -0x99c00000, -0xc81c001c, -0x7cb4800c, -0x24d40002, -0x7d654000, -0xcd400043, -0xce800043, -0xcd000043, -0xcc800040, -0xce400040, -0xce800040, -0xccc00040, -0xdc3a0000, -0x9780ffde, -0xcd000040, -0x7c40c000, -0x80000018, -0x7c410000, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xc818000e, -0x8000000c, -0x31980002, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xc818000e, -0x288c0008, -0x30cc000f, -0x34100001, -0x7d0d0008, -0x8000000c, -0x7d91800b, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xcc4003f9, -0x80000249, -0xcc4003f8, -0xc037ffff, -0x7c414000, -0xcf41a29e, -0xc82003f8, -0xc81c03f9, -0x66200020, -0xc81803fb, -0x7de1c02c, -0x7d58c008, -0x7cdcc020, -0x69100020, -0xc0360003, -0xcc000054, -0x7cb4800c, -0x80000069, -0xcc800040, -0x7c418000, -0xcd81a29e, -0xcc800040, -0x80000067, -0xcd800040, -0xc019ffff, -0xcc800040, -0xcd81a29e, -0x7c40c000, -0x7c410000, -0x7c414000, -0xccc1a1fa, -0xcd01a1f9, -0xcd41a29d, -0xccc00040, -0xcd000040, -0xcd400040, -0xcc400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xcc000054, -0xcc800040, -0x7c40c000, -0x7c410000, -0x7c414000, -0xccc1a1fa, -0xcd01a1f9, -0xcd41a29d, -0xccc00040, -0xcd000040, -0xcd400040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0x7c40c000, -0x30d00001, -0xccc1a29f, -0x95000003, -0x04140001, -0x04140002, -0xcd4003fb, -0xcc800040, -0x80000000, -0xccc00040, -0x7c40c000, -0xcc800040, -0xccc1a2a2, -0x80000000, -0xccc00040, -0x7c40c000, -0x28d4001f, -0xcc800040, -0x95400003, -0x7c410000, -0xccc00057, -0x2918001f, -0xccc00040, -0x95800003, -0xcd000040, -0xcd000058, -0x80000249, -0xcc00007f, -0xc8200017, -0xc8300022, -0x9a000006, -0x0e280001, -0xc824001e, -0x0a640001, -0xd4001240, -0xce400040, -0xc036c000, -0x96800007, -0x37747900, -0x041c0001, -0xcf400040, -0xcdc00040, -0xcf0003fa, -0x7c030000, -0xca0c0010, -0x7c410000, -0x94c00004, -0x7c414000, -0xd42002c4, -0xcde00044, -0x9b00000b, -0x7c418000, -0xcc00004b, -0xcda00049, -0xcd200041, -0xcd600041, -0xcda00041, -0x06200001, -0xce000056, -0x80000249, -0xcc00007f, -0xc8280020, -0xc82c0021, -0xcc000063, -0x7eea4001, -0x65740020, -0x7f53402c, -0x269c0002, -0x7df5c020, -0x69f80020, -0xce80004b, -0xce600049, -0xcde00041, -0xcfa00041, -0xce600041, -0x271c0002, -0x7df5c020, -0x69f80020, -0x7db24001, -0xcf00004b, -0xce600049, -0xcde00041, -0xcfa00041, -0x800000bc, -0xce600041, -0xc8200017, -0xc8300022, -0x9a000006, -0x0e280001, -0xc824001e, -0x0a640001, -0xd4001240, -0xce400040, -0xca0c0010, -0x7c410000, -0x94c0000b, -0xc036c000, -0x96800007, -0x37747900, -0x041c0001, -0xcf400040, -0xcdc00040, -0xcf0003fa, -0x7c030000, -0x800000b5, -0x7c414000, -0xcc000048, -0x800000ee, -0x00000000, -0xc8200017, -0xc81c0023, -0x0e240002, -0x99c00015, -0x7c418000, -0x0a200001, -0xce000056, -0xd4000440, -0xcc000040, -0xc036c000, -0xca140013, -0x96400007, -0x37747900, -0xcf400040, -0xcc000040, -0xc83003fa, -0x80000103, -0xcf000022, -0xcc000022, -0x95400146, -0xcc00007f, -0xcca00046, -0x80000000, -0xcc200046, -0x80000249, -0xcc000064, -0xc8200017, -0xc810001f, -0x96000005, -0x09100001, -0xd4000440, -0xcd000040, -0xcd000022, -0xcc800040, -0xd0400040, -0xc80c0025, -0x94c0feec, -0xc8100008, -0xcd000040, -0xd4000fc0, -0x80000000, -0xd4000fa2, -0x7c40c000, -0x7c410000, -0xccc003fd, -0xcd0003fc, -0xccc00042, -0xcd000042, -0x2914001f, -0x29180010, -0x31980007, -0x3b5c0001, -0x7d76000b, -0x99800005, -0x7d5e400b, -0xcc000042, -0x80000249, -0xcc00004d, -0x29980001, -0x292c0008, -0x9980003d, -0x32ec0001, -0x96000004, -0x2930000c, -0x80000249, -0xcc000042, -0x04140010, -0xcd400042, -0x33300001, -0x34280001, -0x8400015d, -0xc8140003, -0x9b40001b, -0x0438000c, -0x8400015d, -0xc8140003, -0x9b400017, -0x04380008, -0x8400015d, -0xc8140003, -0x9b400013, -0x04380004, -0x8400015d, -0xc8140003, -0x9b400015, -0xc80c03fd, -0x9a800009, -0xc81003fc, -0x9b000101, -0xcc00004d, -0x04140010, -0xccc00042, -0xcd000042, -0x80000135, -0xcd400042, -0x96c000fa, -0xcc00004d, -0x80000249, -0xcc00004e, -0x9ac00003, -0xcc00004d, -0xcc00004e, -0xdf830000, -0x80000000, -0xd80301ff, -0x9ac000f0, -0xcc00004d, -0x80000249, -0xcc00004e, -0xc8180003, -0xc81c0003, -0xc8200003, -0x7d5d4003, -0x7da1c003, -0x7d5d400c, -0x2a10001f, -0x299c001f, -0x7d1d000b, -0x7d17400b, -0x88000000, -0x7e92800b, -0x96400004, -0xcc00004e, -0x80000249, -0xcc000042, -0x04380008, -0xcf800042, -0xc8080003, -0xc80c0003, -0xc8100003, -0xc8140003, -0xc8180003, -0xc81c0003, -0xc8240003, -0xc8280003, -0x29fc001f, -0x2ab0001f, -0x7ff3c00b, -0x28f0001f, -0x7ff3c00b, -0x2970001f, -0x7ff3c00b, -0x7d888001, -0x7dccc001, -0x7e510001, -0x7e954001, -0x7c908002, -0x7cd4c002, -0x7cbc800b, -0x9ac00003, -0x7c8f400b, -0x38b40001, -0x9b4000c1, -0xcc00004d, -0x9bc000bf, -0xcc00004e, -0xc80c03fd, -0xc81003fc, -0xccc00042, -0x8000016e, -0xcd000042, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xcc400040, -0xcc400040, -0xcc400040, -0x7c40c000, -0xccc00040, -0xccc0000d, -0x80000000, -0xd0400040, -0x7c40c000, -0x7c410000, -0x65140020, -0x7d4d402c, -0x24580002, -0x7d598020, -0x7c41c000, -0xcd800042, -0x69980020, -0xcd800042, -0xcdc00042, -0xc023c000, -0x05e40002, -0x7ca0800b, -0x26640010, -0x7ca4800c, -0xcc800040, -0xcdc00040, -0xccc00040, -0x95c0000e, -0xcd000040, -0x09dc0001, -0xc8280003, -0x96800008, -0xce800040, -0xc834001d, -0x97400000, -0xc834001d, -0x26a80008, -0x8400024c, -0xcc2b0000, -0x99c0fff7, -0x09dc0001, -0xdc3a0000, -0x97800004, -0x7c418000, -0x800001a2, -0x25980002, -0xa0000000, -0x7d808000, -0xc818001d, -0x7c40c000, -0x64d00008, -0x95800000, -0xc818001d, -0xcc130000, -0xcc800040, -0xccc00040, -0x80000000, -0xcc400040, -0xc810001f, -0x7c40c000, -0xcc800040, -0x7cd1400c, -0xcd400040, -0x05180001, -0x80000000, -0xcd800022, -0x7c40c000, -0x64500020, -0x8400024c, -0xcc000061, -0x7cd0c02c, -0xc8200017, -0xc8d60000, -0x99400008, -0x7c438000, -0xdf830000, -0xcfa0004f, -0x8400024c, -0xcc000062, -0x80000000, -0xd040007f, -0x80000249, -0xcc000062, -0x8400024c, -0xcc000061, -0xc8200017, -0x7c40c000, -0xc036ff00, -0xc810000d, -0xc0303fff, -0x7cf5400b, -0x7d51800b, -0x7d81800f, -0x99800008, -0x7cf3800b, -0xdf830000, -0xcfa0004f, -0x8400024c, -0xcc000062, -0x80000000, -0xd040007f, -0x80000249, -0xcc000062, -0x8400024c, -0x7c40c000, -0x28dc0008, -0x95c00019, -0x30dc0010, -0x7c410000, -0x99c00004, -0x64540020, -0x80000208, -0xc91d0000, -0x7d15002c, -0xc91e0000, -0x7c420000, -0x7c424000, -0x7c418000, -0x7de5c00b, -0x7de28007, -0x9a80000e, -0x41ac0005, -0x9ac00000, -0x0aec0001, -0x30dc0010, -0x99c00004, -0x00000000, -0x8000020b, -0xc91d0000, -0x8000020b, -0xc91e0000, -0xcc800040, -0xccc00040, -0xd0400040, -0xc80c0025, -0x94c0fde4, -0xc8100008, -0xcd000040, -0xd4000fc0, -0x80000000, -0xd4000fa2, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0xd40003c0, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xd0400040, -0x7c408000, -0xa0000000, -0x7e82800b, -0x7c40c000, -0x30d00006, -0x0d100006, -0x99000007, -0xc8140015, -0x99400005, -0xcc000052, -0xd4000340, -0xd4000fc0, -0xd4000fa2, -0xcc800040, -0xccc00040, -0x80000000, -0xd0400040, -0x7c40c000, -0xcc4d0000, -0xdc3a0000, -0x9780fdbd, -0x04cc0001, -0x80000242, -0xcc4d0000, -0x80000000, -0xd040007f, -0xcc00007f, -0x80000000, -0xcc00007f, -0xcc00007f, -0x88000000, -0xcc00007f, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00030222, -0x0004022a, -0x0005009f, -0x00020003, -0x0006003c, -0x00070027, -0x00080191, -0x00090044, -0x000a002d, -0x00100247, -0x001700f0, -0x002201d7, -0x002301e8, -0x0026004c, -0x0027005f, -0x0020011a, -0x00280092, -0x0029004f, -0x002a0083, -0x002b0064, -0x002f008d, -0x003200d8, -0x00340232, -0x00360074, -0x0039010a, -0x003c01fc, -0x003f009f, -0x00410005, -0x00440194, -0x0048019d, -0x004901c5, -0x004a01cf, -0x00550225, -0x0056022d, -0x0060000a, -0x0061002a, -0x00620030, -0x00630030, -0x00640030, -0x00650030, -0x00660030, -0x00670030, -0x00680037, -0x0069003f, -0x006a0047, -0x006b0047, -0x006c0047, -0x006d0047, -0x006e0047, -0x006f0047, -0x00700047, -0x00730247, -0x007b0240, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -0x00000005, -}; - -static const u32 RV710_cp_microcode[] = { -0xcc0003ea, -0x04080003, -0xcc800043, -0x7c408000, -0xa0000000, -0xcc800062, -0x80000003, -0xd040007f, -0x80000003, -0xcc400041, -0x7c40c000, -0xc0160004, -0x30d03fff, -0x7d15000c, -0xcc110000, -0x28d8001e, -0x31980001, -0x28dc001f, -0xc8200004, -0x95c00006, -0x7c424000, -0xcc000062, -0x7e56800c, -0xcc290000, -0xc8240004, -0x7e26000b, -0x95800006, -0x7c42c000, -0xcc000062, -0x7ed7000c, -0xcc310000, -0xc82c0004, -0x7e2e000c, -0xcc000062, -0x31103fff, -0x80000003, -0xce110000, -0x7c40c000, -0x80000003, -0xcc400040, -0x80000003, -0xcc412257, -0x7c418000, -0xcc400045, -0xcc400048, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xcc400045, -0xcc400048, -0x7c40c000, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xcc000045, -0xcc000048, -0xcc41225c, -0xcc41a1fc, -0x7c408000, -0xa0000000, -0xcc800062, -0x040ca1fd, -0xc0120001, -0xcc000045, -0xcc000048, -0x7cd0c00c, -0xcc41225c, -0xcc41a1fc, -0xd04d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x80000003, -0xcc41225d, -0x7c408000, -0x7c40c000, -0xc02a0002, -0x7c410000, -0x7d29000c, -0x30940001, -0x30980006, -0x309c0300, -0x29dc0008, -0x7c420000, -0x7c424000, -0x9540000f, -0xc02e0004, -0x05f02258, -0x7f2f000c, -0xcc310000, -0xc8280004, -0xccc12169, -0xcd01216a, -0xce81216b, -0x0db40002, -0xcc01216c, -0x9740000e, -0x0db40000, -0x8000007d, -0xc834000a, -0x0db40002, -0x97400009, -0x0db40000, -0xc02e0004, -0x05f02258, -0x7f2f000c, -0xcc310000, -0xc8280004, -0x8000007d, -0xc834000a, -0x97400004, -0x7e028000, -0x8000007d, -0xc834000a, -0x0db40004, -0x9740ff8c, -0x00000000, -0xce01216d, -0xce41216e, -0xc8280003, -0xc834000a, -0x9b400004, -0x043c0005, -0x8400026d, -0xcc000062, -0x0df40000, -0x9740000b, -0xc82c03e6, -0xce81a2b7, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c4, -0x80000003, -0xcfc1a2d1, -0x0df40001, -0x9740000b, -0xc82c03e7, -0xce81a2bb, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c5, -0x80000003, -0xcfc1a2d2, -0x0df40002, -0x9740000b, -0xc82c03e8, -0xce81a2bf, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c6, -0x80000003, -0xcfc1a2d3, -0xc82c03e9, -0xce81a2c3, -0xc0300006, -0x7ef34028, -0xc0300020, -0x7f6b8020, -0x7fb3c029, -0xcf81a2c7, -0x80000003, -0xcfc1a2d4, -0x80000003, -0xcc400042, -0x7c40c000, -0x7c410000, -0x2914001d, -0x31540001, -0x9940000c, -0x31181000, -0xc81c0011, -0x95c00000, -0xc81c0011, -0xccc12100, -0xcd012101, -0xccc12102, -0xcd012103, -0x04180004, -0x8000037e, -0xcd81a2a4, -0xc02a0004, -0x95800008, -0x36a821a3, -0xcc290000, -0xc8280004, -0xc81c0011, -0x0de40040, -0x9640ffff, -0xc81c0011, -0xccc12170, -0xcd012171, -0xc8200012, -0x96000000, -0xc8200012, -0x8000037e, -0xcc000064, -0x7c40c000, -0x7c410000, -0xcc000045, -0xcc000048, -0x40d40003, -0xcd41225c, -0xcd01a1fc, -0xc01a0001, -0x041ca1fd, -0x7dd9c00c, -0x7c420000, -0x08cc0001, -0x06240001, -0x06280002, -0xce1d0000, -0xce5d0000, -0x98c0fffa, -0xce9d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0x30d00001, -0x28cc0001, -0x7c414000, -0x95000006, -0x7c418000, -0xcd41216d, -0xcd81216e, -0x800000f4, -0xc81c0003, -0xc0220004, -0x7e16000c, -0xcc210000, -0xc81c0004, -0x7c424000, -0x98c00004, -0x7c428000, -0x80000003, -0xcde50000, -0xce412169, -0xce81216a, -0xcdc1216b, -0x80000003, -0xcc01216c, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0x7c41c000, -0x28a40008, -0x326400ff, -0x0e68003c, -0x9680000a, -0x7c020000, -0x7c420000, -0x1e300003, -0xcc00006a, -0x9b000003, -0x42200005, -0x04200040, -0x80000111, -0x7c024000, -0x7e024000, -0x9a400000, -0x0a640001, -0x30ec0010, -0x9ac0000a, -0xcc000062, -0xc02a0004, -0xc82c0021, -0x7e92800c, -0xcc000041, -0xcc290000, -0xcec00021, -0x80000121, -0xc8300004, -0xcd01216d, -0xcd41216e, -0xc8300003, -0x7f1f000b, -0x30f40007, -0x27780001, -0x9740002a, -0x07b80126, -0x9f800000, -0x00000000, -0x80000136, -0x7f1b8004, -0x8000013a, -0x7f1b8005, -0x8000013e, -0x7f1b8002, -0x80000142, -0x7f1b8003, -0x80000146, -0x7f1b8007, -0x8000014a, -0x7f1b8006, -0x8000014f, -0x28a40008, -0x9b800019, -0x28a40008, -0x8000015f, -0x326400ff, -0x9b800015, -0x28a40008, -0x8000015f, -0x326400ff, -0x9b800011, -0x28a40008, -0x8000015f, -0x326400ff, -0x9b80000d, -0x28a40008, -0x8000015f, -0x326400ff, -0x9b800009, -0x28a40008, -0x8000015f, -0x326400ff, -0x9b800005, -0x28a40008, -0x8000015f, -0x326400ff, -0x28a40008, -0x326400ff, -0x0e68003c, -0x9a80feb2, -0x28ec0008, -0x7c434000, -0x7c438000, -0x7c43c000, -0x96c00007, -0xcc000062, -0xcf412169, -0xcf81216a, -0xcfc1216b, -0x80000003, -0xcc01216c, -0x80000003, -0xcff50000, -0xcc00006b, -0x84000381, -0x0e68003c, -0x9a800004, -0xc8280015, -0x80000003, -0xd040007f, -0x9680ffab, -0x7e024000, -0x8400023b, -0xc00e0002, -0xcc000041, -0x80000239, -0xccc1304a, -0x7c40c000, -0x7c410000, -0xc01e0001, -0x29240012, -0xc0220002, -0x96400005, -0xc0260004, -0xc027fffb, -0x7d25000b, -0xc0260000, -0x7dd2800b, -0x7e12c00b, -0x7d25000c, -0x7c414000, -0x7c418000, -0xccc12169, -0x9a80000a, -0xcd01216a, -0xcd41216b, -0x96c0fe83, -0xcd81216c, -0xc8300018, -0x97000000, -0xc8300018, -0x80000003, -0xcc000018, -0x84000381, -0xcc00007f, -0xc8140013, -0xc8180014, -0xcd41216b, -0x96c0fe77, -0xcd81216c, -0x80000183, -0xc8300018, -0xc80c0008, -0x98c00000, -0xc80c0008, -0x7c410000, -0x95000002, -0x00000000, -0x7c414000, -0xc8200009, -0xcc400043, -0xce01a1f4, -0xcc400044, -0xc00e8000, -0x7c424000, -0x7c428000, -0x2aac001f, -0x96c0fe64, -0xc035f000, -0xce4003e2, -0x32780003, -0x267c0008, -0x7ff7c00b, -0x7ffbc00c, -0x2a780018, -0xcfc003e3, -0xcf8003e4, -0x26b00002, -0x7f3f0000, -0xcf0003e5, -0x8000031f, -0x7c80c000, -0x7c40c000, -0x28d00008, -0x3110000f, -0x9500000f, -0x25280001, -0x06a801b4, -0x9e800000, -0x00000000, -0x800001d5, -0xc0120800, -0x800001e3, -0xc814000f, -0x800001ea, -0xc8140010, -0x800001f1, -0xccc1a2a4, -0x800001fa, -0xc8140011, -0x30d0003f, -0x0d280015, -0x9a800012, -0x0d28001e, -0x9a80001e, -0x0d280020, -0x9a800023, -0x0d24000f, -0x0d280010, -0x7e6a800c, -0x9a800026, -0x0d200004, -0x0d240014, -0x0d280028, -0x7e62400c, -0x7ea6800c, -0x9a80002a, -0xc8140011, -0x80000003, -0xccc1a2a4, -0xc0120800, -0x7c414000, -0x7d0cc00c, -0xc0120008, -0x29580003, -0x295c000c, -0x7c420000, -0x7dd1c00b, -0x26200014, -0x7e1e400c, -0x7e4e800c, -0xce81a2a4, -0x80000003, -0xcd81a1fe, -0xc814000f, -0x0410210e, -0x95400000, -0xc814000f, -0xd0510000, -0x80000003, -0xccc1a2a4, -0xc8140010, -0x04102108, -0x95400000, -0xc8140010, -0xd0510000, -0x80000003, -0xccc1a2a4, -0xccc1a2a4, -0x04100001, -0xcd000019, -0x84000381, -0xcc00007f, -0xc8100019, -0x99000000, -0xc8100019, -0x80000004, -0x7c408000, -0x04102100, -0x95400000, -0xc8140011, -0xd0510000, -0x8000037e, -0xccc1a2a4, -0x7c40c000, -0xcc40000d, -0x94c0fe01, -0xcc40000e, -0x7c410000, -0x95000005, -0x08cc0001, -0xc8140005, -0x99400014, -0x00000000, -0x98c0fffb, -0x7c410000, -0x80000004, -0x7d008000, -0xc8140005, -0x7c40c000, -0x9940000c, -0xc818000c, -0x7c410000, -0x9580fdf0, -0xc820000e, -0xc81c000d, -0x66200020, -0x7e1e002c, -0x25240002, -0x7e624020, -0x80000003, -0xcce60000, -0x7c410000, -0xcc00006c, -0xcc00006d, -0xc818001f, -0xc81c001e, -0x65980020, -0x7dd9c02c, -0x7cd4c00c, -0xccde0000, -0x45dc0004, -0xc8280017, -0x9680000f, -0xc00e0001, -0x28680008, -0x2aac0016, -0x32a800ff, -0x0eb00049, -0x7f2f000b, -0x97000006, -0x00000000, -0xc8140005, -0x7c40c000, -0x80000223, -0x7c410000, -0x80000226, -0xd040007f, -0x8400023b, -0xcc000041, -0xccc1304a, -0x94000000, -0xc83c001a, -0x043c0005, -0xcfc1a2a4, -0xc0361f90, -0xc0387fff, -0x7c03c010, -0x7f7b400c, -0xcf41217c, -0xcfc1217d, -0xcc01217e, -0xc03a0004, -0x0434217f, -0x7f7b400c, -0xcc350000, -0xc83c0004, -0x2bfc001f, -0x04380020, -0x97c00005, -0xcc000062, -0x9b800000, -0x0bb80001, -0x80000247, -0xcc000071, -0xcc01a1f4, -0x04380016, -0xc0360002, -0xcf81a2a4, -0x88000000, -0xcf412010, -0x7c40c000, -0x28d0001c, -0x95000005, -0x04d40001, -0xcd400065, -0x80000003, -0xcd400068, -0x09540002, -0x80000003, -0xcd400066, -0x8400026c, -0xc81803ea, -0x7c40c000, -0x9980fd9f, -0xc8140016, -0x08d00001, -0x9940002b, -0xcd000068, -0x7c408000, -0xa0000000, -0xcc800062, -0x043c0005, -0xcfc1a2a4, -0xcc01a1f4, -0x84000381, -0xcc000046, -0x88000000, -0xcc00007f, -0x8400027e, -0xc81803ea, -0x7c40c000, -0x9980fd8d, -0xc8140016, -0x08d00001, -0x99400019, -0xcd000068, -0x7c408000, -0xa0000000, -0xcc800062, -0x043c0022, -0xcfc1a2a4, -0x84000381, -0xcc000047, -0x88000000, -0xcc00007f, -0xc8100016, -0x9900000d, -0xcc400067, -0x80000004, -0x7c408000, -0xc81803ea, -0x9980fd79, -0x7c40c000, -0x94c00003, -0xc8100016, -0x99000004, -0xccc00068, -0x80000004, -0x7c408000, -0x8400023b, -0xc0148000, -0xcc000041, -0xcd41304a, -0xc0148000, -0x99000000, -0xc8100016, -0x80000004, -0x7c408000, -0xc0120001, -0x7c51400c, -0x80000003, -0xd0550000, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0x291c001f, -0xccc0004a, -0xcd00004b, -0x95c00003, -0xc01c8000, -0xcdc12010, -0xdd830000, -0x055c2000, -0xcc000062, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc0004c, -0xcd00004d, -0xdd830000, -0x055ca000, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc0004e, -0xcd00004f, -0xdd830000, -0x055cc000, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00050, -0xcd000051, -0xdd830000, -0x055cf8e0, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00052, -0xcd000053, -0xdd830000, -0x055cf880, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00054, -0xcd000055, -0xdd830000, -0x055ce000, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00056, -0xcd000057, -0xdd830000, -0x055cf000, -0x80000003, -0xd81f4100, -0x7c40c000, -0x7c410000, -0x7c414000, -0x7c418000, -0xccc00058, -0xcd000059, -0xdd830000, -0x055cf3fc, -0x80000003, -0xd81f4100, -0xd0432000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043a000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043c000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f8e0, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f880, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043e000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f000, -0x7c408000, -0xa0000000, -0xcc800062, -0xd043f3fc, -0x7c408000, -0xa0000000, -0xcc800062, -0xc81403e0, -0xcc430000, -0xcc430000, -0xcc430000, -0x7d45c000, -0xcdc30000, -0xd0430000, -0x7c408000, -0xa0000000, -0xcc800062, -0x7c40c000, -0xc81003e2, -0xc81403e5, -0xc81803e3, -0xc81c03e4, -0xcd812169, -0xcdc1216a, -0xccc1216b, -0xcc01216c, -0x04200004, -0x7da18000, -0x7d964002, -0x9640fcd9, -0xcd8003e3, -0x31280003, -0xc02df000, -0x25180008, -0x7dad800b, -0x7da9800c, -0x80000003, -0xcd8003e3, -0x308cffff, -0xd04d0000, -0x7c408000, -0xa0000000, -0xcc800062, -0xc8140020, -0x15580002, -0x9580ffff, -0xc8140020, -0xcc00006e, -0xcc412180, -0x7c40c000, -0xccc1218d, -0xcc412181, -0x28d0001f, -0x34588000, -0xcd81218c, -0x9500fcbf, -0xcc412182, -0xc8140020, -0x9940ffff, -0xc8140020, -0x80000004, -0x7c408000, -0x7c40c000, -0x28d00018, -0x31100001, -0xc0160080, -0x95000003, -0xc02a0004, -0x7cd4c00c, -0xccc1217c, -0xcc41217d, -0xcc41217e, -0x7c418000, -0x1db00003, -0x36a0217f, -0x9b000003, -0x419c0005, -0x041c0040, -0x99c00000, -0x09dc0001, -0xcc210000, -0xc8240004, -0x2a6c001f, -0x419c0005, -0x9ac0fffa, -0xcc800062, -0x80000004, -0x7c408000, -0x7c40c000, -0x04d403e6, -0x80000003, -0xcc540000, -0x8000037e, -0xcc4003ea, -0xc01c8000, -0x044ca000, -0xcdc12010, -0x7c410000, -0xc8140009, -0x04180000, -0x041c0008, -0xcd800071, -0x09dc0001, -0x05980001, -0xcd0d0000, -0x99c0fffc, -0xcc800062, -0x8000037e, -0xcd400071, -0xc00e0100, -0xcc000041, -0xccc1304a, -0xc83c007f, -0xcc00007f, -0x80000003, -0xcc00007f, -0xcc00007f, -0x88000000, -0xcc00007f, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00010333, -0x00100006, -0x00170008, -0x0021000a, -0x0027002a, -0x00280025, -0x0029002b, -0x002a0028, -0x002b002b, -0x002d003a, -0x002e0041, -0x002f004c, -0x0034004e, -0x00360032, -0x003900b1, -0x003a00d1, -0x003b00e6, -0x003c00fe, -0x003d016d, -0x003f00af, -0x00410338, -0x0043034b, -0x00440190, -0x004500fe, -0x004601ae, -0x004701ae, -0x00480200, -0x0049020e, -0x004a0257, -0x004b0284, -0x00520261, -0x00530273, -0x00540289, -0x0057029b, -0x0060029f, -0x006102ae, -0x006202b8, -0x006302c2, -0x006402cc, -0x006502d6, -0x006602e0, -0x006702ea, -0x006802f4, -0x006902f8, -0x006a02fc, -0x006b0300, -0x006c0304, -0x006d0308, -0x006e030c, -0x006f0310, -0x00700314, -0x00720365, -0x0074036b, -0x00790369, -0x007c031e, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -0x000f037a, -}; - -#endif diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 79ad982..1041a7c 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -695,6 +695,7 @@ struct radeon_device { bool suspend; bool need_dma32; struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; + const struct firmware *fw; /* firmware */ }; int radeon_device_init(struct radeon_device *rdev, diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c index d835682..6b6cc84 100644 --- a/drivers/gpu/drm/radeon/radeon_cp.c +++ b/drivers/gpu/drm/radeon/radeon_cp.c @@ -36,10 +36,25 @@ #include "radeon_drv.h" #include "r300_reg.h" -#include "radeon_microcode.h" - #define RADEON_FIFO_DEBUG 0 +/* Firmware Names */ +#define FIRMWARE_R100 "radeon/R100_cp.bin" +#define FIRMWARE_R200 "radeon/R200_cp.bin" +#define FIRMWARE_R300 "radeon/R300_cp.bin" +#define FIRMWARE_R420 "radeon/R420_cp.bin" +#define FIRMWARE_RS690 "radeon/RS690_cp.bin" +#define FIRMWARE_RS600 "radeon/RS600_cp.bin" +#define FIRMWARE_R520 "radeon/R520_cp.bin" + +MODULE_FIRMWARE(FIRMWARE_R100); +MODULE_FIRMWARE(FIRMWARE_R200); +MODULE_FIRMWARE(FIRMWARE_R300); +MODULE_FIRMWARE(FIRMWARE_R420); +MODULE_FIRMWARE(FIRMWARE_RS690); +MODULE_FIRMWARE(FIRMWARE_RS600); +MODULE_FIRMWARE(FIRMWARE_R520); + static int radeon_do_cleanup_cp(struct drm_device * dev); static void radeon_do_cp_start(drm_radeon_private_t * dev_priv); @@ -451,37 +466,34 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv) */ /* Load the microcode for the CP */ -static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) +static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv) { - int i; + struct platform_device *pdev; + const char *fw_name = NULL; + int err; + DRM_DEBUG("\n"); - radeon_do_wait_for_idle(dev_priv); + pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); + err = IS_ERR(pdev); + if (err) { + printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); + return -EINVAL; + } - RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { DRM_INFO("Loading R100 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R100_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R100_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R100; } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { DRM_INFO("Loading R200 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R200_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R200_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R200; } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || @@ -489,39 +501,19 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { DRM_INFO("Loading R300 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R300_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R300_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R300; } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { DRM_INFO("Loading R400 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R420_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R420_cp_microcode[i][0]); - } + fw_name = FIRMWARE_R420; } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { DRM_INFO("Loading RS690/RS740 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - RS690_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - RS690_cp_microcode[i][0]); - } + fw_name = FIRMWARE_RS690; } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { DRM_INFO("Loading RS600 Microcode\n"); - for (i = 0; i < 256; i++) { - RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - RS600_cp_microcode[i][1]); - RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - RS600_cp_microcode[i][0]); - } + fw_name = FIRMWARE_RS600; } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || @@ -529,11 +521,41 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { DRM_INFO("Loading R500 Microcode\n"); - for (i = 0; i < 256; i++) { + fw_name = FIRMWARE_R520; + } + + err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); + platform_device_unregister(pdev); + if (err) { + printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", + fw_name); + } else if (dev_priv->me_fw->size % 8) { + printk(KERN_ERR + "radeon_cp: Bogus length %zu in firmware \"%s\"\n", + dev_priv->me_fw->size, fw_name); + err = -EINVAL; + release_firmware(dev_priv->me_fw); + dev_priv->me_fw = NULL; + } + return err; +} + +static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv) +{ + const __be32 *fw_data; + int i, size; + + radeon_do_wait_for_idle(dev_priv); + + if (dev_priv->me_fw) { + size = dev_priv->me_fw->size / 4; + fw_data = (const __be32 *)&dev_priv->me_fw->data[0]; + RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); + for (i = 0; i < size; i += 2) { RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, - R520_cp_microcode[i][1]); + be32_to_cpup(&fw_data[i])); RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, - R520_cp_microcode[i][0]); + be32_to_cpup(&fw_data[i + 1])); } } } @@ -1486,6 +1508,14 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, radeon_set_pcigart(dev_priv, 1); } + if (!dev_priv->me_fw) { + int err = radeon_cp_init_microcode(dev_priv); + if (err) { + DRM_ERROR("Failed to load firmware!\n"); + radeon_do_cleanup_cp(dev); + return err; + } + } radeon_cp_load_microcode(dev_priv); radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); @@ -1755,6 +1785,14 @@ void radeon_do_release(struct drm_device * dev) r600_do_cleanup_cp(dev); else radeon_do_cleanup_cp(dev); + if (dev_priv->me_fw) { + release_firmware(dev_priv->me_fw); + dev_priv->me_fw = NULL; + } + if (dev_priv->pfp_fw) { + release_firmware(dev_priv->pfp_fw); + dev_priv->pfp_fw = NULL; + } } } diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index 3933f82..45a6ad9 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -31,6 +31,9 @@ #ifndef __RADEON_DRV_H__ #define __RADEON_DRV_H__ +#include +#include + /* General customization: */ @@ -351,6 +354,8 @@ typedef struct drm_radeon_private { int r700_sc_hiz_tile_fifo_size; int r700_sc_earlyz_tile_fifo_fize; + /* firmware */ + const struct firmware *me_fw, *pfp_fw; } drm_radeon_private_t; typedef struct drm_radeon_buf_priv { diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c index 9805e4b..1841145 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -28,7 +28,6 @@ #include "drmP.h" #include "radeon_drm.h" #include "radeon_reg.h" -#include "radeon_microcode.h" #include "radeon.h" #include "atom.h" diff --git a/drivers/gpu/drm/radeon/radeon_microcode.h b/drivers/gpu/drm/radeon/radeon_microcode.h deleted file mode 100644 index a348c9e..0000000 --- a/drivers/gpu/drm/radeon/radeon_microcode.h +++ /dev/null @@ -1,1844 +0,0 @@ -/* - * Copyright 2007 Advanced Micro Devices, Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef RADEON_MICROCODE_H -#define RADEON_MICROCODE_H - -/* production radeon ucode r1xx-r6xx */ -static const u32 R100_cp_microcode[][2] = { - { 0x21007000, 0000000000 }, - { 0x20007000, 0000000000 }, - { 0x000000b4, 0x00000004 }, - { 0x000000b8, 0x00000004 }, - { 0x6f5b4d4c, 0000000000 }, - { 0x4c4c427f, 0000000000 }, - { 0x5b568a92, 0000000000 }, - { 0x4ca09c6d, 0000000000 }, - { 0xad4c4c4c, 0000000000 }, - { 0x4ce1af3d, 0000000000 }, - { 0xd8afafaf, 0000000000 }, - { 0xd64c4cdc, 0000000000 }, - { 0x4cd10d10, 0000000000 }, - { 0x000f0000, 0x00000016 }, - { 0x362f242d, 0000000000 }, - { 0x00000012, 0x00000004 }, - { 0x000f0000, 0x00000016 }, - { 0x362f282d, 0000000000 }, - { 0x000380e7, 0x00000002 }, - { 0x04002c97, 0x00000002 }, - { 0x000f0001, 0x00000016 }, - { 0x333a3730, 0000000000 }, - { 0x000077ef, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000021, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000021, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000021, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00000017, 0x00000004 }, - { 0x0003802b, 0x00000002 }, - { 0x040067e0, 0x00000002 }, - { 0x00000017, 0x00000004 }, - { 0x000077e0, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x000037e1, 0x00000002 }, - { 0x040067e1, 0x00000006 }, - { 0x000077e0, 0x00000002 }, - { 0x000077e1, 0x00000002 }, - { 0x000077e1, 0x00000006 }, - { 0xffffffff, 0000000000 }, - { 0x10000000, 0000000000 }, - { 0x0003802b, 0x00000002 }, - { 0x040067e0, 0x00000006 }, - { 0x00007675, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0000002f, 0x00000018 }, - { 0x0000002f, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x00000030, 0x00000018 }, - { 0x00000030, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x01605000, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00098000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x64c0603e, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00080000, 0x00000016 }, - { 0000000000, 0000000000 }, - { 0x0400251d, 0x00000002 }, - { 0x00007580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x04002580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x00000049, 0x00000004 }, - { 0x00005000, 0000000000 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x00019000, 0x00000002 }, - { 0x00011055, 0x00000014 }, - { 0x00000055, 0x00000012 }, - { 0x0400250f, 0x00000002 }, - { 0x0000504f, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00007565, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000058, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x01e655b4, 0x00000002 }, - { 0x4401b0e4, 0x00000002 }, - { 0x01c110e4, 0x00000002 }, - { 0x26667066, 0x00000018 }, - { 0x040c2565, 0x00000002 }, - { 0x00000066, 0x00000018 }, - { 0x04002564, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x0000005d, 0x00000004 }, - { 0x00401069, 0x00000008 }, - { 0x00101000, 0x00000002 }, - { 0x000d80ff, 0x00000002 }, - { 0x0080006c, 0x00000008 }, - { 0x000f9000, 0x00000002 }, - { 0x000e00ff, 0x00000002 }, - { 0000000000, 0x00000006 }, - { 0x0000008f, 0x00000018 }, - { 0x0000005b, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00007576, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00009000, 0x00000002 }, - { 0x00041000, 0x00000002 }, - { 0x0c00350e, 0x00000002 }, - { 0x00049000, 0x00000002 }, - { 0x00051000, 0x00000002 }, - { 0x01e785f8, 0x00000002 }, - { 0x00200000, 0x00000002 }, - { 0x0060007e, 0x0000000c }, - { 0x00007563, 0x00000002 }, - { 0x006075f0, 0x00000021 }, - { 0x20007073, 0x00000004 }, - { 0x00005073, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00007576, 0x00000002 }, - { 0x00007577, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x0000750f, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00600083, 0x0000000c }, - { 0x006075f0, 0x00000021 }, - { 0x000075f8, 0x00000002 }, - { 0x00000083, 0x00000004 }, - { 0x000a750e, 0x00000002 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x0020750f, 0x00000002 }, - { 0x00600086, 0x00000004 }, - { 0x00007570, 0x00000002 }, - { 0x00007571, 0x00000002 }, - { 0x00007572, 0x00000006 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00005000, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00007568, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000095, 0x0000000c }, - { 0x00058000, 0x00000002 }, - { 0x0c607562, 0x00000002 }, - { 0x00000097, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00600096, 0x00000004 }, - { 0x400070e5, 0000000000 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x000380e5, 0x00000002 }, - { 0x000000a8, 0x0000001c }, - { 0x000650aa, 0x00000018 }, - { 0x040025bb, 0x00000002 }, - { 0x000610ab, 0x00000018 }, - { 0x040075bc, 0000000000 }, - { 0x000075bb, 0x00000002 }, - { 0x000075bc, 0000000000 }, - { 0x00090000, 0x00000006 }, - { 0x00090000, 0x00000002 }, - { 0x000d8002, 0x00000006 }, - { 0x00007832, 0x00000002 }, - { 0x00005000, 0x00000002 }, - { 0x000380e7, 0x00000002 }, - { 0x04002c97, 0x00000002 }, - { 0x00007820, 0x00000002 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x01200000, 0x00000002 }, - { 0x20077000, 0x00000002 }, - { 0x01200000, 0x00000002 }, - { 0x20007000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x0120751b, 0x00000002 }, - { 0x8040750a, 0x00000002 }, - { 0x8040750b, 0x00000002 }, - { 0x00110000, 0x00000002 }, - { 0x000380e5, 0x00000002 }, - { 0x000000c6, 0x0000001c }, - { 0x000610ab, 0x00000018 }, - { 0x844075bd, 0x00000002 }, - { 0x000610aa, 0x00000018 }, - { 0x840075bb, 0x00000002 }, - { 0x000610ab, 0x00000018 }, - { 0x844075bc, 0x00000002 }, - { 0x000000c9, 0x00000004 }, - { 0x804075bd, 0x00000002 }, - { 0x800075bb, 0x00000002 }, - { 0x804075bc, 0x00000002 }, - { 0x00108000, 0x00000002 }, - { 0x01400000, 0x00000002 }, - { 0x006000cd, 0x0000000c }, - { 0x20c07000, 0x00000020 }, - { 0x000000cf, 0x00000012 }, - { 0x00800000, 0x00000006 }, - { 0x0080751d, 0x00000006 }, - { 0000000000, 0000000000 }, - { 0x0000775c, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460275d, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x01e00830, 0x00000002 }, - { 0x21007000, 0000000000 }, - { 0x6464614d, 0000000000 }, - { 0x69687420, 0000000000 }, - { 0x00000073, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x00005000, 0x00000002 }, - { 0x000380d0, 0x00000002 }, - { 0x040025e0, 0x00000002 }, - { 0x000075e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000380e0, 0x00000002 }, - { 0x04002394, 0x00000002 }, - { 0x00005000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x00000008, 0000000000 }, - { 0x00000004, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 R200_cp_microcode[][2] = { - { 0x21007000, 0000000000 }, - { 0x20007000, 0000000000 }, - { 0x000000bf, 0x00000004 }, - { 0x000000c3, 0x00000004 }, - { 0x7a685e5d, 0000000000 }, - { 0x5d5d5588, 0000000000 }, - { 0x68659197, 0000000000 }, - { 0x5da19f78, 0000000000 }, - { 0x5d5d5d5d, 0000000000 }, - { 0x5dee5d50, 0000000000 }, - { 0xf2acacac, 0000000000 }, - { 0xe75df9e9, 0000000000 }, - { 0xb1dd0e11, 0000000000 }, - { 0xe2afafaf, 0000000000 }, - { 0x000f0000, 0x00000016 }, - { 0x452f232d, 0000000000 }, - { 0x00000013, 0x00000004 }, - { 0x000f0000, 0x00000016 }, - { 0x452f272d, 0000000000 }, - { 0x000f0001, 0x00000016 }, - { 0x3e4d4a37, 0000000000 }, - { 0x000077ef, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00000016, 0x00000004 }, - { 0x0003802a, 0x00000002 }, - { 0x040067e0, 0x00000002 }, - { 0x00000016, 0x00000004 }, - { 0x000077e0, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x000037e1, 0x00000002 }, - { 0x040067e1, 0x00000006 }, - { 0x000077e0, 0x00000002 }, - { 0x000077e1, 0x00000002 }, - { 0x000077e1, 0x00000006 }, - { 0xffffffff, 0000000000 }, - { 0x10000000, 0000000000 }, - { 0x07f007f0, 0000000000 }, - { 0x0003802a, 0x00000002 }, - { 0x040067e0, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002743, 0x00000002 }, - { 0x00007675, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002743, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802b, 0x00000002 }, - { 0x04002676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x0003802c, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002743, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002741, 0x00000002 }, - { 0x04002743, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0000002f, 0x00000018 }, - { 0x0000002f, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x00000037, 0x00000018 }, - { 0x00000037, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x01605000, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00098000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x64c06051, 0x00000004 }, - { 0x00080000, 0x00000016 }, - { 0000000000, 0000000000 }, - { 0x0400251d, 0x00000002 }, - { 0x00007580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x04002580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x0000005a, 0x00000004 }, - { 0x00005000, 0000000000 }, - { 0x00061000, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x00019000, 0x00000002 }, - { 0x00011064, 0x00000014 }, - { 0x00000064, 0x00000012 }, - { 0x0400250f, 0x00000002 }, - { 0x0000505e, 0x00000004 }, - { 0x00007565, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000065, 0x00000004 }, - { 0x01e655b4, 0x00000002 }, - { 0x4401b0f0, 0x00000002 }, - { 0x01c110f0, 0x00000002 }, - { 0x26667071, 0x00000018 }, - { 0x040c2565, 0x00000002 }, - { 0x00000071, 0x00000018 }, - { 0x04002564, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000068, 0x00000004 }, - { 0x00401074, 0x00000008 }, - { 0x00101000, 0x00000002 }, - { 0x000d80ff, 0x00000002 }, - { 0x00800077, 0x00000008 }, - { 0x000f9000, 0x00000002 }, - { 0x000e00ff, 0x00000002 }, - { 0000000000, 0x00000006 }, - { 0x00000094, 0x00000018 }, - { 0x00000068, 0x00000004 }, - { 0x00007576, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00009000, 0x00000002 }, - { 0x00041000, 0x00000002 }, - { 0x0c00350e, 0x00000002 }, - { 0x00049000, 0x00000002 }, - { 0x00051000, 0x00000002 }, - { 0x01e785f8, 0x00000002 }, - { 0x00200000, 0x00000002 }, - { 0x00600087, 0x0000000c }, - { 0x00007563, 0x00000002 }, - { 0x006075f0, 0x00000021 }, - { 0x2000707c, 0x00000004 }, - { 0x0000507c, 0x00000004 }, - { 0x00007576, 0x00000002 }, - { 0x00007577, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x0000750f, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x0060008a, 0x0000000c }, - { 0x006075f0, 0x00000021 }, - { 0x000075f8, 0x00000002 }, - { 0x0000008a, 0x00000004 }, - { 0x000a750e, 0x00000002 }, - { 0x0020750f, 0x00000002 }, - { 0x0060008d, 0x00000004 }, - { 0x00007570, 0x00000002 }, - { 0x00007571, 0x00000002 }, - { 0x00007572, 0x00000006 }, - { 0x00005000, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00007568, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000098, 0x0000000c }, - { 0x00058000, 0x00000002 }, - { 0x0c607562, 0x00000002 }, - { 0x0000009a, 0x00000004 }, - { 0x00600099, 0x00000004 }, - { 0x400070f1, 0000000000 }, - { 0x000380f1, 0x00000002 }, - { 0x000000a7, 0x0000001c }, - { 0x000650a9, 0x00000018 }, - { 0x040025bb, 0x00000002 }, - { 0x000610aa, 0x00000018 }, - { 0x040075bc, 0000000000 }, - { 0x000075bb, 0x00000002 }, - { 0x000075bc, 0000000000 }, - { 0x00090000, 0x00000006 }, - { 0x00090000, 0x00000002 }, - { 0x000d8002, 0x00000006 }, - { 0x00005000, 0x00000002 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x01665000, 0x00000002 }, - { 0x000a0000, 0x00000002 }, - { 0x000671cc, 0x00000002 }, - { 0x0286f1cd, 0x00000002 }, - { 0x000000b7, 0x00000010 }, - { 0x21007000, 0000000000 }, - { 0x000000be, 0x0000001c }, - { 0x00065000, 0x00000002 }, - { 0x000a0000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x000b0000, 0x00000002 }, - { 0x38067000, 0x00000002 }, - { 0x000a00ba, 0x00000004 }, - { 0x20007000, 0000000000 }, - { 0x01200000, 0x00000002 }, - { 0x20077000, 0x00000002 }, - { 0x01200000, 0x00000002 }, - { 0x20007000, 0000000000 }, - { 0x00061000, 0x00000002 }, - { 0x0120751b, 0x00000002 }, - { 0x8040750a, 0x00000002 }, - { 0x8040750b, 0x00000002 }, - { 0x00110000, 0x00000002 }, - { 0x000380f1, 0x00000002 }, - { 0x000000d1, 0x0000001c }, - { 0x000610aa, 0x00000018 }, - { 0x844075bd, 0x00000002 }, - { 0x000610a9, 0x00000018 }, - { 0x840075bb, 0x00000002 }, - { 0x000610aa, 0x00000018 }, - { 0x844075bc, 0x00000002 }, - { 0x000000d4, 0x00000004 }, - { 0x804075bd, 0x00000002 }, - { 0x800075bb, 0x00000002 }, - { 0x804075bc, 0x00000002 }, - { 0x00108000, 0x00000002 }, - { 0x01400000, 0x00000002 }, - { 0x006000d8, 0x0000000c }, - { 0x20c07000, 0x00000020 }, - { 0x000000da, 0x00000012 }, - { 0x00800000, 0x00000006 }, - { 0x0080751d, 0x00000006 }, - { 0x000025bb, 0x00000002 }, - { 0x000040d4, 0x00000004 }, - { 0x0000775c, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460275d, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x00007999, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460299b, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x01e00830, 0x00000002 }, - { 0x21007000, 0000000000 }, - { 0x00005000, 0x00000002 }, - { 0x00038056, 0x00000002 }, - { 0x040025e0, 0x00000002 }, - { 0x000075e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000380ed, 0x00000002 }, - { 0x04007394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000078c4, 0x00000002 }, - { 0x000078c5, 0x00000002 }, - { 0x000078c6, 0x00000002 }, - { 0x00007924, 0x00000002 }, - { 0x00007925, 0x00000002 }, - { 0x00007926, 0x00000002 }, - { 0x000000f2, 0x00000004 }, - { 0x00007924, 0x00000002 }, - { 0x00007925, 0x00000002 }, - { 0x00007926, 0x00000002 }, - { 0x000000f9, 0x00000004 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 R300_cp_microcode[][2] = { - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x000000ae, 0x00000008 }, - { 0x000000b2, 0x00000008 }, - { 0x67554b4a, 0000000000 }, - { 0x4a4a4475, 0000000000 }, - { 0x55527d83, 0000000000 }, - { 0x4a8c8b65, 0000000000 }, - { 0x4aef4af6, 0000000000 }, - { 0x4ae14a4a, 0000000000 }, - { 0xe4979797, 0000000000 }, - { 0xdb4aebdd, 0000000000 }, - { 0x9ccc4a4a, 0000000000 }, - { 0xd1989898, 0000000000 }, - { 0x4a0f9ad6, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000080, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x00012000, 0x00000004 }, - { 0x00082000, 0x00000004 }, - { 0x1800650e, 0x00000004 }, - { 0x00092000, 0x00000004 }, - { 0x000a2000, 0x00000004 }, - { 0x000f0000, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x00000074, 0x00000018 }, - { 0x0000e563, 0x00000004 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0000a069, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000077, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000077, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0007a, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000084, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000086, 0x00000008 }, - { 0x00c00085, 0x00000008 }, - { 0x000700e3, 0x00000004 }, - { 0x00000092, 0x00000038 }, - { 0x000ca094, 0x00000030 }, - { 0x080045bb, 0x00000004 }, - { 0x000c2095, 0x00000030 }, - { 0x0800e5bc, 0000000000 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x00120000, 0x0000000c }, - { 0x00120000, 0x00000004 }, - { 0x001b0002, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x000000a4, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x000000a1, 0x00000008 }, - { 0x000000a6, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x000000ad, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x001400a9, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700e3, 0x00000004 }, - { 0x000000c0, 0x00000038 }, - { 0x000c2095, 0x00000030 }, - { 0x0880e5bd, 0x00000005 }, - { 0x000c2094, 0x00000030 }, - { 0x0800e5bb, 0x00000005 }, - { 0x000c2095, 0x00000030 }, - { 0x0880e5bc, 0x00000005 }, - { 0x000000c3, 0x00000008 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000c7, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000c9, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080c3, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700e0, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000e4, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000eb, 0x00000008 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000f3, 0x00000034 }, - { 0x000000f0, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 R420_cp_microcode[][2] = { - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x00000099, 0x00000008 }, - { 0x0000009d, 0x00000008 }, - { 0x4a554b4a, 0000000000 }, - { 0x4a4a4467, 0000000000 }, - { 0x55526f75, 0000000000 }, - { 0x4a7e7d65, 0000000000 }, - { 0xd9d3dff6, 0000000000 }, - { 0x4ac54a4a, 0000000000 }, - { 0xc8828282, 0000000000 }, - { 0xbf4acfc1, 0000000000 }, - { 0x87b04a4a, 0000000000 }, - { 0xb5838383, 0000000000 }, - { 0x4a0f85ba, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000072, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000069, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0006c, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000076, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000078, 0x00000008 }, - { 0x00c00077, 0x00000008 }, - { 0x000700c7, 0x00000004 }, - { 0x00000080, 0x00000038 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x0000008f, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x0000008c, 0x00000008 }, - { 0x00000091, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x00000098, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x00140094, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700c7, 0x00000004 }, - { 0x000000a4, 0x00000038 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000ab, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000ad, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080a7, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700c4, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000c8, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000cf, 0x00000008 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000d7, 0x00000034 }, - { 0x000000d4, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0x0000e1cc, 0x00000004 }, - { 0x0500e1cd, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x000000de, 0x00000034 }, - { 0x000000da, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x0019e1cc, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x0500a000, 0x00000004 }, - { 0x080041cd, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 RS600_cp_microcode[][2] = { - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x000000a0, 0x00000008 }, - { 0x000000a4, 0x00000008 }, - { 0x4a554b4a, 0000000000 }, - { 0x4a4a4467, 0000000000 }, - { 0x55526f75, 0000000000 }, - { 0x4a7e7d65, 0000000000 }, - { 0x4ae74af6, 0000000000 }, - { 0x4ad34a4a, 0000000000 }, - { 0xd6898989, 0000000000 }, - { 0xcd4addcf, 0000000000 }, - { 0x8ebe4ae2, 0000000000 }, - { 0xc38a8a8a, 0000000000 }, - { 0x4a0f8cc8, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000072, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000069, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0006c, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000076, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000078, 0x00000008 }, - { 0x00c00077, 0x00000008 }, - { 0x000700d5, 0x00000004 }, - { 0x00000084, 0x00000038 }, - { 0x000ca086, 0x00000030 }, - { 0x080045bb, 0x00000004 }, - { 0x000c2087, 0x00000030 }, - { 0x0800e5bc, 0000000000 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x00120000, 0x0000000c }, - { 0x00120000, 0x00000004 }, - { 0x001b0002, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x00000096, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x00000093, 0x00000008 }, - { 0x00000098, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x0000009f, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x0014009b, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700d5, 0x00000004 }, - { 0x000000b2, 0x00000038 }, - { 0x000c2087, 0x00000030 }, - { 0x0880e5bd, 0x00000005 }, - { 0x000c2086, 0x00000030 }, - { 0x0800e5bb, 0x00000005 }, - { 0x000c2087, 0x00000030 }, - { 0x0880e5bc, 0x00000005 }, - { 0x000000b5, 0x00000008 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000b9, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000bb, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080b5, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700d2, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000d6, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000dd, 0x00000008 }, - { 0x00e00116, 0000000000 }, - { 0x000700e1, 0x00000004 }, - { 0x0800401c, 0x00000004 }, - { 0x200050e7, 0x00000004 }, - { 0x0000e01d, 0x00000004 }, - { 0x000000e4, 0x00000008 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000eb, 0x00000034 }, - { 0x000000e8, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 RS690_cp_microcode[][2] = { - { 0x000000dd, 0x00000008 }, - { 0x000000df, 0x00000008 }, - { 0x000000a0, 0x00000008 }, - { 0x000000a4, 0x00000008 }, - { 0x4a554b4a, 0000000000 }, - { 0x4a4a4467, 0000000000 }, - { 0x55526f75, 0000000000 }, - { 0x4a7e7d65, 0000000000 }, - { 0x4ad74af6, 0000000000 }, - { 0x4ac94a4a, 0000000000 }, - { 0xcc898989, 0000000000 }, - { 0xc34ad3c5, 0000000000 }, - { 0x8e4a4a4a, 0000000000 }, - { 0x4a8a8a8a, 0000000000 }, - { 0x4a0f8c4a, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000072, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000069, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0006c, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000076, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000078, 0x00000008 }, - { 0x00c00077, 0x00000008 }, - { 0x000700cb, 0x00000004 }, - { 0x00000084, 0x00000038 }, - { 0x000ca086, 0x00000030 }, - { 0x080045bb, 0x00000004 }, - { 0x000c2087, 0x00000030 }, - { 0x0800e5bc, 0000000000 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x00120000, 0x0000000c }, - { 0x00120000, 0x00000004 }, - { 0x001b0002, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x00000096, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x00000093, 0x00000008 }, - { 0x00000098, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x0000009f, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x0014009b, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x00100000, 0x0000002c }, - { 0x00004000, 0000000000 }, - { 0x080045c8, 0x00000004 }, - { 0x00240005, 0x00000004 }, - { 0x08004d0b, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700cb, 0x00000004 }, - { 0x000000b7, 0x00000038 }, - { 0x000c2087, 0x00000030 }, - { 0x0880e5bd, 0x00000005 }, - { 0x000c2086, 0x00000030 }, - { 0x0800e5bb, 0x00000005 }, - { 0x000c2087, 0x00000030 }, - { 0x0880e5bc, 0x00000005 }, - { 0x000000ba, 0x00000008 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000be, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000c0, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080ba, 0x00000008 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700c8, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000cc, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000d3, 0x00000008 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000db, 0x00000034 }, - { 0x000000d8, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0x000000e1, 0x00000030 }, - { 0x4200e000, 0000000000 }, - { 0x000000e1, 0x00000030 }, - { 0x4000e000, 0000000000 }, - { 0x0025001b, 0x00000004 }, - { 0x00230000, 0x00000004 }, - { 0x00250005, 0x00000004 }, - { 0x000000e6, 0x00000034 }, - { 0000000000, 0x0000000c }, - { 0x00244000, 0x00000004 }, - { 0x080045c8, 0x00000004 }, - { 0x00240005, 0x00000004 }, - { 0x08004d0b, 0x0000000c }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static const u32 R520_cp_microcode[][2] = { - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x00000099, 0x00000008 }, - { 0x0000009d, 0x00000008 }, - { 0x4a554b4a, 0000000000 }, - { 0x4a4a4467, 0000000000 }, - { 0x55526f75, 0000000000 }, - { 0x4a7e7d65, 0000000000 }, - { 0xe0dae6f6, 0000000000 }, - { 0x4ac54a4a, 0000000000 }, - { 0xc8828282, 0000000000 }, - { 0xbf4acfc1, 0000000000 }, - { 0x87b04ad5, 0000000000 }, - { 0xb5838383, 0000000000 }, - { 0x4a0f85ba, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000e000, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x00000047, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022051, 0x00000028 }, - { 0x00000051, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a04b, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000052, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce05e, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x0000005e, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000055, 0x00000008 }, - { 0x00802061, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000064, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000072, 0x00000030 }, - { 0x00000055, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000069, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x00000069, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0006c, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000076, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x00000078, 0x00000008 }, - { 0x00c00077, 0x00000008 }, - { 0x000700c7, 0x00000004 }, - { 0x00000080, 0x00000038 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x0000008f, 0x00000018 }, - { 0x00c0a000, 0x00000004 }, - { 0x0000008c, 0x00000008 }, - { 0x00000091, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x00000098, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x00140094, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700c7, 0x00000004 }, - { 0x000000a4, 0x00000038 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000ab, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000ad, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080a7, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700c4, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x0000e8c4, 0x00000004 }, - { 0x0000e8c5, 0x00000004 }, - { 0x0000e8c6, 0x00000004 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000c8, 0x00000008 }, - { 0x0000e928, 0x00000004 }, - { 0x0000e929, 0x00000004 }, - { 0x0000e92a, 0x00000004 }, - { 0x000000cf, 0x00000008 }, - { 0xdeadbeef, 0000000000 }, - { 0x00000116, 0000000000 }, - { 0x000700d3, 0x00000004 }, - { 0x080050e7, 0x00000004 }, - { 0x000700d4, 0x00000004 }, - { 0x0800401c, 0x00000004 }, - { 0x0000e01d, 0000000000 }, - { 0x02c02000, 0x00000004 }, - { 0x00060000, 0x00000004 }, - { 0x000000de, 0x00000034 }, - { 0x000000db, 0x00000008 }, - { 0x00008000, 0x00000004 }, - { 0xc000e000, 0000000000 }, - { 0x0000e1cc, 0x00000004 }, - { 0x0500e1cd, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x000000e5, 0x00000034 }, - { 0x000000e1, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x0019e1cc, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x0500a000, 0x00000004 }, - { 0x080041cd, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x001d0018, 0x00000004 }, - { 0x001a0001, 0x00000004 }, - { 0x000000fb, 0x00000034 }, - { 0x0000004a, 0x00000008 }, - { 0x0500a04a, 0x00000008 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - - -#endif diff --git a/firmware/Makefile b/firmware/Makefile index 6ea4e3d..d166a7f 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -44,6 +44,20 @@ fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \ cxgb3/t3fw-7.4.0.bin fw-shipped-$(CONFIG_DRM_MGA) += matrox/g200_warp.fw matrox/g400_warp.fw fw-shipped-$(CONFIG_DRM_R128) += r128/r128_cce.bin +fw-shipped-$(CONFIG_DRM_RADEON) += radeon/R100_cp.bin radeon/R200_cp.bin \ + radeon/R300_cp.bin radeon/R420_cp.bin \ + radeon/RS690_cp.bin radeon/RS600_cp.bin \ + radeon/R520_cp.bin \ + radeon/R600_pfp.bin radeon/R600_me.bin \ + radeon/RV610_pfp.bin radeon/RV610_me.bin \ + radeon/RV630_pfp.bin radeon/RV630_me.bin \ + radeon/RV620_pfp.bin radeon/RV620_me.bin \ + radeon/RV635_pfp.bin radeon/RV635_me.bin \ + radeon/RV670_pfp.bin radeon/RV670_me.bin \ + radeon/RS780_pfp.bin radeon/RS780_me.bin \ + radeon/RV770_pfp.bin radeon/RV770_me.bin \ + radeon/RV730_pfp.bin radeon/RV730_me.bin \ + radeon/RV710_pfp.bin radeon/RV710_me.bin fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \ diff --git a/firmware/WHENCE b/firmware/WHENCE index 578d859..00378ee 100644 --- a/firmware/WHENCE +++ b/firmware/WHENCE @@ -761,3 +761,61 @@ Copyright 2000 Advanced Micro Devices, Inc. Found in decimal form in kernel source. -------------------------------------------------------------------------- + +Driver: radeon - ATI Radeon + +File: radeon/R100_cp.bin +File: radeon/R200_cp.bin +File: radeon/R300_cp.bin +File: radeon/R420_cp.bin +File: radeon/RS600_cp.bin +File: radeon/RS690_cp.bin +File: radeon/R520_cp.bin +File: radeon/R600_pfp.bin +File: radeon/R600_me.bin +File: radeon/RV610_pfp.bin +File: radeon/RV610_me.bin +File: radeon/RV630_pfp.bin +File: radeon/RV630_me.bin +File: radeon/RV620_pfp.bin +File: radeon/RV620_me.bin +File: radeon/RV635_pfp.bin +File: radeon/RV635_me.bin +File: radeon/RV670_pfp.bin +File: radeon/RV670_me.bin +File: radeon/RS780_pfp.bin +File: radeon/RS780_me.bin +File: radeon/RV770_pfp.bin +File: radeon/RV770_me.bin +File: radeon/RV730_pfp.bin +File: radeon/RV730_me.bin +File: radeon/RV710_pfp.bin +File: radeon/RV710_me.bin + +Licence: + + * Copyright 2007-2009 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Found in hex form in kernel source. + +-------------------------------------------------------------------------- diff --git a/firmware/radeon/R100_cp.bin.ihex b/firmware/radeon/R100_cp.bin.ihex new file mode 100644 index 0000000..151647b --- /dev/null +++ b/firmware/radeon/R100_cp.bin.ihex @@ -0,0 +1,130 @@ +:1000000000000000210070000000000020007000CF +:1000100000000004000000B400000004000000B86C +:10002000000000006F5B4D4C000000004C4C427F14 +:10003000000000005B568A92000000004CA09C6DFE +:1000400000000000AD4C4C4C000000004CE1AF3D06 +:1000500000000000D8AFAFAF00000000D64C4CDC71 +:10006000000000004CD10D1000000016000F000031 +:1000700000000000362F242D0000000400000012B4 +:1000800000000016000F000000000000362F282D91 +:1000900000000002000380E70000000204002C972B +:1000A00000000016000F000100000000333A373056 +:1000B00000000002000077EF0000000200061000C0 +:1000C0000000001A000000210000001E0000400097 +:1000D00000000002000610000000001A00000021CD +:1000E0000000001E0000400000000002000610009A +:1000F0000000001A000000210000001E0000400067 +:100100000000000400000017000000020003802B24 +:1001100000000002040067E0000000040000001777 +:1001200000000002000077E000000002000650001E +:1001300000000002000037E100000006040067E153 +:1001400000000002000077E000000002000077E1FC +:1001500000000006000077E100000000FFFFFFFF45 +:100160000000000010000000000000020003802BCF +:1001700000000006040067E0000000020000767541 +:100180000000000200007676000000020000767792 +:100190000000000600007678000000020003802CBA +:1001A00000000002040026760000000200007677BE +:1001B0000000000600007678000000180000002F04 +:1001C000000000180000002F0000000600000000E2 +:1001D000000000180000003000000018000000308F +:1001E0000000000600000000000000020160500056 +:1001F000000000020006500000000002000980001C +:1002000000000002000610000000000464C0603E10 +:1002100000000002000380E600000002040025C583 +:1002200000000016000800000000000000000000B0 +:10023000000000020400251D00000002000075807F +:100240000000000200067581000000020400258005 +:100250000000000200067581000000040000004953 +:10026000000000000000500000000002000380E6D3 +:1002700000000002040025C5000000020006100076 +:10028000000000020000750E000000020001900056 +:10029000000000140001105500000012000000557D +:1002A000000000020400250F000000040000504F71 +:1002B00000000002000380E600000002040025C5E3 +:1002C0000000000200007565000000020000756675 +:1002D000000000040000005800000002000380E657 +:1002E00000000002040025C50000000201E655B42C +:1002F000000000024401B0E40000000201C110E46B +:10030000000000182666706600000002040C2565D7 +:1003100000000018000000660000000204002564D0 +:100320000000000200007566000000040000005D8F +:1003300000000008004010690000000200101000DA +:1003400000000002000D80FF000000080080006C2B +:1003500000000002000F900000000002000E00FFED +:100360000000000600000000000000180000008FE0 +:10037000000000040000005B00000002000380E6B3 +:1003800000000002040025C5000000020000757690 +:100390000000000200065000000000020000900073 +:1003A0000000000200041000000000020C00350EE6 +:1003B0000000000200049000000000020005100090 +:1003C0000000000201E785F80000000200200000A4 +:1003D0000000000C0060007E000000020000756359 +:1003E00000000021006075F0000000042000707320 +:1003F000000000040000507300000002000380E6CB +:1004000000000002040025C500000002000075760F +:100410000000000200007577000000020000750E69 +:10042000000000020000750F0000000200A0500054 +:100430000000000C0060008300000021006075F0E7 +:1004400000000002000075F80000000400000083B6 +:1004500000000002000A750E00000002000380E6A2 +:1004600000000002040025C5000000020020750FF6 +:1004700000000004006000860000000200007570AB +:100480000000000200007571000000060000757297 +:1004900000000002000380E600000002040025C501 +:1004A00000000002000050000000000200A0500008 +:1004B0000000000200007568000000020006100045 +:1004C0000000000C00000095000000020005800004 +:1004D000000000020C60756200000004000000973C +:1004E00000000002000380E600000002040025C5B1 +:1004F000000000040060009600000000400070E56D +:1005000000000002000380E600000002040025C590 +:1005100000000002000380E50000001C000000A8AD +:1005200000000018000650AA00000002040025BBCD +:1005300000000018000610AB00000000040075BCAD +:1005400000000002000075BB00000000000075BC48 +:100550000000000600090000000000020009000081 +:1005600000000006000D800200000002000078324A +:10057000000000020000500000000002000380E7BD +:100580000000000204002C97000000020000782008 +:100590000000000200007821000000000000780048 +:1005A000000000020120000000000002200770008F +:1005B0000000000201200000000000022000700086 +:1005C0000000000200061000000000020120751B60 +:1005D000000000028040750A000000028040750B98 +:1005E000000000020011000000000002000380E58E +:1005F0000000001C000000C600000018000610AB40 +:1006000000000002844075BD00000018000610AA1A +:1006100000000002840075BB00000018000610AB4B +:1006200000000002844075BC00000004000000C906 +:1006300000000002804075BD00000002800075BB14 +:1006400000000002804075BC000000020010800025 +:1006500000000002014000000000000C006000CD1E +:100660000000002020C0700000000012000000CF39 +:100670000000000600800000000000060080751DDC +:100680000000000000000000000000020000775C95 +:100690000000000200A050000000000200661000F0 +:1006A000000000200460275D000000000000400002 +:1006B0000000000201E0083000000000210070008E +:1006C000000000006464614D00000000696874204F +:1006D00000000000000000730000000000000000A7 +:1006E000000000020000500000000002000380D063 +:1006F00000000002040025E000000000000075E199 +:10070000000000000000000100000002000380E083 +:1007100000000002040023940000000000005000CC +:1007200000000000000000000000000000000000C9 +:1007300000000000000000080000000000000004AD +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/R200_cp.bin.ihex b/firmware/radeon/R200_cp.bin.ihex new file mode 100644 index 0000000..3a0bd73 --- /dev/null +++ b/firmware/radeon/R200_cp.bin.ihex @@ -0,0 +1,130 @@ +:1000000000000000210070000000000020007000CF +:1000100000000004000000BF00000004000000C356 +:10002000000000007A685E5D000000005D5D55889C +:100030000000000068659197000000005DA19F78B6 +:10004000000000005D5D5D5D000000005DEE5D5044 +:1000500000000000F2ACACAC00000000E75DF9E984 +:1000600000000000B1DD0E1100000000E2AFAFAFF4 +:1000700000000016000F000000000000452F232D97 +:10008000000000040000001300000016000F000034 +:1000900000000000452F272D00000016000F000172 +:1000A000000000003E4D4A3700000002000077EFDC +:1000B00000000002000610000000001A00000020EE +:1000C0000000001E000040000000000200061000BA +:1000D0000000001A000000200000001E0000400088 +:1000E00000000002000610000000001A00000020BE +:1000F0000000001E00004000000000040000001688 +:10010000000000020003802A00000002040067E0F3 +:10011000000000040000001600000002000077E06C +:10012000000000020006500000000002000037E15D +:1001300000000006040067E100000002000077E014 +:1001400000000002000077E100000006000077E1F7 +:1001500000000000FFFFFFFF000000001000000093 +:100160000000000007F007F0000000020003802AF2 +:1001700000000006040067E0000000020003802C7D +:100180000000000204002741000000020400274193 +:100190000000000204002743000000020000767502 +:1001A0000000000200007676000000020000767772 +:1001B0000000000600007678000000020003802C9A +:1001C0000000000204002741000000020400274153 +:1001D00000000002040027430000000200007676C1 +:1001E000000000020000767700000006000076782C +:1001F000000000020003802B0000000204002676AD +:100200000000000200007677000000020003802C4E +:100210000000000204002741000000020400274300 +:100220000000000600007678000000020003802C29 +:1002300000000002040027410000000204002741E2 +:10024000000000020400274300000006000076784A +:10025000000000180000002F000000180000002F10 +:100260000000000600000000000000180000003739 +:100270000000001800000037000000060000000029 +:100280000000000201605000000000020006500063 +:1002900000000002000980000000000200061000BB +:1002A0000000000464C06051000000160008000057 +:1002B0000000000000000000000000020400251DF6 +:1002C0000000000200007580000000020006758139 +:1002D0000000000204002580000000020006758175 +:1002E000000000040000005A000000000000500060 +:1002F0000000000200061000000000020000750E61 +:1003000000000002000190000000001400011064D1 +:100310000000001200000064000000020400250F2D +:10032000000000040000505E00000002000075653F +:100330000000000200007566000000040000006577 +:100340000000000201E655B4000000024401B0F0D4 +:100350000000000201C110F0000000182666707154 +:1003600000000002040C2565000000180000007168 +:100370000000000204002564000000020000756611 +:100380000000000400000068000000080040107435 +:10039000000000020010100000000002000D80FFAD +:1003A000000000080080007700000002000F9000AD +:1003B00000000002000E00FF000000060000000028 +:1003C0000000001800000094000000040000006815 +:1003D00000000002000075760000000200065000D8 +:1003E0000000000200009000000000020004100065 +:1003F000000000020C00350E000000020004900016 +:1004000000000002000510000000000201E785F86E +:1004100000000002002000000000000C00600087C7 +:10042000000000020000756300000021006075F00C +:10043000000000042000707C000000040000507CDC +:1004400000000002000075760000000200007577D1 +:10045000000000020000750E000000020000750F91 +:100460000000000200A050000000000C0060008AA4 +:1004700000000021006075F000000002000075F827 +:10048000000000040000008A00000002000A750E4F +:10049000000000020020750F000000040060008DC5 +:1004A000000000020000757000000002000075717D +:1004B00000000006000075720000000200005000FD +:1004C0000000000200A0500000000002000075685B +:1004D00000000002000610000000000C0000009860 +:1004E0000000000200058000000000020C60756240 +:1004F000000000040000009A000000040060009961 +:1005000000000000400070F100000002000380F1D4 +:100510000000001C000000A700000018000650A901 +:1005200000000002040025BB00000018000610AA0D +:1005300000000000040075BC00000002000075BB54 +:1005400000000000000075BC00000006000900006B +:10055000000000020009000000000006000D8002FB +:10056000000000020000500000000002000078219E +:100570000000000000007800000000020000782168 +:10058000000000000000780000000002016650003A +:1005900000000002000A000000000002000671CC0A +:1005A000000000020286F1CD00000010000000B73C +:1005B00000000000210070000000001C000000BED0 +:1005C000000000020006500000000002000A0000C7 +:1005D000000000020006100000000002000B0000F6 +:1005E000000000023806700000000004000A00BA93 +:1005F0000000000020007000000000020120000048 +:10060000000000022007700000000002012000002E +:100610000000000020007000000000020006100032 +:10062000000000020120751B000000028040750AD6 +:10063000000000028040750B000000020011000065 +:1006400000000002000380F10000001C000000D147 +:1006500000000018000610AA00000002844075BDCA +:1006600000000018000610A900000002840075BBFD +:1006700000000018000610AA00000002844075BCAB +:1006800000000004000000D400000002804075BD9E +:1006900000000002800075BB00000002804075BCB5 +:1006A0000000000200108000000000020140000075 +:1006B0000000000C006000D80000002020C0700086 +:1006C00000000012000000DA0000000600800000B8 +:1006D000000000060080751D00000002000025BB20 +:1006E00000000004000040D4000000020000775C1D +:1006F0000000000200A05000000000020066100090 +:10070000000000200460275D0000000000004000A1 +:1007100000000002000079990000000200A05000D3 +:100720000000000200661000000000200460299B09 +:1007300000000000000040000000000201E008305E +:1007400000000000210070000000000200005000C6 +:10075000000000020003805600000002040025E0B3 +:1007600000000000000075E1000000000000000132 +:1007700000000002000380ED0000000004007394FC +:100780000000000000000000000000000000000069 +:1007900000000002000078C400000002000078C5DC +:1007A00000000002000078C600000002000079246A +:1007B00000000002000079250000000200007926F8 +:1007C00000000004000000F2000000020000792494 +:1007D00000000002000079250000000200007926D8 +:1007E00000000004000000F900000000000000000C +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/R300_cp.bin.ihex b/firmware/radeon/R300_cp.bin.ihex new file mode 100644 index 0000000..d307d56 --- /dev/null +++ b/firmware/radeon/R300_cp.bin.ihex @@ -0,0 +1,130 @@ +:10000000000000004200E000000000004000E000AE +:1000100000000008000000AE00000008000000B270 +:100020000000000067554B4A000000004A4A447532 +:100030000000000055527D83000000004A8C8B6553 +:10004000000000004AEF4AF6000000004AE14A4A78 +:1000500000000000E497979700000000DB4AEBDD0A +:10006000000000009CCC4A4A00000000D1989898FB +:10007000000000004A0F9AD600000004000CA00007 +:1000800000000038000D0012000000040000E8B479 +:1000900000000038000D0014000000040000E8B665 +:1000A00000000038000D0016000000040000E854B5 +:1000B00000000038000D0018000000040000E855A2 +:1000C00000000038000D001A000000040000E8568F +:1000D00000000038000D001C000000040000E8577C +:1000E00000000038000D001E000000040000E8249D +:1000F00000000038000D0020000000040000E8258A +:1001000000000038000D0022000000040000E8306C +:1001100000000038000D0024000000040000F0C0C2 +:1001200000000038000D0026000000040000F0C1AF +:1001300000000038000D0028000000040000F0411D +:1001400000000038000D002A000000040000F184C7 +:1001500000000038000D002C000000040000F185B4 +:1001600000000038000D002E000000040000F186A1 +:1001700000000038000D0030000000040000F1878E +:1001800000000038000D0032000000040000F18083 +:1001900000000038000D0034000000040000F3935C +:1001A00000000038000D0036000000040000F38A53 +:1001B00000000038000D0038000000040000F38E3D +:1001C000000000040000E821000000040140A0003D +:1001D00000000018000000430000000400CCE8000C +:1001E00000000004001B000100000004080048009B +:1001F00000000004001B000100000004080048008B +:1002000000000004001B000100000004080048007A +:10021000000000080000003A000000000000A000FC +:10022000000000042000451D000000040000E580DF +:1002300000000004000CE581000000040800458077 +:1002400000000004000CE5810000000800000047E9 +:10025000000000000000A00000000004000C2000CE +:10026000000000040000E50E000000040003200070 +:10027000000000280002205100000024000000516E +:10028000000000040800450F000000080000A04B1B +:10029000000000040000E565000000040000E566C1 +:1002A00000000008000000520000000403CCA5B4C8 +:1002B00000000004054320000000000400022000AC +:1002C000000000304CCCE05E0000000408274565CB +:1002D000000000300000005E0000000408004564DB +:1002E000000000040000E566000000080000005562 +:1002F00000000010008020610000000400202000A9 +:1003000000000004001B00FF00000010010000645A +:1003100000000004001F200000000004001C00FF7B +:100320000000000C00000000000000300000008011 +:100330000000000800000055000000040000E57601 +:1003400000000004000CA0000000000400012000D8 +:100350000000000400082000000000041800650EE2 +:10036000000000040009200000000004000A200032 +:1003700000000004000F0000000000040040000026 +:100380000000001800000074000000040000E56395 +:10039000000000C200C0E5F900000008000000698C +:1003A000000000080000A069000000040000E576DD +:1003B000000000040000E577000000040000E50EE6 +:1003C000000000040000E50F000000040140A00050 +:1003D0000000001800000077000000C200C0E5F92E +:1003E0000000000800000077000000040014E50E83 +:1003F000000000040040E50F0000000800C0007A83 +:10040000000000040000E570000000040000E57139 +:100410000000000C0000E572000000040000A000D5 +:10042000000000040140A000000000040000E56896 +:1004300000000004000C20000000001800000084F0 +:1004400000000004000B00000000000418C0E5627A +:1004500000000008000000860000000800C00085C1 +:1004600000000004000700E30000003800000092D4 +:1004700000000030000CA09400000004080045BB00 +:1004800000000030000C2095000000000800E5BCD2 +:10049000000000040000E5BB000000000000E5BC17 +:1004A0000000000C00120000000000040012000018 +:1004B0000000000C001B0002000000040000A0006F +:1004C000000000040000E821000000000000E80037 +:1004D000000000040000E821000000000000E82EF9 +:1004E0000000000402CCA000000000040014000082 +:1004F00000000004000CE1CC00000004050DE1CD7B +:10050000000000040040000000000018000000A4EB +:100510000000000400C0A00000000008000000A1CE +:1005200000000020000000A6000000004200E000E3 +:1005300000000038000000AD00000004000CA00026 +:10054000000000040014000000000004000C200063 +:10055000000000040016000000000004700CE00021 +:1005600000000008001400A9000000004000E000A6 +:10057000000000040240000000000004400EE00003 +:100580000000000402400000000000004000E00005 +:1005900000000004000C2000000000040240E51BE5 +:1005A000000000050080E50A000000050080E50B62 +:1005B000000000040022000000000004000700E327 +:1005C00000000038000000C000000030000C209542 +:1005D000000000050880E5BD00000030000C2094FC +:1005E000000000050800E5BB00000030000C20956D +:1005F000000000050880E5BC00000008000000C302 +:10060000000000050080E5BD000000050000E5BB1E +:10061000000000050080E5BC00000004002100008F +:1006200000000004028000000000001800C000C7A5 +:10063000000000404180E00000000024000000C9EC +:100640000000000C010000000000000C0100E51D8E +:1006500000000004000045BB00000008000080C34B +:10066000000000040000F3CE000000040140A000E0 +:100670000000000400CC20000000004008C053CF60 +:100680000000000000008000000000040000F3D221 +:10069000000000040140A0000000000400CC200085 +:1006A0000000004008C053D300000000000080009C +:1006B000000000040000F39D000000040140A000C1 +:1006C0000000000400CC20000000004008C0539E41 +:1006D00000000000000080000000000403C008309B +:1006E000000000004200E000000000040000A00044 +:1006F00000000004200045E0000000000000E5E1EB +:10070000000000000000000100000004000700E0FD +:10071000000000000800E39400000000000000005A +:10072000000000040000E8C4000000040000E8C568 +:10073000000000040000E8C6000000040000E928F2 +:10074000000000040000E929000000040000E92A7C +:1007500000000008000000E4000000040000E92898 +:10076000000000040000E929000000040000E92A5C +:1007700000000008000000EB0000000402C02000A0 +:10078000000000040006000000000034000000F338 +:1007900000000008000000F00000000400008000DD +:1007A00000000000C000E0000000000000000000A9 +:1007B00000000004000C200000000004001D0018D0 +:1007C00000000004001A000100000034000000FBDB +:1007D000000000080000004A000000080500A04AD0 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/R420_cp.bin.ihex b/firmware/radeon/R420_cp.bin.ihex new file mode 100644 index 0000000..3815891 --- /dev/null +++ b/firmware/radeon/R420_cp.bin.ihex @@ -0,0 +1,130 @@ +:10000000000000004200E000000000004000E000AE +:100010000000000800000099000000080000009D9A +:10002000000000004A554B4A000000004A4A44675D +:100030000000000055526F75000000004A7E7D658B +:1000400000000000D9D3DFF6000000004AC54A4A8C +:1000500000000000C882828200000000BF4ACFC1B9 +:100060000000000087B04A4A00000000B583838387 +:10007000000000004A0F85BA00000004000CA00038 +:1000800000000038000D0012000000040000E8B479 +:1000900000000038000D0014000000040000E8B665 +:1000A00000000038000D0016000000040000E854B5 +:1000B00000000038000D0018000000040000E855A2 +:1000C00000000038000D001A000000040000E8568F +:1000D00000000038000D001C000000040000E8577C +:1000E00000000038000D001E000000040000E8249D +:1000F00000000038000D0020000000040000E8258A +:1001000000000038000D0022000000040000E8306C +:1001100000000038000D0024000000040000F0C0C2 +:1001200000000038000D0026000000040000F0C1AF +:1001300000000038000D0028000000040000F0411D +:1001400000000038000D002A000000040000F184C7 +:1001500000000038000D002C000000040000F185B4 +:1001600000000038000D002E000000040000F186A1 +:1001700000000038000D0030000000040000F1878E +:1001800000000038000D0032000000040000F18083 +:1001900000000038000D0034000000040000F3935C +:1001A00000000038000D0036000000040000F38A53 +:1001B00000000038000D0038000000040000F38E3D +:1001C000000000040000E821000000040140A0003D +:1001D00000000018000000430000000400CCE8000C +:1001E00000000004001B000100000004080048009B +:1001F00000000004001B000100000004080048008B +:1002000000000004001B000100000004080048007A +:10021000000000080000003A000000000000A000FC +:10022000000000042000451D000000040000E580DF +:1002300000000004000CE581000000040800458077 +:1002400000000004000CE5810000000800000047E9 +:10025000000000000000A00000000004000C2000CE +:10026000000000040000E50E000000040003200070 +:10027000000000280002205100000024000000516E +:10028000000000040800450F000000080000A04B1B +:10029000000000040000E565000000040000E566C1 +:1002A00000000008000000520000000403CCA5B4C8 +:1002B00000000004054320000000000400022000AC +:1002C000000000304CCCE05E0000000408274565CB +:1002D000000000300000005E0000000408004564DB +:1002E000000000040000E566000000080000005562 +:1002F00000000010008020610000000400202000A9 +:1003000000000004001B00FF00000010010000645A +:1003100000000004001F200000000004001C00FF7B +:100320000000000C0000000000000030000000721F +:100330000000000800000055000000040000E57601 +:10034000000000040000E577000000040000E50E56 +:10035000000000040000E50F000000040140A000C0 +:100360000000001800000069000000C200C0E5F9AC +:100370000000000800000069000000040014E50E01 +:10038000000000040040E50F0000000800C0006C01 +:10039000000000040000E570000000040000E571AA +:1003A0000000000C0000E572000000040000A00046 +:1003B000000000040140A000000000040000E56807 +:1003C00000000004000C200000000018000000766F +:1003D00000000004000B00000000000418C0E562EB +:1003E00000000008000000780000000800C000774E +:1003F00000000004000700C7000000380000008073 +:10040000000000040000E5BB000000000000E5BCA7 +:10041000000000040000A000000000040000E8212B +:10042000000000000000E800000000040000E821D7 +:10043000000000000000E82E0000000402CCA00034 +:10044000000000040014000000000004000CE1CCD7 +:1004500000000004050DE1CD000000040040000094 +:10046000000000180000008F0000000400C0A00081 +:10047000000000080000008C000000200000009137 +:10048000000000004200E00000000038000000987A +:1004900000000004000CA000000000040014000094 +:1004A00000000004000C2000000000040016000002 +:1004B00000000004700CE00000000008001400942C +:1004C000000000004000E0000000000402400000C6 +:1004D00000000004400EE0000000000402400000A4 +:1004E000000000004000E00000000004000C2000BC +:1004F000000000040240E51B000000050080E50A42 +:10050000000000050080E50B000000040022000050 +:1005100000000004000700C700000038000000A42D +:10052000000000050080E5BD000000050000E5BBFF +:10053000000000050080E5BC000000040021000070 +:1005400000000004028000000000001800C000ABA2 +:10055000000000404180E00000000024000000ADE9 +:100560000000000C010000000000000C0100E51D6F +:1005700000000004000045BB00000008000080A748 +:10058000000000040000F3CE000000040140A000C1 +:100590000000000400CC20000000004008C053CF41 +:1005A0000000000000008000000000040000F3D202 +:1005B000000000040140A0000000000400CC200066 +:1005C0000000004008C053D300000000000080007D +:1005D000000000040000F39D000000040140A000A2 +:1005E0000000000400CC20000000004008C0539E22 +:1005F00000000000000080000000000403C008307C +:10060000000000004200E000000000040000A00024 +:1006100000000004200045E0000000000000E5E1CB +:10062000000000000000000100000004000700C4FA +:10063000000000000800E39400000000000000003B +:10064000000000040000E8C4000000040000E8C549 +:10065000000000040000E8C6000000040000E928D3 +:10066000000000040000E929000000040000E92A5D +:1006700000000008000000C8000000040000E92895 +:10068000000000040000E929000000040000E92A3D +:1006900000000008000000CF0000000402C020009D +:1006A000000000040006000000000034000000D735 +:1006B00000000008000000D40000000400008000DA +:1006C00000000000C000E000000000040000E1CCD9 +:1006D000000000040500E1CD00000004000CA000B3 +:1006E00000000034000000DE00000008000000DA16 +:1006F000000000000000A000000000040019E1CC90 +:1007000000000004001B0001000000040500A00020 +:1007100000000004080041CD00000004000CA0000F +:1007200000000034000000FB000000080000004A48 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B00000000004000C200000000004001D0018D0 +:1007C00000000004001A000100000034000000FBDB +:1007D000000000080000004A000000080500A04AD0 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/R520_cp.bin.ihex b/firmware/radeon/R520_cp.bin.ihex new file mode 100644 index 0000000..372ff82 --- /dev/null +++ b/firmware/radeon/R520_cp.bin.ihex @@ -0,0 +1,130 @@ +:10000000000000004200E000000000004000E000AE +:100010000000000800000099000000080000009D9A +:10002000000000004A554B4A000000004A4A44675D +:100030000000000055526F75000000004A7E7D658B +:1000400000000000E0DAE6F6000000004AC54A4A77 +:1000500000000000C882828200000000BF4ACFC1B9 +:100060000000000087B04AD500000000B5838383FC +:10007000000000004A0F85BA00000004000CA00038 +:1000800000000038000D0012000000040000E8B479 +:1000900000000038000D0014000000040000E8B665 +:1000A00000000038000D0016000000040000E854B5 +:1000B00000000038000D0018000000040000E855A2 +:1000C00000000038000D001A000000040000E8568F +:1000D00000000038000D001C000000040000E8577C +:1000E00000000038000D001E000000040000E8249D +:1000F00000000038000D0020000000040000E8258A +:1001000000000038000D0022000000040000E8306C +:1001100000000038000D0024000000040000F0C0C2 +:1001200000000038000D0026000000040000F0C1AF +:1001300000000038000D0028000000040000E0006E +:1001400000000038000D002A000000040000E0005C +:1001500000000038000D002C000000040000E0004A +:1001600000000038000D002E000000040000E00038 +:1001700000000038000D0030000000040000E00026 +:1001800000000038000D0032000000040000F18083 +:1001900000000038000D0034000000040000F3935C +:1001A00000000038000D0036000000040000F38A53 +:1001B00000000038000D0038000000040000F38E3D +:1001C000000000040000E821000000040140A0003D +:1001D00000000018000000430000000400CCE8000C +:1001E00000000004001B000100000004080048009B +:1001F00000000004001B000100000004080048008B +:1002000000000004001B000100000004080048007A +:10021000000000080000003A000000000000A000FC +:10022000000000042000451D000000040000E580DF +:1002300000000004000CE581000000040800458077 +:1002400000000004000CE5810000000800000047E9 +:10025000000000000000A00000000004000C2000CE +:10026000000000040000E50E000000040003200070 +:10027000000000280002205100000024000000516E +:10028000000000040800450F000000080000A04B1B +:10029000000000040000E565000000040000E566C1 +:1002A00000000008000000520000000403CCA5B4C8 +:1002B00000000004054320000000000400022000AC +:1002C000000000304CCCE05E0000000408274565CB +:1002D000000000300000005E0000000408004564DB +:1002E000000000040000E566000000080000005562 +:1002F00000000010008020610000000400202000A9 +:1003000000000004001B00FF00000010010000645A +:1003100000000004001F200000000004001C00FF7B +:100320000000000C0000000000000030000000721F +:100330000000000800000055000000040000E57601 +:10034000000000040000E577000000040000E50E56 +:10035000000000040000E50F000000040140A000C0 +:100360000000001800000069000000C200C0E5F9AC +:100370000000000800000069000000040014E50E01 +:10038000000000040040E50F0000000800C0006C01 +:10039000000000040000E570000000040000E571AA +:1003A0000000000C0000E572000000040000A00046 +:1003B000000000040140A000000000040000E56807 +:1003C00000000004000C200000000018000000766F +:1003D00000000004000B00000000000418C0E562EB +:1003E00000000008000000780000000800C000774E +:1003F00000000004000700C7000000380000008073 +:10040000000000040000E5BB000000000000E5BCA7 +:10041000000000040000A000000000040000E8212B +:10042000000000000000E800000000040000E821D7 +:10043000000000000000E82E0000000402CCA00034 +:10044000000000040014000000000004000CE1CCD7 +:1004500000000004050DE1CD000000040040000094 +:10046000000000180000008F0000000400C0A00081 +:10047000000000080000008C000000200000009137 +:10048000000000004200E00000000038000000987A +:1004900000000004000CA000000000040014000094 +:1004A00000000004000C2000000000040016000002 +:1004B00000000004700CE00000000008001400942C +:1004C000000000004000E0000000000402400000C6 +:1004D00000000004400EE0000000000402400000A4 +:1004E000000000004000E00000000004000C2000BC +:1004F000000000040240E51B000000050080E50A42 +:10050000000000050080E50B000000040022000050 +:1005100000000004000700C700000038000000A42D +:10052000000000050080E5BD000000050000E5BBFF +:10053000000000050080E5BC000000040021000070 +:1005400000000004028000000000001800C000ABA2 +:10055000000000404180E00000000024000000ADE9 +:100560000000000C010000000000000C0100E51D6F +:1005700000000004000045BB00000008000080A748 +:10058000000000040000F3CE000000040140A000C1 +:100590000000000400CC20000000004008C053CF41 +:1005A0000000000000008000000000040000F3D202 +:1005B000000000040140A0000000000400CC200066 +:1005C0000000004008C053D300000000000080007D +:1005D000000000040000F39D000000040140A000A2 +:1005E0000000000400CC20000000004008C0539E22 +:1005F00000000000000080000000000403C008307C +:10060000000000004200E000000000040000A00024 +:1006100000000004200045E0000000000000E5E1CB +:10062000000000000000000100000004000700C4FA +:10063000000000000800E39400000000000000003B +:10064000000000040000E8C4000000040000E8C549 +:10065000000000040000E8C6000000040000E928D3 +:10066000000000040000E929000000040000E92A5D +:1006700000000008000000C8000000040000E92895 +:10068000000000040000E929000000040000E92A3D +:1006900000000008000000CF00000000DEADBEEF4B +:1006A000000000000000011600000004000700D355 +:1006B00000000004080050E700000004000700D418 +:1006C000000000040800401C000000000000E01DC5 +:1006D0000000000402C0200000000004000600002A +:1006E00000000034000000DE00000008000000DB15 +:1006F000000000040000800000000000C000E000D6 +:10070000000000040000E1CC000000040500E1CD81 +:1007100000000004000CA00000000034000000E510 +:1007200000000008000000E1000000000000A00040 +:10073000000000040019E1CC00000004001B0001CF +:10074000000000040500A00000000004080041CDE6 +:1007500000000004000CA00000000034000000FBBA +:10076000000000080000004A000000000000000037 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B00000000004000C200000000004001D0018D0 +:1007C00000000004001A000100000034000000FBDB +:1007D000000000080000004A000000080500A04AD0 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/R600_me.bin.ihex b/firmware/radeon/R600_me.bin.ihex new file mode 100644 index 0000000..30d4c14 --- /dev/null +++ b/firmware/radeon/R600_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A0000060441100000614000000000060000021 +:1000B000000005B20000000000600000000005C55F +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E0000000000000000020002036250000000075 +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000003100204A2D82 +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000002100203625C1 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001D00200E2D54 +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001D12 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000300020362407 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:1003800000000000000000100020362300000000E4 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E230000000000000011C7 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000003000204A2D0000000046 +:1003F0000000000000204811000000000000003252 +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A0000000000000204804000000000000002DB2 +:1005B0000020162D0000000000000000002F00A306 +:1005C00000000000000000000CC0000000000080DF +:1005D0000000002E0020162D00000000000000008A +:1005E000002F00A400000000000000000CC000006C +:1005F00000000081000000000040000000000087B3 +:100600000000002D00203623000000000000002E16 +:1006100000203624000000000000001D00201E2DD8 +:10062000000000000000000200210227000000007E +:100630000000000014E0000000000087000000003F +:1006400000600000000005ED0000000000600000F8 +:10065000000005E10000000200210E220000000061 +:100660000000000014C000000000008A0000001814 +:10067000C040362000000090000000002EE0000086 +:100680000000008E000000002CE000000000008D43 +:100690000000000200400E2D0000008F000000034B +:1006A00000400E2D0000008F0000000C00200E2DD9 +:1006B00000000000000000180020362300000000A9 +:1006C0000000000300210E220000000000000000D6 +:1006D00014C00000000000950000A00C0020441190 +:1006E0000000000000000000C020480000000000E2 +:1006F00000000000C04048000000009D0000A00C69 +:1007000000204411000000000000000000204811FB +:1007100000000000000000002EE000000000009B30 +:10072000000000002CE000000000009A0000000221 +:1007300000400E2D0000009C0000000300400E2D24 +:100740000000009C0000000C00200E2D00000000A6 +:10075000000000000020480300000000000000002E +:10076000003A0C0200000000003F000000280E23A9 +:10077000000000000000001000210E230000000017 +:100780000000001300203623000000000000001EBF +:100790000021022B000000000000000014C0000037 +:1007A000000000A40000001CC02036200000000053 +:1007B0000000001F0021022B0000000000000000CC +:1007C00014C00000000000A70000001BC02036205D +:1007D000000000000000000800210E2B00000000B7 +:1007E0000000007F00280E23000000000000000031 +:1007F000002F022300000000000000000CE00000B9 +:10080000000000DB000000002700000000000000E6 +:1008100000000000006000000000028C8100000069 +:1008200000204411000000000000000600204811D4 +:10083000000000000000000C00221E30000000003C +:100840009980000000204411000000000000000416 +:100850000020122D000000000000000800221224D9 +:10086000000000000000001000201811000000002F +:100870000000000000291CE400000000000000004F +:1008800000604807000001289B0000000020441180 +:1008900000000000000000000020480200000000EE +:1008A0009C00000000204411000000000000000037 +:1008B0000033146F000000000000000100333E23ED +:1008C0000000000000000000D90048000000000007 +:1008D0000000000000203C05000000008100000036 +:1008E00000204411000000000000000E002048110C +:1008F00000000000000000000020101000000000B8 +:100900000000E00700204411000000000000000F7C +:100910000021022B000000000000000014C00000B5 +:10092000000000C500F8FF0800204811000000008A +:100930009800000000404811000000D6000000F0C0 +:1009400000280E2200000000000000A0002F02235B +:1009500000000000000000000CC00000000000D4F7 +:100960000000001300200E2D000000000000000118 +:10097000002F022300000000000000000CE0000037 +:10098000000000CF00000002002F02230000000042 +:10099000000000000CE00000000000CE00003F005E +:1009A00000400C11000000D000001F0000400C119E +:1009B000000000D000000F0000200C11000000001B +:1009C0000038000900294A23000000003F00000011 +:1009D00000280E2B000000000000000200220E2361 +:1009E000000000000000000700494A23000000D674 +:1009F00000380F09002048110000000068000007BF +:100A000000204811000000000000000800214A27D3 +:100A1000000000000000000000204811000000005D +:100A2000060A020000294A2400000000000000001D +:100A300000204811000000000000000000204811C4 +:100A4000000000000000A20200204411000000008D +:100A500000FF000000284A220000000000000030D3 +:100A600000200E2D000000000000002E0020122D9E +:100A70000000000000000000002F008300000000C4 +:100A8000000000000CE00000000000E30000000097 +:100A900000600000000005E70000000000400000CA +:100AA000000000E40000000000600000000005EA13 +:100AB000000000070020222D0000000000000005BB +:100AC00000220E22000000000010000000280E236B +:100AD0000000000000000000002920680000000065 +:100AE00000000000003A0C0200000000000000EFCF +:100AF00000280E23000000000000000000292068EC +:100B0000000000000000001D00200E2D000000006D +:100B1000000000030021022300000000000000008C +:100B200014E00000000000F10000000B002102288A +:100B3000000000000000000014C00000000000F1F0 +:100B40000000040000292228000000000000001A14 +:100B500000203628000000000000001C00210E22AA +:100B6000000000000000000014C00000000000F6BB +:100B70000000A30C00204411000000000000000051 +:100B800000204811000000000000001E00210E227D +:100B9000000000000000000014C00000000001047C +:100BA0000000A30F0020441100000000000000130B +:100BB00000200E2D0000000000000001002F022385 +:100BC00000000000000000000CC00000000000FD5C +:100BD000FFFFFFFF00404811000001040000000279 +:100BE000002F022300000000000000000CC00000E5 +:100BF000000001000000FFFF004048110000010458 +:100C000000000004002F022300000000000000008C +:100C10000CC0000000000103000000FF004048116C +:100C20000000010400000001002048110000000045 +:100C30000002C40000204411000000000000001F5A +:100C400000210E22000000000000000014C000007F +:100C50000000010B0000001040210E2000000000E9 +:100C600000000019002036230000000000000018DA +:100C700040224A200000000000000010C0424A202C +:100C80000000010D0000000000200C110000000019 +:100C900000000019002036230000000000000000C2 +:100CA0000020481100000000000000000020481152 +:100CB000000000000000000A0020101100000000E9 +:100CC00000000000002F02240000000000000000CF +:100CD0000CE000000000011400000000002048119A +:100CE0000000000000000001005312240000011069 +:100CF000FFBFFFFF00283A2E000000000000001B8D +:100D000000210222000000000000000014C00000CA +:100D100000000127810000000020441100000000B5 +:100D20000000000D00204811000000000000001825 +:100D300000220E3000000000FC00000000280E23FE +:100D400000000000810000000020441100000000AD +:100D50000000000E0020481100000000000000000C +:100D600000201010000000000000E00E00204411E0 +:100D70000000000007F8FF080020481100000000F4 +:100D80000000000000294A230000000000000024A9 +:100D900000201E2D000000000000000800214A274E +:100DA00000000000000000000020481100000000CA +:100DB000060A020000294A2400000000000000008A +:100DC0000020481100000000000000000020481131 +:100DD0000000000000000000008000000000000093 +:100DE000810000000020441100000000000000010C +:100DF00000204811000000000000217C0020441168 +:100E000000000000008000000020481100000000E9 +:100E1000000000000020480600000000000000085C +:100E200000214A2700000000000000001700000019 +:100E3000000000000004217F00604411000006143F +:100E40000000001F00210230000000000000000030 +:100E500014C00000000006130000000400404C1104 +:100E60000000012E00000000006000000000000BE8 +:100E70000000000000600411000002FE00000000FD +:100E800000200411000000000000000000600811B4 +:100E90000000019F00000000006000000000015100 +:100EA0000000FFFF40280E2000000000000000109E +:100EB000C0211220000000000000FFFF4028062093 +:100EC0000000000000000010C0210A200000000007 +:100ED0000000000000341461000000000000000069 +:100EE00000741882000002A40001A1FD00604411FA +:100EF000000002C900003FFF002F022F0000000089 +:100F0000000000000CC000000000013800000000DC +:100F1000C04004000000000100000000006000006C +:100F20000000000B0000000000600411000002FE41 +:100F3000000000000020041100000000000000007C +:100F4000006008110000019F00003FFF002F022FEA +:100F500000000000000000000CE0000000000000A5 +:100F600000000000006000000000015100000010BF +:100F700040210E20000000000000FFFFC0281220CA +:100F800000000000000000104021162000000000BA +:100F90000000FFFFC0681A20000002A40001A1FDAC +:100FA00000604411000002C900003FFF002F022F23 +:100FB00000000000000000000CC00000000001491B +:100FC00000000000C0400400000000010000225C9E +:100FD00000204411000000000000000100300A2F32 +:100FE000000000000000000100210A2200000000B3 +:100FF0000000000300384A220000000000002256D2 +:1010000000204411000000000000001A00204811D8 +:10101000000000000000A1FC0020441100000000BE +:1010200000000001008048110000000000000000E6 +:10103000006000000000000B0000000000600000E5 +:101040000000017C00000000006000000000018D35 +:1010500000003FFF002F022F0000000000000000F2 +:101060000CE00000000000000000000000202C0840 +:10107000000000000000000000202411000000001B +:10108000000000000020281100000000000022568F +:10109000002044110000000000000016002048114C +:1010A000000000000000225C00204411000000004D +:1010B00000000003002048110000000093800000A1 +:1010C00000204411000000000000000200221E2940 +:1010D0000000000000000000007048EB00000189E3 +:1010E0000000000000600000000002A400000001F9 +:1010F000403306200000000000000000C03024093A +:101100000000000000003FFF002F022F0000000041 +:10111000000000000CE000000000000000000000E3 +:10112000006000000000028C9500000000204411C7 +:101130000000000000000000002F0221000000005D +:10114000000000000CE0000000000173000000003F +:10115000C0204800000000000000000100530621EC +:101160000000016F92000000002044110000000008 +:1011700000000000C0604800000001840001A1FDE3 +:101180000020441100000000000000130020062D84 +:1011900000000000000000000078042A000002E4C3 +:1011A00000000000002028090000000000003FFFB0 +:1011B000002F022F00000000000000000CC0000003 +:1011C0000000016500000000C040040000000001B4 +:1011D0000000021000600411000002FE00003FFF4A +:1011E000002F022F00000000000000000CE00000B3 +:1011F000000001810000001BC0203620000000001C +:101200000000001CC0203620000000003F800000CD +:1012100000200411000000004600000000600811DA +:101220000000019F0000000000800000000000009E +:101230000000A1FC002044110000000000003FFF5E +:10124000002F022F00000000000000000CC0000072 +:10125000000001880000000100804811000000002B +:101260000000002100804811000000000000FFFF86 +:1012700040280E200000000000000010C0211220B5 +:10128000000000000000FFFF4028162000000000C2 +:1012900000000010C0811A20000000008100000042 +:1012A000002044110000000000000006002048114A +:1012B000000000000000000800221E3000000000B6 +:1012C0000000003200201A2D000000000000E000A5 +:1012D0000020441100000000FFFBFF09002048111E +:1012E00000000000000000110020222D000000007E +:1012F00000001FFF00294A2800000000000000062F +:101300000020222D0000000000000000002920E83D +:10131000000000000000000000204808000000005D +:10132000000000000020481100000000060A020032 +:1013300000294A260000000000000000002048119B +:101340000000000000000000002048110000000024 +:10135000000001000020181100000000000000083B +:1013600000621E28000001280000000800822228D8 +:10137000000000000002C000002044110000000036 +:101380000000001B00600E2D000001AA0000001CE0 +:1013900000600E2D000001AA0000C00800204411CA +:1013A000000000000000001D00200E2D00000000C5 +:1013B0000000000014C00000000001A600000000B2 +:1013C000002004110000000000000000002048017F +:1013D000000000003900000000204811000000005B +:1013E0000000000000204811000000000000000084 +:1013F00000804802000000000000002000202E2D88 +:101400000000000000000000003B0D630000000031 +:101410000000000800224A23000000000000001025 +:1014200000224A23000000000000001800224A2386 +:1014300000000000000000000080480300000000E1 +:1014400000000000006000000000000B0000100021 +:1014500000600411000002FE0000000000200411E2 +:101460000000000000000000006008110000019F63 +:10147000000000070021062F0000000000000019F6 +:1014800000200A2D000000000000000100202C11A7 +:10149000000000000000FFFF4028222000000000A4 +:1014A0000000000F002622280000000000000010AD +:1014B00040212620000000000000000F0026262901 +:1014C00000000000000000000020280200000000D2 +:1014D0000000225600204411000000000000001B04 +:1014E000002048110000000000000000002F022131 +:1014F00000000000000000000CE00000000001CD32 +:101500000000225C00204411000000000000008167 +:1015100000204811000000000000A1FC0020441140 +:101520000000000000000001002048110000000041 +:101530000000008000201C110000000000000000DE +:10154000002F022700000000000000000CE0000057 +:10155000000001C90000000000600000000001D68A +:101560000000000100531E27000001C5000000011B +:1015700000202C11000000000000001F00280A229B +:10158000000000000000001F00282A2A00000000C0 +:101590000000000100530621000001BE0000225C93 +:1015A00000204411000000000000000200304A2F1B +:1015B000000000000000A1FC002044110000000019 +:1015C00000000001002048110000000000000001A0 +:1015D00000301E2F0000000000000000002F022736 +:1015E00000000000000000000CE00000000000000F +:1015F0000000000000600000000001D600000001B3 +:1016000000531E27000001D20000FFFF40280E20DB +:10161000000000000000000F00260E230000000064 +:1016200000000010C0211220000000000000000F88 +:101630000026122400000000000000000020141109 +:10164000000000000000000000601811000002A46B +:101650000001A1FD00204411000000000000000076 +:10166000002F022B00000000000000000CE0000032 +:10167000000001E500000010002216280000000014 +:10168000FFFF000000281625000000000000FFFFFB +:1016900000281A290000000000000000002948C5A9 +:1016A00000000000000000000020480A00000000C8 +:1016B0000000000000202C110000000000000010BD +:1016C0000022162300000000FFFF0000002816255E +:1016D000000000000000FFFF00281A2400000000A6 +:1016E00000000000002948C50000000000000000C4 +:1016F00000731503000001F200000000002018052F +:10170000000000000000000000731524000001F23A +:1017100000000000002D14C50000000000000000C3 +:10172000003008A200000000000000000020480275 +:10173000000000000000000000202802000000005F +:101740000000000000202003000000000000000056 +:1017500000802404000000000000000F002102258A +:10176000000000000000000014C00000000006138C +:1017700000000000002B1405000000000000000124 +:10178000009016250000000000000000006000002E +:101790000000000B0000000000600411000002FEC9 +:1017A0000000000000200411000000000000000004 +:1017B000006008110000019F000022560020441123 +:1017C000000000000000001A00294A22000000006A +:1017D00000000000C02000000000000000003FFFEB +:1017E000002F022F00000000000000000CE00000AD +:1017F0000000000000000000C02004000000000005 +:101800000000225C002044110000000000000003E2 +:1018100000384A21000000000000A1FC0020441113 +:10182000000000000000000100204811000000003E +:101830000000FFFF40281220000000000000001000 +:10184000C0211A20000000000000FFFF40280E20E9 +:101850000000000000000010C02116200000000061 +:101860000000000000741465000002A40001A1FD46 +:1018700000604411000002C900000001003306218D +:101880000000000000000000002F02210000000006 +:10189000000000000CC000000000020600003FFF36 +:1018A000002F022F00000000000000000CC000000C +:1018B000000001FF00000000C04004000000000123 +:1018C0000000000000600000000005C500000000EE +:1018D0000040040F00000200000000000060000053 +:1018E000000005B20000000000600000000005C517 +:1018F0000000021000600411000002FE0000000061 +:10190000006000000000018D000000000060000089 +:10191000000001890000000000600000000002A437 +:1019200000000000006000000000028C93800000B6 +:1019300000204411000000000000000000204808C2 +:10194000000000009500000000204411000000008D +:1019500000000000002F022F000000000000000027 +:101960000CE000000000021F00000000C040480022 +:101970000000021C92000000002044110000000042 +:1019800000000000C02048000000000000002256B7 +:101990000020441100000000000000160020481143 +:1019A000000000000000225C002044110000000044 +:1019B0000000000300204811000000000000A1FC0E +:1019C0000020441100000000000000010020481128 +:1019D000000000000001A1FD0020441100000000F3 +:1019E0000000000000600411000002E4000000009C +:1019F000C040040000000001000000000060000082 +:101A0000000005B20000A00C0020441100000000FE +:101A100000000000C020480000000000000000009E +:101A2000C04048000000000000000000006000000E +:101A30000000000B0000001840210A2000000000F8 +:101A400000000003002F0222000000000000000040 +:101A50000AE00000000002350000001A0020222DDC +:101A600000000000000801010029222800000000F9 +:101A70000000001A00203628000000000000A30C1F +:101A8000002044110000000000000000C0204800B9 +:101A90000000000000000000C0204800000000001E +:101AA00000000000C04048000000023A00000000B2 +:101AB000006000000000000B000000100060041136 +:101AC000000002FE3F800000002004110000000022 +:101AD00000000000006008110000019F0000225C6F +:101AE0000020441100000000000000030020481105 +:101AF000000000000000000000600000000002651F +:101B00000000001D00201E2D00000000000000014C +:101B100000211E27000000000000000014E000006B +:101B2000000002530000001800201E2D00000000DD +:101B30000000FFFF00281E2700000000000000003A +:101B400000341C27000000000000000012C000004C +:101B5000000002480000000000201C1100000000EE +:101B600000000000002F00E5000000000000000061 +:101B700008C000000000024B000000000020140715 +:101B8000000000000000001800201E2D00000000D2 +:101B90000000001000211E270000000000000000CF +:101BA00000341C47000000000000000012C00000CC +:101BB000000002500000000000201C110000000086 +:101BC00000000000002F00E6000000000000000000 +:101BD00008C00000000002530000000000201807A9 +:101BE000000000000000000000600000000002AAE9 +:101BF00000002256002044110000000000000000F8 +:101C000000342023000000000000000012C000008B +:101C10000000025B000000000034204400000000CF +:101C20000000000012C000000000025A0000001670 +:101C3000004048110000025F0000001800404811F9 +:101C40000000025F0000000000342044000000009B +:101C50000000000012C000000000025E000000173B +:101C6000004048110000025F0000001900204811E8 +:101C7000000000000000A1FC002044110000000052 +:101C80000000000100204811000000000001A1FD3B +:101C900000604411000002D200003FFF002F022F1D +:101CA00000000000000000000CC000000000023F27 +:101CB00000000000C040040000000001000000100F +:101CC00040210620000000000000FFFFC0280A207D +:101CD000000000000000001040210E200000000065 +:101CE0000000FFFFC02812200000000000000010CC +:101CF00040211620000000000000FFFFC0881A20CD +:101D000000000000810000000020441100000000DD +:101D10000000000100204811000000000004200421 +:101D20000060441100000614000000000060000084 +:101D3000000005B200000000C06000000000028C3E +:101D40000000000500200A2D00000000000000082F +:101D500000220A22000000000000003400201A2D9A +:101D6000000000000000002400201E2D00000000E4 +:101D70000000700000281E27000000000000000086 +:101D800000311CE6000000000000003300201A2D86 +:101D9000000000000000000C00221A2600000000D5 +:101DA00000000000002F00E600000000000000001E +:101DB00006E000000000027B0000000000201C1173 +:101DC000000000000000000000200C1100000000D6 +:101DD0000000003400203623000000000000001046 +:101DE00000201811000000000000000000691CE243 +:101DF0000000012893800000002044110000000032 +:101E000000000000002048070000000095000000CE +:101E1000002044110000000000000000002F022FED +:101E200000000000000000000CE00000000002863E +:101E30000000000100333E2F000000000000000001 +:101E4000D90048000000000092000000002044116A +:101E50000000000000000000C0204800000000005A +:101E60000000002400403627000000000000000CA5 +:101E7000C0220A20000000000000003200203622AC +:101E80000000000000000031C040362000000000CB +:101E90000000A2A40020441100000000000000097E +:101EA0000020481100000000A100000000204411A3 +:101EB0000000000000000001008048110000000048 +:101EC0000000002900201E2D00000000000000007E +:101ED000002C1CE300000000000000290020362731 +:101EE000000000000000002A00201E2D000000005D +:101EF00000000000002C1CE4000000000000002A8C +:101F000000203627000000000000002B00201E2DBE +:101F10000000000000000000003120A300000000CD +:101F200000000000002D1D07000000000000002B35 +:101F300000203627000000000000002C00201E2D8D +:101F40000000000000000000003120C4000000007C +:101F500000000000002D1D07000000000000002C04 +:101F600000803627000000000000002900203623F2 +:101F7000000000000000002A0020362400000000BD +:101F80000000000000311CA3000000000000002B36 +:101F900000203627000000000000000000311CC4B3 +:101FA000000000000000002C008036270000000028 +:101FB000000000220020362700000000000000235F +:101FC00000203628000000000000001D00201E2D0B +:101FD00000000000000000020021022700000000B5 +:101FE0000000000014C00000000002C50000000056 +:101FF00000400000000002C200000022002036273E +:10200000000000000000002300203628000000002F +:102010000000001D00201E2D000000000000000236 +:1020200000210227000000000000000014E0000072 +:10203000000002C20000000300210227000000008F +:102040000000000014E00000000002C50000002BAA +:1020500000201E2D0000000000000000002E00E106 +:10206000000000000000000002C00000000002C5E7 +:102070000000002900201E2D0000000000000000CC +:10208000003120A10000000000000000002E00E848 +:10209000000000000000000006C00000000002C5B3 +:1020A0000000002C00201E2D000000000000000099 +:1020B000002E00E2000000000000000002C000004E +:1020C000000002C50000002A00201E2D00000000B4 +:1020D00000000000003120C20000000000000000ED +:1020E000002E00E8000000000000000006C0000014 +:1020F000000002C50000000000600000000005EDC7 +:1021000000000000006000000000029E00000000CF +:1021100000400000000002C7000000000060000056 +:102120000000029E0000000000600000000005E4C6 +:102130000000000000400000000002C70000000096 +:10214000006000000000029000000000004000005D +:10215000000002C70000002200201E2D0000000029 +:10216000000000230080222D00000000000000106D +:1021700000221E2300000000000000000029488704 +:10218000000000000000000000311CA3000000005F +:102190000000001000221E270000000000000000C8 +:1021A00000294887000000000000001000221E23C4 +:1021B0000000000000000000003120C4000000000A +:1021C0000000FFFF0028222800000000000000009F +:1021D00000894907000000000000001000221E23B3 +:1021E00000000000000000000029488700000000F7 +:1021F0000000001000221E2100000000000000006E +:1022000000294847000000000000000000311CA326 +:10221000000000000000001000221E270000000047 +:1022200000000000002948870000000000000000B6 +:1022300000311CA1000000000000001000221E2739 +:1022400000000000000000000029484700000000D6 +:102250000000001000221E2300000000000000000B +:10226000003120C4000000000000FFFF00282228E9 +:1022700000000000000000000029490700000000E5 +:102280000000001000221E210000000000000000DD +:10229000003120C2000000000000FFFF00282228BB +:1022A0000000000000000000008949070000000055 +:1022B0000000001000221E230000000000000000AB +:1022C00000294887000000000000000100220A21C8 +:1022D0000000000000000000003308A20000000021 +:1022E0000000001000221E2200000000000000106C +:1022F0000021222200000000000000000029490700 +:10230000000000000000000000311CA300000000DD +:102310000000001000221E27000000000000000046 +:1023200000294887000000000000000100220A2167 +:102330000000000000000000003008A200000000C3 +:102340000000001000221E2200000000000000100B +:10235000002122220000000000000000002949079F +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:102390000000000000000000003808C50000000038 +:1023A00000000000003008410000000000000001B3 +:1023B00000220A220000000000000000003308A2F2 +:1023C000000000000000001000221E22000000009B +:1023D0000000001000212222000000000000000088 +:1023E00000894907000000000000001D0020222D88 +:1023F000000000000000000014C000000000030105 +:10240000FFFFFFEF00280621000000000000001A77 +:102410000020222D000000000000F8E00020441100 +:102420000000000000000000002949010000000039 +:1024300000000000008949010000000000000000C9 +:10244000002048110000000000000000002048119A +:1024500000000000060A0200008048110000000091 +:1024600000000000C02000000000000097000000F5 +:10247000C02044110000000000000000C0204811EE +:10248000000000008A00000000204411000000004D +:102490000000000000204811000000000000225C45 +:1024A000002044110000000000000000C02048008F +:1024B000000000000000A1FC00204411000000000A +:1024C00000000000C02048000000000000000000E4 +:1024D000C0200400000000000000000000A0000A6E +:1024E00000000000970000000020441100000000E0 +:1024F0000000000000204811000000008A000000D9 +:1025000000204411000000000000000000204811DD +:10251000000000000000225C0020441100000000C8 +:1025200000000000C0204800000000000000A1FCE6 +:10253000002044110000000000000000C0204800FE +:102540000000000000000000C020040000000000A7 +:102550000000000000A0000A00000000970000003A +:10256000002044110000000000000000002048117D +:10257000000000008A00000000204411000000005C +:102580000000000000204811000000000000225C54 +:10259000002044110000000000000000C02048009E +:1025A000000000000000A1FC002044110000000019 +:1025B00000000000C0204800000000000001A1FD54 +:1025C000002044110000000000000000D900480075 +:1025D0000000000000000000C02004000000000017 +:1025E0000000000000A0000A0000000000002257C8 +:1025F000002044110000000000000003C0484A20F1 +:10260000000000000000225D0020441100000000D6 +:1026100000000000C0404800000000000000000072 +:1026200000600000000005C500000000C020080098 +:10263000000000000000225C0020441100000000A7 +:102640000000000300384A22000000000000A1FC46 +:10265000002044110000000000000000C0204800DD +:10266000000000000001A1FD002044110000000056 +:1026700000000000002F0222000000000000000007 +:102680000CE00000000000000000000040204800B6 +:10269000000000000000000140304A20000000005F +:1026A00000000002C0304A200000000000000001CD +:1026B00000530A22000003340000003FC0280A2013 +:1026C0000000000081000000002044110000000014 +:1026D000000000010020481100000000000021F867 +:1026E00000204411000000000000001700204811E5 +:1026F00000000000000421F90060441100000614ED +:102700000000001100210230000000000000000065 +:1027100014E000000000033D00000014002F02221E +:1027200000000000000000000CC000000000035189 +:102730000000201000204411000000000000800074 +:1027400000204811000000000001A2A40020441154 +:102750000000000000000000002048110000000000 +:1027600000000016006048110000035E0000210018 +:10277000002044110000000000000000C0204800BC +:102780000000000000000000C02048000000000021 +:1027900000000000C0204800000000000000000011 +:1027A000C0204800000000000001A2A40020441145 +:1027B00000000000000000000020481100000000A0 +:1027C000000000000040480200000000000000047B +:1027D000002F022200000000000000000CC00000DA +:1027E00000000355000020100020441100000000EC +:1027F000000080000040481100000349000000284C +:10280000002F022200000000000000000CE0000089 +:1028100000000349000021040020441100000000D2 +:1028200000000000C0204800000000000000000080 +:10283000C02048000000000000000000C020480048 +:102840000000000000000000C02048000000000060 +:102850000000A2A4002044110000000000000000BD +:10286000004048020000000000000035002036262D +:1028700000000000000000490020181100000000C6 +:1028800000000000002048110000000000000001CE +:1028900000331A260000000000000000002F02266E +:1028A00000000000000000000CC0000000000360F9 +:1028B0000000003500801A2D000000000000003FDD +:1028C000C0280A200000000000000015002F02228E +:1028D00000000000000000000CE000000000037693 +:1028E0000000001E002F0222000000000000000077 +:1028F0000CE000000000038000000020002F0222F6 +:1029000000000000000000000CE000000000038C4C +:102910000000000F002F0222000000000000000055 +:102920000CE000000000039800000010002F0222BD +:1029300000000000000000000CE000000000039810 +:1029400000000006002F022200000000000000002E +:102950000CE000000000039A00000016002F022285 +:1029600000000000000000000CE000000000039FD9 +:102970000000A2A40020441100000000000000009C +:1029800000404802000000000800000000290A2260 +:10299000000000000000000340210E2000000000A5 +:1029A0000000000CC0211220000000000008000000 +:1029B000002812240000000000000014C02216208D +:1029C0000000000000000000002914A40000000026 +:1029D0000000A2A40020441100000000000000003C +:1029E000002948A2000000000000A1FE00204411C0 +:1029F000000000000000000000404803000000004C +:102A000081000000002044110000000000000001CF +:102A10000020481100000000000021F800204411AF +:102A20000000000000000015002048110000000018 +:102A3000000421F900604411000006140000001594 +:102A400000210230000000000000000014E000003F +:102A5000000003820000210E00204411000000004D +:102A600000000000C020480000000000000000003E +:102A7000C0204800000000000000A2A40020441173 +:102A800000000000000000000040480200000000BC +:102A9000810000000020441100000000000000013F +:102AA0000020481100000000000021F8002044111F +:102AB0000000000000000016002048110000000087 +:102AC000000421F900604411000006140000000316 +:102AD00000210230000000000000000014E00000AF +:102AE0000000038E000021080020441100000000B7 +:102AF00000000000C02048000000000000000000AE +:102B0000C0204800000000000000A2A400204411E2 +:102B1000000000000000000000404802000000002B +:102B20000000201000204411000000000000800080 +:102B30000040481100000000000020100020441157 +:102B4000000000000000800000204811000000008C +:102B50000001A2A4002044110000000000000000B9 +:102B6000002048110000000000000006004048114D +:102B700000000000000020100020441100000000B0 +:102B80000000800000204811000000000001A2A405 +:102B90000020441100000000000000000020481147 +:102BA0000000000000000016006048110000035EF5 +:102BB0000000001600404811000000000000000066 +:102BC000C02008000000000000000000C0200C0031 +:102BD000000000000000001D002102230000000092 +:102BE0000000000014E00000000003B981000000B4 +:102BF00000204411000000000000000100204811E6 +:102C000000000000000021F8002044110000000036 +:102C1000000000170020481100000000000421F906 +:102C20000060441100000614000000110021023071 +:102C3000000000000000000014E00000000003ABF2 +:102C400000002100002044110000000000000000EE +:102C5000002048020000000000000000002048039F +:102C600000000000BABECAFE0020481100000000AB +:102C7000CAFEBABE0020481100000000000020106B +:102C800000204411000000000000800000204811D6 +:102C9000000000000000A2A4002044110000000079 +:102CA00000000004004048110000000000002170F6 +:102CB0000020441100000000000000000020480235 +:102CC0000000000000000000002048030000000099 +:102CD0008100000000204411000000000000000AF4 +:102CE000002048110000000000000000002000103B +:102CF000000000000000000014C00000000003BE3F +:102D00008C0000000020441100000000CAFEBABE82 +:102D10000040481100000000810000000020441124 +:102D20000000000000000001002048110000000029 +:102D300000003FFF40280A20000000008000000043 +:102D400040280E200000000040000000C028122093 +:102D50000000000000040000006946220000061484 +:102D6000000000000020141000000000000000001F +:102D7000002F022300000000000000000CC0000033 +:102D8000000003CC00000000C0401800000003CF8A +:102D900000003FFFC0281A200000000000040000CF +:102DA00000694626000006140000000000201810EC +:102DB0000000000000000000002F022400000000BE +:102DC000000000000CC00000000003D20000000062 +:102DD000C0401C00000003D500003FFFC0281E209B +:102DE00000000000000400000069462700000614EF +:102DF0000000000000201C10000000000000000087 +:102E0000002044020000000000000000002820C54F +:102E10000000000000000000004948E80000000039 +:102E2000A580000000200811000000000000200024 +:102E300000200C110000000083000000006044111D +:102E4000000003FD0000000000204402000000001C +:102E500000000000C020480000000000000000004A +:102E600040204800000000000000001FC021022098 +:102E7000000000000000000014C00000000003E299 +:102E8000000020100020441100000000000080001D +:102E900000204811000000000000FFFFC048122081 +:102EA000000003EAA78000000020081100000000D5 +:102EB0000000A00000200C110000000083000000B2 +:102EC00000604411000003FD0000000000204402E7 +:102ED0000000000000000000C020480000000000CA +:102EE00000000000C0204800000000000000FFFFBC +:102EF000C0281220000000008300000000204411C0 +:102F000000000000000000000030488300000000C6 +:102F100084000000002044110000000000000000B8 +:102F2000C020480000000000000000001D0000005C +:102F3000000000008300000000604411000003FD59 +:102F400000000000C040040000000001A980000053 +:102F500000200811000000000000C00000400C111B +:102F6000000003E5AB800000002008110000000015 +:102F70000000F8E000400C11000003E5AD80000007 +:102F800000200811000000000000F88000400C1133 +:102F9000000003E5B38000000020081100000000DD +:102FA0000000F3FC00400C11000003E5AF800000BE +:102FB00000200811000000000000E00000400C119B +:102FC000000003E5B18000000020081100000000AF +:102FD0000000F00000400C11000003E58300000039 +:102FE000002044110000000000002148002048118A +:102FF00000000000840000000020441100000000D8 +:1030000000000000C0204800000000000000000098 +:103010001D00000000000000000000000080000013 +:103020000000000000182000C03046200000000012 +:1030300000000000D900480000000000000000006F +:10304000C0200400000000000000000000A0000AF2 +:10305000000000000018A000C03046200000000062 +:1030600000000000D900480000000000000000003F +:10307000C0200400000000000000000000A0000AC2 +:10308000000000000018C000C03046200000000012 +:1030900000000000D900480000000000000000000F +:1030A000C0200400000000000000000000A0000A92 +:1030B000000000000018F8E0C030462000000000CA +:1030C00000000000D90048000000000000000000DF +:1030D000C0200400000000000000000000A0000A62 +:1030E000000000000018F880C030462000000000FA +:1030F00000000000D90048000000000000000000AF +:10310000C0200400000000000000000000A0000A31 +:10311000000000000018E000C03046200000000061 +:1031200000000000D900480000000000000000007E +:10313000C0200400000000000000000000A0000A01 +:10314000000000000018F000C03046200000000021 +:1031500000000000D900480000000000000000004E +:10316000C0200400000000000000000000A0000AD1 +:10317000000000000018F3FCC030462000000000F2 +:1031800000000000D900480000000000000000001E +:10319000C0200400000000000000000000A0000AA1 +:1031A0000000000086000000002044110000000024 +:1031B0000000000000404801000000008500000001 +:1031C0000020441100000000000000000040480101 +:1031D000000000000000217C0020441100000000DD +:1031E00000000000C02048000000000000000000B7 +:1031F000C02048000000000000000000C02048007F +:1032000000000000810000000020441100000000C8 +:103210000000000100204811000000000000000034 +:10322000C02008000000000000000000170000009F +:10323000000000000004217F00604411000006141B +:103240000000001F0021023000000000000000000C +:1032500014C00000000000000000000000404C020C +:103260000000042E00000000C0200C000000000040 +:1032700000000000C020100000000000000000005E +:10328000C02014000000000000000000C020180052 +:103290000000000000000000C0201C000000000032 +:1032A00000007F0000280A21000000000000450007 +:1032B000002F022200000000000000000CE00000CF +:1032C0000000043C00000000C020200000000000BE +:1032D00000000000170000000000000000000010C7 +:1032E00000280A230000000000000010002F022226 +:1032F00000000000000000000CE00000000004449A +:1033000081000000002044110000000000000001C6 +:10331000002048110000000000040000006946245D +:103320000000061400000000004000000000044DF2 +:103330008100000000204411000000000000000097 +:1033400000204811000000000000216D0020441101 +:103350000000000000000000002048040000000001 +:1033600000000000002048050000000000000000F0 +:103370001AC00000000004499E0000000020441113 +:1033800000000000CAFEBABE002048110000000084 +:10339000000000001AE000000000044C00000000E3 +:1033A000002824F0000000000000000700280A2385 +:1033B0000000000000000001002F022200000000B9 +:1033C000000000000AE000000000045400000000BB +:1033D000002F00C9000000000000000004E0000011 +:1033E0000000046D00000000004000000000047AAE +:1033F00000000002002F0222000000000000000078 +:103400000AE000000000045900000000002F00C97D +:10341000000000000000000002E000000000046D59 +:1034200000000000004000000000047A00000003DB +:10343000002F022200000000000000000AE000004F +:103440000000045E00000000002F00C90000000022 +:10345000000000000CE000000000046D000000000F +:10346000004000000000047A00000004002F022247 +:1034700000000000000000000AE0000000000463FB +:1034800000000000002F00C9000000000000000044 +:103490000AE000000000046D000000000040000091 +:1034A0000000047A00000005002F02220000000046 +:1034B000000000000AE000000000046800000000B6 +:1034C000002F00C9000000000000000006E000001E +:1034D0000000046D00000000004000000000047ABD +:1034E00000000006002F0222000000000000000083 +:1034F0000AE000000000046D00000000002F00C979 +:10350000000000000000000008E000000000046D62 +:1035100000000000004000000000047A00007F006E +:1035200000280A210000000000004500002F0222B0 +:1035300000000000000000000AE0000000000000A1 +:103540000000000800210A23000000000000000025 +:1035500014C000000000047700002169002044111D +:103560000000000000000000C02048000000000033 +:1035700000000000C0204800000000000000000023 +:10358000C020480000000000CAFEBABE004048113A +:103590000000000000000000C02044000000000007 +:1035A00000000000C020000000000000000000003B +:1035B000C04048000000000000007F0000280A21F1 +:1035C0000000000000004500002F02220000000063 +:1035D000000000000AE0000000000480000000007D +:1035E000C02000000000000000000000C02000001B +:1035F0000000000000000000C040000000000000CB +:103600000000000000404C080000043C00000000E6 +:10361000C0200800000000000000001040210E2023 +:1036200000000000000000114021122000000000F6 +:103630000000001240211620000000000000216957 +:10364000002044110000000000000000002048029B +:103650000000000000000000002102250000000022 +:103660000000000014E000000000048A00040000D4 +:10367000C0494A200000048BFFFBFFFFC0284A20FE +:1036800000000000000000000021022300000000F4 +:103690000000000014E0000000000497000000009B +:1036A000C02048000000000000000000C0204800CA +:1036B00000000000000000000021022400000000C3 +:1036C0000000000014C000000000000081000000A5 +:1036D00000204411000000000000000C00204811F0 +:1036E00000000000000000000020001000000000AA +:1036F0000000000014C0000000000493A0000000BF +:103700000020441100000000CAFEBABE004048116B +:1037100000000000810000000020441100000000B3 +:103720000000000400204811000000000000216B90 +:10373000002044110000000000000000C0204810DC +:103740000000000081000000002044110000000083 +:103750000000000500204811000000000000216C5E +:10376000002044110000000000000000C0204810AC +:103770000000000000000000002F022400000000F4 +:10378000000000000CE0000000000000000000004D +:10379000004000000000049100000000C0210A2049 +:1037A000000000000000000014C00000000004AE93 +:1037B0008100000000204411000000000000000013 +:1037C00000204811000000000000216D002044117D +:1037D0000000000000000000C020480000000000C1 +:1037E00000000000C02048000000000000000000B1 +:1037F0001AC00000000004A99E000000002044112F +:1038000000000000CAFEBABE0020481100000000FF +:10381000000000001AE00000000004AC00000000FE +:1038200000400000000004B28100000000204411AC +:10383000000000000000000100204811000000000E +:1038400000040000C0294620000000000000000025 +:10385000C0600000000006140000000100210222E8 +:10386000000000000000000014C00000000004B9C7 +:103870000000216900204411000000000000000049 +:10388000C02048000000000000000000C0204800E8 +:1038900000000000000000000020481000000000B0 +:1038A000CAFEBABE0040481100000000000000003F +:1038B000C02044000000000000000000C04048108C +:1038C0000000000081000000002044110000000002 +:1038D000000000010020481100000000000021F855 +:1038E00000204411000000000000000D00204811DD +:1038F00000000000000421F90060441100000614DB +:103900000000000000210230000000000000000064 +:1039100014C00000000004BB0000218000204411FE +:103920000000000000000000C0204800000000006F +:1039300000000000C02000000000000000000000A7 +:10394000C02048000000000000000000C02000006F +:103950000000000000000000C0404800000000001F +:103960000000000300333E2F0000000000000001B3 +:1039700000210221000000000000000014E000000F +:10398000000004EB0000003500200A2D00000000BC +:103990000004000018E00C11000004DA000000012F +:1039A00000333E2F00000000000021690020441178 +:1039B000000000000000000000204802000000009D +:1039C0000000000000204803000000000000000884 +:1039D00000300A220000000000000000C020480063 +:1039E0000000000000000000C020480000000000AF +:1039F00000002169002044110000000000000000C8 +:103A000000204802000000000000000000204803E1 +:103A1000000000000000000800300A220000000042 +:103A200000000000C020480000000000000000006E +:103A3000D8C04800000004CE0000216900204411D5 +:103A4000000000000000000000204802000000000C +:103A500000000000002048030000000000000008F3 +:103A600000300A220000000000000000C0204800D2 +:103A70000000000000000000C0204800000000001E +:103A8000000000360020122D0000000000000000A1 +:103A900000290C830000000000002169002044116F +:103AA00000000000000000000020480200000000AC +:103AB0000000000000204803000000000000000893 +:103AC00000300A220000000000000000C020480072 +:103AD0000000000000000000C020480000000000BE +:103AE000000000110021022400000000000000007E +:103AF00014C00000000000000000000000400000B2 +:103B00000000049100000035C020362000000000B5 +:103B100000000036C0403620000000000000304A9F +:103B20000020441100000000E0000000C0484A20CE +:103B3000000000000000000F002102210000000032 +:103B40000000000014C00000000004F200000000AB +:103B5000006000000000000B00000000D900000021 +:103B60000000000000000000C04004000000000150 +:103B7000810000000020441100000000000000024D +:103B80000020481100000000000000FF00280E3057 +:103B90000000000000000000002F022300000000D1 +:103BA000000000000CC00000000004F6000000004F +:103BB000C0200800000000000000000014C0000049 +:103BC0000000050B0000000000200C1100000000A8 +:103BD0000000002400203623000000000000003414 +:103BE00000203623000000000000003200203623B1 +:103BF000000000000000003100203623000000001B +:103C00000000001D00203623000000000000002DF1 +:103C100000203623000000000000002E0020362384 +:103C2000000000000000001B002036230000000000 +:103C30000000001C0020362300000000FFFFE00011 +:103C400000200C1100000000000000290020362395 +:103C5000000000000000002A0020362300000000C1 +:103C600000001FFF00200C11000000000000002BCE +:103C700000203623000000000000002C0020362326 +:103C800000000000F1FFFFFF00283A2E00000000B6 +:103C90000000001AC0220E200000000000000000FA +:103CA0000029386E0000000081000000002044114F +:103CB0000000000000000006002048110000000085 +:103CC0000000003340203620000000008700000084 +:103CD000002044110000000000000000C020480047 +:103CE000000000000000A1F40020441100000000CA +:103CF0000000000000204810000000009D000000AF +:103D000000204411000000000000001F40214A2054 +:103D10000000000096000000002044110000000098 +:103D200000000000C020480000000000000000006B +:103D3000C0200C000000000000000000C0201000A7 +:103D4000000000000000001F0021162400000000F9 +:103D50000000000014C0000000000000000000256A +:103D600000203623000000000000000300281E236E +:103D700000000000000000080022222300000000D4 +:103D8000FFFFF000002822280000000000000000D3 +:103D9000002920E80000000000000027002036284D +:103DA000000000000000001800211E230000000099 +:103DB000000000280020362700000000000000025C +:103DC000002216240000000000000000003014A8AB +:103DD0000000000000000026002036250000000042 +:103DE0000000000300211A24000000001000000061 +:103DF00000281A2600000000EFFFFFFF00283A2EDF +:103E00000000000000000000004938CE000006025B +:103E10000000000140280A20000000000000000609 +:103E200040280E200000000000000300C0281220DF +:103E30000000000000000008002112240000000023 +:103E400000000000C020162000000000000000005C +:103E5000C0201A2000000000000000000021022203 +:103E6000000000000000000014C000000000054138 +:103E7000810000000020441100000000000000014B +:103E800000204811000000000000225800300A24E1 +:103E90000000000000040000006946220000061433 +:103EA0000000216900204411000000000000000013 +:103EB00000204805000000000002000000294A26FA +:103EC000000000000000000000204810000000007A +:103ED000CAFEBABE00204811000000000000000227 +:103EE000002F022300000000000000000CC00000B2 +:103EF0000000054900000000C0201C100000000068 +:103F000000000000C04000000000055B000000024F +:103F1000002F022300000000000000000CC0000081 +:103F2000000005498100000000204411000000004D +:103F3000000000010020481100000000000022588D +:103F400000300A240000000000040000006946223E +:103F50000000061400000000C0201C10000000003B +:103F600000000000C04000000000055B00000000F1 +:103F7000002F022300000000000000000CC0000021 +:103F80000000054D00000000C0201C0000000000E3 +:103F900000000000C04000000000055B00000004BD +:103FA000002F022300000000000000000CC00000F1 +:103FB00000000559810000000020441100000000AD +:103FC0000000000000204811000000000000216DEA +:103FD000002044110000000000000000C020480044 +:103FE0000000000000000000C020480000000000A9 +:103FF000000000001AC00000000005549E000000F0 +:104000000020441100000000CAFEBABE0020481182 +:1040100000000000000000001AE00000000005574A +:104020000000000000401C100000055B00000000C4 +:10403000C02000000000000000000000C0400000A0 +:1040400000000000000000000EE000000000055D20 +:104050000000000000600000000005A40000000057 +:10406000002F022400000000000000000CC000002F +:104070000000056D0000A2B7002044110000000000 +:104080000000000000204807000000008100000040 +:104090000020441100000000000000010020481131 +:1040A000000000000004A2B60060441100000614E5 +:1040B0000000001A0021223000000000000000066D +:1040C00000222630000000000000A2C4002044119D +:1040D0000000000000000000003048E9000000007F +:1040E0000000000000E000000000056B0000A2D10D +:1040F00000204411000000000000000000404808BB +:10410000000000000000A2D10020441100000000C7 +:104110000000000100504A280000000000000001DB +:10412000002F022400000000000000000CC000006E +:104130000000057D0000A2BB00204411000000002B +:10414000000000000020480700000000810000007F +:104150000020441100000000000000010020481170 +:10416000000000000004A2BA006044110000061420 +:104170000000001A002122300000000000000006AC +:1041800000222630000000000000A2C500204411DB +:104190000000000000000000003048E900000000BE +:1041A0000000000000E000000000057B0000A2D23B +:1041B00000204411000000000000000000404808FA +:1041C000000000000000A2D2002044110000000006 +:1041D0000000000100504A2800000000000000021A +:1041E000002F022400000000000000000CC00000AE +:1041F0000000058D0000A2BF002044110000000057 +:1042000000000000002048070000000081000000BE +:1042100000204411000000000000000100204811AF +:10422000000000000004A2BE00604411000006145B +:104230000000001A002122300000000000000006EB +:1042400000222630000000000000A2C60020441119 +:104250000000000000000000003048E900000000FD +:104260000000000000E000000000058B0000A2D369 +:104270000020441100000000000000000040480839 +:10428000000000000000A2D3002044110000000044 +:104290000000000100504A28000000000000A2C3F6 +:1042A000002044110000000000000000002048072A +:1042B0000000000081000000002044110000000008 +:1042C0000000000100204811000000000004A2C20C +:1042D00000604411000006140000001A0021223082 +:1042E0000000000000000006002226300000000050 +:1042F0000000A2C7002044110000000000000000E0 +:10430000003048E9000000000000000000E000006C +:10431000000005990000A2D4002044110000000014 +:104320000000000000404808000000000000A2D487 +:1043300000204411000000000000000100504A2845 +:104340000000000085000000002044110000000073 +:104350000000000000204801000000000000304A7A +:10436000002044110000000001000000002048115E +:104370000000000000000000004000000000059F59 +:10438000A4000000C0204411000000000000000054 +:10439000C04048000000000000000000C0600000B5 +:1043A000000005A400000000C0400400000000015F +:1043B0000001A2A400204411000000000000000041 +:1043C00000204811000000000000000000204811FB +:1043D0000000000000000000002048110000000064 +:1043E000000000000020481100000000000000054F +:1043F00000204811000000000000A1F4002044113A +:104400000000000000000000002048110000000033 +:10441000880000000020441100000000000000019E +:104420000020481100000000FF000000002044119F +:104430000000000000000000002048110000000003 +:1044400000000001002048110000000000000002F0 +:104450000080481100000000000000000EE0000095 +:10446000000005B700001000002008110000000047 +:104470000000003400203622000000000000000090 +:1044800000600000000005BB0000000000600000AC +:10449000000005A498000000002044110000000066 +:1044A0000000000000804811000000000000000033 +:1044B000C0600000000005BB00000000C040040018 +:1044C000000000010000A2A4002044110000000030 +:1044D00000000022002048110000000089000000B8 +:1044E00000204411000000000000000100204811DD +:1044F00000000000FF000000002044110000000048 +:104500000000000000204811000000000000000131 +:104510000020481100000000000000020080481147 +:10452000000000000000217AC020441100000000BB +:10453000000000000040481100000000970000004B +:10454000002044110000000000000000002048117D +:10455000000000008A00000000204411000000005C +:10456000000000000020481100000000FF000000D3 +:10457000002044110000000000000000002048114D +:1045800000000000000000010020481100000000B1 +:104590000000000200804811000000000000000040 +:1045A00000600000000005E1000020100020441120 +:1045B0000000000000008000002048110000000002 +:1045C0000001A2A4C020441100000000000000006F +:1045D0000020481100000000000000160060481193 +:1045E0000000035E000000160020481100000000DB +:1045F0000000201000204411000000000001000015 +:10460000002048110000000081000000002044113B +:104610000000000000000001002048110000000020 +:104620000000217C002044110000000009800000EF +:104630000020481100000000FFFFFFFF002048118C +:1046400000000000000000000020481100000000F1 +:104650000000000017000000000000000004217F9F +:1046600000604411000006140000001F0021023009 +:10467000000000000000000014C000000000000066 +:104680000000000400404C11000005DC0000001D8B +:1046900000201E2D000000000000000400291E273D +:1046A000000000000000001D008036270000000010 +:1046B0000000001D00201E2D00000000FFFFFFFB7A +:1046C00000281E27000000000000001D0080362783 +:1046D000000000000000001D00201E2D0000000052 +:1046E0000000000800291E27000000000000001D37 +:1046F00000803627000000000000001D00201E2D55 +:1047000000000000FFFFFFF700281E270000000048 +:104710000000001D0080362700000000000020106F +:10472000002044110000000000008000002048111B +:10473000000000000001A2A40020441100000000BD +:1047400000000000002048110000000000000016DA +:10475000006048110000035E0000001600204811B0 +:1047600000000000000020100020441100000000A4 +:104770000001000000204811000000000000217C22 +:1047800000204411000000000180000000204811BA +:104790000000000000FFFFFF0020481100000000A3 +:1047A0000000000000204811000000000000000090 +:1047B00017000000000000008100000000204411EC +:1047C000000000000000000100204811000000006F +:1047D0000004217F00604411000006140000000066 +:1047E00000200010000000000000000014C00000C5 +:1047F000000006130000001000404C11000005F9F5 +:1048000000000000C02004000000000000000000C4 +:1048100038C00000000000000000002500200A2D24 +:10482000000000000000002600200E2D0000000007 +:10483000000000270020122D0000000000000028CA +:104840000020162D00000000000021690020441106 +:1048500000000000000000000020480400000000EC +:1048600000000000002048050000000000000000DB +:104870000020480100000000CAFEBABE0020481116 +:1048800000000000000000040030122400000000BE +:1048900000000000002F0064000000000000000085 +:1048A0000CC00000000006120000000300281A22BD +:1048B000000000000000000800221222000000009A +:1048C000FFFFF0000028122400000000000000009C +:1048D000002910C40000000000000027004036241A +:1048E0000000000000000000008000000000000048 +:1048F000000000001AC00000000006149F00000025 +:104900000020441100000000CAFEBABE0020481179 +:1049100000000000000000001AE000000000061780 +:104920000000000000800000000000000000000007 +:10493000006000000000000B000010000060041187 +:10494000000002FE00000000002004110000000032 +:1049500000000000006008110000019F0000225CC0 +:104960000020441100000000000000030020481156 +:10497000000000000000225600204411000000004A +:104980000000001B00204811000000000000A1FCF6 +:104990000020441100000000000000010020481128 +:1049A000000000000001A1FDC02044110000000033 +:1049B0000000002900201E2D000000000000001053 +:1049C00000221E27000000000000002C0020222DE5 +:1049D000000000000000FFFF002822280000000067 +:1049E000000000000029490700000000000000004E +:1049F00000204811000000000000002A0020222DA5 +:104A0000000000000000FFFF002822280000000036 +:104A1000000000000029490700000000000000001D +:104A200000204811000000000000002B00201E2D77 +:104A3000000000000000001000221E2700000000FF +:104A400000000000002949070000000000000000ED +:104A500000404811000000000000000000000000BD +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000000000000000000000E6 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000000000000000000B4 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000000000000000000000B2 +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000000000000000000000B1 +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B000013304EF059B02390000000001B00159E1 +:1052C0000425059B00000000021201F6023901428C +:1052D000000000000210022E0289022A00000000D5 +:1052E00003C2059B059B059B0000000005CD05CE74 +:1052F0000308059B00000000059B05A00309032986 +:10530000000000000313026B032B031D00000000CC +:10531000059B059B059B059B00000000059B052C3C +:10532000059B059B0000000003A5059B04A2032D1F +:1053300000000000048104330423059B00000000EA +:1053400004BB04ED042704C800000000043304F487 +:10535000033A036500000000059B059B059B059B28 +:1053600000000000059B059B059B059B00000000BD +:10537000059B059B05B905A200000000059B059B48 +:105380000007059B00000000059B059B059B059BF6 +:1053900000000000059B059B059B059B000000008D +:1053A00003E303D803F303F10000000003F903F55E +:1053B00003F703FB0000000004070403040F040BC1 +:1053C0000000000004170413041F041B0000000069 +:1053D000059B059B059B059B00000000059B059B0D +:1053E000059B059B00000000059B059B059B059BFD +:1053F0000000000000020600061900060000000080 +:00000001FF diff --git a/firmware/radeon/R600_pfp.bin.ihex b/firmware/radeon/R600_pfp.bin.ihex new file mode 100644 index 0000000..5236108 --- /dev/null +++ b/firmware/radeon/R600_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000D4007100D4007200CA040000A00000F7 +:10001000007E828B0080000300CA040000D4401ED2 +:1000200000EE001E00CA040000A00000007E828BCB +:1000300000C4183800CA240000CA2800009581A80E +:1000400000C41C3A00C3C00000CA080000CA0C006B +:10005000007C744B00C200050099C00000C41C3A2B +:10006000007C744C00C0FFF000042C0400309002AF +:10007000007D250000351402007D350B002554035A +:10008000007CD58000259C030095C00400D5001B92 +:10009000007EDDC1007D9D8000D6801B00D5801BC9 +:1000A00000D4401E00D5401E00D6401E00D6801E43 +:1000B00000D4801E00D4C01E009783D400D5C01E7B +:1000C00000CA08000080001B00CA0C0000E4011EEA +:1000D00000D4001E0080000D00C4183800E4013E6A +:1000E00000D4001E0080000D00C4183800D4401E4B +:1000F00000EE001E00CA040000A00000007E828BFB +:1001000000E4011E00D4001E00D4401E00EE001EBC +:1001100000CA040000A00000007E828B00E4013EC3 +:1001200000D4001E00D4401E00EE001E00CA0400D1 +:1001300000A00000007E828B00CA180000D4401E80 +:1001400000D5801E0080005400D4007300D4401EEF +:1001500000CA080000CA0C0000CA100000D48019B0 +:1001600000D4C01800D5001700D4801E00D4C01ED3 +:1001700000D5001E00E2001E00CA040000A000001E +:10018000007E828B00CA080000D4806000D4401E2C +:100190000080000200D4801E00CA080000D48061E4 +:1001A00000D4401E0080000200D4801E00CA080057 +:1001B00000CA0C0000D4401E00D4801600D4C01623 +:1001C00000D4801E008001B900D4C01E00C6083EC5 +:1001D00000CA0C0000CA10000094800400CA140079 +:1001E00000E420F300D4201300D5606500D4E01CA7 +:1001F00000D5201C00D5601C0080000200062001F4 +:1002000000C6083E00CA0C0000CA1000009483F724 +:1002100000CA140000E420F30080007A00D4201308 +:1002200000C6083E00CA0C0000CA1000009883EF08 +:1002300000CA140000D400640080008E000000009A +:1002400000C4143200C6183E00C4082F00954005B3 +:1002500000C40C3000D4401E0080000200EE001EDE +:10026000009583F500C4103100D4403300D52065DB +:1002700000D4A01C00D4E01C00D5201C00D40073C6 +:1002800000E4015E00D4001E008001B900062001D8 +:10029000000A200100D6007400C4083600C61040D1 +:1002A0000098800700CC38350095010F00D4001F5E +:1002B00000D460620080000200D4206200CC1433BD +:1002C000008401BC00D4007000D5401E00800002F4 +:1002D00000EE001E00CA0C0000CA100000D4C01AB4 +:1002E000008401BC00D5001A00CC04430035101F67 +:1002F000002C9401007D098B00984005007D15CBF2 +:1003000000D4001A008001B900D4006D003444010B +:1003100000CC0C440098403A00CC2C460095800458 +:1003200000CC0445008001B900D4001A00D4C01AE2 +:1003300000282801008400F300CC10030098801BE3 +:100340000004380C008400F300CC100300988017E0 +:1003500000043808008400F300CC100300988013D8 +:1003600000043804008400F300CC100300988014CB +:1003700000CC1047009A800900CC1448009840DA5D +:1003800000D4006D00CC184400D5001A00D5401AE6 +:10039000008000CC00D5801A0096C0D300D4006D38 +:1003A000008001B900D4006E009AC00300D4006D33 +:1003B00000D4006E0080000200EC007F009AC0CAEA +:1003C00000D4006D008001B900D4006E00CC14038D +:1003D00000CC180300CC1C03007D9103007DD58365 +:1003E000007D190C0035CC1F0035701F007CF0CB50 +:1003F000007CD08B00880000007E8E8B0095C004AE +:1004000000D4006E008001B900D4001A00D4C01AD4 +:1004100000CC080300CC0C0300CC100300CC140368 +:1004200000CC180300CC1C0300CC240300CC280310 +:100430000035C41F0036B01F007C704B0034F01F25 +:10044000007C704B0035701F007C704B007D8881F4 +:10045000007DCCC1007E5101007E9541007C9082E0 +:10046000007CD4C2007C848B009AC003007C8C8BFF +:10047000002C88010098809C00D4006D0098409A60 +:1004800000D4006E00CC084700CC0C4800CC1044CF +:1004900000D4801A00D4C01A0080010400D5001ACC +:1004A00000CC083200D40032009482D800CA0C007C +:1004B00000D4401E0080000200D4001E00E4011E93 +:1004C00000D4001E00CA080000CA0C0000CA1000B8 +:1004D00000D4401E00CA140000D4801E00D4C01EE8 +:1004E00000D5001E00D5401E00D54034008000021B +:1004F00000EE001E0028040400E2001A00E2001AC8 +:1005000000D4401A00CA380000CC080300CC0C0309 +:1005100000CC0C0300CC0C03009882BC000000004F +:10052000008401BC00D7806F0080000200EE001F35 +:1005300000CA040000C2FF0000CC083400C13FFF25 +:10054000007C74CB007CC90B007D010F009902AFC9 +:10055000007C738B008401BC00D7806F0080000298 +:1005600000EE001F00CA080000281900007D898BDA +:10057000009580140028140400CA0C0000CA100062 +:1005800000CA1C0000CA240000E2001F00D4C01AE8 +:1005900000D5001A00D5401A00CC180300CC2C035B +:1005A00000CC2C0300CC2C03007DA58B007D9C4748 +:1005B00000984296000000000080016400D4C01A38 +:1005C00000D4401E00D4801E0080000200EE001EF9 +:1005D00000E4011E00D4001E00D4401E00EE001EE8 +:1005E00000CA040000A00000007E828B00E4013EEF +:1005F00000D4001E00D4401E00EE001E00CA0400FD +:1006000000A00000007E828B00CA080000248C0637 +:10061000000CCC060098C00600CC104900990004DC +:1006200000D4007100E4011E00D4001E00D4401E5E +:1006300000D4801E0080000200EE001E00CA0800E8 +:1006400000CA0C000034D018002510010095001FCE +:1006500000C17FFF00CA100000CA140000CA1800C1 +:1006600000D4801D00D4C01D007DB18B00C14202AA +:1006700000C2C00100D5801D0034DC0E007D5D4C41 +:10068000007F734C00D7401E00D5001E00D5401ED1 +:1006900000C1420000C2C00000099C010031DC1012 +:1006A000007F5F4C007F734C007D838000D5806F9E +:1006B00000D5806600D7401E00EC005E00C8240212 +:1006C000008001B900D6007400D4401E00D4801E02 +:1006D00000D4C01E0080000200EE001E0080000258 +:1006E00000EE001F00D4001F0080000200D4001F95 +:1006F00000D4001F0088000000D4001F000000008C +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:10080000000101740002017B0003009000040080DD +:100810000005000500060040000700330008012F16 +:1008200000090047000A0037001001B7001700A4B4 +:100830000022013D0023014C002000B500240128C6 +:100840000027004E0028006B002A0061002B005397 +:10085000002F00660032008800340182003C0159FC +:10086000003F00730041018F0044013100550176C3 +:100870000056017D0060000C006100350062003907 +:1008800000630039006400390065003900660039F2 +:10089000006700390068003B00690042006A0049B7 +:1008A000006B0049006C0049006D0049006E004972 +:1008B000006F0049007301B7000000070000000747 +:1008C000000000070000000700000007000000070C +:1008D00000000007000000070000000700000007FC +:1008E00000000007000000070000000700000007EC +:1008F00000000007000000070000000700000007DC +:00000001FF diff --git a/firmware/radeon/RS600_cp.bin.ihex b/firmware/radeon/RS600_cp.bin.ihex new file mode 100644 index 0000000..4a89501 --- /dev/null +++ b/firmware/radeon/RS600_cp.bin.ihex @@ -0,0 +1,130 @@ +:10000000000000004200E000000000004000E000AE +:1000100000000008000000A000000008000000A48C +:10002000000000004A554B4A000000004A4A44675D +:100030000000000055526F75000000004A7E7D658B +:10004000000000004AE74AF6000000004AD34A4A8E +:1000500000000000D689898900000000CD4ADDCF6C +:10006000000000008EBE4AE200000000C38A8A8AB7 +:10007000000000004A0F8CC800000004000CA00023 +:1000800000000038000D0012000000040000E8B479 +:1000900000000038000D0014000000040000E8B665 +:1000A00000000038000D0016000000040000E854B5 +:1000B00000000038000D0018000000040000E855A2 +:1000C00000000038000D001A000000040000E8568F +:1000D00000000038000D001C000000040000E8577C +:1000E00000000038000D001E000000040000E8249D +:1000F00000000038000D0020000000040000E8258A +:1001000000000038000D0022000000040000E8306C +:1001100000000038000D0024000000040000F0C0C2 +:1001200000000038000D0026000000040000F0C1AF +:1001300000000038000D0028000000040000F0411D +:1001400000000038000D002A000000040000F184C7 +:1001500000000038000D002C000000040000F185B4 +:1001600000000038000D002E000000040000F186A1 +:1001700000000038000D0030000000040000F1878E +:1001800000000038000D0032000000040000F18083 +:1001900000000038000D0034000000040000F3935C +:1001A00000000038000D0036000000040000F38A53 +:1001B00000000038000D0038000000040000F38E3D +:1001C000000000040000E821000000040140A0003D +:1001D00000000018000000430000000400CCE8000C +:1001E00000000004001B000100000004080048009B +:1001F00000000004001B000100000004080048008B +:1002000000000004001B000100000004080048007A +:10021000000000080000003A000000000000A000FC +:10022000000000042000451D000000040000E580DF +:1002300000000004000CE581000000040800458077 +:1002400000000004000CE5810000000800000047E9 +:10025000000000000000A00000000004000C2000CE +:10026000000000040000E50E000000040003200070 +:10027000000000280002205100000024000000516E +:10028000000000040800450F000000080000A04B1B +:10029000000000040000E565000000040000E566C1 +:1002A00000000008000000520000000403CCA5B4C8 +:1002B00000000004054320000000000400022000AC +:1002C000000000304CCCE05E0000000408274565CB +:1002D000000000300000005E0000000408004564DB +:1002E000000000040000E566000000080000005562 +:1002F00000000010008020610000000400202000A9 +:1003000000000004001B00FF00000010010000645A +:1003100000000004001F200000000004001C00FF7B +:100320000000000C0000000000000030000000721F +:100330000000000800000055000000040000E57601 +:10034000000000040000E577000000040000E50E56 +:10035000000000040000E50F000000040140A000C0 +:100360000000001800000069000000C200C0E5F9AC +:100370000000000800000069000000040014E50E01 +:10038000000000040040E50F0000000800C0006C01 +:10039000000000040000E570000000040000E571AA +:1003A0000000000C0000E572000000040000A00046 +:1003B000000000040140A000000000040000E56807 +:1003C00000000004000C200000000018000000766F +:1003D00000000004000B00000000000418C0E562EB +:1003E00000000008000000780000000800C000774E +:1003F00000000004000700D5000000380000008461 +:1004000000000030000CA08600000004080045BB7E +:1004100000000030000C2087000000000800E5BC50 +:10042000000000040000E5BB000000000000E5BC87 +:100430000000000C00120000000000040012000088 +:100440000000000C001B0002000000040000A000DF +:10045000000000040000E821000000000000E800A7 +:10046000000000040000E821000000000000E82E69 +:100470000000000402CCA0000000000400140000F2 +:1004800000000004000CE1CC00000004050DE1CDEB +:10049000000000040040000000000018000000966A +:1004A0000000000400C0A00000000008000000934D +:1004B0000000002000000098000000004200E00062 +:1004C000000000380000009F00000004000CA000A5 +:1004D000000000040014000000000004000C2000D4 +:1004E000000000040016000000000004700CE00092 +:1004F000000000080014009B000000004000E00025 +:10050000000000040240000000000004400EE00073 +:100510000000000402400000000000004000E00075 +:1005200000000004000C2000000000040240E51B55 +:10053000000000050080E50A000000050080E50BD2 +:10054000000000040022000000000004000700D5A5 +:1005500000000038000000B200000030000C2087CE +:10056000000000050880E5BD00000030000C20867A +:10057000000000050800E5BB00000030000C2087EB +:10058000000000050880E5BC00000008000000B580 +:10059000000000050080E5BD000000050000E5BB8F +:1005A000000000050080E5BC000000040021000000 +:1005B00000000004028000000000001800C000B924 +:1005C000000000404180E00000000024000000BB6B +:1005D0000000000C010000000000000C0100E51DFF +:1005E00000000004000045BB00000008000080B5CA +:1005F000000000040000F3CE000000040140A00051 +:100600000000000400CC20000000004008C053CFD0 +:100610000000000000008000000000040000F3D291 +:10062000000000040140A0000000000400CC2000F5 +:100630000000004008C053D300000000000080000C +:10064000000000040000F39D000000040140A00031 +:100650000000000400CC20000000004008C0539EB1 +:1006600000000000000080000000000403C008300B +:10067000000000004200E000000000040000A000B4 +:1006800000000004200045E0000000000000E5E15B +:10069000000000000000000100000004000700D27C +:1006A000000000000800E3940000000000000000CB +:1006B000000000040000E8C4000000040000E8C5D9 +:1006C000000000040000E8C6000000040000E92863 +:1006D000000000040000E929000000040000E92AED +:1006E00000000008000000D6000000040000E92817 +:1006F000000000040000E929000000040000E92ACD +:1007000000000008000000DD0000000000E001160D +:1007100000000004000700E1000000040800401C85 +:1007200000000004200050E7000000040000E01D6D +:1007300000000008000000E40000000402C02000E7 +:10074000000000040006000000000034000000EB80 +:1007500000000008000000E8000000040000800025 +:1007600000000000C000E0000000000000000000E9 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B00000000004000C200000000004001D0018D0 +:1007C00000000004001A000100000034000000FBDB +:1007D000000000080000004A000000080500A04AD0 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/RS690_cp.bin.ihex b/firmware/radeon/RS690_cp.bin.ihex new file mode 100644 index 0000000..6896274 --- /dev/null +++ b/firmware/radeon/RS690_cp.bin.ihex @@ -0,0 +1,130 @@ +:1000000000000008000000DD00000008000000DF24 +:1000100000000008000000A000000008000000A48C +:10002000000000004A554B4A000000004A4A44675D +:100030000000000055526F75000000004A7E7D658B +:10004000000000004AD74AF6000000004AC94A4AA8 +:1000500000000000CC89898900000000C34AD3C594 +:10006000000000008E4A4A4A000000004A8A8A8A3C +:10007000000000004A0F8C4A00000004000CA000A1 +:1000800000000038000D0012000000040000E8B479 +:1000900000000038000D0014000000040000E8B665 +:1000A00000000038000D0016000000040000E854B5 +:1000B00000000038000D0018000000040000E855A2 +:1000C00000000038000D001A000000040000E8568F +:1000D00000000038000D001C000000040000E8577C +:1000E00000000038000D001E000000040000E8249D +:1000F00000000038000D0020000000040000E8258A +:1001000000000038000D0022000000040000E8306C +:1001100000000038000D0024000000040000F0C0C2 +:1001200000000038000D0026000000040000F0C1AF +:1001300000000038000D0028000000040000F0411D +:1001400000000038000D002A000000040000F184C7 +:1001500000000038000D002C000000040000F185B4 +:1001600000000038000D002E000000040000F186A1 +:1001700000000038000D0030000000040000F1878E +:1001800000000038000D0032000000040000F18083 +:1001900000000038000D0034000000040000F3935C +:1001A00000000038000D0036000000040000F38A53 +:1001B00000000038000D0038000000040000F38E3D +:1001C000000000040000E821000000040140A0003D +:1001D00000000018000000430000000400CCE8000C +:1001E00000000004001B000100000004080048009B +:1001F00000000004001B000100000004080048008B +:1002000000000004001B000100000004080048007A +:10021000000000080000003A000000000000A000FC +:10022000000000042000451D000000040000E580DF +:1002300000000004000CE581000000040800458077 +:1002400000000004000CE5810000000800000047E9 +:10025000000000000000A00000000004000C2000CE +:10026000000000040000E50E000000040003200070 +:10027000000000280002205100000024000000516E +:10028000000000040800450F000000080000A04B1B +:10029000000000040000E565000000040000E566C1 +:1002A00000000008000000520000000403CCA5B4C8 +:1002B00000000004054320000000000400022000AC +:1002C000000000304CCCE05E0000000408274565CB +:1002D000000000300000005E0000000408004564DB +:1002E000000000040000E566000000080000005562 +:1002F00000000010008020610000000400202000A9 +:1003000000000004001B00FF00000010010000645A +:1003100000000004001F200000000004001C00FF7B +:100320000000000C0000000000000030000000721F +:100330000000000800000055000000040000E57601 +:10034000000000040000E577000000040000E50E56 +:10035000000000040000E50F000000040140A000C0 +:100360000000001800000069000000C200C0E5F9AC +:100370000000000800000069000000040014E50E01 +:10038000000000040040E50F0000000800C0006C01 +:10039000000000040000E570000000040000E571AA +:1003A0000000000C0000E572000000040000A00046 +:1003B000000000040140A000000000040000E56807 +:1003C00000000004000C200000000018000000766F +:1003D00000000004000B00000000000418C0E562EB +:1003E00000000008000000780000000800C000774E +:1003F00000000004000700CB00000038000000846B +:1004000000000030000CA08600000004080045BB7E +:1004100000000030000C2087000000000800E5BC50 +:10042000000000040000E5BB000000000000E5BC87 +:100430000000000C00120000000000040012000088 +:100440000000000C001B0002000000040000A000DF +:10045000000000040000E821000000000000E800A7 +:10046000000000040000E821000000000000E82E69 +:100470000000000402CCA0000000000400140000F2 +:1004800000000004000CE1CC00000004050DE1CDEB +:10049000000000040040000000000018000000966A +:1004A0000000000400C0A00000000008000000934D +:1004B0000000002000000098000000004200E00062 +:1004C000000000380000009F00000004000CA000A5 +:1004D000000000040014000000000004000C2000D4 +:1004E000000000040016000000000004700CE00092 +:1004F000000000080014009B000000004000E00025 +:10050000000000040240000000000004400EE00073 +:100510000000000402400000000000004000E00075 +:100520000000002C0010000000000000000040004F +:1005300000000004080045C8000000040024000575 +:100540000000000408004D0B00000004000C200017 +:10055000000000040240E51B000000050080E50AE1 +:10056000000000050080E50B0000000400220000F0 +:1005700000000004000700CB00000038000000B7B6 +:1005800000000030000C2087000000050880E5BD59 +:1005900000000030000C2086000000050800E5BBCC +:1005A00000000030000C2087000000050880E5BC3A +:1005B00000000008000000BA000000050080E5BD52 +:1005C000000000050000E5BB000000050080E5BC60 +:1005D0000000000400210000000000040280000070 +:1005E0000000001800C000BE000000404180E00094 +:1005F00000000024000000C00000000C010000000A +:100600000000000C0100E51D00000004000045BBD7 +:1006100000000008000080BA0000000403C0083099 +:10062000000000004200E000000000040000A00004 +:1006300000000004200045E0000000000000E5E1AB +:10064000000000000000000100000004000700C8D6 +:10065000000000000800E39400000000000000001B +:10066000000000040000E8C4000000040000E8C529 +:10067000000000040000E8C6000000040000E928B3 +:10068000000000040000E929000000040000E92A3D +:1006900000000008000000CC000000040000E92871 +:1006A000000000040000E929000000040000E92A1D +:1006B00000000008000000D30000000402C0200079 +:1006C000000000040006000000000034000000DB11 +:1006D00000000008000000D80000000400008000B6 +:1006E00000000000C000E00000000030000000E159 +:1006F000000000004200E00000000030000000E1C7 +:10070000000000004000E000000000040025001B85 +:100710000000000400230000000000040025000584 +:1007200000000034000000E60000000C00000000A3 +:10073000000000040024400000000004080045C838 +:1007400000000004002400050000000C08004D0B10 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B00000000004000C200000000004001D0018D0 +:1007C00000000004001A000100000034000000FBDB +:1007D000000000080000004A000000080500A04AD0 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:00000001FF +/* production radeon ucode r1xx-r6xx */ diff --git a/firmware/radeon/RS780_me.bin.ihex b/firmware/radeon/RS780_me.bin.ihex new file mode 100644 index 0000000..6479c10 --- /dev/null +++ b/firmware/radeon/RS780_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A0000060441100000622000000000060000013 +:1000B000000005D10000000000600000000005DE27 +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E000000000000000001800203625000000007D +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000002800204A2D8B +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000001900203625C9 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001700200E2D5A +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001718 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000270020362410 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:10038000000000000000000E0020362300000000E6 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E23000000000000000FC9 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000002700204A2D000000004F +:1003F000000000000020481100000000000000295B +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A00000000000002048040000000000000030AF +:1005B0000020162D00000000000000020029162572 +:1005C0000000000000000030002036250000000080 +:1005D000000000250020162D000000000000000093 +:1005E000002F00A300000000000000000CC000006D +:1005F00000000083000000260020162D00000000EF +:1006000000000000002F00A4000000000000000017 +:100610000CC000000000008400000000004000004A +:100620000000008A000000250020362300000000A2 +:100630000000002600203624000000000000001703 +:1006400000201E2D000000000000000200210227F3 +:10065000000000000000000014E000000000008A1C +:100660000000000000600000000005FF0000000026 +:1006700000600000000005F30000000200210E22CF +:10068000000000000000000014C000000000008D09 +:1006900000000012C040362000000093000000005F +:1006A0002EE0000000000091000000002CE000009F +:1006B000000000900000000200400E2D000000929B +:1006C0000000000300400E2D000000920000000C0E +:1006D00000200E2D00000000000000120020362334 +:1006E000000000000000000300210E2200000000B6 +:1006F0000000000014C00000000000980000A00CE2 +:10070000002044110000000000000000C02048004C +:100710000000000000000000C0404800000000A0F1 +:100720000000A00C002044110000000000000000A8 +:100730000020481100000000000000002EE0000032 +:100740000000009E000000002CE000000000009D62 +:100750000000000200400E2D0000009F000000037A +:1007600000400E2D0000009F0000000C00200E2D08 +:10077000000000000000000000204803000000000E +:1007800000000000003A0C0200000000003F0000E2 +:1007900000280E23000000000000001000210E239E +:1007A00000000000000000110020362300000000BF +:1007B0000000001E0021022B0000000000000000CD +:1007C00014C00000000000A700000016C020362062 +:1007D000000000000000001F0021022B00000000AC +:1007E0000000000014C00000000000AA0000001576 +:1007F000C0203620000000000000000800210E2B61 +:10080000000000000000007F00280E230000000010 +:1008100000000000002F0223000000000000000084 +:100820000CE00000000000E10000000027000000D4 +:10083000000000000000000000600000000002A3B3 +:1008400000000001002F0223000000000000000053 +:100850000AE00000000000B300000000006000009B +:100860000000013A81000000002044110000000057 +:100870000000000600204811000000000000000CED +:1008800000221E300000000099800000002044116A +:1008900000000000000000040020122D00000000F5 +:1008A00000000008002212240000000000000010D8 +:1008B00000201811000000000000000000291CE4C6 +:1008C0000000000000000000006048070000012F49 +:1008D0009B00000000204411000000000000000008 +:1008E00000204802000000009C000000002044118D +:1008F00000000000000000000033146F0000000042 +:100900000000000100333E23000000000000000052 +:10091000D9004800000000000000000000203C0555 +:1009200000000000810000000020441100000000D1 +:100930000000000E00204811000000000000000030 +:1009400000201010000000000000E007002044110B +:10095000000000000000000F0021022B000000003A +:100960000000000014C00000000000CB00F8FF08E9 +:1009700000204811000000009800000000404811CD +:10098000000000DC000000F000280E220000000043 +:10099000000000A0002F0223000000000000000063 +:1009A0000CC00000000000DA0000001100200E2D35 +:1009B0000000000000000001002F022300000000E2 +:1009C000000000000CE00000000000D50000000264 +:1009D000002F022300000000000000000CE00000D7 +:1009E000000000D400003F0000400C11000000D6C1 +:1009F00000001F0000400C11000000D600000F0096 +:100A000000200C11000000000038000900294A23D2 +:100A1000000000003F00000000280E2B0000000036 +:100A20000000000200220E2300000000000000076A +:100A300000494A23000000DC00380F09002048115B +:100A400000000000680000070020481100000000BE +:100A50000000000800214A270000000000000000FC +:100A60000020481100000000060A020000294A2464 +:100A700000000000000000000020481100000000FD +:100A80000000000000204811000000000000A20249 +:100A9000002044110000000000FF000000280E228A +:100AA000000000000000008000294A230000000030 +:100AB0000000002700200E2D00000000000000268E +:100AC0000020122D0000000000000000002F008315 +:100AD00000000000000000000CE00000000000EA40 +:100AE0000000000000600000000005F900000000A8 +:100AF00000400000000000EB00000000006000006B +:100B0000000005FC000000070020222D000000006E +:100B10000000000500220E2200000000001000006E +:100B200000280E23000000000000000000292068BB +:100B30000000000000000000003A0C02000000006D +:100B4000000000EF00280E2300000000000000005D +:100B500000292068000000000000001700200E2D72 +:100B6000000000000000000300210223000000003C +:100B70000000000014E00000000000F80000000B7E +:100B800000210228000000000000000014C0000046 +:100B9000000000F8000004000029222800000000E6 +:100BA0000000001400203628000000000000001C97 +:100BB00000210E22000000000000000014C0000010 +:100BC000000000FD0000A30C002044110000000004 +:100BD0000000000000204811000000000000001E7E +:100BE00000210E22000000000000000014C00000E0 +:100BF0000000010B0000A30F0020441100000000C2 +:100C00000000001100200E2D000000000000000177 +:100C1000002F022300000000000000000CC00000B4 +:100C200000000104FFFFFFFF004048110000010B1E +:100C300000000002002F022300000000000000005E +:100C40000CC00000000001070000FFFF0040481139 +:100C50000000010B00000004002F02230000000030 +:100C6000000000000CC000000000010A000000FFAE +:100C7000004048110000010B000000010020481155 +:100C8000000000000002C400002044110000000029 +:100C90000000001F00210E220000000000000000E4 +:100CA00014C00000000001120000001040210E20BE +:100CB00000000000000000130020362300000000A8 +:100CC0000000001840224A20000000000000001030 +:100CD000C0424A20000001140000000000200C1156 +:100CE0000000000000000013002036230000000078 +:100CF000000000000020481100000000000000007B +:100D000000204811000000000000000A002010111F +:100D10000000000000000000002F0224000000007E +:100D2000000000000CE000000000011B00000000BB +:100D300000204811000000000000000100531224B0 +:100D400000000117FFBFFFFF00283A2E000000003F +:100D50000000001B00210222000000000000000033 +:100D600014C000000000012E81000000002044118A +:100D7000000000000000000D0020481100000000ED +:100D80000000001800220E3000000000FC000000EF +:100D900000280E2300000000810000000020441104 +:100DA000000000000000000E0020481100000000BC +:100DB0000000000000201010000000000000E00E05 +:100DC000002044110000000007F8FF08002048112F +:100DD000000000000000000000294A23000000007D +:100DE0000000001C00201E2D000000000000000874 +:100DF00000214A27000000000000000000204811E8 +:100E000000000000060A020000294A240000000039 +:100E10000000000000204811000000000000000059 +:100E200000204811000000000000000000800000C9 +:100E300000000000810000000020441100000000BC +:100E40000000000100204811000000000000217C8B +:100E50000020441100000000008000000020481124 +:100E60000000000000000000002048060000000014 +:100E70000000000800214A270000000000000000D8 +:100E800017000000000000000004217F00604411F2 +:100E9000000006220000001F0021023000000000B8 +:100EA0000000000014C00000000006210000000443 +:100EB00000404C1100000135810000000020441169 +:100EC00000000000000000010020481100000000A8 +:100ED000000021F800204411000000000000001C68 +:100EE0000020481100000000000421F900604411B6 +:100EF0000000062200000011002102300000000066 +:100F00000000000014E000000000013C00000000B0 +:100F100000800000000000000000000000600000F1 +:100F20000000000B00000000006004110000031529 +:100F3000000000000020041100000000000000007C +:100F400000600811000001B2000000000060000015 +:100F5000000001600000FFFF40280E20000000009C +:100F600000000010C0211220000000000000FFFF60 +:100F7000402806200000000000000010C0210A20C8 +:100F800000000000000000000034146100000000B8 +:100F90000000000000741882000002BB0001A1FDE7 +:100FA00000604411000002E000003FFF002F022F0C +:100FB00000000000000000000CC00000000001471D +:100FC00000000000C040040000000001000000001C +:100FD000006000000000000B000000000060041131 +:100FE00000000315000000000020041100000000B4 +:100FF0000000000000600811000001B200003FFF87 +:10100000002F022F00000000000000000CE0000094 +:10101000000000000000000000600000000001600F +:101020000000001040210E20000000000000FFFF23 +:10103000C0281220000000000000001040211620EF +:10104000000000000000FFFFC0681A20000002BB83 +:101050000001A1FD00604411000002E000003FFF1C +:10106000002F022F00000000000000000CC0000054 +:101070000000015800000000C04004000000000112 +:101080000000225C0020441100000000000000016C +:1010900000300A2F000000000000000100210A2299 +:1010A000000000000000000300384A220000000099 +:1010B0000000225600204411000000000000001A29 +:1010C00000204811000000000000A1FC0020441195 +:1010D0000000000000000001008048110000000036 +:1010E00000000000006000000000000B0000000095 +:1010F000006000000000018F0000000000600000A0 +:10110000000001A000003FFF002F022F00000000A0 +:10111000000000000CE000000000000000000000E3 +:1011200000202C0800000000000000000020241116 +:101130000000000000000000002028110000000056 +:10114000000022560020441100000000000000169C +:1011500000204811000000000000225C0020441123 +:101160000000000000000003002048110000000003 +:1011700093800000002044110000000000000002E5 +:1011800000221E290000000000000000007048EB53 +:101190000000019C0000000000600000000002BB95 +:1011A00000000001403306200000000000000000A5 +:1011B000C03024090000000000003FFF002F022F74 +:1011C00000000000000000000CE000000000000033 +:1011D0000000000000600000000002A3000000000A +:1011E000002F022100000000000000000AE00000C3 +:1011F0000000018100000000006000000000013AD2 +:101200000000000000400000000001869500000082 +:10121000002044110000000000000000002F022107 +:1012200000000000000000000CE00000000001864B +:1012300000000000C0204800000000000000000185 +:10124000005306210000018292000000002044119A +:101250000000000000000000C0604800000001978E +:101260000001A1FD00204411000000000000001159 +:101270000020062D00000000000000000078042A75 +:10128000000002FB00000000002028090000000010 +:1012900000003FFF002F022F0000000000000000B0 +:1012A0000CC000000000017400000000C0400400F9 +:1012B000000000010000021000600411000003158E +:1012C00000003FFF002F022F000000000000000080 +:1012D0000CE000000000019400000015C020362042 +:1012E0000000000000000016C020362000000000B2 +:1012F0003F800000002004110000000046000000B4 +:1013000000600811000001B2000000000080000031 +:10131000000000000000A1FC0020441100000000BB +:1013200000003FFF002F022F00000000000000001F +:101330000CC000000000019B00000001008048116B +:1013400000000000000000210080481100000000A3 +:101350000000FFFF40280E200000000000000010E9 +:10136000C0211220000000000000FFFF40281620CE +:101370000000000000000010C0811A2000000000E2 +:101380008100000000204411000000000000000661 +:1013900000204811000000000000000800221E305C +:1013A000000000000000002900201A2D00000000AD +:1013B0000000E0000020441100000000FFFBFF09D6 +:1013C00000204811000000000000000F0020222D26 +:1013D0000000000000001FFF00294A280000000054 +:1013E000000000060020222D000000000000000088 +:1013F000002920E80000000000000000002048084C +:101400000000000000000000002048110000000063 +:10141000060A020000294A26000000000000000021 +:1014200000204811000000000000000000204811CA +:101430000000000000000100002018110000000062 +:101440000000000800621E280000012F00000008B4 +:1014500000822228000000000002C0000020441189 +:10146000000000000000001500600E2D000001BD0E +:101470000000001600600E2D000001BD0000C00835 +:1014800000204411000000000000001700200E2D75 +:10149000000000000000000014C00000000001B9BE +:1014A0000000000000200411000000000000000007 +:1014B0000020480100000000390000000020481111 +:1014C00000000000000000000020481100000000A3 +:1014D000000000000080480200000000000000182A +:1014E00000202E2D0000000000000000003B0D63D6 +:1014F000000000000000000800224A230000000055 +:101500000000001000224A23000000000000001824 +:1015100000224A2300000000000000000080480371 +:101520000000000000000000006000000000000B50 +:10153000000010000060041100000315000000000E +:1015400000200411000000000000000000600811ED +:10155000000001B2000000070021062F000000007B +:101560000000001300200A2D000000000000000110 +:1015700000202C11000000000000FFFF4028222066 +:10158000000000000000000F0026222800000000DC +:101590000000001040212620000000000000000F85 +:1015A000002626290000000000000000002028027C +:1015B000000000000000225600204411000000003E +:1015C0000000001B00204811000000000000000087 +:1015D000002F022100000000000000000CE00000CD +:1015E000000001E00000225C002044110000000027 +:1015F0000000008100204811000000000000A1FC54 +:1016000000204411000000000000000100204811EB +:10161000000000000000008000201C1100000000FD +:1016200000000000002F0227000000000000000062 +:101630000CE00000000001DC000000000060000081 +:10164000000001E90000000100531E27000001D83E +:101650000000000100202C11000000000000001F0D +:1016600000280A22000000000000001F00282A2A8B +:10167000000000000000000100530621000001D11D +:101680000000225C00204411000000000000000265 +:1016900000304A2F000000000000A1FC002044118F +:1016A00000000000000000010020481100000000C0 +:1016B0000000000100301E2F0000000000000000AC +:1016C000002F022700000000000000000CE00000D6 +:1016D000000000000000000000600000000001E9C0 +:1016E0000000000100531E27000001E50000FFFF7D +:1016F00040280E20000000000000000F00260E23EE +:101700000000000000000010C021122000000000B6 +:101710000000000F0026122400000000000000005E +:1017200000201411000000000000000000601811EB +:10173000000002BB0001A1FD0020441100000000D8 +:1017400000000000002F022B00000000000000003D +:101750000CE00000000001F8000000100022162834 +:1017600000000000FFFF0000002816250000000018 +:101770000000FFFF00281A29000000000000000000 +:10178000002948C500000000000000000020480AB1 +:10179000000000000000000000202C1100000000EC +:1017A000000000100022162300000000FFFF0000D0 +:1017B00000281625000000000000FFFF00281A2462 +:1017C0000000000000000000002948C500000000E3 +:1017D0000000000000731503000002050000000077 +:1017E0000020180500000000000000000073152410 +:1017F0000000020500000000002D14C500000000DC +:1018000000000000003008A20000000000000000FE +:101810000020480200000000000000000020280214 +:101820000000000000000000002020030000000075 +:101830000000000000802404000000000000000FF1 +:1018400000210225000000000000000014C000007C +:101850000000062100000000002B1405000000001D +:1018600000000001009016250000000000000000AC +:10187000006000000000000B000000000060041188 +:10188000000003150000000000200411000000000B +:101890000000000000600811000001B200002256A4 +:1018A00000204411000000000000001A00294A2214 +:1018B0000000000000000000C02000000000000048 +:1018C00000003FFF002F022F00000000000000007A +:1018D0000CE000000000000000000000C020040038 +:1018E000000000000000225C002044110000000005 +:1018F0000000000300384A21000000000000A1FCA5 +:1019000000204411000000000000000100204811E8 +:10191000000000000000FFFF40281220000000002F +:1019200000000010C0211A20000000000000FFFF8E +:1019300040280E200000000000000010C0211620EA +:10194000000000000000000000741465000002BBED +:101950000001A1FD00604411000002E00000000150 +:10196000003306210000000000000000002F0221CB +:1019700000000000000000000CC000000000021980 +:1019800000003FFF002F022F0000000000000000B9 +:101990000CC000000000021200000000C040040063 +:1019A000000000010000000000600000000005DEF3 +:1019B000000000000040040F0000021300000000BF +:1019C00000600000000005D1000000000060000081 +:1019D000000005DE00000210006004110000031585 +:1019E0000000000000600000000001A000000000F6 +:1019F000006000000000019C00000000006000008A +:101A0000000002BB0000000000600000000002A314 +:101A1000938000000020441100000000000000003E +:101A2000002048080000000000000000002F022FE6 +:101A300000000000000000000AE000000000023288 +:101A400000000000006000000000013A00000000FB +:101A50000040000000000236950000000020441104 +:101A60000000000000000000002F022F0000000016 +:101A7000000000000CE00000000002360000000042 +:101A8000C0404800000002339200000000204411D2 +:101A90000000000000000000C0204800000000001E +:101AA0000000225600204411000000000000001633 +:101AB00000204811000000000000225C00204411BA +:101AC000000000000000000300204811000000009A +:101AD0000000A1FC002044110000000000000001F3 +:101AE00000204811000000000001A1FD0020441169 +:101AF000000000000000000000600411000002FB74 +:101B000000000000C04004000000000100000000D0 +:101B100000600000000005D10000A00C002044116E +:101B20000000000000000000C0204800000000008D +:101B300000000000C040480000000000000000005D +:101B4000006000000000000B0000001840210A2087 +:101B50000000000000000003002F0222000000002F +:101B6000000000000AE000000000024C0000001429 +:101B70000020222D00000000000801010029222879 +:101B800000000000000000140020362800000000C3 +:101B90000000A30C00204411000000000000000021 +:101BA000C02048000000000000000000C0204800E5 +:101BB0000000000000000000C0404800000002518A +:101BC00000000000006000000000000B000000109A +:101BD00000600411000003153F8000000020041184 +:101BE000000000000000000000600811000001B2C9 +:101BF0000000225C002044110000000000000003EF +:101C000000204811000000000000000000600000FB +:101C10000000027C0000001700201E2D00000000C4 +:101C20000000000100211E2700000000000000004D +:101C300014E000000000026A0000001200201E2DC7 +:101C4000000000000000FFFF00281E270000000029 +:101C50000000000000341C2700000000000000000D +:101C600012C000000000025F0000000000201C11F4 +:101C70000000000000000000002F00E50000000050 +:101C80000000000008C00000000002620000000028 +:101C900000201407000000000000001200201E2D8C +:101CA000000000000000001000211E2700000000BE +:101CB0000000000000341C4700000000000000008D +:101CC00012C00000000002670000000000201C118C +:101CD0000000000000000000002F00E600000000EF +:101CE0000000000008C000000000026A00000000C0 +:101CF0000020180700000000000000000060000045 +:101D0000000002C100002256002044110000000023 +:101D1000000000000034202300000000000000004C +:101D200012C00000000002720000000000342044D5 +:101D3000000000000000000012C00000000002715E +:101D40000000001600404811000002760000001854 +:101D500000404811000002760000000000342044DA +:101D6000000000000000000012C00000000002752A +:101D70000000001700404811000002760000001922 +:101D800000204811000000000000A1FC00204411C8 +:101D900000000000000000010020481100000000C9 +:101DA0000001A1FD00604411000002E900003FFFB6 +:101DB000002F022F00000000000000000CC00000F7 +:101DC0000000025600000000C040040000000001B6 +:101DD0000000001040210620000000000000FFFF6E +:101DE000C0280A20000000000000001040210E2042 +:101DF000000000000000FFFFC028122000000000CB +:101E00000000001040211620000000000000FFFF2D +:101E1000C0881A200000000081000000002044114A +:101E20000000000000000001002048110000000038 +:101E3000000420040060441100000622000000009D +:101E400000600000000005D100000000C06000003C +:101E5000000002A30000000500200A2D0000000081 +:101E60000000000800220A22000000000000002BF1 +:101E700000201A2D000000000000001C00201E2D74 +:101E8000000000000000700000281E270000000075 +:101E90000000000000311CE6000000000000002AE5 +:101EA00000201A2D000000000000000C00221A265D +:101EB0000000000000000000002F00E6000000000D +:101EC0000000000006E00000000002920000000098 +:101ED00000201C11000000000000000000200C1178 +:101EE000000000000000002B00203623000000004E +:101EF0000000001000201811000000000000000089 +:101F000000691CE20000012F9380000000204411B2 +:101F10000000000000000000002048070000000052 +:101F200095000000002044110000000000000000A7 +:101F3000002F022F00000000000000000CE0000055 +:101F40000000029D0000000100333E2F0000000051 +:101F500000000000D90048000000000092000000CE +:101F6000002044110000000000000000C0204800D4 +:101F7000000000000000001C0040362700000000A8 +:101F80000000000CC0220A20000000000000002910 +:101F9000002036220000000000000028C04036204B +:101FA000000000000000A2A4002044110000000076 +:101FB000000000090020481100000000A1000000FE +:101FC00000204411000000000000000100804811C2 +:101FD000000000000000002100201E2D0000000075 +:101FE00000000000002C1CE30000000000000021A5 +:101FF00000203627000000000000002200201E2DD7 +:102000000000000000000000002C1CE400000000A4 +:1020100000000022002036270000000000000023FE +:1020200000201E2D0000000000000000003120A351 +:102030000000000000000000002D1D07000000004F +:1020400000000023002036270000000000000024CC +:1020500000201E2D0000000000000000003120C400 +:102060000000000000000000002D1D07000000001F +:10207000000000240080362700000000000000213E +:10208000002036230000000000000022002036243B +:10209000000000000000000000311CA30000000050 +:1020A0000000002300203627000000000000000090 +:1020B00000311CC40000000000000024008036270E +:1020C000000000000000001A002036270000000079 +:1020D0000000001B00203628000000000000001750 +:1020E00000201E2D00000000000000020021022739 +:1020F000000000000000000014C00000000002DC2E +:102100000000000000400000000002D90000001A9A +:1021100000203627000000000000001B00203628A9 +:10212000000000000000001700201E2D000000002D +:102130000000000200210227000000000000000053 +:1021400014E00000000002D9000000030021022773 +:10215000000000000000000014E00000000002DCAD +:102160000000002300201E2D0000000000000000E1 +:10217000002E00E1000000000000000002C000008E +:10218000000002DC0000002100201E2D00000000E5 +:1021900000000000003120A100000000000000004D +:1021A000002E00E8000000000000000006C0000053 +:1021B000000002DC0000002400201E2D00000000B2 +:1021C00000000000002E00E20000000000000000FF +:1021D00002C00000000002DC0000002200201E2DD2 +:1021E0000000000000000000003120C200000000DC +:1021F00000000000002E00E80000000000000000C9 +:1022000006C00000000002DC0000000000600000CA +:10221000000005FF0000000000600000000002B5A3 +:102220000000000000400000000002DE000000008E +:1022300000600000000002B5000000000060000027 +:10224000000005F60000000000400000000002DE73 +:102250000000000000600000000002A70000000075 +:1022600000400000000002DE0000001A00201E2DC9 +:10227000000000000000001B0080222D0000000074 +:102280000000001000221E230000000000000000DB +:1022900000294887000000000000000000311CA356 +:1022A000000000000000001000221E2700000000B7 +:1022B0000000000000294887000000000000001016 +:1022C00000221E230000000000000000003120C496 +:1022D000000000000000FFFF00282228000000008E +:1022E0000000000000894907000000000000001005 +:1022F00000221E2300000000000000000029488783 +:10230000000000000000001000221E21000000005C +:102310000000000000294847000000000000000005 +:1023200000311CA3000000000000001000221E2746 +:1023300000000000000000000029488700000000A5 +:102340000000000000311CA100000000000000108F +:1023500000221E270000000000000000002948475E +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:10239000000000000000001000221E2100000000CC +:1023A00000000000003120C2000000000000FFFF1C +:1023B00000282228000000000000000000894907D2 +:1023C000000000000000001000221E23000000009A +:1023D0000000000000294887000000000000000104 +:1023E00000220A210000000000000000003308A2C3 +:1023F000000000000000001000221E22000000006B +:102400000000001000212222000000000000000057 +:1024100000294907000000000000000000311CA353 +:10242000000000000000001000221E270000000035 +:1024300000000000002948870000000000000001A3 +:1024400000220A210000000000000000003008A265 +:10245000000000000000001000221E22000000000A +:1024600000000010002122220000000000000000F7 +:1024700000294907000000000000001000221E2370 +:102480000000000000000000003120C40000000037 +:102490000000FFFF002822280000000000000000CC +:1024A000002949070000000000000000003808C5AE +:1024B00000000000000000000030084100000000A3 +:1024C0000000000100220A220000000000000000BD +:1024D000003308A2000000000000001000221E22AD +:1024E0000000000000000010002122220000000077 +:1024F00000000000008949070000000000000017EC +:102500000020222D000000000000000014C0000088 +:1025100000000318FFFFFFEF002806210000000065 +:10252000000000140020222D000000000000F8E050 +:1025300000204411000000000000000000294901B3 +:1025400000000000000000000089490100000000B8 +:102550000000000000204811000000000000000002 +:102560000020481100000000060A02000080481107 +:102570000000000000000000C0200000000000007B +:1025800097000000C020441100000000000000007F +:10259000C0204811000000008A0000000020441103 +:1025A00000000000000000000020481100000000B2 +:1025B0000000225C00204411000000000000000028 +:1025C000C0204800000000000000A1FC00204411D1 +:1025D0000000000000000000C020480000000000D3 +:1025E00000000000C0200400000000000000000007 +:1025F00000A0000A0000000097000000C020441165 +:102600000000000000000000C02048110000000091 +:102610008A000000C02044110000000000000000FB +:1026200000204811000000000000225C002044113E +:102630000000000000000000C02048000000000072 +:102640000000A1FC00204411000000000000000078 +:10265000C02048000000000000000000C02004006E +:10266000000000000000000000A0000A00000000C0 +:10267000970000000020441100000000000000004E +:1026800000204811000000008A00000000204411D2 +:1026900000000000000000000020481100000000C1 +:1026A0000000225C00204411000000000000000037 +:1026B000C0204800000000000000A1FC00204411E0 +:1026C0000000000000000000C020480000000000E2 +:1026D00000000000C0200400000000000000000016 +:1026E00000A0000A00000000970000000020441134 +:1026F0000000000000000000002048110000000061 +:102700008A000000002044110000000000000000CA +:1027100000204811000000000000225C002044114D +:102720000000000000000000C02048000000000081 +:102730000000A1FC00204411000000000000000087 +:10274000C0204800000000000001A1FD002044114D +:102750000000000000000000D90048000000000058 +:1027600000000000C0200400000000000000000085 +:1027700000A0000A000000000000225700204411C1 +:102780000000000000000003C0484A2000000000D4 +:102790000000225D00204411000000000000000045 +:1027A000C040480000000000000000000060000081 +:1027B000000005DE00000000C0200800000000004E +:1027C0000000225C00204411000000000000000313 +:1027D00000384A22000000000000A1FC0020441143 +:1027E0000000000000000000C020480000000000C1 +:1027F0000001A1FD002044110000000000000000C5 +:10280000002F022200000000000000000CE0000089 +:102810000000000000000000402048000000000010 +:102820000000000140304A200000000000000002CB +:10283000C0304A20000000000000000100530A22BE +:10284000000003550000003FC0280A2000000000DF +:102850008100000000204411000000000000000181 +:102860000020481100000000000021F80020441161 +:1028700000000000000000180020481100000000C7 +:10288000000421F90060441100000622000000113C +:1028900000210230000000000000000014E00000F1 +:1028A0000000035E00000014002F02220000000060 +:1028B000000000000CC000000000036C0001A2A496 +:1028C00000204411000000000000000000604802E9 +:1028D00000000374000021000020441100000000EB +:1028E00000000000C02048000000000000000000C0 +:1028F000C02048000000000000000000C020480088 +:102900000000000000000000C0404800000000007F +:1029100000000004002F0222000000000000000060 +:102920000CC00000000003700001A2A400204411AC +:1029300000000000000000000040480200000367A3 +:1029400000000028002F022200000000000000000C +:102950000CC00000000005BA0001A2A40020441130 +:102960000000000000000000004048020000036773 +:102970000000002C00203626000000000000004966 +:1029800000201811000000000000003F0020481146 +:10299000000000000000000100331A2600000000C3 +:1029A00000000000002F02260000000000000000D0 +:1029B0000CC00000000003760000002C00801A2DDF +:1029C000000000000000003FC0280A2000000000B6 +:1029D00000000015002F022200000000000000008F +:1029E0000CE000000000038C00000006002F022213 +:1029F00000000000000000000CE00000000003B731 +:102A000000000016002F022200000000000000005D +:102A10000CE00000000003B900000020002F02229B +:102A200000000000000000000CE00000000003A215 +:102A30000000000F002F0222000000000000000034 +:102A40000CE00000000003AE00000010002F022286 +:102A500000000000000000000CE00000000003AED9 +:102A60000000001E002F02220000000000000000F5 +:102A70000CE00000000003960000A2A40020441116 +:102A800000000000000000000040480200000000BC +:102A90000800000000290A220000000000000003D6 +:102AA00040210E20000000000000000CC021122078 +:102AB00000000000000800000028122400000000B0 +:102AC00000000014C02216200000000000000000DA +:102AD000002914A4000000000000A2A4002044115A +:102AE0000000000000000000002948A200000000D3 +:102AF0000000A1FE002044110000000000000000C2 +:102B00000040480300000000810000000020441144 +:102B1000000000000000000100204811000000003B +:102B2000000021F800204411000000000000001601 +:102B30000020481100000000000421F90060441149 +:102B400000000622000000150021023000000000F5 +:102B50000000000014E00000000003980000210EB7 +:102B6000002044110000000000000000C0204800C8 +:102B70000000000000000000C0204800000000002D +:102B80000000A2A40020441100000000000000008A +:102B900000404802000000008100000000204411B5 +:102BA00000000000000000010020481100000000AB +:102BB000000021F800204411000000000000001770 +:102BC0000020481100000000000421F900604411B9 +:102BD0000000062200000003002102300000000077 +:102BE0000000000014E00000000003A40000210821 +:102BF000002044110000000000000000C020480038 +:102C00000000000000000000C0204800000000009C +:102C10000000A2A4002044110000000000000000F9 +:102C200000404802000000000000A2A4002044115F +:102C3000000000000000000000204802000000002A +:102C4000800000000020441100000000000000008F +:102C50000020481100000000810000000020441105 +:102C600000000000000000100020481100000000DB +:102C70000000000000200010000000000000000024 +:102C800014C00000000003B4000000000040000079 +:102C9000000000000001A2A4002044110000000078 +:102CA0000000000600404811000000000001A2A43E +:102CB00000204411000000000000001600604811D0 +:102CC000000003740000000000400000000000004D +:102CD00000000000C020080000000000000000000C +:102CE000C0200C00000000000000001D0021022395 +:102CF000000000000000000014E00000000003CE0F +:102D000081000000002044110000000000000001CC +:102D10000020481100000000000021F800204411AC +:102D20000000000000000018002048110000000012 +:102D3000000421F900604411000006220000001187 +:102D400000210230000000000000000014E000003C +:102D5000000003C200002100002044110000000018 +:102D600000000000002048020000000000000000F9 +:102D70000020480300000000BABECAFE002048112F +:102D800000000000CAFEBABE00204811000000008A +:102D90000000A2A400204411000000000000000474 +:102DA0000040481100000000000021700020441184 +:102DB00000000000000000000020480200000000A9 +:102DC0000000000000204803000000008100000017 +:102DD00000204411000000000000000A00204811FB +:102DE00000000000000000000020001000000000B3 +:102DF0000000000014C00000000003D38C0000009D +:102E00000020441100000000CAFEBABE0040481174 +:102E100000000000810000000020441100000000BC +:102E200000000001002048110000000000003FFFEA +:102E300040280A20000000008000000040280E20EA +:102E40000000000040000000C02812200000000028 +:102E50000004000000694622000006220000000075 +:102E6000002014100000000000000000002F0223CA +:102E700000000000000000000CC00000000003E1A2 +:102E800000000000C0401800000003E400003FFF05 +:102E9000C0281A2000000000000400000069462637 +:102EA00000000622000000000020181000000000B2 +:102EB00000000000002F02240000000000000000BD +:102EC0000CC00000000003E700000000C0401C0030 +:102ED000000003EA00003FFFC0281E2000000000A1 +:102EE00000040000006946270000062200000000E0 +:102EF00000201C1000000000000000000020440220 +:102F00000000000000000000002820C500000000B4 +:102F100000000000004948E800000000A580000013 +:102F200000200811000000000000200000200C110B +:102F30000000000083000000006044110000041243 +:102F4000000000000020440200000000000000001B +:102F5000C0204800000000000000000040204800A1 +:102F6000000000000000001FC0210220000000003F +:102F70000000000014C00000000003F70000201053 +:102F800000204411000000000000800000204811D3 +:102F9000000000000000FFFFC0481220000003FFF7 +:102FA000A780000000200811000000000000A00021 +:102FB00000200C110000000083000000006044119C +:102FC0000000041200000000002044020000000085 +:102FD00000000000C02048000000000000000000C9 +:102FE000C0204800000000000000FFFFC0281220A1 +:102FF00000000000830000000020441100000000D9 +:103000000000000000304883000000008400000041 +:10301000002044110000000000000000C020480013 +:1030200000000000000000001D0000000000000083 +:103030008300000000604411000004120000000042 +:10304000C040040000000001A98000000020081119 +:10305000000000000000C00000400C11000003FA56 +:10306000AB80000000200811000000000000F8E024 +:1030700000400C11000003FAAD8000000020081190 +:10308000000000000000F88000400C11000003FA6E +:10309000B380000000200811000000000000F3FCD5 +:1030A00000400C11000003FAAF800000002008115E +:1030B000000000000000E00000400C11000003FAD6 +:1030C000B180000000200811000000000000F000A6 +:1030D00000400C11000003FA83000000002044119E +:1030E00000000000000021480020481100000000FE +:1030F00084000000002044110000000000000000D7 +:10310000C020480000000000000000001D0000007A +:10311000000000000000000000800000000000002F +:1031200001182000C0304620000000000000000010 +:10313000D90048000000000000000000C02004008A +:10314000000000000000000000A0000A00000000D5 +:103150000218A000C030462000000000000000005F +:10316000D90048000000000000000000C02004005A +:10317000000000000000000000A0000A00000000A5 +:103180000318C000C030462000000000000000000E +:10319000D90048000000000000000000C02004002A +:1031A000000000000000000000A0000A0000000075 +:1031B0000418F8E0C03046200000000000000000C5 +:1031C000D90048000000000000000000C0200400FA +:1031D000000000000000000000A0000A0000000045 +:1031E0000518F880C03046200000000000000000F4 +:1031F000D90048000000000000000000C0200400CA +:10320000000000000000000000A0000A0000000014 +:103210000618E000C030462000000000000000005A +:10322000D90048000000000000000000C020040099 +:10323000000000000000000000A0000A00000000E4 +:103240000718F000C0304620000000000000000019 +:10325000D90048000000000000000000C020040069 +:10326000000000000000000000A0000A00000000B4 +:103270000818F3FCC03046200000000000000000E9 +:10328000D90048000000000000000000C020040039 +:10329000000000000000000000A0000A0000000084 +:1032A00000000033C0300A200000000000000000D1 +:1032B000C0403440000000000000003000200A2D13 +:1032C0000000000000000000C0290C4000000000C9 +:1032D0000000003000203623000000000000000045 +:1032E000C0200400000000000000000000A0000A50 +:1032F00000000000860000000020441100000000D3 +:1033000000000000004048010000000085000000AF +:10331000C0204411000000000000000000404801EF +:10332000000000000000217C00204411000000008B +:1033300000000018402102200000000000000000F2 +:1033400014C000000000044700800000C0494A206B +:103350000000044800000000C020480000000000F9 +:1033600000000000C0204800000000000000000035 +:10337000C02048000000000081000000002044112F +:1033800000000000000000010020481100000000C3 +:1033900000000000C0200800000000000000000441 +:1033A000002F0222000000000000000006E00000E4 +:1033B000000004500000000400200811000000007C +:1033C0000000000017000000000000000004217F42 +:1033D00000604411000006220000001F002102309E +:1033E000000000000000000014C000000000000009 +:1033F0000000000000404C020000045000000000EB +:10340000C0200C000000000000000000C0201000E0 +:103410000000000000000000C020140000000000B8 +:1034200000000000C02018000000000000000000A4 +:10343000C0201C000000000000007F0000280A21BE +:103440000000000000004500002F022200000000E4 +:10345000000000000CE0000000000461000000001B +:10346000C02020000000000000000004002F0228FF +:10347000000000000000000006E000000000046101 +:1034800000000004002020110000000000000000E7 +:1034900017000000000000000000001000280A23B0 +:1034A0000000000000000010002F022200000000B9 +:1034B000000000000CE00000000004698100000032 +:1034C000002044110000000000000001002048110D +:1034D00000000000000400000069462400000622ED +:1034E00000000000004000000000046E81000000A9 +:1034F00000204411000000000000000000204811DE +:10350000000000000000216D0020441100000000B8 +:10351000000000000020480400000000000000003F +:10352000006048050000062700000000002824F085 +:10353000000000000000000700280A23000000002F +:1035400000000001002F0222000000000000000027 +:103550000AE000000000047500000000002F00C910 +:10356000000000000000000004E000000000048EE5 +:1035700000000000004000000000049B000000026A +:10358000002F022200000000000000000AE00000FE +:103590000000047A00000000002F00C900000000B5 +:1035A0000000000002E000000000048E00000000A7 +:1035B000004000000000049B00000003002F0222D6 +:1035C00000000000000000000AE000000000047F8E +:1035D00000000000002F00C90000000000000000F3 +:1035E0000CE000000000048E00000000004000001D +:1035F0000000049B00000004002F022200000000D5 +:10360000000000000AE00000000004840000000048 +:10361000002F00C900000000000000000AE00000C8 +:103620000000048E00000000004000000000049B29 +:1036300000000005002F0222000000000000000032 +:103640000AE000000000048900000000002F00C90B +:10365000000000000000000006E000000000048EF2 +:1036600000000000004000000000049B0000000675 +:10367000002F022200000000000000000AE000000D +:103680000000048E00000000002F00C900000000B0 +:103690000000000008E000000000048E00000000B0 +:1036A000004000000000049B00007F0000280A2169 +:1036B0000000000000004500002F02220000000072 +:1036C000000000000AE00000000000000000000808 +:1036D00000210A23000000000000000014C00000C8 +:1036E000000004980000216900204411000000003F +:1036F00000000000C02048000000000000000000A2 +:10370000C02048000000000000000000C020480069 +:1037100000000000CAFEBABE0040481100000000D0 +:1037200000000000C0204400000000000000000075 +:10373000C02000000000000000000000C040480061 +:103740000000000000007F0000280A2100000000A7 +:1037500000004500002F02220000000000000000D1 +:103760000AE00000000004A100000000C0200000EA +:103770000000000000000000C02000000000000069 +:1037800000000000C0400000000000000000000039 +:1037900000404C080000046100000000C020080048 +:1037A000000000000000001040210E20000000007A +:1037B0000000001140211220000000000000001253 +:1037C0004021162000000000000021690020441163 +:1037D000000000000000000000204802000000007F +:1037E0000000000000210225000000000000000091 +:1037F00014E00000000004AB00040000C0494A20AF +:10380000000004ACFFFBFFFFC0284A2000000000BE +:103810000000000000210223000000000000000062 +:1038200014E00000000004B800000000C0204800C0 +:103830000000000000000000C02048000000000060 +:103840000000000000210224000000000000000031 +:1038500014C000000000000081000000002044119E +:10386000000000000000000C0020481100000000D3 +:103870000000000000200010000000000000000018 +:1038800014C00000000004B4A00000000020441197 +:1038900000000000CAFEBABE00404811000000004F +:1038A000810000000020441100000000000000041E +:1038B00000204811000000000000216B002044118E +:1038C0000000000000000000C020481000000000C0 +:1038D00081000000002044110000000000000005ED +:1038E00000204811000000000000216C002044115D +:1038F0000000000000000000C02048100000000090 +:1039000000000000002F0224000000000000000062 +:103910000CE000000000000000000000004000007B +:10392000000004B200000000C0210A2000000000D6 +:103930000000000014C00000000004CB8100000063 +:103940000020441100000000000000000020481189 +:10395000000000000000216D002044110000000064 +:1039600000000000C020480000000000000000002F +:10397000C060480000000627000000000040000072 +:10398000000004CF8100000000204411000000006E +:1039900000000001002048110000000000040000A9 +:1039A000C02946200000000000000000C0600000A8 +:1039B0000000062200000001002102220000000099 +:1039C0000000000014C00000000004D600002169BF +:1039D000002044110000000000000000C02048004A +:1039E0000000000000000000C020480000000000AF +:1039F000000000000020481000000000CAFEBABE0F +:103A0000004048110000000000000000C0204400F9 +:103A10000000000000000000C0404810000000004E +:103A2000810000000020441100000000000000019F +:103A30000020481100000000000021F8002044117F +:103A4000000000000000000E0020481100000000EF +:103A5000000421F90060441100000622000000006B +:103A600000210230000000000000000014C000002F +:103A7000000004D800002180002044110000000054 +:103A800000000000C020480000000000000000000E +:103A9000C02000000000000000000000C02048001E +:103AA0000000000000000000C02000000000000036 +:103AB00000000000C04048000000000000000003BB +:103AC00000333E2F00000000000000010021022111 +:103AD000000000000000000014E0000000000508E5 +:103AE0000000002C00200A2D00000000000400004F +:103AF00018E00C11000004F70000000100333E2F15 +:103B000000000000000021690020441100000000B6 +:103B1000000000000020480200000000000000003B +:103B200000204803000000000000000800300A22C6 +:103B30000000000000000000C0204800000000005D +:103B400000000000C02048000000000000002169C3 +:103B50000020441100000000000000000020480286 +:103B600000000000000000000020480300000000EA +:103B70000000000800300A220000000000000000E1 +:103B8000C02048000000000000000000D8C048002D +:103B9000000004EB00002169002044110000000037 +:103BA00000000000002048020000000000000000AB +:103BB00000204803000000000000000800300A2236 +:103BC0000000000000000000C020480000000000CD +:103BD00000000000C0204800000000000000002D90 +:103BE0000020122D000000000000000000290C83BE +:103BF00000000000000021690020441100000000C6 +:103C0000000000000020480200000000000000004A +:103C100000204803000000000000000800300A22D5 +:103C20000000000000000000C0204800000000006C +:103C300000000000C020480000000000000000114B +:103C400000210224000000000000000014C0000059 +:103C5000000000000000000000400000000004B26E +:103C60000000002CC0203620000000000000002DC5 +:103C7000C0403620000000000000000F002102219B +:103C8000000000000000000014C000000000050D4E +:103C900000000000006000000000000B00000000B9 +:103CA000D90000000000000000000000C040040037 +:103CB00000000001B50000000020441100000000D9 +:103CC000000020000020481100000000B6000000A5 +:103CD00000204411000000000000A0000020481156 +:103CE00000000000B70000000020441100000000A8 +:103CF0000000C0000020481100000000B8000000D3 +:103D000000204411000000000000F8E000204811ED +:103D100000000000B9000000002044110000000075 +:103D20000000F8800020481100000000BA000000E8 +:103D300000204411000000000000E00000204811B5 +:103D400000000000BB000000002044110000000043 +:103D50000000F0000020481100000000BC0000003E +:103D600000204411000000000000F3FC0020481176 +:103D7000000000008100000000204411000000004D +:103D8000000000020020481100000000000000FFB9 +:103D900000280E300000000000000000002F022369 +:103DA00000000000000000000CC000000000052121 +:103DB00000000000C020080000000000000000001B +:103DC00014C00000000005360000000000200C11A7 +:103DD000000000000000001C00203623000000004E +:103DE0000000002B00203623000000000000002906 +:103DF00000203623000000000000002800203623A9 +:103E00000000000000000017002036230000000022 +:103E100000000025002036230000000000000026DE +:103E2000002036230000000000000015002036238B +:103E300000000000000000160020362300000000F3 +:103E4000FFFFE00000200C11000000000000002136 +:103E5000002036230000000000000022002036234E +:103E60000000000000001FFF00200C1100000000F7 +:103E70000000002300203623000000000000002482 +:103E80000020362300000000F1FFFFFF00283A2E3B +:103E9000000000000000001AC0220E2000000000F8 +:103EA000000000000029386E0000000081000000C2 +:103EB000002044110000000000000006002048110E +:103EC000000000000000002A402036200000000012 +:103ED00087000000002044110000000000000000E6 +:103EE000C0204800000000000000A1F400204411A0 +:103EF000000000000000000000204810000000004A +:103F00009D00000000204411000000000000001F80 +:103F100040214A20000000009600000000204411CB +:103F20000000000000000000C02048000000000069 +:103F300000000000C0200C00000000000000000095 +:103F4000C0201000000000000000001F0021162407 +:103F5000000000000000000014C00000000000008D +:103F60000000001D002036230000000000000003B8 +:103F700000281E2300000000000000080022222369 +:103F800000000000FFFFF0000028222800000000D1 +:103F900000000000002920E8000000000000001FD1 +:103FA00000203628000000000000001800211E2319 +:103FB0000000000000000020002036270000000064 +:103FC0000000000200221624000000000000000093 +:103FD000003014A8000000000000001E002036255C +:103FE000000000000000000300211A24000000006F +:103FF0001000000000281A2600000000EFFFFFFF5D +:1040000000283A2E0000000000000000004938CED1 +:10401000000006100000000140280A2000000000F7 +:104020000000000640280E200000000000000300F1 +:10403000C028122000000000000000080021122407 +:104040000000000000000000C0201620000000005A +:1040500000000000C0201A20000000000000000046 +:1040600000210222000000000000000014C0000037 +:104070000000056C810000000020441100000000D9 +:10408000000000010020481100000000000022583C +:1040900000300A24000000000004000000694622ED +:1040A00000000622000021690020441100000000E9 +:1040B0000000000000204805000000000002000091 +:1040C00000294A26000000000000000000204810DF +:1040D00000000000CAFEBABE002048110000000027 +:1040E00000000002002F022300000000000000007A +:1040F0000CC000000000057400000000C0201C106F +:104100000000000000000000C04000000000058228 +:1041100000000002002F0223000000000000000049 +:104120000CC0000000000574810000000020441154 +:104130000000000000000001002048110000000005 +:104140000000225800300A24000000000004000093 +:10415000006946220000062200000000C0201C105A +:104160000000000000000000C040000000000582C8 +:1041700000000000002F02230000000000000000EB +:104180000CC000000000057800000000C0201C00EA +:104190000000000000000000C04000000000058298 +:1041A00000000004002F02230000000000000000B7 +:1041B0000CC00000000005808100000000204411B8 +:1041C0000000000000000000002048110000000076 +:1041D0000000216D002044110000000000000000DC +:1041E000C02048000000000000000000C06048003F +:1041F000000006270000000000401C10000005829F +:1042000000000000C02000000000000000000000CE +:10421000C040000000000000000000000EE00000B0 +:10422000000005840000000000600000000005C3DD +:1042300000000000002F0224000000000000000029 +:104240000CC00000000005920000A2B7002044113D +:1042500000000000000000000020480700000000EF +:10426000000000330020262D000000000000001A8E +:10427000002122290000000000000006002226295B +:10428000000000000000A2C4002044110000000053 +:1042900000000000003048E90000000000000000BD +:1042A00000E00000000005900000A2D100204411B1 +:1042B000000000000000000000404808000000006E +:1042C0000000A2D100204411000000000000000105 +:1042D00000504A280000000000000001002F0224C6 +:1042E00000000000000000000CC00000000005A05D +:1042F0000000A2BB002044110000000000000000EC +:104300000020480700000000000000340020262D97 +:10431000000000000000001A002122290000000017 +:104320000000000600222629000000000000A2C5AF +:10433000002044110000000000000000003048E9A7 +:10434000000000000000000000E000000000059EEA +:104350000000A2D200204411000000000000000074 +:1043600000404808000000000000A2D200204411D4 +:10437000000000000000000100504A28000000007A +:1043800000000002002F02240000000000000000D6 +:104390000CC00000000005AE0000A2BF00204411C8 +:1043A000000000000000000000204807000000009E +:1043B000000000350020262D000000000000001A3B +:1043C000002122290000000000000006002226290A +:1043D000000000000000A2C6002044110000000000 +:1043E00000000000003048E900000000000000006C +:1043F00000E00000000005AC0000A2D30020441142 +:10440000000000000000000000404808000000001C +:104410000000A2D3002044110000000000000001B1 +:1044200000504A28000000000000A2C300204411F0 +:10443000000000000000000000204807000000000D +:10444000000000360020262D000000000000001AA9 +:104450000021222900000000000000060022262979 +:10446000000000000000A2C700204411000000006E +:1044700000000000003048E90000000000000000DB +:1044800000E00000000005B80000A2D400204411A4 +:10449000000000000000000000404808000000008C +:1044A0000000A2D400204411000000000000000120 +:1044B00000504A2800000000850000000020441140 +:1044C0000000000000000000002048010000000083 +:1044D0000000304A002044110000000001000000EC +:1044E0000020481100000000000000000040000013 +:1044F000000005BEA4000000C02044110000000020 +:1045000000000000C0404800000000000000000063 +:10451000C0600000000005C300000000C0400400AF +:10452000000000010001A2A40020441100000000CE +:104530000000003F00204811000000000000003F84 +:1045400000204811000000000000003F002048113A +:10455000000000000000003F0020481100000000A3 +:104560000000000500204811000000000000A1F438 +:10457000002044110000000000000000002048114D +:10458000000000008800000000204411000000002E +:10459000000000010020481100000000FF000000A2 +:1045A000002044110000000000000000002048111D +:1045B0000000000000000001002048110000000081 +:1045C0000000000200804811000000000000000010 +:1045D0000EE00000000005D60000100000200811C9 +:1045E000000000000000002B002036220000000028 +:1045F0000000000000600000000005DA000000007C +:1046000000600000000005C3980000000020441175 +:1046100000000000000000000080481100000000C1 +:1046200000000000C0600000000005DA000000008B +:10463000C0400400000000010000A2A400204411BA +:1046400000000000000000220020481100000000CF +:10465000890000000020441100000000000000015B +:1046600000404811000005CD9700000000204411D3 +:1046700000000000000000000020481100000000C1 +:104680008A0000000020441100000000000000002B +:1046900000404811000005CD00000000006000004F +:1046A000000005F30001A2A4C02044110000000096 +:1046B0000000001600604811000003740000201084 +:1046C00000204411000000000001000000204811FB +:1046D00000000000810000000020441100000000E4 +:1046E0000000000100204811000000000000217CB3 +:1046F0000020441100000000098000000020481143 +:1047000000000000FFFFFFFF002048110000000034 +:104710000000000000204811000000000000000020 +:1047200017000000000000000004217F0060441119 +:10473000000006220000001F0021023000000000DF +:104740000000000014C00000000000000000000491 +:1047500000404C11000005ED00000000004000008A +:10476000000000000000001700201E2D00000000C7 +:104770000000000400291E270000000000000017B0 +:1047800000803627000000000000001700201E2DCA +:1047900000000000FFFFFFFB00281E2700000000B4 +:1047A00000000017008036270000000000000017FE +:1047B00000201E2D000000000000000800291E2718 +:1047C00000000000000000170080362700000000F5 +:1047D0000000001700201E2D00000000FFFFFFF763 +:1047E00000281E2700000000000000170080362768 +:1047F000000000000001A2A40020441100000000FD +:104800000000001600604811000003740000201032 +:1048100000204411000000000001000000204811A9 +:10482000000000000000217C002044110000000076 +:10483000018000000020481100000000FFFFFFFF82 +:104840000020481100000000000000000020481176 +:104850000000000000000000170000000000000041 +:104860008100000000204411000000000000000151 +:1048700000204811000000000004217F0060441166 +:10488000000006220000001F00210230000000008E +:104890000000000014C0000000000621000000100D +:1048A00000404C110000060700000000C02004007A +:1048B000000000000000000038C000000000000000 +:1048C0000000001D00200A2D000000000000001E56 +:1048D00000200E2D000000000000001F0020122DFF +:1048E00000000000000000200020162D0000000045 +:1048F00000002169002044110000000000000000B9 +:1049000000204804000000000000000000204805CE +:10491000000000000000000000204801000000002E +:10492000CAFEBABE002048110000000000000004CA +:10493000003012240000000000000000002F00647E +:1049400000000000000000000CC000000000062075 +:104950000000000300281A220000000000000008E8 +:104960000022122200000000FFFFF00000281224A5 +:104970000000000000000000002910C4000000003A +:104980000000001F0040362400000000000000006E +:104990000080000000000000000000001AC00000BD +:1049A000000006229F0000000020441100000000CB +:1049B000CAFEBABE0020481100000000000000003E +:1049C0001AE0000000000625000000000080000042 +:1049D00000000000000000001AC0000000000627D0 +:1049E0009E0000000020441100000000CAFEBABE74 +:1049F0000020481100000000000000001AE0000044 +:104A00000000062A000000000080000000000000F6 +:104A100000000000006000000000000B000010001B +:104A200000600411000003150000000000200411C4 +:104A3000000000000000000000600811000001B24A +:104A40000000225C00204411000000000000000370 +:104A500000204811000000000000225600204411F0 +:104A6000000000000000001B0020481100000000B2 +:104A70000000A1FC00204411000000000000000123 +:104A800000204811000000000001A1FDC0204411D9 +:104A9000000000000000002100201E2D000000008A +:104AA0000000001000221E2700000000000000246B +:104AB0000020222D000000000000FFFF0028222817 +:104AC000000000000000000000294907000000006D +:104AD000000000000020481100000000000000223B +:104AE0000020222D000000000000FFFF00282228E7 +:104AF000000000000000000000294907000000003D +:104B00000000000000204811000000000000002309 +:104B100000201E2D000000000000001000221E27B3 +:104B2000000000000000000000294907000000000C +:104B300000000000004048110000000000000000DC +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000000000000000000B4 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000000000000000000000B2 +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000000000000000000000B1 +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B0000142050A05BA02500000000001C301685E +:1052C000044105BA00000000022502090250015104 +:1052D000000000000223024502A00241000000007D +:1052E00003D705BA05BA05BA0000000005E205E3D8 +:1052F000031F05BA00000000032005BF0320034A76 +:105300000000000003340282034C033E0000000052 +:1053100005BA05BA05BA05BA0000000005BA055776 +:1053200005BA032A0000000003BC05BA04C3034EFB +:105330000000000004A20455043F05BA000000006C +:1053400004D805BA044304E5000000000455050F25 +:10535000035B037B0000000005BA05BA05BA05BA75 +:105360000000000005BA05BA05BA05BA0000000041 +:1053700005BA05BA05D805C10000000005BA05BA8E +:10538000000705BA0000000005BA05BA05BA05BA5B +:105390000000000005BA05BA05BA05BA0000000011 +:1053A00003F803ED0408040600000000040E040ADC +:1053B000040C041000000000041C04180424042041 +:1053C00000000000042C0428043404300000000015 +:1053D00005BA05BA043A04380000000005BA05BA57 +:1053E00005BA05BA0000000005BA05BA05BA05BA43 +:1053F000000000000002060E062C0006000000005F +:00000001FF diff --git a/firmware/radeon/RS780_pfp.bin.ihex b/firmware/radeon/RS780_pfp.bin.ihex new file mode 100644 index 0000000..4088041 --- /dev/null +++ b/firmware/radeon/RS780_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000CA040000A00000007E828B007C038BED +:10001000008001DB007C038B00D4401E00EE001E3C +:1000200000CA040000A00000007E828B00C41838C3 +:1000300000CA240000CA2800009581CB00C41C3AE5 +:1000400000C3C00000CA080000CA0C00007C744B4A +:1000500000C200050099C00000C41C3A007C744C2A +:1000600000C0FFE000042C0800309002007D250055 +:1000700000351402007D350B00255407007CD58027 +:1000800000259C070095C00400D5001B007EDDC143 +:10009000007D9D8000D6801B00D5801B00D4401EB3 +:1000A00000D5401E00D6401E00D6801E00D4801E03 +:1000B00000D4C01E009783D300D5C01E00CA08001C +:1000C0000080001A00CA0C0000E4011E00D4001ECB +:1000D0000080000C00C4183800E4013E00D4001E6B +:1000E0000080000C00C4183800D4401E00EE001E32 +:1000F00000CA040000A00000007E828B00E4011E04 +:1001000000D4001E00D4401E00EE001E00CA0400F1 +:1001100000A00000007E828B00E4013E00D4001E9F +:1001200000D4401E00EE001E00CA040000A0000023 +:10013000007E828B00CA080000CA0C00008001DB30 +:1001400000D4802400CA0800007C00C000C8142528 +:1001500000C81824007C9488007C988000C20003AA +:1001600000D40075007C744C0080006400D4401EF4 +:1001700000CA180000D4401E00D5801E0080006216 +:1001800000D4007500D4401E00CA080000CA0C004C +:1001900000CA100000D4801900D4C01800D5001780 +:1001A00000D4801E00D4C01E00D5001E00E2001E38 +:1001B00000CA040000A00000007E828B00D40075FD +:1001C00000D4401E00CA080000CA0C0000CA10007B +:1001D00000D4801900D4C01800D5001700D4801EA8 +:1001E00000D4C01E00D5001E00EE001E00CA040090 +:1001F00000A00000007E828B00CA080000248C0151 +:1002000000D480600094C0030004100100041002B8 +:1002100000D5002500D4401E0080000000D4801EC0 +:1002200000CA080000D4806100D4401E0080000095 +:1002300000D4801E00CA080000CA0C0000D4401E72 +:1002400000D4801600D4C01600D4801E008001DBCC +:1002500000D4C01E00C6084300CA0C0000CA10002B +:100260000094800400CA140000E420F300D420139A +:1002700000D5606500D4E01C00D5201C00D5601CB2 +:10028000008000000006200100C6084300CA0C00E0 +:1002900000CA1000009483F700CA140000E420F3A1 +:1002A0000080009C00D4201300C6084300CA0C0044 +:1002B00000CA1000009883EF00CA140000D4006444 +:1002C000008000B00000000000C4143200C61843D3 +:1002D00000C4082F0095400500C40C3000D4401E17 +:1002E0000080000000EE001E009583F500C4103170 +:1002F00000D4403300D5206500D4A01C00D4E01CFD +:1003000000D5201C00E4015E00D4001E0080000027 +:100310000006200100CA1800000A200100D600765D +:1003200000C408360098800700C6104500950110EB +:1003300000D4001F00D460620080000000D420625E +:1003400000CC383500CC1433008401DE00D40072B8 +:1003500000D5401E0080000000EE001E00E2001AE2 +:10036000008401DE00E2001A00CC104B00CC0447F0 +:10037000002C9401007D098B00984005007D15CB71 +:1003800000D4001A008001DB00D4006D0034440169 +:1003900000CC0C480098403A00CC2C4A00958004D0 +:1003A00000CC0449008001DB00D4001A00D4C01A3C +:1003B000002828010084011300CC10030098801B42 +:1003C0000004380C0084011300CC1003009880173F +:1003D000000438080084011300CC10030098801337 +:1003E000000438040084011300CC1003009880142A +:1003F00000CC104C009A800900CC144D009840DCD1 +:1004000000D4006D00CC184800D5001A00D5401A61 +:10041000008000EC00D5801A0096C0D500D4006D95 +:10042000008001DB00D4006E009AC00300D4006D90 +:1004300000D4006E0080000000EC007F009AC0CC69 +:1004400000D4006D008001DB00D4006E00CC1403EA +:1004500000CC180300CC1C03007D9103007DD583E4 +:10046000007D190C0035CC1F0035701F007CF0CBCF +:10047000007CD08B00880000007E8E8B0095C0042D +:1004800000D4006E008001DB00D4001A00D4C01A32 +:1004900000CC080300CC0C0300CC100300CC1403E8 +:1004A00000CC180300CC1C0300CC240300CC280390 +:1004B0000035C41F0036B01F007C704B0034F01FA5 +:1004C000007C704B0035701F007C704B007D888174 +:1004D000007DCCC1007E5101007E9541007C908260 +:1004E000007CD4C2007C848B009AC003007C8C8B7F +:1004F000002C88010098809E00D4006D0098409CDC +:1005000000D4006E00CC084C00CC0C4D00CC104840 +:1005100000D4801A00D4C01A0080012400D5001A2B +:1005200000CC083200D40032009482B600CA0C001D +:1005300000D4401E0080000000D4001E00E4011E14 +:1005400000D4001E00CA080000CA0C0000CA100037 +:1005500000D4401E00CA140000D4801E00D4C01E67 +:1005600000D5001E00D5401E00D54034008000009C +:1005700000EE001E0028040400E2001A00E2001A47 +:1005800000D4401A00CA380000CC080300CC0C0389 +:1005900000CC0C0300CC0C030098829A00000000F1 +:1005A000008401DE00D7A06F0080000000EE001F75 +:1005B00000CA040000C2FF0000CC083400C13FFFA5 +:1005C000007C74CB007CC90B007D010F0099028D6B +:1005D000007C738B008401DE00D7A06F00800000D8 +:1005E00000EE001F00CA080000281900007D898B5A +:1005F000009580140028140400CA0C0000CA1000E2 +:1006000000CA1C0000CA240000E2001F00D4C01A67 +:1006100000D5001A00D5401A00CC180300CC2C03DA +:1006200000CC2C0300CC2C03007DA58B007D9C47C7 +:1006300000984274000000000080018400D4C01AB9 +:1006400000D4401E00D4801E0080000000EE001E7A +:1006500000E4011E00D4001E00D4401E00EE001E67 +:1006600000CA040000A00000007E828B00E4013E6E +:1006700000D4001E00D4401E00EE001E00CA04007C +:1006800000A00000007E828B00CA080000248C06B7 +:10069000000CCC060098C00600CC104E0099000457 +:1006A00000D4007300E4011E00D4001E00D4401EDC +:1006B00000D4801E0080000000EE001E00CA08006A +:1006C00000CA0C000034D01800251001009500214C +:1006D00000C17FFF00CA100000CA140000CA180041 +:1006E00000D4801D00D4C01D007DB18B00C142022A +:1006F00000C2C00100D5801D0034DC0E007D5D4CC1 +:10070000007F734C00D7401E00D5001E00D5401E50 +:1007100000C1420000C2C00000099C010031DC1091 +:10072000007F5F4C007F734C00042802007D8380B3 +:1007300000D5A86F00D5806600D7401E00EC005E93 +:1007400000C8240200C82402008001DB00D6007625 +:1007500000D4401E00D4801E00D4C01E00800000C3 +:1007600000EE001E0080000000EE001F00D4001FFD +:100770000080000000D4001F00D4001F008800008B +:1007800000D4001F00000000000000000000000076 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:10080000000101940002019B000300B2000400A259 +:10081000000500030006003F000700320008014FFA +:1008200000090046000A0036001001D9001700C573 +:100830000022015D0023016C002000D70024014844 +:100840000026004D0027005C0028008D0029005183 +:10085000002A007E002B0061002F0088003200AAD1 +:10086000003401A20036006F003C0179003F009582 +:10087000004101AF00440151005501960056019D11 +:100880000060000B00610034006200380063003833 +:1008900000640038006500380066003800670038E2 +:1008A0000068003A00690041006A0048006B004897 +:1008B000006C0048006D0048006E0048006F004862 +:1008C000007301D9000000060000000600000006C9 +:1008D0000000000600000006000000060000000600 +:1008E00000000006000000060000000600000006F0 +:1008F00000000006000000060000000600000006E0 +:00000001FF diff --git a/firmware/radeon/RV610_me.bin.ihex b/firmware/radeon/RV610_me.bin.ihex new file mode 100644 index 0000000..ba19ed8 --- /dev/null +++ b/firmware/radeon/RV610_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A000006044110000068D0000000000600000A8 +:1000B000000006310000000000600000000006455E +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E000000000000000001800203625000000007D +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000002800204A2D8B +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000001900203625C9 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001700200E2D5A +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001718 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000270020362410 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:10038000000000000000000E0020362300000000E6 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E23000000000000000FC9 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000002700204A2D000000004F +:1003F000000000000020481100000000000000295B +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A00000000000002048040000000000000030AF +:1005B0000020162D00000000000000020029162572 +:1005C0000000000000000030002036250000000080 +:1005D000000000250020162D000000000000000093 +:1005E000002F00A300000000000000000CC000006D +:1005F00000000083000000260020162D00000000EF +:1006000000000000002F00A4000000000000000017 +:100610000CC000000000008400000000004000004A +:100620000000008A000000250020362300000000A2 +:100630000000002600203624000000000000001703 +:1006400000201E2D000000000000000200210227F3 +:10065000000000000000000014E000000000008A1C +:1006600000000000006000000000066800000000BC +:10067000006000000000065C0000000200210E2265 +:10068000000000000000000014C000000000008D09 +:1006900000000012C040362000000093000000005F +:1006A0002EE0000000000091000000002CE000009F +:1006B000000000900000000200400E2D000000929B +:1006C0000000000300400E2D000000920000000C0E +:1006D00000200E2D00000000000000120020362334 +:1006E000000000000000000300210E2200000000B6 +:1006F0000000000014C00000000000980000A00CE2 +:10070000002044110000000000000000C02048004C +:100710000000000000000000C0404800000000A0F1 +:100720000000A00C002044110000000000000000A8 +:100730000020481100000000000000002EE0000032 +:100740000000009E000000002CE000000000009D62 +:100750000000000200400E2D0000009F000000037A +:1007600000400E2D0000009F0000000C00200E2D08 +:10077000000000000000000000204803000000000E +:1007800000000000003A0C0200000000003F0000E2 +:1007900000280E23000000000000001000210E239E +:1007A00000000000000000110020362300000000BF +:1007B0000000001E0021022B0000000000000000CD +:1007C00014C00000000000A700000016C020362062 +:1007D000000000000000001F0021022B00000000AC +:1007E0000000000014C00000000000AA0000001576 +:1007F000C0203620000000000000000800210E2B61 +:10080000000000000000007F00280E230000000010 +:1008100000000000002F0223000000000000000084 +:100820000CE00000000000E10000000027000000D4 +:10083000000000000000000000600000000002A3B3 +:1008400000000001002F0223000000000000000053 +:100850000AE00000000000B300000000006000009B +:100860000000013A81000000002044110000000057 +:100870000000000600204811000000000000000CED +:1008800000221E300000000099800000002044116A +:1008900000000000000000040020122D00000000F5 +:1008A00000000008002212240000000000000010D8 +:1008B00000201811000000000000000000291CE4C6 +:1008C0000000000000000000006048070000012F49 +:1008D0009B00000000204411000000000000000008 +:1008E00000204802000000009C000000002044118D +:1008F00000000000000000000033146F0000000042 +:100900000000000100333E23000000000000000052 +:10091000D9004800000000000000000000203C0555 +:1009200000000000810000000020441100000000D1 +:100930000000000E00204811000000000000000030 +:1009400000201010000000000000E007002044110B +:10095000000000000000000F0021022B000000003A +:100960000000000014C00000000000CB00F8FF08E9 +:1009700000204811000000009800000000404811CD +:10098000000000DC000000F000280E220000000043 +:10099000000000A0002F0223000000000000000063 +:1009A0000CC00000000000DA0000001100200E2D35 +:1009B0000000000000000001002F022300000000E2 +:1009C000000000000CE00000000000D50000000264 +:1009D000002F022300000000000000000CE00000D7 +:1009E000000000D400003F0000400C11000000D6C1 +:1009F00000001F0000400C11000000D600000F0096 +:100A000000200C11000000000038000900294A23D2 +:100A1000000000003F00000000280E2B0000000036 +:100A20000000000200220E2300000000000000076A +:100A300000494A23000000DC00380F09002048115B +:100A400000000000680000070020481100000000BE +:100A50000000000800214A270000000000000000FC +:100A60000020481100000000060A020000294A2464 +:100A700000000000000000000020481100000000FD +:100A80000000000000204811000000000000A20249 +:100A9000002044110000000000FF000000280E228A +:100AA000000000000000008000294A230000000030 +:100AB0000000002700200E2D00000000000000268E +:100AC0000020122D0000000000000000002F008315 +:100AD00000000000000000000CE00000000000EA40 +:100AE000000000000060000000000662000000003E +:100AF00000400000000000EB00000000006000006B +:100B000000000665000000070020222D0000000004 +:100B10000000000500220E2200000000001000006E +:100B200000280E23000000000000000000292068BB +:100B30000000000000000000003A0C02000000006D +:100B4000000000EF00280E2300000000000000005D +:100B500000292068000000000000001700200E2D72 +:100B6000000000000000000300210223000000003C +:100B70000000000014E00000000000F80000000B7E +:100B800000210228000000000000000014C0000046 +:100B9000000000F8000004000029222800000000E6 +:100BA0000000001400203628000000000000001C97 +:100BB00000210E22000000000000000014C0000010 +:100BC000000000FD0000A30C002044110000000004 +:100BD0000000000000204811000000000000001E7E +:100BE00000210E22000000000000000014C00000E0 +:100BF0000000010B0000A30F0020441100000000C2 +:100C00000000001100200E2D000000000000000177 +:100C1000002F022300000000000000000CC00000B4 +:100C200000000104FFFFFFFF004048110000010B1E +:100C300000000002002F022300000000000000005E +:100C40000CC00000000001070000FFFF0040481139 +:100C50000000010B00000004002F02230000000030 +:100C6000000000000CC000000000010A000000FFAE +:100C7000004048110000010B000000010020481155 +:100C8000000000000002C400002044110000000029 +:100C90000000001F00210E220000000000000000E4 +:100CA00014C00000000001120000001040210E20BE +:100CB00000000000000000130020362300000000A8 +:100CC0000000001840224A20000000000000001030 +:100CD000C0424A20000001140000000000200C1156 +:100CE0000000000000000013002036230000000078 +:100CF000000000000020481100000000000000007B +:100D000000204811000000000000000A002010111F +:100D10000000000000000000002F0224000000007E +:100D2000000000000CE000000000011B00000000BB +:100D300000204811000000000000000100531224B0 +:100D400000000117FFBFFFFF00283A2E000000003F +:100D50000000001B00210222000000000000000033 +:100D600014C000000000012E81000000002044118A +:100D7000000000000000000D0020481100000000ED +:100D80000000001800220E3000000000FC000000EF +:100D900000280E2300000000810000000020441104 +:100DA000000000000000000E0020481100000000BC +:100DB0000000000000201010000000000000E00E05 +:100DC000002044110000000007F8FF08002048112F +:100DD000000000000000000000294A23000000007D +:100DE0000000001C00201E2D000000000000000874 +:100DF00000214A27000000000000000000204811E8 +:100E000000000000060A020000294A240000000039 +:100E10000000000000204811000000000000000059 +:100E200000204811000000000000000000800000C9 +:100E300000000000810000000020441100000000BC +:100E40000000000100204811000000000000217C8B +:100E50000020441100000000008000000020481124 +:100E60000000000000000000002048060000000014 +:100E70000000000800214A270000000000000000D8 +:100E800017000000000000000004217F00604411F2 +:100E90000000068D0000001F00210230000000004D +:100EA0000000000014C000000000068C00000004D8 +:100EB00000404C1100000135810000000020441169 +:100EC00000000000000000010020481100000000A8 +:100ED000000021F800204411000000000000001C68 +:100EE0000020481100000000000421F900604411B6 +:100EF0000000068D000000110021023000000000FB +:100F00000000000014E000000000013C00000000B0 +:100F100000800000000000000000000000600000F1 +:100F20000000000B00000000006004110000031529 +:100F3000000000000020041100000000000000007C +:100F400000600811000001B2000000000060000015 +:100F5000000001600000FFFF40280E20000000009C +:100F600000000010C0211220000000000000FFFF60 +:100F7000402806200000000000000010C0210A20C8 +:100F800000000000000000000034146100000000B8 +:100F90000000000000741882000002BB0001A1FDE7 +:100FA00000604411000002E000003FFF002F022F0C +:100FB00000000000000000000CC00000000001471D +:100FC00000000000C040040000000001000000001C +:100FD000006000000000000B000000000060041131 +:100FE00000000315000000000020041100000000B4 +:100FF0000000000000600811000001B200003FFF87 +:10100000002F022F00000000000000000CE0000094 +:10101000000000000000000000600000000001600F +:101020000000001040210E20000000000000FFFF23 +:10103000C0281220000000000000001040211620EF +:10104000000000000000FFFFC0681A20000002BB83 +:101050000001A1FD00604411000002E000003FFF1C +:10106000002F022F00000000000000000CC0000054 +:101070000000015800000000C04004000000000112 +:101080000000225C0020441100000000000000016C +:1010900000300A2F000000000000000100210A2299 +:1010A000000000000000000300384A220000000099 +:1010B0000000225600204411000000000000001A29 +:1010C00000204811000000000000A1FC0020441195 +:1010D0000000000000000001008048110000000036 +:1010E00000000000006000000000000B0000000095 +:1010F000006000000000018F0000000000600000A0 +:10110000000001A000003FFF002F022F00000000A0 +:10111000000000000CE000000000000000000000E3 +:1011200000202C0800000000000000000020241116 +:101130000000000000000000002028110000000056 +:10114000000022560020441100000000000000169C +:1011500000204811000000000000225C0020441123 +:101160000000000000000003002048110000000003 +:1011700093800000002044110000000000000002E5 +:1011800000221E290000000000000000007048EB53 +:101190000000019C0000000000600000000002BB95 +:1011A00000000001403306200000000000000000A5 +:1011B000C03024090000000000003FFF002F022F74 +:1011C00000000000000000000CE000000000000033 +:1011D0000000000000600000000002A3000000000A +:1011E000002F022100000000000000000AE00000C3 +:1011F0000000018100000000006000000000013AD2 +:101200000000000000400000000001869500000082 +:10121000002044110000000000000000002F022107 +:1012200000000000000000000CE00000000001864B +:1012300000000000C0204800000000000000000185 +:10124000005306210000018292000000002044119A +:101250000000000000000000C0604800000001978E +:101260000001A1FD00204411000000000000001159 +:101270000020062D00000000000000000078042A75 +:10128000000002FB00000000002028090000000010 +:1012900000003FFF002F022F0000000000000000B0 +:1012A0000CC000000000017400000000C0400400F9 +:1012B000000000010000021000600411000003158E +:1012C00000003FFF002F022F000000000000000080 +:1012D0000CE000000000019400000015C020362042 +:1012E0000000000000000016C020362000000000B2 +:1012F0003F800000002004110000000046000000B4 +:1013000000600811000001B2000000000080000031 +:10131000000000000000A1FC0020441100000000BB +:1013200000003FFF002F022F00000000000000001F +:101330000CC000000000019B00000001008048116B +:1013400000000000000000210080481100000000A3 +:101350000000FFFF40280E200000000000000010E9 +:10136000C0211220000000000000FFFF40281620CE +:101370000000000000000010C0811A2000000000E2 +:101380008100000000204411000000000000000661 +:1013900000204811000000000000000800221E305C +:1013A000000000000000002900201A2D00000000AD +:1013B0000000E0000020441100000000FFFBFF09D6 +:1013C00000204811000000000000000F0020222D26 +:1013D0000000000000001FFF00294A280000000054 +:1013E000000000060020222D000000000000000088 +:1013F000002920E80000000000000000002048084C +:101400000000000000000000002048110000000063 +:10141000060A020000294A26000000000000000021 +:1014200000204811000000000000000000204811CA +:101430000000000000000100002018110000000062 +:101440000000000800621E280000012F00000008B4 +:1014500000822228000000000002C0000020441189 +:10146000000000000000001500600E2D000001BD0E +:101470000000001600600E2D000001BD0000C00835 +:1014800000204411000000000000001700200E2D75 +:10149000000000000000000014C00000000001B9BE +:1014A0000000000000200411000000000000000007 +:1014B0000020480100000000390000000020481111 +:1014C00000000000000000000020481100000000A3 +:1014D000000000000080480200000000000000182A +:1014E00000202E2D0000000000000000003B0D63D6 +:1014F000000000000000000800224A230000000055 +:101500000000001000224A23000000000000001824 +:1015100000224A2300000000000000000080480371 +:101520000000000000000000006000000000000B50 +:10153000000010000060041100000315000000000E +:1015400000200411000000000000000000600811ED +:10155000000001B2000000070021062F000000007B +:101560000000001300200A2D000000000000000110 +:1015700000202C11000000000000FFFF4028222066 +:10158000000000000000000F0026222800000000DC +:101590000000001040212620000000000000000F85 +:1015A000002626290000000000000000002028027C +:1015B000000000000000225600204411000000003E +:1015C0000000001B00204811000000000000000087 +:1015D000002F022100000000000000000CE00000CD +:1015E000000001E00000225C002044110000000027 +:1015F0000000008100204811000000000000A1FC54 +:1016000000204411000000000000000100204811EB +:10161000000000000000008000201C1100000000FD +:1016200000000000002F0227000000000000000062 +:101630000CE00000000001DC000000000060000081 +:10164000000001E90000000100531E27000001D83E +:101650000000000100202C11000000000000001F0D +:1016600000280A22000000000000001F00282A2A8B +:10167000000000000000000100530621000001D11D +:101680000000225C00204411000000000000000265 +:1016900000304A2F000000000000A1FC002044118F +:1016A00000000000000000010020481100000000C0 +:1016B0000000000100301E2F0000000000000000AC +:1016C000002F022700000000000000000CE00000D6 +:1016D000000000000000000000600000000001E9C0 +:1016E0000000000100531E27000001E50000FFFF7D +:1016F00040280E20000000000000000F00260E23EE +:101700000000000000000010C021122000000000B6 +:101710000000000F0026122400000000000000005E +:1017200000201411000000000000000000601811EB +:10173000000002BB0001A1FD0020441100000000D8 +:1017400000000000002F022B00000000000000003D +:101750000CE00000000001F8000000100022162834 +:1017600000000000FFFF0000002816250000000018 +:101770000000FFFF00281A29000000000000000000 +:10178000002948C500000000000000000020480AB1 +:10179000000000000000000000202C1100000000EC +:1017A000000000100022162300000000FFFF0000D0 +:1017B00000281625000000000000FFFF00281A2462 +:1017C0000000000000000000002948C500000000E3 +:1017D0000000000000731503000002050000000077 +:1017E0000020180500000000000000000073152410 +:1017F0000000020500000000002D14C500000000DC +:1018000000000000003008A20000000000000000FE +:101810000020480200000000000000000020280214 +:101820000000000000000000002020030000000075 +:101830000000000000802404000000000000000FF1 +:1018400000210225000000000000000014C000007C +:101850000000068C00000000002B140500000000B2 +:1018600000000001009016250000000000000000AC +:10187000006000000000000B000000000060041188 +:10188000000003150000000000200411000000000B +:101890000000000000600811000001B200002256A4 +:1018A00000204411000000000000001A00294A2214 +:1018B0000000000000000000C02000000000000048 +:1018C00000003FFF002F022F00000000000000007A +:1018D0000CE000000000000000000000C020040038 +:1018E000000000000000225C002044110000000005 +:1018F0000000000300384A21000000000000A1FCA5 +:1019000000204411000000000000000100204811E8 +:10191000000000000000FFFF40281220000000002F +:1019200000000010C0211A20000000000000FFFF8E +:1019300040280E200000000000000010C0211620EA +:10194000000000000000000000741465000002BBED +:101950000001A1FD00604411000002E00000000150 +:10196000003306210000000000000000002F0221CB +:1019700000000000000000000CC000000000021980 +:1019800000003FFF002F022F0000000000000000B9 +:101990000CC000000000021200000000C040040063 +:1019A000000000010000000000600000000006458B +:1019B000000000000040040F0000021300000000BF +:1019C0000060000000000631000000000060000020 +:1019D000000006450000021000600411000003151D +:1019E0000000000000600000000001A000000000F6 +:1019F000006000000000019C00000000006000008A +:101A0000000002BB0000000000600000000002A314 +:101A1000938000000020441100000000000000003E +:101A2000002048080000000000000000002F022FE6 +:101A300000000000000000000AE000000000023288 +:101A400000000000006000000000013A00000000FB +:101A50000040000000000236950000000020441104 +:101A60000000000000000000002F022F0000000016 +:101A7000000000000CE00000000002360000000042 +:101A8000C0404800000002339200000000204411D2 +:101A90000000000000000000C0204800000000001E +:101AA0000000225600204411000000000000001633 +:101AB00000204811000000000000225C00204411BA +:101AC000000000000000000300204811000000009A +:101AD0000000A1FC002044110000000000000001F3 +:101AE00000204811000000000001A1FD0020441169 +:101AF000000000000000000000600411000002FB74 +:101B000000000000C04004000000000100000000D0 +:101B100000600000000006310000A00C002044110D +:101B20000000000000000000C0204800000000008D +:101B300000000000C040480000000000000000005D +:101B4000006000000000000B0000001840210A2087 +:101B50000000000000000003002F0222000000002F +:101B6000000000000AE000000000024C0000001429 +:101B70000020222D00000000000801010029222879 +:101B800000000000000000140020362800000000C3 +:101B90000000A30C00204411000000000000000021 +:101BA000C02048000000000000000000C0204800E5 +:101BB0000000000000000000C0404800000002518A +:101BC00000000000006000000000000B000000109A +:101BD00000600411000003153F8000000020041184 +:101BE000000000000000000000600811000001B2C9 +:101BF0000000225C002044110000000000000003EF +:101C000000204811000000000000000000600000FB +:101C10000000027C0000001700201E2D00000000C4 +:101C20000000000100211E2700000000000000004D +:101C300014E000000000026A0000001200201E2DC7 +:101C4000000000000000FFFF00281E270000000029 +:101C50000000000000341C2700000000000000000D +:101C600012C000000000025F0000000000201C11F4 +:101C70000000000000000000002F00E50000000050 +:101C80000000000008C00000000002620000000028 +:101C900000201407000000000000001200201E2D8C +:101CA000000000000000001000211E2700000000BE +:101CB0000000000000341C4700000000000000008D +:101CC00012C00000000002670000000000201C118C +:101CD0000000000000000000002F00E600000000EF +:101CE0000000000008C000000000026A00000000C0 +:101CF0000020180700000000000000000060000045 +:101D0000000002C100002256002044110000000023 +:101D1000000000000034202300000000000000004C +:101D200012C00000000002720000000000342044D5 +:101D3000000000000000000012C00000000002715E +:101D40000000001600404811000002760000001854 +:101D500000404811000002760000000000342044DA +:101D6000000000000000000012C00000000002752A +:101D70000000001700404811000002760000001922 +:101D800000204811000000000000A1FC00204411C8 +:101D900000000000000000010020481100000000C9 +:101DA0000001A1FD00604411000002E900003FFFB6 +:101DB000002F022F00000000000000000CC00000F7 +:101DC0000000025600000000C040040000000001B6 +:101DD0000000001040210620000000000000FFFF6E +:101DE000C0280A20000000000000001040210E2042 +:101DF000000000000000FFFFC028122000000000CB +:101E00000000001040211620000000000000FFFF2D +:101E1000C0881A200000000081000000002044114A +:101E20000000000000000001002048110000000038 +:101E300000042004006044110000068D0000000032 +:101E4000006000000000063100000000C0600000DB +:101E5000000002A30000000500200A2D0000000081 +:101E60000000000800220A22000000000000002BF1 +:101E700000201A2D000000000000001C00201E2D74 +:101E8000000000000000700000281E270000000075 +:101E90000000000000311CE6000000000000002AE5 +:101EA00000201A2D000000000000000C00221A265D +:101EB0000000000000000000002F00E6000000000D +:101EC0000000000006E00000000002920000000098 +:101ED00000201C11000000000000000000200C1178 +:101EE000000000000000002B00203623000000004E +:101EF0000000001000201811000000000000000089 +:101F000000691CE20000012F9380000000204411B2 +:101F10000000000000000000002048070000000052 +:101F200095000000002044110000000000000000A7 +:101F3000002F022F00000000000000000CE0000055 +:101F40000000029D0000000100333E2F0000000051 +:101F500000000000D90048000000000092000000CE +:101F6000002044110000000000000000C0204800D4 +:101F7000000000000000001C0040362700000000A8 +:101F80000000000CC0220A20000000000000002910 +:101F9000002036220000000000000028C04036204B +:101FA000000000000000A2A4002044110000000076 +:101FB000000000090020481100000000A1000000FE +:101FC00000204411000000000000000100804811C2 +:101FD000000000000000002100201E2D0000000075 +:101FE00000000000002C1CE30000000000000021A5 +:101FF00000203627000000000000002200201E2DD7 +:102000000000000000000000002C1CE400000000A4 +:1020100000000022002036270000000000000023FE +:1020200000201E2D0000000000000000003120A351 +:102030000000000000000000002D1D07000000004F +:1020400000000023002036270000000000000024CC +:1020500000201E2D0000000000000000003120C400 +:102060000000000000000000002D1D07000000001F +:10207000000000240080362700000000000000213E +:10208000002036230000000000000022002036243B +:10209000000000000000000000311CA30000000050 +:1020A0000000002300203627000000000000000090 +:1020B00000311CC40000000000000024008036270E +:1020C000000000000000001A002036270000000079 +:1020D0000000001B00203628000000000000001750 +:1020E00000201E2D00000000000000020021022739 +:1020F000000000000000000014C00000000002DC2E +:102100000000000000400000000002D90000001A9A +:1021100000203627000000000000001B00203628A9 +:10212000000000000000001700201E2D000000002D +:102130000000000200210227000000000000000053 +:1021400014E00000000002D9000000030021022773 +:10215000000000000000000014E00000000002DCAD +:102160000000002300201E2D0000000000000000E1 +:10217000002E00E1000000000000000002C000008E +:10218000000002DC0000002100201E2D00000000E5 +:1021900000000000003120A100000000000000004D +:1021A000002E00E8000000000000000006C0000053 +:1021B000000002DC0000002400201E2D00000000B2 +:1021C00000000000002E00E20000000000000000FF +:1021D00002C00000000002DC0000002200201E2DD2 +:1021E0000000000000000000003120C200000000DC +:1021F00000000000002E00E80000000000000000C9 +:1022000006C00000000002DC0000000000600000CA +:10221000000006680000000000600000000002B539 +:102220000000000000400000000002DE000000008E +:1022300000600000000002B5000000000060000027 +:102240000000065F0000000000400000000002DE09 +:102250000000000000600000000002A70000000075 +:1022600000400000000002DE0000001A00201E2DC9 +:10227000000000000000001B0080222D0000000074 +:102280000000001000221E230000000000000000DB +:1022900000294887000000000000000000311CA356 +:1022A000000000000000001000221E2700000000B7 +:1022B0000000000000294887000000000000001016 +:1022C00000221E230000000000000000003120C496 +:1022D000000000000000FFFF00282228000000008E +:1022E0000000000000894907000000000000001005 +:1022F00000221E2300000000000000000029488783 +:10230000000000000000001000221E21000000005C +:102310000000000000294847000000000000000005 +:1023200000311CA3000000000000001000221E2746 +:1023300000000000000000000029488700000000A5 +:102340000000000000311CA100000000000000108F +:1023500000221E270000000000000000002948475E +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:10239000000000000000001000221E2100000000CC +:1023A00000000000003120C2000000000000FFFF1C +:1023B00000282228000000000000000000894907D2 +:1023C000000000000000001000221E23000000009A +:1023D0000000000000294887000000000000000104 +:1023E00000220A210000000000000000003308A2C3 +:1023F000000000000000001000221E22000000006B +:102400000000001000212222000000000000000057 +:1024100000294907000000000000000000311CA353 +:10242000000000000000001000221E270000000035 +:1024300000000000002948870000000000000001A3 +:1024400000220A210000000000000000003008A265 +:10245000000000000000001000221E22000000000A +:1024600000000010002122220000000000000000F7 +:1024700000294907000000000000001000221E2370 +:102480000000000000000000003120C40000000037 +:102490000000FFFF002822280000000000000000CC +:1024A000002949070000000000000000003808C5AE +:1024B00000000000000000000030084100000000A3 +:1024C0000000000100220A220000000000000000BD +:1024D000003308A2000000000000001000221E22AD +:1024E0000000000000000010002122220000000077 +:1024F00000000000008949070000000000000017EC +:102500000020222D000000000000000014C0000088 +:1025100000000318FFFFFFEF002806210000000065 +:10252000000000140020222D000000000000F8E050 +:1025300000204411000000000000000000294901B3 +:1025400000000000000000000089490100000000B8 +:102550000000000000204811000000000000000002 +:102560000020481100000000060A02000080481107 +:102570000000000000000000C0200000000000007B +:1025800097000000C020441100000000000000007F +:10259000C0204811000000008A0000000020441103 +:1025A00000000000000000000020481100000000B2 +:1025B0000000225C00204411000000000000000028 +:1025C000C0204800000000000000A1FC00204411D1 +:1025D0000000000000000000C020480000000000D3 +:1025E00000000000C0200400000000000000000007 +:1025F00000A0000A00000000970000000020441125 +:102600000000000000000000002048110000000051 +:102610008A000000002044110000000000000000BB +:1026200000204811000000000000225C002044113E +:102630000000000000000000C02048000000000072 +:102640000000A1FC00204411000000000000000078 +:10265000C02048000000000000000000C02004006E +:10266000000000000000000000A0000A00000000C0 +:10267000970000000020441100000000000000004E +:1026800000204811000000008A00000000204411D2 +:1026900000000000000000000020481100000000C1 +:1026A0000000225C00204411000000000000000037 +:1026B000C0204800000000000000A1FC00204411E0 +:1026C0000000000000000000C020480000000000E2 +:1026D0000001A1FD002044110000000000000000E6 +:1026E000D90048000000000000000000C0200400E5 +:1026F000000000000000000000A0000A0000000030 +:1027000000002257002044110000000000000003D8 +:10271000C0484A20000000000000225D0020441153 +:102720000000000000000000C04048000000000061 +:1027300000000000006000000000064500000000EE +:10274000C0200800000000000000225C00204411AE +:10275000000000000000000300384A2200000000D2 +:102760000000A1FC00204411000000000000000057 +:10277000C0204800000000000001A1FD002044111D +:102780000000000000000000002F022200000000F6 +:10279000000000000CE0000000000000000000004D +:1027A00040204800000000000000000140304A20A6 +:1027B0000000000000000002C0304A2000000000BD +:1027C0000000000100530A220000034B0000003FFC +:1027D000C0280A20000000008100000000204411F1 +:1027E000000000000000000100204811000000006F +:1027F000000021F800204411000000000000001833 +:102800000020481100000000000421F9006044117C +:102810000000068D000000110021023000000000C1 +:102820000000000014E00000000003540000001449 +:10283000002F022200000000000000000CC0000079 +:10284000000003640000201000204411000000007C +:102850000000800000204811000000000001A2A438 +:102860000020441100000000000000000060480249 +:102870000000036E00002100002044110000000051 +:1028800000000000C0204800000000000000000020 +:10289000C02048000000000000000000C0204800E8 +:1028A0000000000000000000C040480000000000E0 +:1028B00000000004002F02220000000000000000C1 +:1028C0000CC000000000036A00002010002044112A +:1028D00000000000000080000020481100000000FF +:1028E0000001A2A40020441100000000000000002C +:1028F000004048020000035F00000028002F022271 +:1029000000000000000000000CC00000000005C036 +:102910000001A2A4002044110000000000000000FB +:10292000004048020000035F0000002C0020362613 +:102930000000000000000049002018110000000005 +:102940000000003F002048110000000000000001CE +:1029500000331A260000000000000000002F0226AD +:1029600000000000000000000CC000000000037028 +:102970000000002C00801A2D000000000000003F25 +:10298000C0280A200000000000000015002F0222CD +:1029900000000000000000000CE0000000000386C2 +:1029A00000000006002F02220000000000000000CE +:1029B0000CE00000000003B100000016002F02220E +:1029C00000000000000000000CE00000000003B563 +:1029D00000000020002F0222000000000000000084 +:1029E0000CE000000000039C0000000F002F0222FA +:1029F00000000000000000000CE00000000003A840 +:102A000000000010002F0222000000000000000063 +:102A10000CE00000000003A80000001E002F0222AE +:102A200000000000000000000CE000000000039027 +:102A30000000A2A4002044110000000000000000DB +:102A400000404802000000000800000000290A229F +:102A5000000000000000000340210E2000000000E4 +:102A60000000000CC021122000000000000800003F +:102A7000002812240000000000000014C0221620CC +:102A80000000000000000000002914A40000000065 +:102A90000000A2A40020441100000000000000007B +:102AA000002948A2000000000000A1FE00204411FF +:102AB000000000000000000000404803000000008B +:102AC000810000000020441100000000000000010F +:102AD0000020481100000000000021F800204411EF +:102AE0000000000000000016002048110000000057 +:102AF000000421F9006044110000068D000000155B +:102B000000210230000000000000000014E000007E +:102B1000000003920000210E00204411000000007C +:102B200000000000C020480000000000000000007D +:102B3000C0204800000000000000A2A400204411B2 +:102B400000000000000000000040480200000000FB +:102B5000810000000020441100000000000000017E +:102B60000020481100000000000021F8002044115E +:102B700000000000000000170020481100000000C5 +:102B8000000421F9006044110000068D00000003DC +:102B900000210230000000000000000014E00000EE +:102BA0000000039E000021080020441100000000E6 +:102BB00000000000C02048000000000000000000ED +:102BC000C0204800000000000000A2A40020441122 +:102BD000000000000000000000404802000000006B +:102BE0000000A2A40020441100000000000000002A +:102BF0000020480200000000800000000020441176 +:102C0000000000000000000000204811000000004B +:102C100081000000002044110000000000000010AE +:102C200000204811000000000000000000200010FB +:102C3000000000000000000014C00000000003AE0F +:102C40000000000000400000000000000000201014 +:102C50000020441100000000000080000020481106 +:102C6000000000000001A2A40020441100000000A8 +:102C70000000000600404811000000000000201085 +:102C800000204411000000000000800000204811D6 +:102C9000000000000001A2A4002044110000000078 +:102CA00000000016006048110000036E00000000E4 +:102CB000004000000000000000000000C0200800EC +:102CC0000000000000000000C0200C000000000018 +:102CD0000000001D00210223000000000000000091 +:102CE00014E00000000003CE810000000020441129 +:102CF000000000000000000100204811000000005A +:102D0000000021F80020441100000000000000181D +:102D10000020481100000000000421F90060441167 +:102D20000000068D000000110021023000000000AC +:102D30000000000014E00000000003C000002100BB +:102D400000204411000000000000000000204802A4 +:102D50000000000000000000002048030000000008 +:102D6000BABECAFE0020481100000000CAFEBABE6A +:102D70000020481100000000000020100020441135 +:102D8000000000000000800000204811000000004A +:102D90000000A2A400204411000000000000000474 +:102DA0000040481100000000000021700020441184 +:102DB00000000000000000000020480200000000A9 +:102DC0000000000000204803000000008100000017 +:102DD00000204411000000000000000A00204811FB +:102DE00000000000000000000020001000000000B3 +:102DF0000000000014C00000000003D38C0000009D +:102E00000020441100000000CAFEBABE0040481174 +:102E100000000000810000000020441100000000BC +:102E200000000001002048110000000000003FFFEA +:102E300040280A20000000008000000040280E20EA +:102E40000000000040000000C02812200000000028 +:102E500000040000006946220000068D000000000A +:102E6000002014100000000000000000002F0223CA +:102E700000000000000000000CC00000000003E1A2 +:102E800000000000C0401800000003E400003FFF05 +:102E9000C0281A2000000000000400000069462637 +:102EA0000000068D00000000002018100000000047 +:102EB00000000000002F02240000000000000000BD +:102EC0000CC00000000003E700000000C0401C0030 +:102ED000000003EA00003FFFC0281E2000000000A1 +:102EE00000040000006946270000068D0000000075 +:102EF00000201C1000000000000000000020440220 +:102F00000000000000000000002820C500000000B4 +:102F100000000000004948E800000000A580000013 +:102F200000200811000000000000200000200C110B +:102F30000000000083000000006044110000041243 +:102F4000000000000020440200000000000000001B +:102F5000C0204800000000000000000040204800A1 +:102F6000000000000000001FC0210220000000003F +:102F70000000000014C00000000003F70000201053 +:102F800000204411000000000000800000204811D3 +:102F9000000000000000FFFFC0481220000003FFF7 +:102FA000A780000000200811000000000000A00021 +:102FB00000200C110000000083000000006044119C +:102FC0000000041200000000002044020000000085 +:102FD00000000000C02048000000000000000000C9 +:102FE000C0204800000000000000FFFFC0281220A1 +:102FF00000000000830000000020441100000000D9 +:103000000000000000304883000000008400000041 +:10301000002044110000000000000000C020480013 +:1030200000000000000000001D0000000000000083 +:103030008300000000604411000004120000000042 +:10304000C040040000000001A98000000020081119 +:10305000000000000000C00000400C11000003FA56 +:10306000AB80000000200811000000000000F8E024 +:1030700000400C11000003FAAD8000000020081190 +:10308000000000000000F88000400C11000003FA6E +:10309000B380000000200811000000000000F3FCD5 +:1030A00000400C11000003FAAF800000002008115E +:1030B000000000000000E00000400C11000003FAD6 +:1030C000B180000000200811000000000000F000A6 +:1030D00000400C11000003FA83000000002044119E +:1030E00000000000000021480020481100000000FE +:1030F00084000000002044110000000000000000D7 +:10310000C020480000000000000000001D0000007A +:10311000000000000000000000800000000000002F +:1031200001182000C0304620000000000000000010 +:10313000D90048000000000000000000C02004008A +:10314000000000000000000000A0000A00000000D5 +:103150000218A000C030462000000000000000005F +:10316000D90048000000000000000000C02004005A +:10317000000000000000000000A0000A00000000A5 +:103180000318C000C030462000000000000000000E +:10319000D90048000000000000000000C02004002A +:1031A000000000000000000000A0000A0000000075 +:1031B0000418F8E0C03046200000000000000000C5 +:1031C000D90048000000000000000000C0200400FA +:1031D000000000000000000000A0000A0000000045 +:1031E0000518F880C03046200000000000000000F4 +:1031F000D90048000000000000000000C0200400CA +:10320000000000000000000000A0000A0000000014 +:103210000618E000C030462000000000000000005A +:10322000D90048000000000000000000C020040099 +:10323000000000000000000000A0000A00000000E4 +:103240000718F000C0304620000000000000000019 +:10325000D90048000000000000000000C020040069 +:10326000000000000000000000A0000A00000000B4 +:103270000818F3FCC03046200000000000000000E9 +:10328000D90048000000000000000000C020040039 +:10329000000000000000000000A0000A0000000084 +:1032A0000000003000200A2D000000000000000097 +:1032B000C0290C4000000000000000300020362330 +:1032C0000000000000000000C0200400000000001A +:1032D0000000000000A0000A0000000086000000BE +:1032E00000204411000000000000000000404801E0 +:1032F0000000000085000000C02044110000000014 +:103300000000000000404801000000000000217C97 +:10331000002044110000000000000018402102209D +:10332000000000000000000014C000000000044580 +:1033300000800000C0494A20000004460000000050 +:10334000C02048000000000000000000C02048002D +:103350000000000000000000C02048000000000045 +:103360008100000000204411000000000000000166 +:10337000002048110000000000000000C0200800EC +:103380000000000000000000170000000000000026 +:103390000004217F006044110000068D0000001F22 +:1033A00000210230000000000000000014C00000F6 +:1033B000000000000000000000404C020000044B30 +:1033C00000000000C0200C00000000000000000011 +:1033D000C02010000000000000000000C020140009 +:1033E0000000000000000000C020180000000000E5 +:1033F00000000000C0201C000000000000007F0052 +:1034000000280A210000000000004500002F0222D1 +:1034100000000000000000000CE000000000045963 +:1034200000000000C020200000000000000000009C +:1034300017000000000000000000001000280A2310 +:103440000000000000000010002F02220000000019 +:10345000000000000CE0000000000461810000009A +:10346000002044110000000000000001002048116D +:103470000000000000040000006946240000068DE2 +:103480000000000000400000000004668100000011 +:10349000002044110000000000000000002048113E +:1034A000000000000000216D002044110000000019 +:1034B00000000000002048040000000000000000A0 +:1034C000006048050000069200000000002824F07B +:1034D000000000000000000700280A230000000090 +:1034E00000000001002F0222000000000000000088 +:1034F0000AE000000000046D00000000002F00C979 +:10350000000000000000000004E00000000004864D +:1035100000000000004000000000049300000002D2 +:10352000002F022200000000000000000AE000005E +:103530000000047200000000002F00C9000000001D +:103540000000000002E0000000000486000000000F +:10355000004000000000049300000003002F02223E +:1035600000000000000000000AE0000000000477F6 +:1035700000000000002F00C9000000000000000053 +:103580000CE0000000000486000000000040000085 +:103590000000049300000004002F0222000000003D +:1035A000000000000AE000000000047C00000000B1 +:1035B000002F00C900000000000000000AE0000029 +:1035C000000004860000000000400000000004939A +:1035D00000000005002F0222000000000000000093 +:1035E0000AE000000000048100000000002F00C974 +:1035F000000000000000000006E00000000004865B +:1036000000000000004000000000049300000006DD +:10361000002F022200000000000000000AE000006D +:103620000000048600000000002F00C90000000018 +:103630000000000008E00000000004860000000018 +:10364000004000000000049300007F0000280A21D1 +:103650000000000000004500002F022200000000D2 +:10366000000000000AE00000000000000000000868 +:1036700000210A23000000000000000014C0000028 +:1036800000000490000021690020441100000000A7 +:1036900000000000C0204800000000000000000002 +:1036A000C02048000000000000000000C0204800CA +:1036B00000000000CAFEBABE004048110000000031 +:1036C00000000000C02044000000000000000000D6 +:1036D000C02000000000000000000000C0404800C2 +:1036E0000000000000007F0000280A210000000008 +:1036F00000004500002F0222000000000000000032 +:103700000AE000000000049900000000C020000052 +:103710000000000000000000C020000000000000C9 +:1037200000000000C0400000000000000000000099 +:1037300000404C080000045900000000C0200800B0 +:10374000000000000000001040210E2000000000DA +:1037500000000011402112200000000000000012B3 +:1037600040211620000000000000216900204411C3 +:1037700000000000000000000020480200000000DF +:1037800000000000002102250000000000000000F1 +:1037900014E00000000004A300040000C0494A2017 +:1037A000000004A4FFFBFFFFC0284A200000000027 +:1037B00000000000002102230000000000000000C3 +:1037C00014E00000000004B000000000C020480029 +:1037D0000000000000000000C020480000000000C1 +:1037E0000000000000210224000000000000000092 +:1037F00014C00000000000008100000000204411FF +:10380000000000000000000C002048110000000033 +:103810000000000000200010000000000000000078 +:1038200014C00000000004ACA000000000204411FF +:1038300000000000CAFEBABE0040481100000000AF +:10384000810000000020441100000000000000047E +:1038500000204811000000000000216B00204411EE +:103860000000000000000000C02048100000000020 +:10387000810000000020441100000000000000054D +:1038800000204811000000000000216C00204411BD +:103890000000000000000000C020481000000000F0 +:1038A00000000000002F02240000000000000000C3 +:1038B0000CE00000000000000000000000400000DC +:1038C000000004AA00000000C0210A20000000003F +:1038D0000000000014C00000000004C381000000CC +:1038E00000204411000000000000000000204811EA +:1038F000000000000000216D0020441100000000C5 +:1039000000000000C020480000000000000000008F +:10391000C060480000000692000000000040000067 +:10392000000004C7810000000020441100000000D6 +:103930000000000100204811000000000004000009 +:10394000C02946200000000000000000C060000008 +:103950000000068D0000000100210222000000008E +:103960000000000014C00000000004CE0000216927 +:10397000002044110000000000000000C0204800AA +:103980000000000000000000C0204800000000000F +:10399000000000000020481000000000CAFEBABE6F +:1039A000004048110000000000000000C02044005A +:1039B0000000000000000000C040481000000000AF +:1039C0008100000000204411000000000000000100 +:1039D0000020481100000000000021F800204411E0 +:1039E000000000000000000E002048110000000050 +:1039F000000421F9006044110000068D0000000061 +:103A000000210230000000000000000014C000008F +:103A1000000004D0000021800020441100000000BC +:103A200000000000C020480000000000000000006E +:103A3000C02000000000000000000000C02048007E +:103A40000000000000000000C02000000000000096 +:103A500000000000C040480000000000000000031B +:103A600000333E2F00000000000000010021022171 +:103A7000000000000000000014E00000000005004D +:103A80000000002C00200A2D0000000000040000AF +:103A900018E00C11000004EF0000000100333E2F7D +:103AA0000000000000002169002044110000000017 +:103AB000000000000020480200000000000000009C +:103AC00000204803000000000000000800300A2227 +:103AD0000000000000000000C020480000000000BE +:103AE00000000000C0204800000000000000216924 +:103AF00000204411000000000000000000204802E7 +:103B0000000000000000000000204803000000004A +:103B10000000000800300A22000000000000000041 +:103B2000C02048000000000000000000D8C048008D +:103B3000000004E30000216900204411000000009F +:103B4000000000000020480200000000000000000B +:103B500000204803000000000000000800300A2296 +:103B60000000000000000000C0204800000000002D +:103B700000000000C0204800000000000000002DF0 +:103B80000020122D000000000000000000290C831E +:103B90000000000000002169002044110000000026 +:103BA00000000000002048020000000000000000AB +:103BB00000204803000000000000000800300A2236 +:103BC0000000000000000000C020480000000000CD +:103BD00000000000C02048000000000000000011AC +:103BE00000210224000000000000000014C00000BA +:103BF000000000000000000000400000000004AAD7 +:103C00000000002CC0203620000000000000002D25 +:103C1000C0403620000000000000000F00210221FB +:103C2000000000000000000014C0000000000505B6 +:103C300000000000006000000000000B0000000019 +:103C4000D90000000000000000000000C040040097 +:103C500000000001B5000000002044110000000039 +:103C6000000020000020481100000000B600000005 +:103C700000204411000000000000A00000204811B6 +:103C800000000000B7000000002044110000000008 +:103C90000000C0000020481100000000B800000033 +:103CA00000204411000000000000F8E0002048114E +:103CB00000000000B90000000020441100000000D6 +:103CC0000000F8800020481100000000BA00000049 +:103CD00000204411000000000000E0000020481116 +:103CE00000000000BB0000000020441100000000A4 +:103CF0000000F0000020481100000000BC0000009F +:103D000000204411000000000000F3FC00204811D6 +:103D100000000000810000000020441100000000AD +:103D2000000000020020481100000000000000FF19 +:103D300000280E300000000000000000002F0223C9 +:103D400000000000000000000CC000000000051989 +:103D500000000000C020080000000000000000007B +:103D600014C000000000052E0000000000200C110F +:103D7000000000000000001C0020362300000000AE +:103D80000000002B00203623000000000000002966 +:103D90000020362300000000000000280020362309 +:103DA0000000000000000017002036230000000083 +:103DB000000000250020362300000000000000263F +:103DC00000203623000000000000001500203623EC +:103DD0000000000000000016002036230000000054 +:103DE000FFFFE00000200C11000000000000002197 +:103DF00000203623000000000000002200203623AF +:103E00000000000000001FFF00200C110000000057 +:103E100000000023002036230000000000000024E2 +:103E20000020362300000000F1FFFFFF00283A2E9B +:103E3000000000000000001AC0220E200000000058 +:103E4000000000000029386E000000008100000022 +:103E5000002044110000000000000006002048116E +:103E6000000000000000002A402036200000000072 +:103E70008700000000204411000000000000000046 +:103E8000C0204800000000000000A1F40020441100 +:103E900000000000000000000020481000000000AA +:103EA0000000000000200C110000000000000030A5 +:103EB00000203623000000009D0000000020441177 +:103EC000000000000000001F40214A200000000008 +:103ED00096000000002044110000000000000000D7 +:103EE000C02048000000000000000000C0200C00BE +:103EF0000000000000000000C020100000000000D2 +:103F00000000001F00211624000000000000000037 +:103F100014C00000000000000000001D0020362337 +:103F2000000000000000000300281E230000000025 +:103F3000000000080022222300000000FFFFF00024 +:103F4000002822280000000000000000002920E8CE +:103F5000000000000000001F0020362800000000C4 +:103F60000000001800211E230000000000000020B7 +:103F70000020362700000000000000020022162466 +:103F80000000000000000000003014A80000000045 +:103F90000000001E00203625000000000000000385 +:103FA00000211A24000000001000000000281A263A +:103FB00000000000EFFFFFFF00283A2E0000000085 +:103FC00000000000004938CE0000067B0000000120 +:103FD00040280A20000000000000000640280E20B3 +:103FE0000000000000000300C028122000000000B4 +:103FF0000000000800211224000000000000000062 +:10400000C02016200000000000000000C0201A2080 +:10401000000000000000000000210222000000005B +:104020000000000014C000000000056681000000D0 +:104030000020441100000000000000010020481191 +:10404000000000000000225800300A240000000098 +:1040500000040000006946220000068D000021696E +:10406000002044110000000000000000002048056E +:10407000000000000002000000294A2600000000A5 +:10408000000000000020481000000000CAFEBABE78 +:10409000002048110000000000000002002F022351 +:1040A00000000000000000000CC000000000056ED1 +:1040B00000000000C0201C100000000000000000F4 +:1040C000C04000000000057C00000002002F022319 +:1040D00000000000000000000CC000000000056EA1 +:1040E00081000000002044110000000000000001D9 +:1040F00000204811000000000000225800300A246F +:104100000000000000040000006946220000068D47 +:1041100000000000C0201C10000000000000000093 +:10412000C04000000000057C00000000002F0223BA +:1041300000000000000000000CC00000000005723C +:1041400000000000C0201C00000000000000000073 +:10415000C04000000000057C00000004002F022386 +:1041600000000000000000000CC000000000057A04 +:104170008100000000204411000000000000000049 +:1041800000204811000000000000216D00204411B3 +:104190000000000000000000C020480000000000F7 +:1041A00000000000C060480000000692000000000F +:1041B00000401C100000057C00000000C020000032 +:1041C0000000000000000000C040000000000000EF +:1041D000000000000EE000000000057E000000006E +:1041E00000600000000005C900000000002F02244C +:1041F00000000000000000000CC000000000058F5F +:104200000000A2B7002044110000000000000000E0 +:104210000020480700000000810000000020441139 +:104220000000000000000001002048110000000014 +:104230000004A2B6006044110000068D0000001AC0 +:10424000002122300000000000000006002226307D +:104250000000000000042004006044110000068DEE +:104260000000A2C400204411000000000000000073 +:10427000003048E9000000000000000000E00000FD +:104280000000058D0000A2D10020441100000000B4 +:104290000000000000404808000000000000A2D11B +:1042A00000204411000000000000000100504A28D6 +:1042B0000000000000000001002F022400000000A8 +:1042C000000000000CC00000000005A00000A2BB20 +:1042D00000204411000000000000000000204807FA +:1042E00000000000810000000020441100000000D8 +:1042F0000000000100204811000000000004A2BAE4 +:10430000006044110000068D0000001A00212230D8 +:10431000000000000000000600222630000000001F +:1043200000042004006044110000068D0000A2C5B6 +:10433000002044110000000000000000003048E9A7 +:10434000000000000000000000E000000000059EEA +:104350000000A2D200204411000000000000000074 +:1043600000404808000000000000A2D200204411D4 +:10437000000000000000000100504A28000000007A +:1043800000000002002F02240000000000000000D6 +:104390000CC00000000005B10000A2BF00204411C5 +:1043A000000000000000000000204807000000009E +:1043B0008100000000204411000000000000000106 +:1043C00000204811000000000004A2BE006044115B +:1043D0000000068D0000001A0021223000000000BD +:1043E0000000000600222630000000000004200427 +:1043F000006044110000068D0000A2C60020441198 +:104400000000000000000000003048E9000000004B +:104410000000000000E00000000005AF0000A2D393 +:104420000020441100000000000000000040480887 +:10443000000000000000A2D3002044110000000092 +:104440000000000100504A28000000000000A2C344 +:104450000020441100000000000000000020480778 +:104460000000000081000000002044110000000056 +:104470000000000100204811000000000004A2C25A +:10448000006044110000068D0000001A0021223057 +:10449000000000000000000600222630000000009E +:1044A00000042004006044110000068D0000A2C733 +:1044B000002044110000000000000000003048E926 +:1044C000000000000000000000E00000000005BE49 +:1044D0000000A2D4002044110000000000000000F1 +:1044E00000404808000000000000A2D40020441151 +:1044F000000000000000000100504A2800000000F9 +:1045000085000000002044110000000000000000B1 +:1045100000204801000000000000304A0020441143 +:104520000000000001000000002048110000000011 +:104530000000000000400000000005C4A4000000CE +:10454000C02044110000000000000000C0404800EE +:104550000000000000000000C0600000000005C96D +:1045600000000000C0400400000000010000002C1A +:1045700000203621000000008100000000204411CE +:1045800000000000000000060020481100000000AC +:1045900000000000002F02300000000000000000BA +:1045A0000CC00000000005D0000000000020041135 +:1045B000000000000000003000403621000005E34C +:1045C000000000300020062D0000000000007E00EA +:1045D000002806210000000000000000002F02213A +:1045E00000000000000000000CE00000000005E3F7 +:1045F00081000000002044110000000000000001C4 +:1046000000204811000000000004A0920060441146 +:104610000000068D00000031002036300000000050 +:104620000004A093006044110000068D00000032D9 +:1046300000203630000000000004A2B600604411E3 +:104640000000068D0000003300203630000000001E +:104650000004A2BA006044110000068D000000347E +:1046600000203630000000000004A2BE00604411AB +:104670000000068D000000350020363000000000EC +:104680000004A2C2006044110000068D0000003644 +:1046900000203630000000000004200400604411B7 +:1046A0000000068D0001A2A40020441100000000BB +:1046B0000000003F00204811000000000000003F03 +:1046C00000204811000000000000003F00204811B9 +:1046D000000000000000003F002048110000000022 +:1046E0000000000500204811000000000000A1F4B7 +:1046F00000204411000000000000000000204811CC +:1047000000000000880000000020441100000000AC +:10471000000000010020481100000000810000009E +:104720000020441100000000000000060020481195 +:104730000000000000000001002F02300000000017 +:10474000000000000CE000000000062C000000301B +:104750000020062D0000000000000000002F0221B4 +:1047600000000000000000000CE000000000062C2B +:104770008100000000204411000000000000000142 +:10478000002048110000000000007E0000280621E3 +:104790000000000000000000002F022100000000C7 +:1047A000000000000CE00000000006050000A092E0 +:1047B00000204411000000000000003100204A2DBC +:1047C000000000000000A093002044110000000041 +:1047D0000000003200204A2D000000000000A2B6B8 +:1047E00000204411000000000000003300204A2D8A +:1047F000000000000000A2BA0020441100000000E8 +:104800000000003400204A2D000000000000A2BE7D +:1048100000204411000000000000003500204A2D57 +:10482000000000000000A2C20020441100000000AF +:104830000000003600204A2D00000000000000307B +:104840000020062D00000000000001FF00280621C6 +:104850000000000000000000002F02210000000006 +:10486000000000000CE000000000062B000000002B +:1048700000210221000000000000000014C0000020 +:104880000000060E0004A003006044110000068D25 +:104890000000A00300204411000000000000000000 +:1048A0000020481000000000000000010021062147 +:1048B000000000000000000014C00000000006130B +:1048C0000004A010006044110000068D0000A0103C +:1048D00000204411000000000000000000204810EB +:1048E000000000000000000100210621000000007F +:1048F00000000000002F0221000000000000000066 +:104900000CE000000000062B0004A0110060441120 +:104910000000068D0000A0110020441100000000DE +:104920000000000000204810000000000004A01259 +:10493000006044110000068D0000A0120020441108 +:1049400000000000000000000020481000000000EF +:104950000004A013006044110000068D0000A013A5 +:10496000002044110000000000000000002048105A +:10497000000000000004A014006044110000068D37 +:104980000000A014002044110000000000000000FE +:1049900000204810000000000004A0150060441131 +:1049A0000000068D0000A01500204411000000004A +:1049B0000000000000204810000000000004A016C5 +:1049C000006044110000068D0000A0160020441174 +:1049D000000000000000000000204810000000005F +:1049E0000004A017006044110000068D0000A0170D +:1049F00000204411000000000000000000204810CA +:104A00000000000000042004006044110000068D36 +:104A10000000002C0080062D00000000FF000000B8 +:104A20000020441100000000000000000020481198 +:104A300000000000000000010020481100000000FC +:104A4000000000020080481100000000000000008B +:104A50000EE000000000063D000000300020062DA2 +:104A600000000000000000020028062100000000F5 +:104A700000000000002F02210000000000000000E4 +:104A80000CE000000000063B810000000020441103 +:104A9000000000000000000100204811000000009C +:104AA00000042004006044110000068D0000100086 +:104AB00000200811000000000000002B002036221A +:104AC000000000000000000000600000000006413F +:104AD0000000000000600000000005C99800000010 +:104AE0000020441100000000000000000080481178 +:104AF0000000000000000000C0600000000006414F +:104B000000000000C0400400000000010000A2A45A +:104B10000020441100000000000000220020481185 +:104B20000000000089000000002044110000000087 +:104B300000000001004048110000062D9700000011 +:104B40000020441100000000000000000020481177 +:104B5000000000008A000000002044110000000056 +:104B600000000000004048110000062D0000000079 +:104B7000006000000000065C0000201000204411CE +:104B8000000000000000800000204811000000002C +:104B90000001A2A4C0204411000000000000001683 +:104BA000006048110000036E000020100020441136 +:104BB000000000000001000000204811000000007B +:104BC00081000000002044110000000000000001EE +:104BD00000204811000000000000217C002044114A +:104BE00000000000098000000020481100000000C3 +:104BF000FFFFFFFF00204811000000000000000040 +:104C00000020481100000000000000001700000014 +:104C1000000000000004217F006044110000068DA8 +:104C20000000001F00210230000000000000000012 +:104C300014C00000000000000000000400404C11FF +:104C400000000656000000000040000000000000C8 +:104C50000000001700201E2D0000000000000004CE +:104C600000291E27000000000000001700803627E2 +:104C7000000000000000001700201E2D00000000B2 +:104C8000FFFFFFFB00281E270000000000000017A8 +:104C900000803627000000000000001700201E2DB5 +:104CA000000000000000000800291E27000000008E +:104CB00000000017008036270000000000000017E9 +:104CC00000201E2D00000000FFFFFFF700281E2718 +:104CD00000000000000000170080362700000000E0 +:104CE000000020100020441100000000000080009F +:104CF00000204811000000000001A2A4002044117F +:104D00000000000000000016006048110000036E63 +:104D100000002010002044110000000000010000ED +:104D200000204811000000000000217C00204411F8 +:104D30000000000001800000002048110000000079 +:104D4000FFFFFFFF002048110000000000000000EE +:104D500000204811000000000000000017000000C3 +:104D6000000000008100000000204411000000004D +:104D70000000000100204811000000000004217F15 +:104D8000006044110000068D0000001F0021023069 +:104D9000000000000000000014C000000000068CAD +:104DA0000000001000404C110000067200000000DE +:104DB000C0200400000000000000000038C0000017 +:104DC000000000000000001D00200A2D000000006F +:104DD0000000001E00200E2D000000000000001F3B +:104DE0000020122D00000000000000200020162DE1 +:104DF00000000000000021690020441100000000B4 +:104E00000000000000204804000000000000000036 +:104E100000204805000000000000000000204801BC +:104E200000000000CAFEBABE0020481100000000C9 +:104E30000000000400301224000000000000000008 +:104E4000002F006400000000000000000CC0000003 +:104E50000000068B0000000300281A22000000005A +:104E6000000000080022122200000000FFFFF000F6 +:104E7000002812240000000000000000002910C4D7 +:104E8000000000000000001F004036240000000069 +:104E90000000000000800000000000000000000092 +:104EA0001AC000000000068D9F0000000020441181 +:104EB00000000000CAFEBABE002048110000000039 +:104EC000000000001AE00000000006900000000052 +:104ED0000080000000000000000000001AC0000078 +:104EE000000006929E000000002044110000000017 +:104EF000CAFEBABE002048110000000000000000F9 +:104F00001AE000000000069500000000008000008C +:104F10000000000000000000006000000000000B26 +:104F200000001000006004110000031500000000E4 +:104F300000200411000000000000000000600811C3 +:104F4000000001B20000225C0020441100000000BB +:104F5000000000030020481100000000000022565D +:104F600000204411000000000000001B0020481138 +:104F7000000000000000A1FC00204411000000001F +:104F80000000000100204811000000000001A1FD08 +:104F9000C0204411000000000000002100201E2D50 +:104FA000000000000000001000221E27000000008A +:104FB000000000240020222D000000000000FFFF60 +:104FC00000282228000000000000000000294907F6 +:104FD0000000000000000000002048110000000058 +:104FE000000000220020222D000000000000FFFF32 +:104FF00000282228000000000000000000294907C6 +:105000000000000000000000002048110000000027 +:105010000000002300201E2D0000000000000010F2 +:1050200000221E27000000000000000000294907A0 +:1050300000000000000000000040481100000000D7 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B0000142050205C002500000000001C3016860 +:1052C000043F05C000000000022502090250015100 +:1052D000000000000223024502A00241000000007D +:1052E00003D705C005C005C0000000000649064AF6 +:1052F000031F05C00000000005C005C503200340D2 +:1053000000000000032A0282034203340000000070 +:1053100005C005C005C005C00000000005C005515E +:1053200005C005C00000000003BA05C004BB03446B +:1053300000000000049A0450043D05C00000000075 +:1053400004D005C0044104DD00000000045005073E +:10535000035103750000000005C005C005C005C06D +:105360000000000005C005C005C005C00000000029 +:1053700005C005C0063F05C70000000005C005C008 +:10538000000705C00000000005C005C005C005C03D +:105390000000000005C005C005C005C000000000F9 +:1053A00003F803ED0408040600000000040E040ADC +:1053B000040C041000000000041C04180424042041 +:1053C00000000000042C0428043404300000000015 +:1053D00005C005C0043805C00000000005C005C0B8 +:1053E00005C005C00000000005C005C005C005C01F +:1053F0000000000000020679069700060000000089 +:00000001FF diff --git a/firmware/radeon/RV610_pfp.bin.ihex b/firmware/radeon/RV610_pfp.bin.ihex new file mode 100644 index 0000000..f55292c --- /dev/null +++ b/firmware/radeon/RV610_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000CA040000A00000007E828B007C038BED +:10001000008001B8007C038B00D4401E00EE001E5F +:1000200000CA040000A00000007E828B00C41838C3 +:1000300000CA240000CA2800009581A800C41C3A08 +:1000400000C3C00000CA080000CA0C00007C744B4A +:1000500000C200050099C00000C41C3A007C744C2A +:1000600000C0FFF000042C0400309002007D250049 +:1000700000351402007D350B00255403007CD5802B +:1000800000259C030095C00400D5001B007EDDC147 +:10009000007D9D8000D6801B00D5801B00D4401EB3 +:1000A00000D5401E00D6401E00D6801E00D4801E03 +:1000B00000D4C01E009783D300D5C01E00CA08001C +:1000C0000080001A00CA0C0000E4011E00D4001ECB +:1000D0000080000C00C4183800E4013E00D4001E6B +:1000E0000080000C00C4183800D4401E00EE001E32 +:1000F00000CA040000A00000007E828B00E4011E04 +:1001000000D4001E00D4401E00EE001E00CA0400F1 +:1001100000A00000007E828B00E4013E00D4001E9F +:1001200000D4401E00EE001E00CA040000A0000023 +:10013000007E828B00CA180000D4401E00D5801EAD +:100140000080005300D4007500D4401E00CA08008F +:1001500000CA0C0000CA100000D4801900D4C018D6 +:1001600000D5001700D4801E00D4C01E00D5001E8C +:1001700000E2001E00CA040000A00000007E828B86 +:1001800000CA080000D4806000D4401E0080000037 +:1001900000D4801E00CA080000D4806100D4401E34 +:1001A0000080000000D4801E00CA080000CA0C00B5 +:1001B00000D4401E00D4801600D4C01600D4801E87 +:1001C000008001B800D4C01E00C6084300CA0C005D +:1001D00000CA10000094800400CA140000E420F358 +:1001E00000D4201300D5606500D4E01C00D5201C8D +:1001F00000D5601C008000000006200100C60843F6 +:1002000000CA0C0000CA1000009483F700CA140052 +:1002100000E420F30080007900D4201300C60843D6 +:1002200000CA0C0000CA1000009883EF00CA140036 +:1002300000D400640080008D0000000000C414326F +:1002400000C6184300C4082F0095400500C40C30B8 +:1002500000D4401E0080000000EE001E009583F5D3 +:1002600000C4103100D4403300D5206500D4A01C58 +:1002700000D4E01C00D5201C00E4015E00D4001E68 +:10028000008000000006200100CA1800000A2001BA +:1002900000D6007600C408360098800700C61045D6 +:1002A0000095011000D4001F00D46062008000009F +:1002B00000D4206200CC383500CC1433008401BB5C +:1002C00000D4007200D5401E0080000000EE001E29 +:1002D00000E2001A008401BB00E2001A00CC104BBF +:1002E00000CC0447002C9401007D098B0098400548 +:1002F000007D15CB00D4001A008001B800D4006D39 +:100300000034440100CC0C480098403A00CC2C4A00 +:100310000095800400CC0449008001B800D4001A84 +:1003200000D4C01A00282801008400F000CC10037B +:100330000098801B0004380C008400F000CC1003EF +:100340000098801700043808008400F000CC1003E7 +:100350000098801300043804008400F000CC1003DF +:100360000098801400CC104C009A800900CC144DE9 +:10037000009840DC00D4006D00CC184800D5001A6D +:1003800000D5401A008000C900D5801A0096C0D55B +:1003900000D4006D008001B800D4006E009AC00344 +:1003A00000D4006D00D4006E0080000000EC007FDF +:1003B000009AC0CC00D4006D008001B800D4006E5B +:1003C00000CC140300CC180300CC1C03007D910367 +:1003D000007DD583007D190C0035CC1F0035701FC2 +:1003E000007CF0CB007CD08B00880000007E8E8BE0 +:1003F0000095C00400D4006E008001B800D4001A3B +:1004000000D4C01A00CC080300CC0C0300CC1003AD +:1004100000CC140300CC180300CC1C0300CC240334 +:1004200000CC28030035C41F0036B01F007C704B81 +:100430000034F01F007C704B0035701F007C704B47 +:10044000007D8881007DCCC1007E5101007E9541F8 +:10045000007C9082007CD4C2007C848B009AC00314 +:10046000007C8C8B002C88010098809E00D4006D4D +:100470000098409C00D4006E00CC084C00CC0C4D81 +:1004800000CC104800D4801A00D4C01A00800101AA +:1004900000D5001A00CC083200D40032009482D972 +:1004A00000CA0C0000D4401E0080000000D4001ED2 +:1004B00000E4011E00D4001E00CA080000CA0C009F +:1004C00000CA100000D4401E00CA140000D4801ED0 +:1004D00000D4C01E00D5001E00D5401E00D54034FB +:1004E0000080000000EE001E0028040400E2001A54 +:1004F00000E2001A00D4401A00CA380000CC0803F9 +:1005000000CC0C0300CC0C0300CC0C03009882BD83 +:1005100000000000008401BB00D7A06F0080000035 +:1005200000EE001F00CA040000C2FF0000CC083427 +:1005300000C13FFF007C74CB007CC90B007D010F24 +:10054000009902B0007C738B008401BB00D7A06FC0 +:100550000080000000EE001F00CA080000281900FB +:10056000007D898B009580140028140400CA0C00BB +:1005700000CA100000CA1C0000CA240000E2001FCC +:1005800000D4C01A00D5001A00D5401A00CC1803B8 +:1005900000CC2C0300CC2C0300CC2C03007DA58BBD +:1005A000007D9C4700984297000000000080016198 +:1005B00000D4C01A00D4401E00D4801E0080000069 +:1005C00000EE001E00E4011E00D4001E00D4401EF8 +:1005D00000EE001E00CA040000A00000007E828B16 +:1005E00000E4013E00D4001E00D4401E00EE001EB8 +:1005F00000CA040000A00000007E828B00CA080030 +:1006000000248C06000CCC060098C00600CC104ECE +:100610000099000400D4007300E4011E00D4001E01 +:1006200000D4401E00D4801E0080000000EE001E9A +:1006300000CA080000CA0C000034D01800251001C0 +:100640000095002100C17FFF00CA100000CA1400FD +:1006500000CA180000D4801D00D4C01D007DB18BDD +:1006600000C1420200C2C00100D5801D0034DC0E72 +:10067000007D5D4C007F734C00D7401E00D5001EEE +:1006800000D5401E00C1420000C2C00000099C010C +:100690000031DC10007F5F4C007F734C00042802A7 +:1006A000007D838000D5A86F00D5806600D7401EEE +:1006B00000EC005E00C8240200C82402008001B8DB +:1006C00000D6007600D4401E00D4801E00D4C01E88 +:1006D0000080000000EE001E0080000000EE001F01 +:1006E00000D4001F0080000000D4001F00D4001FB1 +:1006F0000088000000D4001F00000000000000007F +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000010171000201780003008F0004007FE5 +:10081000000500030006003F000700320008012C1D +:1008200000090046000A0036001001B6001700A2B9 +:100830000022013A00230149002000B400240125D0 +:100840000027004D0028006A002A0060002B00529B +:10085000002F0065003200870034017F003C015604 +:10086000003F00720041018C0044012E00550173CD +:100870000056017A0060000B00610034006200380D +:1008800000630038006400380065003800660038F6 +:10089000006700380068003A00690041006A0048BB +:1008A000006B0048006C0048006D0048006E004876 +:1008B000006F00480000000600000006000000066F +:1008C0000000000600000006000000060000000610 +:1008D0000000000600000006000000060000000600 +:1008E00000000006000000060000000600000006F0 +:1008F00000000006000000060000000600000006E0 +:00000001FF diff --git a/firmware/radeon/RV620_me.bin.ihex b/firmware/radeon/RV620_me.bin.ihex new file mode 100644 index 0000000..ba19ed8 --- /dev/null +++ b/firmware/radeon/RV620_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A000006044110000068D0000000000600000A8 +:1000B000000006310000000000600000000006455E +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E000000000000000001800203625000000007D +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000002800204A2D8B +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000001900203625C9 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001700200E2D5A +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001718 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000270020362410 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:10038000000000000000000E0020362300000000E6 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E23000000000000000FC9 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000002700204A2D000000004F +:1003F000000000000020481100000000000000295B +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A00000000000002048040000000000000030AF +:1005B0000020162D00000000000000020029162572 +:1005C0000000000000000030002036250000000080 +:1005D000000000250020162D000000000000000093 +:1005E000002F00A300000000000000000CC000006D +:1005F00000000083000000260020162D00000000EF +:1006000000000000002F00A4000000000000000017 +:100610000CC000000000008400000000004000004A +:100620000000008A000000250020362300000000A2 +:100630000000002600203624000000000000001703 +:1006400000201E2D000000000000000200210227F3 +:10065000000000000000000014E000000000008A1C +:1006600000000000006000000000066800000000BC +:10067000006000000000065C0000000200210E2265 +:10068000000000000000000014C000000000008D09 +:1006900000000012C040362000000093000000005F +:1006A0002EE0000000000091000000002CE000009F +:1006B000000000900000000200400E2D000000929B +:1006C0000000000300400E2D000000920000000C0E +:1006D00000200E2D00000000000000120020362334 +:1006E000000000000000000300210E2200000000B6 +:1006F0000000000014C00000000000980000A00CE2 +:10070000002044110000000000000000C02048004C +:100710000000000000000000C0404800000000A0F1 +:100720000000A00C002044110000000000000000A8 +:100730000020481100000000000000002EE0000032 +:100740000000009E000000002CE000000000009D62 +:100750000000000200400E2D0000009F000000037A +:1007600000400E2D0000009F0000000C00200E2D08 +:10077000000000000000000000204803000000000E +:1007800000000000003A0C0200000000003F0000E2 +:1007900000280E23000000000000001000210E239E +:1007A00000000000000000110020362300000000BF +:1007B0000000001E0021022B0000000000000000CD +:1007C00014C00000000000A700000016C020362062 +:1007D000000000000000001F0021022B00000000AC +:1007E0000000000014C00000000000AA0000001576 +:1007F000C0203620000000000000000800210E2B61 +:10080000000000000000007F00280E230000000010 +:1008100000000000002F0223000000000000000084 +:100820000CE00000000000E10000000027000000D4 +:10083000000000000000000000600000000002A3B3 +:1008400000000001002F0223000000000000000053 +:100850000AE00000000000B300000000006000009B +:100860000000013A81000000002044110000000057 +:100870000000000600204811000000000000000CED +:1008800000221E300000000099800000002044116A +:1008900000000000000000040020122D00000000F5 +:1008A00000000008002212240000000000000010D8 +:1008B00000201811000000000000000000291CE4C6 +:1008C0000000000000000000006048070000012F49 +:1008D0009B00000000204411000000000000000008 +:1008E00000204802000000009C000000002044118D +:1008F00000000000000000000033146F0000000042 +:100900000000000100333E23000000000000000052 +:10091000D9004800000000000000000000203C0555 +:1009200000000000810000000020441100000000D1 +:100930000000000E00204811000000000000000030 +:1009400000201010000000000000E007002044110B +:10095000000000000000000F0021022B000000003A +:100960000000000014C00000000000CB00F8FF08E9 +:1009700000204811000000009800000000404811CD +:10098000000000DC000000F000280E220000000043 +:10099000000000A0002F0223000000000000000063 +:1009A0000CC00000000000DA0000001100200E2D35 +:1009B0000000000000000001002F022300000000E2 +:1009C000000000000CE00000000000D50000000264 +:1009D000002F022300000000000000000CE00000D7 +:1009E000000000D400003F0000400C11000000D6C1 +:1009F00000001F0000400C11000000D600000F0096 +:100A000000200C11000000000038000900294A23D2 +:100A1000000000003F00000000280E2B0000000036 +:100A20000000000200220E2300000000000000076A +:100A300000494A23000000DC00380F09002048115B +:100A400000000000680000070020481100000000BE +:100A50000000000800214A270000000000000000FC +:100A60000020481100000000060A020000294A2464 +:100A700000000000000000000020481100000000FD +:100A80000000000000204811000000000000A20249 +:100A9000002044110000000000FF000000280E228A +:100AA000000000000000008000294A230000000030 +:100AB0000000002700200E2D00000000000000268E +:100AC0000020122D0000000000000000002F008315 +:100AD00000000000000000000CE00000000000EA40 +:100AE000000000000060000000000662000000003E +:100AF00000400000000000EB00000000006000006B +:100B000000000665000000070020222D0000000004 +:100B10000000000500220E2200000000001000006E +:100B200000280E23000000000000000000292068BB +:100B30000000000000000000003A0C02000000006D +:100B4000000000EF00280E2300000000000000005D +:100B500000292068000000000000001700200E2D72 +:100B6000000000000000000300210223000000003C +:100B70000000000014E00000000000F80000000B7E +:100B800000210228000000000000000014C0000046 +:100B9000000000F8000004000029222800000000E6 +:100BA0000000001400203628000000000000001C97 +:100BB00000210E22000000000000000014C0000010 +:100BC000000000FD0000A30C002044110000000004 +:100BD0000000000000204811000000000000001E7E +:100BE00000210E22000000000000000014C00000E0 +:100BF0000000010B0000A30F0020441100000000C2 +:100C00000000001100200E2D000000000000000177 +:100C1000002F022300000000000000000CC00000B4 +:100C200000000104FFFFFFFF004048110000010B1E +:100C300000000002002F022300000000000000005E +:100C40000CC00000000001070000FFFF0040481139 +:100C50000000010B00000004002F02230000000030 +:100C6000000000000CC000000000010A000000FFAE +:100C7000004048110000010B000000010020481155 +:100C8000000000000002C400002044110000000029 +:100C90000000001F00210E220000000000000000E4 +:100CA00014C00000000001120000001040210E20BE +:100CB00000000000000000130020362300000000A8 +:100CC0000000001840224A20000000000000001030 +:100CD000C0424A20000001140000000000200C1156 +:100CE0000000000000000013002036230000000078 +:100CF000000000000020481100000000000000007B +:100D000000204811000000000000000A002010111F +:100D10000000000000000000002F0224000000007E +:100D2000000000000CE000000000011B00000000BB +:100D300000204811000000000000000100531224B0 +:100D400000000117FFBFFFFF00283A2E000000003F +:100D50000000001B00210222000000000000000033 +:100D600014C000000000012E81000000002044118A +:100D7000000000000000000D0020481100000000ED +:100D80000000001800220E3000000000FC000000EF +:100D900000280E2300000000810000000020441104 +:100DA000000000000000000E0020481100000000BC +:100DB0000000000000201010000000000000E00E05 +:100DC000002044110000000007F8FF08002048112F +:100DD000000000000000000000294A23000000007D +:100DE0000000001C00201E2D000000000000000874 +:100DF00000214A27000000000000000000204811E8 +:100E000000000000060A020000294A240000000039 +:100E10000000000000204811000000000000000059 +:100E200000204811000000000000000000800000C9 +:100E300000000000810000000020441100000000BC +:100E40000000000100204811000000000000217C8B +:100E50000020441100000000008000000020481124 +:100E60000000000000000000002048060000000014 +:100E70000000000800214A270000000000000000D8 +:100E800017000000000000000004217F00604411F2 +:100E90000000068D0000001F00210230000000004D +:100EA0000000000014C000000000068C00000004D8 +:100EB00000404C1100000135810000000020441169 +:100EC00000000000000000010020481100000000A8 +:100ED000000021F800204411000000000000001C68 +:100EE0000020481100000000000421F900604411B6 +:100EF0000000068D000000110021023000000000FB +:100F00000000000014E000000000013C00000000B0 +:100F100000800000000000000000000000600000F1 +:100F20000000000B00000000006004110000031529 +:100F3000000000000020041100000000000000007C +:100F400000600811000001B2000000000060000015 +:100F5000000001600000FFFF40280E20000000009C +:100F600000000010C0211220000000000000FFFF60 +:100F7000402806200000000000000010C0210A20C8 +:100F800000000000000000000034146100000000B8 +:100F90000000000000741882000002BB0001A1FDE7 +:100FA00000604411000002E000003FFF002F022F0C +:100FB00000000000000000000CC00000000001471D +:100FC00000000000C040040000000001000000001C +:100FD000006000000000000B000000000060041131 +:100FE00000000315000000000020041100000000B4 +:100FF0000000000000600811000001B200003FFF87 +:10100000002F022F00000000000000000CE0000094 +:10101000000000000000000000600000000001600F +:101020000000001040210E20000000000000FFFF23 +:10103000C0281220000000000000001040211620EF +:10104000000000000000FFFFC0681A20000002BB83 +:101050000001A1FD00604411000002E000003FFF1C +:10106000002F022F00000000000000000CC0000054 +:101070000000015800000000C04004000000000112 +:101080000000225C0020441100000000000000016C +:1010900000300A2F000000000000000100210A2299 +:1010A000000000000000000300384A220000000099 +:1010B0000000225600204411000000000000001A29 +:1010C00000204811000000000000A1FC0020441195 +:1010D0000000000000000001008048110000000036 +:1010E00000000000006000000000000B0000000095 +:1010F000006000000000018F0000000000600000A0 +:10110000000001A000003FFF002F022F00000000A0 +:10111000000000000CE000000000000000000000E3 +:1011200000202C0800000000000000000020241116 +:101130000000000000000000002028110000000056 +:10114000000022560020441100000000000000169C +:1011500000204811000000000000225C0020441123 +:101160000000000000000003002048110000000003 +:1011700093800000002044110000000000000002E5 +:1011800000221E290000000000000000007048EB53 +:101190000000019C0000000000600000000002BB95 +:1011A00000000001403306200000000000000000A5 +:1011B000C03024090000000000003FFF002F022F74 +:1011C00000000000000000000CE000000000000033 +:1011D0000000000000600000000002A3000000000A +:1011E000002F022100000000000000000AE00000C3 +:1011F0000000018100000000006000000000013AD2 +:101200000000000000400000000001869500000082 +:10121000002044110000000000000000002F022107 +:1012200000000000000000000CE00000000001864B +:1012300000000000C0204800000000000000000185 +:10124000005306210000018292000000002044119A +:101250000000000000000000C0604800000001978E +:101260000001A1FD00204411000000000000001159 +:101270000020062D00000000000000000078042A75 +:10128000000002FB00000000002028090000000010 +:1012900000003FFF002F022F0000000000000000B0 +:1012A0000CC000000000017400000000C0400400F9 +:1012B000000000010000021000600411000003158E +:1012C00000003FFF002F022F000000000000000080 +:1012D0000CE000000000019400000015C020362042 +:1012E0000000000000000016C020362000000000B2 +:1012F0003F800000002004110000000046000000B4 +:1013000000600811000001B2000000000080000031 +:10131000000000000000A1FC0020441100000000BB +:1013200000003FFF002F022F00000000000000001F +:101330000CC000000000019B00000001008048116B +:1013400000000000000000210080481100000000A3 +:101350000000FFFF40280E200000000000000010E9 +:10136000C0211220000000000000FFFF40281620CE +:101370000000000000000010C0811A2000000000E2 +:101380008100000000204411000000000000000661 +:1013900000204811000000000000000800221E305C +:1013A000000000000000002900201A2D00000000AD +:1013B0000000E0000020441100000000FFFBFF09D6 +:1013C00000204811000000000000000F0020222D26 +:1013D0000000000000001FFF00294A280000000054 +:1013E000000000060020222D000000000000000088 +:1013F000002920E80000000000000000002048084C +:101400000000000000000000002048110000000063 +:10141000060A020000294A26000000000000000021 +:1014200000204811000000000000000000204811CA +:101430000000000000000100002018110000000062 +:101440000000000800621E280000012F00000008B4 +:1014500000822228000000000002C0000020441189 +:10146000000000000000001500600E2D000001BD0E +:101470000000001600600E2D000001BD0000C00835 +:1014800000204411000000000000001700200E2D75 +:10149000000000000000000014C00000000001B9BE +:1014A0000000000000200411000000000000000007 +:1014B0000020480100000000390000000020481111 +:1014C00000000000000000000020481100000000A3 +:1014D000000000000080480200000000000000182A +:1014E00000202E2D0000000000000000003B0D63D6 +:1014F000000000000000000800224A230000000055 +:101500000000001000224A23000000000000001824 +:1015100000224A2300000000000000000080480371 +:101520000000000000000000006000000000000B50 +:10153000000010000060041100000315000000000E +:1015400000200411000000000000000000600811ED +:10155000000001B2000000070021062F000000007B +:101560000000001300200A2D000000000000000110 +:1015700000202C11000000000000FFFF4028222066 +:10158000000000000000000F0026222800000000DC +:101590000000001040212620000000000000000F85 +:1015A000002626290000000000000000002028027C +:1015B000000000000000225600204411000000003E +:1015C0000000001B00204811000000000000000087 +:1015D000002F022100000000000000000CE00000CD +:1015E000000001E00000225C002044110000000027 +:1015F0000000008100204811000000000000A1FC54 +:1016000000204411000000000000000100204811EB +:10161000000000000000008000201C1100000000FD +:1016200000000000002F0227000000000000000062 +:101630000CE00000000001DC000000000060000081 +:10164000000001E90000000100531E27000001D83E +:101650000000000100202C11000000000000001F0D +:1016600000280A22000000000000001F00282A2A8B +:10167000000000000000000100530621000001D11D +:101680000000225C00204411000000000000000265 +:1016900000304A2F000000000000A1FC002044118F +:1016A00000000000000000010020481100000000C0 +:1016B0000000000100301E2F0000000000000000AC +:1016C000002F022700000000000000000CE00000D6 +:1016D000000000000000000000600000000001E9C0 +:1016E0000000000100531E27000001E50000FFFF7D +:1016F00040280E20000000000000000F00260E23EE +:101700000000000000000010C021122000000000B6 +:101710000000000F0026122400000000000000005E +:1017200000201411000000000000000000601811EB +:10173000000002BB0001A1FD0020441100000000D8 +:1017400000000000002F022B00000000000000003D +:101750000CE00000000001F8000000100022162834 +:1017600000000000FFFF0000002816250000000018 +:101770000000FFFF00281A29000000000000000000 +:10178000002948C500000000000000000020480AB1 +:10179000000000000000000000202C1100000000EC +:1017A000000000100022162300000000FFFF0000D0 +:1017B00000281625000000000000FFFF00281A2462 +:1017C0000000000000000000002948C500000000E3 +:1017D0000000000000731503000002050000000077 +:1017E0000020180500000000000000000073152410 +:1017F0000000020500000000002D14C500000000DC +:1018000000000000003008A20000000000000000FE +:101810000020480200000000000000000020280214 +:101820000000000000000000002020030000000075 +:101830000000000000802404000000000000000FF1 +:1018400000210225000000000000000014C000007C +:101850000000068C00000000002B140500000000B2 +:1018600000000001009016250000000000000000AC +:10187000006000000000000B000000000060041188 +:10188000000003150000000000200411000000000B +:101890000000000000600811000001B200002256A4 +:1018A00000204411000000000000001A00294A2214 +:1018B0000000000000000000C02000000000000048 +:1018C00000003FFF002F022F00000000000000007A +:1018D0000CE000000000000000000000C020040038 +:1018E000000000000000225C002044110000000005 +:1018F0000000000300384A21000000000000A1FCA5 +:1019000000204411000000000000000100204811E8 +:10191000000000000000FFFF40281220000000002F +:1019200000000010C0211A20000000000000FFFF8E +:1019300040280E200000000000000010C0211620EA +:10194000000000000000000000741465000002BBED +:101950000001A1FD00604411000002E00000000150 +:10196000003306210000000000000000002F0221CB +:1019700000000000000000000CC000000000021980 +:1019800000003FFF002F022F0000000000000000B9 +:101990000CC000000000021200000000C040040063 +:1019A000000000010000000000600000000006458B +:1019B000000000000040040F0000021300000000BF +:1019C0000060000000000631000000000060000020 +:1019D000000006450000021000600411000003151D +:1019E0000000000000600000000001A000000000F6 +:1019F000006000000000019C00000000006000008A +:101A0000000002BB0000000000600000000002A314 +:101A1000938000000020441100000000000000003E +:101A2000002048080000000000000000002F022FE6 +:101A300000000000000000000AE000000000023288 +:101A400000000000006000000000013A00000000FB +:101A50000040000000000236950000000020441104 +:101A60000000000000000000002F022F0000000016 +:101A7000000000000CE00000000002360000000042 +:101A8000C0404800000002339200000000204411D2 +:101A90000000000000000000C0204800000000001E +:101AA0000000225600204411000000000000001633 +:101AB00000204811000000000000225C00204411BA +:101AC000000000000000000300204811000000009A +:101AD0000000A1FC002044110000000000000001F3 +:101AE00000204811000000000001A1FD0020441169 +:101AF000000000000000000000600411000002FB74 +:101B000000000000C04004000000000100000000D0 +:101B100000600000000006310000A00C002044110D +:101B20000000000000000000C0204800000000008D +:101B300000000000C040480000000000000000005D +:101B4000006000000000000B0000001840210A2087 +:101B50000000000000000003002F0222000000002F +:101B6000000000000AE000000000024C0000001429 +:101B70000020222D00000000000801010029222879 +:101B800000000000000000140020362800000000C3 +:101B90000000A30C00204411000000000000000021 +:101BA000C02048000000000000000000C0204800E5 +:101BB0000000000000000000C0404800000002518A +:101BC00000000000006000000000000B000000109A +:101BD00000600411000003153F8000000020041184 +:101BE000000000000000000000600811000001B2C9 +:101BF0000000225C002044110000000000000003EF +:101C000000204811000000000000000000600000FB +:101C10000000027C0000001700201E2D00000000C4 +:101C20000000000100211E2700000000000000004D +:101C300014E000000000026A0000001200201E2DC7 +:101C4000000000000000FFFF00281E270000000029 +:101C50000000000000341C2700000000000000000D +:101C600012C000000000025F0000000000201C11F4 +:101C70000000000000000000002F00E50000000050 +:101C80000000000008C00000000002620000000028 +:101C900000201407000000000000001200201E2D8C +:101CA000000000000000001000211E2700000000BE +:101CB0000000000000341C4700000000000000008D +:101CC00012C00000000002670000000000201C118C +:101CD0000000000000000000002F00E600000000EF +:101CE0000000000008C000000000026A00000000C0 +:101CF0000020180700000000000000000060000045 +:101D0000000002C100002256002044110000000023 +:101D1000000000000034202300000000000000004C +:101D200012C00000000002720000000000342044D5 +:101D3000000000000000000012C00000000002715E +:101D40000000001600404811000002760000001854 +:101D500000404811000002760000000000342044DA +:101D6000000000000000000012C00000000002752A +:101D70000000001700404811000002760000001922 +:101D800000204811000000000000A1FC00204411C8 +:101D900000000000000000010020481100000000C9 +:101DA0000001A1FD00604411000002E900003FFFB6 +:101DB000002F022F00000000000000000CC00000F7 +:101DC0000000025600000000C040040000000001B6 +:101DD0000000001040210620000000000000FFFF6E +:101DE000C0280A20000000000000001040210E2042 +:101DF000000000000000FFFFC028122000000000CB +:101E00000000001040211620000000000000FFFF2D +:101E1000C0881A200000000081000000002044114A +:101E20000000000000000001002048110000000038 +:101E300000042004006044110000068D0000000032 +:101E4000006000000000063100000000C0600000DB +:101E5000000002A30000000500200A2D0000000081 +:101E60000000000800220A22000000000000002BF1 +:101E700000201A2D000000000000001C00201E2D74 +:101E8000000000000000700000281E270000000075 +:101E90000000000000311CE6000000000000002AE5 +:101EA00000201A2D000000000000000C00221A265D +:101EB0000000000000000000002F00E6000000000D +:101EC0000000000006E00000000002920000000098 +:101ED00000201C11000000000000000000200C1178 +:101EE000000000000000002B00203623000000004E +:101EF0000000001000201811000000000000000089 +:101F000000691CE20000012F9380000000204411B2 +:101F10000000000000000000002048070000000052 +:101F200095000000002044110000000000000000A7 +:101F3000002F022F00000000000000000CE0000055 +:101F40000000029D0000000100333E2F0000000051 +:101F500000000000D90048000000000092000000CE +:101F6000002044110000000000000000C0204800D4 +:101F7000000000000000001C0040362700000000A8 +:101F80000000000CC0220A20000000000000002910 +:101F9000002036220000000000000028C04036204B +:101FA000000000000000A2A4002044110000000076 +:101FB000000000090020481100000000A1000000FE +:101FC00000204411000000000000000100804811C2 +:101FD000000000000000002100201E2D0000000075 +:101FE00000000000002C1CE30000000000000021A5 +:101FF00000203627000000000000002200201E2DD7 +:102000000000000000000000002C1CE400000000A4 +:1020100000000022002036270000000000000023FE +:1020200000201E2D0000000000000000003120A351 +:102030000000000000000000002D1D07000000004F +:1020400000000023002036270000000000000024CC +:1020500000201E2D0000000000000000003120C400 +:102060000000000000000000002D1D07000000001F +:10207000000000240080362700000000000000213E +:10208000002036230000000000000022002036243B +:10209000000000000000000000311CA30000000050 +:1020A0000000002300203627000000000000000090 +:1020B00000311CC40000000000000024008036270E +:1020C000000000000000001A002036270000000079 +:1020D0000000001B00203628000000000000001750 +:1020E00000201E2D00000000000000020021022739 +:1020F000000000000000000014C00000000002DC2E +:102100000000000000400000000002D90000001A9A +:1021100000203627000000000000001B00203628A9 +:10212000000000000000001700201E2D000000002D +:102130000000000200210227000000000000000053 +:1021400014E00000000002D9000000030021022773 +:10215000000000000000000014E00000000002DCAD +:102160000000002300201E2D0000000000000000E1 +:10217000002E00E1000000000000000002C000008E +:10218000000002DC0000002100201E2D00000000E5 +:1021900000000000003120A100000000000000004D +:1021A000002E00E8000000000000000006C0000053 +:1021B000000002DC0000002400201E2D00000000B2 +:1021C00000000000002E00E20000000000000000FF +:1021D00002C00000000002DC0000002200201E2DD2 +:1021E0000000000000000000003120C200000000DC +:1021F00000000000002E00E80000000000000000C9 +:1022000006C00000000002DC0000000000600000CA +:10221000000006680000000000600000000002B539 +:102220000000000000400000000002DE000000008E +:1022300000600000000002B5000000000060000027 +:102240000000065F0000000000400000000002DE09 +:102250000000000000600000000002A70000000075 +:1022600000400000000002DE0000001A00201E2DC9 +:10227000000000000000001B0080222D0000000074 +:102280000000001000221E230000000000000000DB +:1022900000294887000000000000000000311CA356 +:1022A000000000000000001000221E2700000000B7 +:1022B0000000000000294887000000000000001016 +:1022C00000221E230000000000000000003120C496 +:1022D000000000000000FFFF00282228000000008E +:1022E0000000000000894907000000000000001005 +:1022F00000221E2300000000000000000029488783 +:10230000000000000000001000221E21000000005C +:102310000000000000294847000000000000000005 +:1023200000311CA3000000000000001000221E2746 +:1023300000000000000000000029488700000000A5 +:102340000000000000311CA100000000000000108F +:1023500000221E270000000000000000002948475E +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:10239000000000000000001000221E2100000000CC +:1023A00000000000003120C2000000000000FFFF1C +:1023B00000282228000000000000000000894907D2 +:1023C000000000000000001000221E23000000009A +:1023D0000000000000294887000000000000000104 +:1023E00000220A210000000000000000003308A2C3 +:1023F000000000000000001000221E22000000006B +:102400000000001000212222000000000000000057 +:1024100000294907000000000000000000311CA353 +:10242000000000000000001000221E270000000035 +:1024300000000000002948870000000000000001A3 +:1024400000220A210000000000000000003008A265 +:10245000000000000000001000221E22000000000A +:1024600000000010002122220000000000000000F7 +:1024700000294907000000000000001000221E2370 +:102480000000000000000000003120C40000000037 +:102490000000FFFF002822280000000000000000CC +:1024A000002949070000000000000000003808C5AE +:1024B00000000000000000000030084100000000A3 +:1024C0000000000100220A220000000000000000BD +:1024D000003308A2000000000000001000221E22AD +:1024E0000000000000000010002122220000000077 +:1024F00000000000008949070000000000000017EC +:102500000020222D000000000000000014C0000088 +:1025100000000318FFFFFFEF002806210000000065 +:10252000000000140020222D000000000000F8E050 +:1025300000204411000000000000000000294901B3 +:1025400000000000000000000089490100000000B8 +:102550000000000000204811000000000000000002 +:102560000020481100000000060A02000080481107 +:102570000000000000000000C0200000000000007B +:1025800097000000C020441100000000000000007F +:10259000C0204811000000008A0000000020441103 +:1025A00000000000000000000020481100000000B2 +:1025B0000000225C00204411000000000000000028 +:1025C000C0204800000000000000A1FC00204411D1 +:1025D0000000000000000000C020480000000000D3 +:1025E00000000000C0200400000000000000000007 +:1025F00000A0000A00000000970000000020441125 +:102600000000000000000000002048110000000051 +:102610008A000000002044110000000000000000BB +:1026200000204811000000000000225C002044113E +:102630000000000000000000C02048000000000072 +:102640000000A1FC00204411000000000000000078 +:10265000C02048000000000000000000C02004006E +:10266000000000000000000000A0000A00000000C0 +:10267000970000000020441100000000000000004E +:1026800000204811000000008A00000000204411D2 +:1026900000000000000000000020481100000000C1 +:1026A0000000225C00204411000000000000000037 +:1026B000C0204800000000000000A1FC00204411E0 +:1026C0000000000000000000C020480000000000E2 +:1026D0000001A1FD002044110000000000000000E6 +:1026E000D90048000000000000000000C0200400E5 +:1026F000000000000000000000A0000A0000000030 +:1027000000002257002044110000000000000003D8 +:10271000C0484A20000000000000225D0020441153 +:102720000000000000000000C04048000000000061 +:1027300000000000006000000000064500000000EE +:10274000C0200800000000000000225C00204411AE +:10275000000000000000000300384A2200000000D2 +:102760000000A1FC00204411000000000000000057 +:10277000C0204800000000000001A1FD002044111D +:102780000000000000000000002F022200000000F6 +:10279000000000000CE0000000000000000000004D +:1027A00040204800000000000000000140304A20A6 +:1027B0000000000000000002C0304A2000000000BD +:1027C0000000000100530A220000034B0000003FFC +:1027D000C0280A20000000008100000000204411F1 +:1027E000000000000000000100204811000000006F +:1027F000000021F800204411000000000000001833 +:102800000020481100000000000421F9006044117C +:102810000000068D000000110021023000000000C1 +:102820000000000014E00000000003540000001449 +:10283000002F022200000000000000000CC0000079 +:10284000000003640000201000204411000000007C +:102850000000800000204811000000000001A2A438 +:102860000020441100000000000000000060480249 +:102870000000036E00002100002044110000000051 +:1028800000000000C0204800000000000000000020 +:10289000C02048000000000000000000C0204800E8 +:1028A0000000000000000000C040480000000000E0 +:1028B00000000004002F02220000000000000000C1 +:1028C0000CC000000000036A00002010002044112A +:1028D00000000000000080000020481100000000FF +:1028E0000001A2A40020441100000000000000002C +:1028F000004048020000035F00000028002F022271 +:1029000000000000000000000CC00000000005C036 +:102910000001A2A4002044110000000000000000FB +:10292000004048020000035F0000002C0020362613 +:102930000000000000000049002018110000000005 +:102940000000003F002048110000000000000001CE +:1029500000331A260000000000000000002F0226AD +:1029600000000000000000000CC000000000037028 +:102970000000002C00801A2D000000000000003F25 +:10298000C0280A200000000000000015002F0222CD +:1029900000000000000000000CE0000000000386C2 +:1029A00000000006002F02220000000000000000CE +:1029B0000CE00000000003B100000016002F02220E +:1029C00000000000000000000CE00000000003B563 +:1029D00000000020002F0222000000000000000084 +:1029E0000CE000000000039C0000000F002F0222FA +:1029F00000000000000000000CE00000000003A840 +:102A000000000010002F0222000000000000000063 +:102A10000CE00000000003A80000001E002F0222AE +:102A200000000000000000000CE000000000039027 +:102A30000000A2A4002044110000000000000000DB +:102A400000404802000000000800000000290A229F +:102A5000000000000000000340210E2000000000E4 +:102A60000000000CC021122000000000000800003F +:102A7000002812240000000000000014C0221620CC +:102A80000000000000000000002914A40000000065 +:102A90000000A2A40020441100000000000000007B +:102AA000002948A2000000000000A1FE00204411FF +:102AB000000000000000000000404803000000008B +:102AC000810000000020441100000000000000010F +:102AD0000020481100000000000021F800204411EF +:102AE0000000000000000016002048110000000057 +:102AF000000421F9006044110000068D000000155B +:102B000000210230000000000000000014E000007E +:102B1000000003920000210E00204411000000007C +:102B200000000000C020480000000000000000007D +:102B3000C0204800000000000000A2A400204411B2 +:102B400000000000000000000040480200000000FB +:102B5000810000000020441100000000000000017E +:102B60000020481100000000000021F8002044115E +:102B700000000000000000170020481100000000C5 +:102B8000000421F9006044110000068D00000003DC +:102B900000210230000000000000000014E00000EE +:102BA0000000039E000021080020441100000000E6 +:102BB00000000000C02048000000000000000000ED +:102BC000C0204800000000000000A2A40020441122 +:102BD000000000000000000000404802000000006B +:102BE0000000A2A40020441100000000000000002A +:102BF0000020480200000000800000000020441176 +:102C0000000000000000000000204811000000004B +:102C100081000000002044110000000000000010AE +:102C200000204811000000000000000000200010FB +:102C3000000000000000000014C00000000003AE0F +:102C40000000000000400000000000000000201014 +:102C50000020441100000000000080000020481106 +:102C6000000000000001A2A40020441100000000A8 +:102C70000000000600404811000000000000201085 +:102C800000204411000000000000800000204811D6 +:102C9000000000000001A2A4002044110000000078 +:102CA00000000016006048110000036E00000000E4 +:102CB000004000000000000000000000C0200800EC +:102CC0000000000000000000C0200C000000000018 +:102CD0000000001D00210223000000000000000091 +:102CE00014E00000000003CE810000000020441129 +:102CF000000000000000000100204811000000005A +:102D0000000021F80020441100000000000000181D +:102D10000020481100000000000421F90060441167 +:102D20000000068D000000110021023000000000AC +:102D30000000000014E00000000003C000002100BB +:102D400000204411000000000000000000204802A4 +:102D50000000000000000000002048030000000008 +:102D6000BABECAFE0020481100000000CAFEBABE6A +:102D70000020481100000000000020100020441135 +:102D8000000000000000800000204811000000004A +:102D90000000A2A400204411000000000000000474 +:102DA0000040481100000000000021700020441184 +:102DB00000000000000000000020480200000000A9 +:102DC0000000000000204803000000008100000017 +:102DD00000204411000000000000000A00204811FB +:102DE00000000000000000000020001000000000B3 +:102DF0000000000014C00000000003D38C0000009D +:102E00000020441100000000CAFEBABE0040481174 +:102E100000000000810000000020441100000000BC +:102E200000000001002048110000000000003FFFEA +:102E300040280A20000000008000000040280E20EA +:102E40000000000040000000C02812200000000028 +:102E500000040000006946220000068D000000000A +:102E6000002014100000000000000000002F0223CA +:102E700000000000000000000CC00000000003E1A2 +:102E800000000000C0401800000003E400003FFF05 +:102E9000C0281A2000000000000400000069462637 +:102EA0000000068D00000000002018100000000047 +:102EB00000000000002F02240000000000000000BD +:102EC0000CC00000000003E700000000C0401C0030 +:102ED000000003EA00003FFFC0281E2000000000A1 +:102EE00000040000006946270000068D0000000075 +:102EF00000201C1000000000000000000020440220 +:102F00000000000000000000002820C500000000B4 +:102F100000000000004948E800000000A580000013 +:102F200000200811000000000000200000200C110B +:102F30000000000083000000006044110000041243 +:102F4000000000000020440200000000000000001B +:102F5000C0204800000000000000000040204800A1 +:102F6000000000000000001FC0210220000000003F +:102F70000000000014C00000000003F70000201053 +:102F800000204411000000000000800000204811D3 +:102F9000000000000000FFFFC0481220000003FFF7 +:102FA000A780000000200811000000000000A00021 +:102FB00000200C110000000083000000006044119C +:102FC0000000041200000000002044020000000085 +:102FD00000000000C02048000000000000000000C9 +:102FE000C0204800000000000000FFFFC0281220A1 +:102FF00000000000830000000020441100000000D9 +:103000000000000000304883000000008400000041 +:10301000002044110000000000000000C020480013 +:1030200000000000000000001D0000000000000083 +:103030008300000000604411000004120000000042 +:10304000C040040000000001A98000000020081119 +:10305000000000000000C00000400C11000003FA56 +:10306000AB80000000200811000000000000F8E024 +:1030700000400C11000003FAAD8000000020081190 +:10308000000000000000F88000400C11000003FA6E +:10309000B380000000200811000000000000F3FCD5 +:1030A00000400C11000003FAAF800000002008115E +:1030B000000000000000E00000400C11000003FAD6 +:1030C000B180000000200811000000000000F000A6 +:1030D00000400C11000003FA83000000002044119E +:1030E00000000000000021480020481100000000FE +:1030F00084000000002044110000000000000000D7 +:10310000C020480000000000000000001D0000007A +:10311000000000000000000000800000000000002F +:1031200001182000C0304620000000000000000010 +:10313000D90048000000000000000000C02004008A +:10314000000000000000000000A0000A00000000D5 +:103150000218A000C030462000000000000000005F +:10316000D90048000000000000000000C02004005A +:10317000000000000000000000A0000A00000000A5 +:103180000318C000C030462000000000000000000E +:10319000D90048000000000000000000C02004002A +:1031A000000000000000000000A0000A0000000075 +:1031B0000418F8E0C03046200000000000000000C5 +:1031C000D90048000000000000000000C0200400FA +:1031D000000000000000000000A0000A0000000045 +:1031E0000518F880C03046200000000000000000F4 +:1031F000D90048000000000000000000C0200400CA +:10320000000000000000000000A0000A0000000014 +:103210000618E000C030462000000000000000005A +:10322000D90048000000000000000000C020040099 +:10323000000000000000000000A0000A00000000E4 +:103240000718F000C0304620000000000000000019 +:10325000D90048000000000000000000C020040069 +:10326000000000000000000000A0000A00000000B4 +:103270000818F3FCC03046200000000000000000E9 +:10328000D90048000000000000000000C020040039 +:10329000000000000000000000A0000A0000000084 +:1032A0000000003000200A2D000000000000000097 +:1032B000C0290C4000000000000000300020362330 +:1032C0000000000000000000C0200400000000001A +:1032D0000000000000A0000A0000000086000000BE +:1032E00000204411000000000000000000404801E0 +:1032F0000000000085000000C02044110000000014 +:103300000000000000404801000000000000217C97 +:10331000002044110000000000000018402102209D +:10332000000000000000000014C000000000044580 +:1033300000800000C0494A20000004460000000050 +:10334000C02048000000000000000000C02048002D +:103350000000000000000000C02048000000000045 +:103360008100000000204411000000000000000166 +:10337000002048110000000000000000C0200800EC +:103380000000000000000000170000000000000026 +:103390000004217F006044110000068D0000001F22 +:1033A00000210230000000000000000014C00000F6 +:1033B000000000000000000000404C020000044B30 +:1033C00000000000C0200C00000000000000000011 +:1033D000C02010000000000000000000C020140009 +:1033E0000000000000000000C020180000000000E5 +:1033F00000000000C0201C000000000000007F0052 +:1034000000280A210000000000004500002F0222D1 +:1034100000000000000000000CE000000000045963 +:1034200000000000C020200000000000000000009C +:1034300017000000000000000000001000280A2310 +:103440000000000000000010002F02220000000019 +:10345000000000000CE0000000000461810000009A +:10346000002044110000000000000001002048116D +:103470000000000000040000006946240000068DE2 +:103480000000000000400000000004668100000011 +:10349000002044110000000000000000002048113E +:1034A000000000000000216D002044110000000019 +:1034B00000000000002048040000000000000000A0 +:1034C000006048050000069200000000002824F07B +:1034D000000000000000000700280A230000000090 +:1034E00000000001002F0222000000000000000088 +:1034F0000AE000000000046D00000000002F00C979 +:10350000000000000000000004E00000000004864D +:1035100000000000004000000000049300000002D2 +:10352000002F022200000000000000000AE000005E +:103530000000047200000000002F00C9000000001D +:103540000000000002E0000000000486000000000F +:10355000004000000000049300000003002F02223E +:1035600000000000000000000AE0000000000477F6 +:1035700000000000002F00C9000000000000000053 +:103580000CE0000000000486000000000040000085 +:103590000000049300000004002F0222000000003D +:1035A000000000000AE000000000047C00000000B1 +:1035B000002F00C900000000000000000AE0000029 +:1035C000000004860000000000400000000004939A +:1035D00000000005002F0222000000000000000093 +:1035E0000AE000000000048100000000002F00C974 +:1035F000000000000000000006E00000000004865B +:1036000000000000004000000000049300000006DD +:10361000002F022200000000000000000AE000006D +:103620000000048600000000002F00C90000000018 +:103630000000000008E00000000004860000000018 +:10364000004000000000049300007F0000280A21D1 +:103650000000000000004500002F022200000000D2 +:10366000000000000AE00000000000000000000868 +:1036700000210A23000000000000000014C0000028 +:1036800000000490000021690020441100000000A7 +:1036900000000000C0204800000000000000000002 +:1036A000C02048000000000000000000C0204800CA +:1036B00000000000CAFEBABE004048110000000031 +:1036C00000000000C02044000000000000000000D6 +:1036D000C02000000000000000000000C0404800C2 +:1036E0000000000000007F0000280A210000000008 +:1036F00000004500002F0222000000000000000032 +:103700000AE000000000049900000000C020000052 +:103710000000000000000000C020000000000000C9 +:1037200000000000C0400000000000000000000099 +:1037300000404C080000045900000000C0200800B0 +:10374000000000000000001040210E2000000000DA +:1037500000000011402112200000000000000012B3 +:1037600040211620000000000000216900204411C3 +:1037700000000000000000000020480200000000DF +:1037800000000000002102250000000000000000F1 +:1037900014E00000000004A300040000C0494A2017 +:1037A000000004A4FFFBFFFFC0284A200000000027 +:1037B00000000000002102230000000000000000C3 +:1037C00014E00000000004B000000000C020480029 +:1037D0000000000000000000C020480000000000C1 +:1037E0000000000000210224000000000000000092 +:1037F00014C00000000000008100000000204411FF +:10380000000000000000000C002048110000000033 +:103810000000000000200010000000000000000078 +:1038200014C00000000004ACA000000000204411FF +:1038300000000000CAFEBABE0040481100000000AF +:10384000810000000020441100000000000000047E +:1038500000204811000000000000216B00204411EE +:103860000000000000000000C02048100000000020 +:10387000810000000020441100000000000000054D +:1038800000204811000000000000216C00204411BD +:103890000000000000000000C020481000000000F0 +:1038A00000000000002F02240000000000000000C3 +:1038B0000CE00000000000000000000000400000DC +:1038C000000004AA00000000C0210A20000000003F +:1038D0000000000014C00000000004C381000000CC +:1038E00000204411000000000000000000204811EA +:1038F000000000000000216D0020441100000000C5 +:1039000000000000C020480000000000000000008F +:10391000C060480000000692000000000040000067 +:10392000000004C7810000000020441100000000D6 +:103930000000000100204811000000000004000009 +:10394000C02946200000000000000000C060000008 +:103950000000068D0000000100210222000000008E +:103960000000000014C00000000004CE0000216927 +:10397000002044110000000000000000C0204800AA +:103980000000000000000000C0204800000000000F +:10399000000000000020481000000000CAFEBABE6F +:1039A000004048110000000000000000C02044005A +:1039B0000000000000000000C040481000000000AF +:1039C0008100000000204411000000000000000100 +:1039D0000020481100000000000021F800204411E0 +:1039E000000000000000000E002048110000000050 +:1039F000000421F9006044110000068D0000000061 +:103A000000210230000000000000000014C000008F +:103A1000000004D0000021800020441100000000BC +:103A200000000000C020480000000000000000006E +:103A3000C02000000000000000000000C02048007E +:103A40000000000000000000C02000000000000096 +:103A500000000000C040480000000000000000031B +:103A600000333E2F00000000000000010021022171 +:103A7000000000000000000014E00000000005004D +:103A80000000002C00200A2D0000000000040000AF +:103A900018E00C11000004EF0000000100333E2F7D +:103AA0000000000000002169002044110000000017 +:103AB000000000000020480200000000000000009C +:103AC00000204803000000000000000800300A2227 +:103AD0000000000000000000C020480000000000BE +:103AE00000000000C0204800000000000000216924 +:103AF00000204411000000000000000000204802E7 +:103B0000000000000000000000204803000000004A +:103B10000000000800300A22000000000000000041 +:103B2000C02048000000000000000000D8C048008D +:103B3000000004E30000216900204411000000009F +:103B4000000000000020480200000000000000000B +:103B500000204803000000000000000800300A2296 +:103B60000000000000000000C0204800000000002D +:103B700000000000C0204800000000000000002DF0 +:103B80000020122D000000000000000000290C831E +:103B90000000000000002169002044110000000026 +:103BA00000000000002048020000000000000000AB +:103BB00000204803000000000000000800300A2236 +:103BC0000000000000000000C020480000000000CD +:103BD00000000000C02048000000000000000011AC +:103BE00000210224000000000000000014C00000BA +:103BF000000000000000000000400000000004AAD7 +:103C00000000002CC0203620000000000000002D25 +:103C1000C0403620000000000000000F00210221FB +:103C2000000000000000000014C0000000000505B6 +:103C300000000000006000000000000B0000000019 +:103C4000D90000000000000000000000C040040097 +:103C500000000001B5000000002044110000000039 +:103C6000000020000020481100000000B600000005 +:103C700000204411000000000000A00000204811B6 +:103C800000000000B7000000002044110000000008 +:103C90000000C0000020481100000000B800000033 +:103CA00000204411000000000000F8E0002048114E +:103CB00000000000B90000000020441100000000D6 +:103CC0000000F8800020481100000000BA00000049 +:103CD00000204411000000000000E0000020481116 +:103CE00000000000BB0000000020441100000000A4 +:103CF0000000F0000020481100000000BC0000009F +:103D000000204411000000000000F3FC00204811D6 +:103D100000000000810000000020441100000000AD +:103D2000000000020020481100000000000000FF19 +:103D300000280E300000000000000000002F0223C9 +:103D400000000000000000000CC000000000051989 +:103D500000000000C020080000000000000000007B +:103D600014C000000000052E0000000000200C110F +:103D7000000000000000001C0020362300000000AE +:103D80000000002B00203623000000000000002966 +:103D90000020362300000000000000280020362309 +:103DA0000000000000000017002036230000000083 +:103DB000000000250020362300000000000000263F +:103DC00000203623000000000000001500203623EC +:103DD0000000000000000016002036230000000054 +:103DE000FFFFE00000200C11000000000000002197 +:103DF00000203623000000000000002200203623AF +:103E00000000000000001FFF00200C110000000057 +:103E100000000023002036230000000000000024E2 +:103E20000020362300000000F1FFFFFF00283A2E9B +:103E3000000000000000001AC0220E200000000058 +:103E4000000000000029386E000000008100000022 +:103E5000002044110000000000000006002048116E +:103E6000000000000000002A402036200000000072 +:103E70008700000000204411000000000000000046 +:103E8000C0204800000000000000A1F40020441100 +:103E900000000000000000000020481000000000AA +:103EA0000000000000200C110000000000000030A5 +:103EB00000203623000000009D0000000020441177 +:103EC000000000000000001F40214A200000000008 +:103ED00096000000002044110000000000000000D7 +:103EE000C02048000000000000000000C0200C00BE +:103EF0000000000000000000C020100000000000D2 +:103F00000000001F00211624000000000000000037 +:103F100014C00000000000000000001D0020362337 +:103F2000000000000000000300281E230000000025 +:103F3000000000080022222300000000FFFFF00024 +:103F4000002822280000000000000000002920E8CE +:103F5000000000000000001F0020362800000000C4 +:103F60000000001800211E230000000000000020B7 +:103F70000020362700000000000000020022162466 +:103F80000000000000000000003014A80000000045 +:103F90000000001E00203625000000000000000385 +:103FA00000211A24000000001000000000281A263A +:103FB00000000000EFFFFFFF00283A2E0000000085 +:103FC00000000000004938CE0000067B0000000120 +:103FD00040280A20000000000000000640280E20B3 +:103FE0000000000000000300C028122000000000B4 +:103FF0000000000800211224000000000000000062 +:10400000C02016200000000000000000C0201A2080 +:10401000000000000000000000210222000000005B +:104020000000000014C000000000056681000000D0 +:104030000020441100000000000000010020481191 +:10404000000000000000225800300A240000000098 +:1040500000040000006946220000068D000021696E +:10406000002044110000000000000000002048056E +:10407000000000000002000000294A2600000000A5 +:10408000000000000020481000000000CAFEBABE78 +:10409000002048110000000000000002002F022351 +:1040A00000000000000000000CC000000000056ED1 +:1040B00000000000C0201C100000000000000000F4 +:1040C000C04000000000057C00000002002F022319 +:1040D00000000000000000000CC000000000056EA1 +:1040E00081000000002044110000000000000001D9 +:1040F00000204811000000000000225800300A246F +:104100000000000000040000006946220000068D47 +:1041100000000000C0201C10000000000000000093 +:10412000C04000000000057C00000000002F0223BA +:1041300000000000000000000CC00000000005723C +:1041400000000000C0201C00000000000000000073 +:10415000C04000000000057C00000004002F022386 +:1041600000000000000000000CC000000000057A04 +:104170008100000000204411000000000000000049 +:1041800000204811000000000000216D00204411B3 +:104190000000000000000000C020480000000000F7 +:1041A00000000000C060480000000692000000000F +:1041B00000401C100000057C00000000C020000032 +:1041C0000000000000000000C040000000000000EF +:1041D000000000000EE000000000057E000000006E +:1041E00000600000000005C900000000002F02244C +:1041F00000000000000000000CC000000000058F5F +:104200000000A2B7002044110000000000000000E0 +:104210000020480700000000810000000020441139 +:104220000000000000000001002048110000000014 +:104230000004A2B6006044110000068D0000001AC0 +:10424000002122300000000000000006002226307D +:104250000000000000042004006044110000068DEE +:104260000000A2C400204411000000000000000073 +:10427000003048E9000000000000000000E00000FD +:104280000000058D0000A2D10020441100000000B4 +:104290000000000000404808000000000000A2D11B +:1042A00000204411000000000000000100504A28D6 +:1042B0000000000000000001002F022400000000A8 +:1042C000000000000CC00000000005A00000A2BB20 +:1042D00000204411000000000000000000204807FA +:1042E00000000000810000000020441100000000D8 +:1042F0000000000100204811000000000004A2BAE4 +:10430000006044110000068D0000001A00212230D8 +:10431000000000000000000600222630000000001F +:1043200000042004006044110000068D0000A2C5B6 +:10433000002044110000000000000000003048E9A7 +:10434000000000000000000000E000000000059EEA +:104350000000A2D200204411000000000000000074 +:1043600000404808000000000000A2D200204411D4 +:10437000000000000000000100504A28000000007A +:1043800000000002002F02240000000000000000D6 +:104390000CC00000000005B10000A2BF00204411C5 +:1043A000000000000000000000204807000000009E +:1043B0008100000000204411000000000000000106 +:1043C00000204811000000000004A2BE006044115B +:1043D0000000068D0000001A0021223000000000BD +:1043E0000000000600222630000000000004200427 +:1043F000006044110000068D0000A2C60020441198 +:104400000000000000000000003048E9000000004B +:104410000000000000E00000000005AF0000A2D393 +:104420000020441100000000000000000040480887 +:10443000000000000000A2D3002044110000000092 +:104440000000000100504A28000000000000A2C344 +:104450000020441100000000000000000020480778 +:104460000000000081000000002044110000000056 +:104470000000000100204811000000000004A2C25A +:10448000006044110000068D0000001A0021223057 +:10449000000000000000000600222630000000009E +:1044A00000042004006044110000068D0000A2C733 +:1044B000002044110000000000000000003048E926 +:1044C000000000000000000000E00000000005BE49 +:1044D0000000A2D4002044110000000000000000F1 +:1044E00000404808000000000000A2D40020441151 +:1044F000000000000000000100504A2800000000F9 +:1045000085000000002044110000000000000000B1 +:1045100000204801000000000000304A0020441143 +:104520000000000001000000002048110000000011 +:104530000000000000400000000005C4A4000000CE +:10454000C02044110000000000000000C0404800EE +:104550000000000000000000C0600000000005C96D +:1045600000000000C0400400000000010000002C1A +:1045700000203621000000008100000000204411CE +:1045800000000000000000060020481100000000AC +:1045900000000000002F02300000000000000000BA +:1045A0000CC00000000005D0000000000020041135 +:1045B000000000000000003000403621000005E34C +:1045C000000000300020062D0000000000007E00EA +:1045D000002806210000000000000000002F02213A +:1045E00000000000000000000CE00000000005E3F7 +:1045F00081000000002044110000000000000001C4 +:1046000000204811000000000004A0920060441146 +:104610000000068D00000031002036300000000050 +:104620000004A093006044110000068D00000032D9 +:1046300000203630000000000004A2B600604411E3 +:104640000000068D0000003300203630000000001E +:104650000004A2BA006044110000068D000000347E +:1046600000203630000000000004A2BE00604411AB +:104670000000068D000000350020363000000000EC +:104680000004A2C2006044110000068D0000003644 +:1046900000203630000000000004200400604411B7 +:1046A0000000068D0001A2A40020441100000000BB +:1046B0000000003F00204811000000000000003F03 +:1046C00000204811000000000000003F00204811B9 +:1046D000000000000000003F002048110000000022 +:1046E0000000000500204811000000000000A1F4B7 +:1046F00000204411000000000000000000204811CC +:1047000000000000880000000020441100000000AC +:10471000000000010020481100000000810000009E +:104720000020441100000000000000060020481195 +:104730000000000000000001002F02300000000017 +:10474000000000000CE000000000062C000000301B +:104750000020062D0000000000000000002F0221B4 +:1047600000000000000000000CE000000000062C2B +:104770008100000000204411000000000000000142 +:10478000002048110000000000007E0000280621E3 +:104790000000000000000000002F022100000000C7 +:1047A000000000000CE00000000006050000A092E0 +:1047B00000204411000000000000003100204A2DBC +:1047C000000000000000A093002044110000000041 +:1047D0000000003200204A2D000000000000A2B6B8 +:1047E00000204411000000000000003300204A2D8A +:1047F000000000000000A2BA0020441100000000E8 +:104800000000003400204A2D000000000000A2BE7D +:1048100000204411000000000000003500204A2D57 +:10482000000000000000A2C20020441100000000AF +:104830000000003600204A2D00000000000000307B +:104840000020062D00000000000001FF00280621C6 +:104850000000000000000000002F02210000000006 +:10486000000000000CE000000000062B000000002B +:1048700000210221000000000000000014C0000020 +:104880000000060E0004A003006044110000068D25 +:104890000000A00300204411000000000000000000 +:1048A0000020481000000000000000010021062147 +:1048B000000000000000000014C00000000006130B +:1048C0000004A010006044110000068D0000A0103C +:1048D00000204411000000000000000000204810EB +:1048E000000000000000000100210621000000007F +:1048F00000000000002F0221000000000000000066 +:104900000CE000000000062B0004A0110060441120 +:104910000000068D0000A0110020441100000000DE +:104920000000000000204810000000000004A01259 +:10493000006044110000068D0000A0120020441108 +:1049400000000000000000000020481000000000EF +:104950000004A013006044110000068D0000A013A5 +:10496000002044110000000000000000002048105A +:10497000000000000004A014006044110000068D37 +:104980000000A014002044110000000000000000FE +:1049900000204810000000000004A0150060441131 +:1049A0000000068D0000A01500204411000000004A +:1049B0000000000000204810000000000004A016C5 +:1049C000006044110000068D0000A0160020441174 +:1049D000000000000000000000204810000000005F +:1049E0000004A017006044110000068D0000A0170D +:1049F00000204411000000000000000000204810CA +:104A00000000000000042004006044110000068D36 +:104A10000000002C0080062D00000000FF000000B8 +:104A20000020441100000000000000000020481198 +:104A300000000000000000010020481100000000FC +:104A4000000000020080481100000000000000008B +:104A50000EE000000000063D000000300020062DA2 +:104A600000000000000000020028062100000000F5 +:104A700000000000002F02210000000000000000E4 +:104A80000CE000000000063B810000000020441103 +:104A9000000000000000000100204811000000009C +:104AA00000042004006044110000068D0000100086 +:104AB00000200811000000000000002B002036221A +:104AC000000000000000000000600000000006413F +:104AD0000000000000600000000005C99800000010 +:104AE0000020441100000000000000000080481178 +:104AF0000000000000000000C0600000000006414F +:104B000000000000C0400400000000010000A2A45A +:104B10000020441100000000000000220020481185 +:104B20000000000089000000002044110000000087 +:104B300000000001004048110000062D9700000011 +:104B40000020441100000000000000000020481177 +:104B5000000000008A000000002044110000000056 +:104B600000000000004048110000062D0000000079 +:104B7000006000000000065C0000201000204411CE +:104B8000000000000000800000204811000000002C +:104B90000001A2A4C0204411000000000000001683 +:104BA000006048110000036E000020100020441136 +:104BB000000000000001000000204811000000007B +:104BC00081000000002044110000000000000001EE +:104BD00000204811000000000000217C002044114A +:104BE00000000000098000000020481100000000C3 +:104BF000FFFFFFFF00204811000000000000000040 +:104C00000020481100000000000000001700000014 +:104C1000000000000004217F006044110000068DA8 +:104C20000000001F00210230000000000000000012 +:104C300014C00000000000000000000400404C11FF +:104C400000000656000000000040000000000000C8 +:104C50000000001700201E2D0000000000000004CE +:104C600000291E27000000000000001700803627E2 +:104C7000000000000000001700201E2D00000000B2 +:104C8000FFFFFFFB00281E270000000000000017A8 +:104C900000803627000000000000001700201E2DB5 +:104CA000000000000000000800291E27000000008E +:104CB00000000017008036270000000000000017E9 +:104CC00000201E2D00000000FFFFFFF700281E2718 +:104CD00000000000000000170080362700000000E0 +:104CE000000020100020441100000000000080009F +:104CF00000204811000000000001A2A4002044117F +:104D00000000000000000016006048110000036E63 +:104D100000002010002044110000000000010000ED +:104D200000204811000000000000217C00204411F8 +:104D30000000000001800000002048110000000079 +:104D4000FFFFFFFF002048110000000000000000EE +:104D500000204811000000000000000017000000C3 +:104D6000000000008100000000204411000000004D +:104D70000000000100204811000000000004217F15 +:104D8000006044110000068D0000001F0021023069 +:104D9000000000000000000014C000000000068CAD +:104DA0000000001000404C110000067200000000DE +:104DB000C0200400000000000000000038C0000017 +:104DC000000000000000001D00200A2D000000006F +:104DD0000000001E00200E2D000000000000001F3B +:104DE0000020122D00000000000000200020162DE1 +:104DF00000000000000021690020441100000000B4 +:104E00000000000000204804000000000000000036 +:104E100000204805000000000000000000204801BC +:104E200000000000CAFEBABE0020481100000000C9 +:104E30000000000400301224000000000000000008 +:104E4000002F006400000000000000000CC0000003 +:104E50000000068B0000000300281A22000000005A +:104E6000000000080022122200000000FFFFF000F6 +:104E7000002812240000000000000000002910C4D7 +:104E8000000000000000001F004036240000000069 +:104E90000000000000800000000000000000000092 +:104EA0001AC000000000068D9F0000000020441181 +:104EB00000000000CAFEBABE002048110000000039 +:104EC000000000001AE00000000006900000000052 +:104ED0000080000000000000000000001AC0000078 +:104EE000000006929E000000002044110000000017 +:104EF000CAFEBABE002048110000000000000000F9 +:104F00001AE000000000069500000000008000008C +:104F10000000000000000000006000000000000B26 +:104F200000001000006004110000031500000000E4 +:104F300000200411000000000000000000600811C3 +:104F4000000001B20000225C0020441100000000BB +:104F5000000000030020481100000000000022565D +:104F600000204411000000000000001B0020481138 +:104F7000000000000000A1FC00204411000000001F +:104F80000000000100204811000000000001A1FD08 +:104F9000C0204411000000000000002100201E2D50 +:104FA000000000000000001000221E27000000008A +:104FB000000000240020222D000000000000FFFF60 +:104FC00000282228000000000000000000294907F6 +:104FD0000000000000000000002048110000000058 +:104FE000000000220020222D000000000000FFFF32 +:104FF00000282228000000000000000000294907C6 +:105000000000000000000000002048110000000027 +:105010000000002300201E2D0000000000000010F2 +:1050200000221E27000000000000000000294907A0 +:1050300000000000000000000040481100000000D7 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B0000142050205C002500000000001C3016860 +:1052C000043F05C000000000022502090250015100 +:1052D000000000000223024502A00241000000007D +:1052E00003D705C005C005C0000000000649064AF6 +:1052F000031F05C00000000005C005C503200340D2 +:1053000000000000032A0282034203340000000070 +:1053100005C005C005C005C00000000005C005515E +:1053200005C005C00000000003BA05C004BB03446B +:1053300000000000049A0450043D05C00000000075 +:1053400004D005C0044104DD00000000045005073E +:10535000035103750000000005C005C005C005C06D +:105360000000000005C005C005C005C00000000029 +:1053700005C005C0063F05C70000000005C005C008 +:10538000000705C00000000005C005C005C005C03D +:105390000000000005C005C005C005C000000000F9 +:1053A00003F803ED0408040600000000040E040ADC +:1053B000040C041000000000041C04180424042041 +:1053C00000000000042C0428043404300000000015 +:1053D00005C005C0043805C00000000005C005C0B8 +:1053E00005C005C00000000005C005C005C005C01F +:1053F0000000000000020679069700060000000089 +:00000001FF diff --git a/firmware/radeon/RV620_pfp.bin.ihex b/firmware/radeon/RV620_pfp.bin.ihex new file mode 100644 index 0000000..f55292c --- /dev/null +++ b/firmware/radeon/RV620_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000CA040000A00000007E828B007C038BED +:10001000008001B8007C038B00D4401E00EE001E5F +:1000200000CA040000A00000007E828B00C41838C3 +:1000300000CA240000CA2800009581A800C41C3A08 +:1000400000C3C00000CA080000CA0C00007C744B4A +:1000500000C200050099C00000C41C3A007C744C2A +:1000600000C0FFF000042C0400309002007D250049 +:1000700000351402007D350B00255403007CD5802B +:1000800000259C030095C00400D5001B007EDDC147 +:10009000007D9D8000D6801B00D5801B00D4401EB3 +:1000A00000D5401E00D6401E00D6801E00D4801E03 +:1000B00000D4C01E009783D300D5C01E00CA08001C +:1000C0000080001A00CA0C0000E4011E00D4001ECB +:1000D0000080000C00C4183800E4013E00D4001E6B +:1000E0000080000C00C4183800D4401E00EE001E32 +:1000F00000CA040000A00000007E828B00E4011E04 +:1001000000D4001E00D4401E00EE001E00CA0400F1 +:1001100000A00000007E828B00E4013E00D4001E9F +:1001200000D4401E00EE001E00CA040000A0000023 +:10013000007E828B00CA180000D4401E00D5801EAD +:100140000080005300D4007500D4401E00CA08008F +:1001500000CA0C0000CA100000D4801900D4C018D6 +:1001600000D5001700D4801E00D4C01E00D5001E8C +:1001700000E2001E00CA040000A00000007E828B86 +:1001800000CA080000D4806000D4401E0080000037 +:1001900000D4801E00CA080000D4806100D4401E34 +:1001A0000080000000D4801E00CA080000CA0C00B5 +:1001B00000D4401E00D4801600D4C01600D4801E87 +:1001C000008001B800D4C01E00C6084300CA0C005D +:1001D00000CA10000094800400CA140000E420F358 +:1001E00000D4201300D5606500D4E01C00D5201C8D +:1001F00000D5601C008000000006200100C60843F6 +:1002000000CA0C0000CA1000009483F700CA140052 +:1002100000E420F30080007900D4201300C60843D6 +:1002200000CA0C0000CA1000009883EF00CA140036 +:1002300000D400640080008D0000000000C414326F +:1002400000C6184300C4082F0095400500C40C30B8 +:1002500000D4401E0080000000EE001E009583F5D3 +:1002600000C4103100D4403300D5206500D4A01C58 +:1002700000D4E01C00D5201C00E4015E00D4001E68 +:10028000008000000006200100CA1800000A2001BA +:1002900000D6007600C408360098800700C61045D6 +:1002A0000095011000D4001F00D46062008000009F +:1002B00000D4206200CC383500CC1433008401BB5C +:1002C00000D4007200D5401E0080000000EE001E29 +:1002D00000E2001A008401BB00E2001A00CC104BBF +:1002E00000CC0447002C9401007D098B0098400548 +:1002F000007D15CB00D4001A008001B800D4006D39 +:100300000034440100CC0C480098403A00CC2C4A00 +:100310000095800400CC0449008001B800D4001A84 +:1003200000D4C01A00282801008400F000CC10037B +:100330000098801B0004380C008400F000CC1003EF +:100340000098801700043808008400F000CC1003E7 +:100350000098801300043804008400F000CC1003DF +:100360000098801400CC104C009A800900CC144DE9 +:10037000009840DC00D4006D00CC184800D5001A6D +:1003800000D5401A008000C900D5801A0096C0D55B +:1003900000D4006D008001B800D4006E009AC00344 +:1003A00000D4006D00D4006E0080000000EC007FDF +:1003B000009AC0CC00D4006D008001B800D4006E5B +:1003C00000CC140300CC180300CC1C03007D910367 +:1003D000007DD583007D190C0035CC1F0035701FC2 +:1003E000007CF0CB007CD08B00880000007E8E8BE0 +:1003F0000095C00400D4006E008001B800D4001A3B +:1004000000D4C01A00CC080300CC0C0300CC1003AD +:1004100000CC140300CC180300CC1C0300CC240334 +:1004200000CC28030035C41F0036B01F007C704B81 +:100430000034F01F007C704B0035701F007C704B47 +:10044000007D8881007DCCC1007E5101007E9541F8 +:10045000007C9082007CD4C2007C848B009AC00314 +:10046000007C8C8B002C88010098809E00D4006D4D +:100470000098409C00D4006E00CC084C00CC0C4D81 +:1004800000CC104800D4801A00D4C01A00800101AA +:1004900000D5001A00CC083200D40032009482D972 +:1004A00000CA0C0000D4401E0080000000D4001ED2 +:1004B00000E4011E00D4001E00CA080000CA0C009F +:1004C00000CA100000D4401E00CA140000D4801ED0 +:1004D00000D4C01E00D5001E00D5401E00D54034FB +:1004E0000080000000EE001E0028040400E2001A54 +:1004F00000E2001A00D4401A00CA380000CC0803F9 +:1005000000CC0C0300CC0C0300CC0C03009882BD83 +:1005100000000000008401BB00D7A06F0080000035 +:1005200000EE001F00CA040000C2FF0000CC083427 +:1005300000C13FFF007C74CB007CC90B007D010F24 +:10054000009902B0007C738B008401BB00D7A06FC0 +:100550000080000000EE001F00CA080000281900FB +:10056000007D898B009580140028140400CA0C00BB +:1005700000CA100000CA1C0000CA240000E2001FCC +:1005800000D4C01A00D5001A00D5401A00CC1803B8 +:1005900000CC2C0300CC2C0300CC2C03007DA58BBD +:1005A000007D9C4700984297000000000080016198 +:1005B00000D4C01A00D4401E00D4801E0080000069 +:1005C00000EE001E00E4011E00D4001E00D4401EF8 +:1005D00000EE001E00CA040000A00000007E828B16 +:1005E00000E4013E00D4001E00D4401E00EE001EB8 +:1005F00000CA040000A00000007E828B00CA080030 +:1006000000248C06000CCC060098C00600CC104ECE +:100610000099000400D4007300E4011E00D4001E01 +:1006200000D4401E00D4801E0080000000EE001E9A +:1006300000CA080000CA0C000034D01800251001C0 +:100640000095002100C17FFF00CA100000CA1400FD +:1006500000CA180000D4801D00D4C01D007DB18BDD +:1006600000C1420200C2C00100D5801D0034DC0E72 +:10067000007D5D4C007F734C00D7401E00D5001EEE +:1006800000D5401E00C1420000C2C00000099C010C +:100690000031DC10007F5F4C007F734C00042802A7 +:1006A000007D838000D5A86F00D5806600D7401EEE +:1006B00000EC005E00C8240200C82402008001B8DB +:1006C00000D6007600D4401E00D4801E00D4C01E88 +:1006D0000080000000EE001E0080000000EE001F01 +:1006E00000D4001F0080000000D4001F00D4001FB1 +:1006F0000088000000D4001F00000000000000007F +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000010171000201780003008F0004007FE5 +:10081000000500030006003F000700320008012C1D +:1008200000090046000A0036001001B6001700A2B9 +:100830000022013A00230149002000B400240125D0 +:100840000027004D0028006A002A0060002B00529B +:10085000002F0065003200870034017F003C015604 +:10086000003F00720041018C0044012E00550173CD +:100870000056017A0060000B00610034006200380D +:1008800000630038006400380065003800660038F6 +:10089000006700380068003A00690041006A0048BB +:1008A000006B0048006C0048006D0048006E004876 +:1008B000006F00480000000600000006000000066F +:1008C0000000000600000006000000060000000610 +:1008D0000000000600000006000000060000000600 +:1008E00000000006000000060000000600000006F0 +:1008F00000000006000000060000000600000006E0 +:00000001FF diff --git a/firmware/radeon/RV630_me.bin.ihex b/firmware/radeon/RV630_me.bin.ihex new file mode 100644 index 0000000..ba3a7e6 --- /dev/null +++ b/firmware/radeon/RV630_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A000006044110000068A0000000000600000AB +:1000B0000000062E00000000006000000000064264 +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E000000000000000001800203625000000007D +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000002800204A2D8B +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000001900203625C9 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001700200E2D5A +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001718 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000270020362410 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:10038000000000000000000E0020362300000000E6 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E23000000000000000FC9 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000002700204A2D000000004F +:1003F000000000000020481100000000000000295B +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A00000000000002048040000000000000030AF +:1005B0000020162D00000000000000020029162572 +:1005C0000000000000000030002036250000000080 +:1005D000000000250020162D000000000000000093 +:1005E000002F00A300000000000000000CC000006D +:1005F00000000083000000260020162D00000000EF +:1006000000000000002F00A4000000000000000017 +:100610000CC000000000008400000000004000004A +:100620000000008A000000250020362300000000A2 +:100630000000002600203624000000000000001703 +:1006400000201E2D000000000000000200210227F3 +:10065000000000000000000014E000000000008A1C +:1006600000000000006000000000066500000000BF +:1006700000600000000006590000000200210E2268 +:10068000000000000000000014C000000000008D09 +:1006900000000012C040362000000093000000005F +:1006A0002EE0000000000091000000002CE000009F +:1006B000000000900000000200400E2D000000929B +:1006C0000000000300400E2D000000920000000C0E +:1006D00000200E2D00000000000000120020362334 +:1006E000000000000000000300210E2200000000B6 +:1006F0000000000014C00000000000980000A00CE2 +:10070000002044110000000000000000C02048004C +:100710000000000000000000C0404800000000A0F1 +:100720000000A00C002044110000000000000000A8 +:100730000020481100000000000000002EE0000032 +:100740000000009E000000002CE000000000009D62 +:100750000000000200400E2D0000009F000000037A +:1007600000400E2D0000009F0000000C00200E2D08 +:10077000000000000000000000204803000000000E +:1007800000000000003A0C0200000000003F0000E2 +:1007900000280E23000000000000001000210E239E +:1007A00000000000000000110020362300000000BF +:1007B0000000001E0021022B0000000000000000CD +:1007C00014C00000000000A700000016C020362062 +:1007D000000000000000001F0021022B00000000AC +:1007E0000000000014C00000000000AA0000001576 +:1007F000C0203620000000000000000800210E2B61 +:10080000000000000000007F00280E230000000010 +:1008100000000000002F0223000000000000000084 +:100820000CE00000000000E10000000027000000D4 +:10083000000000000000000000600000000002A3B3 +:1008400000000001002F0223000000000000000053 +:100850000AE00000000000B300000000006000009B +:100860000000013A81000000002044110000000057 +:100870000000000600204811000000000000000CED +:1008800000221E300000000099800000002044116A +:1008900000000000000000040020122D00000000F5 +:1008A00000000008002212240000000000000010D8 +:1008B00000201811000000000000000000291CE4C6 +:1008C0000000000000000000006048070000012F49 +:1008D0009B00000000204411000000000000000008 +:1008E00000204802000000009C000000002044118D +:1008F00000000000000000000033146F0000000042 +:100900000000000100333E23000000000000000052 +:10091000D9004800000000000000000000203C0555 +:1009200000000000810000000020441100000000D1 +:100930000000000E00204811000000000000000030 +:1009400000201010000000000000E007002044110B +:10095000000000000000000F0021022B000000003A +:100960000000000014C00000000000CB00F8FF08E9 +:1009700000204811000000009800000000404811CD +:10098000000000DC000000F000280E220000000043 +:10099000000000A0002F0223000000000000000063 +:1009A0000CC00000000000DA0000001100200E2D35 +:1009B0000000000000000001002F022300000000E2 +:1009C000000000000CE00000000000D50000000264 +:1009D000002F022300000000000000000CE00000D7 +:1009E000000000D400003F0000400C11000000D6C1 +:1009F00000001F0000400C11000000D600000F0096 +:100A000000200C11000000000038000900294A23D2 +:100A1000000000003F00000000280E2B0000000036 +:100A20000000000200220E2300000000000000076A +:100A300000494A23000000DC00380F09002048115B +:100A400000000000680000070020481100000000BE +:100A50000000000800214A270000000000000000FC +:100A60000020481100000000060A020000294A2464 +:100A700000000000000000000020481100000000FD +:100A80000000000000204811000000000000A20249 +:100A9000002044110000000000FF000000280E228A +:100AA000000000000000008000294A230000000030 +:100AB0000000002700200E2D00000000000000268E +:100AC0000020122D0000000000000000002F008315 +:100AD00000000000000000000CE00000000000EA40 +:100AE00000000000006000000000065F0000000041 +:100AF00000400000000000EB00000000006000006B +:100B000000000662000000070020222D0000000007 +:100B10000000000500220E2200000000001000006E +:100B200000280E23000000000000000000292068BB +:100B30000000000000000000003A0C02000000006D +:100B4000000000EF00280E2300000000000000005D +:100B500000292068000000000000001700200E2D72 +:100B6000000000000000000300210223000000003C +:100B70000000000014E00000000000F80000000B7E +:100B800000210228000000000000000014C0000046 +:100B9000000000F8000004000029222800000000E6 +:100BA0000000001400203628000000000000001C97 +:100BB00000210E22000000000000000014C0000010 +:100BC000000000FD0000A30C002044110000000004 +:100BD0000000000000204811000000000000001E7E +:100BE00000210E22000000000000000014C00000E0 +:100BF0000000010B0000A30F0020441100000000C2 +:100C00000000001100200E2D000000000000000177 +:100C1000002F022300000000000000000CC00000B4 +:100C200000000104FFFFFFFF004048110000010B1E +:100C300000000002002F022300000000000000005E +:100C40000CC00000000001070000FFFF0040481139 +:100C50000000010B00000004002F02230000000030 +:100C6000000000000CC000000000010A000000FFAE +:100C7000004048110000010B000000010020481155 +:100C8000000000000002C400002044110000000029 +:100C90000000001F00210E220000000000000000E4 +:100CA00014C00000000001120000001040210E20BE +:100CB00000000000000000130020362300000000A8 +:100CC0000000001840224A20000000000000001030 +:100CD000C0424A20000001140000000000200C1156 +:100CE0000000000000000013002036230000000078 +:100CF000000000000020481100000000000000007B +:100D000000204811000000000000000A002010111F +:100D10000000000000000000002F0224000000007E +:100D2000000000000CE000000000011B00000000BB +:100D300000204811000000000000000100531224B0 +:100D400000000117FFBFFFFF00283A2E000000003F +:100D50000000001B00210222000000000000000033 +:100D600014C000000000012E81000000002044118A +:100D7000000000000000000D0020481100000000ED +:100D80000000001800220E3000000000FC000000EF +:100D900000280E2300000000810000000020441104 +:100DA000000000000000000E0020481100000000BC +:100DB0000000000000201010000000000000E00E05 +:100DC000002044110000000007F8FF08002048112F +:100DD000000000000000000000294A23000000007D +:100DE0000000001C00201E2D000000000000000874 +:100DF00000214A27000000000000000000204811E8 +:100E000000000000060A020000294A240000000039 +:100E10000000000000204811000000000000000059 +:100E200000204811000000000000000000800000C9 +:100E300000000000810000000020441100000000BC +:100E40000000000100204811000000000000217C8B +:100E50000020441100000000008000000020481124 +:100E60000000000000000000002048060000000014 +:100E70000000000800214A270000000000000000D8 +:100E800017000000000000000004217F00604411F2 +:100E90000000068A0000001F002102300000000050 +:100EA0000000000014C000000000068900000004DB +:100EB00000404C1100000135810000000020441169 +:100EC00000000000000000010020481100000000A8 +:100ED000000021F800204411000000000000001C68 +:100EE0000020481100000000000421F900604411B6 +:100EF0000000068A000000110021023000000000FE +:100F00000000000014E000000000013C00000000B0 +:100F100000800000000000000000000000600000F1 +:100F20000000000B00000000006004110000031529 +:100F3000000000000020041100000000000000007C +:100F400000600811000001B2000000000060000015 +:100F5000000001600000FFFF40280E20000000009C +:100F600000000010C0211220000000000000FFFF60 +:100F7000402806200000000000000010C0210A20C8 +:100F800000000000000000000034146100000000B8 +:100F90000000000000741882000002BB0001A1FDE7 +:100FA00000604411000002E000003FFF002F022F0C +:100FB00000000000000000000CC00000000001471D +:100FC00000000000C040040000000001000000001C +:100FD000006000000000000B000000000060041131 +:100FE00000000315000000000020041100000000B4 +:100FF0000000000000600811000001B200003FFF87 +:10100000002F022F00000000000000000CE0000094 +:10101000000000000000000000600000000001600F +:101020000000001040210E20000000000000FFFF23 +:10103000C0281220000000000000001040211620EF +:10104000000000000000FFFFC0681A20000002BB83 +:101050000001A1FD00604411000002E000003FFF1C +:10106000002F022F00000000000000000CC0000054 +:101070000000015800000000C04004000000000112 +:101080000000225C0020441100000000000000016C +:1010900000300A2F000000000000000100210A2299 +:1010A000000000000000000300384A220000000099 +:1010B0000000225600204411000000000000001A29 +:1010C00000204811000000000000A1FC0020441195 +:1010D0000000000000000001008048110000000036 +:1010E00000000000006000000000000B0000000095 +:1010F000006000000000018F0000000000600000A0 +:10110000000001A000003FFF002F022F00000000A0 +:10111000000000000CE000000000000000000000E3 +:1011200000202C0800000000000000000020241116 +:101130000000000000000000002028110000000056 +:10114000000022560020441100000000000000169C +:1011500000204811000000000000225C0020441123 +:101160000000000000000003002048110000000003 +:1011700093800000002044110000000000000002E5 +:1011800000221E290000000000000000007048EB53 +:101190000000019C0000000000600000000002BB95 +:1011A00000000001403306200000000000000000A5 +:1011B000C03024090000000000003FFF002F022F74 +:1011C00000000000000000000CE000000000000033 +:1011D0000000000000600000000002A3000000000A +:1011E000002F022100000000000000000AE00000C3 +:1011F0000000018100000000006000000000013AD2 +:101200000000000000400000000001869500000082 +:10121000002044110000000000000000002F022107 +:1012200000000000000000000CE00000000001864B +:1012300000000000C0204800000000000000000185 +:10124000005306210000018292000000002044119A +:101250000000000000000000C0604800000001978E +:101260000001A1FD00204411000000000000001159 +:101270000020062D00000000000000000078042A75 +:10128000000002FB00000000002028090000000010 +:1012900000003FFF002F022F0000000000000000B0 +:1012A0000CC000000000017400000000C0400400F9 +:1012B000000000010000021000600411000003158E +:1012C00000003FFF002F022F000000000000000080 +:1012D0000CE000000000019400000015C020362042 +:1012E0000000000000000016C020362000000000B2 +:1012F0003F800000002004110000000046000000B4 +:1013000000600811000001B2000000000080000031 +:10131000000000000000A1FC0020441100000000BB +:1013200000003FFF002F022F00000000000000001F +:101330000CC000000000019B00000001008048116B +:1013400000000000000000210080481100000000A3 +:101350000000FFFF40280E200000000000000010E9 +:10136000C0211220000000000000FFFF40281620CE +:101370000000000000000010C0811A2000000000E2 +:101380008100000000204411000000000000000661 +:1013900000204811000000000000000800221E305C +:1013A000000000000000002900201A2D00000000AD +:1013B0000000E0000020441100000000FFFBFF09D6 +:1013C00000204811000000000000000F0020222D26 +:1013D0000000000000001FFF00294A280000000054 +:1013E000000000060020222D000000000000000088 +:1013F000002920E80000000000000000002048084C +:101400000000000000000000002048110000000063 +:10141000060A020000294A26000000000000000021 +:1014200000204811000000000000000000204811CA +:101430000000000000000100002018110000000062 +:101440000000000800621E280000012F00000008B4 +:1014500000822228000000000002C0000020441189 +:10146000000000000000001500600E2D000001BD0E +:101470000000001600600E2D000001BD0000C00835 +:1014800000204411000000000000001700200E2D75 +:10149000000000000000000014C00000000001B9BE +:1014A0000000000000200411000000000000000007 +:1014B0000020480100000000390000000020481111 +:1014C00000000000000000000020481100000000A3 +:1014D000000000000080480200000000000000182A +:1014E00000202E2D0000000000000000003B0D63D6 +:1014F000000000000000000800224A230000000055 +:101500000000001000224A23000000000000001824 +:1015100000224A2300000000000000000080480371 +:101520000000000000000000006000000000000B50 +:10153000000010000060041100000315000000000E +:1015400000200411000000000000000000600811ED +:10155000000001B2000000070021062F000000007B +:101560000000001300200A2D000000000000000110 +:1015700000202C11000000000000FFFF4028222066 +:10158000000000000000000F0026222800000000DC +:101590000000001040212620000000000000000F85 +:1015A000002626290000000000000000002028027C +:1015B000000000000000225600204411000000003E +:1015C0000000001B00204811000000000000000087 +:1015D000002F022100000000000000000CE00000CD +:1015E000000001E00000225C002044110000000027 +:1015F0000000008100204811000000000000A1FC54 +:1016000000204411000000000000000100204811EB +:10161000000000000000008000201C1100000000FD +:1016200000000000002F0227000000000000000062 +:101630000CE00000000001DC000000000060000081 +:10164000000001E90000000100531E27000001D83E +:101650000000000100202C11000000000000001F0D +:1016600000280A22000000000000001F00282A2A8B +:10167000000000000000000100530621000001D11D +:101680000000225C00204411000000000000000265 +:1016900000304A2F000000000000A1FC002044118F +:1016A00000000000000000010020481100000000C0 +:1016B0000000000100301E2F0000000000000000AC +:1016C000002F022700000000000000000CE00000D6 +:1016D000000000000000000000600000000001E9C0 +:1016E0000000000100531E27000001E50000FFFF7D +:1016F00040280E20000000000000000F00260E23EE +:101700000000000000000010C021122000000000B6 +:101710000000000F0026122400000000000000005E +:1017200000201411000000000000000000601811EB +:10173000000002BB0001A1FD0020441100000000D8 +:1017400000000000002F022B00000000000000003D +:101750000CE00000000001F8000000100022162834 +:1017600000000000FFFF0000002816250000000018 +:101770000000FFFF00281A29000000000000000000 +:10178000002948C500000000000000000020480AB1 +:10179000000000000000000000202C1100000000EC +:1017A000000000100022162300000000FFFF0000D0 +:1017B00000281625000000000000FFFF00281A2462 +:1017C0000000000000000000002948C500000000E3 +:1017D0000000000000731503000002050000000077 +:1017E0000020180500000000000000000073152410 +:1017F0000000020500000000002D14C500000000DC +:1018000000000000003008A20000000000000000FE +:101810000020480200000000000000000020280214 +:101820000000000000000000002020030000000075 +:101830000000000000802404000000000000000FF1 +:1018400000210225000000000000000014C000007C +:101850000000068900000000002B140500000000B5 +:1018600000000001009016250000000000000000AC +:10187000006000000000000B000000000060041188 +:10188000000003150000000000200411000000000B +:101890000000000000600811000001B200002256A4 +:1018A00000204411000000000000001A00294A2214 +:1018B0000000000000000000C02000000000000048 +:1018C00000003FFF002F022F00000000000000007A +:1018D0000CE000000000000000000000C020040038 +:1018E000000000000000225C002044110000000005 +:1018F0000000000300384A21000000000000A1FCA5 +:1019000000204411000000000000000100204811E8 +:10191000000000000000FFFF40281220000000002F +:1019200000000010C0211A20000000000000FFFF8E +:1019300040280E200000000000000010C0211620EA +:10194000000000000000000000741465000002BBED +:101950000001A1FD00604411000002E00000000150 +:10196000003306210000000000000000002F0221CB +:1019700000000000000000000CC000000000021980 +:1019800000003FFF002F022F0000000000000000B9 +:101990000CC000000000021200000000C040040063 +:1019A000000000010000000000600000000006428E +:1019B000000000000040040F0000021300000000BF +:1019C000006000000000062E000000000060000023 +:1019D0000000064200000210006004110000031520 +:1019E0000000000000600000000001A000000000F6 +:1019F000006000000000019C00000000006000008A +:101A0000000002BB0000000000600000000002A314 +:101A1000938000000020441100000000000000003E +:101A2000002048080000000000000000002F022FE6 +:101A300000000000000000000AE000000000023288 +:101A400000000000006000000000013A00000000FB +:101A50000040000000000236950000000020441104 +:101A60000000000000000000002F022F0000000016 +:101A7000000000000CE00000000002360000000042 +:101A8000C0404800000002339200000000204411D2 +:101A90000000000000000000C0204800000000001E +:101AA0000000225600204411000000000000001633 +:101AB00000204811000000000000225C00204411BA +:101AC000000000000000000300204811000000009A +:101AD0000000A1FC002044110000000000000001F3 +:101AE00000204811000000000001A1FD0020441169 +:101AF000000000000000000000600411000002FB74 +:101B000000000000C04004000000000100000000D0 +:101B1000006000000000062E0000A00C0020441110 +:101B20000000000000000000C0204800000000008D +:101B300000000000C040480000000000000000005D +:101B4000006000000000000B0000001840210A2087 +:101B50000000000000000003002F0222000000002F +:101B6000000000000AE000000000024C0000001429 +:101B70000020222D00000000000801010029222879 +:101B800000000000000000140020362800000000C3 +:101B90000000A30C00204411000000000000000021 +:101BA000C02048000000000000000000C0204800E5 +:101BB0000000000000000000C0404800000002518A +:101BC00000000000006000000000000B000000109A +:101BD00000600411000003153F8000000020041184 +:101BE000000000000000000000600811000001B2C9 +:101BF0000000225C002044110000000000000003EF +:101C000000204811000000000000000000600000FB +:101C10000000027C0000001700201E2D00000000C4 +:101C20000000000100211E2700000000000000004D +:101C300014E000000000026A0000001200201E2DC7 +:101C4000000000000000FFFF00281E270000000029 +:101C50000000000000341C2700000000000000000D +:101C600012C000000000025F0000000000201C11F4 +:101C70000000000000000000002F00E50000000050 +:101C80000000000008C00000000002620000000028 +:101C900000201407000000000000001200201E2D8C +:101CA000000000000000001000211E2700000000BE +:101CB0000000000000341C4700000000000000008D +:101CC00012C00000000002670000000000201C118C +:101CD0000000000000000000002F00E600000000EF +:101CE0000000000008C000000000026A00000000C0 +:101CF0000020180700000000000000000060000045 +:101D0000000002C100002256002044110000000023 +:101D1000000000000034202300000000000000004C +:101D200012C00000000002720000000000342044D5 +:101D3000000000000000000012C00000000002715E +:101D40000000001600404811000002760000001854 +:101D500000404811000002760000000000342044DA +:101D6000000000000000000012C00000000002752A +:101D70000000001700404811000002760000001922 +:101D800000204811000000000000A1FC00204411C8 +:101D900000000000000000010020481100000000C9 +:101DA0000001A1FD00604411000002E900003FFFB6 +:101DB000002F022F00000000000000000CC00000F7 +:101DC0000000025600000000C040040000000001B6 +:101DD0000000001040210620000000000000FFFF6E +:101DE000C0280A20000000000000001040210E2042 +:101DF000000000000000FFFFC028122000000000CB +:101E00000000001040211620000000000000FFFF2D +:101E1000C0881A200000000081000000002044114A +:101E20000000000000000001002048110000000038 +:101E300000042004006044110000068A0000000035 +:101E4000006000000000062E00000000C0600000DE +:101E5000000002A30000000500200A2D0000000081 +:101E60000000000800220A22000000000000002BF1 +:101E700000201A2D000000000000001C00201E2D74 +:101E8000000000000000700000281E270000000075 +:101E90000000000000311CE6000000000000002AE5 +:101EA00000201A2D000000000000000C00221A265D +:101EB0000000000000000000002F00E6000000000D +:101EC0000000000006E00000000002920000000098 +:101ED00000201C11000000000000000000200C1178 +:101EE000000000000000002B00203623000000004E +:101EF0000000001000201811000000000000000089 +:101F000000691CE20000012F9380000000204411B2 +:101F10000000000000000000002048070000000052 +:101F200095000000002044110000000000000000A7 +:101F3000002F022F00000000000000000CE0000055 +:101F40000000029D0000000100333E2F0000000051 +:101F500000000000D90048000000000092000000CE +:101F6000002044110000000000000000C0204800D4 +:101F7000000000000000001C0040362700000000A8 +:101F80000000000CC0220A20000000000000002910 +:101F9000002036220000000000000028C04036204B +:101FA000000000000000A2A4002044110000000076 +:101FB000000000090020481100000000A1000000FE +:101FC00000204411000000000000000100804811C2 +:101FD000000000000000002100201E2D0000000075 +:101FE00000000000002C1CE30000000000000021A5 +:101FF00000203627000000000000002200201E2DD7 +:102000000000000000000000002C1CE400000000A4 +:1020100000000022002036270000000000000023FE +:1020200000201E2D0000000000000000003120A351 +:102030000000000000000000002D1D07000000004F +:1020400000000023002036270000000000000024CC +:1020500000201E2D0000000000000000003120C400 +:102060000000000000000000002D1D07000000001F +:10207000000000240080362700000000000000213E +:10208000002036230000000000000022002036243B +:10209000000000000000000000311CA30000000050 +:1020A0000000002300203627000000000000000090 +:1020B00000311CC40000000000000024008036270E +:1020C000000000000000001A002036270000000079 +:1020D0000000001B00203628000000000000001750 +:1020E00000201E2D00000000000000020021022739 +:1020F000000000000000000014C00000000002DC2E +:102100000000000000400000000002D90000001A9A +:1021100000203627000000000000001B00203628A9 +:10212000000000000000001700201E2D000000002D +:102130000000000200210227000000000000000053 +:1021400014E00000000002D9000000030021022773 +:10215000000000000000000014E00000000002DCAD +:102160000000002300201E2D0000000000000000E1 +:10217000002E00E1000000000000000002C000008E +:10218000000002DC0000002100201E2D00000000E5 +:1021900000000000003120A100000000000000004D +:1021A000002E00E8000000000000000006C0000053 +:1021B000000002DC0000002400201E2D00000000B2 +:1021C00000000000002E00E20000000000000000FF +:1021D00002C00000000002DC0000002200201E2DD2 +:1021E0000000000000000000003120C200000000DC +:1021F00000000000002E00E80000000000000000C9 +:1022000006C00000000002DC0000000000600000CA +:10221000000006650000000000600000000002B53C +:102220000000000000400000000002DE000000008E +:1022300000600000000002B5000000000060000027 +:102240000000065C0000000000400000000002DE0C +:102250000000000000600000000002A70000000075 +:1022600000400000000002DE0000001A00201E2DC9 +:10227000000000000000001B0080222D0000000074 +:102280000000001000221E230000000000000000DB +:1022900000294887000000000000000000311CA356 +:1022A000000000000000001000221E2700000000B7 +:1022B0000000000000294887000000000000001016 +:1022C00000221E230000000000000000003120C496 +:1022D000000000000000FFFF00282228000000008E +:1022E0000000000000894907000000000000001005 +:1022F00000221E2300000000000000000029488783 +:10230000000000000000001000221E21000000005C +:102310000000000000294847000000000000000005 +:1023200000311CA3000000000000001000221E2746 +:1023300000000000000000000029488700000000A5 +:102340000000000000311CA100000000000000108F +:1023500000221E270000000000000000002948475E +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:10239000000000000000001000221E2100000000CC +:1023A00000000000003120C2000000000000FFFF1C +:1023B00000282228000000000000000000894907D2 +:1023C000000000000000001000221E23000000009A +:1023D0000000000000294887000000000000000104 +:1023E00000220A210000000000000000003308A2C3 +:1023F000000000000000001000221E22000000006B +:102400000000001000212222000000000000000057 +:1024100000294907000000000000000000311CA353 +:10242000000000000000001000221E270000000035 +:1024300000000000002948870000000000000001A3 +:1024400000220A210000000000000000003008A265 +:10245000000000000000001000221E22000000000A +:1024600000000010002122220000000000000000F7 +:1024700000294907000000000000001000221E2370 +:102480000000000000000000003120C40000000037 +:102490000000FFFF002822280000000000000000CC +:1024A000002949070000000000000000003808C5AE +:1024B00000000000000000000030084100000000A3 +:1024C0000000000100220A220000000000000000BD +:1024D000003308A2000000000000001000221E22AD +:1024E0000000000000000010002122220000000077 +:1024F00000000000008949070000000000000017EC +:102500000020222D000000000000000014C0000088 +:1025100000000318FFFFFFEF002806210000000065 +:10252000000000140020222D000000000000F8E050 +:1025300000204411000000000000000000294901B3 +:1025400000000000000000000089490100000000B8 +:102550000000000000204811000000000000000002 +:102560000020481100000000060A02000080481107 +:102570000000000000000000C0200000000000007B +:1025800097000000C020441100000000000000007F +:10259000C0204811000000008A0000000020441103 +:1025A00000000000000000000020481100000000B2 +:1025B0000000225C00204411000000000000000028 +:1025C000C0204800000000000000A1FC00204411D1 +:1025D0000000000000000000C020480000000000D3 +:1025E00000000000C0200400000000000000000007 +:1025F00000A0000A00000000970000000020441125 +:102600000000000000000000002048110000000051 +:102610008A000000002044110000000000000000BB +:1026200000204811000000000000225C002044113E +:102630000000000000000000C02048000000000072 +:102640000000A1FC00204411000000000000000078 +:10265000C02048000000000000000000C02004006E +:10266000000000000000000000A0000A00000000C0 +:10267000970000000020441100000000000000004E +:1026800000204811000000008A00000000204411D2 +:1026900000000000000000000020481100000000C1 +:1026A0000000225C00204411000000000000000037 +:1026B000C0204800000000000000A1FC00204411E0 +:1026C0000000000000000000C020480000000000E2 +:1026D0000001A1FD002044110000000000000000E6 +:1026E000D90048000000000000000000C0200400E5 +:1026F000000000000000000000A0000A0000000030 +:1027000000002257002044110000000000000003D8 +:10271000C0484A20000000000000225D0020441153 +:102720000000000000000000C04048000000000061 +:1027300000000000006000000000064200000000F1 +:10274000C0200800000000000000225C00204411AE +:10275000000000000000000300384A2200000000D2 +:102760000000A1FC00204411000000000000000057 +:10277000C0204800000000000001A1FD002044111D +:102780000000000000000000002F022200000000F6 +:10279000000000000CE0000000000000000000004D +:1027A00040204800000000000000000140304A20A6 +:1027B0000000000000000002C0304A2000000000BD +:1027C0000000000100530A220000034B0000003FFC +:1027D000C0280A20000000008100000000204411F1 +:1027E000000000000000000100204811000000006F +:1027F000000021F800204411000000000000001833 +:102800000020481100000000000421F9006044117C +:102810000000068A000000110021023000000000C4 +:102820000000000014E00000000003540000001449 +:10283000002F022200000000000000000CC0000079 +:10284000000003640000201000204411000000007C +:102850000000800000204811000000000001A2A438 +:102860000020441100000000000000000060480249 +:102870000000036E00002100002044110000000051 +:1028800000000000C0204800000000000000000020 +:10289000C02048000000000000000000C0204800E8 +:1028A0000000000000000000C040480000000000E0 +:1028B00000000004002F02220000000000000000C1 +:1028C0000CC000000000036A00002010002044112A +:1028D00000000000000080000020481100000000FF +:1028E0000001A2A40020441100000000000000002C +:1028F000004048020000035F00000028002F022271 +:1029000000000000000000000CC00000000005BD39 +:102910000001A2A4002044110000000000000000FB +:10292000004048020000035F0000002C0020362613 +:102930000000000000000049002018110000000005 +:102940000000003F002048110000000000000001CE +:1029500000331A260000000000000000002F0226AD +:1029600000000000000000000CC000000000037028 +:102970000000002C00801A2D000000000000003F25 +:10298000C0280A200000000000000015002F0222CD +:1029900000000000000000000CE0000000000386C2 +:1029A00000000006002F02220000000000000000CE +:1029B0000CE00000000003B100000016002F02220E +:1029C00000000000000000000CE00000000003B563 +:1029D00000000020002F0222000000000000000084 +:1029E0000CE000000000039C0000000F002F0222FA +:1029F00000000000000000000CE00000000003A840 +:102A000000000010002F0222000000000000000063 +:102A10000CE00000000003A80000001E002F0222AE +:102A200000000000000000000CE000000000039027 +:102A30000000A2A4002044110000000000000000DB +:102A400000404802000000000800000000290A229F +:102A5000000000000000000340210E2000000000E4 +:102A60000000000CC021122000000000000800003F +:102A7000002812240000000000000014C0221620CC +:102A80000000000000000000002914A40000000065 +:102A90000000A2A40020441100000000000000007B +:102AA000002948A2000000000000A1FE00204411FF +:102AB000000000000000000000404803000000008B +:102AC000810000000020441100000000000000010F +:102AD0000020481100000000000021F800204411EF +:102AE0000000000000000016002048110000000057 +:102AF000000421F9006044110000068A000000155E +:102B000000210230000000000000000014E000007E +:102B1000000003920000210E00204411000000007C +:102B200000000000C020480000000000000000007D +:102B3000C0204800000000000000A2A400204411B2 +:102B400000000000000000000040480200000000FB +:102B5000810000000020441100000000000000017E +:102B60000020481100000000000021F8002044115E +:102B700000000000000000170020481100000000C5 +:102B8000000421F9006044110000068A00000003DF +:102B900000210230000000000000000014E00000EE +:102BA0000000039E000021080020441100000000E6 +:102BB00000000000C02048000000000000000000ED +:102BC000C0204800000000000000A2A40020441122 +:102BD000000000000000000000404802000000006B +:102BE0000000A2A40020441100000000000000002A +:102BF0000020480200000000800000000020441176 +:102C0000000000000000000000204811000000004B +:102C100081000000002044110000000000000010AE +:102C200000204811000000000000000000200010FB +:102C3000000000000000000014C00000000003AE0F +:102C40000000000000400000000000000000201014 +:102C50000020441100000000000080000020481106 +:102C6000000000000001A2A40020441100000000A8 +:102C70000000000600404811000000000000201085 +:102C800000204411000000000000800000204811D6 +:102C9000000000000001A2A4002044110000000078 +:102CA00000000016006048110000036E00000000E4 +:102CB000004000000000000000000000C0200800EC +:102CC0000000000000000000C0200C000000000018 +:102CD0000000001D00210223000000000000000091 +:102CE00014E00000000003CE810000000020441129 +:102CF000000000000000000100204811000000005A +:102D0000000021F80020441100000000000000181D +:102D10000020481100000000000421F90060441167 +:102D20000000068A000000110021023000000000AF +:102D30000000000014E00000000003C000002100BB +:102D400000204411000000000000000000204802A4 +:102D50000000000000000000002048030000000008 +:102D6000BABECAFE0020481100000000CAFEBABE6A +:102D70000020481100000000000020100020441135 +:102D8000000000000000800000204811000000004A +:102D90000000A2A400204411000000000000000474 +:102DA0000040481100000000000021700020441184 +:102DB00000000000000000000020480200000000A9 +:102DC0000000000000204803000000008100000017 +:102DD00000204411000000000000000A00204811FB +:102DE00000000000000000000020001000000000B3 +:102DF0000000000014C00000000003D38C0000009D +:102E00000020441100000000CAFEBABE0040481174 +:102E100000000000810000000020441100000000BC +:102E200000000001002048110000000000003FFFEA +:102E300040280A20000000008000000040280E20EA +:102E40000000000040000000C02812200000000028 +:102E500000040000006946220000068A000000000D +:102E6000002014100000000000000000002F0223CA +:102E700000000000000000000CC00000000003E1A2 +:102E800000000000C0401800000003E400003FFF05 +:102E9000C0281A2000000000000400000069462637 +:102EA0000000068A0000000000201810000000004A +:102EB00000000000002F02240000000000000000BD +:102EC0000CC00000000003E700000000C0401C0030 +:102ED000000003EA00003FFFC0281E2000000000A1 +:102EE00000040000006946270000068A0000000078 +:102EF00000201C1000000000000000000020440220 +:102F00000000000000000000002820C500000000B4 +:102F100000000000004948E800000000A580000013 +:102F200000200811000000000000200000200C110B +:102F30000000000083000000006044110000041243 +:102F4000000000000020440200000000000000001B +:102F5000C0204800000000000000000040204800A1 +:102F6000000000000000001FC0210220000000003F +:102F70000000000014C00000000003F70000201053 +:102F800000204411000000000000800000204811D3 +:102F9000000000000000FFFFC0481220000003FFF7 +:102FA000A780000000200811000000000000A00021 +:102FB00000200C110000000083000000006044119C +:102FC0000000041200000000002044020000000085 +:102FD00000000000C02048000000000000000000C9 +:102FE000C0204800000000000000FFFFC0281220A1 +:102FF00000000000830000000020441100000000D9 +:103000000000000000304883000000008400000041 +:10301000002044110000000000000000C020480013 +:1030200000000000000000001D0000000000000083 +:103030008300000000604411000004120000000042 +:10304000C040040000000001A98000000020081119 +:10305000000000000000C00000400C11000003FA56 +:10306000AB80000000200811000000000000F8E024 +:1030700000400C11000003FAAD8000000020081190 +:10308000000000000000F88000400C11000003FA6E +:10309000B380000000200811000000000000F3FCD5 +:1030A00000400C11000003FAAF800000002008115E +:1030B000000000000000E00000400C11000003FAD6 +:1030C000B180000000200811000000000000F000A6 +:1030D00000400C11000003FA83000000002044119E +:1030E00000000000000021480020481100000000FE +:1030F00084000000002044110000000000000000D7 +:10310000C020480000000000000000001D0000007A +:10311000000000000000000000800000000000002F +:1031200001182000C0304620000000000000000010 +:10313000D90048000000000000000000C02004008A +:10314000000000000000000000A0000A00000000D5 +:103150000218A000C030462000000000000000005F +:10316000D90048000000000000000000C02004005A +:10317000000000000000000000A0000A00000000A5 +:103180000318C000C030462000000000000000000E +:10319000D90048000000000000000000C02004002A +:1031A000000000000000000000A0000A0000000075 +:1031B0000418F8E0C03046200000000000000000C5 +:1031C000D90048000000000000000000C0200400FA +:1031D000000000000000000000A0000A0000000045 +:1031E0000518F880C03046200000000000000000F4 +:1031F000D90048000000000000000000C0200400CA +:10320000000000000000000000A0000A0000000014 +:103210000618E000C030462000000000000000005A +:10322000D90048000000000000000000C020040099 +:10323000000000000000000000A0000A00000000E4 +:103240000718F000C0304620000000000000000019 +:10325000D90048000000000000000000C020040069 +:10326000000000000000000000A0000A00000000B4 +:103270000818F3FCC03046200000000000000000E9 +:10328000D90048000000000000000000C020040039 +:10329000000000000000000000A0000A0000000084 +:1032A0000000003000200A2D000000000000000097 +:1032B000C0290C4000000000000000300020362330 +:1032C0000000000000000000C0200400000000001A +:1032D0000000000000A0000A0000000086000000BE +:1032E00000204411000000000000000000404801E0 +:1032F0000000000085000000C02044110000000014 +:103300000000000000404801000000000000217C97 +:10331000002044110000000000000000C020480010 +:103320000000000000000000C02048000000000075 +:1033300000000000C02048000000000081000000E4 +:10334000002044110000000000000001002048118E +:103350000000000000000000C02008000000000085 +:103360000000000017000000000000000004217FA2 +:10337000006044110000068A0000001F0021023096 +:10338000000000000000000014C000000000000069 +:103390000000000000404C02000004480000000053 +:1033A000C0200C000000000000000000C020100041 +:1033B0000000000000000000C02014000000000019 +:1033C00000000000C0201800000000000000000005 +:1033D000C0201C000000000000007F0000280A211F +:1033E0000000000000004500002F02220000000045 +:1033F000000000000CE00000000004560000000087 +:10340000C0202000000000000000000017000000A5 +:10341000000000000000001000280A230000000047 +:1034200000000010002F0222000000000000000039 +:103430000CE000000000045E810000000020441148 +:103440000000000000000001002048110000000002 +:1034500000040000006946240000068A0000000005 +:1034600000400000000004638100000000204411BF +:1034700000000000000000000020481100000000D3 +:103480000000216D00204411000000000000000039 +:103490000020480400000000000000000060480513 +:1034A0000000068F00000000002824F0000000004B +:1034B0000000000700280A230000000000000001AF +:1034C000002F022200000000000000000AE00000BF +:1034D0000000046A00000000002F00C90000000086 +:1034E0000000000004E00000000004830000000071 +:1034F000004000000000049000000002002F0222A3 +:1035000000000000000000000AE000000000046F5E +:1035100000000000002F00C90000000000000000B3 +:1035200002E00000000004830000000000400000F2 +:103530000000049000000003002F022200000000A1 +:10354000000000000AE00000000004740000000019 +:10355000002F00C900000000000000000CE0000087 +:103560000000048300000000004000000000049000 +:1035700000000004002F02220000000000000000F4 +:103580000AE000000000047900000000002F00C9DC +:1035900000000000000000000AE0000000000483BA +:1035A0000000000000400000000004900000000542 +:1035B000002F022200000000000000000AE00000CE +:1035C0000000047E00000000002F00C90000000081 +:1035D0000000000006E0000000000483000000007E +:1035E000004000000000049000000006002F0222AE +:1035F00000000000000000000AE00000000004835A +:1036000000000000002F00C90000000000000000C2 +:1036100008E00000000004830000000000400000FB +:103620000000049000007F0000280A210000000034 +:1036300000004500002F02220000000000000000F2 +:103640000AE00000000000000000000800210A233A +:10365000000000000000000014C000000000048D05 +:10366000000021690020441100000000000000005B +:10367000C02048000000000000000000C0204800FA +:103680000000000000000000C02048000000000012 +:10369000CAFEBABE00404811000000000000000051 +:1036A000C02044000000000000000000C020000016 +:1036B0000000000000000000C040480000000000C2 +:1036C00000007F0000280A210000000000004500E3 +:1036D000002F022200000000000000000AE00000AD +:1036E0000000049600000000C02000000000000060 +:1036F00000000000C02000000000000000000000EA +:10370000C0400000000000000000000000404C0825 +:103710000000045600000000C02008000000000067 +:103720000000001040210E200000000000000011E9 +:10373000402112200000000000000012402116204D +:10374000000000000000216900204411000000007A +:1037500000000000002048020000000000000000FF +:1037600000210225000000000000000014E000001D +:10377000000004A000040000C0494A20000004A189 +:10378000FFFBFFFFC0284A200000000000000000EF +:1037900000210223000000000000000014E00000EF +:1037A000000004AD00000000C02048000000000040 +:1037B00000000000C02048000000000000000000E1 +:1037C00000210224000000000000000014C00000DE +:1037D00000000000810000000020441100000000F3 +:1037E0000000000C00204811000000000000000054 +:1037F00000200010000000000000000014C00000C5 +:10380000000004A9A00000000020441100000000F6 +:10381000CAFEBABE0040481100000000810000004E +:1038200000204411000000000000000400204811A6 +:10383000000000000000216B002044110000000087 +:1038400000000000C02048100000000081000000BF +:103850000020441100000000000000050020481175 +:10386000000000000000216C002044110000000056 +:1038700000000000C0204810000000000000000010 +:10388000002F022400000000000000000CE00000F7 +:10389000000000000000000000400000000004A73D +:1038A00000000000C0210A2000000000000000000D +:1038B00014C00000000004C081000000002044117A +:1038C000000000000000000000204811000000007F +:1038D0000000216D002044110000000000000000E5 +:1038E000C02048000000000000000000C060480048 +:1038F0000000068F0000000000400000000004C42B +:1039000081000000002044110000000000000001C0 +:10391000002048110000000000040000C0294620DB +:103920000000000000000000C06000000000068AE7 +:103930000000000100210222000000000000000041 +:1039400014C00000000004CB0000216900204411D5 +:103950000000000000000000C0204800000000003F +:1039600000000000C020480000000000000000002F +:103970000020481000000000CAFEBABE00404811F6 +:103980000000000000000000C02044000000000013 +:1039900000000000C040481000000000810000004E +:1039A0000020441100000000000000010020481128 +:1039B00000000000000021F8002044110000000079 +:1039C0000000000E0020481100000000000421F952 +:1039D000006044110000068A00000000002102304F +:1039E000000000000000000014C00000000004CD32 +:1039F00000002180002044110000000000000000B1 +:103A0000C02048000000000000000000C0200000AE +:103A10000000000000000000C0204800000000007E +:103A200000000000C02000000000000000000000B6 +:103A3000C0404800000000000000000300333E2F9B +:103A40000000000000000001002102210000000031 +:103A50000000000014E00000000004FD0000002C45 +:103A600000200A2D000000000004000018E00C11E6 +:103A7000000004EC0000000100333E2F00000000B5 +:103A80000000216900204411000000000000000037 +:103A90000020480200000000000000000020480351 +:103AA000000000000000000800300A2200000000B2 +:103AB00000000000C02048000000000000000000DE +:103AC000C0204800000000000000216900204411CF +:103AD000000000000000000000204802000000007C +:103AE0000000000000204803000000000000000863 +:103AF00000300A220000000000000000C020480042 +:103B00000000000000000000D8C04800000004E0F1 +:103B100000002169002044110000000000000000A6 +:103B200000204802000000000000000000204803C0 +:103B3000000000000000000800300A220000000021 +:103B400000000000C020480000000000000000004D +:103B5000C0204800000000000000002D0020122DB1 +:103B6000000000000000000000290C83000000009D +:103B70000000216900204411000000000000000046 +:103B80000020480200000000000000000020480360 +:103B9000000000000000000800300A2200000000C1 +:103BA00000000000C02048000000000000000000ED +:103BB000C020480000000000000000110021022485 +:103BC000000000000000000014C000000000000021 +:103BD0000000000000400000000004A70000002CCE +:103BE000C0203620000000000000002DC04036201C +:103BF000000000000000000F002102210000000072 +:103C00000000000014C000000000050200000000D9 +:103C1000006000000000000B00000000D900000060 +:103C20000000000000000000C0400400000000018F +:103C3000B50000000020441100000000000020003A +:103C40000020481100000000B600000000204411D0 +:103C5000000000000000A00000204811000000004B +:103C6000B700000000204411000000000000C00068 +:103C70000020481100000000B8000000002044119E +:103C8000000000000000F8E00020481100000000E3 +:103C9000B900000000204411000000000000F8807E +:103CA0000020481100000000BA000000002044116C +:103CB000000000000000E0000020481100000000AB +:103CC000BB00000000204411000000000000F000D4 +:103CD0000020481100000000BC000000002044113A +:103CE000000000000000F3FC00204811000000006C +:103CF00081000000002044110000000000000002CC +:103D00000020481100000000000000FF00280E30D5 +:103D10000000000000000000002F0223000000004F +:103D2000000000000CC000000000051600000000AC +:103D3000C0200800000000000000000014C00000C7 +:103D40000000052B0000000000200C110000000006 +:103D50000000001C00203623000000000000002BA3 +:103D60000020362300000000000000290020362338 +:103D700000000000000000280020362300000000A2 +:103D8000000000170020362300000000000000257E +:103D9000002036230000000000000026002036230B +:103DA0000000000000000015002036230000000085 +:103DB000000000160020362300000000FFFFE00096 +:103DC00000200C110000000000000021002036231C +:103DD0000000000000000022002036230000000048 +:103DE00000001FFF00200C11000000000000002355 +:103DF00000203623000000000000002400203623AD +:103E000000000000F1FFFFFF00283A2E0000000034 +:103E10000000001AC0220E20000000000000000078 +:103E20000029386E000000008100000000204411CD +:103E30000000000000000006002048110000000003 +:103E40000000002A4020362000000000870000000B +:103E5000002044110000000000000000C0204800C5 +:103E6000000000000000A1F4002044110000000048 +:103E700000000000002048100000000000000000CA +:103E800000200C110000000000000030002036234C +:103E9000000000009D000000002044110000000010 +:103EA0000000001F40214A20000000009600000092 +:103EB000002044110000000000000000C020480065 +:103EC0000000000000000000C0200C000000000006 +:103ED00000000000C0201000000000000000001FD3 +:103EE00000211624000000000000000014C00000A3 +:103EF000000000000000001D00203623000000002C +:103F00000000000300281E2300000000000000083D +:103F10000022222300000000FFFFF00000282228DA +:103F20000000000000000000002920E80000000060 +:103F30000000001F002036280000000000000018CC +:103F400000211E2300000000000000200020362772 +:103F50000000000000000002002216240000000003 +:103F600000000000003014A8000000000000001E47 +:103F700000203625000000000000000300211A2464 +:103F8000000000001000000000281A2600000000B9 +:103F9000EFFFFFFF00283A2E0000000000000000A5 +:103FA000004938CE000006780000000140280A20B1 +:103FB000000000000000000640280E200000000065 +:103FC00000000300C02812200000000000000008CC +:103FD000002112240000000000000000C020162074 +:103FE0000000000000000000C0201A2000000000B7 +:103FF000000000000021022200000000000000007C +:1040000014C000000000056381000000002044117E +:104010000000000000000001002048110000000026 +:104020000000225800300A240000000000040000B4 +:10403000006946220000068A000021690020441120 +:104040000000000000000000002048050000000003 +:104050000002000000294A260000000000000000C5 +:104060000020481000000000CAFEBABE002048111F +:104070000000000000000002002F022300000000EA +:10408000000000000CC000000000056B00000000F4 +:10409000C0201C100000000000000000C040000014 +:1040A0000000057900000002002F0223000000003C +:1040B000000000000CC000000000056B8100000043 +:1040C0000020441100000000000000010020481101 +:1040D000000000000000225800300A240000000008 +:1040E00000040000006946220000068A000000006B +:1040F000C0201C100000000000000000C0400000B4 +:104100000000057900000000002F022300000000DD +:10411000000000000CC000000000056F000000005F +:10412000C0201C000000000000000000C040000093 +:104130000000057900000004002F022300000000A9 +:10414000000000000CC000000000057781000000A6 +:104150000020441100000000000000000020481171 +:10416000000000000000216D00204411000000004C +:1041700000000000C0204800000000000000000017 +:10418000C06048000000068F0000000000401C10C6 +:104190000000057900000000C020000000000000C1 +:1041A00000000000C040000000000000000000000F +:1041B0000EE000000000057B000000000060000031 +:1041C000000005C600000000002F022400000000CF +:1041D000000000000CC000000000058C0000A2B729 +:1041E00000204411000000000000000000204807EB +:1041F00000000000810000000020441100000000C9 +:104200000000000100204811000000000004A2B6D8 +:10421000006044110000068A0000001A00212230CC +:104220000000000000000006002226300000000010 +:1042300000042004006044110000068A0000A2C4AB +:10424000002044110000000000000000003048E998 +:10425000000000000000000000E000000000058AEF +:104260000000A2D100204411000000000000000066 +:1042700000404808000000000000A2D100204411C6 +:10428000000000000000000100504A28000000006B +:1042900000000001002F02240000000000000000C8 +:1042A0000CC000000000059D0000A2BB00204411CE +:1042B000000000000000000000204807000000008F +:1042C00081000000002044110000000000000001F7 +:1042D00000204811000000000004A2BA0060441150 +:1042E0000000068A0000001A0021223000000000B1 +:1042F0000000000600222630000000000004200418 +:10430000006044110000068A0000A2C5002044118C +:104310000000000000000000003048E9000000003C +:104320000000000000E000000000059B0000A2D299 +:104330000020441100000000000000000040480878 +:10434000000000000000A2D2002044110000000084 +:104350000000000100504A28000000000000000298 +:10436000002F022400000000000000000CC000002C +:10437000000005AE0000A2BF0020441100000000B4 +:10438000000000000020480700000000810000003D +:10439000002044110000000000000001002048112E +:1043A000000000000004A2BE006044110000068A64 +:1043B0000000001A0021223000000000000000066A +:1043C0000022263000000000000420040060441198 +:1043D0000000068A0000A2C6002044110000000070 +:1043E00000000000003048E900000000000000006C +:1043F00000E00000000005AC0000A2D30020441142 +:10440000000000000000000000404808000000001C +:104410000000A2D3002044110000000000000001B1 +:1044200000504A28000000000000A2C300204411F0 +:10443000000000000000000000204807000000000D +:104440008100000000204411000000000000000175 +:1044500000204811000000000004A2C200604411C6 +:104460000000068A0000001A00212230000000002F +:104470000000000600222630000000000004200496 +:10448000006044110000068A0000A2C70020441109 +:104490000000000000000000003048E900000000BB +:1044A0000000000000E00000000005BB0000A2D4F6 +:1044B00000204411000000000000000000404808F7 +:1044C000000000000000A2D4002044110000000001 +:1044D0000000000100504A28000000008500000094 +:1044E00000204411000000000000000000204801EE +:1044F000000000000000304A0020441100000000CD +:104500000100000000204811000000000000000031 +:1045100000400000000005C1A4000000C0204411BC +:104520000000000000000000C04048000000000043 +:1045300000000000C0600000000005C60000000090 +:10454000C0400400000000010000002C00203621C3 +:104550000000000081000000002044110000000065 +:1045600000000006002048110000000000000000CC +:10457000002F023000000000000000000CC000000E +:10458000000005CD00000000002004110000000024 +:104590000000003000403621000005E0000000303F +:1045A0000020062D0000000000007E0000280621EB +:1045B0000000000000000000002F022100000000A9 +:1045C000000000000CE00000000005E08100000099 +:1045D00000204411000000000000000100204811EC +:1045E000000000000004A092006044110000068A50 +:1045F0000000003100203630000000000004A093CD +:10460000006044110000068A0000003200203630AD +:10461000000000000004A2B6006044110000068AF9 +:104620000000003300203630000000000004A2BA71 +:10463000006044110000068A00000034002036307B +:10464000000000000004A2BE006044110000068AC1 +:104650000000003500203630000000000004A2C237 +:10466000006044110000068A000000360020363049 +:104670000000000000042004006044110000068ACD +:104680000001A2A400204411000000000000003F2F +:1046900000204811000000000000003F00204811E9 +:1046A000000000000000003F002048110000000052 +:1046B0000000003F0020481100000000000000053D +:1046C00000204811000000000000A1F40020441167 +:1046D0000000000000000000002048110000000061 +:1046E00088000000002044110000000000000001CC +:1046F000002048110000000081000000002044114B +:10470000000000000000000600204811000000002A +:1047100000000001002F0230000000000000000037 +:104720000CE0000000000629000000300020062DEB +:104730000000000000000000002F02210000000027 +:10474000000000000CE000000000062981000000CD +:10475000002044110000000000000001002048116A +:104760000000000000007E0000280621000000007C +:1047700000000000002F02210000000000000000E7 +:104780000CE00000000006020000A092002044118E +:10479000000000000000003100204A2D0000000051 +:1047A0000000A0930020441100000000000000322F +:1047B00000204A2D000000000000A2B60020441195 +:1047C000000000000000003300204A2D000000001F +:1047D0000000A2BA002044110000000000000034D4 +:1047E00000204A2D000000000000A2BE002044115D +:1047F000000000000000003500204A2D00000000ED +:104800000000A2C200204411000000000000003699 +:1048100000204A2D00000000000000300020062D7E +:1048200000000000000001FF002806210000000039 +:1048300000000000002F0221000000000000000026 +:104840000CE000000000062800000000002102210A +:10485000000000000000000014C000000000060B73 +:104860000004A003006044110000068A0000A003B9 +:10487000002044110000000000000000002048104B +:1048800000000000000000010021062100000000DF +:104890000000000014C00000000006100004A0107A +:1048A000006044110000068A0000A010002044119E +:1048B0000000000000000000002048100000000080 +:1048C000000000010021062100000000000000009F +:1048D000002F022100000000000000000CE000009A +:1048E000000006280004A011006044110000068AA0 +:1048F0000000A01100204411000000000000000092 +:1049000000204810000000000004A01200604411C4 +:104910000000068A0000A0120020441100000000E0 +:104920000000000000204810000000000004A01358 +:10493000006044110000068A0000A013002044110A +:1049400000000000000000000020481000000000EF +:104950000004A014006044110000068A0000A014A6 +:10496000002044110000000000000000002048105A +:10497000000000000004A015006044110000068A39 +:104980000000A015002044110000000000000000FD +:1049900000204810000000000004A0160060441130 +:1049A0000000068A0000A01600204411000000004C +:1049B0000000000000204810000000000004A017C4 +:1049C000006044110000068A0000A0170020441176 +:1049D000000000000000000000204810000000005F +:1049E00000042004006044110000068A0000002C2E +:1049F0000080062D00000000FF0000000020441190 +:104A0000000000000000000000204811000000002D +:104A1000000000010020481100000000000000021A +:104A20000080481100000000000000000EE00000BF +:104A30000000063A000000300020062D00000000B3 +:104A40000000000200280621000000000000000015 +:104A5000002F022100000000000000000CE0000018 +:104A60000000063881000000002044110000000012 +:104A70000000000100204811000000000004200494 +:104A8000006044110000068A000010000020081198 +:104A9000000000000000002B002036220000000073 +:104AA00000000000006000000000063E0000000062 +:104AB00000600000000005C69800000000204411BE +:104AC000000000000000000000804811000000000D +:104AD00000000000C06000000000063E0000000072 +:104AE000C0400400000000010000A2A40020441106 +:104AF000000000000000002200204811000000001B +:104B000089000000002044110000000000000001A6 +:104B1000004048110000062A9700000000204411C0 +:104B2000000000000000000000204811000000000C +:104B30008A00000000204411000000000000000076 +:104B4000004048110000062A00000000006000003C +:104B50000000065900002010002044110000000051 +:104B60000000800000204811000000000001A2A405 +:104B7000C020441100000000000000160060481131 +:104B80000000036E0000201000204411000000000F +:104B9000000100000020481100000000810000001A +:104BA0000020441100000000000000010020481116 +:104BB000000000000000217C0020441100000000E3 +:104BC000098000000020481100000000FFFFFFFFE7 +:104BD00000204811000000000000000000204811E3 +:104BE00000000000000000001700000000000000AE +:104BF0000004217F006044110000068A0000001FAD +:104C000000210230000000000000000014C000007D +:104C1000000000000000000400404C11000006539A +:104C2000000000000040000000000000000000172D +:104C300000201E2D000000000000000400291E2797 +:104C40000000000000000017008036270000000070 +:104C50000000001700201E2D00000000FFFFFFFBDA +:104C600000281E27000000000000001700803627E3 +:104C7000000000000000001700201E2D00000000B2 +:104C80000000000800291E27000000000000001797 +:104C900000803627000000000000001700201E2DB5 +:104CA00000000000FFFFFFF700281E2700000000A3 +:104CB00000000017008036270000000000002010D0 +:104CC0000020441100000000000080000020481176 +:104CD000000000000001A2A4002044110000000018 +:104CE00000000016006048110000036E0000201054 +:104CF00000204411000000000001000000204811C5 +:104D0000000000000000217C002044110000000091 +:104D1000018000000020481100000000FFFFFFFF9D +:104D20000020481100000000000000000020481191 +:104D3000000000000000000017000000000000005C +:104D4000810000000020441100000000000000016C +:104D500000204811000000000004217F0060441181 +:104D60000000068A0000001F002102300000000041 +:104D70000000000014C000000000068900000010C0 +:104D800000404C110000066F00000000C02004002D +:104D9000000000000000000038C00000000000001B +:104DA0000000001D00200A2D000000000000001E71 +:104DB00000200E2D000000000000001F0020122D1A +:104DC00000000000000000200020162D0000000060 +:104DD00000002169002044110000000000000000D4 +:104DE00000204804000000000000000000204805EA +:104DF000000000000000000000204801000000004A +:104E0000CAFEBABE002048110000000000000004E5 +:104E1000003012240000000000000000002F006499 +:104E200000000000000000000CC000000000068828 +:104E30000000000300281A22000000000000000803 +:104E40000022122200000000FFFFF00000281224C0 +:104E50000000000000000000002910C40000000055 +:104E60000000001F00403624000000000000000089 +:104E70000080000000000000000000001AC00000D8 +:104E80000000068A9F00000000204411000000007E +:104E9000CAFEBABE00204811000000000000000059 +:104EA0001AE000000000068D0000000000800000F5 +:104EB00000000000000000001AC000000000068F83 +:104EC0009E0000000020441100000000CAFEBABE8F +:104ED0000020481100000000000000001AE000005F +:104EE00000000692000000000080000000000000AA +:104EF00000000000006000000000000B0000100037 +:104F000000600411000003150000000000200411DF +:104F1000000000000000000000600811000001B265 +:104F20000000225C0020441100000000000000038B +:104F3000002048110000000000002256002044110B +:104F4000000000000000001B0020481100000000CD +:104F50000000A1FC0020441100000000000000013E +:104F600000204811000000000001A1FDC0204411F4 +:104F7000000000000000002100201E2D00000000A5 +:104F80000000001000221E27000000000000002486 +:104F90000020222D000000000000FFFF0028222832 +:104FA0000000000000000000002949070000000088 +:104FB0000000000000204811000000000000002256 +:104FC0000020222D000000000000FFFF0028222802 +:104FD0000000000000000000002949070000000058 +:104FE0000000000000204811000000000000002325 +:104FF00000201E2D000000000000001000221E27CF +:105000000000000000000000002949070000000027 +:1050100000000000004048110000000000000000F7 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B000014204FF05BD02500000000001C3016867 +:1052C000043F05BD00000000022502090250015103 +:1052D000000000000223024502A00241000000007D +:1052E00003D705BD05BD05BD000000000646064705 +:1052F000031F05BD0000000005BD05C203200340DB +:1053000000000000032A0282034203340000000070 +:1053100005BD05BD05BD05BD0000000005BD054E70 +:1053200005BD05BD0000000003BA05BD04B8034477 +:10533000000000000497044D043D05BD000000007E +:1053400004CD05BD044104DA00000000044D05044D +:10535000035103750000000005BD05BD05BD05BD79 +:105360000000000005BD05BD05BD05BD0000000035 +:1053700005BD05BD063C05C40000000005BD05BD1A +:10538000000705BD0000000005BD05BD05BD05BD4C +:105390000000000005BD05BD05BD05BD0000000005 +:1053A00003F803ED0408040600000000040E040ADC +:1053B000040C041000000000041C04180424042041 +:1053C00000000000042C0428043404300000000015 +:1053D00005BD05BD043805BD0000000005BD05BDC7 +:1053E00005BD05BD0000000005BD05BD05BD05BD31 +:1053F000000000000002067606940006000000008F +:00000001FF diff --git a/firmware/radeon/RV630_pfp.bin.ihex b/firmware/radeon/RV630_pfp.bin.ihex new file mode 100644 index 0000000..f55292c --- /dev/null +++ b/firmware/radeon/RV630_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000CA040000A00000007E828B007C038BED +:10001000008001B8007C038B00D4401E00EE001E5F +:1000200000CA040000A00000007E828B00C41838C3 +:1000300000CA240000CA2800009581A800C41C3A08 +:1000400000C3C00000CA080000CA0C00007C744B4A +:1000500000C200050099C00000C41C3A007C744C2A +:1000600000C0FFF000042C0400309002007D250049 +:1000700000351402007D350B00255403007CD5802B +:1000800000259C030095C00400D5001B007EDDC147 +:10009000007D9D8000D6801B00D5801B00D4401EB3 +:1000A00000D5401E00D6401E00D6801E00D4801E03 +:1000B00000D4C01E009783D300D5C01E00CA08001C +:1000C0000080001A00CA0C0000E4011E00D4001ECB +:1000D0000080000C00C4183800E4013E00D4001E6B +:1000E0000080000C00C4183800D4401E00EE001E32 +:1000F00000CA040000A00000007E828B00E4011E04 +:1001000000D4001E00D4401E00EE001E00CA0400F1 +:1001100000A00000007E828B00E4013E00D4001E9F +:1001200000D4401E00EE001E00CA040000A0000023 +:10013000007E828B00CA180000D4401E00D5801EAD +:100140000080005300D4007500D4401E00CA08008F +:1001500000CA0C0000CA100000D4801900D4C018D6 +:1001600000D5001700D4801E00D4C01E00D5001E8C +:1001700000E2001E00CA040000A00000007E828B86 +:1001800000CA080000D4806000D4401E0080000037 +:1001900000D4801E00CA080000D4806100D4401E34 +:1001A0000080000000D4801E00CA080000CA0C00B5 +:1001B00000D4401E00D4801600D4C01600D4801E87 +:1001C000008001B800D4C01E00C6084300CA0C005D +:1001D00000CA10000094800400CA140000E420F358 +:1001E00000D4201300D5606500D4E01C00D5201C8D +:1001F00000D5601C008000000006200100C60843F6 +:1002000000CA0C0000CA1000009483F700CA140052 +:1002100000E420F30080007900D4201300C60843D6 +:1002200000CA0C0000CA1000009883EF00CA140036 +:1002300000D400640080008D0000000000C414326F +:1002400000C6184300C4082F0095400500C40C30B8 +:1002500000D4401E0080000000EE001E009583F5D3 +:1002600000C4103100D4403300D5206500D4A01C58 +:1002700000D4E01C00D5201C00E4015E00D4001E68 +:10028000008000000006200100CA1800000A2001BA +:1002900000D6007600C408360098800700C61045D6 +:1002A0000095011000D4001F00D46062008000009F +:1002B00000D4206200CC383500CC1433008401BB5C +:1002C00000D4007200D5401E0080000000EE001E29 +:1002D00000E2001A008401BB00E2001A00CC104BBF +:1002E00000CC0447002C9401007D098B0098400548 +:1002F000007D15CB00D4001A008001B800D4006D39 +:100300000034440100CC0C480098403A00CC2C4A00 +:100310000095800400CC0449008001B800D4001A84 +:1003200000D4C01A00282801008400F000CC10037B +:100330000098801B0004380C008400F000CC1003EF +:100340000098801700043808008400F000CC1003E7 +:100350000098801300043804008400F000CC1003DF +:100360000098801400CC104C009A800900CC144DE9 +:10037000009840DC00D4006D00CC184800D5001A6D +:1003800000D5401A008000C900D5801A0096C0D55B +:1003900000D4006D008001B800D4006E009AC00344 +:1003A00000D4006D00D4006E0080000000EC007FDF +:1003B000009AC0CC00D4006D008001B800D4006E5B +:1003C00000CC140300CC180300CC1C03007D910367 +:1003D000007DD583007D190C0035CC1F0035701FC2 +:1003E000007CF0CB007CD08B00880000007E8E8BE0 +:1003F0000095C00400D4006E008001B800D4001A3B +:1004000000D4C01A00CC080300CC0C0300CC1003AD +:1004100000CC140300CC180300CC1C0300CC240334 +:1004200000CC28030035C41F0036B01F007C704B81 +:100430000034F01F007C704B0035701F007C704B47 +:10044000007D8881007DCCC1007E5101007E9541F8 +:10045000007C9082007CD4C2007C848B009AC00314 +:10046000007C8C8B002C88010098809E00D4006D4D +:100470000098409C00D4006E00CC084C00CC0C4D81 +:1004800000CC104800D4801A00D4C01A00800101AA +:1004900000D5001A00CC083200D40032009482D972 +:1004A00000CA0C0000D4401E0080000000D4001ED2 +:1004B00000E4011E00D4001E00CA080000CA0C009F +:1004C00000CA100000D4401E00CA140000D4801ED0 +:1004D00000D4C01E00D5001E00D5401E00D54034FB +:1004E0000080000000EE001E0028040400E2001A54 +:1004F00000E2001A00D4401A00CA380000CC0803F9 +:1005000000CC0C0300CC0C0300CC0C03009882BD83 +:1005100000000000008401BB00D7A06F0080000035 +:1005200000EE001F00CA040000C2FF0000CC083427 +:1005300000C13FFF007C74CB007CC90B007D010F24 +:10054000009902B0007C738B008401BB00D7A06FC0 +:100550000080000000EE001F00CA080000281900FB +:10056000007D898B009580140028140400CA0C00BB +:1005700000CA100000CA1C0000CA240000E2001FCC +:1005800000D4C01A00D5001A00D5401A00CC1803B8 +:1005900000CC2C0300CC2C0300CC2C03007DA58BBD +:1005A000007D9C4700984297000000000080016198 +:1005B00000D4C01A00D4401E00D4801E0080000069 +:1005C00000EE001E00E4011E00D4001E00D4401EF8 +:1005D00000EE001E00CA040000A00000007E828B16 +:1005E00000E4013E00D4001E00D4401E00EE001EB8 +:1005F00000CA040000A00000007E828B00CA080030 +:1006000000248C06000CCC060098C00600CC104ECE +:100610000099000400D4007300E4011E00D4001E01 +:1006200000D4401E00D4801E0080000000EE001E9A +:1006300000CA080000CA0C000034D01800251001C0 +:100640000095002100C17FFF00CA100000CA1400FD +:1006500000CA180000D4801D00D4C01D007DB18BDD +:1006600000C1420200C2C00100D5801D0034DC0E72 +:10067000007D5D4C007F734C00D7401E00D5001EEE +:1006800000D5401E00C1420000C2C00000099C010C +:100690000031DC10007F5F4C007F734C00042802A7 +:1006A000007D838000D5A86F00D5806600D7401EEE +:1006B00000EC005E00C8240200C82402008001B8DB +:1006C00000D6007600D4401E00D4801E00D4C01E88 +:1006D0000080000000EE001E0080000000EE001F01 +:1006E00000D4001F0080000000D4001F00D4001FB1 +:1006F0000088000000D4001F00000000000000007F +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000010171000201780003008F0004007FE5 +:10081000000500030006003F000700320008012C1D +:1008200000090046000A0036001001B6001700A2B9 +:100830000022013A00230149002000B400240125D0 +:100840000027004D0028006A002A0060002B00529B +:10085000002F0065003200870034017F003C015604 +:10086000003F00720041018C0044012E00550173CD +:100870000056017A0060000B00610034006200380D +:1008800000630038006400380065003800660038F6 +:10089000006700380068003A00690041006A0048BB +:1008A000006B0048006C0048006D0048006E004876 +:1008B000006F00480000000600000006000000066F +:1008C0000000000600000006000000060000000610 +:1008D0000000000600000006000000060000000600 +:1008E00000000006000000060000000600000006F0 +:1008F00000000006000000060000000600000006E0 +:00000001FF diff --git a/firmware/radeon/RV635_me.bin.ihex b/firmware/radeon/RV635_me.bin.ihex new file mode 100644 index 0000000..ba3a7e6 --- /dev/null +++ b/firmware/radeon/RV635_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A000006044110000068A0000000000600000AB +:1000B0000000062E00000000006000000000064264 +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E000000000000000001800203625000000007D +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000002800204A2D8B +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000001900203625C9 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001700200E2D5A +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001718 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000270020362410 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:10038000000000000000000E0020362300000000E6 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E23000000000000000FC9 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000002700204A2D000000004F +:1003F000000000000020481100000000000000295B +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A00000000000002048040000000000000030AF +:1005B0000020162D00000000000000020029162572 +:1005C0000000000000000030002036250000000080 +:1005D000000000250020162D000000000000000093 +:1005E000002F00A300000000000000000CC000006D +:1005F00000000083000000260020162D00000000EF +:1006000000000000002F00A4000000000000000017 +:100610000CC000000000008400000000004000004A +:100620000000008A000000250020362300000000A2 +:100630000000002600203624000000000000001703 +:1006400000201E2D000000000000000200210227F3 +:10065000000000000000000014E000000000008A1C +:1006600000000000006000000000066500000000BF +:1006700000600000000006590000000200210E2268 +:10068000000000000000000014C000000000008D09 +:1006900000000012C040362000000093000000005F +:1006A0002EE0000000000091000000002CE000009F +:1006B000000000900000000200400E2D000000929B +:1006C0000000000300400E2D000000920000000C0E +:1006D00000200E2D00000000000000120020362334 +:1006E000000000000000000300210E2200000000B6 +:1006F0000000000014C00000000000980000A00CE2 +:10070000002044110000000000000000C02048004C +:100710000000000000000000C0404800000000A0F1 +:100720000000A00C002044110000000000000000A8 +:100730000020481100000000000000002EE0000032 +:100740000000009E000000002CE000000000009D62 +:100750000000000200400E2D0000009F000000037A +:1007600000400E2D0000009F0000000C00200E2D08 +:10077000000000000000000000204803000000000E +:1007800000000000003A0C0200000000003F0000E2 +:1007900000280E23000000000000001000210E239E +:1007A00000000000000000110020362300000000BF +:1007B0000000001E0021022B0000000000000000CD +:1007C00014C00000000000A700000016C020362062 +:1007D000000000000000001F0021022B00000000AC +:1007E0000000000014C00000000000AA0000001576 +:1007F000C0203620000000000000000800210E2B61 +:10080000000000000000007F00280E230000000010 +:1008100000000000002F0223000000000000000084 +:100820000CE00000000000E10000000027000000D4 +:10083000000000000000000000600000000002A3B3 +:1008400000000001002F0223000000000000000053 +:100850000AE00000000000B300000000006000009B +:100860000000013A81000000002044110000000057 +:100870000000000600204811000000000000000CED +:1008800000221E300000000099800000002044116A +:1008900000000000000000040020122D00000000F5 +:1008A00000000008002212240000000000000010D8 +:1008B00000201811000000000000000000291CE4C6 +:1008C0000000000000000000006048070000012F49 +:1008D0009B00000000204411000000000000000008 +:1008E00000204802000000009C000000002044118D +:1008F00000000000000000000033146F0000000042 +:100900000000000100333E23000000000000000052 +:10091000D9004800000000000000000000203C0555 +:1009200000000000810000000020441100000000D1 +:100930000000000E00204811000000000000000030 +:1009400000201010000000000000E007002044110B +:10095000000000000000000F0021022B000000003A +:100960000000000014C00000000000CB00F8FF08E9 +:1009700000204811000000009800000000404811CD +:10098000000000DC000000F000280E220000000043 +:10099000000000A0002F0223000000000000000063 +:1009A0000CC00000000000DA0000001100200E2D35 +:1009B0000000000000000001002F022300000000E2 +:1009C000000000000CE00000000000D50000000264 +:1009D000002F022300000000000000000CE00000D7 +:1009E000000000D400003F0000400C11000000D6C1 +:1009F00000001F0000400C11000000D600000F0096 +:100A000000200C11000000000038000900294A23D2 +:100A1000000000003F00000000280E2B0000000036 +:100A20000000000200220E2300000000000000076A +:100A300000494A23000000DC00380F09002048115B +:100A400000000000680000070020481100000000BE +:100A50000000000800214A270000000000000000FC +:100A60000020481100000000060A020000294A2464 +:100A700000000000000000000020481100000000FD +:100A80000000000000204811000000000000A20249 +:100A9000002044110000000000FF000000280E228A +:100AA000000000000000008000294A230000000030 +:100AB0000000002700200E2D00000000000000268E +:100AC0000020122D0000000000000000002F008315 +:100AD00000000000000000000CE00000000000EA40 +:100AE00000000000006000000000065F0000000041 +:100AF00000400000000000EB00000000006000006B +:100B000000000662000000070020222D0000000007 +:100B10000000000500220E2200000000001000006E +:100B200000280E23000000000000000000292068BB +:100B30000000000000000000003A0C02000000006D +:100B4000000000EF00280E2300000000000000005D +:100B500000292068000000000000001700200E2D72 +:100B6000000000000000000300210223000000003C +:100B70000000000014E00000000000F80000000B7E +:100B800000210228000000000000000014C0000046 +:100B9000000000F8000004000029222800000000E6 +:100BA0000000001400203628000000000000001C97 +:100BB00000210E22000000000000000014C0000010 +:100BC000000000FD0000A30C002044110000000004 +:100BD0000000000000204811000000000000001E7E +:100BE00000210E22000000000000000014C00000E0 +:100BF0000000010B0000A30F0020441100000000C2 +:100C00000000001100200E2D000000000000000177 +:100C1000002F022300000000000000000CC00000B4 +:100C200000000104FFFFFFFF004048110000010B1E +:100C300000000002002F022300000000000000005E +:100C40000CC00000000001070000FFFF0040481139 +:100C50000000010B00000004002F02230000000030 +:100C6000000000000CC000000000010A000000FFAE +:100C7000004048110000010B000000010020481155 +:100C8000000000000002C400002044110000000029 +:100C90000000001F00210E220000000000000000E4 +:100CA00014C00000000001120000001040210E20BE +:100CB00000000000000000130020362300000000A8 +:100CC0000000001840224A20000000000000001030 +:100CD000C0424A20000001140000000000200C1156 +:100CE0000000000000000013002036230000000078 +:100CF000000000000020481100000000000000007B +:100D000000204811000000000000000A002010111F +:100D10000000000000000000002F0224000000007E +:100D2000000000000CE000000000011B00000000BB +:100D300000204811000000000000000100531224B0 +:100D400000000117FFBFFFFF00283A2E000000003F +:100D50000000001B00210222000000000000000033 +:100D600014C000000000012E81000000002044118A +:100D7000000000000000000D0020481100000000ED +:100D80000000001800220E3000000000FC000000EF +:100D900000280E2300000000810000000020441104 +:100DA000000000000000000E0020481100000000BC +:100DB0000000000000201010000000000000E00E05 +:100DC000002044110000000007F8FF08002048112F +:100DD000000000000000000000294A23000000007D +:100DE0000000001C00201E2D000000000000000874 +:100DF00000214A27000000000000000000204811E8 +:100E000000000000060A020000294A240000000039 +:100E10000000000000204811000000000000000059 +:100E200000204811000000000000000000800000C9 +:100E300000000000810000000020441100000000BC +:100E40000000000100204811000000000000217C8B +:100E50000020441100000000008000000020481124 +:100E60000000000000000000002048060000000014 +:100E70000000000800214A270000000000000000D8 +:100E800017000000000000000004217F00604411F2 +:100E90000000068A0000001F002102300000000050 +:100EA0000000000014C000000000068900000004DB +:100EB00000404C1100000135810000000020441169 +:100EC00000000000000000010020481100000000A8 +:100ED000000021F800204411000000000000001C68 +:100EE0000020481100000000000421F900604411B6 +:100EF0000000068A000000110021023000000000FE +:100F00000000000014E000000000013C00000000B0 +:100F100000800000000000000000000000600000F1 +:100F20000000000B00000000006004110000031529 +:100F3000000000000020041100000000000000007C +:100F400000600811000001B2000000000060000015 +:100F5000000001600000FFFF40280E20000000009C +:100F600000000010C0211220000000000000FFFF60 +:100F7000402806200000000000000010C0210A20C8 +:100F800000000000000000000034146100000000B8 +:100F90000000000000741882000002BB0001A1FDE7 +:100FA00000604411000002E000003FFF002F022F0C +:100FB00000000000000000000CC00000000001471D +:100FC00000000000C040040000000001000000001C +:100FD000006000000000000B000000000060041131 +:100FE00000000315000000000020041100000000B4 +:100FF0000000000000600811000001B200003FFF87 +:10100000002F022F00000000000000000CE0000094 +:10101000000000000000000000600000000001600F +:101020000000001040210E20000000000000FFFF23 +:10103000C0281220000000000000001040211620EF +:10104000000000000000FFFFC0681A20000002BB83 +:101050000001A1FD00604411000002E000003FFF1C +:10106000002F022F00000000000000000CC0000054 +:101070000000015800000000C04004000000000112 +:101080000000225C0020441100000000000000016C +:1010900000300A2F000000000000000100210A2299 +:1010A000000000000000000300384A220000000099 +:1010B0000000225600204411000000000000001A29 +:1010C00000204811000000000000A1FC0020441195 +:1010D0000000000000000001008048110000000036 +:1010E00000000000006000000000000B0000000095 +:1010F000006000000000018F0000000000600000A0 +:10110000000001A000003FFF002F022F00000000A0 +:10111000000000000CE000000000000000000000E3 +:1011200000202C0800000000000000000020241116 +:101130000000000000000000002028110000000056 +:10114000000022560020441100000000000000169C +:1011500000204811000000000000225C0020441123 +:101160000000000000000003002048110000000003 +:1011700093800000002044110000000000000002E5 +:1011800000221E290000000000000000007048EB53 +:101190000000019C0000000000600000000002BB95 +:1011A00000000001403306200000000000000000A5 +:1011B000C03024090000000000003FFF002F022F74 +:1011C00000000000000000000CE000000000000033 +:1011D0000000000000600000000002A3000000000A +:1011E000002F022100000000000000000AE00000C3 +:1011F0000000018100000000006000000000013AD2 +:101200000000000000400000000001869500000082 +:10121000002044110000000000000000002F022107 +:1012200000000000000000000CE00000000001864B +:1012300000000000C0204800000000000000000185 +:10124000005306210000018292000000002044119A +:101250000000000000000000C0604800000001978E +:101260000001A1FD00204411000000000000001159 +:101270000020062D00000000000000000078042A75 +:10128000000002FB00000000002028090000000010 +:1012900000003FFF002F022F0000000000000000B0 +:1012A0000CC000000000017400000000C0400400F9 +:1012B000000000010000021000600411000003158E +:1012C00000003FFF002F022F000000000000000080 +:1012D0000CE000000000019400000015C020362042 +:1012E0000000000000000016C020362000000000B2 +:1012F0003F800000002004110000000046000000B4 +:1013000000600811000001B2000000000080000031 +:10131000000000000000A1FC0020441100000000BB +:1013200000003FFF002F022F00000000000000001F +:101330000CC000000000019B00000001008048116B +:1013400000000000000000210080481100000000A3 +:101350000000FFFF40280E200000000000000010E9 +:10136000C0211220000000000000FFFF40281620CE +:101370000000000000000010C0811A2000000000E2 +:101380008100000000204411000000000000000661 +:1013900000204811000000000000000800221E305C +:1013A000000000000000002900201A2D00000000AD +:1013B0000000E0000020441100000000FFFBFF09D6 +:1013C00000204811000000000000000F0020222D26 +:1013D0000000000000001FFF00294A280000000054 +:1013E000000000060020222D000000000000000088 +:1013F000002920E80000000000000000002048084C +:101400000000000000000000002048110000000063 +:10141000060A020000294A26000000000000000021 +:1014200000204811000000000000000000204811CA +:101430000000000000000100002018110000000062 +:101440000000000800621E280000012F00000008B4 +:1014500000822228000000000002C0000020441189 +:10146000000000000000001500600E2D000001BD0E +:101470000000001600600E2D000001BD0000C00835 +:1014800000204411000000000000001700200E2D75 +:10149000000000000000000014C00000000001B9BE +:1014A0000000000000200411000000000000000007 +:1014B0000020480100000000390000000020481111 +:1014C00000000000000000000020481100000000A3 +:1014D000000000000080480200000000000000182A +:1014E00000202E2D0000000000000000003B0D63D6 +:1014F000000000000000000800224A230000000055 +:101500000000001000224A23000000000000001824 +:1015100000224A2300000000000000000080480371 +:101520000000000000000000006000000000000B50 +:10153000000010000060041100000315000000000E +:1015400000200411000000000000000000600811ED +:10155000000001B2000000070021062F000000007B +:101560000000001300200A2D000000000000000110 +:1015700000202C11000000000000FFFF4028222066 +:10158000000000000000000F0026222800000000DC +:101590000000001040212620000000000000000F85 +:1015A000002626290000000000000000002028027C +:1015B000000000000000225600204411000000003E +:1015C0000000001B00204811000000000000000087 +:1015D000002F022100000000000000000CE00000CD +:1015E000000001E00000225C002044110000000027 +:1015F0000000008100204811000000000000A1FC54 +:1016000000204411000000000000000100204811EB +:10161000000000000000008000201C1100000000FD +:1016200000000000002F0227000000000000000062 +:101630000CE00000000001DC000000000060000081 +:10164000000001E90000000100531E27000001D83E +:101650000000000100202C11000000000000001F0D +:1016600000280A22000000000000001F00282A2A8B +:10167000000000000000000100530621000001D11D +:101680000000225C00204411000000000000000265 +:1016900000304A2F000000000000A1FC002044118F +:1016A00000000000000000010020481100000000C0 +:1016B0000000000100301E2F0000000000000000AC +:1016C000002F022700000000000000000CE00000D6 +:1016D000000000000000000000600000000001E9C0 +:1016E0000000000100531E27000001E50000FFFF7D +:1016F00040280E20000000000000000F00260E23EE +:101700000000000000000010C021122000000000B6 +:101710000000000F0026122400000000000000005E +:1017200000201411000000000000000000601811EB +:10173000000002BB0001A1FD0020441100000000D8 +:1017400000000000002F022B00000000000000003D +:101750000CE00000000001F8000000100022162834 +:1017600000000000FFFF0000002816250000000018 +:101770000000FFFF00281A29000000000000000000 +:10178000002948C500000000000000000020480AB1 +:10179000000000000000000000202C1100000000EC +:1017A000000000100022162300000000FFFF0000D0 +:1017B00000281625000000000000FFFF00281A2462 +:1017C0000000000000000000002948C500000000E3 +:1017D0000000000000731503000002050000000077 +:1017E0000020180500000000000000000073152410 +:1017F0000000020500000000002D14C500000000DC +:1018000000000000003008A20000000000000000FE +:101810000020480200000000000000000020280214 +:101820000000000000000000002020030000000075 +:101830000000000000802404000000000000000FF1 +:1018400000210225000000000000000014C000007C +:101850000000068900000000002B140500000000B5 +:1018600000000001009016250000000000000000AC +:10187000006000000000000B000000000060041188 +:10188000000003150000000000200411000000000B +:101890000000000000600811000001B200002256A4 +:1018A00000204411000000000000001A00294A2214 +:1018B0000000000000000000C02000000000000048 +:1018C00000003FFF002F022F00000000000000007A +:1018D0000CE000000000000000000000C020040038 +:1018E000000000000000225C002044110000000005 +:1018F0000000000300384A21000000000000A1FCA5 +:1019000000204411000000000000000100204811E8 +:10191000000000000000FFFF40281220000000002F +:1019200000000010C0211A20000000000000FFFF8E +:1019300040280E200000000000000010C0211620EA +:10194000000000000000000000741465000002BBED +:101950000001A1FD00604411000002E00000000150 +:10196000003306210000000000000000002F0221CB +:1019700000000000000000000CC000000000021980 +:1019800000003FFF002F022F0000000000000000B9 +:101990000CC000000000021200000000C040040063 +:1019A000000000010000000000600000000006428E +:1019B000000000000040040F0000021300000000BF +:1019C000006000000000062E000000000060000023 +:1019D0000000064200000210006004110000031520 +:1019E0000000000000600000000001A000000000F6 +:1019F000006000000000019C00000000006000008A +:101A0000000002BB0000000000600000000002A314 +:101A1000938000000020441100000000000000003E +:101A2000002048080000000000000000002F022FE6 +:101A300000000000000000000AE000000000023288 +:101A400000000000006000000000013A00000000FB +:101A50000040000000000236950000000020441104 +:101A60000000000000000000002F022F0000000016 +:101A7000000000000CE00000000002360000000042 +:101A8000C0404800000002339200000000204411D2 +:101A90000000000000000000C0204800000000001E +:101AA0000000225600204411000000000000001633 +:101AB00000204811000000000000225C00204411BA +:101AC000000000000000000300204811000000009A +:101AD0000000A1FC002044110000000000000001F3 +:101AE00000204811000000000001A1FD0020441169 +:101AF000000000000000000000600411000002FB74 +:101B000000000000C04004000000000100000000D0 +:101B1000006000000000062E0000A00C0020441110 +:101B20000000000000000000C0204800000000008D +:101B300000000000C040480000000000000000005D +:101B4000006000000000000B0000001840210A2087 +:101B50000000000000000003002F0222000000002F +:101B6000000000000AE000000000024C0000001429 +:101B70000020222D00000000000801010029222879 +:101B800000000000000000140020362800000000C3 +:101B90000000A30C00204411000000000000000021 +:101BA000C02048000000000000000000C0204800E5 +:101BB0000000000000000000C0404800000002518A +:101BC00000000000006000000000000B000000109A +:101BD00000600411000003153F8000000020041184 +:101BE000000000000000000000600811000001B2C9 +:101BF0000000225C002044110000000000000003EF +:101C000000204811000000000000000000600000FB +:101C10000000027C0000001700201E2D00000000C4 +:101C20000000000100211E2700000000000000004D +:101C300014E000000000026A0000001200201E2DC7 +:101C4000000000000000FFFF00281E270000000029 +:101C50000000000000341C2700000000000000000D +:101C600012C000000000025F0000000000201C11F4 +:101C70000000000000000000002F00E50000000050 +:101C80000000000008C00000000002620000000028 +:101C900000201407000000000000001200201E2D8C +:101CA000000000000000001000211E2700000000BE +:101CB0000000000000341C4700000000000000008D +:101CC00012C00000000002670000000000201C118C +:101CD0000000000000000000002F00E600000000EF +:101CE0000000000008C000000000026A00000000C0 +:101CF0000020180700000000000000000060000045 +:101D0000000002C100002256002044110000000023 +:101D1000000000000034202300000000000000004C +:101D200012C00000000002720000000000342044D5 +:101D3000000000000000000012C00000000002715E +:101D40000000001600404811000002760000001854 +:101D500000404811000002760000000000342044DA +:101D6000000000000000000012C00000000002752A +:101D70000000001700404811000002760000001922 +:101D800000204811000000000000A1FC00204411C8 +:101D900000000000000000010020481100000000C9 +:101DA0000001A1FD00604411000002E900003FFFB6 +:101DB000002F022F00000000000000000CC00000F7 +:101DC0000000025600000000C040040000000001B6 +:101DD0000000001040210620000000000000FFFF6E +:101DE000C0280A20000000000000001040210E2042 +:101DF000000000000000FFFFC028122000000000CB +:101E00000000001040211620000000000000FFFF2D +:101E1000C0881A200000000081000000002044114A +:101E20000000000000000001002048110000000038 +:101E300000042004006044110000068A0000000035 +:101E4000006000000000062E00000000C0600000DE +:101E5000000002A30000000500200A2D0000000081 +:101E60000000000800220A22000000000000002BF1 +:101E700000201A2D000000000000001C00201E2D74 +:101E8000000000000000700000281E270000000075 +:101E90000000000000311CE6000000000000002AE5 +:101EA00000201A2D000000000000000C00221A265D +:101EB0000000000000000000002F00E6000000000D +:101EC0000000000006E00000000002920000000098 +:101ED00000201C11000000000000000000200C1178 +:101EE000000000000000002B00203623000000004E +:101EF0000000001000201811000000000000000089 +:101F000000691CE20000012F9380000000204411B2 +:101F10000000000000000000002048070000000052 +:101F200095000000002044110000000000000000A7 +:101F3000002F022F00000000000000000CE0000055 +:101F40000000029D0000000100333E2F0000000051 +:101F500000000000D90048000000000092000000CE +:101F6000002044110000000000000000C0204800D4 +:101F7000000000000000001C0040362700000000A8 +:101F80000000000CC0220A20000000000000002910 +:101F9000002036220000000000000028C04036204B +:101FA000000000000000A2A4002044110000000076 +:101FB000000000090020481100000000A1000000FE +:101FC00000204411000000000000000100804811C2 +:101FD000000000000000002100201E2D0000000075 +:101FE00000000000002C1CE30000000000000021A5 +:101FF00000203627000000000000002200201E2DD7 +:102000000000000000000000002C1CE400000000A4 +:1020100000000022002036270000000000000023FE +:1020200000201E2D0000000000000000003120A351 +:102030000000000000000000002D1D07000000004F +:1020400000000023002036270000000000000024CC +:1020500000201E2D0000000000000000003120C400 +:102060000000000000000000002D1D07000000001F +:10207000000000240080362700000000000000213E +:10208000002036230000000000000022002036243B +:10209000000000000000000000311CA30000000050 +:1020A0000000002300203627000000000000000090 +:1020B00000311CC40000000000000024008036270E +:1020C000000000000000001A002036270000000079 +:1020D0000000001B00203628000000000000001750 +:1020E00000201E2D00000000000000020021022739 +:1020F000000000000000000014C00000000002DC2E +:102100000000000000400000000002D90000001A9A +:1021100000203627000000000000001B00203628A9 +:10212000000000000000001700201E2D000000002D +:102130000000000200210227000000000000000053 +:1021400014E00000000002D9000000030021022773 +:10215000000000000000000014E00000000002DCAD +:102160000000002300201E2D0000000000000000E1 +:10217000002E00E1000000000000000002C000008E +:10218000000002DC0000002100201E2D00000000E5 +:1021900000000000003120A100000000000000004D +:1021A000002E00E8000000000000000006C0000053 +:1021B000000002DC0000002400201E2D00000000B2 +:1021C00000000000002E00E20000000000000000FF +:1021D00002C00000000002DC0000002200201E2DD2 +:1021E0000000000000000000003120C200000000DC +:1021F00000000000002E00E80000000000000000C9 +:1022000006C00000000002DC0000000000600000CA +:10221000000006650000000000600000000002B53C +:102220000000000000400000000002DE000000008E +:1022300000600000000002B5000000000060000027 +:102240000000065C0000000000400000000002DE0C +:102250000000000000600000000002A70000000075 +:1022600000400000000002DE0000001A00201E2DC9 +:10227000000000000000001B0080222D0000000074 +:102280000000001000221E230000000000000000DB +:1022900000294887000000000000000000311CA356 +:1022A000000000000000001000221E2700000000B7 +:1022B0000000000000294887000000000000001016 +:1022C00000221E230000000000000000003120C496 +:1022D000000000000000FFFF00282228000000008E +:1022E0000000000000894907000000000000001005 +:1022F00000221E2300000000000000000029488783 +:10230000000000000000001000221E21000000005C +:102310000000000000294847000000000000000005 +:1023200000311CA3000000000000001000221E2746 +:1023300000000000000000000029488700000000A5 +:102340000000000000311CA100000000000000108F +:1023500000221E270000000000000000002948475E +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:10239000000000000000001000221E2100000000CC +:1023A00000000000003120C2000000000000FFFF1C +:1023B00000282228000000000000000000894907D2 +:1023C000000000000000001000221E23000000009A +:1023D0000000000000294887000000000000000104 +:1023E00000220A210000000000000000003308A2C3 +:1023F000000000000000001000221E22000000006B +:102400000000001000212222000000000000000057 +:1024100000294907000000000000000000311CA353 +:10242000000000000000001000221E270000000035 +:1024300000000000002948870000000000000001A3 +:1024400000220A210000000000000000003008A265 +:10245000000000000000001000221E22000000000A +:1024600000000010002122220000000000000000F7 +:1024700000294907000000000000001000221E2370 +:102480000000000000000000003120C40000000037 +:102490000000FFFF002822280000000000000000CC +:1024A000002949070000000000000000003808C5AE +:1024B00000000000000000000030084100000000A3 +:1024C0000000000100220A220000000000000000BD +:1024D000003308A2000000000000001000221E22AD +:1024E0000000000000000010002122220000000077 +:1024F00000000000008949070000000000000017EC +:102500000020222D000000000000000014C0000088 +:1025100000000318FFFFFFEF002806210000000065 +:10252000000000140020222D000000000000F8E050 +:1025300000204411000000000000000000294901B3 +:1025400000000000000000000089490100000000B8 +:102550000000000000204811000000000000000002 +:102560000020481100000000060A02000080481107 +:102570000000000000000000C0200000000000007B +:1025800097000000C020441100000000000000007F +:10259000C0204811000000008A0000000020441103 +:1025A00000000000000000000020481100000000B2 +:1025B0000000225C00204411000000000000000028 +:1025C000C0204800000000000000A1FC00204411D1 +:1025D0000000000000000000C020480000000000D3 +:1025E00000000000C0200400000000000000000007 +:1025F00000A0000A00000000970000000020441125 +:102600000000000000000000002048110000000051 +:102610008A000000002044110000000000000000BB +:1026200000204811000000000000225C002044113E +:102630000000000000000000C02048000000000072 +:102640000000A1FC00204411000000000000000078 +:10265000C02048000000000000000000C02004006E +:10266000000000000000000000A0000A00000000C0 +:10267000970000000020441100000000000000004E +:1026800000204811000000008A00000000204411D2 +:1026900000000000000000000020481100000000C1 +:1026A0000000225C00204411000000000000000037 +:1026B000C0204800000000000000A1FC00204411E0 +:1026C0000000000000000000C020480000000000E2 +:1026D0000001A1FD002044110000000000000000E6 +:1026E000D90048000000000000000000C0200400E5 +:1026F000000000000000000000A0000A0000000030 +:1027000000002257002044110000000000000003D8 +:10271000C0484A20000000000000225D0020441153 +:102720000000000000000000C04048000000000061 +:1027300000000000006000000000064200000000F1 +:10274000C0200800000000000000225C00204411AE +:10275000000000000000000300384A2200000000D2 +:102760000000A1FC00204411000000000000000057 +:10277000C0204800000000000001A1FD002044111D +:102780000000000000000000002F022200000000F6 +:10279000000000000CE0000000000000000000004D +:1027A00040204800000000000000000140304A20A6 +:1027B0000000000000000002C0304A2000000000BD +:1027C0000000000100530A220000034B0000003FFC +:1027D000C0280A20000000008100000000204411F1 +:1027E000000000000000000100204811000000006F +:1027F000000021F800204411000000000000001833 +:102800000020481100000000000421F9006044117C +:102810000000068A000000110021023000000000C4 +:102820000000000014E00000000003540000001449 +:10283000002F022200000000000000000CC0000079 +:10284000000003640000201000204411000000007C +:102850000000800000204811000000000001A2A438 +:102860000020441100000000000000000060480249 +:102870000000036E00002100002044110000000051 +:1028800000000000C0204800000000000000000020 +:10289000C02048000000000000000000C0204800E8 +:1028A0000000000000000000C040480000000000E0 +:1028B00000000004002F02220000000000000000C1 +:1028C0000CC000000000036A00002010002044112A +:1028D00000000000000080000020481100000000FF +:1028E0000001A2A40020441100000000000000002C +:1028F000004048020000035F00000028002F022271 +:1029000000000000000000000CC00000000005BD39 +:102910000001A2A4002044110000000000000000FB +:10292000004048020000035F0000002C0020362613 +:102930000000000000000049002018110000000005 +:102940000000003F002048110000000000000001CE +:1029500000331A260000000000000000002F0226AD +:1029600000000000000000000CC000000000037028 +:102970000000002C00801A2D000000000000003F25 +:10298000C0280A200000000000000015002F0222CD +:1029900000000000000000000CE0000000000386C2 +:1029A00000000006002F02220000000000000000CE +:1029B0000CE00000000003B100000016002F02220E +:1029C00000000000000000000CE00000000003B563 +:1029D00000000020002F0222000000000000000084 +:1029E0000CE000000000039C0000000F002F0222FA +:1029F00000000000000000000CE00000000003A840 +:102A000000000010002F0222000000000000000063 +:102A10000CE00000000003A80000001E002F0222AE +:102A200000000000000000000CE000000000039027 +:102A30000000A2A4002044110000000000000000DB +:102A400000404802000000000800000000290A229F +:102A5000000000000000000340210E2000000000E4 +:102A60000000000CC021122000000000000800003F +:102A7000002812240000000000000014C0221620CC +:102A80000000000000000000002914A40000000065 +:102A90000000A2A40020441100000000000000007B +:102AA000002948A2000000000000A1FE00204411FF +:102AB000000000000000000000404803000000008B +:102AC000810000000020441100000000000000010F +:102AD0000020481100000000000021F800204411EF +:102AE0000000000000000016002048110000000057 +:102AF000000421F9006044110000068A000000155E +:102B000000210230000000000000000014E000007E +:102B1000000003920000210E00204411000000007C +:102B200000000000C020480000000000000000007D +:102B3000C0204800000000000000A2A400204411B2 +:102B400000000000000000000040480200000000FB +:102B5000810000000020441100000000000000017E +:102B60000020481100000000000021F8002044115E +:102B700000000000000000170020481100000000C5 +:102B8000000421F9006044110000068A00000003DF +:102B900000210230000000000000000014E00000EE +:102BA0000000039E000021080020441100000000E6 +:102BB00000000000C02048000000000000000000ED +:102BC000C0204800000000000000A2A40020441122 +:102BD000000000000000000000404802000000006B +:102BE0000000A2A40020441100000000000000002A +:102BF0000020480200000000800000000020441176 +:102C0000000000000000000000204811000000004B +:102C100081000000002044110000000000000010AE +:102C200000204811000000000000000000200010FB +:102C3000000000000000000014C00000000003AE0F +:102C40000000000000400000000000000000201014 +:102C50000020441100000000000080000020481106 +:102C6000000000000001A2A40020441100000000A8 +:102C70000000000600404811000000000000201085 +:102C800000204411000000000000800000204811D6 +:102C9000000000000001A2A4002044110000000078 +:102CA00000000016006048110000036E00000000E4 +:102CB000004000000000000000000000C0200800EC +:102CC0000000000000000000C0200C000000000018 +:102CD0000000001D00210223000000000000000091 +:102CE00014E00000000003CE810000000020441129 +:102CF000000000000000000100204811000000005A +:102D0000000021F80020441100000000000000181D +:102D10000020481100000000000421F90060441167 +:102D20000000068A000000110021023000000000AF +:102D30000000000014E00000000003C000002100BB +:102D400000204411000000000000000000204802A4 +:102D50000000000000000000002048030000000008 +:102D6000BABECAFE0020481100000000CAFEBABE6A +:102D70000020481100000000000020100020441135 +:102D8000000000000000800000204811000000004A +:102D90000000A2A400204411000000000000000474 +:102DA0000040481100000000000021700020441184 +:102DB00000000000000000000020480200000000A9 +:102DC0000000000000204803000000008100000017 +:102DD00000204411000000000000000A00204811FB +:102DE00000000000000000000020001000000000B3 +:102DF0000000000014C00000000003D38C0000009D +:102E00000020441100000000CAFEBABE0040481174 +:102E100000000000810000000020441100000000BC +:102E200000000001002048110000000000003FFFEA +:102E300040280A20000000008000000040280E20EA +:102E40000000000040000000C02812200000000028 +:102E500000040000006946220000068A000000000D +:102E6000002014100000000000000000002F0223CA +:102E700000000000000000000CC00000000003E1A2 +:102E800000000000C0401800000003E400003FFF05 +:102E9000C0281A2000000000000400000069462637 +:102EA0000000068A0000000000201810000000004A +:102EB00000000000002F02240000000000000000BD +:102EC0000CC00000000003E700000000C0401C0030 +:102ED000000003EA00003FFFC0281E2000000000A1 +:102EE00000040000006946270000068A0000000078 +:102EF00000201C1000000000000000000020440220 +:102F00000000000000000000002820C500000000B4 +:102F100000000000004948E800000000A580000013 +:102F200000200811000000000000200000200C110B +:102F30000000000083000000006044110000041243 +:102F4000000000000020440200000000000000001B +:102F5000C0204800000000000000000040204800A1 +:102F6000000000000000001FC0210220000000003F +:102F70000000000014C00000000003F70000201053 +:102F800000204411000000000000800000204811D3 +:102F9000000000000000FFFFC0481220000003FFF7 +:102FA000A780000000200811000000000000A00021 +:102FB00000200C110000000083000000006044119C +:102FC0000000041200000000002044020000000085 +:102FD00000000000C02048000000000000000000C9 +:102FE000C0204800000000000000FFFFC0281220A1 +:102FF00000000000830000000020441100000000D9 +:103000000000000000304883000000008400000041 +:10301000002044110000000000000000C020480013 +:1030200000000000000000001D0000000000000083 +:103030008300000000604411000004120000000042 +:10304000C040040000000001A98000000020081119 +:10305000000000000000C00000400C11000003FA56 +:10306000AB80000000200811000000000000F8E024 +:1030700000400C11000003FAAD8000000020081190 +:10308000000000000000F88000400C11000003FA6E +:10309000B380000000200811000000000000F3FCD5 +:1030A00000400C11000003FAAF800000002008115E +:1030B000000000000000E00000400C11000003FAD6 +:1030C000B180000000200811000000000000F000A6 +:1030D00000400C11000003FA83000000002044119E +:1030E00000000000000021480020481100000000FE +:1030F00084000000002044110000000000000000D7 +:10310000C020480000000000000000001D0000007A +:10311000000000000000000000800000000000002F +:1031200001182000C0304620000000000000000010 +:10313000D90048000000000000000000C02004008A +:10314000000000000000000000A0000A00000000D5 +:103150000218A000C030462000000000000000005F +:10316000D90048000000000000000000C02004005A +:10317000000000000000000000A0000A00000000A5 +:103180000318C000C030462000000000000000000E +:10319000D90048000000000000000000C02004002A +:1031A000000000000000000000A0000A0000000075 +:1031B0000418F8E0C03046200000000000000000C5 +:1031C000D90048000000000000000000C0200400FA +:1031D000000000000000000000A0000A0000000045 +:1031E0000518F880C03046200000000000000000F4 +:1031F000D90048000000000000000000C0200400CA +:10320000000000000000000000A0000A0000000014 +:103210000618E000C030462000000000000000005A +:10322000D90048000000000000000000C020040099 +:10323000000000000000000000A0000A00000000E4 +:103240000718F000C0304620000000000000000019 +:10325000D90048000000000000000000C020040069 +:10326000000000000000000000A0000A00000000B4 +:103270000818F3FCC03046200000000000000000E9 +:10328000D90048000000000000000000C020040039 +:10329000000000000000000000A0000A0000000084 +:1032A0000000003000200A2D000000000000000097 +:1032B000C0290C4000000000000000300020362330 +:1032C0000000000000000000C0200400000000001A +:1032D0000000000000A0000A0000000086000000BE +:1032E00000204411000000000000000000404801E0 +:1032F0000000000085000000C02044110000000014 +:103300000000000000404801000000000000217C97 +:10331000002044110000000000000000C020480010 +:103320000000000000000000C02048000000000075 +:1033300000000000C02048000000000081000000E4 +:10334000002044110000000000000001002048118E +:103350000000000000000000C02008000000000085 +:103360000000000017000000000000000004217FA2 +:10337000006044110000068A0000001F0021023096 +:10338000000000000000000014C000000000000069 +:103390000000000000404C02000004480000000053 +:1033A000C0200C000000000000000000C020100041 +:1033B0000000000000000000C02014000000000019 +:1033C00000000000C0201800000000000000000005 +:1033D000C0201C000000000000007F0000280A211F +:1033E0000000000000004500002F02220000000045 +:1033F000000000000CE00000000004560000000087 +:10340000C0202000000000000000000017000000A5 +:10341000000000000000001000280A230000000047 +:1034200000000010002F0222000000000000000039 +:103430000CE000000000045E810000000020441148 +:103440000000000000000001002048110000000002 +:1034500000040000006946240000068A0000000005 +:1034600000400000000004638100000000204411BF +:1034700000000000000000000020481100000000D3 +:103480000000216D00204411000000000000000039 +:103490000020480400000000000000000060480513 +:1034A0000000068F00000000002824F0000000004B +:1034B0000000000700280A230000000000000001AF +:1034C000002F022200000000000000000AE00000BF +:1034D0000000046A00000000002F00C90000000086 +:1034E0000000000004E00000000004830000000071 +:1034F000004000000000049000000002002F0222A3 +:1035000000000000000000000AE000000000046F5E +:1035100000000000002F00C90000000000000000B3 +:1035200002E00000000004830000000000400000F2 +:103530000000049000000003002F022200000000A1 +:10354000000000000AE00000000004740000000019 +:10355000002F00C900000000000000000CE0000087 +:103560000000048300000000004000000000049000 +:1035700000000004002F02220000000000000000F4 +:103580000AE000000000047900000000002F00C9DC +:1035900000000000000000000AE0000000000483BA +:1035A0000000000000400000000004900000000542 +:1035B000002F022200000000000000000AE00000CE +:1035C0000000047E00000000002F00C90000000081 +:1035D0000000000006E0000000000483000000007E +:1035E000004000000000049000000006002F0222AE +:1035F00000000000000000000AE00000000004835A +:1036000000000000002F00C90000000000000000C2 +:1036100008E00000000004830000000000400000FB +:103620000000049000007F0000280A210000000034 +:1036300000004500002F02220000000000000000F2 +:103640000AE00000000000000000000800210A233A +:10365000000000000000000014C000000000048D05 +:10366000000021690020441100000000000000005B +:10367000C02048000000000000000000C0204800FA +:103680000000000000000000C02048000000000012 +:10369000CAFEBABE00404811000000000000000051 +:1036A000C02044000000000000000000C020000016 +:1036B0000000000000000000C040480000000000C2 +:1036C00000007F0000280A210000000000004500E3 +:1036D000002F022200000000000000000AE00000AD +:1036E0000000049600000000C02000000000000060 +:1036F00000000000C02000000000000000000000EA +:10370000C0400000000000000000000000404C0825 +:103710000000045600000000C02008000000000067 +:103720000000001040210E200000000000000011E9 +:10373000402112200000000000000012402116204D +:10374000000000000000216900204411000000007A +:1037500000000000002048020000000000000000FF +:1037600000210225000000000000000014E000001D +:10377000000004A000040000C0494A20000004A189 +:10378000FFFBFFFFC0284A200000000000000000EF +:1037900000210223000000000000000014E00000EF +:1037A000000004AD00000000C02048000000000040 +:1037B00000000000C02048000000000000000000E1 +:1037C00000210224000000000000000014C00000DE +:1037D00000000000810000000020441100000000F3 +:1037E0000000000C00204811000000000000000054 +:1037F00000200010000000000000000014C00000C5 +:10380000000004A9A00000000020441100000000F6 +:10381000CAFEBABE0040481100000000810000004E +:1038200000204411000000000000000400204811A6 +:10383000000000000000216B002044110000000087 +:1038400000000000C02048100000000081000000BF +:103850000020441100000000000000050020481175 +:10386000000000000000216C002044110000000056 +:1038700000000000C0204810000000000000000010 +:10388000002F022400000000000000000CE00000F7 +:10389000000000000000000000400000000004A73D +:1038A00000000000C0210A2000000000000000000D +:1038B00014C00000000004C081000000002044117A +:1038C000000000000000000000204811000000007F +:1038D0000000216D002044110000000000000000E5 +:1038E000C02048000000000000000000C060480048 +:1038F0000000068F0000000000400000000004C42B +:1039000081000000002044110000000000000001C0 +:10391000002048110000000000040000C0294620DB +:103920000000000000000000C06000000000068AE7 +:103930000000000100210222000000000000000041 +:1039400014C00000000004CB0000216900204411D5 +:103950000000000000000000C0204800000000003F +:1039600000000000C020480000000000000000002F +:103970000020481000000000CAFEBABE00404811F6 +:103980000000000000000000C02044000000000013 +:1039900000000000C040481000000000810000004E +:1039A0000020441100000000000000010020481128 +:1039B00000000000000021F8002044110000000079 +:1039C0000000000E0020481100000000000421F952 +:1039D000006044110000068A00000000002102304F +:1039E000000000000000000014C00000000004CD32 +:1039F00000002180002044110000000000000000B1 +:103A0000C02048000000000000000000C0200000AE +:103A10000000000000000000C0204800000000007E +:103A200000000000C02000000000000000000000B6 +:103A3000C0404800000000000000000300333E2F9B +:103A40000000000000000001002102210000000031 +:103A50000000000014E00000000004FD0000002C45 +:103A600000200A2D000000000004000018E00C11E6 +:103A7000000004EC0000000100333E2F00000000B5 +:103A80000000216900204411000000000000000037 +:103A90000020480200000000000000000020480351 +:103AA000000000000000000800300A2200000000B2 +:103AB00000000000C02048000000000000000000DE +:103AC000C0204800000000000000216900204411CF +:103AD000000000000000000000204802000000007C +:103AE0000000000000204803000000000000000863 +:103AF00000300A220000000000000000C020480042 +:103B00000000000000000000D8C04800000004E0F1 +:103B100000002169002044110000000000000000A6 +:103B200000204802000000000000000000204803C0 +:103B3000000000000000000800300A220000000021 +:103B400000000000C020480000000000000000004D +:103B5000C0204800000000000000002D0020122DB1 +:103B6000000000000000000000290C83000000009D +:103B70000000216900204411000000000000000046 +:103B80000020480200000000000000000020480360 +:103B9000000000000000000800300A2200000000C1 +:103BA00000000000C02048000000000000000000ED +:103BB000C020480000000000000000110021022485 +:103BC000000000000000000014C000000000000021 +:103BD0000000000000400000000004A70000002CCE +:103BE000C0203620000000000000002DC04036201C +:103BF000000000000000000F002102210000000072 +:103C00000000000014C000000000050200000000D9 +:103C1000006000000000000B00000000D900000060 +:103C20000000000000000000C0400400000000018F +:103C3000B50000000020441100000000000020003A +:103C40000020481100000000B600000000204411D0 +:103C5000000000000000A00000204811000000004B +:103C6000B700000000204411000000000000C00068 +:103C70000020481100000000B8000000002044119E +:103C8000000000000000F8E00020481100000000E3 +:103C9000B900000000204411000000000000F8807E +:103CA0000020481100000000BA000000002044116C +:103CB000000000000000E0000020481100000000AB +:103CC000BB00000000204411000000000000F000D4 +:103CD0000020481100000000BC000000002044113A +:103CE000000000000000F3FC00204811000000006C +:103CF00081000000002044110000000000000002CC +:103D00000020481100000000000000FF00280E30D5 +:103D10000000000000000000002F0223000000004F +:103D2000000000000CC000000000051600000000AC +:103D3000C0200800000000000000000014C00000C7 +:103D40000000052B0000000000200C110000000006 +:103D50000000001C00203623000000000000002BA3 +:103D60000020362300000000000000290020362338 +:103D700000000000000000280020362300000000A2 +:103D8000000000170020362300000000000000257E +:103D9000002036230000000000000026002036230B +:103DA0000000000000000015002036230000000085 +:103DB000000000160020362300000000FFFFE00096 +:103DC00000200C110000000000000021002036231C +:103DD0000000000000000022002036230000000048 +:103DE00000001FFF00200C11000000000000002355 +:103DF00000203623000000000000002400203623AD +:103E000000000000F1FFFFFF00283A2E0000000034 +:103E10000000001AC0220E20000000000000000078 +:103E20000029386E000000008100000000204411CD +:103E30000000000000000006002048110000000003 +:103E40000000002A4020362000000000870000000B +:103E5000002044110000000000000000C0204800C5 +:103E6000000000000000A1F4002044110000000048 +:103E700000000000002048100000000000000000CA +:103E800000200C110000000000000030002036234C +:103E9000000000009D000000002044110000000010 +:103EA0000000001F40214A20000000009600000092 +:103EB000002044110000000000000000C020480065 +:103EC0000000000000000000C0200C000000000006 +:103ED00000000000C0201000000000000000001FD3 +:103EE00000211624000000000000000014C00000A3 +:103EF000000000000000001D00203623000000002C +:103F00000000000300281E2300000000000000083D +:103F10000022222300000000FFFFF00000282228DA +:103F20000000000000000000002920E80000000060 +:103F30000000001F002036280000000000000018CC +:103F400000211E2300000000000000200020362772 +:103F50000000000000000002002216240000000003 +:103F600000000000003014A8000000000000001E47 +:103F700000203625000000000000000300211A2464 +:103F8000000000001000000000281A2600000000B9 +:103F9000EFFFFFFF00283A2E0000000000000000A5 +:103FA000004938CE000006780000000140280A20B1 +:103FB000000000000000000640280E200000000065 +:103FC00000000300C02812200000000000000008CC +:103FD000002112240000000000000000C020162074 +:103FE0000000000000000000C0201A2000000000B7 +:103FF000000000000021022200000000000000007C +:1040000014C000000000056381000000002044117E +:104010000000000000000001002048110000000026 +:104020000000225800300A240000000000040000B4 +:10403000006946220000068A000021690020441120 +:104040000000000000000000002048050000000003 +:104050000002000000294A260000000000000000C5 +:104060000020481000000000CAFEBABE002048111F +:104070000000000000000002002F022300000000EA +:10408000000000000CC000000000056B00000000F4 +:10409000C0201C100000000000000000C040000014 +:1040A0000000057900000002002F0223000000003C +:1040B000000000000CC000000000056B8100000043 +:1040C0000020441100000000000000010020481101 +:1040D000000000000000225800300A240000000008 +:1040E00000040000006946220000068A000000006B +:1040F000C0201C100000000000000000C0400000B4 +:104100000000057900000000002F022300000000DD +:10411000000000000CC000000000056F000000005F +:10412000C0201C000000000000000000C040000093 +:104130000000057900000004002F022300000000A9 +:10414000000000000CC000000000057781000000A6 +:104150000020441100000000000000000020481171 +:10416000000000000000216D00204411000000004C +:1041700000000000C0204800000000000000000017 +:10418000C06048000000068F0000000000401C10C6 +:104190000000057900000000C020000000000000C1 +:1041A00000000000C040000000000000000000000F +:1041B0000EE000000000057B000000000060000031 +:1041C000000005C600000000002F022400000000CF +:1041D000000000000CC000000000058C0000A2B729 +:1041E00000204411000000000000000000204807EB +:1041F00000000000810000000020441100000000C9 +:104200000000000100204811000000000004A2B6D8 +:10421000006044110000068A0000001A00212230CC +:104220000000000000000006002226300000000010 +:1042300000042004006044110000068A0000A2C4AB +:10424000002044110000000000000000003048E998 +:10425000000000000000000000E000000000058AEF +:104260000000A2D100204411000000000000000066 +:1042700000404808000000000000A2D100204411C6 +:10428000000000000000000100504A28000000006B +:1042900000000001002F02240000000000000000C8 +:1042A0000CC000000000059D0000A2BB00204411CE +:1042B000000000000000000000204807000000008F +:1042C00081000000002044110000000000000001F7 +:1042D00000204811000000000004A2BA0060441150 +:1042E0000000068A0000001A0021223000000000B1 +:1042F0000000000600222630000000000004200418 +:10430000006044110000068A0000A2C5002044118C +:104310000000000000000000003048E9000000003C +:104320000000000000E000000000059B0000A2D299 +:104330000020441100000000000000000040480878 +:10434000000000000000A2D2002044110000000084 +:104350000000000100504A28000000000000000298 +:10436000002F022400000000000000000CC000002C +:10437000000005AE0000A2BF0020441100000000B4 +:10438000000000000020480700000000810000003D +:10439000002044110000000000000001002048112E +:1043A000000000000004A2BE006044110000068A64 +:1043B0000000001A0021223000000000000000066A +:1043C0000022263000000000000420040060441198 +:1043D0000000068A0000A2C6002044110000000070 +:1043E00000000000003048E900000000000000006C +:1043F00000E00000000005AC0000A2D30020441142 +:10440000000000000000000000404808000000001C +:104410000000A2D3002044110000000000000001B1 +:1044200000504A28000000000000A2C300204411F0 +:10443000000000000000000000204807000000000D +:104440008100000000204411000000000000000175 +:1044500000204811000000000004A2C200604411C6 +:104460000000068A0000001A00212230000000002F +:104470000000000600222630000000000004200496 +:10448000006044110000068A0000A2C70020441109 +:104490000000000000000000003048E900000000BB +:1044A0000000000000E00000000005BB0000A2D4F6 +:1044B00000204411000000000000000000404808F7 +:1044C000000000000000A2D4002044110000000001 +:1044D0000000000100504A28000000008500000094 +:1044E00000204411000000000000000000204801EE +:1044F000000000000000304A0020441100000000CD +:104500000100000000204811000000000000000031 +:1045100000400000000005C1A4000000C0204411BC +:104520000000000000000000C04048000000000043 +:1045300000000000C0600000000005C60000000090 +:10454000C0400400000000010000002C00203621C3 +:104550000000000081000000002044110000000065 +:1045600000000006002048110000000000000000CC +:10457000002F023000000000000000000CC000000E +:10458000000005CD00000000002004110000000024 +:104590000000003000403621000005E0000000303F +:1045A0000020062D0000000000007E0000280621EB +:1045B0000000000000000000002F022100000000A9 +:1045C000000000000CE00000000005E08100000099 +:1045D00000204411000000000000000100204811EC +:1045E000000000000004A092006044110000068A50 +:1045F0000000003100203630000000000004A093CD +:10460000006044110000068A0000003200203630AD +:10461000000000000004A2B6006044110000068AF9 +:104620000000003300203630000000000004A2BA71 +:10463000006044110000068A00000034002036307B +:10464000000000000004A2BE006044110000068AC1 +:104650000000003500203630000000000004A2C237 +:10466000006044110000068A000000360020363049 +:104670000000000000042004006044110000068ACD +:104680000001A2A400204411000000000000003F2F +:1046900000204811000000000000003F00204811E9 +:1046A000000000000000003F002048110000000052 +:1046B0000000003F0020481100000000000000053D +:1046C00000204811000000000000A1F40020441167 +:1046D0000000000000000000002048110000000061 +:1046E00088000000002044110000000000000001CC +:1046F000002048110000000081000000002044114B +:10470000000000000000000600204811000000002A +:1047100000000001002F0230000000000000000037 +:104720000CE0000000000629000000300020062DEB +:104730000000000000000000002F02210000000027 +:10474000000000000CE000000000062981000000CD +:10475000002044110000000000000001002048116A +:104760000000000000007E0000280621000000007C +:1047700000000000002F02210000000000000000E7 +:104780000CE00000000006020000A092002044118E +:10479000000000000000003100204A2D0000000051 +:1047A0000000A0930020441100000000000000322F +:1047B00000204A2D000000000000A2B60020441195 +:1047C000000000000000003300204A2D000000001F +:1047D0000000A2BA002044110000000000000034D4 +:1047E00000204A2D000000000000A2BE002044115D +:1047F000000000000000003500204A2D00000000ED +:104800000000A2C200204411000000000000003699 +:1048100000204A2D00000000000000300020062D7E +:1048200000000000000001FF002806210000000039 +:1048300000000000002F0221000000000000000026 +:104840000CE000000000062800000000002102210A +:10485000000000000000000014C000000000060B73 +:104860000004A003006044110000068A0000A003B9 +:10487000002044110000000000000000002048104B +:1048800000000000000000010021062100000000DF +:104890000000000014C00000000006100004A0107A +:1048A000006044110000068A0000A010002044119E +:1048B0000000000000000000002048100000000080 +:1048C000000000010021062100000000000000009F +:1048D000002F022100000000000000000CE000009A +:1048E000000006280004A011006044110000068AA0 +:1048F0000000A01100204411000000000000000092 +:1049000000204810000000000004A01200604411C4 +:104910000000068A0000A0120020441100000000E0 +:104920000000000000204810000000000004A01358 +:10493000006044110000068A0000A013002044110A +:1049400000000000000000000020481000000000EF +:104950000004A014006044110000068A0000A014A6 +:10496000002044110000000000000000002048105A +:10497000000000000004A015006044110000068A39 +:104980000000A015002044110000000000000000FD +:1049900000204810000000000004A0160060441130 +:1049A0000000068A0000A01600204411000000004C +:1049B0000000000000204810000000000004A017C4 +:1049C000006044110000068A0000A0170020441176 +:1049D000000000000000000000204810000000005F +:1049E00000042004006044110000068A0000002C2E +:1049F0000080062D00000000FF0000000020441190 +:104A0000000000000000000000204811000000002D +:104A1000000000010020481100000000000000021A +:104A20000080481100000000000000000EE00000BF +:104A30000000063A000000300020062D00000000B3 +:104A40000000000200280621000000000000000015 +:104A5000002F022100000000000000000CE0000018 +:104A60000000063881000000002044110000000012 +:104A70000000000100204811000000000004200494 +:104A8000006044110000068A000010000020081198 +:104A9000000000000000002B002036220000000073 +:104AA00000000000006000000000063E0000000062 +:104AB00000600000000005C69800000000204411BE +:104AC000000000000000000000804811000000000D +:104AD00000000000C06000000000063E0000000072 +:104AE000C0400400000000010000A2A40020441106 +:104AF000000000000000002200204811000000001B +:104B000089000000002044110000000000000001A6 +:104B1000004048110000062A9700000000204411C0 +:104B2000000000000000000000204811000000000C +:104B30008A00000000204411000000000000000076 +:104B4000004048110000062A00000000006000003C +:104B50000000065900002010002044110000000051 +:104B60000000800000204811000000000001A2A405 +:104B7000C020441100000000000000160060481131 +:104B80000000036E0000201000204411000000000F +:104B9000000100000020481100000000810000001A +:104BA0000020441100000000000000010020481116 +:104BB000000000000000217C0020441100000000E3 +:104BC000098000000020481100000000FFFFFFFFE7 +:104BD00000204811000000000000000000204811E3 +:104BE00000000000000000001700000000000000AE +:104BF0000004217F006044110000068A0000001FAD +:104C000000210230000000000000000014C000007D +:104C1000000000000000000400404C11000006539A +:104C2000000000000040000000000000000000172D +:104C300000201E2D000000000000000400291E2797 +:104C40000000000000000017008036270000000070 +:104C50000000001700201E2D00000000FFFFFFFBDA +:104C600000281E27000000000000001700803627E3 +:104C7000000000000000001700201E2D00000000B2 +:104C80000000000800291E27000000000000001797 +:104C900000803627000000000000001700201E2DB5 +:104CA00000000000FFFFFFF700281E2700000000A3 +:104CB00000000017008036270000000000002010D0 +:104CC0000020441100000000000080000020481176 +:104CD000000000000001A2A4002044110000000018 +:104CE00000000016006048110000036E0000201054 +:104CF00000204411000000000001000000204811C5 +:104D0000000000000000217C002044110000000091 +:104D1000018000000020481100000000FFFFFFFF9D +:104D20000020481100000000000000000020481191 +:104D3000000000000000000017000000000000005C +:104D4000810000000020441100000000000000016C +:104D500000204811000000000004217F0060441181 +:104D60000000068A0000001F002102300000000041 +:104D70000000000014C000000000068900000010C0 +:104D800000404C110000066F00000000C02004002D +:104D9000000000000000000038C00000000000001B +:104DA0000000001D00200A2D000000000000001E71 +:104DB00000200E2D000000000000001F0020122D1A +:104DC00000000000000000200020162D0000000060 +:104DD00000002169002044110000000000000000D4 +:104DE00000204804000000000000000000204805EA +:104DF000000000000000000000204801000000004A +:104E0000CAFEBABE002048110000000000000004E5 +:104E1000003012240000000000000000002F006499 +:104E200000000000000000000CC000000000068828 +:104E30000000000300281A22000000000000000803 +:104E40000022122200000000FFFFF00000281224C0 +:104E50000000000000000000002910C40000000055 +:104E60000000001F00403624000000000000000089 +:104E70000080000000000000000000001AC00000D8 +:104E80000000068A9F00000000204411000000007E +:104E9000CAFEBABE00204811000000000000000059 +:104EA0001AE000000000068D0000000000800000F5 +:104EB00000000000000000001AC000000000068F83 +:104EC0009E0000000020441100000000CAFEBABE8F +:104ED0000020481100000000000000001AE000005F +:104EE00000000692000000000080000000000000AA +:104EF00000000000006000000000000B0000100037 +:104F000000600411000003150000000000200411DF +:104F1000000000000000000000600811000001B265 +:104F20000000225C0020441100000000000000038B +:104F3000002048110000000000002256002044110B +:104F4000000000000000001B0020481100000000CD +:104F50000000A1FC0020441100000000000000013E +:104F600000204811000000000001A1FDC0204411F4 +:104F7000000000000000002100201E2D00000000A5 +:104F80000000001000221E27000000000000002486 +:104F90000020222D000000000000FFFF0028222832 +:104FA0000000000000000000002949070000000088 +:104FB0000000000000204811000000000000002256 +:104FC0000020222D000000000000FFFF0028222802 +:104FD0000000000000000000002949070000000058 +:104FE0000000000000204811000000000000002325 +:104FF00000201E2D000000000000001000221E27CF +:105000000000000000000000002949070000000027 +:1050100000000000004048110000000000000000F7 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B000014204FF05BD02500000000001C3016867 +:1052C000043F05BD00000000022502090250015103 +:1052D000000000000223024502A00241000000007D +:1052E00003D705BD05BD05BD000000000646064705 +:1052F000031F05BD0000000005BD05C203200340DB +:1053000000000000032A0282034203340000000070 +:1053100005BD05BD05BD05BD0000000005BD054E70 +:1053200005BD05BD0000000003BA05BD04B8034477 +:10533000000000000497044D043D05BD000000007E +:1053400004CD05BD044104DA00000000044D05044D +:10535000035103750000000005BD05BD05BD05BD79 +:105360000000000005BD05BD05BD05BD0000000035 +:1053700005BD05BD063C05C40000000005BD05BD1A +:10538000000705BD0000000005BD05BD05BD05BD4C +:105390000000000005BD05BD05BD05BD0000000005 +:1053A00003F803ED0408040600000000040E040ADC +:1053B000040C041000000000041C04180424042041 +:1053C00000000000042C0428043404300000000015 +:1053D00005BD05BD043805BD0000000005BD05BDC7 +:1053E00005BD05BD0000000005BD05BD05BD05BD31 +:1053F000000000000002067606940006000000008F +:00000001FF diff --git a/firmware/radeon/RV635_pfp.bin.ihex b/firmware/radeon/RV635_pfp.bin.ihex new file mode 100644 index 0000000..f55292c --- /dev/null +++ b/firmware/radeon/RV635_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000CA040000A00000007E828B007C038BED +:10001000008001B8007C038B00D4401E00EE001E5F +:1000200000CA040000A00000007E828B00C41838C3 +:1000300000CA240000CA2800009581A800C41C3A08 +:1000400000C3C00000CA080000CA0C00007C744B4A +:1000500000C200050099C00000C41C3A007C744C2A +:1000600000C0FFF000042C0400309002007D250049 +:1000700000351402007D350B00255403007CD5802B +:1000800000259C030095C00400D5001B007EDDC147 +:10009000007D9D8000D6801B00D5801B00D4401EB3 +:1000A00000D5401E00D6401E00D6801E00D4801E03 +:1000B00000D4C01E009783D300D5C01E00CA08001C +:1000C0000080001A00CA0C0000E4011E00D4001ECB +:1000D0000080000C00C4183800E4013E00D4001E6B +:1000E0000080000C00C4183800D4401E00EE001E32 +:1000F00000CA040000A00000007E828B00E4011E04 +:1001000000D4001E00D4401E00EE001E00CA0400F1 +:1001100000A00000007E828B00E4013E00D4001E9F +:1001200000D4401E00EE001E00CA040000A0000023 +:10013000007E828B00CA180000D4401E00D5801EAD +:100140000080005300D4007500D4401E00CA08008F +:1001500000CA0C0000CA100000D4801900D4C018D6 +:1001600000D5001700D4801E00D4C01E00D5001E8C +:1001700000E2001E00CA040000A00000007E828B86 +:1001800000CA080000D4806000D4401E0080000037 +:1001900000D4801E00CA080000D4806100D4401E34 +:1001A0000080000000D4801E00CA080000CA0C00B5 +:1001B00000D4401E00D4801600D4C01600D4801E87 +:1001C000008001B800D4C01E00C6084300CA0C005D +:1001D00000CA10000094800400CA140000E420F358 +:1001E00000D4201300D5606500D4E01C00D5201C8D +:1001F00000D5601C008000000006200100C60843F6 +:1002000000CA0C0000CA1000009483F700CA140052 +:1002100000E420F30080007900D4201300C60843D6 +:1002200000CA0C0000CA1000009883EF00CA140036 +:1002300000D400640080008D0000000000C414326F +:1002400000C6184300C4082F0095400500C40C30B8 +:1002500000D4401E0080000000EE001E009583F5D3 +:1002600000C4103100D4403300D5206500D4A01C58 +:1002700000D4E01C00D5201C00E4015E00D4001E68 +:10028000008000000006200100CA1800000A2001BA +:1002900000D6007600C408360098800700C61045D6 +:1002A0000095011000D4001F00D46062008000009F +:1002B00000D4206200CC383500CC1433008401BB5C +:1002C00000D4007200D5401E0080000000EE001E29 +:1002D00000E2001A008401BB00E2001A00CC104BBF +:1002E00000CC0447002C9401007D098B0098400548 +:1002F000007D15CB00D4001A008001B800D4006D39 +:100300000034440100CC0C480098403A00CC2C4A00 +:100310000095800400CC0449008001B800D4001A84 +:1003200000D4C01A00282801008400F000CC10037B +:100330000098801B0004380C008400F000CC1003EF +:100340000098801700043808008400F000CC1003E7 +:100350000098801300043804008400F000CC1003DF +:100360000098801400CC104C009A800900CC144DE9 +:10037000009840DC00D4006D00CC184800D5001A6D +:1003800000D5401A008000C900D5801A0096C0D55B +:1003900000D4006D008001B800D4006E009AC00344 +:1003A00000D4006D00D4006E0080000000EC007FDF +:1003B000009AC0CC00D4006D008001B800D4006E5B +:1003C00000CC140300CC180300CC1C03007D910367 +:1003D000007DD583007D190C0035CC1F0035701FC2 +:1003E000007CF0CB007CD08B00880000007E8E8BE0 +:1003F0000095C00400D4006E008001B800D4001A3B +:1004000000D4C01A00CC080300CC0C0300CC1003AD +:1004100000CC140300CC180300CC1C0300CC240334 +:1004200000CC28030035C41F0036B01F007C704B81 +:100430000034F01F007C704B0035701F007C704B47 +:10044000007D8881007DCCC1007E5101007E9541F8 +:10045000007C9082007CD4C2007C848B009AC00314 +:10046000007C8C8B002C88010098809E00D4006D4D +:100470000098409C00D4006E00CC084C00CC0C4D81 +:1004800000CC104800D4801A00D4C01A00800101AA +:1004900000D5001A00CC083200D40032009482D972 +:1004A00000CA0C0000D4401E0080000000D4001ED2 +:1004B00000E4011E00D4001E00CA080000CA0C009F +:1004C00000CA100000D4401E00CA140000D4801ED0 +:1004D00000D4C01E00D5001E00D5401E00D54034FB +:1004E0000080000000EE001E0028040400E2001A54 +:1004F00000E2001A00D4401A00CA380000CC0803F9 +:1005000000CC0C0300CC0C0300CC0C03009882BD83 +:1005100000000000008401BB00D7A06F0080000035 +:1005200000EE001F00CA040000C2FF0000CC083427 +:1005300000C13FFF007C74CB007CC90B007D010F24 +:10054000009902B0007C738B008401BB00D7A06FC0 +:100550000080000000EE001F00CA080000281900FB +:10056000007D898B009580140028140400CA0C00BB +:1005700000CA100000CA1C0000CA240000E2001FCC +:1005800000D4C01A00D5001A00D5401A00CC1803B8 +:1005900000CC2C0300CC2C0300CC2C03007DA58BBD +:1005A000007D9C4700984297000000000080016198 +:1005B00000D4C01A00D4401E00D4801E0080000069 +:1005C00000EE001E00E4011E00D4001E00D4401EF8 +:1005D00000EE001E00CA040000A00000007E828B16 +:1005E00000E4013E00D4001E00D4401E00EE001EB8 +:1005F00000CA040000A00000007E828B00CA080030 +:1006000000248C06000CCC060098C00600CC104ECE +:100610000099000400D4007300E4011E00D4001E01 +:1006200000D4401E00D4801E0080000000EE001E9A +:1006300000CA080000CA0C000034D01800251001C0 +:100640000095002100C17FFF00CA100000CA1400FD +:1006500000CA180000D4801D00D4C01D007DB18BDD +:1006600000C1420200C2C00100D5801D0034DC0E72 +:10067000007D5D4C007F734C00D7401E00D5001EEE +:1006800000D5401E00C1420000C2C00000099C010C +:100690000031DC10007F5F4C007F734C00042802A7 +:1006A000007D838000D5A86F00D5806600D7401EEE +:1006B00000EC005E00C8240200C82402008001B8DB +:1006C00000D6007600D4401E00D4801E00D4C01E88 +:1006D0000080000000EE001E0080000000EE001F01 +:1006E00000D4001F0080000000D4001F00D4001FB1 +:1006F0000088000000D4001F00000000000000007F +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000010171000201780003008F0004007FE5 +:10081000000500030006003F000700320008012C1D +:1008200000090046000A0036001001B6001700A2B9 +:100830000022013A00230149002000B400240125D0 +:100840000027004D0028006A002A0060002B00529B +:10085000002F0065003200870034017F003C015604 +:10086000003F00720041018C0044012E00550173CD +:100870000056017A0060000B00610034006200380D +:1008800000630038006400380065003800660038F6 +:10089000006700380068003A00690041006A0048BB +:1008A000006B0048006C0048006D0048006E004876 +:1008B000006F00480000000600000006000000066F +:1008C0000000000600000006000000060000000610 +:1008D0000000000600000006000000060000000600 +:1008E00000000006000000060000000600000006F0 +:1008F00000000006000000060000000600000006E0 +:00000001FF diff --git a/firmware/radeon/RV670_me.bin.ihex b/firmware/radeon/RV670_me.bin.ihex new file mode 100644 index 0000000..9fbfc0e --- /dev/null +++ b/firmware/radeon/RV670_me.bin.ihex @@ -0,0 +1,1345 @@ +:1000000000000000C020040000000000000000000C +:1000100000A0000A000000000000FFFF00284621A9 +:100020000000000000000000D900480000000000AF +:1000300000000000C02004000000000000000000DC +:1000400000A0000A000000000000000000E0000026 +:100050000000000000010000C02946200000000050 +:1000600000000000D900480000000000000000006F +:10007000C0200400000000000000000000A0000AF2 +:10008000000000008100000000204411000000007A +:1000900000000001002048110000000000042004BE +:1000A000006044110000067C0000000000600000B9 +:1000B0000000062400000000006000000000063878 +:1000C00000000000C02008000000000000000F0039 +:1000D000002816220000000000000008002116255C +:1000E000000000000000001800203625000000007D +:1000F0008D000000002044110000000000000004FA +:10010000002F022500000000000000000CE00000AD +:1001100000000018004120000040481100000019B4 +:100120000042200000204811000000008E00000066 +:1001300000204411000000000000002800204A2D8B +:1001400000000000900000000020441100000000AA +:100150000000000000204805000000000000000C26 +:1001600000211622000000000000000300281625D0 +:10017000000000000000001900211A220000000009 +:100180000000000400281A26000000000000000003 +:10019000002914C5000000000000001900203625C9 +:1001A0000000000000000000003A140200000000FF +:1001B00000000016002116250000000000000003CA +:1001C00000281625000000000000001700200E2D5A +:1001D00000000000FFFFFFFC00280E2300000000CD +:1001E00000000000002914A3000000000000001718 +:1001F00000203625000000000000800000280E22AC +:10020000000000000000000700220E230000000094 +:10021000000000000029386E0000000020000000EF +:1002200000280E22000000000000000600210E231E +:1002300000000000000000000029386E00000000EF +:100240000000000000220222000000000000000068 +:1002500014E0000000000038000000002EE0000064 +:1002600000000035000000002CE000000000003716 +:100270000000000000400E2D0000003900000008C2 +:1002800000200E2D00000000000000090040122D8B +:10029000000000460000000100400E2D0000003963 +:1002A00000000000C0200C0000000000003FFFFC28 +:1002B0000028122300000000000000020022122487 +:1002C000000000000000001F00211E2300000000AD +:1002D0000000000014E000000000003E00000008E4 +:1002E00000401C11000000410000000D00201E2DE8 +:1002F000000000000000000F00281E270000000082 +:100300000000000300221E27000000007FC0000044 +:1003100000281A23000000000000001400211A2603 +:10032000000000000000000100331A260000000059 +:100330000000000800221A26000000000000000053 +:1003400000290CC700000000000000270020362410 +:100350000000000000007F000028122100000000C3 +:1003600000001400002F0224000000000000000024 +:100370000CE000000000004B0000000100290E23EB +:10038000000000000000000E0020362300000000E6 +:100390000000E0000020441100000000FFF8000011 +:1003A00000294A230000000000000000003A2C024F +:1003B000000000000000000200220E2B00000000E0 +:1003C000FC00000000280E23000000000000000FC9 +:1003D000002036230000000000001FFF00294A23F0 +:1003E000000000000000002700204A2D000000004F +:1003F000000000000020481100000000000000295B +:1004000000200E2D00000000060A020000294A23E9 +:100410000000000000000000002048110000000063 +:100420000000000000204811000000000000000152 +:1004300000210222000000000000000014E0000083 +:1004400000000061000000002EE000000000005FDE +:10045000000000002CE000000000005E0000000032 +:1004600000400E2D000000620000000100400E2D33 +:10047000000000620000000A00200E2D00000000B5 +:100480000000000B0040122D0000006A0000000078 +:10049000C0200C0000000000003FFFFC00281223D9 +:1004A00000000000000000020022122400000000F2 +:1004B0007FC0000000281623000000000000001488 +:1004C0000021162500000000000000010033162561 +:1004D000000000008000000000280E230000000043 +:1004E0000000000000290CA3000000003FFFFC00FA +:1004F00000290E23000000000000001F00211E2321 +:10050000000000000000000014E000000000006D8A +:100510000000010000401C11000000700000000DF0 +:1005200000201E2D00000000000000F000281E2703 +:10053000000000000000000400221E270000000050 +:100540008100000000204411000000000000000DA8 +:100550000020481100000000FFFFF0FF00281A30C3 +:10056000000000000000A02800204411000000004E +:1005700000000000002948E6000000000000A0186C +:1005800000204411000000003FFFFFFF00284A2325 +:10059000000000000000A010002044110000000036 +:1005A00000000000002048040000000000000030AF +:1005B0000020162D00000000000000020029162572 +:1005C0000000000000000030002036250000000080 +:1005D000000000250020162D000000000000000093 +:1005E000002F00A300000000000000000CC000006D +:1005F00000000083000000260020162D00000000EF +:1006000000000000002F00A4000000000000000017 +:100610000CC000000000008400000000004000004A +:100620000000008A000000250020362300000000A2 +:100630000000002600203624000000000000001703 +:1006400000201E2D000000000000000200210227F3 +:10065000000000000000000014E000000000008A1C +:1006600000000000006000000000065900000000CB +:10067000006000000000064D0000000200210E2274 +:10068000000000000000000014C000000000008D09 +:1006900000000012C040362000000093000000005F +:1006A0002EE0000000000091000000002CE000009F +:1006B000000000900000000200400E2D000000929B +:1006C0000000000300400E2D000000920000000C0E +:1006D00000200E2D00000000000000120020362334 +:1006E000000000000000000300210E2200000000B6 +:1006F0000000000014C00000000000980000A00CE2 +:10070000002044110000000000000000C02048004C +:100710000000000000000000C0404800000000A0F1 +:100720000000A00C002044110000000000000000A8 +:100730000020481100000000000000002EE0000032 +:100740000000009E000000002CE000000000009D62 +:100750000000000200400E2D0000009F000000037A +:1007600000400E2D0000009F0000000C00200E2D08 +:10077000000000000000000000204803000000000E +:1007800000000000003A0C0200000000003F0000E2 +:1007900000280E23000000000000001000210E239E +:1007A00000000000000000110020362300000000BF +:1007B0000000001E0021022B0000000000000000CD +:1007C00014C00000000000A700000016C020362062 +:1007D000000000000000001F0021022B00000000AC +:1007E0000000000014C00000000000AA0000001576 +:1007F000C0203620000000000000000800210E2B61 +:10080000000000000000007F00280E230000000010 +:1008100000000000002F0223000000000000000084 +:100820000CE00000000000E10000000027000000D4 +:10083000000000000000000000600000000002A3B3 +:1008400000000001002F0223000000000000000053 +:100850000AE00000000000B300000000006000009B +:100860000000013A81000000002044110000000057 +:100870000000000600204811000000000000000CED +:1008800000221E300000000099800000002044116A +:1008900000000000000000040020122D00000000F5 +:1008A00000000008002212240000000000000010D8 +:1008B00000201811000000000000000000291CE4C6 +:1008C0000000000000000000006048070000012F49 +:1008D0009B00000000204411000000000000000008 +:1008E00000204802000000009C000000002044118D +:1008F00000000000000000000033146F0000000042 +:100900000000000100333E23000000000000000052 +:10091000D9004800000000000000000000203C0555 +:1009200000000000810000000020441100000000D1 +:100930000000000E00204811000000000000000030 +:1009400000201010000000000000E007002044110B +:10095000000000000000000F0021022B000000003A +:100960000000000014C00000000000CB00F8FF08E9 +:1009700000204811000000009800000000404811CD +:10098000000000DC000000F000280E220000000043 +:10099000000000A0002F0223000000000000000063 +:1009A0000CC00000000000DA0000001100200E2D35 +:1009B0000000000000000001002F022300000000E2 +:1009C000000000000CE00000000000D50000000264 +:1009D000002F022300000000000000000CE00000D7 +:1009E000000000D400003F0000400C11000000D6C1 +:1009F00000001F0000400C11000000D600000F0096 +:100A000000200C11000000000038000900294A23D2 +:100A1000000000003F00000000280E2B0000000036 +:100A20000000000200220E2300000000000000076A +:100A300000494A23000000DC00380F09002048115B +:100A400000000000680000070020481100000000BE +:100A50000000000800214A270000000000000000FC +:100A60000020481100000000060A020000294A2464 +:100A700000000000000000000020481100000000FD +:100A80000000000000204811000000000000A20249 +:100A9000002044110000000000FF000000280E228A +:100AA000000000000000008000294A230000000030 +:100AB0000000002700200E2D00000000000000268E +:100AC0000020122D0000000000000000002F008315 +:100AD00000000000000000000CE00000000000EA40 +:100AE000000000000060000000000653000000004D +:100AF00000400000000000EB00000000006000006B +:100B000000000656000000070020222D0000000013 +:100B10000000000500220E2200000000001000006E +:100B200000280E23000000000000000000292068BB +:100B30000000000000000000003A0C02000000006D +:100B4000000000EF00280E2300000000000000005D +:100B500000292068000000000000001700200E2D72 +:100B6000000000000000000300210223000000003C +:100B70000000000014E00000000000F80000000B7E +:100B800000210228000000000000000014C0000046 +:100B9000000000F8000004000029222800000000E6 +:100BA0000000001400203628000000000000001C97 +:100BB00000210E22000000000000000014C0000010 +:100BC000000000FD0000A30C002044110000000004 +:100BD0000000000000204811000000000000001E7E +:100BE00000210E22000000000000000014C00000E0 +:100BF0000000010B0000A30F0020441100000000C2 +:100C00000000001100200E2D000000000000000177 +:100C1000002F022300000000000000000CC00000B4 +:100C200000000104FFFFFFFF004048110000010B1E +:100C300000000002002F022300000000000000005E +:100C40000CC00000000001070000FFFF0040481139 +:100C50000000010B00000004002F02230000000030 +:100C6000000000000CC000000000010A000000FFAE +:100C7000004048110000010B000000010020481155 +:100C8000000000000002C400002044110000000029 +:100C90000000001F00210E220000000000000000E4 +:100CA00014C00000000001120000001040210E20BE +:100CB00000000000000000130020362300000000A8 +:100CC0000000001840224A20000000000000001030 +:100CD000C0424A20000001140000000000200C1156 +:100CE0000000000000000013002036230000000078 +:100CF000000000000020481100000000000000007B +:100D000000204811000000000000000A002010111F +:100D10000000000000000000002F0224000000007E +:100D2000000000000CE000000000011B00000000BB +:100D300000204811000000000000000100531224B0 +:100D400000000117FFBFFFFF00283A2E000000003F +:100D50000000001B00210222000000000000000033 +:100D600014C000000000012E81000000002044118A +:100D7000000000000000000D0020481100000000ED +:100D80000000001800220E3000000000FC000000EF +:100D900000280E2300000000810000000020441104 +:100DA000000000000000000E0020481100000000BC +:100DB0000000000000201010000000000000E00E05 +:100DC000002044110000000007F8FF08002048112F +:100DD000000000000000000000294A23000000007D +:100DE0000000001C00201E2D000000000000000874 +:100DF00000214A27000000000000000000204811E8 +:100E000000000000060A020000294A240000000039 +:100E10000000000000204811000000000000000059 +:100E200000204811000000000000000000800000C9 +:100E300000000000810000000020441100000000BC +:100E40000000000100204811000000000000217C8B +:100E50000020441100000000008000000020481124 +:100E60000000000000000000002048060000000014 +:100E70000000000800214A270000000000000000D8 +:100E800017000000000000000004217F00604411F2 +:100E90000000067C0000001F00210230000000005E +:100EA0000000000014C000000000067B00000004E9 +:100EB00000404C1100000135810000000020441169 +:100EC00000000000000000010020481100000000A8 +:100ED000000021F800204411000000000000001C68 +:100EE0000020481100000000000421F900604411B6 +:100EF0000000067C0000001100210230000000000C +:100F00000000000014E000000000013C00000000B0 +:100F100000800000000000000000000000600000F1 +:100F20000000000B00000000006004110000031529 +:100F3000000000000020041100000000000000007C +:100F400000600811000001B2000000000060000015 +:100F5000000001600000FFFF40280E20000000009C +:100F600000000010C0211220000000000000FFFF60 +:100F7000402806200000000000000010C0210A20C8 +:100F800000000000000000000034146100000000B8 +:100F90000000000000741882000002BB0001A1FDE7 +:100FA00000604411000002E000003FFF002F022F0C +:100FB00000000000000000000CC00000000001471D +:100FC00000000000C040040000000001000000001C +:100FD000006000000000000B000000000060041131 +:100FE00000000315000000000020041100000000B4 +:100FF0000000000000600811000001B200003FFF87 +:10100000002F022F00000000000000000CE0000094 +:10101000000000000000000000600000000001600F +:101020000000001040210E20000000000000FFFF23 +:10103000C0281220000000000000001040211620EF +:10104000000000000000FFFFC0681A20000002BB83 +:101050000001A1FD00604411000002E000003FFF1C +:10106000002F022F00000000000000000CC0000054 +:101070000000015800000000C04004000000000112 +:101080000000225C0020441100000000000000016C +:1010900000300A2F000000000000000100210A2299 +:1010A000000000000000000300384A220000000099 +:1010B0000000225600204411000000000000001A29 +:1010C00000204811000000000000A1FC0020441195 +:1010D0000000000000000001008048110000000036 +:1010E00000000000006000000000000B0000000095 +:1010F000006000000000018F0000000000600000A0 +:10110000000001A000003FFF002F022F00000000A0 +:10111000000000000CE000000000000000000000E3 +:1011200000202C0800000000000000000020241116 +:101130000000000000000000002028110000000056 +:10114000000022560020441100000000000000169C +:1011500000204811000000000000225C0020441123 +:101160000000000000000003002048110000000003 +:1011700093800000002044110000000000000002E5 +:1011800000221E290000000000000000007048EB53 +:101190000000019C0000000000600000000002BB95 +:1011A00000000001403306200000000000000000A5 +:1011B000C03024090000000000003FFF002F022F74 +:1011C00000000000000000000CE000000000000033 +:1011D0000000000000600000000002A3000000000A +:1011E000002F022100000000000000000AE00000C3 +:1011F0000000018100000000006000000000013AD2 +:101200000000000000400000000001869500000082 +:10121000002044110000000000000000002F022107 +:1012200000000000000000000CE00000000001864B +:1012300000000000C0204800000000000000000185 +:10124000005306210000018292000000002044119A +:101250000000000000000000C0604800000001978E +:101260000001A1FD00204411000000000000001159 +:101270000020062D00000000000000000078042A75 +:10128000000002FB00000000002028090000000010 +:1012900000003FFF002F022F0000000000000000B0 +:1012A0000CC000000000017400000000C0400400F9 +:1012B000000000010000021000600411000003158E +:1012C00000003FFF002F022F000000000000000080 +:1012D0000CE000000000019400000015C020362042 +:1012E0000000000000000016C020362000000000B2 +:1012F0003F800000002004110000000046000000B4 +:1013000000600811000001B2000000000080000031 +:10131000000000000000A1FC0020441100000000BB +:1013200000003FFF002F022F00000000000000001F +:101330000CC000000000019B00000001008048116B +:1013400000000000000000210080481100000000A3 +:101350000000FFFF40280E200000000000000010E9 +:10136000C0211220000000000000FFFF40281620CE +:101370000000000000000010C0811A2000000000E2 +:101380008100000000204411000000000000000661 +:1013900000204811000000000000000800221E305C +:1013A000000000000000002900201A2D00000000AD +:1013B0000000E0000020441100000000FFFBFF09D6 +:1013C00000204811000000000000000F0020222D26 +:1013D0000000000000001FFF00294A280000000054 +:1013E000000000060020222D000000000000000088 +:1013F000002920E80000000000000000002048084C +:101400000000000000000000002048110000000063 +:10141000060A020000294A26000000000000000021 +:1014200000204811000000000000000000204811CA +:101430000000000000000100002018110000000062 +:101440000000000800621E280000012F00000008B4 +:1014500000822228000000000002C0000020441189 +:10146000000000000000001500600E2D000001BD0E +:101470000000001600600E2D000001BD0000C00835 +:1014800000204411000000000000001700200E2D75 +:10149000000000000000000014C00000000001B9BE +:1014A0000000000000200411000000000000000007 +:1014B0000020480100000000390000000020481111 +:1014C00000000000000000000020481100000000A3 +:1014D000000000000080480200000000000000182A +:1014E00000202E2D0000000000000000003B0D63D6 +:1014F000000000000000000800224A230000000055 +:101500000000001000224A23000000000000001824 +:1015100000224A2300000000000000000080480371 +:101520000000000000000000006000000000000B50 +:10153000000010000060041100000315000000000E +:1015400000200411000000000000000000600811ED +:10155000000001B2000000070021062F000000007B +:101560000000001300200A2D000000000000000110 +:1015700000202C11000000000000FFFF4028222066 +:10158000000000000000000F0026222800000000DC +:101590000000001040212620000000000000000F85 +:1015A000002626290000000000000000002028027C +:1015B000000000000000225600204411000000003E +:1015C0000000001B00204811000000000000000087 +:1015D000002F022100000000000000000CE00000CD +:1015E000000001E00000225C002044110000000027 +:1015F0000000008100204811000000000000A1FC54 +:1016000000204411000000000000000100204811EB +:10161000000000000000008000201C1100000000FD +:1016200000000000002F0227000000000000000062 +:101630000CE00000000001DC000000000060000081 +:10164000000001E90000000100531E27000001D83E +:101650000000000100202C11000000000000001F0D +:1016600000280A22000000000000001F00282A2A8B +:10167000000000000000000100530621000001D11D +:101680000000225C00204411000000000000000265 +:1016900000304A2F000000000000A1FC002044118F +:1016A00000000000000000010020481100000000C0 +:1016B0000000000100301E2F0000000000000000AC +:1016C000002F022700000000000000000CE00000D6 +:1016D000000000000000000000600000000001E9C0 +:1016E0000000000100531E27000001E50000FFFF7D +:1016F00040280E20000000000000000F00260E23EE +:101700000000000000000010C021122000000000B6 +:101710000000000F0026122400000000000000005E +:1017200000201411000000000000000000601811EB +:10173000000002BB0001A1FD0020441100000000D8 +:1017400000000000002F022B00000000000000003D +:101750000CE00000000001F8000000100022162834 +:1017600000000000FFFF0000002816250000000018 +:101770000000FFFF00281A29000000000000000000 +:10178000002948C500000000000000000020480AB1 +:10179000000000000000000000202C1100000000EC +:1017A000000000100022162300000000FFFF0000D0 +:1017B00000281625000000000000FFFF00281A2462 +:1017C0000000000000000000002948C500000000E3 +:1017D0000000000000731503000002050000000077 +:1017E0000020180500000000000000000073152410 +:1017F0000000020500000000002D14C500000000DC +:1018000000000000003008A20000000000000000FE +:101810000020480200000000000000000020280214 +:101820000000000000000000002020030000000075 +:101830000000000000802404000000000000000FF1 +:1018400000210225000000000000000014C000007C +:101850000000067B00000000002B140500000000C3 +:1018600000000001009016250000000000000000AC +:10187000006000000000000B000000000060041188 +:10188000000003150000000000200411000000000B +:101890000000000000600811000001B200002256A4 +:1018A00000204411000000000000001A00294A2214 +:1018B0000000000000000000C02000000000000048 +:1018C00000003FFF002F022F00000000000000007A +:1018D0000CE000000000000000000000C020040038 +:1018E000000000000000225C002044110000000005 +:1018F0000000000300384A21000000000000A1FCA5 +:1019000000204411000000000000000100204811E8 +:10191000000000000000FFFF40281220000000002F +:1019200000000010C0211A20000000000000FFFF8E +:1019300040280E200000000000000010C0211620EA +:10194000000000000000000000741465000002BBED +:101950000001A1FD00604411000002E00000000150 +:10196000003306210000000000000000002F0221CB +:1019700000000000000000000CC000000000021980 +:1019800000003FFF002F022F0000000000000000B9 +:101990000CC000000000021200000000C040040063 +:1019A0000000000100000000006000000000063898 +:1019B000000000000040040F0000021300000000BF +:1019C000006000000000062400000000006000002D +:1019D000000006380000021000600411000003152A +:1019E0000000000000600000000001A000000000F6 +:1019F000006000000000019C00000000006000008A +:101A0000000002BB0000000000600000000002A314 +:101A1000938000000020441100000000000000003E +:101A2000002048080000000000000000002F022FE6 +:101A300000000000000000000AE000000000023288 +:101A400000000000006000000000013A00000000FB +:101A50000040000000000236950000000020441104 +:101A60000000000000000000002F022F0000000016 +:101A7000000000000CE00000000002360000000042 +:101A8000C0404800000002339200000000204411D2 +:101A90000000000000000000C0204800000000001E +:101AA0000000225600204411000000000000001633 +:101AB00000204811000000000000225C00204411BA +:101AC000000000000000000300204811000000009A +:101AD0000000A1FC002044110000000000000001F3 +:101AE00000204811000000000001A1FD0020441169 +:101AF000000000000000000000600411000002FB74 +:101B000000000000C04004000000000100000000D0 +:101B100000600000000006240000A00C002044111A +:101B20000000000000000000C0204800000000008D +:101B300000000000C040480000000000000000005D +:101B4000006000000000000B0000001840210A2087 +:101B50000000000000000003002F0222000000002F +:101B6000000000000AE000000000024C0000001429 +:101B70000020222D00000000000801010029222879 +:101B800000000000000000140020362800000000C3 +:101B90000000A30C00204411000000000000000021 +:101BA000C02048000000000000000000C0204800E5 +:101BB0000000000000000000C0404800000002518A +:101BC00000000000006000000000000B000000109A +:101BD00000600411000003153F8000000020041184 +:101BE000000000000000000000600811000001B2C9 +:101BF0000000225C002044110000000000000003EF +:101C000000204811000000000000000000600000FB +:101C10000000027C0000001700201E2D00000000C4 +:101C20000000000100211E2700000000000000004D +:101C300014E000000000026A0000001200201E2DC7 +:101C4000000000000000FFFF00281E270000000029 +:101C50000000000000341C2700000000000000000D +:101C600012C000000000025F0000000000201C11F4 +:101C70000000000000000000002F00E50000000050 +:101C80000000000008C00000000002620000000028 +:101C900000201407000000000000001200201E2D8C +:101CA000000000000000001000211E2700000000BE +:101CB0000000000000341C4700000000000000008D +:101CC00012C00000000002670000000000201C118C +:101CD0000000000000000000002F00E600000000EF +:101CE0000000000008C000000000026A00000000C0 +:101CF0000020180700000000000000000060000045 +:101D0000000002C100002256002044110000000023 +:101D1000000000000034202300000000000000004C +:101D200012C00000000002720000000000342044D5 +:101D3000000000000000000012C00000000002715E +:101D40000000001600404811000002760000001854 +:101D500000404811000002760000000000342044DA +:101D6000000000000000000012C00000000002752A +:101D70000000001700404811000002760000001922 +:101D800000204811000000000000A1FC00204411C8 +:101D900000000000000000010020481100000000C9 +:101DA0000001A1FD00604411000002E900003FFFB6 +:101DB000002F022F00000000000000000CC00000F7 +:101DC0000000025600000000C040040000000001B6 +:101DD0000000001040210620000000000000FFFF6E +:101DE000C0280A20000000000000001040210E2042 +:101DF000000000000000FFFFC028122000000000CB +:101E00000000001040211620000000000000FFFF2D +:101E1000C0881A200000000081000000002044114A +:101E20000000000000000001002048110000000038 +:101E300000042004006044110000067C0000000043 +:101E4000006000000000062400000000C0600000E8 +:101E5000000002A30000000500200A2D0000000081 +:101E60000000000800220A22000000000000002BF1 +:101E700000201A2D000000000000001C00201E2D74 +:101E8000000000000000700000281E270000000075 +:101E90000000000000311CE6000000000000002AE5 +:101EA00000201A2D000000000000000C00221A265D +:101EB0000000000000000000002F00E6000000000D +:101EC0000000000006E00000000002920000000098 +:101ED00000201C11000000000000000000200C1178 +:101EE000000000000000002B00203623000000004E +:101EF0000000001000201811000000000000000089 +:101F000000691CE20000012F9380000000204411B2 +:101F10000000000000000000002048070000000052 +:101F200095000000002044110000000000000000A7 +:101F3000002F022F00000000000000000CE0000055 +:101F40000000029D0000000100333E2F0000000051 +:101F500000000000D90048000000000092000000CE +:101F6000002044110000000000000000C0204800D4 +:101F7000000000000000001C0040362700000000A8 +:101F80000000000CC0220A20000000000000002910 +:101F9000002036220000000000000028C04036204B +:101FA000000000000000A2A4002044110000000076 +:101FB000000000090020481100000000A1000000FE +:101FC00000204411000000000000000100804811C2 +:101FD000000000000000002100201E2D0000000075 +:101FE00000000000002C1CE30000000000000021A5 +:101FF00000203627000000000000002200201E2DD7 +:102000000000000000000000002C1CE400000000A4 +:1020100000000022002036270000000000000023FE +:1020200000201E2D0000000000000000003120A351 +:102030000000000000000000002D1D07000000004F +:1020400000000023002036270000000000000024CC +:1020500000201E2D0000000000000000003120C400 +:102060000000000000000000002D1D07000000001F +:10207000000000240080362700000000000000213E +:10208000002036230000000000000022002036243B +:10209000000000000000000000311CA30000000050 +:1020A0000000002300203627000000000000000090 +:1020B00000311CC40000000000000024008036270E +:1020C000000000000000001A002036270000000079 +:1020D0000000001B00203628000000000000001750 +:1020E00000201E2D00000000000000020021022739 +:1020F000000000000000000014C00000000002DC2E +:102100000000000000400000000002D90000001A9A +:1021100000203627000000000000001B00203628A9 +:10212000000000000000001700201E2D000000002D +:102130000000000200210227000000000000000053 +:1021400014E00000000002D9000000030021022773 +:10215000000000000000000014E00000000002DCAD +:102160000000002300201E2D0000000000000000E1 +:10217000002E00E1000000000000000002C000008E +:10218000000002DC0000002100201E2D00000000E5 +:1021900000000000003120A100000000000000004D +:1021A000002E00E8000000000000000006C0000053 +:1021B000000002DC0000002400201E2D00000000B2 +:1021C00000000000002E00E20000000000000000FF +:1021D00002C00000000002DC0000002200201E2DD2 +:1021E0000000000000000000003120C200000000DC +:1021F00000000000002E00E80000000000000000C9 +:1022000006C00000000002DC0000000000600000CA +:10221000000006590000000000600000000002B548 +:102220000000000000400000000002DE000000008E +:1022300000600000000002B5000000000060000027 +:10224000000006500000000000400000000002DE18 +:102250000000000000600000000002A70000000075 +:1022600000400000000002DE0000001A00201E2DC9 +:10227000000000000000001B0080222D0000000074 +:102280000000001000221E230000000000000000DB +:1022900000294887000000000000000000311CA356 +:1022A000000000000000001000221E2700000000B7 +:1022B0000000000000294887000000000000001016 +:1022C00000221E230000000000000000003120C496 +:1022D000000000000000FFFF00282228000000008E +:1022E0000000000000894907000000000000001005 +:1022F00000221E2300000000000000000029488783 +:10230000000000000000001000221E21000000005C +:102310000000000000294847000000000000000005 +:1023200000311CA3000000000000001000221E2746 +:1023300000000000000000000029488700000000A5 +:102340000000000000311CA100000000000000108F +:1023500000221E270000000000000000002948475E +:10236000000000000000001000221E2300000000FA +:1023700000000000003120C4000000000000FFFF4A +:102380000028222800000000000000000029490762 +:10239000000000000000001000221E2100000000CC +:1023A00000000000003120C2000000000000FFFF1C +:1023B00000282228000000000000000000894907D2 +:1023C000000000000000001000221E23000000009A +:1023D0000000000000294887000000000000000104 +:1023E00000220A210000000000000000003308A2C3 +:1023F000000000000000001000221E22000000006B +:102400000000001000212222000000000000000057 +:1024100000294907000000000000000000311CA353 +:10242000000000000000001000221E270000000035 +:1024300000000000002948870000000000000001A3 +:1024400000220A210000000000000000003008A265 +:10245000000000000000001000221E22000000000A +:1024600000000010002122220000000000000000F7 +:1024700000294907000000000000001000221E2370 +:102480000000000000000000003120C40000000037 +:102490000000FFFF002822280000000000000000CC +:1024A000002949070000000000000000003808C5AE +:1024B00000000000000000000030084100000000A3 +:1024C0000000000100220A220000000000000000BD +:1024D000003308A2000000000000001000221E22AD +:1024E0000000000000000010002122220000000077 +:1024F00000000000008949070000000000000017EC +:102500000020222D000000000000000014C0000088 +:1025100000000318FFFFFFEF002806210000000065 +:10252000000000140020222D000000000000F8E050 +:1025300000204411000000000000000000294901B3 +:1025400000000000000000000089490100000000B8 +:102550000000000000204811000000000000000002 +:102560000020481100000000060A02000080481107 +:102570000000000000000000C0200000000000007B +:1025800097000000C020441100000000000000007F +:10259000C0204811000000008A0000000020441103 +:1025A00000000000000000000020481100000000B2 +:1025B0000000225C00204411000000000000000028 +:1025C000C0204800000000000000A1FC00204411D1 +:1025D0000000000000000000C020480000000000D3 +:1025E00000000000C0200400000000000000000007 +:1025F00000A0000A00000000970000000020441125 +:102600000000000000000000002048110000000051 +:102610008A000000002044110000000000000000BB +:1026200000204811000000000000225C002044113E +:102630000000000000000000C02048000000000072 +:102640000000A1FC00204411000000000000000078 +:10265000C02048000000000000000000C02004006E +:10266000000000000000000000A0000A00000000C0 +:10267000970000000020441100000000000000004E +:1026800000204811000000008A00000000204411D2 +:1026900000000000000000000020481100000000C1 +:1026A0000000225C00204411000000000000000037 +:1026B000C0204800000000000000A1FC00204411E0 +:1026C0000000000000000000C020480000000000E2 +:1026D0000001A1FD002044110000000000000000E6 +:1026E000D90048000000000000000000C0200400E5 +:1026F000000000000000000000A0000A0000000030 +:1027000000002257002044110000000000000003D8 +:10271000C0484A20000000000000225D0020441153 +:102720000000000000000000C04048000000000061 +:1027300000000000006000000000063800000000FB +:10274000C0200800000000000000225C00204411AE +:10275000000000000000000300384A2200000000D2 +:102760000000A1FC00204411000000000000000057 +:10277000C0204800000000000001A1FD002044111D +:102780000000000000000000002F022200000000F6 +:10279000000000000CE0000000000000000000004D +:1027A00040204800000000000000000140304A20A6 +:1027B0000000000000000002C0304A2000000000BD +:1027C0000000000100530A220000034B0000003FFC +:1027D000C0280A20000000008100000000204411F1 +:1027E000000000000000000100204811000000006F +:1027F000000021F800204411000000000000001833 +:102800000020481100000000000421F9006044117C +:102810000000067C000000110021023000000000D2 +:102820000000000014E00000000003540000001449 +:10283000002F022200000000000000000CC0000079 +:10284000000003620001A2A4002044110000000067 +:1028500000000000006048020000036A0000210040 +:10286000002044110000000000000000C0204800CB +:102870000000000000000000C02048000000000030 +:1028800000000000C0204800000000000000000020 +:10289000C04048000000000000000004002F022299 +:1028A00000000000000000000CC0000000000366F3 +:1028B0000001A2A40020441100000000000000005C +:1028C000004048020000035D00000028002F0222A3 +:1028D00000000000000000000CC00000000005B374 +:1028E0000001A2A40020441100000000000000002C +:1028F000004048020000035D0000002C0020362646 +:102900000000000000000049002018110000000035 +:102910000000003F002048110000000000000001FE +:1029200000331A260000000000000000002F0226DD +:1029300000000000000000000CC000000000036C5C +:102940000000002C00801A2D000000000000003F55 +:10295000C0280A200000000000000015002F0222FD +:1029600000000000000000000CE0000000000382F6 +:1029700000000006002F02220000000000000000FE +:102980000CE00000000003AD00000016002F022242 +:1029900000000000000000000CE00000000003AF99 +:1029A00000000020002F02220000000000000000B4 +:1029B0000CE00000000003980000000F002F02222E +:1029C00000000000000000000CE00000000003A474 +:1029D00000000010002F0222000000000000000094 +:1029E0000CE00000000003A40000001E002F0222E3 +:1029F00000000000000000000CE000000000038C5C +:102A00000000A2A40020441100000000000000000B +:102A100000404802000000000800000000290A22CF +:102A2000000000000000000340210E200000000014 +:102A30000000000CC021122000000000000800006F +:102A4000002812240000000000000014C0221620FC +:102A50000000000000000000002914A40000000095 +:102A60000000A2A4002044110000000000000000AB +:102A7000002948A2000000000000A1FE002044112F +:102A800000000000000000000040480300000000BB +:102A9000810000000020441100000000000000013F +:102AA0000020481100000000000021F8002044111F +:102AB0000000000000000016002048110000000087 +:102AC000000421F9006044110000067C000000159C +:102AD00000210230000000000000000014E00000AF +:102AE0000000038E0000210E0020441100000000B1 +:102AF00000000000C02048000000000000000000AE +:102B0000C0204800000000000000A2A400204411E2 +:102B1000000000000000000000404802000000002B +:102B200081000000002044110000000000000001AE +:102B30000020481100000000000021F8002044118E +:102B400000000000000000170020481100000000F5 +:102B5000000421F9006044110000067C000000031D +:102B600000210230000000000000000014E000001E +:102B70000000039A0000210800204411000000001A +:102B800000000000C020480000000000000000001D +:102B9000C0204800000000000000A2A40020441152 +:102BA000000000000000000000404802000000009B +:102BB0000000A2A40020441100000000000000005A +:102BC00000204802000000008000000000204411A6 +:102BD000000000000000000000204811000000007C +:102BE00081000000002044110000000000000010DF +:102BF000002048110000000000000000002000102C +:102C0000000000000000000014C00000000003AA43 +:102C10000000000000400000000000000001A2A42D +:102C20000020441100000000000000060040481190 +:102C3000000000000001A2A40020441100000000D8 +:102C400000000016006048110000036A0000000048 +:102C5000004000000000000000000000C02008004C +:102C60000000000000000000C0200C000000000078 +:102C70000000001D002102230000000000000000F1 +:102C800014E00000000003C4810000000020441193 +:102C900000000000000000010020481100000000BA +:102CA000000021F80020441100000000000000187E +:102CB0000020481100000000000421F900604411C8 +:102CC0000000067C0000001100210230000000001E +:102CD0000000000014E00000000003B80000210024 +:102CE0000020441100000000000000000020480205 +:102CF0000000000000000000002048030000000069 +:102D0000BABECAFE0020481100000000CAFEBABECA +:102D100000204811000000000000A2A4002044117F +:102D20000000000000000004004048110000000006 +:102D3000000021700020441100000000000000008D +:102D400000204802000000000000000000204803AE +:102D5000000000008100000000204411000000007D +:102D60000000000A002048110000000000000000E0 +:102D700000200010000000000000000014C000004F +:102D8000000003C98C000000002044110000000076 +:102D9000CAFEBABE004048110000000081000000D9 +:102DA0000020441100000000000000010020481134 +:102DB0000000000000003FFF40280A200000000043 +:102DC0008000000040280E200000000040000000AD +:102DD000C028122000000000000400000069462204 +:102DE0000000067C0000000000201410000000001D +:102DF00000000000002F022300000000000000007F +:102E00000CC00000000003D700000000C040180004 +:102E1000000003DA00003FFFC0281A200000000075 +:102E200000040000006946260000067C0000000047 +:102E3000002018100000000000000000002F0224F5 +:102E400000000000000000000CC00000000003DDD6 +:102E500000000000C0401C00000003E000003FFF35 +:102E6000C0281E2000000000000400000069462762 +:102E70000000067C0000000000201C100000000084 +:102E800000000000002044020000000000000000DC +:102E9000002820C50000000000000000004948E8AC +:102EA00000000000A58000000020081100000000C4 +:102EB0000000200000200C11000000008300000032 +:102EC00000604411000004080000000000204402DB +:102ED0000000000000000000C020480000000000CA +:102EE0000000000040204800000000000000001F1B +:102EF000C0210220000000000000000014C00000FB +:102F0000000003ED0000201000204411000000002C +:102F10000000800000204811000000000000FFFFBA +:102F2000C0481220000003F5A7800000002008110F +:102F3000000000000000A00000200C1100000000B4 +:102F4000830000000060441100000408000000003D +:102F5000002044020000000000000000C0204800E3 +:102F60000000000000000000C02048000000000039 +:102F70000000FFFFC02812200000000083000000B6 +:102F800000204411000000000000000000304883D1 +:102F90000000000084000000002044110000000038 +:102FA00000000000C02048000000000000000000F9 +:102FB0001D000000000000008300000000604411BC +:102FC0000000040800000000C040040000000001F0 +:102FD000A980000000200811000000000000C000CF +:102FE00000400C11000003F0AB800000002008112D +:102FF000000000000000F8E000400C11000003F0A9 +:10300000AD80000000200811000000000000F880E2 +:1030100000400C11000003F0B380000000200811F4 +:10302000000000000000F3FC00400C11000003F061 +:10303000AF80000000200811000000000000E00048 +:1030400000400C11000003F0B180000000200811C6 +:10305000000000000000F00000400C11000003F030 +:1030600083000000002044110000000000002148FF +:1030700000204811000000008400000000204411DE +:103080000000000000000000C02048000000000018 +:10309000000000001D000000000000000000000013 +:1030A000008000000000000001182000C030462011 +:1030B0000000000000000000D900480000000000EF +:1030C00000000000C020040000000000000000001C +:1030D00000A0000A000000000218A000C030462036 +:1030E0000000000000000000D900480000000000BF +:1030F00000000000C02004000000000000000000EC +:1031000000A0000A000000000318C000C0304620E4 +:103110000000000000000000D9004800000000008E +:1031200000000000C02004000000000000000000BB +:1031300000A0000A000000000418F8E0C03046209B +:103140000000000000000000D9004800000000005E +:1031500000000000C020040000000000000000008B +:1031600000A0000A000000000518F880C0304620CA +:103170000000000000000000D9004800000000002E +:1031800000000000C020040000000000000000005B +:1031900000A0000A000000000618E000C030462031 +:1031A0000000000000000000D900480000000000FE +:1031B00000000000C020040000000000000000002B +:1031C00000A0000A000000000718F000C0304620F0 +:1031D0000000000000000000D900480000000000CE +:1031E00000000000C02004000000000000000000FB +:1031F00000A0000A000000000818F3FCC0304620C0 +:103200000000000000000000D9004800000000009D +:1032100000000000C02004000000000000000000CA +:1032200000A0000A000000000000003000200A2D6D +:103230000000000000000000C0290C400000000059 +:1032400000000030002036230000000000000000D5 +:10325000C0200400000000000000000000A0000AE0 +:103260000000000086000000002044110000000063 +:103270000000000000404801000000008500000040 +:10328000C020441100000000000000000040480180 +:10329000000000000000217C00204411000000001C +:1032A00000000000C02048000000000000000000F6 +:1032B000C02048000000000000000000C0204800BE +:1032C0000000000081000000002044110000000008 +:1032D0000000000100204811000000000000000074 +:1032E000C0200800000000000000000017000000DF +:1032F000000000000004217F006044110000067CF3 +:103300000000001F0021023000000000000000004B +:1033100014C00000000000000000000000404C024B +:103320000000043E00000000C0200C00000000006F +:1033300000000000C020100000000000000000009D +:10334000C02014000000000000000000C020180091 +:103350000000000000000000C0201C000000000071 +:1033600000007F0000280A21000000000000450046 +:10337000002F022200000000000000000CE000000E +:103380000000044C00000000C020200000000000ED +:103390000000000017000000000000000000001006 +:1033A00000280A230000000000000010002F022265 +:1033B00000000000000000000CE0000000000454C9 +:1033C0008100000000204411000000000000000106 +:1033D000002048110000000000040000006946249D +:1033E0000000067C000000000040000000000459BE +:1033F00081000000002044110000000000000000D7 +:1034000000204811000000000000216D0020441140 +:103410000000000000000000002048040000000040 +:103420000000000000604805000006810000000068 +:10343000002824F0000000000000000700280A23F4 +:103440000000000000000001002F02220000000028 +:10345000000000000AE0000000000460000000001E +:10346000002F00C9000000000000000004E0000080 +:103470000000047900000000004000000000048605 +:1034800000000002002F02220000000000000000E7 +:103490000AE000000000046500000000002F00C9E1 +:1034A000000000000000000002E0000000000479BD +:1034B000000000000040000000000486000000033F +:1034C000002F022200000000000000000AE00000BF +:1034D0000000046A00000000002F00C90000000086 +:1034E000000000000CE00000000004790000000073 +:1034F000004000000000048600000004002F0222AB +:1035000000000000000000000AE000000000046F5E +:1035100000000000002F00C90000000000000000B3 +:103520000AE00000000004790000000000400000F4 +:103530000000048600000005002F022200000000A9 +:10354000000000000AE00000000004740000000019 +:10355000002F00C9000000000000000006E000008D +:103560000000047900000000004000000000048614 +:1035700000000006002F02220000000000000000F2 +:103580000AE000000000047900000000002F00C9DC +:10359000000000000000000008E0000000000479C6 +:1035A00000000000004000000000048600007F00D2 +:1035B00000280A210000000000004500002F022220 +:1035C00000000000000000000AE000000000000011 +:1035D0000000000800210A23000000000000000095 +:1035E00014C0000000000483000021690020441181 +:1035F0000000000000000000C020480000000000A3 +:1036000000000000C0204800000000000000000092 +:10361000C020480000000000CAFEBABE00404811A9 +:103620000000000000000000C02044000000000076 +:1036300000000000C02000000000000000000000AA +:10364000C04048000000000000007F0000280A2160 +:103650000000000000004500002F022200000000D2 +:10366000000000000AE000000000048C00000000E0 +:10367000C02000000000000000000000C02000008A +:103680000000000000000000C0400000000000003A +:103690000000000000404C080000044C0000000046 +:1036A000C0200800000000000000001040210E2093 +:1036B0000000000000000011402112200000000066 +:1036C00000000012402116200000000000002169C7 +:1036D000002044110000000000000000002048020B +:1036E0000000000000000000002102250000000092 +:1036F0000000000014E00000000004960004000038 +:10370000C0494A2000000497FFFBFFFFC0284A2061 +:103710000000000000000000002102230000000063 +:103720000000000014E00000000004A300000000FE +:10373000C02048000000000000000000C020480039 +:103740000000000000000000002102240000000032 +:103750000000000014C00000000000008100000014 +:1037600000204411000000000000000C002048115F +:103770000000000000000000002000100000000019 +:103780000000000014C000000000049FA000000022 +:103790000020441100000000CAFEBABE00404811DB +:1037A0000000000081000000002044110000000023 +:1037B0000000000400204811000000000000216B00 +:1037C000002044110000000000000000C02048104C +:1037D00000000000810000000020441100000000F3 +:1037E0000000000500204811000000000000216CCE +:1037F000002044110000000000000000C02048101C +:103800000000000000000000002F02240000000063 +:10381000000000000CE000000000000000000000BC +:10382000004000000000049D00000000C0210A20AC +:10383000000000000000000014C00000000004B6FA +:103840008100000000204411000000000000000082 +:1038500000204811000000000000216D00204411EC +:103860000000000000000000C02048000000000030 +:1038700000000000C0604800000006810000000059 +:1038800000400000000004BA810000000020441144 +:1038900000000000000000010020481100000000AE +:1038A00000040000C02946200000000000000000C5 +:1038B000C06000000000067C000000010021022220 +:1038C000000000000000000014C00000000004C15F +:1038D00000002169002044110000000000000000E9 +:1038E000C02048000000000000000000C020480088 +:1038F0000000000000000000002048100000000050 +:10390000CAFEBABE004048110000000000000000DE +:10391000C02044000000000000000000C04048102B +:1039200000000000810000000020441100000000A1 +:10393000000000010020481100000000000021F8F4 +:1039400000204411000000000000000E002048117B +:1039500000000000000421F9006044110000067C12 +:103960000000000000210230000000000000000004 +:1039700014C00000000004C3000021800020441196 +:103980000000000000000000C0204800000000000F +:1039900000000000C0200000000000000000000047 +:1039A000C02048000000000000000000C02000000F +:1039B0000000000000000000C040480000000000BF +:1039C0000000000300333E2F000000000000000153 +:1039D00000210221000000000000000014E00000AF +:1039E000000004F30000002C00200A2D000000005D +:1039F0000004000018E00C11000004E200000001C7 +:103A000000333E2F00000000000021690020441117 +:103A1000000000000000000000204802000000003C +:103A20000000000000204803000000000000000823 +:103A300000300A220000000000000000C020480002 +:103A40000000000000000000C0204800000000004E +:103A50000000216900204411000000000000000067 +:103A60000020480200000000000000000020480381 +:103A7000000000000000000800300A2200000000E2 +:103A800000000000C020480000000000000000000E +:103A9000D8C04800000004D600002169002044116D +:103AA00000000000000000000020480200000000AC +:103AB0000000000000204803000000000000000893 +:103AC00000300A220000000000000000C020480072 +:103AD0000000000000000000C020480000000000BE +:103AE0000000002D0020122D00000000000000004A +:103AF00000290C830000000000002169002044110F +:103B0000000000000000000000204802000000004B +:103B10000000000000204803000000000000000832 +:103B200000300A220000000000000000C020480011 +:103B30000000000000000000C0204800000000005D +:103B4000000000110021022400000000000000001D +:103B500014C0000000000000000000000040000051 +:103B60000000049D0000002CC02036200000000052 +:103B70000000002DC0403620000000000000000FB3 +:103B800000210221000000000000000014C000001D +:103B9000000004F800000000006000000000000BBE +:103BA00000000000D900000000000000000000003C +:103BB000C040040000000001B500000000204411D6 +:103BC000000000000000200000204811000000005C +:103BD000B600000000204411000000000000A0001A +:103BE0000020481100000000B70000000020441130 +:103BF000000000000000C00000204811000000008C +:103C0000B800000000204411000000000000F8E0AF +:103C10000020481100000000B900000000204411FD +:103C2000000000000000F8800020481100000000A3 +:103C3000BA00000000204411000000000000E00075 +:103C40000020481100000000BB00000000204411CB +:103C5000000000000000F0000020481100000000FB +:103C6000BC00000000204411000000000000F3FC34 +:103C700000204811000000008100000000204411D5 +:103C800000000000000000020020481100000000B9 +:103C9000000000FF00280E300000000000000000BF +:103CA000002F022300000000000000000CC00000F4 +:103CB0000000050C00000000C0200800000000000B +:103CC0000000000014C000000000052100000000FA +:103CD00000200C11000000000000001C0020362312 +:103CE000000000000000002B002036230000000030 +:103CF00000000029002036230000000000000028FA +:103D000000203623000000000000001700203623AA +:103D10000000000000000025002036230000000005 +:103D200000000026002036230000000000000015DF +:103D3000002036230000000000000016002036237B +:103D400000000000FFFFE00000200C110000000058 +:103D500000000021002036230000000000000022A7 +:103D6000002036230000000000001FFF00200C117F +:103D700000000000000000230020362300000000A7 +:103D8000000000240020362300000000F1FFFFFFA8 +:103D900000283A2E000000000000001AC0220E2069 +:103DA00000000000000000000029386E0000000044 +:103DB0008100000000204411000000000000000607 +:103DC00000204811000000000000002A402036209A +:103DD00000000000870000000020441100000000E7 +:103DE00000000000C0204800000000000000A1F416 +:103DF00000204411000000000000000000204810D6 +:103E0000000000000000000000200C110000000075 +:103E10000000003000203623000000009D0000005C +:103E200000204411000000000000001F40214A2033 +:103E30000000000096000000002044110000000077 +:103E400000000000C020480000000000000000004A +:103E5000C0200C000000000000000000C020100086 +:103E6000000000000000001F0021162400000000D8 +:103E70000000000014C00000000000000000001D51 +:103E800000203623000000000000000300281E234D +:103E900000000000000000080022222300000000B3 +:103EA000FFFFF000002822280000000000000000B2 +:103EB000002920E8000000000000001F0020362834 +:103EC000000000000000001800211E230000000078 +:103ED0000000002000203627000000000000000243 +:103EE000002216240000000000000000003014A88A +:103EF000000000000000001E002036250000000029 +:103F00000000000300211A2400000000100000003F +:103F100000281A2600000000EFFFFFFF00283A2EBD +:103F20000000000000000000004938CE0000066AD2 +:103F30000000000140280A200000000000000006E8 +:103F400040280E200000000000000300C0281220BE +:103F50000000000000000008002112240000000002 +:103F600000000000C020162000000000000000003B +:103F7000C0201A20000000000000000000210222E2 +:103F8000000000000000000014C0000000000559FF +:103F9000810000000020441100000000000000012A +:103FA00000204811000000000000225800300A24C0 +:103FB0000000000000040000006946220000067CAA +:103FC00000002169002044110000000000000000F2 +:103FD00000204805000000000002000000294A26D9 +:103FE0000000000000000000002048100000000059 +:103FF000CAFEBABE00204811000000000000000206 +:10400000002F022300000000000000000CC0000090 +:104010000000056100000000C0201C10000000002E +:1040200000000000C04000000000056F000000021A +:10403000002F022300000000000000000CC0000060 +:104040000000056181000000002044110000000014 +:10405000000000010020481100000000000022586C +:1040600000300A240000000000040000006946221D +:104070000000067C00000000C0201C1000000000B2 +:1040800000000000C04000000000056F00000000BC +:10409000002F022300000000000000000CC0000000 +:1040A0000000056500000000C0201C0000000000AA +:1040B00000000000C04000000000056F0000000488 +:1040C000002F022300000000000000000CC00000D0 +:1040D0000000056D81000000002044110000000078 +:1040E0000000000000204811000000000000216DC9 +:1040F000002044110000000000000000C020480023 +:104100000000000000000000C060480000000681C0 +:104110000000000000401C100000056F00000000BF +:10412000C02000000000000000000000C0400000AF +:1041300000000000000000000EE00000000005711B +:104140000000000000600000000005BC000000004E +:10415000002F022400000000000000000CC000003E +:10416000000005820000A2B70020441100000000FA +:10417000000000000020480700000000810000004F +:104180000020441100000000000000010020481140 +:10419000000000000004A2B6006044110000067C8C +:1041A0000000001A0021223000000000000000067C +:1041B00000222630000000000004200400604411AA +:1041C0000000067C0000A2C4002044110000000092 +:1041D00000000000003048E900000000000000007E +:1041E00000E00000000005800000A2D10020441182 +:1041F000000000000000000000404808000000002F +:104200000000A2D1002044110000000000000001C5 +:1042100000504A280000000000000001002F022486 +:1042200000000000000000000CC00000000005932A +:104230000000A2BB002044110000000000000000AC +:104240000020480700000000810000000020441109 +:1042500000000000000000010020481100000000E4 +:104260000004A2BA006044110000067C0000001A9D +:10427000002122300000000000000006002226304D +:104280000000000000042004006044110000067CCF +:104290000000A2C500204411000000000000000042 +:1042A000003048E9000000000000000000E00000CD +:1042B000000005910000A2D200204411000000007F +:1042C0000000000000404808000000000000A2D2EA +:1042D00000204411000000000000000100504A28A6 +:1042E0000000000000000002002F02240000000077 +:1042F000000000000CC00000000005A40000A2BFE8 +:1043000000204411000000000000000000204807C9 +:1043100000000000810000000020441100000000A7 +:104320000000000100204811000000000004A2BEAF +:10433000006044110000067C0000001A00212230B9 +:1043400000000000000000060022263000000000EF +:1043500000042004006044110000067C0000A2C696 +:10436000002044110000000000000000003048E977 +:10437000000000000000000000E00000000005A2B6 +:104380000000A2D300204411000000000000000043 +:1043900000404808000000000000A2D300204411A3 +:1043A000000000000000000100504A28000000004A +:1043B0000000A2C300204411000000000000000023 +:1043C0000020480700000000810000000020441188 +:1043D0000000000000000001002048110000000063 +:1043E0000004A2C2006044110000067C0000001A14 +:1043F00000212230000000000000000600222630CC +:104400000000000000042004006044110000067C4D +:104410000000A2C7002044110000000000000000BE +:10442000003048E9000000000000000000E000004B +:10443000000005B10000A2D40020441100000000DB +:104440000000000000404808000000000000A2D466 +:1044500000204411000000000000000100504A2824 +:104460000000000085000000002044110000000052 +:104470000000000000204801000000000000304A59 +:10448000002044110000000001000000002048113D +:10449000000000000000000000400000000005B720 +:1044A000A4000000C0204411000000000000000033 +:1044B000C04048000000000000000000C060000094 +:1044C000000005BC00000000C04004000000000126 +:1044D0000000002C002036210000000081000000B8 +:1044E00000204411000000000000000600204811D8 +:1044F0000000000000000000002F0230000000005B +:10450000000000000CC00000000005C30000000017 +:10451000002004110000000000000030004036219F +:10452000000005D6000000300020062D000000002D +:1045300000007E00002806210000000000000000AE +:10454000002F022100000000000000000CE000002D +:10455000000005D68100000000204411000000008A +:104560000000000100204811000000000004A0929B +:10457000006044110000067C00000031002036304D +:10458000000000000004A093006044110000067CBD +:104590000000003200203630000000000004A2B607 +:1045A000006044110000067C00000033002036301B +:1045B000000000000004A2BA006044110000067C64 +:1045C0000000003400203630000000000004A2BECD +:1045D000006044110000067C0000003500203630E9 +:1045E000000000000004A2C2006044110000067C2C +:1045F00000000036002036300000000000042004D7 +:10460000006044110000067C0001A2A400204411B7 +:10461000000000000000003F0020481100000000E2 +:104620000000003F00204811000000000000003F93 +:1046300000204811000000000000003F0020481149 +:1046400000000000000000050020481100000000EC +:104650000000A1F400204411000000000000000050 +:1046600000204811000000008800000000204411D4 +:1046700000000000000000010020481100000000C0 +:10468000810000000020441100000000000000062E +:10469000002048110000000000000001002F02303F +:1046A00000000000000000000CE000000000061FF9 +:1046B000000000300020062D000000000000000077 +:1046C000002F022100000000000000000CE00000AC +:1046D0000000061F810000000020441100000000BF +:1046E00000000001002048110000000000007E00D2 +:1046F000002806210000000000000000002F022119 +:1047000000000000000000000CE00000000005F8C0 +:104710000000A092002044110000000000000031C1 +:1047200000204A2D000000000000A093002044114A +:10473000000000000000003200204A2D00000000B0 +:104740000000A2B600204411000000000000003369 +:1047500000204A2D000000000000A2BA00204411F1 +:10476000000000000000003400204A2D000000007E +:104770000000A2BE0020441100000000000000352F +:1047800000204A2D000000000000A2C200204411B9 +:10479000000000000000003600204A2D000000004C +:1047A000000000300020062D00000000000001FF86 +:1047B000002806210000000000000000002F022158 +:1047C00000000000000000000CE000000000061ED9 +:1047D0000000000000210221000000000000000095 +:1047E00014C00000000006010004A0030060441192 +:1047F0000000067C0000A00300204411000000001F +:10480000000000000020481000000000000000012F +:1048100000210621000000000000000014C000007C +:10482000000006060004A010006044110000067C91 +:104830000000A01000204411000000000000000053 +:1048400000204810000000000000000100210621A7 +:104850000000000000000000002F02210000000006 +:10486000000000000CE000000000061E0004A01183 +:10487000006044110000067C0000A01100204411DB +:1048800000000000000000000020481000000000B0 +:104890000004A012006044110000067C0000A01279 +:1048A000002044110000000000000000002048101B +:1048B000000000000004A013006044110000067C0A +:1048C0000000A013002044110000000000000000C0 +:1048D00000204810000000000004A01400604411F3 +:1048E0000000067C0000A01400204411000000001D +:1048F0000000000000204810000000000004A01587 +:10490000006044110000067C0000A0150020441146 +:10491000000000000000000000204810000000001F +:104920000004A016006044110000067C0000A016E0 +:10493000002044110000000000000000002048108A +:10494000000000000004A017006044110000067C75 +:104950000000A0170020441100000000000000002B +:1049600000204810000000000004200400604411F2 +:104970000000067C0000002C0080062D00000000D6 +:10498000FF000000002044110000000000000000B3 +:104990000020481100000000000000010020481124 +:1049A000000000000000000200804811000000002C +:1049B000000000000EE000000000063000000030A3 +:1049C0000020062D00000000000000020028062143 +:1049D0000000000000000000002F02210000000085 +:1049E000000000000CE000000000062E8100000026 +:1049F00000204411000000000000000100204811C8 +:104A00000000000000042004006044110000067C47 +:104A10000000100000200811000000000000002B22 +:104A200000203622000000000000000000600000AE +:104A3000000006340000000000600000000005BC1B +:104A40009800000000204411000000000000000059 +:104A5000008048110000000000000000C06000005D +:104A60000000063400000000C04004000000000107 +:104A70000000A2A400204411000000000000002259 +:104A800000204811000000008900000000204411AF +:104A90000000000000000001004048110000062056 +:104AA00097000000002044110000000000000000FA +:104AB00000204811000000008A000000002044117E +:104AC0000000000000000000004048110000062027 +:104AD00000000000006000000000064D0001A2A4DC +:104AE000C0204411000000000000001600604811C2 +:104AF0000000036A000020100020441100000000A4 +:104B000000010000002048110000000081000000AA +:104B100000204411000000000000000100204811A6 +:104B2000000000000000217C002044110000000073 +:104B3000098000000020481100000000FFFFFFFF77 +:104B40000020481100000000000000000020481173 +:104B5000000000000000000017000000000000003E +:104B60000004217F006044110000067C0000001F4B +:104B700000210230000000000000000014C000000E +:104B8000000000000000000400404C110000064737 +:104B900000000000004000000000000000000017BE +:104BA00000201E2D000000000000000400291E2728 +:104BB0000000000000000017008036270000000001 +:104BC0000000001700201E2D00000000FFFFFFFB6B +:104BD00000281E2700000000000000170080362774 +:104BE000000000000000001700201E2D0000000043 +:104BF0000000000800291E27000000000000001728 +:104C000000803627000000000000001700201E2D45 +:104C100000000000FFFFFFF700281E270000000033 +:104C20000000001700803627000000000001A2A449 +:104C30000020441100000000000000160060481130 +:104C40000000036A00002010002044110000000052 +:104C50000001000000204811000000000000217C3D +:104C600000204411000000000180000000204811D5 +:104C700000000000FFFFFFFF0020481100000000BF +:104C800000000000002048110000000000000000AB +:104C90001700000000000000810000000020441107 +:104CA000000000000000000100204811000000008A +:104CB0000004217F006044110000067C0000001FFA +:104CC00000210230000000000000000014C00000BD +:104CD0000000067B0000001000404C11000006613F +:104CE00000000000C02004000000000000000000E0 +:104CF00038C00000000000000000001D00200A2D48 +:104D0000000000000000001E00200E2D000000002A +:104D10000000001F0020122D0000000000000020F5 +:104D20000020162D00000000000021690020441121 +:104D30000000000000000000002048040000000007 +:104D400000000000002048050000000000000000F6 +:104D50000020480100000000CAFEBABE0020481131 +:104D600000000000000000040030122400000000D9 +:104D700000000000002F00640000000000000000A0 +:104D80000CC000000000067A0000000300281A2270 +:104D900000000000000000080022122200000000B5 +:104DA000FFFFF000002812240000000000000000B7 +:104DB000002910C4000000000000001F004036243D +:104DC0000000000000000000008000000000000063 +:104DD000000000001AC000000000067C9F000000D8 +:104DE0000020441100000000CAFEBABE0020481195 +:104DF00000000000000000001AE000000000067F34 +:104E00000000000000800000000000000000000022 +:104E10001AC00000000006819E000000002044111E +:104E200000000000CAFEBABE0020481100000000C9 +:104E3000000000001AE000000000068400000000EE +:104E40000080000000000000000000000060000082 +:104E50000000000B000010000060041100000315AA +:104E6000000000000020041100000000000000000D +:104E700000600811000001B20000225C0020441113 +:104E800000000000000000030020481100000000A6 +:104E90000000225600204411000000000000001B0A +:104EA00000204811000000000000A1FC0020441177 +:104EB0000000000000000001002048110000000078 +:104EC0000001A1FDC02044110000000000000021ED +:104ED00000201E2D000000000000001000221E27F0 +:104EE00000000000000000240020222D000000002F +:104EF0000000FFFF00282228000000000000000042 +:104F000000294907000000000000000000204811AF +:104F100000000000000000220020222D0000000000 +:104F20000000FFFF00282228000000000000000011 +:104F3000002949070000000000000000002048117F +:104F4000000000000000002300201E2D00000000D3 +:104F50000000001000221E270000000000000000DA +:104F6000002949070000000000000000004048112F +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000000000000000000000B1 +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B000014204F505B302500000000001C301687B +:1052C000043505B300000000022502090250015117 +:1052D000000000000223024502A00241000000007D +:1052E00003CD05B305B305B300000000063C063D41 +:1052F000031F05B30000000005B305B803200340F9 +:1053000000000000032A0282034203340000000070 +:1053100005B305B305B305B30000000005B30544AC +:1053200005B305B30000000003B205B304AE0344A7 +:1053300000000000048D0443043305B300000000A6 +:1053400004C305B3043704D000000000044304FA8A +:10535000035103710000000005B305B305B305B3A5 +:105360000000000005B305B305B305B3000000005D +:1053700005B305B3063205BA0000000005B305B356 +:10538000000705B30000000005B305B305B305B37E +:105390000000000005B305B305B305B3000000002D +:1053A00003EE03E303FE03FC00000000040404001A +:1053B00004020406000000000412040E041A04167D +:1053C000000000000422041E042A0426000000003D +:1053D00005B305B3042E05B30000000005B305B303 +:1053E00005B305B30000000005B305B305B305B36D +:1053F00000000000000206680686000600000000AB +:00000001FF diff --git a/firmware/radeon/RV670_pfp.bin.ihex b/firmware/radeon/RV670_pfp.bin.ihex new file mode 100644 index 0000000..f55292c --- /dev/null +++ b/firmware/radeon/RV670_pfp.bin.ihex @@ -0,0 +1,145 @@ +:1000000000CA040000A00000007E828B007C038BED +:10001000008001B8007C038B00D4401E00EE001E5F +:1000200000CA040000A00000007E828B00C41838C3 +:1000300000CA240000CA2800009581A800C41C3A08 +:1000400000C3C00000CA080000CA0C00007C744B4A +:1000500000C200050099C00000C41C3A007C744C2A +:1000600000C0FFF000042C0400309002007D250049 +:1000700000351402007D350B00255403007CD5802B +:1000800000259C030095C00400D5001B007EDDC147 +:10009000007D9D8000D6801B00D5801B00D4401EB3 +:1000A00000D5401E00D6401E00D6801E00D4801E03 +:1000B00000D4C01E009783D300D5C01E00CA08001C +:1000C0000080001A00CA0C0000E4011E00D4001ECB +:1000D0000080000C00C4183800E4013E00D4001E6B +:1000E0000080000C00C4183800D4401E00EE001E32 +:1000F00000CA040000A00000007E828B00E4011E04 +:1001000000D4001E00D4401E00EE001E00CA0400F1 +:1001100000A00000007E828B00E4013E00D4001E9F +:1001200000D4401E00EE001E00CA040000A0000023 +:10013000007E828B00CA180000D4401E00D5801EAD +:100140000080005300D4007500D4401E00CA08008F +:1001500000CA0C0000CA100000D4801900D4C018D6 +:1001600000D5001700D4801E00D4C01E00D5001E8C +:1001700000E2001E00CA040000A00000007E828B86 +:1001800000CA080000D4806000D4401E0080000037 +:1001900000D4801E00CA080000D4806100D4401E34 +:1001A0000080000000D4801E00CA080000CA0C00B5 +:1001B00000D4401E00D4801600D4C01600D4801E87 +:1001C000008001B800D4C01E00C6084300CA0C005D +:1001D00000CA10000094800400CA140000E420F358 +:1001E00000D4201300D5606500D4E01C00D5201C8D +:1001F00000D5601C008000000006200100C60843F6 +:1002000000CA0C0000CA1000009483F700CA140052 +:1002100000E420F30080007900D4201300C60843D6 +:1002200000CA0C0000CA1000009883EF00CA140036 +:1002300000D400640080008D0000000000C414326F +:1002400000C6184300C4082F0095400500C40C30B8 +:1002500000D4401E0080000000EE001E009583F5D3 +:1002600000C4103100D4403300D5206500D4A01C58 +:1002700000D4E01C00D5201C00E4015E00D4001E68 +:10028000008000000006200100CA1800000A2001BA +:1002900000D6007600C408360098800700C61045D6 +:1002A0000095011000D4001F00D46062008000009F +:1002B00000D4206200CC383500CC1433008401BB5C +:1002C00000D4007200D5401E0080000000EE001E29 +:1002D00000E2001A008401BB00E2001A00CC104BBF +:1002E00000CC0447002C9401007D098B0098400548 +:1002F000007D15CB00D4001A008001B800D4006D39 +:100300000034440100CC0C480098403A00CC2C4A00 +:100310000095800400CC0449008001B800D4001A84 +:1003200000D4C01A00282801008400F000CC10037B +:100330000098801B0004380C008400F000CC1003EF +:100340000098801700043808008400F000CC1003E7 +:100350000098801300043804008400F000CC1003DF +:100360000098801400CC104C009A800900CC144DE9 +:10037000009840DC00D4006D00CC184800D5001A6D +:1003800000D5401A008000C900D5801A0096C0D55B +:1003900000D4006D008001B800D4006E009AC00344 +:1003A00000D4006D00D4006E0080000000EC007FDF +:1003B000009AC0CC00D4006D008001B800D4006E5B +:1003C00000CC140300CC180300CC1C03007D910367 +:1003D000007DD583007D190C0035CC1F0035701FC2 +:1003E000007CF0CB007CD08B00880000007E8E8BE0 +:1003F0000095C00400D4006E008001B800D4001A3B +:1004000000D4C01A00CC080300CC0C0300CC1003AD +:1004100000CC140300CC180300CC1C0300CC240334 +:1004200000CC28030035C41F0036B01F007C704B81 +:100430000034F01F007C704B0035701F007C704B47 +:10044000007D8881007DCCC1007E5101007E9541F8 +:10045000007C9082007CD4C2007C848B009AC00314 +:10046000007C8C8B002C88010098809E00D4006D4D +:100470000098409C00D4006E00CC084C00CC0C4D81 +:1004800000CC104800D4801A00D4C01A00800101AA +:1004900000D5001A00CC083200D40032009482D972 +:1004A00000CA0C0000D4401E0080000000D4001ED2 +:1004B00000E4011E00D4001E00CA080000CA0C009F +:1004C00000CA100000D4401E00CA140000D4801ED0 +:1004D00000D4C01E00D5001E00D5401E00D54034FB +:1004E0000080000000EE001E0028040400E2001A54 +:1004F00000E2001A00D4401A00CA380000CC0803F9 +:1005000000CC0C0300CC0C0300CC0C03009882BD83 +:1005100000000000008401BB00D7A06F0080000035 +:1005200000EE001F00CA040000C2FF0000CC083427 +:1005300000C13FFF007C74CB007CC90B007D010F24 +:10054000009902B0007C738B008401BB00D7A06FC0 +:100550000080000000EE001F00CA080000281900FB +:10056000007D898B009580140028140400CA0C00BB +:1005700000CA100000CA1C0000CA240000E2001FCC +:1005800000D4C01A00D5001A00D5401A00CC1803B8 +:1005900000CC2C0300CC2C0300CC2C03007DA58BBD +:1005A000007D9C4700984297000000000080016198 +:1005B00000D4C01A00D4401E00D4801E0080000069 +:1005C00000EE001E00E4011E00D4001E00D4401EF8 +:1005D00000EE001E00CA040000A00000007E828B16 +:1005E00000E4013E00D4001E00D4401E00EE001EB8 +:1005F00000CA040000A00000007E828B00CA080030 +:1006000000248C06000CCC060098C00600CC104ECE +:100610000099000400D4007300E4011E00D4001E01 +:1006200000D4401E00D4801E0080000000EE001E9A +:1006300000CA080000CA0C000034D01800251001C0 +:100640000095002100C17FFF00CA100000CA1400FD +:1006500000CA180000D4801D00D4C01D007DB18BDD +:1006600000C1420200C2C00100D5801D0034DC0E72 +:10067000007D5D4C007F734C00D7401E00D5001EEE +:1006800000D5401E00C1420000C2C00000099C010C +:100690000031DC10007F5F4C007F734C00042802A7 +:1006A000007D838000D5A86F00D5806600D7401EEE +:1006B00000EC005E00C8240200C82402008001B8DB +:1006C00000D6007600D4401E00D4801E00D4C01E88 +:1006D0000080000000EE001E0080000000EE001F01 +:1006E00000D4001F0080000000D4001F00D4001FB1 +:1006F0000088000000D4001F00000000000000007F +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000010171000201780003008F0004007FE5 +:10081000000500030006003F000700320008012C1D +:1008200000090046000A0036001001B6001700A2B9 +:100830000022013A00230149002000B400240125D0 +:100840000027004D0028006A002A0060002B00529B +:10085000002F0065003200870034017F003C015604 +:10086000003F00720041018C0044012E00550173CD +:100870000056017A0060000B00610034006200380D +:1008800000630038006400380065003800660038F6 +:10089000006700380068003A00690041006A0048BB +:1008A000006B0048006C0048006D0048006E004876 +:1008B000006F00480000000600000006000000066F +:1008C0000000000600000006000000060000000610 +:1008D0000000000600000006000000060000000600 +:1008E00000000006000000060000000600000006F0 +:1008F00000000006000000060000000600000006E0 +:00000001FF diff --git a/firmware/radeon/RV710_me.bin.ihex b/firmware/radeon/RV710_me.bin.ihex new file mode 100644 index 0000000..5cdfe30 --- /dev/null +++ b/firmware/radeon/RV710_me.bin.ihex @@ -0,0 +1,341 @@ +:10000000CC0003EA04080003CC8000437C4080005D +:10001000A0000000CC80006280000003D040007F80 +:1000200080000003CC4000417C40C000C0160004AA +:1000300030D03FFF7D15000CCC11000028D8001EE9 +:100040003198000128DC001FC820000495C000067C +:100050007C424000CC0000627E56800CCC2900001F +:10006000C82400047E26000B958000067C42C00058 +:10007000CC0000627ED7000CCC310000C82C0004FC +:100080007E2E000CCC00006231103FFF8000000388 +:10009000CE1100007C40C00080000003CC40004036 +:1000A00080000003CC4122577C418000CC400045B9 +:1000B000CC400048CC41225CCC41A1FC7C4080007B +:1000C000A0000000CC800062CC400045CC4000483D +:1000D0007C40C000CC41225CCC41A1FC7C40800033 +:1000E000A0000000CC800062CC000045CC0000489D +:1000F000CC41225CCC41A1FC7C408000A0000000EF +:10010000CC800062040CA1FDC0120001CC000045AF +:10011000CC0000487CD0C00CCC41225CCC41A1FC7E +:10012000D04D00007C408000A0000000CC80006228 +:1001300080000003CC41225D7C4080007C40C000F8 +:10014000C02A00027C4100007D29000C309400018F +:1001500030980006309C030029DC00087C42000037 +:100160007C4240009540000FC02E000405F022584C +:100170007F2F000CCC310000C8280004CCC12169BD +:10018000CD01216ACE81216B0DB40002CC01216C1E +:100190009740000E0DB400008000007DC834000AB6 +:1001A0000DB40002974000090DB40000C02E0004F9 +:1001B00005F022587F2F000CCC310000C828000425 +:1001C0008000007DC834000A974000047E02800051 +:1001D0008000007DC834000A0DB400049740FF8CF5 +:1001E00000000000CE01216DCE41216EC828000321 +:1001F000C834000A9B400004043C00058400026DE2 +:10020000CC0000620DF400009740000BC82C03E600 +:10021000CE81A2B7C03000067EF34028C030002057 +:100220007F6B80207FB3C029CF81A2C480000003F0 +:10023000CFC1A2D10DF400019740000BC82C03E7F9 +:10024000CE81A2BBC03000067EF34028C030002023 +:100250007F6B80207FB3C029CF81A2C580000003BF +:10026000CFC1A2D20DF400029740000BC82C03E8C6 +:10027000CE81A2BFC03000067EF34028C0300020EF +:100280007F6B80207FB3C029CF81A2C6800000038E +:10029000CFC1A2D3C82C03E9CE81A2C3C0300006CF +:1002A0007EF34028C03000207F6B80207FB3C029C0 +:1002B000CF81A2C780000003CFC1A2D48000000379 +:1002C000CC4000427C40C0007C4100002914001D4D +:1002D000315400019940000C31181000C81C001165 +:1002E00095C00000C81C0011CCC12100CD01210126 +:1002F000CCC12102CD012103041800048000037E3B +:10030000CD81A2A4C02A00049580000836A821A3AC +:10031000CC290000C8280004C81C00110DE40040CE +:100320009640FFFFC81C0011CCC12170CD01217186 +:10033000C820001296000000C82000128000037E32 +:10034000CC0000647C40C0007C410000CC00004533 +:10035000CC00004840D40003CD41225CCD01A1FC7B +:10036000C01A0001041CA1FD7DD9C00C7C42000014 +:1003700008CC00010624000106280002CE1D000062 +:10038000CE5D000098C0FFFACE9D00007C4080004A +:10039000A0000000CC8000627C40C00030D0000192 +:1003A00028CC00017C414000950000067C41800083 +:1003B000CD41216DCD81216E800000F4C81C000369 +:1003C000C02200047E16000CCC210000C81C0004D2 +:1003D0007C42400098C000047C4280008000000302 +:1003E000CDE50000CE412169CE81216ACDC1216BCE +:1003F00080000003CC01216C7C40C0007C410000E7 +:100400007C4140007C4180007C41C00028A4000861 +:10041000326400FF0E68003C9680000A7C020000F7 +:100420007C4200001E300003CC00006A9B000003E9 +:100430004220000504200040800001117C024000A1 +:100440007E0240009A4000000A64000130EC001077 +:100450009AC0000ACC000062C02A0004C82C002107 +:100460007E92800CCC000041CC290000CEC000213F +:1004700080000121C8300004CD01216DCD41216EE5 +:10048000C83000037F1F000B30F4000727780001FD +:100490009740002A07B801269F8000000000000056 +:1004A000800001367F1B80048000013A7F1B80059D +:1004B0008000013E7F1B8002800001427F1B800381 +:1004C000800001467F1B80078000014A7F1B800659 +:1004D0008000014F28A400089B80001928A4000870 +:1004E0008000015F326400FF9B80001528A4000893 +:1004F0008000015F326400FF9B80001128A4000887 +:100500008000015F326400FF9B80000D28A400087A +:100510008000015F326400FF9B80000928A400086E +:100520008000015F326400FF9B80000528A4000862 +:100530008000015F326400FF28A40008326400FFDD +:100540000E68003C9A80FEB228EC00087C43400014 +:100550007C4380007C43C00096C00007CC00006252 +:10056000CF412169CF81216ACFC1216B8000000377 +:10057000CC01216C80000003CFF50000CC00006BA3 +:10058000840003810E68003C9A800004C82800158E +:1005900080000003D040007F9680FFAB7E024000C9 +:1005A0008400023BC00E0002CC00004180000239F2 +:1005B000CCC1304A7C40C0007C410000C01E00011C +:1005C00029240012C022000296400005C026000423 +:1005D000C027FFFB7D25000BC02600007DD2800BCD +:1005E0007E12C00B7D25000C7C4140007C418000C8 +:1005F000CCC121699A80000ACD01216ACD41216BCD +:1006000096C0FE83CD81216CC83000189700000091 +:10061000C830001880000003CC000018840003815B +:10062000CC00007FC8140013C8180014CD41216B02 +:1006300096C0FE77CD81216C80000183C830001800 +:10064000C80C000898C00000C80C00087C410000DD +:1006500095000002000000007C414000C820000915 +:10066000CC400043CE01A1F4CC400044C00E800039 +:100670007C4240007C4280002AAC001F96C0FE6491 +:10068000C035F000CE4003E232780003267C00083B +:100690007FF7C00B7FFBC00C2A780018CFC003E3A4 +:1006A000CF8003E426B000027F3F0000CF0003E5C7 +:1006B0008000031F7C80C0007C40C00028D0000860 +:1006C0003110000F9500000F2528000106A801B485 +:1006D0009E80000000000000800001D5C0120800CC +:1006E000800001E3C814000F800001EAC814001064 +:1006F000800001F1CCC1A2A4800001FAC81400114D +:1007000030D0003F0D2800159A8000120D28001EE1 +:100710009A80001E0D2800209A8000230D24000FCF +:100720000D2800107E6A800C9A8000260D2000049F +:100730000D2400140D2800287E62400C7EA6800C3B +:100740009A80002AC814001180000003CCC1A2A422 +:10075000C01208007C4140007D0CC00CC012000893 +:1007600029580003295C000C7C4200007DD1C00B9D +:10077000262000147E1E400C7E4E800CCE81A2A44A +:1007800080000003CD81A1FEC814000F0410210ECB +:1007900095400000C814000FD051000080000003F5 +:1007A000CCC1A2A4C8140010041021089540000078 +:1007B000C8140010D051000080000003CCC1A2A4D6 +:1007C000CCC1A2A404100001CD0000198400038153 +:1007D000CC00007FC810001999000000C810001953 +:1007E000800000047C40800004102100954000003F +:1007F000C8140011D05100008000037ECCC1A2A417 +:100800007C40C000CC40000D94C0FE01CC40000EE6 +:100810007C4100009500000508CC0001C8140005CB +:10082000994000140000000098C0FFFB7C410000CC +:10083000800000047D008000C81400057C40C000DA +:100840009940000CC818000C7C4100009580FDF018 +:10085000C820000EC81C000D662000207E1E002C43 +:10086000252400027E62402080000003CCE60000C8 +:100870007C410000CC00006CCC00006DC818001F4B +:10088000C81C001E659800207DD9C02C7CD4C00CEB +:10089000CCDE000045DC0004C82800179680000F5D +:1008A000C00E0001286800082AAC001632A800FF1C +:1008B0000EB000497F2F000B9700000600000000DB +:1008C000C81400057C40C000800002237C41000069 +:1008D00080000226D040007F8400023BCC00004113 +:1008E000CCC1304A94000000C83C001A043C00050A +:1008F000CFC1A2A4C0361F90C0387FFF7C03C010B8 +:100900007F7B400CCF41217CCFC1217DCC01217E5A +:10091000C03A00040434217F7F7B400CCC350000BA +:10092000C83C00042BFC001F0438002097C00005C1 +:10093000CC0000629B8000000BB8000180000247E1 +:10094000CC000071CC01A1F404380016C0360002BE +:10095000CF81A2A488000000CF4120107C40C000BD +:1009600028D0001C9500000504D40001CD4000658E +:1009700080000003CD40006809540002800000039D +:10098000CD4000668400026CC81803EA7C40C000B9 +:100990009980FD9FC814001608D000019940002BD3 +:1009A000CD0000687C408000A0000000CC80006288 +:1009B000043C0005CFC1A2A4CC01A1F484000381B2 +:1009C000CC00004688000000CC00007F8400027E3E +:1009D000C81803EA7C40C0009980FD8DC814001639 +:1009E00008D0000199400019CD0000687C408000CB +:1009F000A0000000CC800062043C0022CFC1A2A471 +:100A000084000381CC00004788000000CC00007FF8 +:100A1000C81000169900000DCC400067800000044B +:100A20007C408000C81803EA9980FD797C40C000B2 +:100A300094C00003C810001699000004CCC00068E0 +:100A4000800000047C4080008400023BC0148000D1 +:100A5000CC000041CD41304AC01480009900000014 +:100A6000C8100016800000047C408000C012000105 +:100A70007C51400C80000003D05500007C40C00039 +:100A80007C4100007C4140007C418000291C001F0B +:100A9000CCC0004ACD00004B95C00003C01C8000B4 +:100AA000CDC12010DD830000055C2000CC00006279 +:100AB00080000003D81F41007C40C0007C41000042 +:100AC0007C4140007C418000CCC0004CCD00004DFA +:100AD000DD830000055CA00080000003D81F4100FA +:100AE0007C40C0007C4100007C4140007C41800093 +:100AF000CCC0004ECD00004FDD830000055CC0007F +:100B000080000003D81F41007C40C0007C410000F1 +:100B10007C4140007C418000CCC00050CD000051A1 +:100B2000DD830000055CF8E080000003D81F410071 +:100B30007C40C0007C4100007C4140007C41800042 +:100B4000CCC00052CD000053DD830000055CF8806E +:100B500080000003D81F41007C40C0007C410000A1 +:100B60007C4140007C418000CCC00054CD00005549 +:100B7000DD830000055CE00080000003D81F410019 +:100B80007C40C0007C4100007C4140007C418000F2 +:100B9000CCC00056CD000057DD830000055CF0009E +:100BA00080000003D81F41007C40C0007C41000051 +:100BB0007C4140007C418000CCC00058CD000059F1 +:100BC000DD830000055CF3FC80000003D81F4100BA +:100BD000D04320007C408000A0000000CC80006258 +:100BE000D043A0007C408000A0000000CC800062C8 +:100BF000D043C0007C408000A0000000CC80006298 +:100C0000D043F8E07C408000A0000000CC8000626F +:100C1000D043F8807C408000A0000000CC800062BF +:100C2000D043E0007C408000A0000000CC80006247 +:100C3000D043F0007C408000A0000000CC80006227 +:100C4000D043F3FC7C408000A0000000CC80006218 +:100C5000C81403E0CC430000CC430000CC430000A8 +:100C60007D45C000CDC30000D04300007C40800023 +:100C7000A0000000CC8000627C40C000C81003E2ED +:100C8000C81403E5C81803E3C81C03E4CD81216937 +:100C9000CDC1216ACCC1216BCC01216C04200004A0 +:100CA0007DA180007D9640029640FCD9CD8003E373 +:100CB00031280003C02DF000251800087DAD800B01 +:100CC0007DA9800C80000003CD8003E3308CFFFF02 +:100CD000D04D00007C408000A0000000CC8000626D +:100CE000C8140020155800029580FFFFC81400208A +:100CF000CC00006ECC4121807C40C000CCC1218D55 +:100D0000CC41218128D0001F34588000CD81218C16 +:100D10009500FCBFCC412182C81400209940FFFF00 +:100D2000C8140020800000047C4080007C40C0008B +:100D300028D0001831100001C01600809500000373 +:100D4000C02A00047CD4C00CCCC1217CCC41217DC4 +:100D5000CC41217E7C4180001DB0000336A0217F64 +:100D60009B000003419C0005041C004099C000004A +:100D700009DC0001CC210000C82400042A6C001FFB +:100D8000419C00059AC0FFFACC80006280000004FC +:100D90007C4080007C40C00004D403E68000000357 +:100DA000CC5400008000037ECC4003EAC01C8000CD +:100DB000044CA000CDC120107C410000C8140009E3 +:100DC00004180000041C0008CD80007109DC00013B +:100DD00005980001CD0D000099C0FFFCCC80006299 +:100DE0008000037ECD400071C00E0100CC000041A8 +:100DF000CCC1304AC83C007FCC00007F800000039B +:100E0000CC00007FCC00007F88000000CC00007F79 +:100E100000000000000000000000000000000000D2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:101400000001033300100006001700080021000A45 +:101410000027002A002800250029002B002A002888 +:10142000002B002B002D003A002E0041002F004C15 +:101430000034004E00360032003900B1003A00D1CD +:10144000003B00E6003C00FE003D016D003F00AFA8 +:10145000004103380043034B00440190004500FE67 +:10146000004601AE004701AE004802000049020EEE +:10147000004A0257004B028400520261005302737B +:10148000005402890057029B0060029F006102AE77 +:10149000006202B8006302C2006402CC006502D69A +:1014A000006602E0006702EA006802F4006902F8E0 +:1014B000006A02FC006B0300006C0304006D03086B +:1014C000006E030C006F03100070031400720365BC +:1014D0000074036B00790369007C031E000F037A1C +:1014E000000F037A000F037A000F037A000F037ACC +:1014F000000F037A000F037A000F037A000F037ABC +:10150000000F037A000F037A000F037A000F037AAB +:10151000000F037A000F037A000F037A000F037A9B +:10152000000F037A000F037A000F037A000F037A8B +:10153000000F037A000F037A000F037A000F037A7B +:00000001FF diff --git a/firmware/radeon/RV710_pfp.bin.ihex b/firmware/radeon/RV710_pfp.bin.ihex new file mode 100644 index 0000000..3d811ff --- /dev/null +++ b/firmware/radeon/RV710_pfp.bin.ihex @@ -0,0 +1,213 @@ +:100000007C408000A00000007E82800B8000000009 +:10001000DC030000CC800040D04000407C408000E9 +:10002000A00000007E82800BC818000E31980001ED +:100030007C4240009580023A7C428000C81C001C33 +:10004000C037C0007C40C0007C4100007CB4800B05 +:10005000C036000399C00000C81C001C7CB4800C92 +:1000600024D400027D654000CD400043CE80004393 +:10007000CD000043CC800040CE400040CE80004008 +:10008000CCC00040DC3A00009780FFDECD0000408D +:100090007C40C000800000187C410000D400034078 +:1000A000D4000FC0D4000FA2C818000E8000000CAE +:1000B00031980002D40003C0D4000FC0D4000FA2B6 +:1000C000C818000E288C000830CC000F3410000136 +:1000D0007D0D00088000000C7D91800BCC800040DD +:1000E000D04000407C408000A00000007E82800B59 +:1000F000D4000340D4000FC0D4000FA2CC80004035 +:10010000D04000407C408000A00000007E82800B38 +:10011000D40003C0D4000FC0D4000FA2CC80004094 +:10012000D04000407C408000A00000007E82800B18 +:10013000CC4003F980000249CC4003F8C037FFFFF0 +:100140007C414000CF41A29EC82003F8C81C03F99F +:1001500066200020C81803FB7DE1C02C7D58C00834 +:100160007CDCC02069100020C0360003CC000054A5 +:100170007CB4800C80000069CC8000407C41800011 +:10018000CD81A29ECC80004080000067CD800040E1 +:10019000C019FFFFCC800040CD81A29E7C40C000F2 +:1001A0007C4100007C414000CCC1A1FACD01A1F905 +:1001B000CD41A29DCCC00040CD000040CD400040CC +:1001C000CC4000407C408000A00000007E82800B7C +:1001D000CC000054CC8000407C40C0007C4100003A +:1001E0007C414000CCC1A1FACD01A1F9CD41A29D35 +:1001F000CCC00040CD000040CD400040D040004089 +:100200007C408000A00000007E82800B7C40C0000B +:1002100030D00001CCC1A29F95000003041400015E +:1002200004140002CD4003FBCC800040800000009D +:10023000CCC000407C40C000CC800040CCC1A2A219 +:1002400080000000CCC000407C40C00028D4001FCB +:10025000CC800040954000037C410000CCC000579A +:100260002918001FCCC0004095800003CD0000403D +:10027000CD00005880000249CC00007FC820001744 +:10028000C83000229A0000060E280001C824001E73 +:100290000A640001D4001240CE400040C036C000C5 +:1002A0009680000737747900041C0001CF4000409D +:1002B000CDC00040CF0003FA7C030000CA0C001040 +:1002C0007C41000094C000047C414000D42002C462 +:1002D000CDE000449B00000B7C418000CC00004B33 +:1002E000CDA00049CD200041CD600041CDA000410E +:1002F00006200001CE00005680000249CC00007F9D +:10030000C8280020C82C0021CC0000637EEA4001F0 +:10031000657400207F53402C269C00027DF5C02090 +:1003200069F80020CE80004BCE600049CDE000414E +:10033000CFA00041CE600041271C00027DF5C02007 +:1003400069F800207DB24001CF00004BCE6000492B +:10035000CDE00041CFA00041800000BCCE60004154 +:10036000C8200017C83000229A0000060E2800019D +:10037000C824001E0A640001D4001240CE40004090 +:10038000CA0C00107C41000094C0000BC036C000B5 +:100390009680000737747900041C0001CF400040AC +:1003A000CDC00040CF0003FA7C030000800000B500 +:1003B0007C414000CC000048800000EE00000000BE +:1003C000C8200017C81C00230E24000299C0001585 +:1003D0007C4180000A200001CE000056D400044079 +:1003E000CC000040C036C000CA140013964000077D +:1003F00037747900CF400040CC000040C83003FA89 +:1004000080000103CF000022CC000022954001466D +:10041000CC00007FCCA0004680000000CC2000462D +:1004200080000249CC000064C8200017C810001FDB +:100430009600000509100001D4000440CD000040E2 +:10044000CD000022CC800040D0400040C80C0025E8 +:1004500094C0FEECC8100008CD000040D4000FC0CE +:1004600080000000D4000FA27C40C0007C4100004E +:10047000CCC003FDCD0003FCCCC00042CD00004247 +:100480002914001F29180010319800073B5C000157 +:100490007D76000B998000057D5E400BCC0000420C +:1004A00080000249CC00004D29980001292C000849 +:1004B0009980003D32EC0001960000042930000CC8 +:1004C00080000249CC00004204140010CD400042DC +:1004D00033300001342800018400015DC81400039A +:1004E0009B40001B0438000C8400015DC81400030D +:1004F0009B400017043800088400015DC814000305 +:100500009B400013043800048400015DC8140003FC +:100510009B400015C80C03FD9A800009C81003FC1D +:100520009B000101CC00004D04140010CCC000421F +:10053000CD00004280000135CD40004296C000FA57 +:10054000CC00004D80000249CC00004E9AC0000350 +:10055000CC00004DCC00004EDF8300008000000086 +:10056000D80301FF9AC000F0CC00004D8000024982 +:10057000CC00004EC8180003C81C0003C8200003AC +:100580007D5D40037DA1C0037D5D400C2A10001FEE +:10059000299C001F7D1D000B7D17400B880000006B +:1005A0007E92800B96400004CC00004E80000249F1 +:1005B000CC00004204380008CF800042C808000385 +:1005C000C80C0003C8100003C8140003C8180003B7 +:1005D000C81C0003C8240003C828000329FC001F0E +:1005E0002AB0001F7FF3C00B28F0001F7FF3C00B61 +:1005F0002970001F7FF3C00B7D8880017DCCC00176 +:100600007E5100017E9540017C9080027CD4C00226 +:100610007CBC800B9AC000037C8F400B38B4000177 +:100620009B4000C1CC00004D9BC000BFCC00004EE1 +:10063000C80C03FDC81003FCCCC000428000016E52 +:10064000CD000042D4000340D4000FC0D4000FA25C +:10065000CC800040CC400040CC400040CC4000402A +:100660007C40C000CCC00040CCC0000D8000000029 +:10067000D04000407C40C0007C4100006514002058 +:100680007D4D402C245800027D5980207C41C000C3 +:10069000CD80004269980020CD800042CDC000424C +:1006A000C023C00005E400027CA0800B266400107B +:1006B0007CA4800CCC800040CDC00040CCC0004069 +:1006C00095C0000ECD00004009DC0001C8280003E1 +:1006D00096800008CE800040C834001D974000007E +:1006E000C834001D26A800088400024CCC2B000052 +:1006F00099C0FFF709DC0001DC3A00009780000494 +:100700007C418000800001A225980002A00000002A +:100710007D808000C818001D7C40C00064D00008A7 +:1007200095800000C818001DCC130000CC8000404C +:10073000CCC0004080000000CC400040C810001F2A +:100740007C40C000CC8000407CD1400CCD400040BB +:100750000518000180000000CD8000227C40C00010 +:10076000645000208400024CCC0000617CD0C02C7E +:10077000C8200017C8D60000994000087C438000BC +:10078000DF830000CFA0004F8400024CCC00006249 +:1007900080000000D040007F80000249CC00006251 +:1007A0008400024CCC000061C82000177C40C000CF +:1007B000C036FF00C810000DC0303FFF7CF5400B75 +:1007C0007D51800B7D81800F998000087CF3800B28 +:1007D000DF830000CFA0004F8400024CCC000062F9 +:1007E00080000000D040007F80000249CC00006201 +:1007F0008400024C7C40C00028DC000895C0001931 +:1008000030DC00107C41000099C0000464540020DA +:1008100080000208C91D00007D15002CC91E0000C3 +:100820007C4200007C4240007C4180007DE5C00BA2 +:100830007DE280079A80000E41AC00059AC000005E +:100840000AEC000130DC001099C000040000000038 +:100850008000020BC91D00008000020BC91E0000B1 +:10086000CC800040CCC00040D0400040C80C0025E7 +:1008700094C0FDE4C8100008CD000040D4000FC0B3 +:1008800080000000D4000FA2D4000340D4000FC0A9 +:10089000D4000FA2CC800040D04000407C408000BB +:1008A000A00000007E82800BD40003C0D4000FC0E3 +:1008B000D4000FA2CC800040D04000407C4080009B +:1008C000A00000007E82800B7C40C00030D000067B +:1008D0000D10000699000007C81400159940000586 +:1008E000CC000052D4000340D4000FC0D4000FA2AB +:1008F000CC800040CCC0004080000000D0400040D0 +:100900007C40C000CC4D0000DC3A00009780FDBD6B +:1009100004CC000180000242CC4D000080000000A9 +:10092000D040007FCC00007F80000000CC00007F22 +:10093000CC00007F88000000CC00007F0000000099 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C0000000302220004022A0005009F00020003E4 +:100C10000006003C0007002700080191000900447D +:100C2000000A002D00100247001700F0002201D733 +:100C3000002301E80026004C0027005F0020011A75 +:100C4000002800920029004F002A0083002B006436 +:100C5000002F008D003200D80034023200360074BC +:100C60000039010A003C01FC003F009F00410005E3 +:100C7000004401940048019D004901C5004A01CF8C +:100C8000005502250056022D0060000A0061002A6E +:100C90000062003000630030006400300065003006 +:100CA0000066003000670030006800370069003FD0 +:100CB000006A0047006B0047006C0047006D00476A +:100CC000006E0047006F0047007000470073024746 +:100CD000007B024000000005000000050000000548 +:100CE00000000005000000050000000500000005F0 +:100CF00000000005000000050000000500000005E0 +:100D000000000005000000050000000500000005CF +:100D100000000005000000050000000500000005BF +:100D200000000005000000050000000500000005AF +:100D3000000000050000000500000005000000059F +:00000001FF diff --git a/firmware/radeon/RV730_me.bin.ihex b/firmware/radeon/RV730_me.bin.ihex new file mode 100644 index 0000000..390c18e --- /dev/null +++ b/firmware/radeon/RV730_me.bin.ihex @@ -0,0 +1,341 @@ +:10000000CC0003EA7C408000A0000000CC800062AD +:1000100080000001D040007F80000001CC40004102 +:100020007C40C000C016000430D03FFF7D15000C9E +:10003000CC11000028D8001E3198000128DC001FD8 +:10004000C820000495C000067C424000CC0000623D +:100050007E56800CCC290000C82400047E26000BAC +:10006000958000067C42C000CC0000627ED7000C68 +:10007000CC310000C82C00047E2E000CCC000062A5 +:1000800031103FFF80000001CE1100007C40C00015 +:1000900080000001CC40004080000001CC4122578C +:1000A0007C418000CC400045CC400048CC41225CE3 +:1000B000CC41A1FC7C408000A0000000CC8000620C +:1000C000CC400045CC4000487C40C000CC41225C84 +:1000D000CC41A1FC7C408000A0000000CC800062EC +:1000E000CC000045CC000048CC41225CCC41A1FCB6 +:1000F0007C408000A0000000CC800062040CA1FDC8 +:10010000C0120001CC000045CC0000487CD0C00CDF +:10011000CC41225CCC41A1FCD04D00007C40800051 +:10012000A0000000CC80006280000001CC41225D74 +:100130007C4080007C40C000C02A00027C4100005E +:100140007D29000C3094000130980006309C03009B +:1001500029DC00087C4200007C4240009540000FF2 +:10016000C02E000405F022587F2F000CCC31000077 +:10017000C8280004CCC12169CD01216ACE81216B40 +:100180000DB40002CC01216C9740000E0DB40000AC +:100190008000007BC834000A0DB4000297400009BB +:1001A0000DB40000C02E000405F022587F2F000C73 +:1001B000CC310000C82800048000007BC834000A4D +:1001C000974000047E0280008000007BC834000A53 +:1001D0000DB400049740FF8C00000000CE01216D9B +:1001E000CE41216EC8280003C834000A9B40000499 +:1001F000043C00058400026BCC0000620DF400009A +:100200009740000BC82C03E6CE81A2B7C030000691 +:100210007EF34028C03000207F6B80207FB3C02950 +:10022000CF81A2C480000001CFC1A2D10DF4000192 +:100230009740000BC82C03E7CE81A2BBC03000065C +:100240007EF34028C03000207F6B80207FB3C02920 +:10025000CF81A2C580000001CFC1A2D20DF400025F +:100260009740000BC82C03E8CE81A2BFC030000627 +:100270007EF34028C03000207F6B80207FB3C029F0 +:10028000CF81A2C680000001CFC1A2D3C82C03E950 +:10029000CE81A2C3C03000067EF34028C0300020CB +:1002A0007F6B80207FB3C029CF81A2C7800000016F +:1002B000CFC1A2D480000001CC4000427C40C000ED +:1002C0007C4100002914001D315400019940000CAC +:1002D00031181000C81C001195C00000C81C001186 +:1002E000CCC12100CD012101CCC12102CD012103CE +:1002F000041800048000037CCD81A2A4C02A00045D +:100300009580000836A821A3CC290000C828000445 +:10031000C81C00110DE400409640FFFFC81C0011EE +:10032000CCC12170CD012171C820001296000000BF +:10033000C82000128000037CCC0000647C40C00018 +:100340007C410000CC000045CC00004840D40003B4 +:10035000CD41225CCD01A1FCC01A0001041CA1FD0D +:100360007DD9C00C7C42000008CC000106240001AD +:1003700006280002CE1D0000CE5D000098C0FFFAE6 +:10038000CE9D00007C408000A0000000CC80006278 +:100390007C40C00030D0000128CC00017C414000EE +:1003A000950000067C418000CD41216DCD81216EFC +:1003B000800000F2C81C0003C02200047E16000C5E +:1003C000CC210000C81C00047C42400098C00004FE +:1003D0007C42800080000001CDE50000CE41216913 +:1003E000CE81216ACDC1216B80000001CC01216C3E +:1003F0007C40C0007C4100007C4140007C4180008A +:100400007C41C00028A40008326400FF0E68003C54 +:100410009680000A7C0200007C4200001E3000032F +:10042000CC00006A9B00000342200005042000402D +:100430008000010F7C0240007E0240009A400000D4 +:100440000A64000130EC00109AC0000ACC0000627F +:10045000C02A0004C82C00217E92800CCC000041F0 +:10046000CC290000CEC000218000011FC83000044C +:10047000CD01216DCD41216EC83000037F1F000BDF +:1004800030F40007277800019740002A07B80124BC +:100490009F80000000000000800001347F1B80046A +:1004A000800001387F1B80058000013C7F1B80029B +:1004B000800001407F1B8003800001447F1B800778 +:1004C000800001487F1B80068000014D28A40008A1 +:1004D0009B80001928A400088000015D326400FFA1 +:1004E0009B80001528A400088000015D326400FF95 +:1004F0009B80001128A400088000015D326400FF89 +:100500009B80000D28A400088000015D326400FF7C +:100510009B80000928A400088000015D326400FF70 +:100520009B80000528A400088000015D326400FF64 +:1005300028A40008326400FF0E68003C9A80FEB2D6 +:1005400028EC00087C4340007C4380007C43C000D2 +:1005500096C00007CC000062CF412169CF81216A9B +:10056000CFC1216B80000001CC01216C8000000113 +:10057000CFF50000CC00006B8400037F0E68003CC8 +:100580009A800004C828001580000001D040007F38 +:100590009680FFAB7E02400084000239C00E00024C +:1005A000CC00004180000237CCC1304A7C40C00002 +:1005B0007C410000C01E000129240012C02200025C +:1005C00096400005C0260004C027FFFB7D25000BD8 +:1005D000C02600007DD2800B7E12C00B7D25000C52 +:1005E0007C4140007C418000CCC121699A80000A96 +:1005F000CD01216ACD41216B96C0FE83CD81216C56 +:10060000C830001897000000C830001880000001B2 +:10061000CC0000188400037FCC00007FC8140013B6 +:10062000C8180014CD41216B96C0FE77CD81216C96 +:1006300080000181C8300018C80C000898C0000074 +:10064000C80C00087C41000095000002000000007A +:100650007C414000C8200009CC400043CE01A1F4F9 +:10066000CC400044C00E80007C4240007C428000B0 +:100670002AAC001F96C0FE64C035F000CE4003E2F5 +:1006800032780003267C00087FF7C00B7FFBC00C8C +:100690002A780018CFC003E3CF8003E426B000021D +:1006A0007F3F0000CF0003E58000031D7C80C00079 +:1006B0007C40C00028D000083110000F9500000FCA +:1006C0002528000106A801B29E800000000000005D +:1006D000800001D3C0120800800001E1C814000F9F +:1006E000800001E8C8140010800001EFCCC1A2A472 +:1006F000800001F8C814001130D0003F0D2800150B +:100700009A8000120D28001E9A80001E0D280020DD +:100710009A8000230D24000F0D2800107E6A800CA3 +:100720009A8000260D2000040D2400140D280028B6 +:100730007E62400C7EA6800C9A80002AC8140011AC +:1007400080000001CCC1A2A4C01208007C4140007E +:100750007D0CC00CC012000829580003295C000C55 +:100760007C4200007DD1C00B262000147E1E400C70 +:100770007E4E800CCE81A2A480000001CD81A1FE1E +:10078000C814000F0410210E95400000C814000F7B +:10079000D051000080000001CCC1A2A4C8140010F8 +:1007A0000410210895400000C8140010D05100002A +:1007B00080000001CCC1A2A4CCC1A2A404100001FD +:1007C000CD0000198400037FCC00007FC810001901 +:1007D00099000000C8100019800000027C408000D1 +:1007E0000410210095400000C8140011D0510000F1 +:1007F0008000037CCCC1A2A47C40C000CC40000D92 +:1008000094C0FE01CC40000E7C4100009500000524 +:1008100008CC0001C8140005994000140000000035 +:1008200098C0FFFB7C410000800000027D0080003A +:10083000C81400057C40C0009940000CC818000C8A +:100840007C4100009580FDF0C820000EC81C000D02 +:10085000662000207E1E002C252400027E6240209F +:1008600080000001CCE600007C410000CC00006C60 +:10087000CC00006DC818001FC81C001E6598002021 +:100880007DD9C02C7CD4C00CCCDE000045DC00043B +:10089000C82800179680000FC00E000128680008C5 +:1008A0002AAC001632A800FF0EB000497F2F000BC3 +:1008B0009700000600000000C81400057C40C0003E +:1008C000800002217C41000080000224D040007F93 +:1008D00084000239CC000041CCC1304A94000000B1 +:1008E000C83C001A043C0005CFC1A2A4C0361F902A +:1008F000C0387FFF7C03C0107F7B400CCF41217C40 +:10090000CFC1217DCC01217EC03A00040434217F77 +:100910007F7B400CCC350000C83C00042BFC001F42 +:100920000438002097C00005CC0000629B800000C6 +:100930000BB8000180000245CC000071CC01A1F48D +:1009400004380016C0360002CF81A2A4880000003F +:10095000CF4120107C40C00028D0001C950000052D +:1009600004D40001CD40006580000001CD40006846 +:100970000954000280000001CD4000668400026A34 +:10098000C81803EA7C40C0009980FD9FC814001677 +:1009900008D000019940002BCD0000687C40800009 +:1009A000A0000000CC800062043C0005CFC1A2A4DE +:1009B000CC01A1F48400037FCC0000468800000035 +:1009C000CC00007F8400027CC81803EA7C40C00091 +:1009D0009980FD8DC814001608D0000199400019B7 +:1009E000CD0000687C408000A0000000CC80006248 +:1009F000043C0022CFC1A2A48400037FCC000047A6 +:100A000088000000CC00007FC81000169900000D7F +:100A1000CC400067800000027C408000C81803EAD8 +:100A20009980FD797C40C00094C00003C810001676 +:100A300099000004CCC00068800000027C40800067 +:100A400084000239C0148000CC000041CD41304AFE +:100A5000C014800099000000C81000168000000239 +:100A60007C408000C01200017C51400C80000001DD +:100A7000D05500007C40C0007C4100007C4140001B +:100A80007C418000291C001FCCC0004ACD00004BD7 +:100A900095C00003C01C8000CDC12010DD83000084 +:100AA000055C2000CC00006280000001D81F4100DE +:100AB0007C40C0007C4100007C4140007C418000C3 +:100AC000CCC0004CCD00004DDD830000055CA000D3 +:100AD00080000001D81F41007C40C0007C41000024 +:100AE0007C4140007C418000CCC0004ECD00004FD6 +:100AF000DD830000055CC00080000001D81F4100BC +:100B00007C40C0007C4100007C4140007C41800072 +:100B1000CCC00050CD000051DD830000055CF8E042 +:100B200080000001D81F41007C40C0007C410000D3 +:100B30007C4140007C418000CCC00052CD0000537D +:100B4000DD830000055CF88080000001D81F4100B3 +:100B50007C40C0007C4100007C4140007C41800022 +:100B6000CCC00054CD000055DD830000055CE000E2 +:100B700080000001D81F41007C40C0007C41000083 +:100B80007C4140007C418000CCC00056CD00005725 +:100B9000DD830000055CF00080000001D81F4100EB +:100BA0007C40C0007C4100007C4140007C418000D2 +:100BB000CCC00058CD000059DD830000055CF3FC7B +:100BC00080000001D81F4100D04320007C408000FD +:100BD000A0000000CC800062D043A0007C408000D8 +:100BE000A0000000CC800062D043C0007C408000A8 +:100BF000A0000000CC800062D043F8E07C40800080 +:100C0000A0000000CC800062D043F8807C408000CF +:100C1000A0000000CC800062D043E0007C40800057 +:100C2000A0000000CC800062D043F0007C40800037 +:100C3000A0000000CC800062D043F3FC7C40800028 +:100C4000A0000000CC800062C81403E0CC43000088 +:100C5000CC430000CC4300007D45C000CDC3000064 +:100C6000D04300007C408000A0000000CC800062E7 +:100C70007C40C000C81003E2C81403E5C81803E3B1 +:100C8000C81C03E4CD812169CDC1216ACCC1216B8F +:100C9000CC01216C042000047DA180007D964002DF +:100CA0009640FCD9CD8003E331280003C02DF0002D +:100CB000251800087DAD800B7DA9800C8000000107 +:100CC000CD8003E3308CFFFFD04D00007C408000DE +:100CD000A0000000CC800062C8140020155800025B +:100CE0009580FFFFC8140020CC00006ECC4121800D +:100CF0007C40C000CCC1218DCC41218128D0001F77 +:100D000034588000CD81218C9500FCBFCC412182DC +:100D1000C81400209940FFFFC81400208000000282 +:100D20007C4080007C40C00028D0001831100001B9 +:100D3000C016008095000003C02A00047CD4C00CBB +:100D4000CCC1217CCC41217DCC41217E7C418000E5 +:100D50001DB0000336A0217F9B000003419C0005CD +:100D6000041C004099C0000009DC0001CC210000F7 +:100D7000C82400042A6C001F419C00059AC0FFFA99 +:100D8000CC800062800000027C4080007C40C0007B +:100D900004D403E680000001CC5400008000037CF2 +:100DA000CC4003EAC01C8000044CA000CDC1201040 +:100DB0007C410000C814000904180000041C00084D +:100DC000CD80007109DC000105980001CD0D000007 +:100DD00099C0FFFCCC8000628000037CCD40007194 +:100DE000C00E0100CC000041CCC1304AC83C007F9D +:100DF000CC00007F80000001CC00007FCC00007F91 +:100E000088000000CC00007F00000000000000000F +:100E100000000000000000000000000000000000D2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:10140000000103310010000400170006002100084D +:10141000002700280028002300290029002A002690 +:10142000002B0029002D0038002E003F002F004A1D +:101430000034004C00360030003900AF003A00CFD5 +:10144000003B00E4003C00FC003D016B003F00ADB0 +:1014500000410336004303490044018E004500FC6F +:10146000004601AC004701AC004801FE0049020CF7 +:10147000004A0255004B02820052025F0053027183 +:1014800000540287005702990060029D006102AC7F +:10149000006202B6006302C0006402CA006502D4A2 +:1014A000006602DE006702E8006802F2006902F6E8 +:1014B000006A02FA006B02FE006C0302006D030674 +:1014C000006E030A006F030E0070031200720363C4 +:1014D0000074036900790367007C031C000F037824 +:1014E000000F0378000F0378000F0378000F0378D4 +:1014F000000F0378000F0378000F0378000F0378C4 +:10150000000F0378000F0378000F0378000F0378B3 +:10151000000F0378000F0378000F0378000F0378A3 +:10152000000F0378000F0378000F0378000F037893 +:10153000000F0378000F0378000F0378000F037883 +:00000001FF diff --git a/firmware/radeon/RV730_pfp.bin.ihex b/firmware/radeon/RV730_pfp.bin.ihex new file mode 100644 index 0000000..3d811ff --- /dev/null +++ b/firmware/radeon/RV730_pfp.bin.ihex @@ -0,0 +1,213 @@ +:100000007C408000A00000007E82800B8000000009 +:10001000DC030000CC800040D04000407C408000E9 +:10002000A00000007E82800BC818000E31980001ED +:100030007C4240009580023A7C428000C81C001C33 +:10004000C037C0007C40C0007C4100007CB4800B05 +:10005000C036000399C00000C81C001C7CB4800C92 +:1000600024D400027D654000CD400043CE80004393 +:10007000CD000043CC800040CE400040CE80004008 +:10008000CCC00040DC3A00009780FFDECD0000408D +:100090007C40C000800000187C410000D400034078 +:1000A000D4000FC0D4000FA2C818000E8000000CAE +:1000B00031980002D40003C0D4000FC0D4000FA2B6 +:1000C000C818000E288C000830CC000F3410000136 +:1000D0007D0D00088000000C7D91800BCC800040DD +:1000E000D04000407C408000A00000007E82800B59 +:1000F000D4000340D4000FC0D4000FA2CC80004035 +:10010000D04000407C408000A00000007E82800B38 +:10011000D40003C0D4000FC0D4000FA2CC80004094 +:10012000D04000407C408000A00000007E82800B18 +:10013000CC4003F980000249CC4003F8C037FFFFF0 +:100140007C414000CF41A29EC82003F8C81C03F99F +:1001500066200020C81803FB7DE1C02C7D58C00834 +:100160007CDCC02069100020C0360003CC000054A5 +:100170007CB4800C80000069CC8000407C41800011 +:10018000CD81A29ECC80004080000067CD800040E1 +:10019000C019FFFFCC800040CD81A29E7C40C000F2 +:1001A0007C4100007C414000CCC1A1FACD01A1F905 +:1001B000CD41A29DCCC00040CD000040CD400040CC +:1001C000CC4000407C408000A00000007E82800B7C +:1001D000CC000054CC8000407C40C0007C4100003A +:1001E0007C414000CCC1A1FACD01A1F9CD41A29D35 +:1001F000CCC00040CD000040CD400040D040004089 +:100200007C408000A00000007E82800B7C40C0000B +:1002100030D00001CCC1A29F95000003041400015E +:1002200004140002CD4003FBCC800040800000009D +:10023000CCC000407C40C000CC800040CCC1A2A219 +:1002400080000000CCC000407C40C00028D4001FCB +:10025000CC800040954000037C410000CCC000579A +:100260002918001FCCC0004095800003CD0000403D +:10027000CD00005880000249CC00007FC820001744 +:10028000C83000229A0000060E280001C824001E73 +:100290000A640001D4001240CE400040C036C000C5 +:1002A0009680000737747900041C0001CF4000409D +:1002B000CDC00040CF0003FA7C030000CA0C001040 +:1002C0007C41000094C000047C414000D42002C462 +:1002D000CDE000449B00000B7C418000CC00004B33 +:1002E000CDA00049CD200041CD600041CDA000410E +:1002F00006200001CE00005680000249CC00007F9D +:10030000C8280020C82C0021CC0000637EEA4001F0 +:10031000657400207F53402C269C00027DF5C02090 +:1003200069F80020CE80004BCE600049CDE000414E +:10033000CFA00041CE600041271C00027DF5C02007 +:1003400069F800207DB24001CF00004BCE6000492B +:10035000CDE00041CFA00041800000BCCE60004154 +:10036000C8200017C83000229A0000060E2800019D +:10037000C824001E0A640001D4001240CE40004090 +:10038000CA0C00107C41000094C0000BC036C000B5 +:100390009680000737747900041C0001CF400040AC +:1003A000CDC00040CF0003FA7C030000800000B500 +:1003B0007C414000CC000048800000EE00000000BE +:1003C000C8200017C81C00230E24000299C0001585 +:1003D0007C4180000A200001CE000056D400044079 +:1003E000CC000040C036C000CA140013964000077D +:1003F00037747900CF400040CC000040C83003FA89 +:1004000080000103CF000022CC000022954001466D +:10041000CC00007FCCA0004680000000CC2000462D +:1004200080000249CC000064C8200017C810001FDB +:100430009600000509100001D4000440CD000040E2 +:10044000CD000022CC800040D0400040C80C0025E8 +:1004500094C0FEECC8100008CD000040D4000FC0CE +:1004600080000000D4000FA27C40C0007C4100004E +:10047000CCC003FDCD0003FCCCC00042CD00004247 +:100480002914001F29180010319800073B5C000157 +:100490007D76000B998000057D5E400BCC0000420C +:1004A00080000249CC00004D29980001292C000849 +:1004B0009980003D32EC0001960000042930000CC8 +:1004C00080000249CC00004204140010CD400042DC +:1004D00033300001342800018400015DC81400039A +:1004E0009B40001B0438000C8400015DC81400030D +:1004F0009B400017043800088400015DC814000305 +:100500009B400013043800048400015DC8140003FC +:100510009B400015C80C03FD9A800009C81003FC1D +:100520009B000101CC00004D04140010CCC000421F +:10053000CD00004280000135CD40004296C000FA57 +:10054000CC00004D80000249CC00004E9AC0000350 +:10055000CC00004DCC00004EDF8300008000000086 +:10056000D80301FF9AC000F0CC00004D8000024982 +:10057000CC00004EC8180003C81C0003C8200003AC +:100580007D5D40037DA1C0037D5D400C2A10001FEE +:10059000299C001F7D1D000B7D17400B880000006B +:1005A0007E92800B96400004CC00004E80000249F1 +:1005B000CC00004204380008CF800042C808000385 +:1005C000C80C0003C8100003C8140003C8180003B7 +:1005D000C81C0003C8240003C828000329FC001F0E +:1005E0002AB0001F7FF3C00B28F0001F7FF3C00B61 +:1005F0002970001F7FF3C00B7D8880017DCCC00176 +:100600007E5100017E9540017C9080027CD4C00226 +:100610007CBC800B9AC000037C8F400B38B4000177 +:100620009B4000C1CC00004D9BC000BFCC00004EE1 +:10063000C80C03FDC81003FCCCC000428000016E52 +:10064000CD000042D4000340D4000FC0D4000FA25C +:10065000CC800040CC400040CC400040CC4000402A +:100660007C40C000CCC00040CCC0000D8000000029 +:10067000D04000407C40C0007C4100006514002058 +:100680007D4D402C245800027D5980207C41C000C3 +:10069000CD80004269980020CD800042CDC000424C +:1006A000C023C00005E400027CA0800B266400107B +:1006B0007CA4800CCC800040CDC00040CCC0004069 +:1006C00095C0000ECD00004009DC0001C8280003E1 +:1006D00096800008CE800040C834001D974000007E +:1006E000C834001D26A800088400024CCC2B000052 +:1006F00099C0FFF709DC0001DC3A00009780000494 +:100700007C418000800001A225980002A00000002A +:100710007D808000C818001D7C40C00064D00008A7 +:1007200095800000C818001DCC130000CC8000404C +:10073000CCC0004080000000CC400040C810001F2A +:100740007C40C000CC8000407CD1400CCD400040BB +:100750000518000180000000CD8000227C40C00010 +:10076000645000208400024CCC0000617CD0C02C7E +:10077000C8200017C8D60000994000087C438000BC +:10078000DF830000CFA0004F8400024CCC00006249 +:1007900080000000D040007F80000249CC00006251 +:1007A0008400024CCC000061C82000177C40C000CF +:1007B000C036FF00C810000DC0303FFF7CF5400B75 +:1007C0007D51800B7D81800F998000087CF3800B28 +:1007D000DF830000CFA0004F8400024CCC000062F9 +:1007E00080000000D040007F80000249CC00006201 +:1007F0008400024C7C40C00028DC000895C0001931 +:1008000030DC00107C41000099C0000464540020DA +:1008100080000208C91D00007D15002CC91E0000C3 +:100820007C4200007C4240007C4180007DE5C00BA2 +:100830007DE280079A80000E41AC00059AC000005E +:100840000AEC000130DC001099C000040000000038 +:100850008000020BC91D00008000020BC91E0000B1 +:10086000CC800040CCC00040D0400040C80C0025E7 +:1008700094C0FDE4C8100008CD000040D4000FC0B3 +:1008800080000000D4000FA2D4000340D4000FC0A9 +:10089000D4000FA2CC800040D04000407C408000BB +:1008A000A00000007E82800BD40003C0D4000FC0E3 +:1008B000D4000FA2CC800040D04000407C4080009B +:1008C000A00000007E82800B7C40C00030D000067B +:1008D0000D10000699000007C81400159940000586 +:1008E000CC000052D4000340D4000FC0D4000FA2AB +:1008F000CC800040CCC0004080000000D0400040D0 +:100900007C40C000CC4D0000DC3A00009780FDBD6B +:1009100004CC000180000242CC4D000080000000A9 +:10092000D040007FCC00007F80000000CC00007F22 +:10093000CC00007F88000000CC00007F0000000099 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C0000000302220004022A0005009F00020003E4 +:100C10000006003C0007002700080191000900447D +:100C2000000A002D00100247001700F0002201D733 +:100C3000002301E80026004C0027005F0020011A75 +:100C4000002800920029004F002A0083002B006436 +:100C5000002F008D003200D80034023200360074BC +:100C60000039010A003C01FC003F009F00410005E3 +:100C7000004401940048019D004901C5004A01CF8C +:100C8000005502250056022D0060000A0061002A6E +:100C90000062003000630030006400300065003006 +:100CA0000066003000670030006800370069003FD0 +:100CB000006A0047006B0047006C0047006D00476A +:100CC000006E0047006F0047007000470073024746 +:100CD000007B024000000005000000050000000548 +:100CE00000000005000000050000000500000005F0 +:100CF00000000005000000050000000500000005E0 +:100D000000000005000000050000000500000005CF +:100D100000000005000000050000000500000005BF +:100D200000000005000000050000000500000005AF +:100D3000000000050000000500000005000000059F +:00000001FF diff --git a/firmware/radeon/RV770_me.bin.ihex b/firmware/radeon/RV770_me.bin.ihex new file mode 100644 index 0000000..a0e1699 --- /dev/null +++ b/firmware/radeon/RV770_me.bin.ihex @@ -0,0 +1,341 @@ +:10000000CC0003EA7C408000A0000000CC800062AD +:1000100080000001D040007F80000001CC40004102 +:100020007C40C000C016000430D03FFF7D15000C9E +:10003000CC11000028D8001E3198000128DC001FD8 +:10004000C820000495C000067C424000CC0000623D +:100050007E56800CCC290000C82400047E26000BAC +:10006000958000067C42C000CC0000627ED7000C68 +:10007000CC310000C82C00047E2E000CCC000062A5 +:1000800031103FFF80000001CE1100007C40C00015 +:1000900080000001CC40004080000001CC4122578C +:1000A0007C418000CC400045CC400048CC41225CE3 +:1000B000CC41A1FC7C408000A0000000CC8000620C +:1000C000CC400045CC4000487C40C000CC41225C84 +:1000D000CC41A1FC7C408000A0000000CC800062EC +:1000E000CC000045CC000048CC41225CCC41A1FCB6 +:1000F0007C408000A0000000CC800062040CA1FDC8 +:10010000C0120001CC000045CC0000487CD0C00CDF +:10011000CC41225CCC41A1FCD04D00007C40800051 +:10012000A0000000CC80006280000001CC41225D74 +:100130007C4080007C40C000C02A00027C4100005E +:100140007D29000C3094000130980006309C03009B +:1001500029DC00087C4200007C4240009540000FF2 +:10016000C02E000405F022587F2F000CCC31000077 +:10017000C8280004CCC12169CD01216ACE81216B40 +:100180000DB40002CC01216C9740000E0DB40000AC +:100190008000007BC834000A0DB4000297400009BB +:1001A0000DB40000C02E000405F022587F2F000C73 +:1001B000CC310000C82800048000007BC834000A4D +:1001C000974000047E0280008000007BC834000A53 +:1001D0000DB400049740FF8C00000000CE01216D9B +:1001E000CE41216EC8280003C834000A9B40000499 +:1001F000043C00058400026DCC0000620DF4000098 +:100200009740000BC82C03E6CE81A2B7C030000691 +:100210007EF34028C03000207F6B80207FB3C02950 +:10022000CF81A2C480000001CFC1A2D10DF4000192 +:100230009740000BC82C03E7CE81A2BBC03000065C +:100240007EF34028C03000207F6B80207FB3C02920 +:10025000CF81A2C580000001CFC1A2D20DF400025F +:100260009740000BC82C03E8CE81A2BFC030000627 +:100270007EF34028C03000207F6B80207FB3C029F0 +:10028000CF81A2C680000001CFC1A2D3C82C03E950 +:10029000CE81A2C3C03000067EF34028C0300020CB +:1002A0007F6B80207FB3C029CF81A2C7800000016F +:1002B000CFC1A2D480000001CC4000427C40C000ED +:1002C0007C4100002914001D315400019940000DAB +:1002D00031181000C81C001109DC000195C0FFFF97 +:1002E000C81C0011CCC12100CD012101CCC12102CB +:1002F000CD012103041800048000039FCD81A2A436 +:10030000C02A00049580000836A821A3CC2900004B +:10031000C8280004C81C00110DE400409640FFFFEF +:10032000C81C0011CCC12170CD012171C820001260 +:1003300096000000C82000128000039FCC000064DB +:100340007C40C0007C410000CC000045CC0000484F +:1003500040D40003CD41225CCD01A1FCC01A0001B4 +:10036000041CA1FD7DD9C00C7C42000008CC00011A +:100370000624000106280002CE1D0000CE5D00000C +:1003800098C0FFFACE9D00007C408000A0000000D5 +:10039000CC8000627C40C00030D0000128CC00013D +:1003A0007C414000950000067C418000CD41216DDC +:1003B000CD81216E800000F3C81C0003C022000420 +:1003C0007E16000CCC210000C81C00047C424000BA +:1003D00098C000047C42800080000001CDE5000050 +:1003E000CE412169CE81216ACDC1216B80000001FF +:1003F000CC01216C7C40C0007C4100007C4140006D +:100400007C4180007C41C00028A40008326400FFC9 +:100410000E68003C9680000A7C0200007C420000CE +:100420001E300003CC00006A9B0000034220000540 +:1004300004200040800001107C0240007E02400049 +:100440009A4000000A64000130EC00109AC0000AD3 +:10045000CC000062C02A0004C82C00217E92800CCF +:10046000CC000041CC290000CEC00021800001203A +:10047000C8300004CD01216DCD41216EC83000038C +:100480007F1F000B30F40007277800019740002AF7 +:1004900007B801259F8000000000000080000135A2 +:1004A0007F1B8004800001397F1B80058000013D97 +:1004B0007F1B8002800001417F1B8003800001457B +:1004C0007F1B8007800001497F1B80068000014E52 +:1004D00028A400089B80001928A400088000015E61 +:1004E000326400FF9B80001528A400088000015E94 +:1004F000326400FF9B80001128A400088000015E88 +:10050000326400FF9B80000D28A400088000015E7B +:10051000326400FF9B80000928A400088000015E6F +:10052000326400FF9B80000528A400088000015E63 +:10053000326400FF28A40008326400FF0E68003C0B +:100540009A80FEB128EC00087C4340007C43800088 +:100550007C43C00096C00007CC000062CF412169F7 +:10056000CF81216ACFC1216B80000001CC01216CB9 +:1005700080000001CFF50000CC00006B840003A2D6 +:100580000E68003C9A800004C82800158000000115 +:10059000D040007F9680FFAB7E0240008400023B8B +:1005A000C00E0002CC00004180000239CCC1304AAC +:1005B0007C40C0007C410000C01E000129240012C4 +:1005C000C022000296400005C0260004C027FFFBA1 +:1005D0007D25000BC02600007DD2800B7E12C00B53 +:1005E0007D25000C7C4140007C418000CCC121690C +:1005F0009A80000ACD01216ACD41216B96C0FE820E +:10060000CD81216CC830001897000000C830001858 +:1006100080000001CC000018840003A2CC00007F01 +:10062000C8140013C8180014CD41216B96C0FE7683 +:10063000CD81216C80000182C8300018C80C0008F0 +:1006400098C00000C80C00087C4100009500000222 +:10065000000000007C414000C8200009CC4000435D +:10066000CE01A1F4CC400044C00E80007C4240008A +:100670007C4280002AAC001F96C0FE63C035F000AB +:10068000CE4003E232780003267C00087FF7C00BDF +:100690007FFBC00C2A780018CFC003E3CF8003E4AF +:1006A00026B000027F3F0000CF0003E58000031F5B +:1006B0007C80C0007C40C00028D000083110000FB2 +:1006C0009500000F2528000106A801B39E800000B8 +:1006D00000000000800001D4C0120800800001E288 +:1006E000C814000F800001E9C8140010800001F058 +:1006F000CCC1A2A4800001F9C814001130D0003F81 +:100700000D2800159A8000120D28001E9A80001EE8 +:100710000D2800209A8000230D24000F0D280010C2 +:100720007E6A800C9A8000260D2000040D2400149F +:100730000D2800287E62400C7EA6800C9A80002A3C +:10074000C814001180000001CCC1A2A4C01208008E +:100750007C4140007D0CC00CC012000829580003E9 +:10076000295C000C7C4200007DD1C00B26200014C7 +:100770007E1E400C7E4E800CCE81A2A48000000123 +:10078000CD81A1FEC814000F0410210E9540000079 +:10079000C814000FD051000080000001CCC1A2A4F9 +:1007A000C81400100410210895400000C81400105F +:1007B000D051000080000001CCC1A2A4CCC1A2A4F1 +:1007C00004100001CD000019840003A2CC00007FBA +:1007D000C810001999000000C8100019800000021C +:1007E0007C40800004102100095400019540FFFF67 +:1007F000C8140011D05100008000039FCCC1A2A4F6 +:100800007C40C000CC40000D94C0FDFFCC40000EE9 +:100810007C4100009500000508CC0001C8140005CB +:10082000994000140000000098C0FFFB7C410000CC +:10083000800000027D008000C81400057C40C000DC +:100840009940000CC818000C7C4100009580FDEE1A +:10085000C820000EC81C000D662000207E1E002C43 +:10086000252400027E62402080000001CCE60000CA +:100870007C410000CC00006CCC00006DC818001F4B +:10088000C81C001E659800207DD9C02C7CD4C00CEB +:10089000CCDE000045DC0004C82800179680000F5D +:1008A000C00E0001286800082AAC001632A800FF1C +:1008B0000EB000497F2F000B9700000600000000DB +:1008C000C81400057C40C000800002237C41000069 +:1008D00080000226D040007F8400023BCC00004113 +:1008E000CCC1304A94000000C83C001A043C00050A +:1008F000CFC1A2A4C0361F90C0387FFF7C03C010B8 +:100900007F7B400CCF41217CCFC1217DCC01217E5A +:10091000C03A00040434217F7F7B400CCC350000BA +:10092000C83C00042BFC001F0438002097C00005C1 +:10093000CC0000629B8000000BB8000180000247E1 +:10094000CC000071CC01A1F404380016C0360002BE +:10095000CF81A2A488000000CF4120107C40C000BD +:1009600028D0001C9500000504D40001CD4000658E +:1009700080000001CD4000680954000280000001A1 +:10098000CD4000668400026CC81803EA7C40C000B9 +:100990009980FD9DC814001608D000019940002BD5 +:1009A000CD0000687C408000A0000000CC80006288 +:1009B000043C0005CFC1A2A4CC01A1F4840003A291 +:1009C000CC00004688000000CC00007F8400027E3E +:1009D000C81803EA7C40C0009980FD8BC81400163B +:1009E00008D0000199400019CD0000687C408000CB +:1009F000A0000000CC800062043C0022CFC1A2A471 +:100A0000840003A2CC00004788000000CC00007FD7 +:100A1000C81000169900000DCC400067800000024D +:100A20007C408000C81803EA9980FD777C40C000B4 +:100A300094C00003C810001699000004CCC00068E0 +:100A4000800000027C4080008400023BC0148000D3 +:100A5000CC000041CD41304AC01480009900000014 +:100A6000C8100016800000027C408000C012000107 +:100A70007C51400C80000001D05500007C40C0003B +:100A80007C4100007C4140007C418000291C001F0B +:100A9000CCC0004ACD00004B95C00003C01C8000B4 +:100AA000CDC12010DD830000055C2000CC00006279 +:100AB00080000001D81F41007C40C0007C41000044 +:100AC0007C4140007C418000CCC0004CCD00004DFA +:100AD000DD830000055CA00080000001D81F4100FC +:100AE0007C40C0007C4100007C4140007C41800093 +:100AF000CCC0004ECD00004FDD830000055CC0007F +:100B000080000001D81F41007C40C0007C410000F3 +:100B10007C4140007C418000CCC00050CD000051A1 +:100B2000DD830000055CF8E080000001D81F410073 +:100B30007C40C0007C4100007C4140007C41800042 +:100B4000CCC00052CD000053DD830000055CF8806E +:100B500080000001D81F41007C40C0007C410000A3 +:100B60007C4140007C418000CCC00054CD00005549 +:100B7000DD830000055CE00080000001D81F41001B +:100B80007C40C0007C4100007C4140007C418000F2 +:100B9000CCC00056CD000057DD830000055CF0009E +:100BA00080000001D81F41007C40C0007C41000053 +:100BB0007C4140007C418000CCC00058CD000059F1 +:100BC000DD830000055CF3FC80000001D81F4100BC +:100BD000D04320007C408000A0000000CC80006258 +:100BE000D043A0007C408000A0000000CC800062C8 +:100BF000D043C0007C408000A0000000CC80006298 +:100C0000D043F8E07C408000A0000000CC8000626F +:100C1000D043F8807C408000A0000000CC800062BF +:100C2000D043E0007C408000A0000000CC80006247 +:100C3000D043F0007C408000A0000000CC80006227 +:100C4000D043F3FC7C408000A0000000CC80006218 +:100C5000C81403E0CC430000CC430000CC430000A8 +:100C60007D45C000CDC30000D04300007C40800023 +:100C7000A0000000CC8000627C40C000C81003E2ED +:100C8000C81403E5C81803E3C81C03E4CD81216937 +:100C9000CDC1216ACCC1216BCC01216C04200004A0 +:100CA0007DA180007D9640029640FCD7CD8003E375 +:100CB00031280003C02DF000251800087DAD800B01 +:100CC0007DA9800C80000001CD8003E3308CFFFF04 +:100CD000D04D00007C408000A0000000CC8000626D +:100CE0007C40C0007C4100002924001832640001CF +:100CF0009A400013C8140020155800029580FFFF89 +:100D0000C8140020CC00006ECCC12180CD01218D03 +:100D1000CC4121812914001F34588000CD81218CC1 +:100D20009540FCB9CC412182C81400209940FFFFB6 +:100D3000C8140020800000027C4080007C414000FC +:100D40007C4180007C41C00065B400207F57402C6E +:100D5000D437810047740004D437810047740004FD +:100D6000D43781004774000409DC0004D4378100C3 +:100D700099C0FFF8477400042924001FC0380019E7 +:100D80009640FCA1C03E0004CF8121F837E021F954 +:100D9000CC210000C82000042A20001832200001C5 +:100DA0009A00FFFBCF8121F8800000027C40800088 +:100DB0007C40C00028D0001831100001C01600800F +:100DC00095000003C02A00047CD4C00CCCC1217C57 +:100DD000CC41217DCC41217E7C4180001DB00003AF +:100DE00036A0217F9B000003419C0005041C0040AD +:100DF00099C0000009DC0001CC210000C8240004D7 +:100E00002A6C001F419C00059AC0FFFACC8000624A +:100E1000800000027C4080007C40C00004D403E6D7 +:100E200080000001CC5400008000039FCC4003EA06 +:100E3000C01C8000044CA000CDC120107C410000EB +:100E4000C814000904180000041C0008CD800071BB +:100E500009DC000105980001CD0D000099C0FFFCE0 +:100E6000CC8000628000039FCD400071C00E010065 +:100E7000CC000041CCC1304AC83C007FCC00007F90 +:100E800080000001CC00007FCC00007F88000000C3 +:100E9000CC00007F00000000000000000000000007 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:10140000000103330010000400170006002100084B +:10141000002700280028002300290029002A002690 +:10142000002B0029002D0038002E003F002F004A1D +:101430000034004C00360030003900AF003A00D0D4 +:10144000003B00E5003C00FD003D016C003F00ADAD +:10145000004103380043036C0044018F004500FD48 +:10146000004601AD004701AD004802000049020EF0 +:10147000004A0257004B028400520261005302737B +:10148000005402890057029B0060029F006102AE77 +:10149000006202B8006302C2006402CC006502D69A +:1014A000006602E0006702EA006802F4006902F8E0 +:1014B000006A02FC006B0300006C0304006D03086B +:1014C000006E030C006F031000700314007203869B +:1014D0000074038C0079038A007C031E000F039BB9 +:1014E000000F039B000F039B000F039B000F039B48 +:1014F000000F039B000F039B000F039B000F039B38 +:10150000000F039B000F039B000F039B000F039B27 +:10151000000F039B000F039B000F039B000F039B17 +:10152000000F039B000F039B000F039B000F039B07 +:10153000000F039B000F039B000F039B000F039BF7 +:00000001FF diff --git a/firmware/radeon/RV770_pfp.bin.ihex b/firmware/radeon/RV770_pfp.bin.ihex new file mode 100644 index 0000000..a2d1619 --- /dev/null +++ b/firmware/radeon/RV770_pfp.bin.ihex @@ -0,0 +1,213 @@ +:100000007C408000A00000007E82800B8000000009 +:10001000DC030000CC800040D04000407C408000E9 +:10002000A00000007E82800BC818000E31980001ED +:100030007C424000958002527C428000C81C001C1B +:10004000C037C0007C40C0007C4100007CB4800B05 +:10005000C036000399C00000C81C001C7CB4800C92 +:1000600024D400027D654000CD400043CE80004393 +:10007000CD000043CC800040CE400040CE80004008 +:10008000CCC00040DC3A00009780FFDECD0000408D +:100090007C40C000800000187C410000D400034078 +:1000A000D4000FC0D4000FA2C818000E8000000CAE +:1000B00031980002D40003C0D4000FC0D4000FA2B6 +:1000C000C818000E288C000830CC000F3410000136 +:1000D0007D0D00088000000C7D91800BCC800040DD +:1000E000D04000407C408000A00000007E82800B59 +:1000F000D4000340D4000FC0D4000FA2CC80004035 +:10010000D04000407C408000A00000007E82800B38 +:10011000D40003C0D4000FC0D4000FA2CC80004094 +:10012000D04000407C408000A00000007E82800B18 +:10013000CC4003F980000261CC4003F8C82003F8EA +:10014000C81C03F9C81803FBC037FFFF7C414000FF +:10015000CF41A29E662000207DE1C02C7D58C008C2 +:100160007CDCC02068D00020C0360003CC000054E6 +:100170007CB4800C8000006ACC8000407C41800010 +:10018000CD81A29ECC800040CD80004080000068E0 +:10019000CC000054C019FFFFCC800040CD81A29E4E +:1001A0007C40C0007C4100007C414000CCC1A1FAF1 +:1001B000CD01A1F9CD41A29DCCC00040CD000040B1 +:1001C000CD400040CC4000407C408000A0000000BA +:1001D0007E82800BCC000054CC8000407C40C0006C +:1001E0007C4100007C414000CCC1A1FACD01A1F9C5 +:1001F000CD41A29DCCC00040CD000040CD4000408C +:10020000D04000407C408000A00000007E82800B37 +:100210007C40C00030D00001CCC1A29F95000003FB +:100220000414000104140002CD4003FBCC80004004 +:1002300080000000CCC000407C40C000CC8000406A +:10024000CCC1A2A280000000CCC000407C40C00015 +:1002500028D4001FCC800040954000037C41000062 +:10026000CCC000572918001FCCC000409580000367 +:10027000CD000040CD00005880000261CC00007F1E +:10028000C8200017C83000229A0000060E2800017E +:10029000C824001E0A640001D4001240CE40004071 +:1002A000C036C0009680000737747900041C000136 +:1002B000CF400040CDC00040CF0003FA7C030000D7 +:1002C000CA0C00107C41000094C000047C41400036 +:1002D000D42002C4CDE000449B00000B7C41800090 +:1002E000CC00004BCDA00049CD200041CD600041A5 +:1002F000CDA0004106200001CE0000568000026122 +:10030000CC00007FC8280020C82C0021CC0000634E +:100310007EEA4001657400207F53402C269C000239 +:100320007DF5C02069F80020CE80004BCE600049EA +:10033000CDE00041CFA00041CE600041271C00026B +:100340007DF5C02069F800207DB24001CF00004B50 +:10035000CE600049CDE00041CFA00041800000BD4B +:10036000CE600041C8200017C83000229A00000665 +:100370000E280001C824001E0A640001D4001240A7 +:10038000CE400040CA0C00107C41000094C0000B1D +:10039000C036C0009680000737747900041C000145 +:1003A000CF400040CDC00040CF0003FA7C030000E6 +:1003B000800000B67C414000CC000048800000EF87 +:1003C00000000000C8200017C81C00230E240002F3 +:1003D00099C000157C4180000A200001CE00005623 +:1003E000D4000440CC000040C036C000CA14001342 +:1003F0009640000737747900CF400040CC000040A1 +:10040000C83003FA80000104CF000022CC00002293 +:100410009540015DCC00007FCCA00046800000002C +:10042000CC20004680000261CC000064C820001788 +:10043000C810001F9600000509100001D4000440F8 +:10044000CD000040CD000022CC800040D0400040D4 +:10045000C80C002594C0FEEBC8100008CD00004079 +:10046000D4000FC080000000D4000FA27C40C00068 +:100470007C410000CCC003FDCD0003FCCCC0004299 +:10048000CD0000422914001F2918001031980007E0 +:100490003B5C00017D76000B998000057D5E400B82 +:1004A000CC00004280000261CC00004D2998000180 +:1004B000292C00089980003D32EC000196000004D0 +:1004C0002930000C80000261CC00004204140010AE +:1004D000CD40004233300001342800018400015E29 +:1004E000C81400039B40001B0438000C8400015E0C +:1004F000C81400039B400017043800088400015E04 +:10050000C81400039B400013043800048400015EFB +:10051000C81400039B400015C80C03FD9A80000915 +:10052000C81003FC9B000118CC00004D04140010FF +:10053000CCC00042CD00004280000136CD400042D8 +:1005400096C00111CC00004D80000261CC00004E2D +:100550009AC00003CC00004DCC00004EDF830000A9 +:1005600080000000D80301FF9AC00107CC00004DB5 +:1005700080000261CC00004EC8180003C81C0003B4 +:10058000C82000037D5D40037DA1C0037D5D400C5C +:100590002A10001F299C001F7D1D000B7D17400B9A +:1005A000880000007E92800B96400004CC00004E34 +:1005B00080000261CC00004204380008CF80004275 +:1005C000C8080003C80C0003C8100003C8140003C7 +:1005D000C8180003C81C0003C8240003C82800036F +:1005E00029FC001F2AB0001F7FF3C00B28F0001F5A +:1005F0007FF3C00B2970001F7FF3C00B7D88800143 +:100600007DCCC0017E5100017E9540017C9080022E +:100610007CD4C0027CBC800B9AC000037C8F400B52 +:1006200038B400019B4000D8CC00004D9BC000D6E0 +:10063000CC00004EC80C03FDC81003FCCCC0004227 +:100640008000016FCD000042D4000340D4000FC0F1 +:10065000D4000FA2CC800040CC400040CC400040F1 +:10066000CC4000407C40C000CCC00040CCC0000D5D +:1006700080000000D04000407C40C0007C41000071 +:10068000651400207D4D402C245800027D598020A7 +:100690007C41C000CD80004269980020CD8000429E +:1006A000CDC00042C023C00005E400027CA0800B46 +:1006B000266400107CA4800CCC800040CDC000409B +:1006C000CCC0004095C0000ECD00004009DC000108 +:1006D000C828000396800008CE800040C834001D62 +:1006E00097400000C834001D26A80008840002645A +:1006F000CC2B000099C0FFF709DC0001DC3A0000B8 +:10070000978000047C418000800001A325980002AE +:10071000A00000007D808000C818001D7C40C00043 +:1007200064D0000895800000C818001DCC1300009C +:10073000CC800040CCC0004080000000CC40004095 +:10074000C810001F7C40C000CC8000407CD1400C11 +:10075000CD4000400518000180000000CD8000223F +:100760007C40C0006450002084000264CC00006122 +:100770007CD0C02CC8200017C8D6000099400008C3 +:100780007C438000DF830000CFA0004F8400026420 +:10079000CC00006280000000D040007F8000026139 +:1007A000CC00006284000264CC000061C820001705 +:1007B0007C40C000C036FF00C810000DC0303FFFB5 +:1007C0007CF5400B7D51800B7D81800F9980000866 +:1007D0007CF3800BDF830000CFA0004F8400026415 +:1007E000CC00006280000000D040007F80000261E9 +:1007F000CC000062840002647C40C00028DC000859 +:1008000095C0001930DC00107C41000099C0000444 +:100810006454002080000209C91D00007D15002CD1 +:10082000C91E00007C4200007C4240007C418000E8 +:100830007DE5C00B7DE280079A80000E41AC00058B +:100840009AC000000AEC000130DC001099C00004DE +:10085000000000008000020CC91D00008000020C96 +:10086000C91E0000CC800040CCC00040D0400040F9 +:10087000C80C002594C0FDE3C8100008CD0000405E +:10088000D4000FC080000000D4000FA2D4000340A9 +:10089000D4000FC0D4000FA2CC800040D040004054 +:1008A0007C408000A00000007E82800BD40003C04A +:1008B000D4000FC0D4000FA2CC800040D040004034 +:1008C0007C408000A00000007E82800B7C40C00045 +:1008D00030D000060D10000699000007C81400155E +:1008E00099400005CC000052D4000340D4000FC052 +:1008F000D4000FA2CC800040CCC00040800000009B +:10090000D04000407C40C000CC4D0000DC3A0000EC +:100910009780FDBC04CC000180000243CC4D000058 +:100920007C40C0007C410000292400183264000192 +:100930009640000FCC8000407C4140007C4180000C +:100940007C41C000CCC00043CD00004331DC7FFFC0 +:10095000CDC00043CCC00040CD000040CD400040A1 +:10096000CD80004080000000CDC00040CCC00040E1 +:10097000CD00004080000000D0400040800000001A +:10098000D040007FCC00007F80000000CC00007FC2 +:10099000CC00007F88000000CC00007F0000000039 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C0000000302230004022B000500A000020003E1 +:100C10000006003C0007002700080192000900447C +:100C2000000A002D0010025F001700F1002201D819 +:100C3000002301E90026004C0027005F0020011B73 +:100C4000002800930029004F002A0084002B006533 +:100C5000002F008E003200D90034023300360075B8 +:100C60000039010B003C01FD003F00A0004102489B +:100C7000004401950048019E004901C6004A01D088 +:100C8000005502260056022E0060000A0061002A6C +:100C90000062003000630030006400300065003006 +:100CA0000066003000670030006800370069003FD0 +:100CB000006A0047006B0047006C0047006D00476A +:100CC000006E0047006F0047007000470073025F2E +:100CD000007B024100000005000000050000000547 +:100CE00000000005000000050000000500000005F0 +:100CF00000000005000000050000000500000005E0 +:100D000000000005000000050000000500000005CF +:100D100000000005000000050000000500000005BF +:100D200000000005000000050000000500000005AF +:100D3000000000050000000500000005000000059F +:00000001FF -- cgit v0.10.2 From 7dc482dfeeeefcfd000d4271c4626937406756d7 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Sun, 23 Aug 2009 16:59:04 +0100 Subject: drm/r128: Add test for initialisation to all ioctls that require it Almost all r128's private ioctls require that the CCE state has already been initialised. However, most do not test that this has been done, and will proceed to dereference a null pointer. This may result in a security vulnerability, since some ioctls are unprivileged. This adds a macro for the common initialisation test and changes all ioctl implementations that require prior initialisation to use that macro. Also, r128_do_init_cce() does not test that the CCE state has not been initialised already. Repeated initialisation may lead to a crash or resource leak. This adds that test. Signed-off-by: Ben Hutchings Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/r128/r128_cce.c b/drivers/gpu/drm/r128/r128_cce.c index 15252f6..4c39a40 100644 --- a/drivers/gpu/drm/r128/r128_cce.c +++ b/drivers/gpu/drm/r128/r128_cce.c @@ -346,6 +346,11 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init) DRM_DEBUG("\n"); + if (dev->dev_private) { + DRM_DEBUG("called when already initialized\n"); + return -EINVAL; + } + dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL); if (dev_priv == NULL) return -ENOMEM; @@ -647,6 +652,8 @@ int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_pri LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) { DRM_DEBUG("while CCE running\n"); return 0; @@ -669,6 +676,8 @@ int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + /* Flush any pending CCE commands. This ensures any outstanding * commands are exectuted by the engine before we turn it off. */ @@ -706,10 +715,7 @@ int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_pri LOCK_TEST_WITH_RETURN(dev, file_priv); - if (!dev_priv) { - DRM_DEBUG("called before init done\n"); - return -EINVAL; - } + DEV_INIT_TEST_WITH_RETURN(dev_priv); r128_do_cce_reset(dev_priv); @@ -726,6 +732,8 @@ int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + if (dev_priv->cce_running) { r128_do_cce_flush(dev_priv); } @@ -739,6 +747,8 @@ int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_ LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev->dev_private); + return r128_do_engine_reset(dev); } diff --git a/drivers/gpu/drm/r128/r128_drv.h b/drivers/gpu/drm/r128/r128_drv.h index 797a26c..3c60829 100644 --- a/drivers/gpu/drm/r128/r128_drv.h +++ b/drivers/gpu/drm/r128/r128_drv.h @@ -422,6 +422,14 @@ static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv) * Misc helper macros */ +#define DEV_INIT_TEST_WITH_RETURN(_dev_priv) \ +do { \ + if (!_dev_priv) { \ + DRM_ERROR("called with no initialization\n"); \ + return -EINVAL; \ + } \ +} while (0) + #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ do { \ drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ diff --git a/drivers/gpu/drm/r128/r128_state.c b/drivers/gpu/drm/r128/r128_state.c index 026a48c..af2665c 100644 --- a/drivers/gpu/drm/r128/r128_state.c +++ b/drivers/gpu/drm/r128/r128_state.c @@ -1244,14 +1244,18 @@ static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple) static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) { drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_r128_sarea_t *sarea_priv; drm_r128_clear_t *clear = data; DRM_DEBUG("\n"); LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + sarea_priv = dev_priv->sarea_priv; + if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; @@ -1312,6 +1316,8 @@ static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *fi LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + RING_SPACE_TEST_WITH_RETURN(dev_priv); if (!dev_priv->page_flipping) @@ -1331,6 +1337,8 @@ static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *fi LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + RING_SPACE_TEST_WITH_RETURN(dev_priv); if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) @@ -1354,10 +1362,7 @@ static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file * LOCK_TEST_WITH_RETURN(dev, file_priv); - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } + DEV_INIT_TEST_WITH_RETURN(dev_priv); DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard); @@ -1410,10 +1415,7 @@ static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file LOCK_TEST_WITH_RETURN(dev, file_priv); - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } + DEV_INIT_TEST_WITH_RETURN(dev_priv); DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, elts->idx, elts->start, elts->end, elts->discard); @@ -1476,6 +1478,8 @@ static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *fi LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx); if (blit->idx < 0 || blit->idx >= dma->buf_count) { @@ -1501,6 +1505,8 @@ static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *f LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + RING_SPACE_TEST_WITH_RETURN(dev_priv); ret = -EINVAL; @@ -1531,6 +1537,8 @@ static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file LOCK_TEST_WITH_RETURN(dev, file_priv); + DEV_INIT_TEST_WITH_RETURN(dev_priv); + if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) return -EFAULT; @@ -1555,10 +1563,7 @@ static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file LOCK_TEST_WITH_RETURN(dev, file_priv); - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } + DEV_INIT_TEST_WITH_RETURN(dev_priv); DRM_DEBUG("idx=%d s=%d e=%d d=%d\n", indirect->idx, indirect->start, indirect->end, @@ -1620,10 +1625,7 @@ static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *fi drm_r128_getparam_t *param = data; int value; - if (!dev_priv) { - DRM_ERROR("called with no initialization\n"); - return -EINVAL; - } + DEV_INIT_TEST_WITH_RETURN(dev_priv); DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); -- cgit v0.10.2 From 785b93ef8c309730c2de84ce9c229e40e2d01480 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 28 Aug 2009 15:46:53 +1000 Subject: drm/kms: move driver specific fb common code to helper functions (v2) Initially I always meant this code to be shared, but things ran away from me before I got to it. This refactors the i915 and radeon kms fbdev interaction layers out into generic helpers + driver specific pieces. It moves all the panic/sysrq enhancements to the core file, and stores a linked list of kernel fbs. This could possibly be improved to only store the fb which has fbcon on it for panics etc. radeon retains some specific codes used for a big endian workaround. changes: fix oops in v1 fix freeing path for crtc_info Reviewed-by: Jesse Barnes Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 5f0aec4..9907168 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -11,7 +11,8 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \ drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \ drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \ drm_crtc.o drm_crtc_helper.o drm_modes.o drm_edid.o \ - drm_info.o drm_debugfs.o drm_encoder_slave.o + drm_info.o drm_debugfs.o drm_encoder_slave.o \ + drm_fb_helper.o drm-$(CONFIG_COMPAT) += drm_ioc32.o diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c new file mode 100644 index 0000000..d6ffea7 --- /dev/null +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -0,0 +1,697 @@ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ +#include +#include +#include "drmP.h" +#include "drm_crtc.h" +#include "drm_fb_helper.h" +#include "drm_crtc_helper.h" + +static LIST_HEAD(kernel_fb_helper_list); + +bool drm_fb_helper_force_kernel_mode(void) +{ + int i = 0; + bool ret, error = false; + struct drm_fb_helper *helper; + + if (list_empty(&kernel_fb_helper_list)) + return false; + + list_for_each_entry(helper, &kernel_fb_helper_list, kernel_fb_list) { + for (i = 0; i < helper->crtc_count; i++) { + struct drm_mode_set *mode_set = &helper->crtc_info[i].mode_set; + ret = drm_crtc_helper_set_config(mode_set); + if (ret) + error = true; + } + } + return error; +} + +int drm_fb_helper_panic(struct notifier_block *n, unsigned long ununsed, + void *panic_str) +{ + DRM_ERROR("panic occurred, switching back to text console\n"); + return drm_fb_helper_force_kernel_mode(); + return 0; +} +EXPORT_SYMBOL(drm_fb_helper_panic); + +static struct notifier_block paniced = { + .notifier_call = drm_fb_helper_panic, +}; + +/** + * drm_fb_helper_restore - restore the framebuffer console (kernel) config + * + * Restore's the kernel's fbcon mode, used for lastclose & panic paths. + */ +void drm_fb_helper_restore(void) +{ + bool ret; + ret = drm_fb_helper_force_kernel_mode(); + if (ret == true) + DRM_ERROR("Failed to restore crtc configuration\n"); +} +EXPORT_SYMBOL(drm_fb_helper_restore); + +static void drm_fb_helper_restore_work_fn(struct work_struct *ignored) +{ + drm_fb_helper_restore(); +} +static DECLARE_WORK(drm_fb_helper_restore_work, drm_fb_helper_restore_work_fn); + +static void drm_fb_helper_sysrq(int dummy1, struct tty_struct *dummy3) +{ + schedule_work(&drm_fb_helper_restore_work); +} + +static struct sysrq_key_op sysrq_drm_fb_helper_restore_op = { + .handler = drm_fb_helper_sysrq, + .help_msg = "force-fb(V)", + .action_msg = "Restore framebuffer console", +}; + +static void drm_fb_helper_on(struct fb_info *info) +{ + struct drm_fb_helper *fb_helper = info->par; + struct drm_device *dev = fb_helper->dev; + struct drm_crtc *crtc; + struct drm_encoder *encoder; + int i; + + /* + * For each CRTC in this fb, turn the crtc on then, + * find all associated encoders and turn them on. + */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; + + for (i = 0; i < fb_helper->crtc_count; i++) { + if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) + break; + } + + mutex_lock(&dev->mode_config.mutex); + crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); + mutex_unlock(&dev->mode_config.mutex); + + /* Found a CRTC on this fb, now find encoders */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + struct drm_encoder_helper_funcs *encoder_funcs; + + encoder_funcs = encoder->helper_private; + mutex_lock(&dev->mode_config.mutex); + encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); + mutex_unlock(&dev->mode_config.mutex); + } + } + } +} + +static void drm_fb_helper_off(struct fb_info *info, int dpms_mode) +{ + struct drm_fb_helper *fb_helper = info->par; + struct drm_device *dev = fb_helper->dev; + struct drm_crtc *crtc; + struct drm_encoder *encoder; + int i; + + /* + * For each CRTC in this fb, find all associated encoders + * and turn them off, then turn off the CRTC. + */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; + + for (i = 0; i < fb_helper->crtc_count; i++) { + if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) + break; + } + + /* Found a CRTC on this fb, now find encoders */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + struct drm_encoder_helper_funcs *encoder_funcs; + + encoder_funcs = encoder->helper_private; + mutex_lock(&dev->mode_config.mutex); + encoder_funcs->dpms(encoder, dpms_mode); + mutex_unlock(&dev->mode_config.mutex); + } + } + if (dpms_mode == DRM_MODE_DPMS_OFF) { + mutex_lock(&dev->mode_config.mutex); + crtc_funcs->dpms(crtc, dpms_mode); + mutex_unlock(&dev->mode_config.mutex); + } + } +} + +int drm_fb_helper_blank(int blank, struct fb_info *info) +{ + switch (blank) { + case FB_BLANK_UNBLANK: + drm_fb_helper_on(info); + break; + case FB_BLANK_NORMAL: + drm_fb_helper_off(info, DRM_MODE_DPMS_STANDBY); + break; + case FB_BLANK_HSYNC_SUSPEND: + drm_fb_helper_off(info, DRM_MODE_DPMS_STANDBY); + break; + case FB_BLANK_VSYNC_SUSPEND: + drm_fb_helper_off(info, DRM_MODE_DPMS_SUSPEND); + break; + case FB_BLANK_POWERDOWN: + drm_fb_helper_off(info, DRM_MODE_DPMS_OFF); + break; + } + return 0; +} +EXPORT_SYMBOL(drm_fb_helper_blank); + +static void drm_fb_helper_crtc_free(struct drm_fb_helper *helper) +{ + int i; + + for (i = 0; i < helper->crtc_count; i++) + kfree(helper->crtc_info[i].mode_set.connectors); + kfree(helper->crtc_info); +} + +int drm_fb_helper_init_crtc_count(struct drm_fb_helper *helper, int crtc_count, int max_conn_count) +{ + struct drm_device *dev = helper->dev; + struct drm_crtc *crtc; + int ret = 0; + int i; + + helper->crtc_info = kcalloc(crtc_count, sizeof(struct drm_fb_helper_crtc), GFP_KERNEL); + if (!helper->crtc_info) + return -ENOMEM; + + helper->crtc_count = crtc_count; + + for (i = 0; i < crtc_count; i++) { + helper->crtc_info[i].mode_set.connectors = + kcalloc(max_conn_count, + sizeof(struct drm_connector *), + GFP_KERNEL); + + if (!helper->crtc_info[i].mode_set.connectors) { + ret = -ENOMEM; + goto out_free; + } + helper->crtc_info[i].mode_set.num_connectors = 0; + } + + i = 0; + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + helper->crtc_info[i].crtc_id = crtc->base.id; + helper->crtc_info[i].mode_set.crtc = crtc; + i++; + } + helper->conn_limit = max_conn_count; + return 0; +out_free: + drm_fb_helper_crtc_free(helper); + return -ENOMEM; +} +EXPORT_SYMBOL(drm_fb_helper_init_crtc_count); + +int drm_fb_helper_setcolreg(unsigned regno, + unsigned red, + unsigned green, + unsigned blue, + unsigned transp, + struct fb_info *info) +{ + struct drm_fb_helper *fb_helper = info->par; + struct drm_device *dev = fb_helper->dev; + struct drm_crtc *crtc; + int i; + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct drm_framebuffer *fb = fb_helper->fb; + + for (i = 0; i < fb_helper->crtc_count; i++) { + if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) + break; + } + if (i == fb_helper->crtc_count) + continue; + + if (regno > 255) + return 1; + + if (fb->depth == 8) { + fb_helper->funcs->gamma_set(crtc, red, green, blue, regno); + return 0; + } + + if (regno < 16) { + switch (fb->depth) { + case 15: + fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) | + ((green & 0xf800) >> 6) | + ((blue & 0xf800) >> 11); + break; + case 16: + fb->pseudo_palette[regno] = (red & 0xf800) | + ((green & 0xfc00) >> 5) | + ((blue & 0xf800) >> 11); + break; + case 24: + case 32: + fb->pseudo_palette[regno] = + (((red >> 8) & 0xff) << info->var.red.offset) | + (((green >> 8) & 0xff) << info->var.green.offset) | + (((blue >> 8) & 0xff) << info->var.blue.offset); + break; + } + } + } + return 0; +} +EXPORT_SYMBOL(drm_fb_helper_setcolreg); + +int drm_fb_helper_check_var(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct drm_fb_helper *fb_helper = info->par; + struct drm_framebuffer *fb = fb_helper->fb; + int depth; + + if (var->pixclock == -1 || !var->pixclock) + return -EINVAL; + + /* Need to resize the fb object !!! */ + if (var->xres > fb->width || var->yres > fb->height) { + DRM_ERROR("Requested width/height is greater than current fb " + "object %dx%d > %dx%d\n", var->xres, var->yres, + fb->width, fb->height); + DRM_ERROR("Need resizing code.\n"); + return -EINVAL; + } + + switch (var->bits_per_pixel) { + case 16: + depth = (var->green.length == 6) ? 16 : 15; + break; + case 32: + depth = (var->transp.length > 0) ? 32 : 24; + break; + default: + depth = var->bits_per_pixel; + break; + } + + switch (depth) { + case 8: + var->red.offset = 0; + var->green.offset = 0; + var->blue.offset = 0; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.length = 0; + var->transp.offset = 0; + break; + case 15: + var->red.offset = 10; + var->green.offset = 5; + var->blue.offset = 0; + var->red.length = 5; + var->green.length = 5; + var->blue.length = 5; + var->transp.length = 1; + var->transp.offset = 15; + break; + case 16: + var->red.offset = 11; + var->green.offset = 5; + var->blue.offset = 0; + var->red.length = 5; + var->green.length = 6; + var->blue.length = 5; + var->transp.length = 0; + var->transp.offset = 0; + break; + case 24: + var->red.offset = 16; + var->green.offset = 8; + var->blue.offset = 0; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.length = 0; + var->transp.offset = 0; + break; + case 32: + var->red.offset = 16; + var->green.offset = 8; + var->blue.offset = 0; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.length = 8; + var->transp.offset = 24; + break; + default: + return -EINVAL; + } + return 0; +} +EXPORT_SYMBOL(drm_fb_helper_check_var); + +/* this will let fbcon do the mode init */ +int drm_fb_helper_set_par(struct fb_info *info) +{ + struct drm_fb_helper *fb_helper = info->par; + struct drm_device *dev = fb_helper->dev; + struct fb_var_screeninfo *var = &info->var; + struct drm_crtc *crtc; + int ret; + int i; + + if (var->pixclock != -1) { + DRM_ERROR("PIXEL CLCOK SET\n"); + return -EINVAL; + } + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + + for (i = 0; i < fb_helper->crtc_count; i++) { + if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) + break; + } + if (i == fb_helper->crtc_count) + continue; + + if (crtc->fb == fb_helper->crtc_info[i].mode_set.fb) { + mutex_lock(&dev->mode_config.mutex); + ret = crtc->funcs->set_config(&fb_helper->crtc_info->mode_set); + mutex_unlock(&dev->mode_config.mutex); + if (ret) + return ret; + } + } + return 0; +} +EXPORT_SYMBOL(drm_fb_helper_set_par); + +int drm_fb_helper_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct drm_fb_helper *fb_helper = info->par; + struct drm_device *dev = fb_helper->dev; + struct drm_mode_set *modeset; + struct drm_crtc *crtc; + int ret = 0; + int i; + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + for (i = 0; i < fb_helper->crtc_count; i++) { + if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) + break; + } + + if (i == fb_helper->crtc_count) + continue; + + modeset = &fb_helper->crtc_info[i].mode_set; + + modeset->x = var->xoffset; + modeset->y = var->yoffset; + + if (modeset->num_connectors) { + mutex_lock(&dev->mode_config.mutex); + ret = crtc->funcs->set_config(modeset); + mutex_unlock(&dev->mode_config.mutex); + if (!ret) { + info->var.xoffset = var->xoffset; + info->var.yoffset = var->yoffset; + } + } + } + return ret; +} +EXPORT_SYMBOL(drm_fb_helper_pan_display); + +int drm_fb_helper_single_fb_probe(struct drm_device *dev, + int (*fb_create)(struct drm_device *dev, + uint32_t fb_width, + uint32_t fb_height, + uint32_t surface_width, + uint32_t surface_height, + struct drm_framebuffer **fb_ptr)) +{ + struct drm_crtc *crtc; + struct drm_connector *connector; + unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1; + unsigned int surface_width = 0, surface_height = 0; + int new_fb = 0; + int crtc_count = 0; + int ret, i, conn_count = 0; + struct fb_info *info; + struct drm_framebuffer *fb; + struct drm_mode_set *modeset = NULL; + struct drm_fb_helper *fb_helper; + + /* first up get a count of crtcs now in use and new min/maxes width/heights */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + if (drm_helper_crtc_in_use(crtc)) { + if (crtc->desired_mode) { + if (crtc->desired_mode->hdisplay < fb_width) + fb_width = crtc->desired_mode->hdisplay; + + if (crtc->desired_mode->vdisplay < fb_height) + fb_height = crtc->desired_mode->vdisplay; + + if (crtc->desired_mode->hdisplay > surface_width) + surface_width = crtc->desired_mode->hdisplay; + + if (crtc->desired_mode->vdisplay > surface_height) + surface_height = crtc->desired_mode->vdisplay; + } + crtc_count++; + } + } + + if (crtc_count == 0 || fb_width == -1 || fb_height == -1) { + /* hmm everyone went away - assume VGA cable just fell out + and will come back later. */ + return 0; + } + + /* do we have an fb already? */ + if (list_empty(&dev->mode_config.fb_kernel_list)) { + ret = (*fb_create)(dev, fb_width, fb_height, surface_width, + surface_height, &fb); + if (ret) + return -EINVAL; + new_fb = 1; + } else { + fb = list_first_entry(&dev->mode_config.fb_kernel_list, + struct drm_framebuffer, filp_head); + + /* if someone hotplugs something bigger than we have already allocated, we are pwned. + As really we can't resize an fbdev that is in the wild currently due to fbdev + not really being designed for the lower layers moving stuff around under it. + - so in the grand style of things - punt. */ + if ((fb->width < surface_width) || + (fb->height < surface_height)) { + DRM_ERROR("Framebuffer not large enough to scale console onto.\n"); + return -EINVAL; + } + } + + info = fb->fbdev; + fb_helper = info->par; + + crtc_count = 0; + /* okay we need to setup new connector sets in the crtcs */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + modeset = &fb_helper->crtc_info[crtc_count].mode_set; + modeset->fb = fb; + conn_count = 0; + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + if (connector->encoder) + if (connector->encoder->crtc == modeset->crtc) { + modeset->connectors[conn_count] = connector; + conn_count++; + if (conn_count > fb_helper->conn_limit) + BUG(); + } + } + + for (i = conn_count; i < fb_helper->conn_limit; i++) + modeset->connectors[i] = NULL; + + modeset->crtc = crtc; + crtc_count++; + + modeset->num_connectors = conn_count; + if (modeset->crtc->desired_mode) { + if (modeset->mode) + drm_mode_destroy(dev, modeset->mode); + modeset->mode = drm_mode_duplicate(dev, + modeset->crtc->desired_mode); + } + } + fb_helper->crtc_count = crtc_count; + fb_helper->fb = fb; + + if (new_fb) { + info->var.pixclock = -1; + if (register_framebuffer(info) < 0) + return -EINVAL; + } else { + drm_fb_helper_set_par(info); + } + printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, + info->fix.id); + + /* Switch back to kernel console on panic */ + /* multi card linked list maybe */ + if (list_empty(&kernel_fb_helper_list)) { + printk(KERN_INFO "registered panic notifier\n"); + atomic_notifier_chain_register(&panic_notifier_list, + &paniced); + register_sysrq_key('v', &sysrq_drm_fb_helper_restore_op); + } + list_add(&fb_helper->kernel_fb_list, &kernel_fb_helper_list); + return 0; +} +EXPORT_SYMBOL(drm_fb_helper_single_fb_probe); + +void drm_fb_helper_free(struct drm_fb_helper *helper) +{ + list_del(&helper->kernel_fb_list); + if (list_empty(&kernel_fb_helper_list)) { + printk(KERN_INFO "unregistered panic notifier\n"); + atomic_notifier_chain_unregister(&panic_notifier_list, + &paniced); + unregister_sysrq_key('v', &sysrq_drm_fb_helper_restore_op); + } + drm_fb_helper_crtc_free(helper); +} +EXPORT_SYMBOL(drm_fb_helper_free); + +void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch) +{ + info->fix.type = FB_TYPE_PACKED_PIXELS; + info->fix.visual = FB_VISUAL_TRUECOLOR; + info->fix.type_aux = 0; + info->fix.xpanstep = 1; /* doing it in hw */ + info->fix.ypanstep = 1; /* doing it in hw */ + info->fix.ywrapstep = 0; + info->fix.accel = FB_ACCEL_I830; + info->fix.type_aux = 0; + + info->fix.line_length = pitch; + return; +} +EXPORT_SYMBOL(drm_fb_helper_fill_fix); + +void drm_fb_helper_fill_var(struct fb_info *info, struct drm_framebuffer *fb, + uint32_t fb_width, uint32_t fb_height) +{ + info->pseudo_palette = fb->pseudo_palette; + info->var.xres_virtual = fb->width; + info->var.yres_virtual = fb->height; + info->var.bits_per_pixel = fb->bits_per_pixel; + info->var.xoffset = 0; + info->var.yoffset = 0; + info->var.activate = FB_ACTIVATE_NOW; + info->var.height = -1; + info->var.width = -1; + + switch (fb->depth) { + case 8: + info->var.red.offset = 0; + info->var.green.offset = 0; + info->var.blue.offset = 0; + info->var.red.length = 8; /* 8bit DAC */ + info->var.green.length = 8; + info->var.blue.length = 8; + info->var.transp.offset = 0; + info->var.transp.length = 0; + break; + case 15: + info->var.red.offset = 10; + info->var.green.offset = 5; + info->var.blue.offset = 0; + info->var.red.length = 5; + info->var.green.length = 5; + info->var.blue.length = 5; + info->var.transp.offset = 15; + info->var.transp.length = 1; + break; + case 16: + info->var.red.offset = 11; + info->var.green.offset = 5; + info->var.blue.offset = 0; + info->var.red.length = 5; + info->var.green.length = 6; + info->var.blue.length = 5; + info->var.transp.offset = 0; + break; + case 24: + info->var.red.offset = 16; + info->var.green.offset = 8; + info->var.blue.offset = 0; + info->var.red.length = 8; + info->var.green.length = 8; + info->var.blue.length = 8; + info->var.transp.offset = 0; + info->var.transp.length = 0; + break; + case 32: + info->var.red.offset = 16; + info->var.green.offset = 8; + info->var.blue.offset = 0; + info->var.red.length = 8; + info->var.green.length = 8; + info->var.blue.length = 8; + info->var.transp.offset = 24; + info->var.transp.length = 8; + break; + default: + break; + } + + info->var.xres = fb_width; + info->var.yres = fb_height; +} +EXPORT_SYMBOL(drm_fb_helper_fill_var); diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 544d889..c628c36 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -29,6 +29,7 @@ #include "drmP.h" #include "drm.h" #include "drm_crtc_helper.h" +#include "drm_fb_helper.h" #include "intel_drv.h" #include "i915_drm.h" #include "i915_drv.h" @@ -1347,7 +1348,7 @@ void i915_driver_lastclose(struct drm_device * dev) drm_i915_private_t *dev_priv = dev->dev_private; if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { - intelfb_restore(); + drm_fb_helper_restore(); return; } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d6fce21..5fb7a4f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3060,8 +3060,6 @@ static void intel_crtc_destroy(struct drm_crtc *crtc) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - if (intel_crtc->mode_set.mode) - drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode); drm_crtc_cleanup(crtc); kfree(intel_crtc); } @@ -3107,16 +3105,6 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) intel_crtc->cursor_addr = 0; intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); - - intel_crtc->mode_set.crtc = &intel_crtc->base; - intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1); - intel_crtc->mode_set.num_connectors = 0; - - if (i915_fbpercrtc) { - - - - } } int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d6f92ea..38910f8 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -96,9 +96,6 @@ struct intel_crtc { uint32_t cursor_addr; u8 lut_r[256], lut_g[256], lut_b[256]; int dpms_mode; - struct intel_framebuffer *fbdev_fb; - /* a mode_set for fbdev users on this crtc */ - struct drm_mode_set mode_set; }; #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c index 1d30802..3041530 100644 --- a/drivers/gpu/drm/i915/intel_fb.c +++ b/drivers/gpu/drm/i915/intel_fb.c @@ -39,339 +39,34 @@ #include "drmP.h" #include "drm.h" #include "drm_crtc.h" +#include "drm_fb_helper.h" #include "intel_drv.h" #include "i915_drm.h" #include "i915_drv.h" struct intelfb_par { - struct drm_device *dev; - struct drm_display_mode *our_mode; + struct drm_fb_helper helper; struct intel_framebuffer *intel_fb; - int crtc_count; - /* crtc currently bound to this */ - uint32_t crtc_ids[2]; + struct drm_display_mode *our_mode; }; -static int intelfb_setcolreg(unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, - struct fb_info *info) -{ - struct intelfb_par *par = info->par; - struct drm_device *dev = par->dev; - struct drm_crtc *crtc; - int i; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_mode_set *modeset = &intel_crtc->mode_set; - struct drm_framebuffer *fb = modeset->fb; - - for (i = 0; i < par->crtc_count; i++) - if (crtc->base.id == par->crtc_ids[i]) - break; - - if (i == par->crtc_count) - continue; - - - if (regno > 255) - return 1; - - if (fb->depth == 8) { - intel_crtc_fb_gamma_set(crtc, red, green, blue, regno); - return 0; - } - - if (regno < 16) { - switch (fb->depth) { - case 15: - fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) | - ((green & 0xf800) >> 6) | - ((blue & 0xf800) >> 11); - break; - case 16: - fb->pseudo_palette[regno] = (red & 0xf800) | - ((green & 0xfc00) >> 5) | - ((blue & 0xf800) >> 11); - break; - case 24: - case 32: - fb->pseudo_palette[regno] = ((red & 0xff00) << 8) | - (green & 0xff00) | - ((blue & 0xff00) >> 8); - break; - } - } - } - return 0; -} - -static int intelfb_check_var(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct intelfb_par *par = info->par; - struct intel_framebuffer *intel_fb = par->intel_fb; - struct drm_framebuffer *fb = &intel_fb->base; - int depth; - - if (var->pixclock == -1 || !var->pixclock) - return -EINVAL; - - /* Need to resize the fb object !!! */ - if (var->xres > fb->width || var->yres > fb->height) { - DRM_ERROR("Requested width/height is greater than current fb object %dx%d > %dx%d\n",var->xres,var->yres,fb->width,fb->height); - DRM_ERROR("Need resizing code.\n"); - return -EINVAL; - } - - switch (var->bits_per_pixel) { - case 16: - depth = (var->green.length == 6) ? 16 : 15; - break; - case 32: - depth = (var->transp.length > 0) ? 32 : 24; - break; - default: - depth = var->bits_per_pixel; - break; - } - - switch (depth) { - case 8: - var->red.offset = 0; - var->green.offset = 0; - var->blue.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 15: - var->red.offset = 10; - var->green.offset = 5; - var->blue.offset = 0; - var->red.length = 5; - var->green.length = 5; - var->blue.length = 5; - var->transp.length = 1; - var->transp.offset = 15; - break; - case 16: - var->red.offset = 11; - var->green.offset = 5; - var->blue.offset = 0; - var->red.length = 5; - var->green.length = 6; - var->blue.length = 5; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 24: - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 32: - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 8; - var->transp.offset = 24; - break; - default: - return -EINVAL; - } - - return 0; -} - -/* this will let fbcon do the mode init */ -/* FIXME: take mode config lock? */ -static int intelfb_set_par(struct fb_info *info) -{ - struct intelfb_par *par = info->par; - struct drm_device *dev = par->dev; - struct fb_var_screeninfo *var = &info->var; - int i; - - DRM_DEBUG("%d %d\n", var->xres, var->pixclock); - - if (var->pixclock != -1) { - - DRM_ERROR("PIXEL CLOCK SET\n"); - return -EINVAL; - } else { - struct drm_crtc *crtc; - int ret; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - - for (i = 0; i < par->crtc_count; i++) - if (crtc->base.id == par->crtc_ids[i]) - break; - - if (i == par->crtc_count) - continue; - - if (crtc->fb == intel_crtc->mode_set.fb) { - mutex_lock(&dev->mode_config.mutex); - ret = crtc->funcs->set_config(&intel_crtc->mode_set); - mutex_unlock(&dev->mode_config.mutex); - if (ret) - return ret; - } - } - return 0; - } -} - -static int intelfb_pan_display(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct intelfb_par *par = info->par; - struct drm_device *dev = par->dev; - struct drm_mode_set *modeset; - struct drm_crtc *crtc; - struct intel_crtc *intel_crtc; - int ret = 0; - int i; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - for (i = 0; i < par->crtc_count; i++) - if (crtc->base.id == par->crtc_ids[i]) - break; - - if (i == par->crtc_count) - continue; - - intel_crtc = to_intel_crtc(crtc); - modeset = &intel_crtc->mode_set; - - modeset->x = var->xoffset; - modeset->y = var->yoffset; - - if (modeset->num_connectors) { - mutex_lock(&dev->mode_config.mutex); - ret = crtc->funcs->set_config(modeset); - mutex_unlock(&dev->mode_config.mutex); - if (!ret) { - info->var.xoffset = var->xoffset; - info->var.yoffset = var->yoffset; - } - } - } - - return ret; -} - -static void intelfb_on(struct fb_info *info) -{ - struct intelfb_par *par = info->par; - struct drm_device *dev = par->dev; - struct drm_crtc *crtc; - struct drm_encoder *encoder; - int i; - - /* - * For each CRTC in this fb, find all associated encoders - * and turn them off, then turn off the CRTC. - */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; - - for (i = 0; i < par->crtc_count; i++) - if (crtc->base.id == par->crtc_ids[i]) - break; - - crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); - - /* Found a CRTC on this fb, now find encoders */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc == crtc) { - struct drm_encoder_helper_funcs *encoder_funcs; - encoder_funcs = encoder->helper_private; - encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); - } - } - } -} - -static void intelfb_off(struct fb_info *info, int dpms_mode) -{ - struct intelfb_par *par = info->par; - struct drm_device *dev = par->dev; - struct drm_crtc *crtc; - struct drm_encoder *encoder; - int i; - - /* - * For each CRTC in this fb, find all associated encoders - * and turn them off, then turn off the CRTC. - */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; - - for (i = 0; i < par->crtc_count; i++) - if (crtc->base.id == par->crtc_ids[i]) - break; - - /* Found a CRTC on this fb, now find encoders */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc == crtc) { - struct drm_encoder_helper_funcs *encoder_funcs; - encoder_funcs = encoder->helper_private; - encoder_funcs->dpms(encoder, dpms_mode); - } - } - if (dpms_mode == DRM_MODE_DPMS_OFF) - crtc_funcs->dpms(crtc, dpms_mode); - } -} - -static int intelfb_blank(int blank, struct fb_info *info) -{ - switch (blank) { - case FB_BLANK_UNBLANK: - intelfb_on(info); - break; - case FB_BLANK_NORMAL: - intelfb_off(info, DRM_MODE_DPMS_STANDBY); - break; - case FB_BLANK_HSYNC_SUSPEND: - intelfb_off(info, DRM_MODE_DPMS_STANDBY); - break; - case FB_BLANK_VSYNC_SUSPEND: - intelfb_off(info, DRM_MODE_DPMS_SUSPEND); - break; - case FB_BLANK_POWERDOWN: - intelfb_off(info, DRM_MODE_DPMS_OFF); - break; - } - return 0; -} - static struct fb_ops intelfb_ops = { .owner = THIS_MODULE, - .fb_check_var = intelfb_check_var, - .fb_set_par = intelfb_set_par, - .fb_setcolreg = intelfb_setcolreg, + .fb_check_var = drm_fb_helper_check_var, + .fb_set_par = drm_fb_helper_set_par, + .fb_setcolreg = drm_fb_helper_setcolreg, .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit, - .fb_pan_display = intelfb_pan_display, - .fb_blank = intelfb_blank, + .fb_pan_display = drm_fb_helper_pan_display, + .fb_blank = drm_fb_helper_blank, }; +static struct drm_fb_helper_funcs intel_fb_helper_funcs = { + .gamma_set = intel_crtc_fb_gamma_set, +}; + + /** * Curretly it is assumed that the old framebuffer is reused. * @@ -412,25 +107,10 @@ int intelfb_resize(struct drm_device *dev, struct drm_crtc *crtc) } EXPORT_SYMBOL(intelfb_resize); -static struct drm_mode_set kernelfb_mode; - -static int intelfb_panic(struct notifier_block *n, unsigned long ununsed, - void *panic_str) -{ - DRM_ERROR("panic occurred, switching back to text console\n"); - - intelfb_restore(); - return 0; -} - -static struct notifier_block paniced = { - .notifier_call = intelfb_panic, -}; - static int intelfb_create(struct drm_device *dev, uint32_t fb_width, uint32_t fb_height, uint32_t surface_width, uint32_t surface_height, - struct intel_framebuffer **intel_fb_p) + struct drm_framebuffer **fb_p) { struct fb_info *info; struct intelfb_par *par; @@ -479,7 +159,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, list_add(&fb->filp_head, &dev->mode_config.fb_kernel_list); intel_fb = to_intel_framebuffer(fb); - *intel_fb_p = intel_fb; + *fb_p = fb; info = framebuffer_alloc(sizeof(struct intelfb_par), device); if (!info) { @@ -489,21 +169,19 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, par = info->par; + par->helper.funcs = &intel_fb_helper_funcs; + par->helper.dev = dev; + ret = drm_fb_helper_init_crtc_count(&par->helper, 2, + INTELFB_CONN_LIMIT); + if (ret) + goto out_unref; + strcpy(info->fix.id, "inteldrmfb"); - info->fix.type = FB_TYPE_PACKED_PIXELS; - info->fix.visual = FB_VISUAL_TRUECOLOR; - info->fix.type_aux = 0; - info->fix.xpanstep = 1; /* doing it in hw */ - info->fix.ypanstep = 1; /* doing it in hw */ - info->fix.ywrapstep = 0; - info->fix.accel = FB_ACCEL_I830; - info->fix.type_aux = 0; info->flags = FBINFO_DEFAULT; info->fbops = &intelfb_ops; - info->fix.line_length = fb->pitch; /* setup aperture base/size for vesafb takeover */ info->aperture_base = dev->mode_config.fb_base; @@ -527,18 +205,8 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, // memset(info->screen_base, 0, size); - info->pseudo_palette = fb->pseudo_palette; - info->var.xres_virtual = fb->width; - info->var.yres_virtual = fb->height; - info->var.bits_per_pixel = fb->bits_per_pixel; - info->var.xoffset = 0; - info->var.yoffset = 0; - info->var.activate = FB_ACTIVATE_NOW; - info->var.height = -1; - info->var.width = -1; - - info->var.xres = fb_width; - info->var.yres = fb_height; + drm_fb_helper_fill_fix(info, fb->depth); + drm_fb_helper_fill_var(info, fb, fb_width, fb_height); /* FIXME: we really shouldn't expose mmio space at all */ info->fix.mmio_start = pci_resource_start(dev->pdev, mmio_bar); @@ -550,64 +218,9 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, info->pixmap.flags = FB_PIXMAP_SYSTEM; info->pixmap.scan_align = 1; - switch(fb->depth) { - case 8: - info->var.red.offset = 0; - info->var.green.offset = 0; - info->var.blue.offset = 0; - info->var.red.length = 8; /* 8bit DAC */ - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 0; - info->var.transp.length = 0; - break; - case 15: - info->var.red.offset = 10; - info->var.green.offset = 5; - info->var.blue.offset = 0; - info->var.red.length = 5; - info->var.green.length = 5; - info->var.blue.length = 5; - info->var.transp.offset = 15; - info->var.transp.length = 1; - break; - case 16: - info->var.red.offset = 11; - info->var.green.offset = 5; - info->var.blue.offset = 0; - info->var.red.length = 5; - info->var.green.length = 6; - info->var.blue.length = 5; - info->var.transp.offset = 0; - break; - case 24: - info->var.red.offset = 16; - info->var.green.offset = 8; - info->var.blue.offset = 0; - info->var.red.length = 8; - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 0; - info->var.transp.length = 0; - break; - case 32: - info->var.red.offset = 16; - info->var.green.offset = 8; - info->var.blue.offset = 0; - info->var.red.length = 8; - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 24; - info->var.transp.length = 8; - break; - default: - break; - } - fb->fbdev = info; par->intel_fb = intel_fb; - par->dev = dev; /* To allow resizeing without swapping buffers */ DRM_DEBUG("allocated %dx%d fb: 0x%08x, bo %p\n", intel_fb->base.width, @@ -625,307 +238,12 @@ out: return ret; } -static int intelfb_multi_fb_probe_crtc(struct drm_device *dev, struct drm_crtc *crtc) -{ - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_framebuffer *intel_fb; - struct drm_framebuffer *fb; - struct drm_connector *connector; - struct fb_info *info; - struct intelfb_par *par; - struct drm_mode_set *modeset; - unsigned int width, height; - int new_fb = 0; - int ret, i, conn_count; - - if (!drm_helper_crtc_in_use(crtc)) - return 0; - - if (!crtc->desired_mode) - return 0; - - width = crtc->desired_mode->hdisplay; - height = crtc->desired_mode->vdisplay; - - /* is there an fb bound to this crtc already */ - if (!intel_crtc->mode_set.fb) { - ret = intelfb_create(dev, width, height, width, height, &intel_fb); - if (ret) - return -EINVAL; - new_fb = 1; - } else { - fb = intel_crtc->mode_set.fb; - intel_fb = to_intel_framebuffer(fb); - if ((intel_fb->base.width < width) || (intel_fb->base.height < height)) - return -EINVAL; - } - - info = intel_fb->base.fbdev; - par = info->par; - - modeset = &intel_crtc->mode_set; - modeset->fb = &intel_fb->base; - conn_count = 0; - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - if (connector->encoder) - if (connector->encoder->crtc == modeset->crtc) { - modeset->connectors[conn_count] = connector; - conn_count++; - if (conn_count > INTELFB_CONN_LIMIT) - BUG(); - } - } - - for (i = conn_count; i < INTELFB_CONN_LIMIT; i++) - modeset->connectors[i] = NULL; - - par->crtc_ids[0] = crtc->base.id; - - modeset->num_connectors = conn_count; - if (modeset->crtc->desired_mode) { - if (modeset->mode) - drm_mode_destroy(dev, modeset->mode); - modeset->mode = drm_mode_duplicate(dev, - modeset->crtc->desired_mode); - } - - par->crtc_count = 1; - - if (new_fb) { - info->var.pixclock = -1; - if (register_framebuffer(info) < 0) - return -EINVAL; - } else - intelfb_set_par(info); - - DRM_INFO("fb%d: %s frame buffer device\n", info->node, - info->fix.id); - - /* Switch back to kernel console on panic */ - kernelfb_mode = *modeset; - atomic_notifier_chain_register(&panic_notifier_list, &paniced); - DRM_DEBUG("registered panic notifier\n"); - - return 0; -} - -static int intelfb_multi_fb_probe(struct drm_device *dev) -{ - - struct drm_crtc *crtc; - int ret = 0; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - ret = intelfb_multi_fb_probe_crtc(dev, crtc); - if (ret) - return ret; - } - return ret; -} - -static int intelfb_single_fb_probe(struct drm_device *dev) -{ - struct drm_crtc *crtc; - struct drm_connector *connector; - unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1; - unsigned int surface_width = 0, surface_height = 0; - int new_fb = 0; - int crtc_count = 0; - int ret, i, conn_count = 0; - struct intel_framebuffer *intel_fb; - struct fb_info *info; - struct intelfb_par *par; - struct drm_mode_set *modeset = NULL; - - DRM_DEBUG("\n"); - - /* Get a count of crtcs now in use and new min/maxes width/heights */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - if (!drm_helper_crtc_in_use(crtc)) - continue; - - crtc_count++; - if (!crtc->desired_mode) - continue; - - /* Smallest mode determines console size... */ - if (crtc->desired_mode->hdisplay < fb_width) - fb_width = crtc->desired_mode->hdisplay; - - if (crtc->desired_mode->vdisplay < fb_height) - fb_height = crtc->desired_mode->vdisplay; - - /* ... but largest for memory allocation dimensions */ - if (crtc->desired_mode->hdisplay > surface_width) - surface_width = crtc->desired_mode->hdisplay; - - if (crtc->desired_mode->vdisplay > surface_height) - surface_height = crtc->desired_mode->vdisplay; - } - - if (crtc_count == 0 || fb_width == -1 || fb_height == -1) { - /* hmm everyone went away - assume VGA cable just fell out - and will come back later. */ - DRM_DEBUG("no CRTCs available?\n"); - return 0; - } - -//fail - /* Find the fb for our new config */ - if (list_empty(&dev->mode_config.fb_kernel_list)) { - DRM_DEBUG("creating new fb (console size %dx%d, " - "buffer size %dx%d)\n", fb_width, fb_height, - surface_width, surface_height); - ret = intelfb_create(dev, fb_width, fb_height, surface_width, - surface_height, &intel_fb); - if (ret) - return -EINVAL; - new_fb = 1; - } else { - struct drm_framebuffer *fb; - - fb = list_first_entry(&dev->mode_config.fb_kernel_list, - struct drm_framebuffer, filp_head); - intel_fb = to_intel_framebuffer(fb); - - /* if someone hotplugs something bigger than we have already - * allocated, we are pwned. As really we can't resize an - * fbdev that is in the wild currently due to fbdev not really - * being designed for the lower layers moving stuff around - * under it. - * - so in the grand style of things - punt. - */ - if ((fb->width < surface_width) || - (fb->height < surface_height)) { - DRM_ERROR("fb not large enough for console\n"); - return -EINVAL; - } - } -// fail - - info = intel_fb->base.fbdev; - par = info->par; - - crtc_count = 0; - /* - * For each CRTC, set up the connector list for the CRTC's mode - * set configuration. - */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - - modeset = &intel_crtc->mode_set; - modeset->fb = &intel_fb->base; - conn_count = 0; - list_for_each_entry(connector, &dev->mode_config.connector_list, - head) { - if (!connector->encoder) - continue; - - if(connector->encoder->crtc == modeset->crtc) { - modeset->connectors[conn_count++] = connector; - if (conn_count > INTELFB_CONN_LIMIT) - BUG(); - } - } - - /* Zero out remaining connector pointers */ - for (i = conn_count; i < INTELFB_CONN_LIMIT; i++) - modeset->connectors[i] = NULL; - - par->crtc_ids[crtc_count++] = crtc->base.id; - - modeset->num_connectors = conn_count; - if (modeset->crtc->desired_mode) { - if (modeset->mode) - drm_mode_destroy(dev, modeset->mode); - modeset->mode = drm_mode_duplicate(dev, - modeset->crtc->desired_mode); - } - } - par->crtc_count = crtc_count; - - if (new_fb) { - info->var.pixclock = -1; - if (register_framebuffer(info) < 0) - return -EINVAL; - } else - intelfb_set_par(info); - - DRM_INFO("fb%d: %s frame buffer device\n", info->node, - info->fix.id); - - /* Switch back to kernel console on panic */ - kernelfb_mode = *modeset; - atomic_notifier_chain_register(&panic_notifier_list, &paniced); - DRM_DEBUG("registered panic notifier\n"); - - return 0; -} - -/** - * intelfb_restore - restore the framebuffer console (kernel) config - * - * Restore's the kernel's fbcon mode, used for lastclose & panic paths. - */ -void intelfb_restore(void) -{ - int ret; - if ((ret = drm_crtc_helper_set_config(&kernelfb_mode)) != 0) { - DRM_ERROR("Failed to restore crtc configuration: %d\n", - ret); - } -} - -static void intelfb_restore_work_fn(struct work_struct *ignored) -{ - intelfb_restore(); -} -static DECLARE_WORK(intelfb_restore_work, intelfb_restore_work_fn); - -static void intelfb_sysrq(int dummy1, struct tty_struct *dummy3) -{ - schedule_work(&intelfb_restore_work); -} - -static struct sysrq_key_op sysrq_intelfb_restore_op = { - .handler = intelfb_sysrq, - .help_msg = "force-fb(V)", - .action_msg = "Restore framebuffer console", -}; - int intelfb_probe(struct drm_device *dev) { int ret; DRM_DEBUG("\n"); - - /* something has changed in the lower levels of hell - deal with it - here */ - - /* two modes : a) 1 fb to rule all crtcs. - b) one fb per crtc. - two actions 1) new connected device - 2) device removed. - case a/1 : if the fb surface isn't big enough - resize the surface fb. - if the fb size isn't big enough - resize fb into surface. - if everything big enough configure the new crtc/etc. - case a/2 : undo the configuration - possibly resize down the fb to fit the new configuration. - case b/1 : see if it is on a new crtc - setup a new fb and add it. - case b/2 : teardown the new fb. - */ - - /* mode a first */ - /* search for an fb */ - if (i915_fbpercrtc == 1) { - ret = intelfb_multi_fb_probe(dev); - } else { - ret = intelfb_single_fb_probe(dev); - } - - register_sysrq_key('v', &sysrq_intelfb_restore_op); - + ret = drm_fb_helper_single_fb_probe(dev, intelfb_create); return ret; } EXPORT_SYMBOL(intelfb_probe); @@ -940,13 +258,14 @@ int intelfb_remove(struct drm_device *dev, struct drm_framebuffer *fb) info = fb->fbdev; if (info) { + struct intelfb_par *par = info->par; unregister_framebuffer(info); iounmap(info->screen_base); + if (info->par) + drm_fb_helper_free(&par->helper); framebuffer_release(info); } - atomic_notifier_chain_unregister(&panic_notifier_list, &paniced); - memset(&kernelfb_mode, 0, sizeof(struct drm_mode_set)); return 0; } EXPORT_SYMBOL(intelfb_remove); diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index a8fa1bb..af03560 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -158,9 +158,6 @@ static void radeon_crtc_destroy(struct drm_crtc *crtc) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); - if (radeon_crtc->mode_set.mode) { - drm_mode_destroy(crtc->dev, radeon_crtc->mode_set.mode); - } drm_crtc_cleanup(crtc); kfree(radeon_crtc); } @@ -189,9 +186,11 @@ static void radeon_crtc_init(struct drm_device *dev, int index) radeon_crtc->crtc_id = index; rdev->mode_info.crtcs[index] = radeon_crtc; +#if 0 radeon_crtc->mode_set.crtc = &radeon_crtc->base; radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); radeon_crtc->mode_set.num_connectors = 0; +#endif for (i = 0; i < 256; i++) { radeon_crtc->lut_r[i] = i << 2; diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index ec383ed..ebb5895 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -28,15 +28,7 @@ */ #include -#include -#include -#include -#include -#include -#include -#include #include -#include #include "drmP.h" #include "drm.h" @@ -45,375 +37,86 @@ #include "radeon_drm.h" #include "radeon.h" +#include "drm_fb_helper.h" + struct radeon_fb_device { - struct radeon_device *rdev; - struct drm_display_mode *mode; + struct drm_fb_helper helper; struct radeon_framebuffer *rfb; - int crtc_count; - /* crtc currently bound to this */ - uint32_t crtc_ids[2]; + struct radeon_device *rdev; }; -static int radeonfb_setcolreg(unsigned regno, - unsigned red, - unsigned green, - unsigned blue, - unsigned transp, - struct fb_info *info) -{ - struct radeon_fb_device *rfbdev = info->par; - struct drm_device *dev = rfbdev->rdev->ddev; - struct drm_crtc *crtc; - int i; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); - struct drm_mode_set *modeset = &radeon_crtc->mode_set; - struct drm_framebuffer *fb = modeset->fb; - - for (i = 0; i < rfbdev->crtc_count; i++) { - if (crtc->base.id == rfbdev->crtc_ids[i]) { - break; - } - } - if (i == rfbdev->crtc_count) { - continue; - } - if (regno > 255) { - return 1; - } - if (fb->depth == 8) { - radeon_crtc_fb_gamma_set(crtc, red, green, blue, regno); - return 0; - } - - if (regno < 16) { - switch (fb->depth) { - case 15: - fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) | - ((green & 0xf800) >> 6) | - ((blue & 0xf800) >> 11); - break; - case 16: - fb->pseudo_palette[regno] = (red & 0xf800) | - ((green & 0xfc00) >> 5) | - ((blue & 0xf800) >> 11); - break; - case 24: - case 32: - fb->pseudo_palette[regno] = - (((red >> 8) & 0xff) << info->var.red.offset) | - (((green >> 8) & 0xff) << info->var.green.offset) | - (((blue >> 8) & 0xff) << info->var.blue.offset); - break; - } - } - } - return 0; -} - -static int radeonfb_check_var(struct fb_var_screeninfo *var, - struct fb_info *info) +static int radeon_fb_check_var(struct fb_var_screeninfo *var, + struct fb_info *info) { - struct radeon_fb_device *rfbdev = info->par; - struct radeon_framebuffer *rfb = rfbdev->rfb; - struct drm_framebuffer *fb = &rfb->base; - int depth; - - if (var->pixclock == -1 || !var->pixclock) { - return -EINVAL; - } - /* Need to resize the fb object !!! */ - if (var->xres > fb->width || var->yres > fb->height) { - DRM_ERROR("Requested width/height is greater than current fb " - "object %dx%d > %dx%d\n", var->xres, var->yres, - fb->width, fb->height); - DRM_ERROR("Need resizing code.\n"); - return -EINVAL; - } - - switch (var->bits_per_pixel) { - case 16: - depth = (var->green.length == 6) ? 16 : 15; - break; - case 32: - depth = (var->transp.length > 0) ? 32 : 24; - break; - default: - depth = var->bits_per_pixel; - break; - } - - switch (depth) { - case 8: - var->red.offset = 0; - var->green.offset = 0; - var->blue.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 0; - var->transp.offset = 0; - break; -#ifdef __LITTLE_ENDIAN - case 15: - var->red.offset = 10; - var->green.offset = 5; - var->blue.offset = 0; - var->red.length = 5; - var->green.length = 5; - var->blue.length = 5; - var->transp.length = 1; - var->transp.offset = 15; - break; - case 16: - var->red.offset = 11; - var->green.offset = 5; - var->blue.offset = 0; - var->red.length = 5; - var->green.length = 6; - var->blue.length = 5; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 24: - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 32: - var->red.offset = 16; - var->green.offset = 8; - var->blue.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 8; - var->transp.offset = 24; - break; -#else - case 24: - var->red.offset = 8; - var->green.offset = 16; - var->blue.offset = 24; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 0; - var->transp.offset = 0; - break; - case 32: - var->red.offset = 8; - var->green.offset = 16; - var->blue.offset = 24; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 8; - var->transp.offset = 0; - break; -#endif - default: - return -EINVAL; - } - return 0; -} - -/* this will let fbcon do the mode init */ -static int radeonfb_set_par(struct fb_info *info) -{ - struct radeon_fb_device *rfbdev = info->par; - struct drm_device *dev = rfbdev->rdev->ddev; - struct fb_var_screeninfo *var = &info->var; - struct drm_crtc *crtc; int ret; - int i; - - if (var->pixclock != -1) { - DRM_ERROR("PIXEL CLCOK SET\n"); - return -EINVAL; - } - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); - - for (i = 0; i < rfbdev->crtc_count; i++) { - if (crtc->base.id == rfbdev->crtc_ids[i]) { - break; - } - } - if (i == rfbdev->crtc_count) { - continue; - } - if (crtc->fb == radeon_crtc->mode_set.fb) { - mutex_lock(&dev->mode_config.mutex); - ret = crtc->funcs->set_config(&radeon_crtc->mode_set); - mutex_unlock(&dev->mode_config.mutex); - if (ret) { - return ret; - } - } - } - return 0; -} - -static int radeonfb_pan_display(struct fb_var_screeninfo *var, - struct fb_info *info) -{ - struct radeon_fb_device *rfbdev = info->par; - struct drm_device *dev = rfbdev->rdev->ddev; - struct drm_mode_set *modeset; - struct drm_crtc *crtc; - struct radeon_crtc *radeon_crtc; - int ret = 0; - int i; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - for (i = 0; i < rfbdev->crtc_count; i++) { - if (crtc->base.id == rfbdev->crtc_ids[i]) { - break; - } - } - - if (i == rfbdev->crtc_count) { - continue; - } - - radeon_crtc = to_radeon_crtc(crtc); - modeset = &radeon_crtc->mode_set; - - modeset->x = var->xoffset; - modeset->y = var->yoffset; - - if (modeset->num_connectors) { - mutex_lock(&dev->mode_config.mutex); - ret = crtc->funcs->set_config(modeset); - mutex_unlock(&dev->mode_config.mutex); - if (!ret) { - info->var.xoffset = var->xoffset; - info->var.yoffset = var->yoffset; - } + ret = drm_fb_helper_check_var(var, info); + if (ret) + return ret; + + /* big endian override for radeon endian workaround */ +#ifdef __BIG_ENDIAN + { + int depth; + switch (var->bits_per_pixel) { + case 16: + depth = (var->green.length == 6) ? 16 : 15; + break; + case 32: + depth = (var->transp.length > 0) ? 32 : 24; + break; + default: + depth = var->bits_per_pixel; + break; } - } - return ret; -} - -static void radeonfb_on(struct fb_info *info) -{ - struct radeon_fb_device *rfbdev = info->par; - struct drm_device *dev = rfbdev->rdev->ddev; - struct drm_crtc *crtc; - struct drm_encoder *encoder; - int i; - - /* - * For each CRTC in this fb, find all associated encoders - * and turn them off, then turn off the CRTC. - */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; - - for (i = 0; i < rfbdev->crtc_count; i++) { - if (crtc->base.id == rfbdev->crtc_ids[i]) { - break; - } - } - - mutex_lock(&dev->mode_config.mutex); - crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); - mutex_unlock(&dev->mode_config.mutex); - - /* Found a CRTC on this fb, now find encoders */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc == crtc) { - struct drm_encoder_helper_funcs *encoder_funcs; - - encoder_funcs = encoder->helper_private; - mutex_lock(&dev->mode_config.mutex); - encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); - mutex_unlock(&dev->mode_config.mutex); - } - } - } -} - -static void radeonfb_off(struct fb_info *info, int dpms_mode) -{ - struct radeon_fb_device *rfbdev = info->par; - struct drm_device *dev = rfbdev->rdev->ddev; - struct drm_crtc *crtc; - struct drm_encoder *encoder; - int i; - - /* - * For each CRTC in this fb, find all associated encoders - * and turn them off, then turn off the CRTC. - */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; - - for (i = 0; i < rfbdev->crtc_count; i++) { - if (crtc->base.id == rfbdev->crtc_ids[i]) { - break; - } - } - - /* Found a CRTC on this fb, now find encoders */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc == crtc) { - struct drm_encoder_helper_funcs *encoder_funcs; - - encoder_funcs = encoder->helper_private; - mutex_lock(&dev->mode_config.mutex); - encoder_funcs->dpms(encoder, dpms_mode); - mutex_unlock(&dev->mode_config.mutex); - } - } - if (dpms_mode == DRM_MODE_DPMS_OFF) { - mutex_lock(&dev->mode_config.mutex); - crtc_funcs->dpms(crtc, dpms_mode); - mutex_unlock(&dev->mode_config.mutex); + switch (depth) { + case 8: + var->red.offset = 0; + var->green.offset = 0; + var->blue.offset = 0; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.length = 0; + var->transp.offset = 0; + break; + case 24: + var->red.offset = 8; + var->green.offset = 16; + var->blue.offset = 24; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.length = 0; + var->transp.offset = 0; + break; + case 32: + var->red.offset = 8; + var->green.offset = 16; + var->blue.offset = 24; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.length = 8; + var->transp.offset = 0; + break; + default: + return -EINVAL; } } -} - -int radeonfb_blank(int blank, struct fb_info *info) -{ - switch (blank) { - case FB_BLANK_UNBLANK: - radeonfb_on(info); - break; - case FB_BLANK_NORMAL: - radeonfb_off(info, DRM_MODE_DPMS_STANDBY); - break; - case FB_BLANK_HSYNC_SUSPEND: - radeonfb_off(info, DRM_MODE_DPMS_STANDBY); - break; - case FB_BLANK_VSYNC_SUSPEND: - radeonfb_off(info, DRM_MODE_DPMS_SUSPEND); - break; - case FB_BLANK_POWERDOWN: - radeonfb_off(info, DRM_MODE_DPMS_OFF); - break; - } +#endif return 0; } static struct fb_ops radeonfb_ops = { .owner = THIS_MODULE, - .fb_check_var = radeonfb_check_var, - .fb_set_par = radeonfb_set_par, - .fb_setcolreg = radeonfb_setcolreg, + .fb_check_var = radeon_fb_check_var, + .fb_set_par = drm_fb_helper_set_par, + .fb_setcolreg = drm_fb_helper_setcolreg, .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit, - .fb_pan_display = radeonfb_pan_display, - .fb_blank = radeonfb_blank, + .fb_pan_display = drm_fb_helper_pan_display, + .fb_blank = drm_fb_helper_blank, }; /** @@ -456,21 +159,6 @@ int radeonfb_resize(struct drm_device *dev, struct drm_crtc *crtc) } EXPORT_SYMBOL(radeonfb_resize); -static struct drm_mode_set panic_mode; - -int radeonfb_panic(struct notifier_block *n, unsigned long ununsed, - void *panic_str) -{ - DRM_ERROR("panic occurred, switching back to text console\n"); - drm_crtc_helper_set_config(&panic_mode); - return 0; -} -EXPORT_SYMBOL(radeonfb_panic); - -static struct notifier_block paniced = { - .notifier_call = radeonfb_panic, -}; - static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) { int aligned = width; @@ -495,11 +183,16 @@ static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bo return aligned; } -int radeonfb_create(struct radeon_device *rdev, +static struct drm_fb_helper_funcs radeon_fb_helper_funcs = { + .gamma_set = radeon_crtc_fb_gamma_set, +}; + +int radeonfb_create(struct drm_device *dev, uint32_t fb_width, uint32_t fb_height, uint32_t surface_width, uint32_t surface_height, - struct radeon_framebuffer **rfb_p) + struct drm_framebuffer **fb_p) { + struct radeon_device *rdev = dev->dev_private; struct fb_info *info; struct radeon_fb_device *rfbdev; struct drm_framebuffer *fb = NULL; @@ -554,8 +247,8 @@ int radeonfb_create(struct radeon_device *rdev, list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list); + *fb_p = fb; rfb = to_radeon_framebuffer(fb); - *rfb_p = rfb; rdev->fbdev_rfb = rfb; rdev->fbdev_robj = robj; @@ -564,7 +257,14 @@ int radeonfb_create(struct radeon_device *rdev, ret = -ENOMEM; goto out_unref; } + rfbdev = info->par; + rfbdev->helper.funcs = &radeon_fb_helper_funcs; + rfbdev->helper.dev = dev; + ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, 2, + RADEONFB_CONN_LIMIT); + if (ret) + goto out_unref; if (fb_tiled) radeon_object_check_tiling(robj, 0, 0); @@ -577,33 +277,19 @@ int radeonfb_create(struct radeon_device *rdev, memset_io(fbptr, 0, aligned_size); strcpy(info->fix.id, "radeondrmfb"); - info->fix.type = FB_TYPE_PACKED_PIXELS; - info->fix.visual = FB_VISUAL_TRUECOLOR; - info->fix.type_aux = 0; - info->fix.xpanstep = 1; /* doing it in hw */ - info->fix.ypanstep = 1; /* doing it in hw */ - info->fix.ywrapstep = 0; - info->fix.accel = FB_ACCEL_NONE; - info->fix.type_aux = 0; + + drm_fb_helper_fill_fix(info, fb->pitch); + info->flags = FBINFO_DEFAULT; info->fbops = &radeonfb_ops; - info->fix.line_length = fb->pitch; + tmp = fb_gpuaddr - rdev->mc.vram_location; info->fix.smem_start = rdev->mc.aper_base + tmp; info->fix.smem_len = size; info->screen_base = fbptr; info->screen_size = size; - info->pseudo_palette = fb->pseudo_palette; - info->var.xres_virtual = fb->width; - info->var.yres_virtual = fb->height; - info->var.bits_per_pixel = fb->bits_per_pixel; - info->var.xoffset = 0; - info->var.yoffset = 0; - info->var.activate = FB_ACTIVATE_NOW; - info->var.height = -1; - info->var.width = -1; - info->var.xres = fb_width; - info->var.yres = fb_height; + + drm_fb_helper_fill_var(info, fb, fb_width, fb_height); /* setup aperture base/size for vesafb takeover */ info->aperture_base = rdev->ddev->mode_config.fb_base; @@ -626,6 +312,9 @@ int radeonfb_create(struct radeon_device *rdev, DRM_INFO("fb depth is %d\n", fb->depth); DRM_INFO(" pitch is %d\n", fb->pitch); +#ifdef __BIG_ENDIAN + /* fill var sets defaults for this stuff - override + on big endian */ switch (fb->depth) { case 8: info->var.red.offset = 0; @@ -637,47 +326,6 @@ int radeonfb_create(struct radeon_device *rdev, info->var.transp.offset = 0; info->var.transp.length = 0; break; -#ifdef __LITTLE_ENDIAN - case 15: - info->var.red.offset = 10; - info->var.green.offset = 5; - info->var.blue.offset = 0; - info->var.red.length = 5; - info->var.green.length = 5; - info->var.blue.length = 5; - info->var.transp.offset = 15; - info->var.transp.length = 1; - break; - case 16: - info->var.red.offset = 11; - info->var.green.offset = 5; - info->var.blue.offset = 0; - info->var.red.length = 5; - info->var.green.length = 6; - info->var.blue.length = 5; - info->var.transp.offset = 0; - break; - case 24: - info->var.red.offset = 16; - info->var.green.offset = 8; - info->var.blue.offset = 0; - info->var.red.length = 8; - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 0; - info->var.transp.length = 0; - break; - case 32: - info->var.red.offset = 16; - info->var.green.offset = 8; - info->var.blue.offset = 0; - info->var.red.length = 8; - info->var.green.length = 8; - info->var.blue.length = 8; - info->var.transp.offset = 24; - info->var.transp.length = 8; - break; -#else case 24: info->var.red.offset = 8; info->var.green.offset = 16; @@ -699,9 +347,9 @@ int radeonfb_create(struct radeon_device *rdev, info->var.transp.length = 8; break; default: -#endif break; } +#endif fb->fbdev = info; rfbdev->rfb = rfb; @@ -726,145 +374,10 @@ out: return ret; } -static int radeonfb_single_fb_probe(struct radeon_device *rdev) -{ - struct drm_crtc *crtc; - struct drm_connector *connector; - unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1; - unsigned int surface_width = 0, surface_height = 0; - int new_fb = 0; - int crtc_count = 0; - int ret, i, conn_count = 0; - struct radeon_framebuffer *rfb; - struct fb_info *info; - struct radeon_fb_device *rfbdev; - struct drm_mode_set *modeset = NULL; - - /* first up get a count of crtcs now in use and new min/maxes width/heights */ - list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) { - if (drm_helper_crtc_in_use(crtc)) { - if (crtc->desired_mode) { - if (crtc->desired_mode->hdisplay < fb_width) - fb_width = crtc->desired_mode->hdisplay; - - if (crtc->desired_mode->vdisplay < fb_height) - fb_height = crtc->desired_mode->vdisplay; - - if (crtc->desired_mode->hdisplay > surface_width) - surface_width = crtc->desired_mode->hdisplay; - - if (crtc->desired_mode->vdisplay > surface_height) - surface_height = crtc->desired_mode->vdisplay; - } - crtc_count++; - } - } - - if (crtc_count == 0 || fb_width == -1 || fb_height == -1) { - /* hmm everyone went away - assume VGA cable just fell out - and will come back later. */ - return 0; - } - - /* do we have an fb already? */ - if (list_empty(&rdev->ddev->mode_config.fb_kernel_list)) { - /* create an fb if we don't have one */ - ret = radeonfb_create(rdev, fb_width, fb_height, surface_width, surface_height, &rfb); - if (ret) { - return -EINVAL; - } - new_fb = 1; - } else { - struct drm_framebuffer *fb; - fb = list_first_entry(&rdev->ddev->mode_config.fb_kernel_list, struct drm_framebuffer, filp_head); - rfb = to_radeon_framebuffer(fb); - - /* if someone hotplugs something bigger than we have already allocated, we are pwned. - As really we can't resize an fbdev that is in the wild currently due to fbdev - not really being designed for the lower layers moving stuff around under it. - - so in the grand style of things - punt. */ - if ((fb->width < surface_width) || (fb->height < surface_height)) { - DRM_ERROR("Framebuffer not large enough to scale console onto.\n"); - return -EINVAL; - } - } - - info = rfb->base.fbdev; - rdev->fbdev_info = info; - rfbdev = info->par; - - crtc_count = 0; - /* okay we need to setup new connector sets in the crtcs */ - list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) { - struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); - modeset = &radeon_crtc->mode_set; - modeset->fb = &rfb->base; - conn_count = 0; - list_for_each_entry(connector, &rdev->ddev->mode_config.connector_list, head) { - if (connector->encoder) - if (connector->encoder->crtc == modeset->crtc) { - modeset->connectors[conn_count] = connector; - conn_count++; - if (conn_count > RADEONFB_CONN_LIMIT) - BUG(); - } - } - - for (i = conn_count; i < RADEONFB_CONN_LIMIT; i++) - modeset->connectors[i] = NULL; - - - rfbdev->crtc_ids[crtc_count++] = crtc->base.id; - - modeset->num_connectors = conn_count; - if (modeset->crtc->desired_mode) { - if (modeset->mode) { - drm_mode_destroy(rdev->ddev, modeset->mode); - } - modeset->mode = drm_mode_duplicate(rdev->ddev, - modeset->crtc->desired_mode); - } - } - rfbdev->crtc_count = crtc_count; - - if (new_fb) { - info->var.pixclock = -1; - if (register_framebuffer(info) < 0) - return -EINVAL; - } else { - radeonfb_set_par(info); - } - printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, - info->fix.id); - - /* Switch back to kernel console on panic */ - panic_mode = *modeset; - atomic_notifier_chain_register(&panic_notifier_list, &paniced); - printk(KERN_INFO "registered panic notifier\n"); - - return 0; -} - int radeonfb_probe(struct drm_device *dev) { int ret; - - /* something has changed in the lower levels of hell - deal with it - here */ - - /* two modes : a) 1 fb to rule all crtcs. - b) one fb per crtc. - two actions 1) new connected device - 2) device removed. - case a/1 : if the fb surface isn't big enough - resize the surface fb. - if the fb size isn't big enough - resize fb into surface. - if everything big enough configure the new crtc/etc. - case a/2 : undo the configuration - possibly resize down the fb to fit the new configuration. - case b/1 : see if it is on a new crtc - setup a new fb and add it. - case b/2 : teardown the new fb. - */ - ret = radeonfb_single_fb_probe(dev->dev_private); + ret = drm_fb_helper_single_fb_probe(dev, &radeonfb_create); return ret; } EXPORT_SYMBOL(radeonfb_probe); @@ -880,16 +393,17 @@ int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb) } info = fb->fbdev; if (info) { + struct radeon_fb_device *rfbdev = info->par; robj = rfb->obj->driver_private; unregister_framebuffer(info); radeon_object_kunmap(robj); radeon_object_unpin(robj); + drm_fb_helper_free(&rfbdev->helper); framebuffer_release(info); } printk(KERN_INFO "unregistered panic notifier\n"); - atomic_notifier_chain_unregister(&panic_notifier_list, &paniced); - memset(&panic_mode, 0, sizeof(struct drm_mode_set)); + return 0; } EXPORT_SYMBOL(radeonfb_remove); diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 3b09a1f..20e9509 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -195,8 +195,6 @@ struct radeon_crtc { bool enabled; bool can_tile; uint32_t crtc_offset; - struct radeon_framebuffer *fbdev_fb; - struct drm_mode_set mode_set; struct drm_gem_object *cursor_bo; uint64_t cursor_addr; int cursor_width; diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index db92a83..b0427a7 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -259,6 +259,8 @@ struct drm_framebuffer { void *fbdev; u32 pseudo_palette[17]; struct list_head filp_head; + /* if you are using the helper */ + void *helper_private; }; struct drm_property_blob { diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h new file mode 100644 index 0000000..88fffbd --- /dev/null +++ b/include/drm/drm_fb_helper.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ +#ifndef DRM_FB_HELPER_H +#define DRM_FB_HELPER_H + +struct drm_fb_helper_crtc { + uint32_t crtc_id; + struct drm_mode_set mode_set; +}; + +struct drm_fb_helper_funcs { + void (*gamma_set)(struct drm_crtc *crtc, u16 red, u16 green, + u16 blue, int regno); +}; + +struct drm_fb_helper { + struct drm_framebuffer *fb; + struct drm_device *dev; + struct drm_display_mode *mode; + int crtc_count; + struct drm_fb_helper_crtc *crtc_info; + struct drm_fb_helper_funcs *funcs; + int conn_limit; + struct list_head kernel_fb_list; +}; + +int drm_fb_helper_single_fb_probe(struct drm_device *dev, + int (*fb_create)(struct drm_device *dev, + uint32_t fb_width, + uint32_t fb_height, + uint32_t surface_width, + uint32_t surface_height, + struct drm_framebuffer **fb_ptr)); +int drm_fb_helper_init_crtc_count(struct drm_fb_helper *helper, int crtc_count, + int max_conn); +void drm_fb_helper_free(struct drm_fb_helper *helper); +int drm_fb_helper_blank(int blank, struct fb_info *info); +int drm_fb_helper_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info); +int drm_fb_helper_set_par(struct fb_info *info); +int drm_fb_helper_check_var(struct fb_var_screeninfo *var, + struct fb_info *info); +int drm_fb_helper_setcolreg(unsigned regno, + unsigned red, + unsigned green, + unsigned blue, + unsigned transp, + struct fb_info *info); + +void drm_fb_helper_restore(void); +void drm_fb_helper_fill_var(struct fb_info *info, struct drm_framebuffer *fb, + uint32_t fb_width, uint32_t fb_height); +void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch); + +#endif -- cgit v0.10.2 From 882f0219518196a94cd2772004e87b178467139a Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Wed, 26 Aug 2009 18:20:49 +0800 Subject: drm/kms: Parse the detailed time info in CEA-EDID Sometimes we can obtain the EDID with multiple blocks from the display device. For example: HDMI monitor. When the CEA-EDID block is detected, we should also parse the detailed timing info from it. Otherwise we will lose some modes for the display device. The first step is check whether the CEA EDID block is found. If it exists, it will skip the CEA-data block and parse the detailed timing info. Signed-off-by: Zhao Yakui Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index a1cab5d..e4f1cb5 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -60,6 +60,8 @@ #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) /* use +hsync +vsync for detailed mode */ #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) +/* define the number of Extension EDID block */ +#define MAX_EDID_EXT_NUM 4 #define LEVEL_DMT 0 #define LEVEL_GTF 1 @@ -597,6 +599,122 @@ static int add_detailed_info(struct drm_connector *connector, return modes; } +/** + * add_detailed_mode_eedid - get detailed mode info from addtional timing + * EDID block + * @connector: attached connector + * @edid: EDID block to scan(It is only to get addtional timing EDID block) + * @quirks: quirks to apply + * + * Some of the detailed timing sections may contain mode information. Grab + * it and add it to the list. + */ +static int add_detailed_info_eedid(struct drm_connector *connector, + struct edid *edid, u32 quirks) +{ + struct drm_device *dev = connector->dev; + int i, j, modes = 0; + char *edid_ext = NULL; + struct detailed_timing *timing; + struct detailed_non_pixel *data; + struct drm_display_mode *newmode; + int edid_ext_num; + int start_offset, end_offset; + int timing_level; + + if (edid->version == 1 && edid->revision < 3) { + /* If the EDID version is less than 1.3, there is no + * extension EDID. + */ + return 0; + } + if (!edid->extensions) { + /* if there is no extension EDID, it is unnecessary to + * parse the E-EDID to get detailed info + */ + return 0; + } + + /* Chose real EDID extension number */ + edid_ext_num = edid->extensions > MAX_EDID_EXT_NUM ? + MAX_EDID_EXT_NUM : edid->extensions; + + /* Find CEA extension */ + for (i = 0; i < edid_ext_num; i++) { + edid_ext = (char *)edid + EDID_LENGTH * (i + 1); + /* This block is CEA extension */ + if (edid_ext[0] == 0x02) + break; + } + + if (i == edid_ext_num) { + /* if there is no additional timing EDID block, return */ + return 0; + } + + /* Get the start offset of detailed timing block */ + start_offset = edid_ext[2]; + if (start_offset == 0) { + /* If the start_offset is zero, it means that neither detailed + * info nor data block exist. In such case it is also + * unnecessary to parse the detailed timing info. + */ + return 0; + } + + timing_level = standard_timing_level(edid); + end_offset = EDID_LENGTH; + end_offset -= sizeof(struct detailed_timing); + for (i = start_offset; i < end_offset; + i += sizeof(struct detailed_timing)) { + timing = (struct detailed_timing *)(edid_ext + i); + data = &timing->data.other_data; + /* Detailed mode timing */ + if (timing->pixel_clock) { + newmode = drm_mode_detailed(dev, edid, timing, quirks); + if (!newmode) + continue; + + drm_mode_probed_add(connector, newmode); + + modes++; + continue; + } + + /* Other timing or info */ + switch (data->type) { + case EDID_DETAIL_MONITOR_SERIAL: + break; + case EDID_DETAIL_MONITOR_STRING: + break; + case EDID_DETAIL_MONITOR_RANGE: + /* Get monitor range data */ + break; + case EDID_DETAIL_MONITOR_NAME: + break; + case EDID_DETAIL_MONITOR_CPDATA: + break; + case EDID_DETAIL_STD_MODES: + /* Five modes per detailed section */ + for (j = 0; j < 5; i++) { + struct std_timing *std; + struct drm_display_mode *newmode; + + std = &data->data.timings[j]; + newmode = drm_mode_std(dev, std, timing_level); + if (newmode) { + drm_mode_probed_add(connector, newmode); + modes++; + } + } + break; + default: + break; + } + } + + return modes; +} #define DDC_ADDR 0x50 /** @@ -656,7 +774,6 @@ end: return ret; } -#define MAX_EDID_EXT_NUM 4 /** * drm_get_edid - get EDID data, if available * @connector: connector we're probing @@ -809,6 +926,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) num_modes += add_established_modes(connector, edid); num_modes += add_standard_modes(connector, edid); num_modes += add_detailed_info(connector, edid, quirks); + num_modes += add_detailed_info_eedid(connector, edid, quirks); if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) edid_fixup_preferred(connector, quirks); -- cgit v0.10.2 From 3b51096f95633e6ab47675984e8e38fc37b09eeb Mon Sep 17 00:00:00 2001 From: Alexey Dobriyan Date: Fri, 28 Aug 2009 22:58:07 +0400 Subject: drm: use proc_create_data() airlied: fixup race against drm info by filling out tmp before adding it to proc. Signed-off-by: Alexey Dobriyan Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_proc.c b/drivers/gpu/drm/drm_proc.c index dc967af..d379c4f 100644 --- a/drivers/gpu/drm/drm_proc.c +++ b/drivers/gpu/drm/drm_proc.c @@ -110,20 +110,21 @@ int drm_proc_create_files(struct drm_info_list *files, int count, ret = -1; goto fail; } - ent = create_proc_entry(files[i].name, S_IFREG | S_IRUGO, root); + tmp->minor = minor; + tmp->info_ent = &files[i]; + list_add(&tmp->list, &minor->proc_nodes.list); + + ent = proc_create_data(files[i].name, S_IRUGO, root, + &drm_proc_fops, tmp); if (!ent) { DRM_ERROR("Cannot create /proc/dri/%s/%s\n", name, files[i].name); + list_del(&tmp->list); kfree(tmp); ret = -1; goto fail; } - ent->proc_fops = &drm_proc_fops; - ent->data = tmp; - tmp->minor = minor; - tmp->info_ent = &files[i]; - list_add(&(tmp->list), &(minor->proc_nodes.list)); } return 0; -- cgit v0.10.2 From 3420e74262a7d6496d0ac433d6f61c9972f015f6 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 31 Aug 2009 10:33:29 +1000 Subject: drm: fix two issues with fb consolidation. Set accel to none, we really don't want anyone thinking fb is an accel interface. Pass pitch not depth to function for intel. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index d6ffea7..41086e9 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -616,7 +616,7 @@ void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch) info->fix.xpanstep = 1; /* doing it in hw */ info->fix.ypanstep = 1; /* doing it in hw */ info->fix.ywrapstep = 0; - info->fix.accel = FB_ACCEL_I830; + info->fix.accel = FB_ACCEL_NONE; info->fix.type_aux = 0; info->fix.line_length = pitch; diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c index 3041530..7ba4a23 100644 --- a/drivers/gpu/drm/i915/intel_fb.c +++ b/drivers/gpu/drm/i915/intel_fb.c @@ -205,7 +205,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, // memset(info->screen_base, 0, size); - drm_fb_helper_fill_fix(info, fb->depth); + drm_fb_helper_fill_fix(info, fb->pitch); drm_fb_helper_fill_var(info, fb, fb_width, fb_height); /* FIXME: we really shouldn't expose mmio space at all */ -- cgit v0.10.2 From adb2fe0277607d50f4e9ef06e1d180051a609c25 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Mon, 31 Aug 2009 15:24:23 +1000 Subject: intel-iommu: include linux/dmi.h to use dmi_ routines This file needs to include linux/dmi.h directly rather than relying on it being pulled in from elsewhere. Signed-off-by: Stephen Rothwell Signed-off-by: David Woodhouse diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index d36fa80..2ec5899 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include "pci.h" -- cgit v0.10.2 From d8fb91e8344ff11381fc47d43e0b234065be4bd0 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 26 Jun 2009 08:14:36 +0200 Subject: CRIS: add pgprot_noncached On CRIS, the high address bit controls caching, which means that we can add a pgprot_noncached() macro that sets this bit in the address. Signed-off-by: Arnd Bergmann Acked-by: Jesper Nilsson diff --git a/arch/cris/include/arch-v10/arch/mmu.h b/arch/cris/include/arch-v10/arch/mmu.h index df84f17..e829e5a 100644 --- a/arch/cris/include/arch-v10/arch/mmu.h +++ b/arch/cris/include/arch-v10/arch/mmu.h @@ -33,10 +33,10 @@ typedef struct /* CRIS PTE bits (see R_TLB_LO in the register description) * - * Bit: 31-13 12-------4 3 2 1 0 - * ________________________________________________ - * | pfn | reserved | global | valid | kernel | we | - * |_____|__________|________|_______|________|_____| + * Bit: 31 30-13 12-------4 3 2 1 0 + * _______________________________________________________ + * | cache |pfn | reserved | global | valid | kernel | we | + * |_______|____|__________|________|_______|________|_____| * * (pfn = physical frame number) */ @@ -53,6 +53,7 @@ typedef struct #define _PAGE_VALID (1<<2) /* page is valid */ #define _PAGE_SILENT_READ (1<<2) /* synonym */ #define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */ +#define _PAGE_NO_CACHE (1<<31) /* part of the uncached memory map */ /* Bits the HW doesn't care about but the kernel uses them in SW */ diff --git a/arch/cris/include/arch-v32/arch/mmu.h b/arch/cris/include/arch-v32/arch/mmu.h index 6bcdc3f..c1a13e0 100644 --- a/arch/cris/include/arch-v32/arch/mmu.h +++ b/arch/cris/include/arch-v32/arch/mmu.h @@ -28,10 +28,10 @@ typedef struct /* * CRISv32 PTE bits: * - * Bit: 31-13 12-5 4 3 2 1 0 - * +-----+------+--------+-------+--------+-------+---------+ - * | pfn | zero | global | valid | kernel | write | execute | - * +-----+------+--------+-------+--------+-------+---------+ + * Bit: 31 30-13 12-5 4 3 2 1 0 + * +-------+-----+------+--------+-------+--------+-------+---------+ + * | cache | pfn | zero | global | valid | kernel | write | execute | + * +-------+-----+------+--------+-------+--------+-------+---------+ */ /* @@ -45,6 +45,8 @@ typedef struct #define _PAGE_VALID (1 << 3) /* Page is valid. */ #define _PAGE_SILENT_READ (1 << 3) /* Same as above. */ #define _PAGE_GLOBAL (1 << 4) /* Global page. */ +#define _PAGE_NO_CACHE (1 << 31) /* part of the uncached memory map */ + /* * The hardware doesn't care about these bits, but the kernel uses them in diff --git a/arch/cris/include/asm/pgtable.h b/arch/cris/include/asm/pgtable.h index 50aa974..1fcce00 100644 --- a/arch/cris/include/asm/pgtable.h +++ b/arch/cris/include/asm/pgtable.h @@ -197,6 +197,8 @@ static inline pte_t __mk_pte(void * page, pgprot_t pgprot) static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } +#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE)) + /* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval * __pte_page(pte_val) refers to the "virtual" DRAM interval -- cgit v0.10.2 From a090ca2c840a3459642971f26bdbad96d2482e32 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Mon, 31 Aug 2009 18:20:30 +0200 Subject: CRIS: fix defconfig build failure The CRIS defconfig fails to build with: drivers/serial/crisv10.c: In function 'rs_wait_until_sent': drivers/serial/crisv10.c:3926: error: implicit declaration of function 'lock_kernel' drivers/serial/crisv10.c:3943: error: implicit declaration of function 'unlock_kernel' Include smp_lock.h. LKML-Reference: Signed-off-by: Ingo Molnar Signed-off-by: Jesper Nilsson diff --git a/drivers/serial/crisv10.c b/drivers/serial/crisv10.c index 7be52fe..31f1723 100644 --- a/drivers/serial/crisv10.c +++ b/drivers/serial/crisv10.c @@ -18,6 +18,7 @@ static char *serial_version = "$Revision: 1.25 $"; #include #include #include +#include #include #include #include -- cgit v0.10.2 From e6cd19743bfc76ca81804c2a259e3a0d7b03fd73 Mon Sep 17 00:00:00 2001 From: Jesper Nilsson Date: Mon, 31 Aug 2009 18:28:26 +0200 Subject: CRISv10: Don't autonegotiate if autonegotiation is off If autonegotiation was disabled, we still set the BMCR_ANENABLE and BMCR_ANRESTART, which resulted in autonegotiation never being disabled. Signed-off-by: Jesper Nilsson Reported-by: Julia Lawall diff --git a/drivers/net/cris/eth_v10.c b/drivers/net/cris/eth_v10.c index 7a18dc7..d70d203 100644 --- a/drivers/net/cris/eth_v10.c +++ b/drivers/net/cris/eth_v10.c @@ -768,10 +768,24 @@ e100_negotiate(struct net_device* dev) e100_set_mdio_reg(dev, np->mii_if.phy_id, MII_ADVERTISE, data); - /* Renegotiate with link partner */ + data = e100_get_mdio_reg(dev, np->mii_if.phy_id, MII_BMCR); if (autoneg_normal) { - data = e100_get_mdio_reg(dev, np->mii_if.phy_id, MII_BMCR); - data |= BMCR_ANENABLE | BMCR_ANRESTART; + /* Renegotiate with link partner */ + data |= BMCR_ANENABLE | BMCR_ANRESTART; + } else { + /* Don't negotiate speed or duplex */ + data &= ~(BMCR_ANENABLE | BMCR_ANRESTART); + + /* Set speed and duplex static */ + if (current_speed_selection == 10) + data &= ~BMCR_SPEED100; + else + data |= BMCR_SPEED100; + + if (current_duplex != full) + data &= ~BMCR_FULLDPLX; + else + data |= BMCR_FULLDPLX; } e100_set_mdio_reg(dev, np->mii_if.phy_id, MII_BMCR, data); } -- cgit v0.10.2 From 90c53ca426cb93d15eefea79dcf6bd15ad3ffeb4 Mon Sep 17 00:00:00 2001 From: Zhang Rui Date: Mon, 31 Aug 2009 12:39:54 -0400 Subject: ACPI video: work-around BIOS AML bug in _BQC _BQC on some laptops returns an uninitialized value when it's invoked for the first time. Set the laptop to the maximum backlight level in this case. http://bugzilla.kernel.org/attachment.cgi?id=22675 Signed-off-by: Zhang Rui Signed-off-by: Len Brown diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c index a8432c2..097f24c 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c @@ -878,7 +878,7 @@ acpi_video_init_brightness(struct acpi_video_device *device) br->flags._BCM_use_index = br->flags._BCL_use_index; /* _BQC uses INDEX while _BCL uses VALUE in some laptops */ - br->curr = level_old = max_level; + br->curr = level = max_level; if (!device->cap._BQC) goto set_level; @@ -900,15 +900,25 @@ acpi_video_init_brightness(struct acpi_video_device *device) br->flags._BQC_use_index = (level == max_level ? 0 : 1); - if (!br->flags._BQC_use_index) + if (!br->flags._BQC_use_index) { + /* + * Set the backlight to the initial state. + * On some buggy laptops, _BQC returns an uninitialized value + * when invoked for the first time, i.e. level_old is invalid. + * set the backlight to max_level in this case + */ + for (i = 2; i < br->count; i++) + if (level_old == br->levels[i]) + level = level_old; goto set_level; + } if (br->flags._BCL_reversed) level_old = (br->count - 1) - level_old; - level_old = br->levels[level_old]; + level = br->levels[level_old]; set_level: - result = acpi_video_device_lcd_set_level(device, level_old); + result = acpi_video_device_lcd_set_level(device, level); if (result) goto out_free_levels; -- cgit v0.10.2 From 7e24bc1ce669b2876ffa475ea1147f2bb9ffdc52 Mon Sep 17 00:00:00 2001 From: Alex Chiang Date: Tue, 4 Aug 2009 14:44:17 -0600 Subject: ACPI: pci_slot.ko wants a 64-bit _SUN Similar to commit b6adc195 (PCI hotplug: acpiphp wants a 64-bit _SUN), pci_slot.ko reads and creates sysfs directories based on the _SUN method. Certain HP platforms return 64 bits in _SUN. This change to pci_slot.ko allows us to see the correct sysfs directories. Reported-by: Chad Smith Cc: stable@kernel.org Signed-off-by: Alex Chiang Signed-off-by: Len Brown diff --git a/drivers/acpi/pci_slot.c b/drivers/acpi/pci_slot.c index 12158e0..da9d6d2 100644 --- a/drivers/acpi/pci_slot.c +++ b/drivers/acpi/pci_slot.c @@ -57,7 +57,7 @@ ACPI_MODULE_NAME("pci_slot"); MY_NAME , ## arg); \ } while (0) -#define SLOT_NAME_SIZE 20 /* Inspired by #define in acpiphp.h */ +#define SLOT_NAME_SIZE 21 /* Inspired by #define in acpiphp.h */ struct acpi_pci_slot { acpi_handle root_handle; /* handle of the root bridge */ @@ -149,7 +149,7 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv) return AE_OK; } - snprintf(name, sizeof(name), "%u", (u32)sun); + snprintf(name, sizeof(name), "%llu", sun); pci_slot = pci_create_slot(pci_bus, device, name, NULL); if (IS_ERR(pci_slot)) { err("pci_create_slot returned %ld\n", PTR_ERR(pci_slot)); -- cgit v0.10.2 From 718fb0de8ff88f71b3b91a8ee8e42e60c88e5128 Mon Sep 17 00:00:00 2001 From: Hugh Dickins Date: Thu, 6 Aug 2009 23:18:12 +0000 Subject: ACPI: fix NULL bug for HID/UID string acpi_device->pnp.hardware_id and unique_id are now allocated pointers, replacing the previous arrays. acpi_device_install_notify_handler() oopsed on the NULL hid when probing the video device, and perhaps other uses are vulnerable too. So initialize those pointers to empty strings when there is no hid or uid. Also, free hardware_id and unique_id when when acpi_device is going to be freed. http://bugzilla.kernel.org/show_bug.cgi?id=14096 Signed-off-by: Hugh Dickins Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 9606af1..dc14421 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -309,6 +309,10 @@ static void acpi_device_release(struct device *dev) struct acpi_device *acpi_dev = to_acpi_device(dev); kfree(acpi_dev->pnp.cid_list); + if (acpi_dev->flags.hardware_id) + kfree(acpi_dev->pnp.hardware_id); + if (acpi_dev->flags.unique_id) + kfree(acpi_dev->pnp.unique_id); kfree(acpi_dev); } @@ -1137,8 +1141,9 @@ static void acpi_device_set_id(struct acpi_device *device, strcpy(device->pnp.hardware_id, hid); device->flags.hardware_id = 1; } - } else - device->pnp.hardware_id = NULL; + } + if (!device->flags.hardware_id) + device->pnp.hardware_id = ""; if (uid) { device->pnp.unique_id = ACPI_ALLOCATE_ZEROED(strlen (uid) + 1); @@ -1146,8 +1151,9 @@ static void acpi_device_set_id(struct acpi_device *device, strcpy(device->pnp.unique_id, uid); device->flags.unique_id = 1; } - } else - device->pnp.unique_id = NULL; + } + if (!device->flags.unique_id) + device->pnp.unique_id = ""; if (cid_list || cid_add) { struct acpica_device_id_list *list; @@ -1362,10 +1368,8 @@ acpi_add_single_object(struct acpi_device **child, end: if (!result) *child = device; - else { - kfree(device->pnp.cid_list); - kfree(device); - } + else + acpi_device_release(&device->dev); return result; } -- cgit v0.10.2 From 0395ac6447c05e9393d4f8187ea6588b9d1daeb7 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 4 Aug 2009 16:49:52 +0200 Subject: CRIS: convert to asm-generic/hardirq.h Convert CRIS to use asm-generic/hardirq.h Also remove unneeded (incorrect) prototypes for setup_irq(). Signed-off-by: Christoph Hellwig Signed-off-by: Jesper Nilsson diff --git a/arch/cris/arch-v10/kernel/time.c b/arch/cris/arch-v10/kernel/time.c index 2b73c7a..31ca141 100644 --- a/arch/cris/arch-v10/kernel/time.c +++ b/arch/cris/arch-v10/kernel/time.c @@ -28,7 +28,6 @@ extern void update_xtime_from_cmos(void); extern int set_rtc_mmss(unsigned long nowtime); -extern int setup_irq(int, struct irqaction *); extern int have_rtc; unsigned long get_ns_in_jiffie(void) diff --git a/arch/cris/arch-v32/kernel/smp.c b/arch/cris/arch-v32/kernel/smp.c index d2a3ff8..058addd 100644 --- a/arch/cris/arch-v32/kernel/smp.c +++ b/arch/cris/arch-v32/kernel/smp.c @@ -52,8 +52,6 @@ static struct mm_struct* flush_mm; static struct vm_area_struct* flush_vma; static unsigned long flush_addr; -extern int setup_irq(int, struct irqaction *); - /* Mode registers */ static unsigned long irq_regs[NR_CPUS] = { regi_irq, diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c index 65633d0..b1920d8 100644 --- a/arch/cris/arch-v32/kernel/time.c +++ b/arch/cris/arch-v32/kernel/time.c @@ -46,7 +46,6 @@ unsigned long timer_regs[NR_CPUS] = extern void update_xtime_from_cmos(void); extern int set_rtc_mmss(unsigned long nowtime); -extern int setup_irq(int, struct irqaction *); extern int have_rtc; #ifdef CONFIG_CPU_FREQ diff --git a/arch/cris/include/asm/hardirq.h b/arch/cris/include/asm/hardirq.h index 74178ad..17bb12d 100644 --- a/arch/cris/include/asm/hardirq.h +++ b/arch/cris/include/asm/hardirq.h @@ -2,16 +2,6 @@ #define __ASM_HARDIRQ_H #include -#include -#include - -typedef struct { - unsigned int __softirq_pending; -} ____cacheline_aligned irq_cpustat_t; - -#include /* Standard mappings for irq_cpustat_t above */ - -void ack_bad_irq(unsigned int irq); #define HARDIRQ_BITS 8 @@ -24,4 +14,6 @@ void ack_bad_irq(unsigned int irq); # error HARDIRQ_BITS is too low! #endif +#include + #endif /* __ASM_HARDIRQ_H */ diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c index 7f642fc..0ca7d98 100644 --- a/arch/cris/kernel/irq.c +++ b/arch/cris/kernel/irq.c @@ -38,11 +38,6 @@ #include -void ack_bad_irq(unsigned int irq) -{ - printk("unexpected IRQ trap at vector %02x\n", irq); -} - int show_interrupts(struct seq_file *p, void *v) { int i = *(loff_t *) v, j; -- cgit v0.10.2 From 62f589c5e391dc2081db42e801382304c652e43a Mon Sep 17 00:00:00 2001 From: Stoyan Gaydarov Date: Wed, 22 Jul 2009 05:02:33 +0200 Subject: ARRAY_SIZE changes These changes were a direct result of using a semantic patch More information can be found at http://www.emn.fr/x-info/coccinelle/ Signed-off-by: Stoyan Gaydarov Signed-off-by: Jesper Nilsson diff --git a/arch/cris/arch-v32/mach-a3/io.c b/arch/cris/arch-v32/mach-a3/io.c index c22f67e..090ceb9 100644 --- a/arch/cris/arch-v32/mach-a3/io.c +++ b/arch/cris/arch-v32/mach-a3/io.c @@ -36,7 +36,7 @@ struct crisv32_ioport crisv32_ioports[] = { }, }; -#define NBR_OF_PORTS sizeof(crisv32_ioports)/sizeof(struct crisv32_ioport) +#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports) struct crisv32_iopin crisv32_led_net0_green; struct crisv32_iopin crisv32_led_net0_red; diff --git a/arch/cris/arch-v32/mach-fs/io.c b/arch/cris/arch-v32/mach-fs/io.c index cb6327b..a695866 100644 --- a/arch/cris/arch-v32/mach-fs/io.c +++ b/arch/cris/arch-v32/mach-fs/io.c @@ -52,7 +52,7 @@ struct crisv32_ioport crisv32_ioports[] = { } }; -#define NBR_OF_PORTS sizeof(crisv32_ioports)/sizeof(struct crisv32_ioport) +#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports) struct crisv32_iopin crisv32_led_net0_green; struct crisv32_iopin crisv32_led_net0_red; -- cgit v0.10.2 From fa8a123855e20068204982596b8fafceb1a67f0b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 26 Aug 2009 13:13:37 +1000 Subject: drm/mm: add ability to dump mm lists via debugfs This adds code to the drm_mm to talk to debugfs, and adds support to radeon to add the VRAM and GTT mm lists to debugfs. I tested with spinlock debugging and it doesn't give out. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index 3e47869..c861d80 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -44,6 +44,7 @@ #include "drmP.h" #include "drm_mm.h" #include +#include #define MM_UNUSED_TARGET 4 @@ -370,3 +371,23 @@ void drm_mm_takedown(struct drm_mm * mm) BUG_ON(mm->num_unused != 0); } EXPORT_SYMBOL(drm_mm_takedown); + +#if defined(CONFIG_DEBUG_FS) +int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm) +{ + struct drm_mm_node *entry; + int total_used = 0, total_free = 0, total = 0; + + list_for_each_entry(entry, &mm->ml_entry, ml_entry) { + seq_printf(m, "0x%08lx-0x%08lx: 0x%08lx: %s\n", entry->start, entry->start + entry->size, entry->size, entry->free ? "free" : "used"); + total += entry->size; + if (entry->free) + total_free += entry->size; + else + total_used += entry->size; + } + seq_printf(m, "total: %d, used %d free %d\n", total, total_free, total_used); + return 0; +} +EXPORT_SYMBOL(drm_mm_dump_table); +#endif diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 0a85e7b..dc7a442 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -35,11 +35,14 @@ #include #include #include +#include #include "radeon_reg.h" #include "radeon.h" #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) +static int radeon_ttm_debugfs_init(struct radeon_device *rdev); + static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) { struct radeon_mman *mman; @@ -504,6 +507,12 @@ int radeon_ttm_init(struct radeon_device *rdev) if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; } + + r = radeon_ttm_debugfs_init(rdev); + if (r) { + DRM_ERROR("Failed to init debugfs\n"); + return r; + } return 0; } @@ -678,3 +687,50 @@ struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev) gtt->bound = false; return >t->backend; } + +#define RADEON_DEBUGFS_MEM_TYPES 2 + +static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES]; +static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES][32]; + +#if defined(CONFIG_DEBUG_FS) +static int radeon_mm_dump_table(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; + struct drm_device *dev = node->minor->dev; + struct radeon_device *rdev = dev->dev_private; + int ret; + struct ttm_bo_global *glob = rdev->mman.bdev.glob; + + spin_lock(&glob->lru_lock); + ret = drm_mm_dump_table(m, mm); + spin_unlock(&glob->lru_lock); + return ret; +} +#endif + +static int radeon_ttm_debugfs_init(struct radeon_device *rdev) +{ + unsigned i; + +#if defined(CONFIG_DEBUG_FS) + for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { + if (i == 0) + sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); + else + sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); + radeon_mem_types_list[i].name = radeon_mem_types_names[i]; + radeon_mem_types_list[i].show = &radeon_mm_dump_table; + radeon_mem_types_list[i].driver_features = 0; + if (i == 0) + radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_VRAM].manager; + else + radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_TT].manager; + + } + return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES); + +#endif + return 0; +} diff --git a/include/drm/drm_mm.h b/include/drm/drm_mm.h index f833207..bc5a87e 100644 --- a/include/drm/drm_mm.h +++ b/include/drm/drm_mm.h @@ -96,4 +96,8 @@ static inline struct drm_mm *drm_get_mm(struct drm_mm_node *block) return block->mm; } +#ifdef CONFIG_DEBUG_FS +int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm); +#endif + #endif -- cgit v0.10.2 From ed017d9fb17af3162f5acf922eb5731c541e1f3a Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 2 Sep 2009 09:41:13 +1000 Subject: drm: fix drm_cache.c for arch with no support. This produces a warn on for architectures where this gets called but we don't have a cache flushing implementation suitable. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 3a5575e..0e3bd5b 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -62,11 +62,8 @@ drm_clflush_ipi_handler(void *null) { wbinvd(); } -#elif !defined(__powerpc__) -static void drm_cache_ipi_handler(void *dummy) -{ -} #endif + void drm_clflush_pages(struct page *pages[], unsigned long num_pages) { @@ -95,8 +92,8 @@ drm_clflush_pages(struct page *pages[], unsigned long num_pages) kunmap_atomic(page_virtual, KM_USER0); } #else - if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) - printk(KERN_ERR "Timed out waiting for drm cache flush\n"); + printk(KERN_ERR "Architecture has no drm_cache.c support\n"); + WARN_ON_ONCE(1); #endif } EXPORT_SYMBOL(drm_clflush_pages); -- cgit v0.10.2 From a3a0544b2c84e1d7a2022b558ecf66d8c6a8dd93 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 31 Aug 2009 15:16:30 +1000 Subject: drm/kms: add explicit encoder disable function and detach harder. For shared tv-out and VGA encoders, we really need to know if the encoder is just being switched off temporarily in blanking or if we are really disabling it hard. Also we need to try harder to disconnect encoders from unused connectors so we can share more efficently. (shared encoders stuff is coming in radeon tv-out support) Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index 205349e..eea5e6c 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -260,13 +260,27 @@ EXPORT_SYMBOL(drm_helper_crtc_in_use); void drm_helper_disable_unused_functions(struct drm_device *dev) { struct drm_encoder *encoder; + struct drm_connector *connector; struct drm_encoder_helper_funcs *encoder_funcs; struct drm_crtc *crtc; + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + if (!connector->encoder) + continue; + if (connector->status == connector_status_disconnected) + connector->encoder = NULL; + } + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { encoder_funcs = encoder->helper_private; - if (!drm_helper_encoder_in_use(encoder)) - (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF); + if (!drm_helper_encoder_in_use(encoder)) { + if (encoder_funcs->disable) + (*encoder_funcs->disable)(encoder); + else + (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF); + } + /* disconnector encoder from any connector */ + encoder->crtc = NULL; } list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { @@ -411,7 +425,7 @@ static int drm_pick_crtcs(struct drm_device *dev, c = 0; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - if ((connector->encoder->possible_crtcs & (1 << c)) == 0) { + if ((encoder->possible_crtcs & (1 << c)) == 0) { c++; continue; } @@ -496,8 +510,10 @@ static void drm_setup_crtcs(struct drm_device *dev) mode->name, crtc->base.id); crtc->desired_mode = mode; connector->encoder->crtc = crtc; - } else + } else { connector->encoder->crtc = NULL; + connector->encoder = NULL; + } i++; } diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h index e44a4f8..4c8daca 100644 --- a/include/drm/drm_crtc_helper.h +++ b/include/drm/drm_crtc_helper.h @@ -79,6 +79,8 @@ struct drm_encoder_helper_funcs { /* detect for DAC style encoders */ enum drm_connector_status (*detect)(struct drm_encoder *encoder, struct drm_connector *connector); + /* disable encoder when not in use - more explicit than dpms off */ + void (*disable)(struct drm_encoder *encoder); }; struct drm_connector_helper_funcs { -- cgit v0.10.2 From a06b1261bdb580b35967d0e055d1ab131b332254 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Mon, 31 Aug 2009 15:16:11 -0400 Subject: NFSD: Fix a bug in the NFSv4 'supported attrs' mandatory attribute The fact that the filesystem doesn't currently list any alternate locations does _not_ imply that the fs_locations attribute should be marked as "unsupported". Signed-off-by: Trond Myklebust Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c index 6fde431..bebc0c2 100644 --- a/fs/nfsd/nfs4proc.c +++ b/fs/nfsd/nfs4proc.c @@ -68,7 +68,6 @@ check_attr_support(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, u32 *bmval, u32 *writable) { struct dentry *dentry = cstate->current_fh.fh_dentry; - struct svc_export *exp = cstate->current_fh.fh_export; /* * Check about attributes are supported by the NFSv4 server or not. @@ -80,17 +79,13 @@ check_attr_support(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, return nfserr_attrnotsupp; /* - * Check FATTR4_WORD0_ACL & FATTR4_WORD0_FS_LOCATIONS can be supported + * Check FATTR4_WORD0_ACL can be supported * in current environment or not. */ if (bmval[0] & FATTR4_WORD0_ACL) { if (!IS_POSIXACL(dentry->d_inode)) return nfserr_attrnotsupp; } - if (bmval[0] & FATTR4_WORD0_FS_LOCATIONS) { - if (exp->ex_fslocs.locations == NULL) - return nfserr_attrnotsupp; - } /* * According to spec, read-only attributes return ERR_INVAL. diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c index fdf632b..20c5e3d 100644 --- a/fs/nfsd/nfs4xdr.c +++ b/fs/nfsd/nfs4xdr.c @@ -1793,11 +1793,6 @@ nfsd4_encode_fattr(struct svc_fh *fhp, struct svc_export *exp, goto out_nfserr; } } - if (bmval0 & FATTR4_WORD0_FS_LOCATIONS) { - if (exp->ex_fslocs.locations == NULL) { - bmval0 &= ~FATTR4_WORD0_FS_LOCATIONS; - } - } if ((buflen -= 16) < 0) goto out_resource; @@ -1825,8 +1820,6 @@ nfsd4_encode_fattr(struct svc_fh *fhp, struct svc_export *exp, goto out_resource; if (!aclsupport) word0 &= ~FATTR4_WORD0_ACL; - if (!exp->ex_fslocs.locations) - word0 &= ~FATTR4_WORD0_FS_LOCATIONS; if (!word2) { WRITE32(2); WRITE32(word0); -- cgit v0.10.2 From a649637c73a36174287a403cdda7607177d64523 Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Fri, 28 Aug 2009 08:45:01 -0400 Subject: nfsd41: bound forechannel drc size by memory usage By using the requested ca_maxresponsesize_cached * ca_maxresponses to bound a forechannel drc request size, clients can tailor a session to usage. For example, an I/O session (READ/WRITE only) can have a much smaller ca_maxresponsesize_cached (for only WRITE compound responses) and a lot larger ca_maxresponses to service a large in-flight data window. Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index b44a2cf..02b3ddd 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -414,34 +414,64 @@ gen_sessionid(struct nfsd4_session *ses) } /* - * Give the client the number of slots it requests bound by - * NFSD_MAX_SLOTS_PER_SESSION and by nfsd_drc_max_mem. + * The protocol defines ca_maxresponssize_cached to include the size of + * the rpc header, but all we need to cache is the data starting after + * the end of the initial SEQUENCE operation--the rest we regenerate + * each time. Therefore we can advertise a ca_maxresponssize_cached + * value that is the number of bytes in our cache plus a few additional + * bytes. In order to stay on the safe side, and not promise more than + * we can cache, those additional bytes must be the minimum possible: 24 + * bytes of rpc header (xid through accept state, with AUTH_NULL + * verifier), 12 for the compound header (with zero-length tag), and 44 + * for the SEQUENCE op response: + */ +#define NFSD_MIN_HDR_SEQ_SZ (24 + 12 + 44) + +/* + * Give the client the number of ca_maxresponsesize_cached slots it + * requests, of size bounded by NFSD_SLOT_CACHE_SIZE, + * NFSD_MAX_MEM_PER_SESSION, and nfsd_drc_max_mem. Do not allow more + * than NFSD_MAX_SLOTS_PER_SESSION. * - * If we run out of reserved DRC memory we should (up to a point) re-negotiate - * active sessions and reduce their slot usage to make rooom for new - * connections. For now we just fail the create session. + * If we run out of reserved DRC memory we should (up to a point) + * re-negotiate active sessions and reduce their slot usage to make + * rooom for new connections. For now we just fail the create session. */ -static int set_forechannel_maxreqs(struct nfsd4_channel_attrs *fchan) +static int set_forechannel_drc_size(struct nfsd4_channel_attrs *fchan) { - int mem; + int mem, size = fchan->maxresp_cached; if (fchan->maxreqs < 1) return nfserr_inval; - else if (fchan->maxreqs > NFSD_MAX_SLOTS_PER_SESSION) - fchan->maxreqs = NFSD_MAX_SLOTS_PER_SESSION; - mem = fchan->maxreqs * NFSD_SLOT_CACHE_SIZE; + if (size < NFSD_MIN_HDR_SEQ_SZ) + size = NFSD_MIN_HDR_SEQ_SZ; + size -= NFSD_MIN_HDR_SEQ_SZ; + if (size > NFSD_SLOT_CACHE_SIZE) + size = NFSD_SLOT_CACHE_SIZE; + + /* bound the maxreqs by NFSD_MAX_MEM_PER_SESSION */ + mem = fchan->maxreqs * size; + if (mem > NFSD_MAX_MEM_PER_SESSION) { + fchan->maxreqs = NFSD_MAX_MEM_PER_SESSION / size; + if (fchan->maxreqs > NFSD_MAX_SLOTS_PER_SESSION) + fchan->maxreqs = NFSD_MAX_SLOTS_PER_SESSION; + mem = fchan->maxreqs * size; + } spin_lock(&nfsd_drc_lock); - if (mem + nfsd_drc_mem_used > nfsd_drc_max_mem) - mem = ((nfsd_drc_max_mem - nfsd_drc_mem_used) / - NFSD_SLOT_CACHE_SIZE) * NFSD_SLOT_CACHE_SIZE; + /* bound the total session drc memory ussage */ + if (mem + nfsd_drc_mem_used > nfsd_drc_max_mem) { + fchan->maxreqs = (nfsd_drc_max_mem - nfsd_drc_mem_used) / size; + mem = fchan->maxreqs * size; + } nfsd_drc_mem_used += mem; spin_unlock(&nfsd_drc_lock); - fchan->maxreqs = mem / NFSD_SLOT_CACHE_SIZE; if (fchan->maxreqs == 0) return nfserr_resource; + + fchan->maxresp_cached = size + NFSD_MIN_HDR_SEQ_SZ; return 0; } @@ -466,9 +496,6 @@ static int init_forechannel_attrs(struct svc_rqst *rqstp, fchan->maxresp_sz = maxcount; session_fchan->maxresp_sz = fchan->maxresp_sz; - session_fchan->maxresp_cached = NFSD_SLOT_CACHE_SIZE; - fchan->maxresp_cached = session_fchan->maxresp_cached; - /* Use the client's maxops if possible */ if (fchan->maxops > NFSD_MAX_OPS_PER_COMPOUND) fchan->maxops = NFSD_MAX_OPS_PER_COMPOUND; @@ -478,9 +505,12 @@ static int init_forechannel_attrs(struct svc_rqst *rqstp, * recover pages from existing sessions. For now fail session * creation. */ - status = set_forechannel_maxreqs(fchan); + status = set_forechannel_drc_size(fchan); + session_fchan->maxresp_cached = fchan->maxresp_cached; session_fchan->maxreqs = fchan->maxreqs; + + dprintk("%s status %d\n", __func__, status); return status; } diff --git a/include/linux/nfsd/state.h b/include/linux/nfsd/state.h index fb0c404..ff0b771 100644 --- a/include/linux/nfsd/state.h +++ b/include/linux/nfsd/state.h @@ -92,13 +92,17 @@ struct nfs4_cb_conn { struct rpc_cred * cb_cred; }; -/* Maximum number of slots per session. 128 is useful for long haul TCP */ -#define NFSD_MAX_SLOTS_PER_SESSION 128 +/* Maximum number of slots per session. 160 is useful for long haul TCP */ +#define NFSD_MAX_SLOTS_PER_SESSION 160 /* Maximum number of pages per slot cache entry */ #define NFSD_PAGES_PER_SLOT 1 #define NFSD_SLOT_CACHE_SIZE PAGE_SIZE /* Maximum number of operations per session compound */ #define NFSD_MAX_OPS_PER_COMPOUND 16 +/* Maximum number of NFSD_SLOT_CACHE_SIZE slots per session */ +#define NFSD_CACHE_SIZE_SLOTS_PER_SESSION 32 +#define NFSD_MAX_MEM_PER_SESSION \ + (NFSD_CACHE_SIZE_SLOTS_PER_SESSION * NFSD_SLOT_CACHE_SIZE) struct nfsd4_cache_entry { __be32 ce_status; -- cgit v0.10.2 From a8dfdaeb7a8b1295f45d9d208dd27e6e20113d1b Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Fri, 28 Aug 2009 08:45:02 -0400 Subject: nfsd41: use session maxreqs for sequence target and highest slotid This fixes a bug in the sequence operation reply. The sequence operation returns the highest slotid it will accept in the future in sr_highest_slotid, and the highest slotid it prefers the client to use. Since we do not re-negotiate the session slot table yet, these should both always be set to the session ca_maxrequests. Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 02b3ddd..ec074e7 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -1133,7 +1133,6 @@ nfsd4_replay_cache_entry(struct nfsd4_compoundres *resp, * session inactivity timer fires and a solo sequence operation * is sent (lease renewal). */ - seq->maxslots = resp->cstate.session->se_fchannel.maxreqs; /* Either returns 0 or nfserr_retry_uncached */ status = nfsd4_enc_sequence_replay(resp->rqstp->rq_argp, resp); @@ -1497,6 +1496,11 @@ nfsd4_sequence(struct svc_rqst *rqstp, slot = &session->se_slots[seq->slotid]; dprintk("%s: slotid %d\n", __func__, seq->slotid); + /* We do not negotiate the number of slots yet, so set the + * maxslots to the session maxreqs which is used to encode + * sr_highest_slotid and the sr_target_slot id to maxslots */ + seq->maxslots = session->se_fchannel.maxreqs; + status = check_slot_seqid(seq->seqid, slot->sl_seqid, slot->sl_inuse); if (status == nfserr_replay_cache) { cstate->slot = slot; -- cgit v0.10.2 From bdac86e2154cfe47552639113265d1fa27cfbe72 Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Fri, 28 Aug 2009 08:45:03 -0400 Subject: nfsd41: replace nfserr_resource in pure nfs41 responses nfserr_resource is not a legal error for NFSv4.1. Replace it with nfserr_serverfault for EXCHANGE_ID and CREATE_SESSION processing. We will also need to map nfserr_resource to other errors in routines shared by NFSv4.0 and NFSv4.1 Signed-off-by: Andy Adamson Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index ec074e7..c9a45f4 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -469,7 +469,7 @@ static int set_forechannel_drc_size(struct nfsd4_channel_attrs *fchan) spin_unlock(&nfsd_drc_lock); if (fchan->maxreqs == 0) - return nfserr_resource; + return nfserr_serverfault; fchan->maxresp_cached = size + NFSD_MIN_HDR_SEQ_SZ; return 0; @@ -519,7 +519,7 @@ alloc_init_session(struct svc_rqst *rqstp, struct nfs4_client *clp, struct nfsd4_create_session *cses) { struct nfsd4_session *new, tmp; - int idx, status = nfserr_resource, slotsize; + int idx, status = nfserr_serverfault, slotsize; memset(&tmp, 0, sizeof(tmp)); @@ -1282,7 +1282,7 @@ out_new: /* Normal case */ new = create_client(exid->clname, dname); if (new == NULL) { - status = nfserr_resource; + status = nfserr_serverfault; goto out; } -- cgit v0.10.2 From 557ce2646e775f6bda734dd92b10d4780874b9c7 Mon Sep 17 00:00:00 2001 From: Andy Adamson Date: Fri, 28 Aug 2009 08:45:04 -0400 Subject: nfsd41: replace page based DRC with buffer based DRC Use NFSD_SLOT_CACHE_SIZE size buffers for sessions DRC instead of holding nfsd pages in cache. Connectathon testing has shown that 1024 bytes for encoded compound operation responses past the sequence operation is sufficient, 512 bytes is a little too small. Set NFSD_SLOT_CACHE_SIZE to 1024. Allocate memory for the session DRC in the CREATE_SESSION operation to guarantee that the memory resource is available for caching responses. Allocate each slot individually in preparation for slot table size negotiation. Remove struct nfsd4_cache_entry and helper functions for the old page-based DRC. The iov_len calculation in nfs4svc_encode_compoundres is now always correct. Replay is now done in nfsd4_sequence under the state lock, so the session ref count is only bumped on non-replay. Clean up the nfs4svc_encode_compoundres session logic. The nfsd4_compound_state statp pointer is also not used. Remove nfsd4_set_statp(). Move useful nfsd4_cache_entry fields into nfsd4_slot. Signed-off-by: Andy Adamson diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index c9a45f4..46e9ac5 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -514,12 +514,23 @@ static int init_forechannel_attrs(struct svc_rqst *rqstp, return status; } +static void +free_session_slots(struct nfsd4_session *ses) +{ + int i; + + for (i = 0; i < ses->se_fchannel.maxreqs; i++) + kfree(ses->se_slots[i]); +} + static int alloc_init_session(struct svc_rqst *rqstp, struct nfs4_client *clp, struct nfsd4_create_session *cses) { struct nfsd4_session *new, tmp; - int idx, status = nfserr_serverfault, slotsize; + struct nfsd4_slot *sp; + int idx, slotsize, cachesize, i; + int status; memset(&tmp, 0, sizeof(tmp)); @@ -530,14 +541,27 @@ alloc_init_session(struct svc_rqst *rqstp, struct nfs4_client *clp, if (status) goto out; - /* allocate struct nfsd4_session and slot table in one piece */ - slotsize = tmp.se_fchannel.maxreqs * sizeof(struct nfsd4_slot); + BUILD_BUG_ON(NFSD_MAX_SLOTS_PER_SESSION * sizeof(struct nfsd4_slot) + + sizeof(struct nfsd4_session) > PAGE_SIZE); + + status = nfserr_serverfault; + /* allocate struct nfsd4_session and slot table pointers in one piece */ + slotsize = tmp.se_fchannel.maxreqs * sizeof(struct nfsd4_slot *); new = kzalloc(sizeof(*new) + slotsize, GFP_KERNEL); if (!new) goto out; memcpy(new, &tmp, sizeof(*new)); + /* allocate each struct nfsd4_slot and data cache in one piece */ + cachesize = new->se_fchannel.maxresp_cached - NFSD_MIN_HDR_SEQ_SZ; + for (i = 0; i < new->se_fchannel.maxreqs; i++) { + sp = kzalloc(sizeof(*sp) + cachesize, GFP_KERNEL); + if (!sp) + goto out_free; + new->se_slots[i] = sp; + } + new->se_client = clp; gen_sessionid(new); idx = hash_sessionid(&new->se_sessionid); @@ -554,6 +578,10 @@ alloc_init_session(struct svc_rqst *rqstp, struct nfs4_client *clp, status = nfs_ok; out: return status; +out_free: + free_session_slots(new); + kfree(new); + goto out; } /* caller must hold sessionid_lock */ @@ -596,22 +624,16 @@ release_session(struct nfsd4_session *ses) nfsd4_put_session(ses); } -static void nfsd4_release_respages(struct page **respages, short resused); - void free_session(struct kref *kref) { struct nfsd4_session *ses; - int i; ses = container_of(kref, struct nfsd4_session, se_ref); - for (i = 0; i < ses->se_fchannel.maxreqs; i++) { - struct nfsd4_cache_entry *e = &ses->se_slots[i].sl_cache_entry; - nfsd4_release_respages(e->ce_respages, e->ce_resused); - } spin_lock(&nfsd_drc_lock); nfsd_drc_mem_used -= ses->se_fchannel.maxreqs * NFSD_SLOT_CACHE_SIZE; spin_unlock(&nfsd_drc_lock); + free_session_slots(ses); kfree(ses); } @@ -968,116 +990,31 @@ out_err: return; } -void -nfsd4_set_statp(struct svc_rqst *rqstp, __be32 *statp) -{ - struct nfsd4_compoundres *resp = rqstp->rq_resp; - - resp->cstate.statp = statp; -} - -/* - * Dereference the result pages. - */ -static void -nfsd4_release_respages(struct page **respages, short resused) -{ - int i; - - dprintk("--> %s\n", __func__); - for (i = 0; i < resused; i++) { - if (!respages[i]) - continue; - put_page(respages[i]); - respages[i] = NULL; - } -} - -static void -nfsd4_copy_pages(struct page **topages, struct page **frompages, short count) -{ - int i; - - for (i = 0; i < count; i++) { - topages[i] = frompages[i]; - if (!topages[i]) - continue; - get_page(topages[i]); - } -} - /* - * Cache the reply pages up to NFSD_PAGES_PER_SLOT + 1, clearing the previous - * pages. We add a page to NFSD_PAGES_PER_SLOT for the case where the total - * length of the XDR response is less than se_fmaxresp_cached - * (NFSD_PAGES_PER_SLOT * PAGE_SIZE) but the xdr_buf pages is used for a - * of the reply (e.g. readdir). - * - * Store the base and length of the rq_req.head[0] page - * of the NFSv4.1 data, just past the rpc header. + * Cache a reply. nfsd4_check_drc_limit() has bounded the cache size. */ void nfsd4_store_cache_entry(struct nfsd4_compoundres *resp) { - struct nfsd4_cache_entry *entry = &resp->cstate.slot->sl_cache_entry; - struct svc_rqst *rqstp = resp->rqstp; - struct kvec *resv = &rqstp->rq_res.head[0]; - - dprintk("--> %s entry %p\n", __func__, entry); + struct nfsd4_slot *slot = resp->cstate.slot; + unsigned int base; - nfsd4_release_respages(entry->ce_respages, entry->ce_resused); - entry->ce_opcnt = resp->opcnt; - entry->ce_status = resp->cstate.status; + dprintk("--> %s slot %p\n", __func__, slot); - /* - * Don't need a page to cache just the sequence operation - the slot - * does this for us! - */ + slot->sl_opcnt = resp->opcnt; + slot->sl_status = resp->cstate.status; if (nfsd4_not_cached(resp)) { - entry->ce_resused = 0; - entry->ce_rpchdrlen = 0; - dprintk("%s Just cache SEQUENCE. ce_cachethis %d\n", __func__, - resp->cstate.slot->sl_cache_entry.ce_cachethis); + slot->sl_datalen = 0; return; } - entry->ce_resused = rqstp->rq_resused; - if (entry->ce_resused > NFSD_PAGES_PER_SLOT + 1) - entry->ce_resused = NFSD_PAGES_PER_SLOT + 1; - nfsd4_copy_pages(entry->ce_respages, rqstp->rq_respages, - entry->ce_resused); - entry->ce_datav.iov_base = resp->cstate.statp; - entry->ce_datav.iov_len = resv->iov_len - ((char *)resp->cstate.statp - - (char *)page_address(rqstp->rq_respages[0])); - /* Current request rpc header length*/ - entry->ce_rpchdrlen = (char *)resp->cstate.statp - - (char *)page_address(rqstp->rq_respages[0]); -} - -/* - * We keep the rpc header, but take the nfs reply from the replycache. - */ -static int -nfsd41_copy_replay_data(struct nfsd4_compoundres *resp, - struct nfsd4_cache_entry *entry) -{ - struct svc_rqst *rqstp = resp->rqstp; - struct kvec *resv = &resp->rqstp->rq_res.head[0]; - int len; - - /* Current request rpc header length*/ - len = (char *)resp->cstate.statp - - (char *)page_address(rqstp->rq_respages[0]); - if (entry->ce_datav.iov_len + len > PAGE_SIZE) { - dprintk("%s v41 cached reply too large (%Zd).\n", __func__, - entry->ce_datav.iov_len); - return 0; - } - /* copy the cached reply nfsd data past the current rpc header */ - memcpy((char *)resv->iov_base + len, entry->ce_datav.iov_base, - entry->ce_datav.iov_len); - resv->iov_len = len + entry->ce_datav.iov_len; - return 1; + slot->sl_datalen = (char *)resp->p - (char *)resp->cstate.datap; + base = (char *)resp->cstate.datap - + (char *)resp->xbuf->head[0].iov_base; + if (read_bytes_from_xdr_buf(resp->xbuf, base, slot->sl_data, + slot->sl_datalen)) + WARN("%s: sessions DRC could not cache compound\n", __func__); + return; } /* @@ -1095,14 +1032,14 @@ nfsd4_enc_sequence_replay(struct nfsd4_compoundargs *args, struct nfsd4_slot *slot = resp->cstate.slot; dprintk("--> %s resp->opcnt %d cachethis %u \n", __func__, - resp->opcnt, resp->cstate.slot->sl_cache_entry.ce_cachethis); + resp->opcnt, resp->cstate.slot->sl_cachethis); /* Encode the replayed sequence operation */ op = &args->ops[resp->opcnt - 1]; nfsd4_encode_operation(resp, op); /* Return nfserr_retry_uncached_rep in next operation. */ - if (args->opcnt > 1 && slot->sl_cache_entry.ce_cachethis == 0) { + if (args->opcnt > 1 && slot->sl_cachethis == 0) { op = &args->ops[resp->opcnt++]; op->status = nfserr_retry_uncached_rep; nfsd4_encode_operation(resp, op); @@ -1111,57 +1048,29 @@ nfsd4_enc_sequence_replay(struct nfsd4_compoundargs *args, } /* - * Keep the first page of the replay. Copy the NFSv4.1 data from the first - * cached page. Replace any futher replay pages from the cache. + * The sequence operation is not cached because we can use the slot and + * session values. */ __be32 nfsd4_replay_cache_entry(struct nfsd4_compoundres *resp, struct nfsd4_sequence *seq) { - struct nfsd4_cache_entry *entry = &resp->cstate.slot->sl_cache_entry; + struct nfsd4_slot *slot = resp->cstate.slot; __be32 status; - dprintk("--> %s entry %p\n", __func__, entry); - - /* - * If this is just the sequence operation, we did not keep - * a page in the cache entry because we can just use the - * slot info stored in struct nfsd4_sequence that was checked - * against the slot in nfsd4_sequence(). - * - * This occurs when seq->cachethis is FALSE, or when the client - * session inactivity timer fires and a solo sequence operation - * is sent (lease renewal). - */ + dprintk("--> %s slot %p\n", __func__, slot); /* Either returns 0 or nfserr_retry_uncached */ status = nfsd4_enc_sequence_replay(resp->rqstp->rq_argp, resp); if (status == nfserr_retry_uncached_rep) return status; - if (!nfsd41_copy_replay_data(resp, entry)) { - /* - * Not enough room to use the replay rpc header, send the - * cached header. Release all the allocated result pages. - */ - svc_free_res_pages(resp->rqstp); - nfsd4_copy_pages(resp->rqstp->rq_respages, entry->ce_respages, - entry->ce_resused); - } else { - /* Release all but the first allocated result page */ - - resp->rqstp->rq_resused--; - svc_free_res_pages(resp->rqstp); - - nfsd4_copy_pages(&resp->rqstp->rq_respages[1], - &entry->ce_respages[1], - entry->ce_resused - 1); - } + /* The sequence operation has been encoded, cstate->datap set. */ + memcpy(resp->cstate.datap, slot->sl_data, slot->sl_datalen); - resp->rqstp->rq_resused = entry->ce_resused; - resp->opcnt = entry->ce_opcnt; - resp->cstate.iovlen = entry->ce_datav.iov_len + entry->ce_rpchdrlen; - status = entry->ce_status; + resp->opcnt = slot->sl_opcnt; + resp->p = resp->cstate.datap + XDR_QUADLEN(slot->sl_datalen); + status = slot->sl_status; return status; } @@ -1493,7 +1402,7 @@ nfsd4_sequence(struct svc_rqst *rqstp, if (seq->slotid >= session->se_fchannel.maxreqs) goto out; - slot = &session->se_slots[seq->slotid]; + slot = session->se_slots[seq->slotid]; dprintk("%s: slotid %d\n", __func__, seq->slotid); /* We do not negotiate the number of slots yet, so set the @@ -1506,7 +1415,7 @@ nfsd4_sequence(struct svc_rqst *rqstp, cstate->slot = slot; cstate->session = session; /* Return the cached reply status and set cstate->status - * for nfsd4_svc_encode_compoundres processing */ + * for nfsd4_proc_compound processing */ status = nfsd4_replay_cache_entry(resp, seq); cstate->status = nfserr_replay_cache; goto out; @@ -1517,7 +1426,7 @@ nfsd4_sequence(struct svc_rqst *rqstp, /* Success! bump slot seqid */ slot->sl_inuse = true; slot->sl_seqid = seq->seqid; - slot->sl_cache_entry.ce_cachethis = seq->cachethis; + slot->sl_cachethis = seq->cachethis; cstate->slot = slot; cstate->session = session; diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c index 20c5e3d..00ed16a 100644 --- a/fs/nfsd/nfs4xdr.c +++ b/fs/nfsd/nfs4xdr.c @@ -3057,6 +3057,7 @@ nfsd4_encode_sequence(struct nfsd4_compoundres *resp, int nfserr, WRITE32(0); ADJUST_ARGS(); + resp->cstate.datap = p; /* DRC cache data pointer */ return 0; } @@ -3159,7 +3160,7 @@ static int nfsd4_check_drc_limit(struct nfsd4_compoundres *resp) return status; session = resp->cstate.session; - if (session == NULL || slot->sl_cache_entry.ce_cachethis == 0) + if (session == NULL || slot->sl_cachethis == 0) return status; if (resp->opcnt >= args->opcnt) @@ -3284,6 +3285,7 @@ nfs4svc_encode_compoundres(struct svc_rqst *rqstp, __be32 *p, struct nfsd4_compo /* * All that remains is to write the tag and operation count... */ + struct nfsd4_compound_state *cs = &resp->cstate; struct kvec *iov; p = resp->tagp; *p++ = htonl(resp->taglen); @@ -3297,15 +3299,10 @@ nfs4svc_encode_compoundres(struct svc_rqst *rqstp, __be32 *p, struct nfsd4_compo iov = &rqstp->rq_res.head[0]; iov->iov_len = ((char*)resp->p) - (char*)iov->iov_base; BUG_ON(iov->iov_len > PAGE_SIZE); - if (nfsd4_has_session(&resp->cstate)) { - if (resp->cstate.status == nfserr_replay_cache && - !nfsd4_not_cached(resp)) { - iov->iov_len = resp->cstate.iovlen; - } else { - nfsd4_store_cache_entry(resp); - dprintk("%s: SET SLOT STATE TO AVAILABLE\n", __func__); - resp->cstate.slot->sl_inuse = 0; - } + if (nfsd4_has_session(cs) && cs->status != nfserr_replay_cache) { + nfsd4_store_cache_entry(resp); + dprintk("%s: SET SLOT STATE TO AVAILABLE\n", __func__); + resp->cstate.slot->sl_inuse = false; nfsd4_put_session(resp->cstate.session); } return 1; diff --git a/fs/nfsd/nfssvc.c b/fs/nfsd/nfssvc.c index 675d395..4472449 100644 --- a/fs/nfsd/nfssvc.c +++ b/fs/nfsd/nfssvc.c @@ -577,10 +577,6 @@ nfsd_dispatch(struct svc_rqst *rqstp, __be32 *statp) + rqstp->rq_res.head[0].iov_len; rqstp->rq_res.head[0].iov_len += sizeof(__be32); - /* NFSv4.1 DRC requires statp */ - if (rqstp->rq_vers == 4) - nfsd4_set_statp(rqstp, statp); - /* Now call the procedure handler, and encode NFS status. */ nfserr = proc->pc_func(rqstp, rqstp->rq_argp, rqstp->rq_resp); nfserr = map_new_errors(rqstp->rq_vers, nfserr); diff --git a/include/linux/nfsd/state.h b/include/linux/nfsd/state.h index ff0b771..70ef5f4 100644 --- a/include/linux/nfsd/state.h +++ b/include/linux/nfsd/state.h @@ -94,30 +94,23 @@ struct nfs4_cb_conn { /* Maximum number of slots per session. 160 is useful for long haul TCP */ #define NFSD_MAX_SLOTS_PER_SESSION 160 -/* Maximum number of pages per slot cache entry */ -#define NFSD_PAGES_PER_SLOT 1 -#define NFSD_SLOT_CACHE_SIZE PAGE_SIZE /* Maximum number of operations per session compound */ #define NFSD_MAX_OPS_PER_COMPOUND 16 +/* Maximum session per slot cache size */ +#define NFSD_SLOT_CACHE_SIZE 1024 /* Maximum number of NFSD_SLOT_CACHE_SIZE slots per session */ #define NFSD_CACHE_SIZE_SLOTS_PER_SESSION 32 #define NFSD_MAX_MEM_PER_SESSION \ (NFSD_CACHE_SIZE_SLOTS_PER_SESSION * NFSD_SLOT_CACHE_SIZE) -struct nfsd4_cache_entry { - __be32 ce_status; - struct kvec ce_datav; /* encoded NFSv4.1 data in rq_res.head[0] */ - struct page *ce_respages[NFSD_PAGES_PER_SLOT + 1]; - int ce_cachethis; - short ce_resused; - int ce_opcnt; - int ce_rpchdrlen; -}; - struct nfsd4_slot { - bool sl_inuse; - u32 sl_seqid; - struct nfsd4_cache_entry sl_cache_entry; + bool sl_inuse; + bool sl_cachethis; + u16 sl_opcnt; + u32 sl_seqid; + __be32 sl_status; + u32 sl_datalen; + char sl_data[]; }; struct nfsd4_channel_attrs { @@ -159,7 +152,7 @@ struct nfsd4_session { struct nfs4_sessionid se_sessionid; struct nfsd4_channel_attrs se_fchannel; struct nfsd4_channel_attrs se_bchannel; - struct nfsd4_slot se_slots[]; /* forward channel slots */ + struct nfsd4_slot *se_slots[]; /* forward channel slots */ }; static inline void diff --git a/include/linux/nfsd/xdr4.h b/include/linux/nfsd/xdr4.h index 3f71660..73164c2 100644 --- a/include/linux/nfsd/xdr4.h +++ b/include/linux/nfsd/xdr4.h @@ -51,7 +51,7 @@ struct nfsd4_compound_state { /* For sessions DRC */ struct nfsd4_session *session; struct nfsd4_slot *slot; - __be32 *statp; + __be32 *datap; size_t iovlen; u32 minorversion; u32 status; @@ -472,8 +472,7 @@ static inline bool nfsd4_is_solo_sequence(struct nfsd4_compoundres *resp) static inline bool nfsd4_not_cached(struct nfsd4_compoundres *resp) { - return !resp->cstate.slot->sl_cache_entry.ce_cachethis || - nfsd4_is_solo_sequence(resp); + return !resp->cstate.slot->sl_cachethis || nfsd4_is_solo_sequence(resp); } #define NFS4_SVC_XDRSIZE sizeof(struct nfsd4_compoundargs) -- cgit v0.10.2 From 9c552dd79346f86a3b53e41255c92c6f560b80fb Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 2 Sep 2009 14:00:11 +1000 Subject: drm/crtc: fix mismerge of last patch. We only want to NULL encoder->crtc when it is off. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index eea5e6c..db0237d 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -278,9 +278,9 @@ void drm_helper_disable_unused_functions(struct drm_device *dev) (*encoder_funcs->disable)(encoder); else (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF); + /* disconnector encoder from any connector */ + encoder->crtc = NULL; } - /* disconnector encoder from any connector */ - encoder->crtc = NULL; } list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { -- cgit v0.10.2 From ff6fdbed8f465f796da7ab32cde67e2dfb9e1f8f Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Tue, 1 Sep 2009 03:39:04 +0200 Subject: drm/crtc_helper: avoid NULL-pointer dereference when encoder is NULL Signed-off-by: Maarten Maathuis Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index db0237d..e7e6c25 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -842,7 +842,8 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) /* If the encoder is reused for another connector, then * the appropriate crtc will be set later. */ - connector->encoder->crtc = NULL; + if (connector->encoder) + connector->encoder->crtc = NULL; connector->encoder = new_encoder; } } -- cgit v0.10.2 From 8e498751f2f36074ffa6fc7f0a9ec6e055b350e6 Mon Sep 17 00:00:00 2001 From: "J. Bruce Fields" Date: Wed, 2 Sep 2009 19:31:32 -0400 Subject: nfsd: move some of fh_compose into helper functions Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfsfh.c b/fs/nfsd/nfsfh.c index 8847f3f..78d8ebf 100644 --- a/fs/nfsd/nfsfh.c +++ b/fs/nfsd/nfsfh.c @@ -397,6 +397,40 @@ static inline void _fh_update_old(struct dentry *dentry, fh->ofh_dirino = 0; } +static bool is_root_export(struct svc_export *exp) +{ + return exp->ex_path.dentry == exp->ex_path.dentry->d_sb->s_root; +} + +static struct super_block *exp_sb(struct svc_export *exp) +{ + return exp->ex_path.dentry->d_inode->i_sb; +} + +static bool fsid_type_ok_for_exp(u8 fsid_type, struct svc_export *exp) +{ + switch (fsid_type) { + case FSID_DEV: + if (!old_valid_dev(exp_sb(exp)->s_dev)) + return 0; + /* FALL THROUGH */ + case FSID_MAJOR_MINOR: + case FSID_ENCODE_DEV: + return exp_sb(exp)->s_type->fs_flags & FS_REQUIRES_DEV; + case FSID_NUM: + return exp->ex_flags & NFSEXP_FSID; + case FSID_UUID8: + case FSID_UUID16: + if (!is_root_export(exp)) + return 0; + /* fall through */ + case FSID_UUID4_INUM: + case FSID_UUID16_INUM: + return exp->ex_uuid != NULL; + } + return 1; +} + __be32 fh_compose(struct svc_fh *fhp, struct svc_export *exp, struct dentry *dentry, struct svc_fh *ref_fh) @@ -414,8 +448,7 @@ fh_compose(struct svc_fh *fhp, struct svc_export *exp, struct dentry *dentry, struct inode * inode = dentry->d_inode; struct dentry *parent = dentry->d_parent; __u32 *datap; - dev_t ex_dev = exp->ex_path.dentry->d_inode->i_sb->s_dev; - int root_export = (exp->ex_path.dentry == exp->ex_path.dentry->d_sb->s_root); + dev_t ex_dev = exp_sb(exp)->s_dev; dprintk("nfsd: fh_compose(exp %02x:%02x/%ld %s/%s, ino=%ld)\n", MAJOR(ex_dev), MINOR(ex_dev), @@ -447,49 +480,24 @@ fh_compose(struct svc_fh *fhp, struct svc_export *exp, struct dentry *dentry, goto retry; } - /* Need to check that this type works for this - * export point. As the fsid -> filesystem mapping - * was guided by user-space, there is no guarantee - * that the filesystem actually supports that fsid - * type. If it doesn't we loop around again without - * ref_fh set. + /* + * As the fsid -> filesystem mapping was guided by + * user-space, there is no guarantee that the filesystem + * actually supports that fsid type. If it doesn't we + * loop around again without ref_fh set. */ - switch(fsid_type) { - case FSID_DEV: - if (!old_valid_dev(ex_dev)) - goto retry; - /* FALL THROUGH */ - case FSID_MAJOR_MINOR: - case FSID_ENCODE_DEV: - if (!(exp->ex_path.dentry->d_inode->i_sb->s_type->fs_flags - & FS_REQUIRES_DEV)) - goto retry; - break; - case FSID_NUM: - if (! (exp->ex_flags & NFSEXP_FSID)) - goto retry; - break; - case FSID_UUID8: - case FSID_UUID16: - if (!root_export) - goto retry; - /* fall through */ - case FSID_UUID4_INUM: - case FSID_UUID16_INUM: - if (exp->ex_uuid == NULL) - goto retry; - break; - } + if (!fsid_type_ok_for_exp(fsid_type, exp)) + goto retry; } else if (exp->ex_flags & NFSEXP_FSID) { fsid_type = FSID_NUM; } else if (exp->ex_uuid) { if (fhp->fh_maxsize >= 64) { - if (root_export) + if (is_root_export(exp)) fsid_type = FSID_UUID16; else fsid_type = FSID_UUID16_INUM; } else { - if (root_export) + if (is_root_export(exp)) fsid_type = FSID_UUID8; else fsid_type = FSID_UUID4_INUM; @@ -639,8 +647,7 @@ enum fsid_source fsid_source(struct svc_fh *fhp) case FSID_DEV: case FSID_ENCODE_DEV: case FSID_MAJOR_MINOR: - if (fhp->fh_export->ex_path.dentry->d_inode->i_sb->s_type->fs_flags - & FS_REQUIRES_DEV) + if (exp_sb(fhp->fh_export)->s_type->fs_flags & FS_REQUIRES_DEV) return FSIDSOURCE_DEV; break; case FSID_NUM: -- cgit v0.10.2 From bc6c53d5a1383d5d9632adf33bd03458cfc0869d Mon Sep 17 00:00:00 2001 From: "J. Bruce Fields" Date: Wed, 2 Sep 2009 19:50:40 -0400 Subject: nfsd: move fsid_type choice out of fh_compose More trivial cleanup. Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfsfh.c b/fs/nfsd/nfsfh.c index 78d8ebf..bce0b2b 100644 --- a/fs/nfsd/nfsfh.c +++ b/fs/nfsd/nfsfh.c @@ -431,43 +431,17 @@ static bool fsid_type_ok_for_exp(u8 fsid_type, struct svc_export *exp) return 1; } -__be32 -fh_compose(struct svc_fh *fhp, struct svc_export *exp, struct dentry *dentry, - struct svc_fh *ref_fh) -{ - /* ref_fh is a reference file handle. - * if it is non-null and for the same filesystem, then we should compose - * a filehandle which is of the same version, where possible. - * Currently, that means that if ref_fh->fh_handle.fh_version == 0xca - * Then create a 32byte filehandle using nfs_fhbase_old - * - */ +static void set_version_and_fsid_type(struct svc_fh *fhp, struct svc_export *exp, struct svc_fh *ref_fh) +{ u8 version; - u8 fsid_type = 0; - struct inode * inode = dentry->d_inode; - struct dentry *parent = dentry->d_parent; - __u32 *datap; - dev_t ex_dev = exp_sb(exp)->s_dev; - - dprintk("nfsd: fh_compose(exp %02x:%02x/%ld %s/%s, ino=%ld)\n", - MAJOR(ex_dev), MINOR(ex_dev), - (long) exp->ex_path.dentry->d_inode->i_ino, - parent->d_name.name, dentry->d_name.name, - (inode ? inode->i_ino : 0)); - - /* Choose filehandle version and fsid type based on - * the reference filehandle (if it is in the same export) - * or the export options. - */ - retry: + u8 fsid_type; +retry: version = 1; if (ref_fh && ref_fh->fh_export == exp) { version = ref_fh->fh_handle.fh_version; fsid_type = ref_fh->fh_handle.fh_fsid_type; - if (ref_fh == fhp) - fh_put(ref_fh); ref_fh = NULL; switch (version) { @@ -502,11 +476,44 @@ fh_compose(struct svc_fh *fhp, struct svc_export *exp, struct dentry *dentry, else fsid_type = FSID_UUID4_INUM; } - } else if (!old_valid_dev(ex_dev)) + } else if (!old_valid_dev(exp_sb(exp)->s_dev)) /* for newer device numbers, we must use a newer fsid format */ fsid_type = FSID_ENCODE_DEV; else fsid_type = FSID_DEV; + fhp->fh_handle.fh_version = version; + if (version) + fhp->fh_handle.fh_fsid_type = fsid_type; +} + +__be32 +fh_compose(struct svc_fh *fhp, struct svc_export *exp, struct dentry *dentry, + struct svc_fh *ref_fh) +{ + /* ref_fh is a reference file handle. + * if it is non-null and for the same filesystem, then we should compose + * a filehandle which is of the same version, where possible. + * Currently, that means that if ref_fh->fh_handle.fh_version == 0xca + * Then create a 32byte filehandle using nfs_fhbase_old + * + */ + + struct inode * inode = dentry->d_inode; + struct dentry *parent = dentry->d_parent; + __u32 *datap; + dev_t ex_dev = exp_sb(exp)->s_dev; + + dprintk("nfsd: fh_compose(exp %02x:%02x/%ld %s/%s, ino=%ld)\n", + MAJOR(ex_dev), MINOR(ex_dev), + (long) exp->ex_path.dentry->d_inode->i_ino, + parent->d_name.name, dentry->d_name.name, + (inode ? inode->i_ino : 0)); + + /* Choose filehandle version and fsid type based on + * the reference filehandle (if it is in the same export) + * or the export options. + */ + set_version_and_fsid_type(fhp, exp, ref_fh); if (ref_fh == fhp) fh_put(ref_fh); @@ -524,7 +531,7 @@ fh_compose(struct svc_fh *fhp, struct svc_export *exp, struct dentry *dentry, fhp->fh_export = exp; cache_get(&exp->h); - if (version == 0xca) { + if (fhp->fh_handle.fh_version == 0xca) { /* old style filehandle please */ memset(&fhp->fh_handle.fh_base, 0, NFS_FHSIZE); fhp->fh_handle.fh_size = NFS_FHSIZE; @@ -538,15 +545,13 @@ fh_compose(struct svc_fh *fhp, struct svc_export *exp, struct dentry *dentry, _fh_update_old(dentry, exp, &fhp->fh_handle); } else { int len; - fhp->fh_handle.fh_version = 1; fhp->fh_handle.fh_auth_type = 0; datap = fhp->fh_handle.fh_auth+0; - fhp->fh_handle.fh_fsid_type = fsid_type; - mk_fsid(fsid_type, datap, ex_dev, + mk_fsid(fhp->fh_handle.fh_fsid_type, datap, ex_dev, exp->ex_path.dentry->d_inode->i_ino, exp->ex_fsid, exp->ex_uuid); - len = key_len(fsid_type); + len = key_len(fhp->fh_handle.fh_fsid_type); datap += len/4; fhp->fh_handle.fh_size = 4 + len; -- cgit v0.10.2 From 2671a4bf3516757ca028c139a7902a50f2bd994a Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Wed, 2 Sep 2009 16:48:32 -0400 Subject: NFSd: Fix filehandle leak in exp_pseudoroot() and nfsd4_path() nfsd4_path() allocates a temporary filehandle and then fails to free it before the function exits, leaking reference counts to the dentry and export that it refers to. Also, nfsd4_lookupp() puts the result of exp_pseudoroot() in a temporary filehandle which it releases on success of exp_pseudoroot() but not on failure; fix exp_pseudoroot to ensure that on failure it releases the filehandle before returning. Signed-off-by: Trond Myklebust Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/export.c b/fs/nfsd/export.c index d946264..984a5eb 100644 --- a/fs/nfsd/export.c +++ b/fs/nfsd/export.c @@ -1341,6 +1341,8 @@ exp_pseudoroot(struct svc_rqst *rqstp, struct svc_fh *fhp) if (rv) goto out; rv = check_nfsd_access(exp, rqstp); + if (rv) + fh_put(fhp); out: exp_put(exp); return rv; diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c index 00ed16a..0fbd50c 100644 --- a/fs/nfsd/nfs4xdr.c +++ b/fs/nfsd/nfs4xdr.c @@ -1599,7 +1599,8 @@ static __be32 nfsd4_encode_fs_location4(struct nfsd4_fs_location *location, static char *nfsd4_path(struct svc_rqst *rqstp, struct svc_export *exp, __be32 *stat) { struct svc_fh tmp_fh; - char *path, *rootpath; + char *path = NULL, *rootpath; + size_t rootlen; fh_init(&tmp_fh, NFS4_FHSIZE); *stat = exp_pseudoroot(rqstp, &tmp_fh); @@ -1609,14 +1610,18 @@ static char *nfsd4_path(struct svc_rqst *rqstp, struct svc_export *exp, __be32 * path = exp->ex_pathname; - if (strncmp(path, rootpath, strlen(rootpath))) { + rootlen = strlen(rootpath); + if (strncmp(path, rootpath, rootlen)) { dprintk("nfsd: fs_locations failed;" "%s is not contained in %s\n", path, rootpath); *stat = nfserr_notsupp; - return NULL; + path = NULL; + goto out; } - - return path + strlen(rootpath); + path += rootlen; +out: + fh_put(&tmp_fh); + return path; } /* -- cgit v0.10.2 From 492e1501431e0d24c5b46933fdcb60639eacded7 Mon Sep 17 00:00:00 2001 From: Mika Korhonen Date: Tue, 9 Jun 2009 21:52:35 +0300 Subject: mtd: OneNAND: spelling fixes Signed-off-by: Mika Korhonen Acked-by: Kyungmin Park Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 6e82909..ff66e43 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -1191,7 +1191,7 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, /* * Chip boundary handling in DDP * Now we issued chip 1 read and pointed chip 1 - * bufferam so we have to point chip 0 bufferam. + * bufferram so we have to point chip 0 bufferram. */ if (ONENAND_IS_DDP(this) && unlikely(from == (this->chipsize >> 1))) { @@ -1867,8 +1867,8 @@ static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to, ONENAND_SET_NEXT_BUFFERRAM(this); /* - * 2 PLANE, MLC, and Flex-OneNAND doesn't support - * write-while-programe feature. + * 2 PLANE, MLC, and Flex-OneNAND do not support + * write-while-program feature. */ if (!ONENAND_IS_2PLANE(this) && !first) { ONENAND_SET_PREV_BUFFERRAM(this); @@ -1879,7 +1879,7 @@ static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to, onenand_update_bufferram(mtd, prev, !ret && !prev_subpage); if (ret) { written -= prevlen; - printk(KERN_ERR "onenand_write_ops_nolock: write filaed %d\n", ret); + printk(KERN_ERR "onenand_write_ops_nolock: write failed %d\n", ret); break; } @@ -1905,7 +1905,7 @@ static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to, /* In partial page write we don't update bufferram */ onenand_update_bufferram(mtd, to, !ret && !subpage); if (ret) { - printk(KERN_ERR "onenand_write_ops_nolock: write filaed %d\n", ret); + printk(KERN_ERR "onenand_write_ops_nolock: write failed %d\n", ret); break; } @@ -2201,7 +2201,7 @@ static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) /* Grab the lock and see if the device is available */ onenand_get_device(mtd, FL_ERASING); - /* Loop throught the pages */ + /* Loop through the blocks */ instr->state = MTD_ERASING; while (len) { @@ -2328,7 +2328,7 @@ static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) if (bbm->bbt) bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); - /* We write two bytes, so we dont have to mess with 16 bit access */ + /* We write two bytes, so we don't have to mess with 16-bit access */ ofs += mtd->oobsize + (bbm->badblockpos & ~0x01); /* FIXME : What to do when marking SLC block in partition * with MLC erasesize? For now, it is not advisable to @@ -2557,7 +2557,7 @@ static void onenand_unlock_all(struct mtd_info *mtd) #ifdef CONFIG_MTD_ONENAND_OTP -/* Interal OTP operation */ +/* Internal OTP operation */ typedef int (*otp_op_t)(struct mtd_info *mtd, loff_t form, size_t len, size_t *retlen, u_char *buf); @@ -2921,7 +2921,7 @@ static void onenand_check_features(struct mtd_info *mtd) this->options |= ONENAND_HAS_2PLANE; case ONENAND_DEVICE_DENSITY_2Gb: - /* 2Gb DDP don't have 2 plane */ + /* 2Gb DDP does not have 2 plane */ if (!ONENAND_IS_DDP(this)) this->options |= ONENAND_HAS_2PLANE; this->options |= ONENAND_HAS_UNLOCK_ALL; @@ -3364,7 +3364,7 @@ static int onenand_probe(struct mtd_info *mtd) /* It's real page size */ this->writesize = mtd->writesize; - /* REVIST: Multichip handling */ + /* REVISIT: Multichip handling */ if (FLEXONENAND(this)) flexonenand_get_size(mtd); -- cgit v0.10.2 From 652696efce135559b98ee5a3d7899295e8d553fa Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Wed, 24 Jun 2009 12:03:51 +0900 Subject: mtd: OneNAND: 4-bit ECC status macros Define ECC status for 4-bit ECC status Signed-off-by: Kyungmin Park Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h index 86a6bbe..acadbf5 100644 --- a/include/linux/mtd/onenand_regs.h +++ b/include/linux/mtd/onenand_regs.h @@ -207,6 +207,9 @@ #define ONENAND_ECC_2BIT (1 << 1) #define ONENAND_ECC_2BIT_ALL (0xAAAA) #define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010) +#define ONENAND_ECC_3BIT (1 << 2) +#define ONENAND_ECC_4BIT (1 << 3) +#define ONENAND_ECC_4BIT_UNCORRECTABLE (0x1010) /* * One-Time Programmable (OTP) -- cgit v0.10.2 From b8b3ee9aabbc3e6fc7ef025d861dd780b84eb6c5 Mon Sep 17 00:00:00 2001 From: vimal singh Date: Thu, 9 Jul 2009 20:41:22 +0530 Subject: mtd: nand: remove repeated comment, fix spelling Singed-off-by: Vimal Singh Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 8c21b89..4a5a329 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -688,8 +688,7 @@ nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) retry: spin_lock(lock); - /* Hardware controller shared among independend devices */ - /* Hardware controller shared among independend devices */ + /* Hardware controller shared among independent devices */ if (!chip->controller->active) chip->controller->active = chip; -- cgit v0.10.2 From 20d8e2489d619ac4f14c46ca376655fc06b3c1ff Mon Sep 17 00:00:00 2001 From: vimal singh Date: Tue, 7 Jul 2009 15:49:49 +0530 Subject: mtd: nand_base: use __func__ instead of typing names Correcting debug prints by removing function names from print messages and using '__func__' macro instead. Function names were wrong in few places. Signed-off-by: Vimal Singh Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 4a5a329..268c9a4 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1412,8 +1412,8 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, int len; uint8_t *buf = ops->oobbuf; - DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n", - (unsigned long long)from, readlen); + DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n", + __func__, (unsigned long long)from, readlen); if (ops->mode == MTD_OOB_AUTO) len = chip->ecc.layout->oobavail; @@ -1421,8 +1421,8 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, len = mtd->oobsize; if (unlikely(ops->ooboffs >= len)) { - DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " - "Attempt to start read outside oob\n"); + DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read " + "outside oob\n", __func__); return -EINVAL; } @@ -1430,8 +1430,8 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, if (unlikely(from >= mtd->size || ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - (from >> chip->page_shift)) * len)) { - DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " - "Attempt read beyond end of device\n"); + DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end " + "of device\n", __func__); return -EINVAL; } @@ -1505,8 +1505,8 @@ static int nand_read_oob(struct mtd_info *mtd, loff_t from, /* Do not allow reads past end of device */ if (ops->datbuf && (from + ops->len) > mtd->size) { - DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " - "Attempt read beyond end of device\n"); + DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read " + "beyond end of device\n", __func__); return -EINVAL; } @@ -1815,8 +1815,8 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, /* reject writes, which are not page aligned */ if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { - printk(KERN_NOTICE "nand_write: " - "Attempt to write not page aligned data\n"); + printk(KERN_NOTICE "%s: Attempt to write not " + "page aligned data\n", __func__); return -EINVAL; } @@ -1943,8 +1943,8 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, int chipnr, page, status, len; struct nand_chip *chip = mtd->priv; - DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", - (unsigned int)to, (int)ops->ooblen); + DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n", + __func__, (unsigned int)to, (int)ops->ooblen); if (ops->mode == MTD_OOB_AUTO) len = chip->ecc.layout->oobavail; @@ -1953,14 +1953,14 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, /* Do not allow write past end of page */ if ((ops->ooboffs + ops->ooblen) > len) { - DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " - "Attempt to write past end of page\n"); + DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write " + "past end of page\n", __func__); return -EINVAL; } if (unlikely(ops->ooboffs >= len)) { - DEBUG(MTD_DEBUG_LEVEL0, "nand_do_write_oob: " - "Attempt to start write outside oob\n"); + DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start " + "write outside oob\n", __func__); return -EINVAL; } @@ -1969,8 +1969,8 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, ops->ooboffs + ops->ooblen > ((mtd->size >> chip->page_shift) - (to >> chip->page_shift)) * len)) { - DEBUG(MTD_DEBUG_LEVEL0, "nand_do_write_oob: " - "Attempt write beyond end of device\n"); + DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " + "end of device\n", __func__); return -EINVAL; } @@ -2025,8 +2025,8 @@ static int nand_write_oob(struct mtd_info *mtd, loff_t to, /* Do not allow writes past end of device */ if (ops->datbuf && (to + ops->len) > mtd->size) { - DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " - "Attempt write beyond end of device\n"); + DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " + "end of device\n", __func__); return -EINVAL; } @@ -2116,26 +2116,27 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, unsigned int bbt_masked_page = 0xffffffff; loff_t len; - DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, len = %llu\n", - (unsigned long long)instr->addr, (unsigned long long)instr->len); + DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", + __func__, (unsigned long long)instr->addr, + (unsigned long long)instr->len); /* Start address must align on block boundary */ if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) { - DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); + DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__); return -EINVAL; } /* Length must align on block boundary */ if (instr->len & ((1 << chip->phys_erase_shift) - 1)) { - DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " - "Length not block aligned\n"); + DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n", + __func__); return -EINVAL; } /* Do not allow erase past end of device */ if ((instr->len + instr->addr) > mtd->size) { - DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " - "Erase past end of device\n"); + DEBUG(MTD_DEBUG_LEVEL0, "%s: Erase past end of device\n", + __func__); return -EINVAL; } @@ -2156,8 +2157,8 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, /* Check, if it is write protected */ if (nand_check_wp(mtd)) { - DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " - "Device is write protected!!!\n"); + DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", + __func__); instr->state = MTD_ERASE_FAILED; goto erase_exit; } @@ -2182,8 +2183,8 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, */ if (nand_block_checkbad(mtd, ((loff_t) page) << chip->page_shift, 0, allowbbt)) { - printk(KERN_WARNING "nand_erase: attempt to erase a " - "bad block at page 0x%08x\n", page); + printk(KERN_WARNING "%s: attempt to erase a bad block " + "at page 0x%08x\n", __func__, page); instr->state = MTD_ERASE_FAILED; goto erase_exit; } @@ -2210,8 +2211,8 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, /* See if block erase succeeded */ if (status & NAND_STATUS_FAIL) { - DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " - "Failed erase, page 0x%08x\n", page); + DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, " + "page 0x%08x\n", __func__, page); instr->state = MTD_ERASE_FAILED; instr->fail_addr = ((loff_t)page << chip->page_shift); @@ -2271,9 +2272,9 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, if (!rewrite_bbt[chipnr]) continue; /* update the BBT for chip */ - DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt " - "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr], - chip->bbt_td->pages[chipnr]); + DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt " + "(%d:0x%0llx 0x%0x)\n", __func__, chipnr, + rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]); nand_update_bbt(mtd, rewrite_bbt[chipnr]); } @@ -2291,7 +2292,7 @@ static void nand_sync(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; - DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n"); + DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__); /* Grab the lock and see if the device is available */ nand_get_device(chip, mtd, FL_SYNCING); @@ -2355,8 +2356,8 @@ static void nand_resume(struct mtd_info *mtd) if (chip->state == FL_PM_SUSPENDED) nand_release_device(mtd); else - printk(KERN_ERR "nand_resume() called for a chip which is not " - "in suspended state\n"); + printk(KERN_ERR "%s called for a chip which is not " + "in suspended state\n", __func__); } /* @@ -2857,7 +2858,8 @@ int nand_scan(struct mtd_info *mtd, int maxchips) /* Many callers got this wrong, so check for it for a while... */ if (!mtd->owner && caller_is_module()) { - printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n"); + printk(KERN_CRIT "%s called with NULL mtd->owner!\n", + __func__); BUG(); } -- cgit v0.10.2 From dff1550986a4c0e2a4e857c9085ef3cb66b2cec5 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 6 Jul 2009 12:02:08 +0200 Subject: mtd: fix a typo in comment mtdblock erase_write(): fix typo in comment Signed-off-by: Matthias Kaehlcke Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/mtdblock.c b/drivers/mtd/mtdblock.c index 77db5ce..bcfb177 100644 --- a/drivers/mtd/mtdblock.c +++ b/drivers/mtd/mtdblock.c @@ -84,7 +84,7 @@ static int erase_write (struct mtd_info *mtd, unsigned long pos, remove_wait_queue(&wait_q, &wait); /* - * Next, writhe data to flash. + * Next, write the data to flash. */ ret = mtd->write(mtd, pos, len, &retlen, buf); -- cgit v0.10.2 From 44a1f2085e8fe07b3aecdab7c391ca057d75da0f Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Tue, 30 Jun 2009 15:38:00 -0400 Subject: mtd: ep93xx: cleanup includes in ts7250 nand driver 1. should be included not 2. add platform specific header Signed-off-by: H Hartley Sweeten Cc: Lennert Buytenhek Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/nand/ts7250.c b/drivers/mtd/nand/ts7250.c index 2c410a0..0f5562a 100644 --- a/drivers/mtd/nand/ts7250.c +++ b/drivers/mtd/nand/ts7250.c @@ -24,8 +24,11 @@ #include #include #include -#include +#include + #include +#include + #include #include -- cgit v0.10.2 From 2763c508a3c8f8ec5d6df4e8c63d5e2a5a7d3954 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 17 Jul 2009 17:54:14 +0200 Subject: mtd: physmap_of: use resource_size Signed-off-by: Wolfram Sang Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/maps/physmap_of.c b/drivers/mtd/maps/physmap_of.c index 39d357b..f223f3f 100644 --- a/drivers/mtd/maps/physmap_of.c +++ b/drivers/mtd/maps/physmap_of.c @@ -190,6 +190,7 @@ static int __devinit of_flash_probe(struct of_device *dev, const u32 *p; int reg_tuple_size; struct mtd_info **mtd_list = NULL; + resource_size_t res_size; reg_tuple_size = (of_n_addr_cells(dp) + of_n_size_cells(dp)) * sizeof(u32); @@ -233,8 +234,8 @@ static int __devinit of_flash_probe(struct of_device *dev, (unsigned long long)res.end); err = -EBUSY; - info->list[i].res = request_mem_region(res.start, res.end - - res.start + 1, + res_size = resource_size(&res); + info->list[i].res = request_mem_region(res.start, res_size, dev_name(&dev->dev)); if (!info->list[i].res) goto err_out; @@ -249,7 +250,7 @@ static int __devinit of_flash_probe(struct of_device *dev, info->list[i].map.name = dev_name(&dev->dev); info->list[i].map.phys = res.start; - info->list[i].map.size = res.end - res.start + 1; + info->list[i].map.size = res_size; info->list[i].map.bankwidth = *width; err = -ENOMEM; -- cgit v0.10.2 From 76d6a4791609e4d14b411a513c7648b19b258d8f Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 17 Jul 2009 17:47:37 +0200 Subject: mtd: plat-ram: use resource_size Signed-off-by: Wolfram Sang Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/maps/plat-ram.c b/drivers/mtd/maps/plat-ram.c index 49c9ece..dafb919 100644 --- a/drivers/mtd/maps/plat-ram.c +++ b/drivers/mtd/maps/plat-ram.c @@ -175,7 +175,7 @@ static int platram_probe(struct platform_device *pdev) /* setup map parameters */ info->map.phys = res->start; - info->map.size = (res->end - res->start) + 1; + info->map.size = resource_size(res); info->map.name = pdata->mapname != NULL ? (char *)pdata->mapname : (char *)pdev->name; info->map.bankwidth = pdata->bankwidth; -- cgit v0.10.2 From 0ffd24fc7f82a0b594250e5f221340be4c322cda Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 18 Jul 2009 14:10:44 +0100 Subject: mtd: afs: fix build warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/mtd/afs.c:244: warning: format ‘%5d’ expects type ‘int’, but argument 4 has type ‘uint64_t’ [dwmw2: fix incorrect 'KB' too] Signed-off-by: Russell King Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/afs.c b/drivers/mtd/afs.c index d072ca5..cec7ab9 100644 --- a/drivers/mtd/afs.c +++ b/drivers/mtd/afs.c @@ -239,7 +239,7 @@ static int parse_afs_partitions(struct mtd_info *mtd, parts[idx].offset = img_ptr; parts[idx].mask_flags = 0; - printk(" mtd%d: at 0x%08x, %5dKB, %8u, %s\n", + printk(" mtd%d: at 0x%08x, %5lluKiB, %8u, %s\n", idx, img_ptr, parts[idx].size / 1024, iis.imageNumber, str); -- cgit v0.10.2 From 05dd180709fca14fbae617c0dab1bed56be334fc Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Sun, 19 Jul 2009 21:19:08 -0400 Subject: mtd: correct typo "MTD_DATAFLASH_VERIFY_WRITE" Fix the misspelling to match the actual config variable defined in drivers/mtd/devi ces/Kconfig: config MTD_DATAFLASH_WRITE_VERIFY bool "Verify DataFlash page writes" depends on MTD_DATAFLASH Signed-off-by: Robert P. J. Day Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/devices/mtd_dataflash.c b/drivers/mtd/devices/mtd_dataflash.c index 43976aa..70a7369 100644 --- a/drivers/mtd/devices/mtd_dataflash.c +++ b/drivers/mtd/devices/mtd_dataflash.c @@ -401,7 +401,7 @@ static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, (void) dataflash_waitready(priv->spi); -#ifdef CONFIG_MTD_DATAFLASH_VERIFY_WRITE +#ifdef CONFIG_MTD_DATAFLASH_WRITE_VERIFY /* (3) Compare to Buffer1 */ addr = pageaddr << priv->page_offset; @@ -430,7 +430,7 @@ static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, } else status = 0; -#endif /* CONFIG_MTD_DATAFLASH_VERIFY_WRITE */ +#endif /* CONFIG_MTD_DATAFLASH_WRITE_VERIFY */ remaining = remaining - writelen; pageaddr++; -- cgit v0.10.2 From 9a73290d7735c0671d1d2379ed40025db8b773d0 Mon Sep 17 00:00:00 2001 From: "Singh, Vimal" Date: Fri, 12 Dec 2008 00:10:57 +0000 Subject: mtd: nand_base: allow drivers to choose ECC block size This patch allows core driver to choose ECC block size in sw ecc case. Signed-off-by: Vimal Singh Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 268c9a4..4c5e8a7 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2728,7 +2728,8 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.write_page_raw = nand_write_page_raw; chip->ecc.read_oob = nand_read_oob_std; chip->ecc.write_oob = nand_write_oob_std; - chip->ecc.size = 256; + if (!chip->ecc.size) + chip->ecc.size = 256; chip->ecc.bytes = 3; break; -- cgit v0.10.2 From ad4fbc7921bd7cca108ecc1340a014e91ecc8536 Mon Sep 17 00:00:00 2001 From: vimal singh Date: Thu, 30 Jul 2009 20:54:27 +0530 Subject: mtd: physmap_of: fix incorrect check This patch fixes a spelling error that has resulted from copy and pasting. The location of the error was found using a semantic patch but the semantic patch was not trying to find these errors. After looking things over it seemed logical that this change was needed. The patch also makes sure mtd_list is not being freed if it has not been allocated Signed-off-by: Stoyan Gaydarov Signed-off-by: Vimal Singh Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/maps/physmap_of.c b/drivers/mtd/maps/physmap_of.c index f223f3f..e828d58 100644 --- a/drivers/mtd/maps/physmap_of.c +++ b/drivers/mtd/maps/physmap_of.c @@ -205,7 +205,7 @@ static int __devinit of_flash_probe(struct of_device *dev, dev_err(&dev->dev, "Malformed reg property on %s\n", dev->node->full_name); err = -EINVAL; - goto err_out; + goto err_flash_remove; } count /= reg_tuple_size; @@ -213,14 +213,14 @@ static int __devinit of_flash_probe(struct of_device *dev, info = kzalloc(sizeof(struct of_flash) + sizeof(struct of_flash_list) * count, GFP_KERNEL); if (!info) - goto err_out; - - mtd_list = kzalloc(sizeof(struct mtd_info) * count, GFP_KERNEL); - if (!info) - goto err_out; + goto err_flash_remove; dev_set_drvdata(&dev->dev, info); + mtd_list = kzalloc(sizeof(struct mtd_info) * count, GFP_KERNEL); + if (!mtd_list) + goto err_flash_remove; + for (i = 0; i < count; i++) { err = -ENXIO; if (of_address_to_resource(dp, i, &res)) { @@ -339,6 +339,7 @@ static int __devinit of_flash_probe(struct of_device *dev, err_out: kfree(mtd_list); +err_flash_remove: of_flash_remove(dev); return err; -- cgit v0.10.2 From 269c0ee66367b11de9758ee64ea039843f0c7cad Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Fri, 31 Jul 2009 14:47:58 +0200 Subject: slram: Read buffer overflow map[count] is checked before count < SLRAM_MAX_DEVICES_PARAMS Signed-off-by: Roel Kluin Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/devices/slram.c b/drivers/mtd/devices/slram.c index 00248e8..239500b 100644 --- a/drivers/mtd/devices/slram.c +++ b/drivers/mtd/devices/slram.c @@ -341,7 +341,7 @@ static int init_slram(void) #else int count; - for (count = 0; (map[count]) && (count < SLRAM_MAX_DEVICES_PARAMS); + for (count = 0; count < SLRAM_MAX_DEVICES_PARAMS && map[count]; count++) { } -- cgit v0.10.2 From c6f7e7beb9e6a64816f534a3a0dd0cfa4937f1fe Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Fri, 31 Jul 2009 16:21:01 +0200 Subject: mtd: tests: fix read buffer overflows Check whether index is within bounds before testing the element. Signed-off-by: Roel Kluin Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/tests/mtd_oobtest.c b/drivers/mtd/tests/mtd_oobtest.c index a18e8d2..5553cd4 100644 --- a/drivers/mtd/tests/mtd_oobtest.c +++ b/drivers/mtd/tests/mtd_oobtest.c @@ -512,7 +512,7 @@ static int __init mtd_oobtest_init(void) goto out; addr0 = 0; - for (i = 0; bbt[i] && i < ebcnt; ++i) + for (i = 0; i < ebcnt && bbt[i]; ++i) addr0 += mtd->erasesize; /* Attempt to write off end of OOB */ diff --git a/drivers/mtd/tests/mtd_pagetest.c b/drivers/mtd/tests/mtd_pagetest.c index 9648818..103cac4 100644 --- a/drivers/mtd/tests/mtd_pagetest.c +++ b/drivers/mtd/tests/mtd_pagetest.c @@ -116,11 +116,11 @@ static int verify_eraseblock(int ebnum) loff_t addr = ebnum * mtd->erasesize; addr0 = 0; - for (i = 0; bbt[i] && i < ebcnt; ++i) + for (i = 0; i < ebcnt && bbt[i]; ++i) addr0 += mtd->erasesize; addrn = mtd->size; - for (i = 0; bbt[ebcnt - i - 1] && i < ebcnt; ++i) + for (i = 0; i < ebcnt && bbt[ebcnt - i - 1]; ++i) addrn -= mtd->erasesize; set_random_data(writebuf, mtd->erasesize); @@ -219,11 +219,11 @@ static int crosstest(void) memset(pp1, 0, pgsize * 4); addr0 = 0; - for (i = 0; bbt[i] && i < ebcnt; ++i) + for (i = 0; i < ebcnt && bbt[i]; ++i) addr0 += mtd->erasesize; addrn = mtd->size; - for (i = 0; bbt[ebcnt - i - 1] && i < ebcnt; ++i) + for (i = 0; i < ebcnt && bbt[ebcnt - i - 1]; ++i) addrn -= mtd->erasesize; /* Read 2nd-to-last page to pp1 */ @@ -317,7 +317,7 @@ static int erasecrosstest(void) ebnum = 0; addr0 = 0; - for (i = 0; bbt[i] && i < ebcnt; ++i) { + for (i = 0; i < ebcnt && bbt[i]; ++i) { addr0 += mtd->erasesize; ebnum += 1; } @@ -413,7 +413,7 @@ static int erasetest(void) ebnum = 0; addr0 = 0; - for (i = 0; bbt[i] && i < ebcnt; ++i) { + for (i = 0; i < ebcnt && bbt[i]; ++i) { addr0 += mtd->erasesize; ebnum += 1; } -- cgit v0.10.2 From b0469ea785d12a6c025fa213293d608fc41405fe Mon Sep 17 00:00:00 2001 From: Siddarth Gore Date: Tue, 4 Aug 2009 08:42:08 +0530 Subject: mtd: m25p80: add support for 3 Macronix flash chips Signed-off-by: Siddarth Gore Signed-off-by: Nicolas Pitre Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index 10ed195..6d8d265 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -501,7 +501,10 @@ static struct flash_info __devinitdata m25p_data [] = { { "at26df321", 0x1f4701, 0, 64 * 1024, 64, SECT_4K, }, /* Macronix */ + { "mx25l3205d", 0xc22016, 0, 64 * 1024, 64, }, + { "mx25l6405d", 0xc22017, 0, 64 * 1024, 128, }, { "mx25l12805d", 0xc22018, 0, 64 * 1024, 256, }, + { "mx25l12855e", 0xc22618, 0, 64 * 1024, 256, }, /* Spansion -- single (large) sector size only, at least * for the chips listed here (without boot sectors). -- cgit v0.10.2 From 0acfe530a2be9192861b84566625ba9b95703226 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 7 Aug 2009 12:34:48 +0900 Subject: mtd: onenand: select MTD_PARTITIONS All of the onenand drivers depend on mtd partition support being compiled in, so just select it. Fixes up build breakage: drivers/built-in.o: In function `generic_onenand_remove': generic.c:(.devexit.text+0x80): undefined reference to `del_mtd_partitions' Reported-by: Randy Dunlap Signed-off-by: Paul Mundt Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/onenand/Kconfig b/drivers/mtd/onenand/Kconfig index 79fa79e..3a094d1 100644 --- a/drivers/mtd/onenand/Kconfig +++ b/drivers/mtd/onenand/Kconfig @@ -5,6 +5,7 @@ menuconfig MTD_ONENAND tristate "OneNAND Device Support" depends on MTD + select MTD_PARTITIONS help This enables support for accessing all type of OneNAND flash devices. For further information see @@ -66,7 +67,6 @@ config MTD_ONENAND_2X_PROGRAM config MTD_ONENAND_SIM tristate "OneNAND simulator support" - depends on MTD_PARTITIONS help The simulator may simulate various OneNAND flash chips for the OneNAND MTD layer. -- cgit v0.10.2 From fca910883324d437a24d447b08f524fa19261a94 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Thu, 6 Aug 2009 16:05:32 -0700 Subject: mtd: make few symbols static Make mtd_group and mtd_groups static since they are only used in this file. [Amended by Artem Bityutskiy] Signed-off-by: H Hartley Sweeten Signed-off-by: Andrew Morton Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 00ebf7a..3f559c0 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -213,11 +213,11 @@ static struct attribute *mtd_attrs[] = { NULL, }; -struct attribute_group mtd_group = { +static struct attribute_group mtd_group = { .attrs = mtd_attrs, }; -struct attribute_group *mtd_groups[] = { +static struct attribute_group *mtd_groups[] = { &mtd_group, NULL, }; -- cgit v0.10.2 From 2c78c44362bc9b7c715a3c2119b89a407c1cb739 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Mon, 10 Aug 2009 10:16:37 +0200 Subject: mtd: pmcmsp-flash: fix error paths in init_msp_flash Cleanin up after errors in init_msp_flash(). Also cleanup_msp_flash() attempts to determine the size of msp_flash with `sizeof(msp_flash) / sizeof(struct mtd_info **)' This will not work since msp_flash is not an array. Signed-off-by: Roel Kluin Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse diff --git a/drivers/mtd/maps/pmcmsp-flash.c b/drivers/mtd/maps/pmcmsp-flash.c index 4768bd5..c8fd8da 100644 --- a/drivers/mtd/maps/pmcmsp-flash.c +++ b/drivers/mtd/maps/pmcmsp-flash.c @@ -50,7 +50,7 @@ static int fcnt; static int __init init_msp_flash(void) { - int i, j; + int i, j, ret = -ENOMEM; int offset, coff; char *env; int pcnt; @@ -75,14 +75,16 @@ static int __init init_msp_flash(void) printk(KERN_NOTICE "Found %d PMC flash devices\n", fcnt); msp_flash = kmalloc(fcnt * sizeof(struct map_info *), GFP_KERNEL); + if (!msp_flash) + return -ENOMEM; + msp_parts = kmalloc(fcnt * sizeof(struct mtd_partition *), GFP_KERNEL); + if (!msp_parts) + goto free_msp_flash; + msp_maps = kcalloc(fcnt, sizeof(struct mtd_info), GFP_KERNEL); - if (!msp_flash || !msp_parts || !msp_maps) { - kfree(msp_maps); - kfree(msp_parts); - kfree(msp_flash); - return -ENOMEM; - } + if (!msp_maps) + goto free_msp_parts; /* loop over the flash devices, initializing each */ for (i = 0; i < fcnt; i++) { @@ -100,13 +102,18 @@ static int __init init_msp_flash(void) msp_parts[i] = kcalloc(pcnt, sizeof(struct mtd_partition), GFP_KERNEL); + if (!msp_parts[i]) + goto cleanup_loop; /* now initialize the devices proper */ flash_name[5] = '0' + i; env = prom_getenv(flash_name); - if (sscanf(env, "%x:%x", &addr, &size) < 2) - return -ENXIO; + if (sscanf(env, "%x:%x", &addr, &size) < 2) { + ret = -ENXIO; + kfree(msp_parts[i]); + goto cleanup_loop; + } addr = CPHYSADDR(addr); printk(KERN_NOTICE @@ -122,13 +129,23 @@ static int __init init_msp_flash(void) */ if (size > CONFIG_MSP_FLASH_MAP_LIMIT) size = CONFIG_MSP_FLASH_MAP_LIMIT; + msp_maps[i].virt = ioremap(addr, size); + if (msp_maps[i].virt == NULL) { + ret = -ENXIO; + kfree(msp_parts[i]); + goto cleanup_loop; + } + msp_maps[i].bankwidth = 1; - msp_maps[i].name = strncpy(kmalloc(7, GFP_KERNEL), - flash_name, 7); + msp_maps[i].name = kmalloc(7, GFP_KERNEL); + if (!msp_maps[i].name) { + iounmap(msp_maps[i].virt); + kfree(msp_parts[i]); + goto cleanup_loop; + } - if (msp_maps[i].virt == NULL) - return -ENXIO; + msp_maps[i].name = strncpy(msp_maps[i].name, flash_name, 7); for (j = 0; j < pcnt; j++) { part_name[5] = '0' + i; @@ -136,8 +153,14 @@ static int __init init_msp_flash(void) env = prom_getenv(part_name); - if (sscanf(env, "%x:%x:%n", &offset, &size, &coff) < 2) - return -ENXIO; + if (sscanf(env, "%x:%x:%n", &offset, &size, + &coff) < 2) { + ret = -ENXIO; + kfree(msp_maps[i].name); + iounmap(msp_maps[i].virt); + kfree(msp_parts[i]); + goto cleanup_loop; + } msp_parts[i][j].size = size; msp_parts[i][j].offset = offset; @@ -152,18 +175,37 @@ static int __init init_msp_flash(void) add_mtd_partitions(msp_flash[i], msp_parts[i], pcnt); } else { printk(KERN_ERR "map probe failed for flash\n"); - return -ENXIO; + ret = -ENXIO; + kfree(msp_maps[i].name); + iounmap(msp_maps[i].virt); + kfree(msp_parts[i]); + goto cleanup_loop; } } return 0; + +cleanup_loop: + while (i--) { + del_mtd_partitions(msp_flash[i]); + map_destroy(msp_flash[i]); + kfree(msp_maps[i].name); + iounmap(msp_maps[i].virt); + kfree(msp_parts[i]); + } + kfree(msp_maps); +free_msp_parts: + kfree(msp_parts); +free_msp_flash: + kfree(msp_flash); + return ret; } static void __exit cleanup_msp_flash(void) { int i; - for (i = 0; i < sizeof(msp_flash) / sizeof(struct mtd_info **); i++) { + for (i = 0; i < fcnt; i++) { del_mtd_partitions(msp_flash[i]); map_destroy(msp_flash[i]); iounmap((void *)msp_maps[i].virt); -- cgit v0.10.2 From 91e0955b57377578f7555b5d0f2a21040691004b Mon Sep 17 00:00:00 2001 From: Gerard Lledo Date: Wed, 17 Jun 2009 13:08:55 -0700 Subject: jffs2: move jffs2_gcd_mtd threads to the new kthread API Move the jffs2 garbage collecting thread to the new kthread API. Signed-off-by: Gerard Lledo Signed-off-by: Andrew Morton Signed-off-by: David Woodhouse diff --git a/fs/jffs2/background.c b/fs/jffs2/background.c index e958010..3ff50da 100644 --- a/fs/jffs2/background.c +++ b/fs/jffs2/background.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "nodelist.h" @@ -31,7 +32,7 @@ void jffs2_garbage_collect_trigger(struct jffs2_sb_info *c) /* This must only ever be called when no GC thread is currently running */ int jffs2_start_garbage_collect_thread(struct jffs2_sb_info *c) { - pid_t pid; + struct task_struct *tsk; int ret = 0; BUG_ON(c->gc_task); @@ -39,15 +40,16 @@ int jffs2_start_garbage_collect_thread(struct jffs2_sb_info *c) init_completion(&c->gc_thread_start); init_completion(&c->gc_thread_exit); - pid = kernel_thread(jffs2_garbage_collect_thread, c, CLONE_FS|CLONE_FILES); - if (pid < 0) { - printk(KERN_WARNING "fork failed for JFFS2 garbage collect thread: %d\n", -pid); + tsk = kthread_run(jffs2_garbage_collect_thread, c, "jffs2_gcd_mtd%d", c->mtd->index); + if (IS_ERR(tsk)) { + printk(KERN_WARNING "fork failed for JFFS2 garbage collect thread: %ld\n", -PTR_ERR(tsk)); complete(&c->gc_thread_exit); - ret = pid; + ret = PTR_ERR(tsk); } else { /* Wait for it... */ - D1(printk(KERN_DEBUG "JFFS2: Garbage collect thread is pid %d\n", pid)); + D1(printk(KERN_DEBUG "JFFS2: Garbage collect thread is pid %d\n", tsk->pid)); wait_for_completion(&c->gc_thread_start); + ret = tsk->pid; } return ret; @@ -71,7 +73,6 @@ static int jffs2_garbage_collect_thread(void *_c) { struct jffs2_sb_info *c = _c; - daemonize("jffs2_gcd_mtd%d", c->mtd->index); allow_signal(SIGKILL); allow_signal(SIGSTOP); allow_signal(SIGCONT); @@ -107,6 +108,11 @@ static int jffs2_garbage_collect_thread(void *_c) * the GC thread get there first. */ schedule_timeout_interruptible(msecs_to_jiffies(50)); + if (kthread_should_stop()) { + D1(printk(KERN_DEBUG "jffs2_garbage_collect_thread(): kthread_stop() called.\n")); + goto die; + } + /* Put_super will send a SIGKILL and then wait on the sem. */ while (signal_pending(current) || freezing(current)) { -- cgit v0.10.2 From 1be10a88cac5e589cdd2bcb0cf6a13ed30bcc233 Mon Sep 17 00:00:00 2001 From: "J. Bruce Fields" Date: Fri, 4 Sep 2009 11:59:32 -0400 Subject: nfsd4: filehandle leak or error exit from fh_compose() A number of callers (nfsd4_encode_fattr(), at least) don't bother to release the filehandle returned to fh_compose() if fh_compose() returns an error. So, modify fh_compose() to release the filehandle before returning an error. Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfsfh.c b/fs/nfsd/nfsfh.c index bce0b2b..01965b2 100644 --- a/fs/nfsd/nfsfh.c +++ b/fs/nfsd/nfsfh.c @@ -557,8 +557,10 @@ fh_compose(struct svc_fh *fhp, struct svc_export *exp, struct dentry *dentry, if (inode) _fh_update(fhp, exp, dentry); - if (fhp->fh_handle.fh_fileid_type == 255) + if (fhp->fh_handle.fh_fileid_type == 255) { + fh_put(fhp); return nfserr_opnotsupp; + } } return 0; -- cgit v0.10.2 From 32bb0e0c778a4a6cd4534a5b98f08cd45e9ab5b9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 Jul 2009 15:50:43 +0200 Subject: wm97xx-core: Pass platform_data to battery Signed-off-by: Marek Vasut Acked-by: Dmitry Torokhov Signed-off-by: Anton Vorontsov diff --git a/drivers/input/touchscreen/wm97xx-core.c b/drivers/input/touchscreen/wm97xx-core.c index 2957d48..cf8cbc6 100644 --- a/drivers/input/touchscreen/wm97xx-core.c +++ b/drivers/input/touchscreen/wm97xx-core.c @@ -561,6 +561,7 @@ static void wm97xx_ts_input_close(struct input_dev *idev) static int wm97xx_probe(struct device *dev) { struct wm97xx *wm; + struct wm97xx_pdata *pdata = dev->platform_data; int ret = 0, id = 0; wm = kzalloc(sizeof(struct wm97xx), GFP_KERNEL); @@ -656,6 +657,7 @@ static int wm97xx_probe(struct device *dev) } platform_set_drvdata(wm->battery_dev, wm); wm->battery_dev->dev.parent = dev; + wm->battery_dev->dev.platform_data = pdata; ret = platform_device_add(wm->battery_dev); if (ret < 0) goto batt_reg_err; @@ -669,6 +671,7 @@ static int wm97xx_probe(struct device *dev) } platform_set_drvdata(wm->touch_dev, wm); wm->touch_dev->dev.parent = dev; + wm->touch_dev->dev.platform_data = pdata; ret = platform_device_add(wm->touch_dev); if (ret < 0) goto touch_reg_err; -- cgit v0.10.2 From b8bdc1d0cfc488ac0d94724639f9a61b0a5a1d40 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 31 Aug 2009 06:20:12 +0200 Subject: wm97xx_battery: Use platform_data This patch converts the wm97xx-battery driver to use platform_data supplied by ac97 bus. Signed-off-by: Marek Vasut Signed-off-by: Anton Vorontsov diff --git a/drivers/power/wm97xx_battery.c b/drivers/power/wm97xx_battery.c index 8bde921..14ebd96 100644 --- a/drivers/power/wm97xx_battery.c +++ b/drivers/power/wm97xx_battery.c @@ -22,17 +22,19 @@ #include #include #include -#include static DEFINE_MUTEX(bat_lock); static struct work_struct bat_work; struct mutex work_lock; static int bat_status = POWER_SUPPLY_STATUS_UNKNOWN; -static struct wm97xx_batt_info *pdata; +static struct wm97xx_batt_info *gpdata; static enum power_supply_property *prop; static unsigned long wm97xx_read_bat(struct power_supply *bat_ps) { + struct wm97xx_pdata *wmdata = bat_ps->dev->parent->platform_data; + struct wm97xx_batt_pdata *pdata = wmdata->batt_pdata; + return wm97xx_read_aux_adc(bat_ps->dev->parent->driver_data, pdata->batt_aux) * pdata->batt_mult / pdata->batt_div; @@ -40,6 +42,9 @@ static unsigned long wm97xx_read_bat(struct power_supply *bat_ps) static unsigned long wm97xx_read_temp(struct power_supply *bat_ps) { + struct wm97xx_pdata *wmdata = bat_ps->dev->parent->platform_data; + struct wm97xx_batt_pdata *pdata = wmdata->batt_pdata; + return wm97xx_read_aux_adc(bat_ps->dev->parent->driver_data, pdata->temp_aux) * pdata->temp_mult / pdata->temp_div; @@ -49,6 +54,9 @@ static int wm97xx_bat_get_property(struct power_supply *bat_ps, enum power_supply_property psp, union power_supply_propval *val) { + struct wm97xx_pdata *wmdata = bat_ps->dev->parent->platform_data; + struct wm97xx_batt_pdata *pdata = wmdata->batt_pdata; + switch (psp) { case POWER_SUPPLY_PROP_STATUS: val->intval = bat_status; @@ -97,6 +105,8 @@ static void wm97xx_bat_external_power_changed(struct power_supply *bat_ps) static void wm97xx_bat_update(struct power_supply *bat_ps) { int old_status = bat_status; + struct wm97xx_pdata *wmdata = bat_ps->dev->parent->platform_data; + struct wm97xx_batt_pdata *pdata = wmdata->batt_pdata; mutex_lock(&work_lock); @@ -149,6 +159,15 @@ static int __devinit wm97xx_bat_probe(struct platform_device *dev) int ret = 0; int props = 1; /* POWER_SUPPLY_PROP_PRESENT */ int i = 0; + struct wm97xx_pdata *wmdata = dev->dev.platform_data; + struct wm97xx_batt_pdata *pdata; + + if (gpdata) { + dev_err(&dev->dev, "Do not pass platform_data through " + "wm97xx_bat_set_pdata!\n"); + return -EINVAL; + } else + pdata = wmdata->batt_pdata; if (dev->id != -1) return -EINVAL; @@ -156,7 +175,7 @@ static int __devinit wm97xx_bat_probe(struct platform_device *dev) mutex_init(&work_lock); if (!pdata) { - dev_err(&dev->dev, "Please use wm97xx_bat_set_pdata\n"); + dev_err(&dev->dev, "No platform_data supplied\n"); return -EINVAL; } @@ -229,6 +248,9 @@ err: static int __devexit wm97xx_bat_remove(struct platform_device *dev) { + struct wm97xx_pdata *wmdata = dev->dev.platform_data; + struct wm97xx_batt_pdata *pdata = wmdata->batt_pdata; + if (pdata && pdata->charge_gpio && pdata->charge_gpio >= 0) gpio_free(pdata->charge_gpio); flush_scheduled_work(); @@ -258,9 +280,9 @@ static void __exit wm97xx_bat_exit(void) platform_driver_unregister(&wm97xx_bat_driver); } -void __init wm97xx_bat_set_pdata(struct wm97xx_batt_info *data) +void wm97xx_bat_set_pdata(struct wm97xx_batt_info *data) { - pdata = data; + gpdata = data; } EXPORT_SYMBOL_GPL(wm97xx_bat_set_pdata); diff --git a/include/linux/wm97xx.h b/include/linux/wm97xx.h index 6f69968..b2c2297 100644 --- a/include/linux/wm97xx.h +++ b/include/linux/wm97xx.h @@ -286,6 +286,24 @@ struct wm97xx { u16 suspend_mode; /* PRP in suspend mode */ }; +struct wm97xx_batt_pdata { + int batt_aux; + int temp_aux; + int charge_gpio; + int min_voltage; + int max_voltage; + int batt_div; + int batt_mult; + int temp_div; + int temp_mult; + int batt_tech; + char *batt_name; +}; + +struct wm97xx_pdata { + struct wm97xx_batt_pdata *batt_pdata; /* battery data */ +}; + /* * Codec GPIO access (not supported on WM9705) * This can be used to set/get codec GPIO and Virtual GPIO status. diff --git a/include/linux/wm97xx_batt.h b/include/linux/wm97xx_batt.h index 9681d1a..a1d6419 100644 --- a/include/linux/wm97xx_batt.h +++ b/include/linux/wm97xx_batt.h @@ -3,22 +3,12 @@ #include -struct wm97xx_batt_info { - int batt_aux; - int temp_aux; - int charge_gpio; - int min_voltage; - int max_voltage; - int batt_div; - int batt_mult; - int temp_div; - int temp_mult; - int batt_tech; - char *batt_name; -}; +#warning This file will be removed soon, use wm97xx.h instead! + +#define wm97xx_batt_info wm97xx_batt_pdata #ifdef CONFIG_BATTERY_WM97XX -void __init wm97xx_bat_set_pdata(struct wm97xx_batt_info *data); +void wm97xx_bat_set_pdata(struct wm97xx_batt_info *data); #else static inline void wm97xx_bat_set_pdata(struct wm97xx_batt_info *data) {} #endif -- cgit v0.10.2 From 7c87942aef52d2120e95ff1dec739998b9f95a78 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 Jul 2009 16:02:08 +0200 Subject: wm97xx_battery: Use irq to detect charger state Signed-off-by: Marek Vasut Signed-off-by: Anton Vorontsov diff --git a/drivers/power/wm97xx_battery.c b/drivers/power/wm97xx_battery.c index 14ebd96..cad1ba2 100644 --- a/drivers/power/wm97xx_battery.c +++ b/drivers/power/wm97xx_battery.c @@ -22,6 +22,7 @@ #include #include #include +#include static DEFINE_MUTEX(bat_lock); static struct work_struct bat_work; @@ -137,6 +138,12 @@ static void wm97xx_bat_work(struct work_struct *work) wm97xx_bat_update(&bat_ps); } +static irqreturn_t wm97xx_chrg_irq(int irq, void *data) +{ + schedule_work(&bat_work); + return IRQ_HANDLED; +} + #ifdef CONFIG_PM static int wm97xx_bat_suspend(struct platform_device *dev, pm_message_t state) { @@ -179,13 +186,18 @@ static int __devinit wm97xx_bat_probe(struct platform_device *dev) return -EINVAL; } - if (pdata->charge_gpio >= 0 && gpio_is_valid(pdata->charge_gpio)) { + if (gpio_is_valid(pdata->charge_gpio)) { ret = gpio_request(pdata->charge_gpio, "BATT CHRG"); if (ret) goto err; ret = gpio_direction_input(pdata->charge_gpio); if (ret) goto err2; + ret = request_irq(gpio_to_irq(pdata->charge_gpio), + wm97xx_chrg_irq, IRQF_DISABLED, + "AC Detect", 0); + if (ret) + goto err2; props++; /* POWER_SUPPLY_PROP_STATUS */ } @@ -202,7 +214,7 @@ static int __devinit wm97xx_bat_probe(struct platform_device *dev) prop = kzalloc(props * sizeof(*prop), GFP_KERNEL); if (!prop) - goto err2; + goto err3; prop[i++] = POWER_SUPPLY_PROP_PRESENT; if (pdata->charge_gpio >= 0) @@ -235,13 +247,17 @@ static int __devinit wm97xx_bat_probe(struct platform_device *dev) if (!ret) schedule_work(&bat_work); else - goto err3; + goto err4; return 0; -err3: +err4: kfree(prop); +err3: + if (gpio_is_valid(pdata->charge_gpio)) + free_irq(gpio_to_irq(pdata->charge_gpio), dev); err2: - gpio_free(pdata->charge_gpio); + if (gpio_is_valid(pdata->charge_gpio)) + gpio_free(pdata->charge_gpio); err: return ret; } @@ -251,8 +267,10 @@ static int __devexit wm97xx_bat_remove(struct platform_device *dev) struct wm97xx_pdata *wmdata = dev->dev.platform_data; struct wm97xx_batt_pdata *pdata = wmdata->batt_pdata; - if (pdata && pdata->charge_gpio && pdata->charge_gpio >= 0) + if (pdata && gpio_is_valid(pdata->charge_gpio)) { + free_irq(gpio_to_irq(pdata->charge_gpio), dev); gpio_free(pdata->charge_gpio); + } flush_scheduled_work(); power_supply_unregister(&bat_ps); kfree(prop); -- cgit v0.10.2 From 83a8af0d31cfa6c728a68c00f6b1b518e2dcc03d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 22 Aug 2009 00:36:43 +0200 Subject: wm97xx_battery: Convert to dev_pm_ops Signed-off-by: Marek Vasut Signed-off-by: Anton Vorontsov diff --git a/drivers/power/wm97xx_battery.c b/drivers/power/wm97xx_battery.c index cad1ba2..c552082c 100644 --- a/drivers/power/wm97xx_battery.c +++ b/drivers/power/wm97xx_battery.c @@ -145,20 +145,22 @@ static irqreturn_t wm97xx_chrg_irq(int irq, void *data) } #ifdef CONFIG_PM -static int wm97xx_bat_suspend(struct platform_device *dev, pm_message_t state) +static int wm97xx_bat_suspend(struct device *dev) { flush_scheduled_work(); return 0; } -static int wm97xx_bat_resume(struct platform_device *dev) +static int wm97xx_bat_resume(struct device *dev) { schedule_work(&bat_work); return 0; } -#else -#define wm97xx_bat_suspend NULL -#define wm97xx_bat_resume NULL + +static struct dev_pm_ops wm97xx_bat_pm_ops = { + .suspend = wm97xx_bat_suspend, + .resume = wm97xx_bat_resume, +}; #endif static int __devinit wm97xx_bat_probe(struct platform_device *dev) @@ -281,11 +283,12 @@ static struct platform_driver wm97xx_bat_driver = { .driver = { .name = "wm97xx-battery", .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &wm97xx_bat_pm_ops, +#endif }, .probe = wm97xx_bat_probe, .remove = __devexit_p(wm97xx_bat_remove), - .suspend = wm97xx_bat_suspend, - .resume = wm97xx_bat_resume, }; static int __init wm97xx_bat_init(void) -- cgit v0.10.2 From b0525b48f06714e8d5cf6a3266261b71de8d6dd4 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 24 Jul 2009 15:08:11 +0200 Subject: ds2760_battery: Fix integer overflow for time_to_empty_now On the device we're currently developing, battery sizes of ~2.8Ah and current flow of ~600mA are typical. With that values, the life_sec computation overflows due to the multiplication by 3600. Signed-off-by: Daniel Mack Cc: Szabolcs Gyurko Cc: Matt Reimer Signed-off-by: Anton Vorontsov diff --git a/drivers/power/ds2760_battery.c b/drivers/power/ds2760_battery.c index 1bb8498..6f1dba5 100644 --- a/drivers/power/ds2760_battery.c +++ b/drivers/power/ds2760_battery.c @@ -211,9 +211,9 @@ static int ds2760_battery_read_status(struct ds2760_device_info *di) if (di->rem_capacity > 100) di->rem_capacity = 100; - if (di->current_uA) - di->life_sec = -((di->accum_current_uAh - di->empty_uAh) * - 3600L) / di->current_uA; + if (di->current_uA >= 100L) + di->life_sec = -((di->accum_current_uAh - di->empty_uAh) * 36L) + / (di->current_uA / 100L); else di->life_sec = 0; -- cgit v0.10.2 From 3961f7c3cf247eee5df7fabadc7a40f2deeb98f3 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 10 Aug 2009 17:43:53 +0100 Subject: power_supply: Add driver for the PMU on WM831x PMICs The WM831x PMICs provide power path management from three sources: a wall supply, USB and a battery with integrated charger. They also provide an additional backup supply with integrated for maintaining always on functionality such as the RTC and monitoring of power switches. After some initial configuration at startup the device operates autonomously, the driver simply provides reporting of the current state. Signed-off-by: Mark Brown Signed-off-by: Anton Vorontsov diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index bdbc4f7..cea6cef 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -29,6 +29,13 @@ config APM_POWER Say Y here to enable support APM status emulation using battery class devices. +config WM831X_POWER + tristate "WM831X PMU support" + depends on MFD_WM831X + help + Say Y here to enable support for the power management unit + provided by Wolfson Microelectronics WM831x PMICs. + config WM8350_POWER tristate "WM8350 PMU support" depends on MFD_WM8350 diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 380d17c..b96f29d 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_POWER_SUPPLY) += power_supply.o obj-$(CONFIG_PDA_POWER) += pda_power.o obj-$(CONFIG_APM_POWER) += apm_power.o +obj-$(CONFIG_WM831X_POWER) += wm831x_power.o obj-$(CONFIG_WM8350_POWER) += wm8350_power.o obj-$(CONFIG_BATTERY_DS2760) += ds2760_battery.o diff --git a/drivers/power/wm831x_power.c b/drivers/power/wm831x_power.c new file mode 100644 index 0000000..2a4c8b0 --- /dev/null +++ b/drivers/power/wm831x_power.c @@ -0,0 +1,779 @@ +/* + * PMU driver for Wolfson Microelectronics wm831x PMICs + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +struct wm831x_power { + struct wm831x *wm831x; + struct power_supply wall; + struct power_supply backup; + struct power_supply usb; + struct power_supply battery; +}; + +static int wm831x_power_check_online(struct wm831x *wm831x, int supply, + union power_supply_propval *val) +{ + int ret; + + ret = wm831x_reg_read(wm831x, WM831X_SYSTEM_STATUS); + if (ret < 0) + return ret; + + if (ret & supply) + val->intval = 1; + else + val->intval = 0; + + return 0; +} + +static int wm831x_power_read_voltage(struct wm831x *wm831x, + enum wm831x_auxadc src, + union power_supply_propval *val) +{ + int ret; + + ret = wm831x_auxadc_read_uv(wm831x, src); + if (ret >= 0) + val->intval = ret; + + return ret; +} + +/********************************************************************* + * WALL Power + *********************************************************************/ +static int wm831x_wall_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct wm831x_power *wm831x_power = dev_get_drvdata(psy->dev->parent); + struct wm831x *wm831x = wm831x_power->wm831x; + int ret = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + ret = wm831x_power_check_online(wm831x, WM831X_PWR_WALL, val); + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + ret = wm831x_power_read_voltage(wm831x, WM831X_AUX_WALL, val); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static enum power_supply_property wm831x_wall_props[] = { + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_VOLTAGE_NOW, +}; + +/********************************************************************* + * USB Power + *********************************************************************/ +static int wm831x_usb_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct wm831x_power *wm831x_power = dev_get_drvdata(psy->dev->parent); + struct wm831x *wm831x = wm831x_power->wm831x; + int ret = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + ret = wm831x_power_check_online(wm831x, WM831X_PWR_USB, val); + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + ret = wm831x_power_read_voltage(wm831x, WM831X_AUX_USB, val); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static enum power_supply_property wm831x_usb_props[] = { + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_VOLTAGE_NOW, +}; + +/********************************************************************* + * Battery properties + *********************************************************************/ + +struct chg_map { + int val; + int reg_val; +}; + +static struct chg_map trickle_ilims[] = { + { 50, 0 << WM831X_CHG_TRKL_ILIM_SHIFT }, + { 100, 1 << WM831X_CHG_TRKL_ILIM_SHIFT }, + { 150, 2 << WM831X_CHG_TRKL_ILIM_SHIFT }, + { 200, 3 << WM831X_CHG_TRKL_ILIM_SHIFT }, +}; + +static struct chg_map vsels[] = { + { 4050, 0 << WM831X_CHG_VSEL_SHIFT }, + { 4100, 1 << WM831X_CHG_VSEL_SHIFT }, + { 4150, 2 << WM831X_CHG_VSEL_SHIFT }, + { 4200, 3 << WM831X_CHG_VSEL_SHIFT }, +}; + +static struct chg_map fast_ilims[] = { + { 0, 0 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 50, 1 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 100, 2 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 150, 3 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 200, 4 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 250, 5 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 300, 6 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 350, 7 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 400, 8 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 450, 9 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 500, 10 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 600, 11 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 700, 12 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 800, 13 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 900, 14 << WM831X_CHG_FAST_ILIM_SHIFT }, + { 1000, 15 << WM831X_CHG_FAST_ILIM_SHIFT }, +}; + +static struct chg_map eoc_iterms[] = { + { 20, 0 << WM831X_CHG_ITERM_SHIFT }, + { 30, 1 << WM831X_CHG_ITERM_SHIFT }, + { 40, 2 << WM831X_CHG_ITERM_SHIFT }, + { 50, 3 << WM831X_CHG_ITERM_SHIFT }, + { 60, 4 << WM831X_CHG_ITERM_SHIFT }, + { 70, 5 << WM831X_CHG_ITERM_SHIFT }, + { 80, 6 << WM831X_CHG_ITERM_SHIFT }, + { 90, 7 << WM831X_CHG_ITERM_SHIFT }, +}; + +static struct chg_map chg_times[] = { + { 60, 0 << WM831X_CHG_TIME_SHIFT }, + { 90, 1 << WM831X_CHG_TIME_SHIFT }, + { 120, 2 << WM831X_CHG_TIME_SHIFT }, + { 150, 3 << WM831X_CHG_TIME_SHIFT }, + { 180, 4 << WM831X_CHG_TIME_SHIFT }, + { 210, 5 << WM831X_CHG_TIME_SHIFT }, + { 240, 6 << WM831X_CHG_TIME_SHIFT }, + { 270, 7 << WM831X_CHG_TIME_SHIFT }, + { 300, 8 << WM831X_CHG_TIME_SHIFT }, + { 330, 9 << WM831X_CHG_TIME_SHIFT }, + { 360, 10 << WM831X_CHG_TIME_SHIFT }, + { 390, 11 << WM831X_CHG_TIME_SHIFT }, + { 420, 12 << WM831X_CHG_TIME_SHIFT }, + { 450, 13 << WM831X_CHG_TIME_SHIFT }, + { 480, 14 << WM831X_CHG_TIME_SHIFT }, + { 510, 15 << WM831X_CHG_TIME_SHIFT }, +}; + +static void wm831x_battey_apply_config(struct wm831x *wm831x, + struct chg_map *map, int count, int val, + int *reg, const char *name, + const char *units) +{ + int i; + + for (i = 0; i < count; i++) + if (val == map[i].val) + break; + if (i == count) { + dev_err(wm831x->dev, "Invalid %s %d%s\n", + name, val, units); + } else { + *reg |= map[i].reg_val; + dev_dbg(wm831x->dev, "Set %s of %d%s\n", name, val, units); + } +} + +static void wm831x_config_battery(struct wm831x *wm831x) +{ + struct wm831x_pdata *wm831x_pdata = wm831x->dev->platform_data; + struct wm831x_battery_pdata *pdata; + int ret, reg1, reg2; + + if (!wm831x_pdata || !wm831x_pdata->battery) { + dev_warn(wm831x->dev, + "No battery charger configuration\n"); + return; + } + + pdata = wm831x_pdata->battery; + + reg1 = 0; + reg2 = 0; + + if (!pdata->enable) { + dev_info(wm831x->dev, "Battery charger disabled\n"); + return; + } + + reg1 |= WM831X_CHG_ENA; + if (pdata->off_mask) + reg2 |= WM831X_CHG_OFF_MSK; + if (pdata->fast_enable) + reg1 |= WM831X_CHG_FAST; + + wm831x_battey_apply_config(wm831x, trickle_ilims, + ARRAY_SIZE(trickle_ilims), + pdata->trickle_ilim, ®2, + "trickle charge current limit", "mA"); + + wm831x_battey_apply_config(wm831x, vsels, ARRAY_SIZE(vsels), + pdata->vsel, ®2, + "target voltage", "mV"); + + wm831x_battey_apply_config(wm831x, fast_ilims, ARRAY_SIZE(fast_ilims), + pdata->fast_ilim, ®2, + "fast charge current limit", "mA"); + + wm831x_battey_apply_config(wm831x, eoc_iterms, ARRAY_SIZE(eoc_iterms), + pdata->eoc_iterm, ®1, + "end of charge current threshold", "mA"); + + wm831x_battey_apply_config(wm831x, chg_times, ARRAY_SIZE(chg_times), + pdata->timeout, ®2, + "charger timeout", "min"); + + ret = wm831x_reg_unlock(wm831x); + if (ret != 0) { + dev_err(wm831x->dev, "Failed to unlock registers: %d\n", ret); + return; + } + + ret = wm831x_set_bits(wm831x, WM831X_CHARGER_CONTROL_1, + WM831X_CHG_ENA_MASK | + WM831X_CHG_FAST_MASK | + WM831X_CHG_ITERM_MASK | + WM831X_CHG_ITERM_MASK, + reg1); + if (ret != 0) + dev_err(wm831x->dev, "Failed to set charger control 1: %d\n", + ret); + + ret = wm831x_set_bits(wm831x, WM831X_CHARGER_CONTROL_2, + WM831X_CHG_OFF_MSK | + WM831X_CHG_TIME_MASK | + WM831X_CHG_FAST_ILIM_MASK | + WM831X_CHG_TRKL_ILIM_MASK | + WM831X_CHG_VSEL_MASK, + reg2); + if (ret != 0) + dev_err(wm831x->dev, "Failed to set charger control 2: %d\n", + ret); + + wm831x_reg_lock(wm831x); +} + +static int wm831x_bat_check_status(struct wm831x *wm831x, int *status) +{ + int ret; + + ret = wm831x_reg_read(wm831x, WM831X_SYSTEM_STATUS); + if (ret < 0) + return ret; + + if (ret & WM831X_PWR_SRC_BATT) { + *status = POWER_SUPPLY_STATUS_DISCHARGING; + return 0; + } + + ret = wm831x_reg_read(wm831x, WM831X_CHARGER_STATUS); + if (ret < 0) + return ret; + + switch (ret & WM831X_CHG_STATE_MASK) { + case WM831X_CHG_STATE_OFF: + *status = POWER_SUPPLY_STATUS_NOT_CHARGING; + break; + case WM831X_CHG_STATE_TRICKLE: + case WM831X_CHG_STATE_FAST: + *status = POWER_SUPPLY_STATUS_CHARGING; + break; + + default: + *status = POWER_SUPPLY_STATUS_UNKNOWN; + break; + } + + return 0; +} + +static int wm831x_bat_check_type(struct wm831x *wm831x, int *type) +{ + int ret; + + ret = wm831x_reg_read(wm831x, WM831X_CHARGER_STATUS); + if (ret < 0) + return ret; + + switch (ret & WM831X_CHG_STATE_MASK) { + case WM831X_CHG_STATE_TRICKLE: + case WM831X_CHG_STATE_TRICKLE_OT: + *type = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; + break; + case WM831X_CHG_STATE_FAST: + case WM831X_CHG_STATE_FAST_OT: + *type = POWER_SUPPLY_CHARGE_TYPE_FAST; + break; + default: + *type = POWER_SUPPLY_CHARGE_TYPE_NONE; + break; + } + + return 0; +} + +static int wm831x_bat_check_health(struct wm831x *wm831x, int *health) +{ + int ret; + + ret = wm831x_reg_read(wm831x, WM831X_CHARGER_STATUS); + if (ret < 0) + return ret; + + if (ret & WM831X_BATT_HOT_STS) { + *health = POWER_SUPPLY_HEALTH_OVERHEAT; + return 0; + } + + if (ret & WM831X_BATT_COLD_STS) { + *health = POWER_SUPPLY_HEALTH_COLD; + return 0; + } + + if (ret & WM831X_BATT_OV_STS) { + *health = POWER_SUPPLY_HEALTH_OVERVOLTAGE; + return 0; + } + + switch (ret & WM831X_CHG_STATE_MASK) { + case WM831X_CHG_STATE_TRICKLE_OT: + case WM831X_CHG_STATE_FAST_OT: + *health = POWER_SUPPLY_HEALTH_OVERHEAT; + break; + case WM831X_CHG_STATE_DEFECTIVE: + *health = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; + break; + default: + *health = POWER_SUPPLY_HEALTH_GOOD; + break; + } + + return 0; +} + +static int wm831x_bat_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct wm831x_power *wm831x_power = dev_get_drvdata(psy->dev->parent); + struct wm831x *wm831x = wm831x_power->wm831x; + int ret = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + ret = wm831x_bat_check_status(wm831x, &val->intval); + break; + case POWER_SUPPLY_PROP_ONLINE: + ret = wm831x_power_check_online(wm831x, WM831X_PWR_SRC_BATT, + val); + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + ret = wm831x_power_read_voltage(wm831x, WM831X_AUX_BATT, val); + break; + case POWER_SUPPLY_PROP_HEALTH: + ret = wm831x_bat_check_health(wm831x, &val->intval); + break; + case POWER_SUPPLY_PROP_CHARGE_TYPE: + ret = wm831x_bat_check_type(wm831x, &val->intval); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static enum power_supply_property wm831x_bat_props[] = { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_CHARGE_TYPE, +}; + +static const char *wm831x_bat_irqs[] = { + "BATT HOT", + "BATT COLD", + "BATT FAIL", + "OV", + "END", + "TO", + "MODE", + "START", +}; + +static irqreturn_t wm831x_bat_irq(int irq, void *data) +{ + struct wm831x_power *wm831x_power = data; + struct wm831x *wm831x = wm831x_power->wm831x; + + dev_dbg(wm831x->dev, "Battery status changed: %d\n", irq); + + /* The battery charger is autonomous so we don't need to do + * anything except kick user space */ + power_supply_changed(&wm831x_power->battery); + + return IRQ_HANDLED; +} + + +/********************************************************************* + * Backup supply properties + *********************************************************************/ + +static void wm831x_config_backup(struct wm831x *wm831x) +{ + struct wm831x_pdata *wm831x_pdata = wm831x->dev->platform_data; + struct wm831x_backup_pdata *pdata; + int ret, reg; + + if (!wm831x_pdata || !wm831x_pdata->backup) { + dev_warn(wm831x->dev, + "No backup battery charger configuration\n"); + return; + } + + pdata = wm831x_pdata->backup; + + reg = 0; + + if (pdata->charger_enable) + reg |= WM831X_BKUP_CHG_ENA | WM831X_BKUP_BATT_DET_ENA; + if (pdata->no_constant_voltage) + reg |= WM831X_BKUP_CHG_MODE; + + switch (pdata->vlim) { + case 2500: + break; + case 3100: + reg |= WM831X_BKUP_CHG_VLIM; + break; + default: + dev_err(wm831x->dev, "Invalid backup voltage limit %dmV\n", + pdata->vlim); + } + + switch (pdata->ilim) { + case 100: + break; + case 200: + reg |= 1; + break; + case 300: + reg |= 2; + break; + case 400: + reg |= 3; + break; + default: + dev_err(wm831x->dev, "Invalid backup current limit %duA\n", + pdata->ilim); + } + + ret = wm831x_reg_unlock(wm831x); + if (ret != 0) { + dev_err(wm831x->dev, "Failed to unlock registers: %d\n", ret); + return; + } + + ret = wm831x_set_bits(wm831x, WM831X_BACKUP_CHARGER_CONTROL, + WM831X_BKUP_CHG_ENA_MASK | + WM831X_BKUP_CHG_MODE_MASK | + WM831X_BKUP_BATT_DET_ENA_MASK | + WM831X_BKUP_CHG_VLIM_MASK | + WM831X_BKUP_CHG_ILIM_MASK, + reg); + if (ret != 0) + dev_err(wm831x->dev, + "Failed to set backup charger config: %d\n", ret); + + wm831x_reg_lock(wm831x); +} + +static int wm831x_backup_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct wm831x_power *wm831x_power = dev_get_drvdata(psy->dev->parent); + struct wm831x *wm831x = wm831x_power->wm831x; + int ret = 0; + + ret = wm831x_reg_read(wm831x, WM831X_BACKUP_CHARGER_CONTROL); + if (ret < 0) + return ret; + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + if (ret & WM831X_BKUP_CHG_STS) + val->intval = POWER_SUPPLY_STATUS_CHARGING; + else + val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; + break; + + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + ret = wm831x_power_read_voltage(wm831x, WM831X_AUX_BKUP_BATT, + val); + break; + + case POWER_SUPPLY_PROP_PRESENT: + if (ret & WM831X_BKUP_CHG_STS) + val->intval = 1; + else + val->intval = 0; + break; + + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static enum power_supply_property wm831x_backup_props[] = { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_PRESENT, +}; + +/********************************************************************* + * Initialisation + *********************************************************************/ + +static irqreturn_t wm831x_syslo_irq(int irq, void *data) +{ + struct wm831x_power *wm831x_power = data; + struct wm831x *wm831x = wm831x_power->wm831x; + + /* Not much we can actually *do* but tell people for + * posterity, we're probably about to run out of power. */ + dev_crit(wm831x->dev, "SYSVDD under voltage\n"); + + return IRQ_HANDLED; +} + +static irqreturn_t wm831x_pwr_src_irq(int irq, void *data) +{ + struct wm831x_power *wm831x_power = data; + struct wm831x *wm831x = wm831x_power->wm831x; + + dev_dbg(wm831x->dev, "Power source changed\n"); + + /* Just notify for everything - little harm in overnotifying. + * The backup battery is not a power source while the system + * is running so skip that. + */ + power_supply_changed(&wm831x_power->battery); + power_supply_changed(&wm831x_power->usb); + power_supply_changed(&wm831x_power->wall); + + return IRQ_HANDLED; +} + +static __devinit int wm831x_power_probe(struct platform_device *pdev) +{ + struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); + struct wm831x_power *power; + struct power_supply *usb; + struct power_supply *battery; + struct power_supply *wall; + struct power_supply *backup; + int ret, irq, i; + + power = kzalloc(sizeof(struct wm831x_power), GFP_KERNEL); + if (power == NULL) + return -ENOMEM; + + power->wm831x = wm831x; + platform_set_drvdata(pdev, power); + + usb = &power->usb; + battery = &power->battery; + wall = &power->wall; + backup = &power->backup; + + /* We ignore configuration failures since we can still read back + * the status without enabling either of the chargers. + */ + wm831x_config_battery(wm831x); + wm831x_config_backup(wm831x); + + wall->name = "wm831x-wall"; + wall->type = POWER_SUPPLY_TYPE_MAINS; + wall->properties = wm831x_wall_props; + wall->num_properties = ARRAY_SIZE(wm831x_wall_props); + wall->get_property = wm831x_wall_get_prop; + ret = power_supply_register(&pdev->dev, wall); + if (ret) + goto err_kmalloc; + + battery->name = "wm831x-battery"; + battery->properties = wm831x_bat_props; + battery->num_properties = ARRAY_SIZE(wm831x_bat_props); + battery->get_property = wm831x_bat_get_prop; + battery->use_for_apm = 1; + ret = power_supply_register(&pdev->dev, battery); + if (ret) + goto err_wall; + + usb->name = "wm831x-usb", + usb->type = POWER_SUPPLY_TYPE_USB; + usb->properties = wm831x_usb_props; + usb->num_properties = ARRAY_SIZE(wm831x_usb_props); + usb->get_property = wm831x_usb_get_prop; + ret = power_supply_register(&pdev->dev, usb); + if (ret) + goto err_battery; + + backup->name = "wm831x-backup"; + backup->type = POWER_SUPPLY_TYPE_BATTERY; + backup->properties = wm831x_backup_props; + backup->num_properties = ARRAY_SIZE(wm831x_backup_props); + backup->get_property = wm831x_backup_get_prop; + ret = power_supply_register(&pdev->dev, backup); + if (ret) + goto err_usb; + + irq = platform_get_irq_byname(pdev, "SYSLO"); + ret = wm831x_request_irq(wm831x, irq, wm831x_syslo_irq, + IRQF_TRIGGER_RISING, "SYSLO", + power); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to request SYSLO IRQ %d: %d\n", + irq, ret); + goto err_backup; + } + + irq = platform_get_irq_byname(pdev, "PWR SRC"); + ret = wm831x_request_irq(wm831x, irq, wm831x_pwr_src_irq, + IRQF_TRIGGER_RISING, "Power source", + power); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to request PWR SRC IRQ %d: %d\n", + irq, ret); + goto err_syslo; + } + + for (i = 0; i < ARRAY_SIZE(wm831x_bat_irqs); i++) { + irq = platform_get_irq_byname(pdev, wm831x_bat_irqs[i]); + ret = wm831x_request_irq(wm831x, irq, wm831x_bat_irq, + IRQF_TRIGGER_RISING, + wm831x_bat_irqs[i], + power); + if (ret != 0) { + dev_err(&pdev->dev, + "Failed to request %s IRQ %d: %d\n", + wm831x_bat_irqs[i], irq, ret); + goto err_bat_irq; + } + } + + return ret; + +err_bat_irq: + for (; i >= 0; i--) { + irq = platform_get_irq_byname(pdev, wm831x_bat_irqs[i]); + wm831x_free_irq(wm831x, irq, power); + } + irq = platform_get_irq_byname(pdev, "PWR SRC"); + wm831x_free_irq(wm831x, irq, power); +err_syslo: + irq = platform_get_irq_byname(pdev, "SYSLO"); + wm831x_free_irq(wm831x, irq, power); +err_backup: + power_supply_unregister(backup); +err_usb: + power_supply_unregister(usb); +err_battery: + power_supply_unregister(battery); +err_wall: + power_supply_unregister(wall); +err_kmalloc: + kfree(power); + return ret; +} + +static __devexit int wm831x_power_remove(struct platform_device *pdev) +{ + struct wm831x_power *wm831x_power = platform_get_drvdata(pdev); + struct wm831x *wm831x = wm831x_power->wm831x; + int irq, i; + + for (i = 0; i < ARRAY_SIZE(wm831x_bat_irqs); i++) { + irq = platform_get_irq_byname(pdev, wm831x_bat_irqs[i]); + wm831x_free_irq(wm831x, irq, wm831x_power); + } + + irq = platform_get_irq_byname(pdev, "PWR SRC"); + wm831x_free_irq(wm831x, irq, wm831x_power); + + irq = platform_get_irq_byname(pdev, "SYSLO"); + wm831x_free_irq(wm831x, irq, wm831x_power); + + power_supply_unregister(&wm831x_power->backup); + power_supply_unregister(&wm831x_power->battery); + power_supply_unregister(&wm831x_power->wall); + power_supply_unregister(&wm831x_power->usb); + return 0; +} + +static struct platform_driver wm831x_power_driver = { + .probe = wm831x_power_probe, + .remove = __devexit_p(wm831x_power_remove), + .driver = { + .name = "wm831x-power", + }, +}; + +static int __init wm831x_power_init(void) +{ + return platform_driver_register(&wm831x_power_driver); +} +module_init(wm831x_power_init); + +static void __exit wm831x_power_exit(void) +{ + platform_driver_unregister(&wm831x_power_driver); +} +module_exit(wm831x_power_exit); + +MODULE_DESCRIPTION("Power supply driver for WM831x PMICs"); +MODULE_AUTHOR("Mark Brown "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:wm831x-power"); diff --git a/include/linux/mfd/wm831x/pmu.h b/include/linux/mfd/wm831x/pmu.h new file mode 100644 index 0000000..b18cbb0 --- /dev/null +++ b/include/linux/mfd/wm831x/pmu.h @@ -0,0 +1,189 @@ +/* + * include/linux/mfd/wm831x/pmu.h -- PMU for WM831x + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __MFD_WM831X_PMU_H__ +#define __MFD_WM831X_PMU_H__ + +/* + * R16387 (0x4003) - Power State + */ +#define WM831X_CHIP_ON 0x8000 /* CHIP_ON */ +#define WM831X_CHIP_ON_MASK 0x8000 /* CHIP_ON */ +#define WM831X_CHIP_ON_SHIFT 15 /* CHIP_ON */ +#define WM831X_CHIP_ON_WIDTH 1 /* CHIP_ON */ +#define WM831X_CHIP_SLP 0x4000 /* CHIP_SLP */ +#define WM831X_CHIP_SLP_MASK 0x4000 /* CHIP_SLP */ +#define WM831X_CHIP_SLP_SHIFT 14 /* CHIP_SLP */ +#define WM831X_CHIP_SLP_WIDTH 1 /* CHIP_SLP */ +#define WM831X_REF_LP 0x1000 /* REF_LP */ +#define WM831X_REF_LP_MASK 0x1000 /* REF_LP */ +#define WM831X_REF_LP_SHIFT 12 /* REF_LP */ +#define WM831X_REF_LP_WIDTH 1 /* REF_LP */ +#define WM831X_PWRSTATE_DLY_MASK 0x0C00 /* PWRSTATE_DLY - [11:10] */ +#define WM831X_PWRSTATE_DLY_SHIFT 10 /* PWRSTATE_DLY - [11:10] */ +#define WM831X_PWRSTATE_DLY_WIDTH 2 /* PWRSTATE_DLY - [11:10] */ +#define WM831X_SWRST_DLY 0x0200 /* SWRST_DLY */ +#define WM831X_SWRST_DLY_MASK 0x0200 /* SWRST_DLY */ +#define WM831X_SWRST_DLY_SHIFT 9 /* SWRST_DLY */ +#define WM831X_SWRST_DLY_WIDTH 1 /* SWRST_DLY */ +#define WM831X_USB100MA_STARTUP_MASK 0x0030 /* USB100MA_STARTUP - [5:4] */ +#define WM831X_USB100MA_STARTUP_SHIFT 4 /* USB100MA_STARTUP - [5:4] */ +#define WM831X_USB100MA_STARTUP_WIDTH 2 /* USB100MA_STARTUP - [5:4] */ +#define WM831X_USB_CURR_STS 0x0008 /* USB_CURR_STS */ +#define WM831X_USB_CURR_STS_MASK 0x0008 /* USB_CURR_STS */ +#define WM831X_USB_CURR_STS_SHIFT 3 /* USB_CURR_STS */ +#define WM831X_USB_CURR_STS_WIDTH 1 /* USB_CURR_STS */ +#define WM831X_USB_ILIM_MASK 0x0007 /* USB_ILIM - [2:0] */ +#define WM831X_USB_ILIM_SHIFT 0 /* USB_ILIM - [2:0] */ +#define WM831X_USB_ILIM_WIDTH 3 /* USB_ILIM - [2:0] */ + +/* + * R16397 (0x400D) - System Status + */ +#define WM831X_THW_STS 0x8000 /* THW_STS */ +#define WM831X_THW_STS_MASK 0x8000 /* THW_STS */ +#define WM831X_THW_STS_SHIFT 15 /* THW_STS */ +#define WM831X_THW_STS_WIDTH 1 /* THW_STS */ +#define WM831X_PWR_SRC_BATT 0x0400 /* PWR_SRC_BATT */ +#define WM831X_PWR_SRC_BATT_MASK 0x0400 /* PWR_SRC_BATT */ +#define WM831X_PWR_SRC_BATT_SHIFT 10 /* PWR_SRC_BATT */ +#define WM831X_PWR_SRC_BATT_WIDTH 1 /* PWR_SRC_BATT */ +#define WM831X_PWR_WALL 0x0200 /* PWR_WALL */ +#define WM831X_PWR_WALL_MASK 0x0200 /* PWR_WALL */ +#define WM831X_PWR_WALL_SHIFT 9 /* PWR_WALL */ +#define WM831X_PWR_WALL_WIDTH 1 /* PWR_WALL */ +#define WM831X_PWR_USB 0x0100 /* PWR_USB */ +#define WM831X_PWR_USB_MASK 0x0100 /* PWR_USB */ +#define WM831X_PWR_USB_SHIFT 8 /* PWR_USB */ +#define WM831X_PWR_USB_WIDTH 1 /* PWR_USB */ +#define WM831X_MAIN_STATE_MASK 0x001F /* MAIN_STATE - [4:0] */ +#define WM831X_MAIN_STATE_SHIFT 0 /* MAIN_STATE - [4:0] */ +#define WM831X_MAIN_STATE_WIDTH 5 /* MAIN_STATE - [4:0] */ + +/* + * R16456 (0x4048) - Charger Control 1 + */ +#define WM831X_CHG_ENA 0x8000 /* CHG_ENA */ +#define WM831X_CHG_ENA_MASK 0x8000 /* CHG_ENA */ +#define WM831X_CHG_ENA_SHIFT 15 /* CHG_ENA */ +#define WM831X_CHG_ENA_WIDTH 1 /* CHG_ENA */ +#define WM831X_CHG_FRC 0x4000 /* CHG_FRC */ +#define WM831X_CHG_FRC_MASK 0x4000 /* CHG_FRC */ +#define WM831X_CHG_FRC_SHIFT 14 /* CHG_FRC */ +#define WM831X_CHG_FRC_WIDTH 1 /* CHG_FRC */ +#define WM831X_CHG_ITERM_MASK 0x1C00 /* CHG_ITERM - [12:10] */ +#define WM831X_CHG_ITERM_SHIFT 10 /* CHG_ITERM - [12:10] */ +#define WM831X_CHG_ITERM_WIDTH 3 /* CHG_ITERM - [12:10] */ +#define WM831X_CHG_FAST 0x0020 /* CHG_FAST */ +#define WM831X_CHG_FAST_MASK 0x0020 /* CHG_FAST */ +#define WM831X_CHG_FAST_SHIFT 5 /* CHG_FAST */ +#define WM831X_CHG_FAST_WIDTH 1 /* CHG_FAST */ +#define WM831X_CHG_IMON_ENA 0x0002 /* CHG_IMON_ENA */ +#define WM831X_CHG_IMON_ENA_MASK 0x0002 /* CHG_IMON_ENA */ +#define WM831X_CHG_IMON_ENA_SHIFT 1 /* CHG_IMON_ENA */ +#define WM831X_CHG_IMON_ENA_WIDTH 1 /* CHG_IMON_ENA */ +#define WM831X_CHG_CHIP_TEMP_MON 0x0001 /* CHG_CHIP_TEMP_MON */ +#define WM831X_CHG_CHIP_TEMP_MON_MASK 0x0001 /* CHG_CHIP_TEMP_MON */ +#define WM831X_CHG_CHIP_TEMP_MON_SHIFT 0 /* CHG_CHIP_TEMP_MON */ +#define WM831X_CHG_CHIP_TEMP_MON_WIDTH 1 /* CHG_CHIP_TEMP_MON */ + +/* + * R16457 (0x4049) - Charger Control 2 + */ +#define WM831X_CHG_OFF_MSK 0x4000 /* CHG_OFF_MSK */ +#define WM831X_CHG_OFF_MSK_MASK 0x4000 /* CHG_OFF_MSK */ +#define WM831X_CHG_OFF_MSK_SHIFT 14 /* CHG_OFF_MSK */ +#define WM831X_CHG_OFF_MSK_WIDTH 1 /* CHG_OFF_MSK */ +#define WM831X_CHG_TIME_MASK 0x0F00 /* CHG_TIME - [11:8] */ +#define WM831X_CHG_TIME_SHIFT 8 /* CHG_TIME - [11:8] */ +#define WM831X_CHG_TIME_WIDTH 4 /* CHG_TIME - [11:8] */ +#define WM831X_CHG_TRKL_ILIM_MASK 0x00C0 /* CHG_TRKL_ILIM - [7:6] */ +#define WM831X_CHG_TRKL_ILIM_SHIFT 6 /* CHG_TRKL_ILIM - [7:6] */ +#define WM831X_CHG_TRKL_ILIM_WIDTH 2 /* CHG_TRKL_ILIM - [7:6] */ +#define WM831X_CHG_VSEL_MASK 0x0030 /* CHG_VSEL - [5:4] */ +#define WM831X_CHG_VSEL_SHIFT 4 /* CHG_VSEL - [5:4] */ +#define WM831X_CHG_VSEL_WIDTH 2 /* CHG_VSEL - [5:4] */ +#define WM831X_CHG_FAST_ILIM_MASK 0x000F /* CHG_FAST_ILIM - [3:0] */ +#define WM831X_CHG_FAST_ILIM_SHIFT 0 /* CHG_FAST_ILIM - [3:0] */ +#define WM831X_CHG_FAST_ILIM_WIDTH 4 /* CHG_FAST_ILIM - [3:0] */ + +/* + * R16458 (0x404A) - Charger Status + */ +#define WM831X_BATT_OV_STS 0x8000 /* BATT_OV_STS */ +#define WM831X_BATT_OV_STS_MASK 0x8000 /* BATT_OV_STS */ +#define WM831X_BATT_OV_STS_SHIFT 15 /* BATT_OV_STS */ +#define WM831X_BATT_OV_STS_WIDTH 1 /* BATT_OV_STS */ +#define WM831X_CHG_STATE_MASK 0x7000 /* CHG_STATE - [14:12] */ +#define WM831X_CHG_STATE_SHIFT 12 /* CHG_STATE - [14:12] */ +#define WM831X_CHG_STATE_WIDTH 3 /* CHG_STATE - [14:12] */ +#define WM831X_BATT_HOT_STS 0x0800 /* BATT_HOT_STS */ +#define WM831X_BATT_HOT_STS_MASK 0x0800 /* BATT_HOT_STS */ +#define WM831X_BATT_HOT_STS_SHIFT 11 /* BATT_HOT_STS */ +#define WM831X_BATT_HOT_STS_WIDTH 1 /* BATT_HOT_STS */ +#define WM831X_BATT_COLD_STS 0x0400 /* BATT_COLD_STS */ +#define WM831X_BATT_COLD_STS_MASK 0x0400 /* BATT_COLD_STS */ +#define WM831X_BATT_COLD_STS_SHIFT 10 /* BATT_COLD_STS */ +#define WM831X_BATT_COLD_STS_WIDTH 1 /* BATT_COLD_STS */ +#define WM831X_CHG_TOPOFF 0x0200 /* CHG_TOPOFF */ +#define WM831X_CHG_TOPOFF_MASK 0x0200 /* CHG_TOPOFF */ +#define WM831X_CHG_TOPOFF_SHIFT 9 /* CHG_TOPOFF */ +#define WM831X_CHG_TOPOFF_WIDTH 1 /* CHG_TOPOFF */ +#define WM831X_CHG_ACTIVE 0x0100 /* CHG_ACTIVE */ +#define WM831X_CHG_ACTIVE_MASK 0x0100 /* CHG_ACTIVE */ +#define WM831X_CHG_ACTIVE_SHIFT 8 /* CHG_ACTIVE */ +#define WM831X_CHG_ACTIVE_WIDTH 1 /* CHG_ACTIVE */ +#define WM831X_CHG_TIME_ELAPSED_MASK 0x00FF /* CHG_TIME_ELAPSED - [7:0] */ +#define WM831X_CHG_TIME_ELAPSED_SHIFT 0 /* CHG_TIME_ELAPSED - [7:0] */ +#define WM831X_CHG_TIME_ELAPSED_WIDTH 8 /* CHG_TIME_ELAPSED - [7:0] */ + +#define WM831X_CHG_STATE_OFF (0 << WM831X_CHG_STATE_SHIFT) +#define WM831X_CHG_STATE_TRICKLE (1 << WM831X_CHG_STATE_SHIFT) +#define WM831X_CHG_STATE_FAST (2 << WM831X_CHG_STATE_SHIFT) +#define WM831X_CHG_STATE_TRICKLE_OT (3 << WM831X_CHG_STATE_SHIFT) +#define WM831X_CHG_STATE_FAST_OT (4 << WM831X_CHG_STATE_SHIFT) +#define WM831X_CHG_STATE_DEFECTIVE (5 << WM831X_CHG_STATE_SHIFT) + +/* + * R16459 (0x404B) - Backup Charger Control + */ +#define WM831X_BKUP_CHG_ENA 0x8000 /* BKUP_CHG_ENA */ +#define WM831X_BKUP_CHG_ENA_MASK 0x8000 /* BKUP_CHG_ENA */ +#define WM831X_BKUP_CHG_ENA_SHIFT 15 /* BKUP_CHG_ENA */ +#define WM831X_BKUP_CHG_ENA_WIDTH 1 /* BKUP_CHG_ENA */ +#define WM831X_BKUP_CHG_STS 0x4000 /* BKUP_CHG_STS */ +#define WM831X_BKUP_CHG_STS_MASK 0x4000 /* BKUP_CHG_STS */ +#define WM831X_BKUP_CHG_STS_SHIFT 14 /* BKUP_CHG_STS */ +#define WM831X_BKUP_CHG_STS_WIDTH 1 /* BKUP_CHG_STS */ +#define WM831X_BKUP_CHG_MODE 0x1000 /* BKUP_CHG_MODE */ +#define WM831X_BKUP_CHG_MODE_MASK 0x1000 /* BKUP_CHG_MODE */ +#define WM831X_BKUP_CHG_MODE_SHIFT 12 /* BKUP_CHG_MODE */ +#define WM831X_BKUP_CHG_MODE_WIDTH 1 /* BKUP_CHG_MODE */ +#define WM831X_BKUP_BATT_DET_ENA 0x0800 /* BKUP_BATT_DET_ENA */ +#define WM831X_BKUP_BATT_DET_ENA_MASK 0x0800 /* BKUP_BATT_DET_ENA */ +#define WM831X_BKUP_BATT_DET_ENA_SHIFT 11 /* BKUP_BATT_DET_ENA */ +#define WM831X_BKUP_BATT_DET_ENA_WIDTH 1 /* BKUP_BATT_DET_ENA */ +#define WM831X_BKUP_BATT_STS 0x0400 /* BKUP_BATT_STS */ +#define WM831X_BKUP_BATT_STS_MASK 0x0400 /* BKUP_BATT_STS */ +#define WM831X_BKUP_BATT_STS_SHIFT 10 /* BKUP_BATT_STS */ +#define WM831X_BKUP_BATT_STS_WIDTH 1 /* BKUP_BATT_STS */ +#define WM831X_BKUP_CHG_VLIM 0x0010 /* BKUP_CHG_VLIM */ +#define WM831X_BKUP_CHG_VLIM_MASK 0x0010 /* BKUP_CHG_VLIM */ +#define WM831X_BKUP_CHG_VLIM_SHIFT 4 /* BKUP_CHG_VLIM */ +#define WM831X_BKUP_CHG_VLIM_WIDTH 1 /* BKUP_CHG_VLIM */ +#define WM831X_BKUP_CHG_ILIM_MASK 0x0003 /* BKUP_CHG_ILIM - [1:0] */ +#define WM831X_BKUP_CHG_ILIM_SHIFT 0 /* BKUP_CHG_ILIM - [1:0] */ +#define WM831X_BKUP_CHG_ILIM_WIDTH 2 /* BKUP_CHG_ILIM - [1:0] */ + +#endif -- cgit v0.10.2 From 8177e6d6dfb9cd03d9bdeb647c32161f8f58f686 Mon Sep 17 00:00:00 2001 From: "J. Bruce Fields" Date: Fri, 4 Sep 2009 14:13:09 -0400 Subject: nfsd: clean up readdirplus encoding Make the return from compose_entry_fh() zero or an error, even though the returned error isn't used, just to make the meaning of the return immediately obvious. Move some repeated code out of main function into helper. Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs3xdr.c b/fs/nfsd/nfs3xdr.c index 01d4ec1..f16184a 100644 --- a/fs/nfsd/nfs3xdr.c +++ b/fs/nfsd/nfs3xdr.c @@ -814,17 +814,6 @@ encode_entry_baggage(struct nfsd3_readdirres *cd, __be32 *p, const char *name, return p; } -static __be32 * -encode_entryplus_baggage(struct nfsd3_readdirres *cd, __be32 *p, - struct svc_fh *fhp) -{ - p = encode_post_op_attr(cd->rqstp, p, fhp); - *p++ = xdr_one; /* yes, a file handle follows */ - p = encode_fh(p, fhp); - fh_put(fhp); - return p; -} - static int compose_entry_fh(struct nfsd3_readdirres *cd, struct svc_fh *fhp, const char *name, int namlen) @@ -843,22 +832,46 @@ compose_entry_fh(struct nfsd3_readdirres *cd, struct svc_fh *fhp, if (dchild == dparent) { /* filesystem root - cannot return filehandle for ".." */ dput(dchild); - return 1; + return -ENOENT; } } else dchild = dget(dparent); } else dchild = lookup_one_len(name, dparent, namlen); if (IS_ERR(dchild)) - return 1; - if (d_mountpoint(dchild) || - fh_compose(fhp, exp, dchild, &cd->fh) != 0 || - !dchild->d_inode) - rv = 1; + return -ENOENT; + rv = -ENOENT; + if (d_mountpoint(dchild)) + goto out; + rv = fh_compose(fhp, exp, dchild, &cd->fh); + if (rv) + goto out; + if (!dchild->d_inode) + goto out; + rv = 0; +out: dput(dchild); return rv; } +__be32 *encode_entryplus_baggage(struct nfsd3_readdirres *cd, __be32 *p, const char *name, int namlen) +{ + struct svc_fh fh; + int err; + + err = compose_entry_fh(cd, &fh, name, namlen); + if (err) { + *p++ = 0; + *p++ = 0; + return p; + } + p = encode_post_op_attr(cd->rqstp, p, &fh); + *p++ = xdr_one; /* yes, a file handle follows */ + p = encode_fh(p, &fh); + fh_put(&fh); + return p; +} + /* * Encode a directory entry. This one works for both normal readdir * and readdirplus. @@ -929,16 +942,8 @@ encode_entry(struct readdir_cd *ccd, const char *name, int namlen, p = encode_entry_baggage(cd, p, name, namlen, ino); - /* throw in readdirplus baggage */ - if (plus) { - struct svc_fh fh; - - if (compose_entry_fh(cd, &fh, name, namlen) > 0) { - *p++ = 0; - *p++ = 0; - } else - p = encode_entryplus_baggage(cd, p, &fh); - } + if (plus) + p = encode_entryplus_baggage(cd, p, name, namlen); num_entry_words = p - cd->buffer; } else if (cd->rqstp->rq_respages[pn+1] != NULL) { /* temporarily encode entry into next page, then move back to @@ -951,17 +956,8 @@ encode_entry(struct readdir_cd *ccd, const char *name, int namlen, p1 = encode_entry_baggage(cd, p1, name, namlen, ino); - /* throw in readdirplus baggage */ - if (plus) { - struct svc_fh fh; - - if (compose_entry_fh(cd, &fh, name, namlen) > 0) { - /* zero out the filehandle */ - *p1++ = 0; - *p1++ = 0; - } else - p1 = encode_entryplus_baggage(cd, p1, &fh); - } + if (plus) + p = encode_entryplus_baggage(cd, p1, name, namlen); /* determine entry word length and lengths to go in pages */ num_entry_words = p1 - tmp; -- cgit v0.10.2 From aed100fafb90aaabe8fb31e58af9dc7e68696507 Mon Sep 17 00:00:00 2001 From: "J. Bruce Fields" Date: Fri, 4 Sep 2009 14:40:36 -0400 Subject: nfsd: fix leak on error in nfsv3 readdir Note the !dchild->d_inode case can leak the filehandle. Signed-off-by: J. Bruce Fields diff --git a/fs/nfsd/nfs3xdr.c b/fs/nfsd/nfs3xdr.c index f16184a..edf926e 100644 --- a/fs/nfsd/nfs3xdr.c +++ b/fs/nfsd/nfs3xdr.c @@ -825,7 +825,6 @@ compose_entry_fh(struct nfsd3_readdirres *cd, struct svc_fh *fhp, dparent = cd->fh.fh_dentry; exp = cd->fh.fh_export; - fh_init(fhp, NFS3_FHSIZE); if (isdotent(name, namlen)) { if (namlen == 2) { dchild = dget_parent(dparent); @@ -859,15 +858,17 @@ __be32 *encode_entryplus_baggage(struct nfsd3_readdirres *cd, __be32 *p, const c struct svc_fh fh; int err; + fh_init(&fh, NFS3_FHSIZE); err = compose_entry_fh(cd, &fh, name, namlen); if (err) { *p++ = 0; *p++ = 0; - return p; + goto out; } p = encode_post_op_attr(cd->rqstp, p, &fh); *p++ = xdr_one; /* yes, a file handle follows */ p = encode_fh(p, &fh); +out: fh_put(&fh); return p; } -- cgit v0.10.2 From 27c202ad7f141d4efa9c64e30bf4a4d3bcd799ae Mon Sep 17 00:00:00 2001 From: Ben Gamari Date: Wed, 1 Jul 2009 22:26:52 -0400 Subject: drm/i915: Move i915_gem_debugfs.c to i915_debugfs.c Signed-off-by: Ben Gamari [anholt: hand-applied for conflicts] Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 30d6b99..5269dfa 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -4,10 +4,10 @@ ccflags-y := -Iinclude/drm i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ + i915_debugfs.o \ i915_suspend.o \ i915_gem.o \ i915_gem_debug.o \ - i915_gem_debugfs.o \ i915_gem_tiling.o \ intel_display.o \ intel_crt.o \ diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c new file mode 100644 index 0000000..b4f2d6b --- /dev/null +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -0,0 +1,396 @@ +/* + * Copyright © 2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * Keith Packard + * + */ + +#include +#include "drmP.h" +#include "drm.h" +#include "i915_drm.h" +#include "i915_drv.h" + +#define DRM_I915_RING_DEBUG 1 + + +#if defined(CONFIG_DEBUG_FS) + +#define ACTIVE_LIST 1 +#define FLUSHING_LIST 2 +#define INACTIVE_LIST 3 + +static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv) +{ + if (obj_priv->user_pin_count > 0) + return "P"; + else if (obj_priv->pin_count > 0) + return "p"; + else + return " "; +} + +static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv) +{ + switch (obj_priv->tiling_mode) { + default: + case I915_TILING_NONE: return " "; + case I915_TILING_X: return "X"; + case I915_TILING_Y: return "Y"; + } +} + +static int i915_gem_object_list_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + uintptr_t list = (uintptr_t) node->info_ent->data; + struct list_head *head; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + struct drm_i915_gem_object *obj_priv; + spinlock_t *lock = NULL; + + switch (list) { + case ACTIVE_LIST: + seq_printf(m, "Active:\n"); + lock = &dev_priv->mm.active_list_lock; + head = &dev_priv->mm.active_list; + break; + case INACTIVE_LIST: + seq_printf(m, "Inactive:\n"); + head = &dev_priv->mm.inactive_list; + break; + case FLUSHING_LIST: + seq_printf(m, "Flushing:\n"); + head = &dev_priv->mm.flushing_list; + break; + default: + DRM_INFO("Ooops, unexpected list\n"); + return 0; + } + + if (lock) + spin_lock(lock); + list_for_each_entry(obj_priv, head, list) + { + struct drm_gem_object *obj = obj_priv->obj; + + seq_printf(m, " %p: %s %08x %08x %d", + obj, + get_pin_flag(obj_priv), + obj->read_domains, obj->write_domain, + obj_priv->last_rendering_seqno); + + if (obj->name) + seq_printf(m, " (name: %d)", obj->name); + if (obj_priv->fence_reg != I915_FENCE_REG_NONE) + seq_printf(m, " (fence: %d)", obj_priv->fence_reg); + if (obj_priv->gtt_space != NULL) + seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset); + + seq_printf(m, "\n"); + } + + if (lock) + spin_unlock(lock); + return 0; +} + +static int i915_gem_request_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + struct drm_i915_gem_request *gem_request; + + seq_printf(m, "Request:\n"); + list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) { + seq_printf(m, " %d @ %d\n", + gem_request->seqno, + (int) (jiffies - gem_request->emitted_jiffies)); + } + return 0; +} + +static int i915_gem_seqno_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + + if (dev_priv->hw_status_page != NULL) { + seq_printf(m, "Current sequence: %d\n", + i915_get_gem_seqno(dev)); + } else { + seq_printf(m, "Current sequence: hws uninitialized\n"); + } + seq_printf(m, "Waiter sequence: %d\n", + dev_priv->mm.waiting_gem_seqno); + seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno); + return 0; +} + + +static int i915_interrupt_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + + seq_printf(m, "Interrupt enable: %08x\n", + I915_READ(IER)); + seq_printf(m, "Interrupt identity: %08x\n", + I915_READ(IIR)); + seq_printf(m, "Interrupt mask: %08x\n", + I915_READ(IMR)); + seq_printf(m, "Pipe A stat: %08x\n", + I915_READ(PIPEASTAT)); + seq_printf(m, "Pipe B stat: %08x\n", + I915_READ(PIPEBSTAT)); + seq_printf(m, "Interrupts received: %d\n", + atomic_read(&dev_priv->irq_received)); + if (dev_priv->hw_status_page != NULL) { + seq_printf(m, "Current sequence: %d\n", + i915_get_gem_seqno(dev)); + } else { + seq_printf(m, "Current sequence: hws uninitialized\n"); + } + seq_printf(m, "Waiter sequence: %d\n", + dev_priv->mm.waiting_gem_seqno); + seq_printf(m, "IRQ sequence: %d\n", + dev_priv->mm.irq_gem_seqno); + return 0; +} + +static int i915_gem_fence_regs_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + int i; + + seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); + seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); + for (i = 0; i < dev_priv->num_fence_regs; i++) { + struct drm_gem_object *obj = dev_priv->fence_regs[i].obj; + + if (obj == NULL) { + seq_printf(m, "Fenced object[%2d] = unused\n", i); + } else { + struct drm_i915_gem_object *obj_priv; + + obj_priv = obj->driver_private; + seq_printf(m, "Fenced object[%2d] = %p: %s " + "%08x %08zx %08x %s %08x %08x %d", + i, obj, get_pin_flag(obj_priv), + obj_priv->gtt_offset, + obj->size, obj_priv->stride, + get_tiling_flag(obj_priv), + obj->read_domains, obj->write_domain, + obj_priv->last_rendering_seqno); + if (obj->name) + seq_printf(m, " (name: %d)", obj->name); + seq_printf(m, "\n"); + } + } + + return 0; +} + +static int i915_hws_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + int i; + volatile u32 *hws; + + hws = (volatile u32 *)dev_priv->hw_status_page; + if (hws == NULL) + return 0; + + for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { + seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", + i * 4, + hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); + } + return 0; +} + +static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count) +{ + int page, i; + uint32_t *mem; + + for (page = 0; page < page_count; page++) { + mem = kmap(pages[page]); + for (i = 0; i < PAGE_SIZE; i += 4) + seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); + kunmap(pages[page]); + } +} + +static int i915_batchbuffer_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + struct drm_gem_object *obj; + struct drm_i915_gem_object *obj_priv; + int ret; + + spin_lock(&dev_priv->mm.active_list_lock); + + list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) { + obj = obj_priv->obj; + if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) { + ret = i915_gem_object_get_pages(obj); + if (ret) { + DRM_ERROR("Failed to get pages: %d\n", ret); + spin_unlock(&dev_priv->mm.active_list_lock); + return ret; + } + + seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset); + i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE); + + i915_gem_object_put_pages(obj); + } + } + + spin_unlock(&dev_priv->mm.active_list_lock); + + return 0; +} + +static int i915_ringbuffer_data(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + u8 *virt; + uint32_t *ptr, off; + + if (!dev_priv->ring.ring_obj) { + seq_printf(m, "No ringbuffer setup\n"); + return 0; + } + + virt = dev_priv->ring.virtual_start; + + for (off = 0; off < dev_priv->ring.Size; off += 4) { + ptr = (uint32_t *)(virt + off); + seq_printf(m, "%08x : %08x\n", off, *ptr); + } + + return 0; +} + +static int i915_ringbuffer_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + unsigned int head, tail, mask; + + head = I915_READ(PRB0_HEAD) & HEAD_ADDR; + tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; + mask = dev_priv->ring.tail_mask; + + seq_printf(m, "RingHead : %08x\n", head); + seq_printf(m, "RingTail : %08x\n", tail); + seq_printf(m, "RingMask : %08x\n", mask); + seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size); + seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD)); + + return 0; +} + +static int i915_error_state(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + struct drm_i915_error_state *error; + unsigned long flags; + + spin_lock_irqsave(&dev_priv->error_lock, flags); + if (!dev_priv->first_error) { + seq_printf(m, "no error state collected\n"); + goto out; + } + + error = dev_priv->first_error; + + seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, + error->time.tv_usec); + seq_printf(m, "EIR: 0x%08x\n", error->eir); + seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er); + seq_printf(m, " INSTPM: 0x%08x\n", error->instpm); + seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir); + seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr); + seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone); + seq_printf(m, " ACTHD: 0x%08x\n", error->acthd); + if (IS_I965G(dev)) { + seq_printf(m, " INSTPS: 0x%08x\n", error->instps); + seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); + } + +out: + spin_unlock_irqrestore(&dev_priv->error_lock, flags); + + return 0; +} + +static struct drm_info_list i915_debugfs_list[] = { + {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, + {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, + {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, + {"i915_gem_request", i915_gem_request_info, 0}, + {"i915_gem_seqno", i915_gem_seqno_info, 0}, + {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, + {"i915_gem_interrupt", i915_interrupt_info, 0}, + {"i915_gem_hws", i915_hws_info, 0}, + {"i915_ringbuffer_data", i915_ringbuffer_data, 0}, + {"i915_ringbuffer_info", i915_ringbuffer_info, 0}, + {"i915_batchbuffers", i915_batchbuffer_info, 0}, + {"i915_error_state", i915_error_state, 0}, +}; +#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) + +int i915_debugfs_init(struct drm_minor *minor) +{ + return drm_debugfs_create_files(i915_debugfs_list, + I915_DEBUGFS_ENTRIES, + minor->debugfs_root, minor); +} + +void i915_debugfs_cleanup(struct drm_minor *minor) +{ + drm_debugfs_remove_files(i915_debugfs_list, + I915_DEBUGFS_ENTRIES, minor); +} + +#endif /* CONFIG_DEBUG_FS */ + diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index fc4b68a..263636e 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -188,8 +188,8 @@ static struct drm_driver driver = { .master_create = i915_master_create, .master_destroy = i915_master_destroy, #if defined(CONFIG_DEBUG_FS) - .debugfs_init = i915_gem_debugfs_init, - .debugfs_cleanup = i915_gem_debugfs_cleanup, + .debugfs_init = i915_debugfs_init, + .debugfs_cleanup = i915_debugfs_cleanup, #endif .gem_init_object = i915_gem_init_object, .gem_free_object = i915_gem_free_object, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5b4f87e..e286f4e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -730,8 +730,8 @@ void i915_gem_dump_object(struct drm_gem_object *obj, int len, void i915_dump_lru(struct drm_device *dev, const char *where); /* i915_debugfs.c */ -int i915_gem_debugfs_init(struct drm_minor *minor); -void i915_gem_debugfs_cleanup(struct drm_minor *minor); +int i915_debugfs_init(struct drm_minor *minor); +void i915_debugfs_cleanup(struct drm_minor *minor); /* i915_suspend.c */ extern int i915_save_state(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/i915_gem_debugfs.c b/drivers/gpu/drm/i915/i915_gem_debugfs.c deleted file mode 100644 index cb3b974..0000000 --- a/drivers/gpu/drm/i915/i915_gem_debugfs.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - * Copyright © 2008 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * Authors: - * Eric Anholt - * Keith Packard - * - */ - -#include -#include "drmP.h" -#include "drm.h" -#include "i915_drm.h" -#include "i915_drv.h" - -#define DRM_I915_RING_DEBUG 1 - - -#if defined(CONFIG_DEBUG_FS) - -#define ACTIVE_LIST 1 -#define FLUSHING_LIST 2 -#define INACTIVE_LIST 3 - -static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv) -{ - if (obj_priv->user_pin_count > 0) - return "P"; - else if (obj_priv->pin_count > 0) - return "p"; - else - return " "; -} - -static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv) -{ - switch (obj_priv->tiling_mode) { - default: - case I915_TILING_NONE: return " "; - case I915_TILING_X: return "X"; - case I915_TILING_Y: return "Y"; - } -} - -static int i915_gem_object_list_info(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *) m->private; - uintptr_t list = (uintptr_t) node->info_ent->data; - struct list_head *head; - struct drm_device *dev = node->minor->dev; - drm_i915_private_t *dev_priv = dev->dev_private; - struct drm_i915_gem_object *obj_priv; - spinlock_t *lock = NULL; - - switch (list) { - case ACTIVE_LIST: - seq_printf(m, "Active:\n"); - lock = &dev_priv->mm.active_list_lock; - head = &dev_priv->mm.active_list; - break; - case INACTIVE_LIST: - seq_printf(m, "Inactive:\n"); - head = &dev_priv->mm.inactive_list; - break; - case FLUSHING_LIST: - seq_printf(m, "Flushing:\n"); - head = &dev_priv->mm.flushing_list; - break; - default: - DRM_INFO("Ooops, unexpected list\n"); - return 0; - } - - if (lock) - spin_lock(lock); - list_for_each_entry(obj_priv, head, list) - { - struct drm_gem_object *obj = obj_priv->obj; - - seq_printf(m, " %p: %s %08x %08x %d", - obj, - get_pin_flag(obj_priv), - obj->read_domains, obj->write_domain, - obj_priv->last_rendering_seqno); - - if (obj->name) - seq_printf(m, " (name: %d)", obj->name); - if (obj_priv->fence_reg != I915_FENCE_REG_NONE) - seq_printf(m, " (fence: %d)", obj_priv->fence_reg); - if (obj_priv->gtt_space != NULL) - seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset); - - seq_printf(m, "\n"); - } - - if (lock) - spin_unlock(lock); - return 0; -} - -static int i915_gem_request_info(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - drm_i915_private_t *dev_priv = dev->dev_private; - struct drm_i915_gem_request *gem_request; - - seq_printf(m, "Request:\n"); - list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) { - seq_printf(m, " %d @ %d\n", - gem_request->seqno, - (int) (jiffies - gem_request->emitted_jiffies)); - } - return 0; -} - -static int i915_gem_seqno_info(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - drm_i915_private_t *dev_priv = dev->dev_private; - - if (dev_priv->hw_status_page != NULL) { - seq_printf(m, "Current sequence: %d\n", - i915_get_gem_seqno(dev)); - } else { - seq_printf(m, "Current sequence: hws uninitialized\n"); - } - seq_printf(m, "Waiter sequence: %d\n", - dev_priv->mm.waiting_gem_seqno); - seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno); - return 0; -} - - -static int i915_interrupt_info(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - drm_i915_private_t *dev_priv = dev->dev_private; - - seq_printf(m, "Interrupt enable: %08x\n", - I915_READ(IER)); - seq_printf(m, "Interrupt identity: %08x\n", - I915_READ(IIR)); - seq_printf(m, "Interrupt mask: %08x\n", - I915_READ(IMR)); - seq_printf(m, "Pipe A stat: %08x\n", - I915_READ(PIPEASTAT)); - seq_printf(m, "Pipe B stat: %08x\n", - I915_READ(PIPEBSTAT)); - seq_printf(m, "Interrupts received: %d\n", - atomic_read(&dev_priv->irq_received)); - if (dev_priv->hw_status_page != NULL) { - seq_printf(m, "Current sequence: %d\n", - i915_get_gem_seqno(dev)); - } else { - seq_printf(m, "Current sequence: hws uninitialized\n"); - } - seq_printf(m, "Waiter sequence: %d\n", - dev_priv->mm.waiting_gem_seqno); - seq_printf(m, "IRQ sequence: %d\n", - dev_priv->mm.irq_gem_seqno); - return 0; -} - -static int i915_gem_fence_regs_info(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - drm_i915_private_t *dev_priv = dev->dev_private; - int i; - - seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); - seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); - for (i = 0; i < dev_priv->num_fence_regs; i++) { - struct drm_gem_object *obj = dev_priv->fence_regs[i].obj; - - if (obj == NULL) { - seq_printf(m, "Fenced object[%2d] = unused\n", i); - } else { - struct drm_i915_gem_object *obj_priv; - - obj_priv = obj->driver_private; - seq_printf(m, "Fenced object[%2d] = %p: %s " - "%08x %08zx %08x %s %08x %08x %d", - i, obj, get_pin_flag(obj_priv), - obj_priv->gtt_offset, - obj->size, obj_priv->stride, - get_tiling_flag(obj_priv), - obj->read_domains, obj->write_domain, - obj_priv->last_rendering_seqno); - if (obj->name) - seq_printf(m, " (name: %d)", obj->name); - seq_printf(m, "\n"); - } - } - - return 0; -} - -static int i915_hws_info(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - drm_i915_private_t *dev_priv = dev->dev_private; - int i; - volatile u32 *hws; - - hws = (volatile u32 *)dev_priv->hw_status_page; - if (hws == NULL) - return 0; - - for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { - seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", - i * 4, - hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); - } - return 0; -} - -static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count) -{ - int page, i; - uint32_t *mem; - - for (page = 0; page < page_count; page++) { - mem = kmap(pages[page]); - for (i = 0; i < PAGE_SIZE; i += 4) - seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); - kunmap(pages[page]); - } -} - -static int i915_batchbuffer_info(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - drm_i915_private_t *dev_priv = dev->dev_private; - struct drm_gem_object *obj; - struct drm_i915_gem_object *obj_priv; - int ret; - - spin_lock(&dev_priv->mm.active_list_lock); - - list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) { - obj = obj_priv->obj; - if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) { - ret = i915_gem_object_get_pages(obj); - if (ret) { - DRM_ERROR("Failed to get pages: %d\n", ret); - spin_unlock(&dev_priv->mm.active_list_lock); - return ret; - } - - seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset); - i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE); - - i915_gem_object_put_pages(obj); - } - } - - spin_unlock(&dev_priv->mm.active_list_lock); - - return 0; -} - -static int i915_ringbuffer_data(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - drm_i915_private_t *dev_priv = dev->dev_private; - u8 *virt; - uint32_t *ptr, off; - - if (!dev_priv->ring.ring_obj) { - seq_printf(m, "No ringbuffer setup\n"); - return 0; - } - - virt = dev_priv->ring.virtual_start; - - for (off = 0; off < dev_priv->ring.Size; off += 4) { - ptr = (uint32_t *)(virt + off); - seq_printf(m, "%08x : %08x\n", off, *ptr); - } - - return 0; -} - -static int i915_ringbuffer_info(struct seq_file *m, void *data) -{ - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - drm_i915_private_t *dev_priv = dev->dev_private; - unsigned int head, tail, mask; - - head = I915_READ(PRB0_HEAD) & HEAD_ADDR; - tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; - mask = dev_priv->ring.tail_mask; - - seq_printf(m, "RingHead : %08x\n", head); - seq_printf(m, "RingTail : %08x\n", tail); - seq_printf(m, "RingMask : %08x\n", mask); - seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size); - seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD)); - - return 0; -} - -static int i915_error_state(struct seq_file *m, void *unused) -{ - struct drm_info_node *node = (struct drm_info_node *) m->private; - struct drm_device *dev = node->minor->dev; - drm_i915_private_t *dev_priv = dev->dev_private; - struct drm_i915_error_state *error; - unsigned long flags; - - spin_lock_irqsave(&dev_priv->error_lock, flags); - if (!dev_priv->first_error) { - seq_printf(m, "no error state collected\n"); - goto out; - } - - error = dev_priv->first_error; - - seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, - error->time.tv_usec); - seq_printf(m, "EIR: 0x%08x\n", error->eir); - seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er); - seq_printf(m, " INSTPM: 0x%08x\n", error->instpm); - seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir); - seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr); - seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone); - seq_printf(m, " ACTHD: 0x%08x\n", error->acthd); - if (IS_I965G(dev)) { - seq_printf(m, " INSTPS: 0x%08x\n", error->instps); - seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); - } - -out: - spin_unlock_irqrestore(&dev_priv->error_lock, flags); - - return 0; -} - -static struct drm_info_list i915_gem_debugfs_list[] = { - {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, - {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, - {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, - {"i915_gem_request", i915_gem_request_info, 0}, - {"i915_gem_seqno", i915_gem_seqno_info, 0}, - {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, - {"i915_gem_interrupt", i915_interrupt_info, 0}, - {"i915_gem_hws", i915_hws_info, 0}, - {"i915_ringbuffer_data", i915_ringbuffer_data, 0}, - {"i915_ringbuffer_info", i915_ringbuffer_info, 0}, - {"i915_batchbuffers", i915_batchbuffer_info, 0}, - {"i915_error_state", i915_error_state, 0}, -}; -#define I915_GEM_DEBUGFS_ENTRIES ARRAY_SIZE(i915_gem_debugfs_list) - -int i915_gem_debugfs_init(struct drm_minor *minor) -{ - return drm_debugfs_create_files(i915_gem_debugfs_list, - I915_GEM_DEBUGFS_ENTRIES, - minor->debugfs_root, minor); -} - -void i915_gem_debugfs_cleanup(struct drm_minor *minor) -{ - drm_debugfs_remove_files(i915_gem_debugfs_list, - I915_GEM_DEBUGFS_ENTRIES, minor); -} - -#endif /* CONFIG_DEBUG_FS */ - -- cgit v0.10.2 From 9e3a6d155ed0a7636b926a798dd7221ea107b274 Mon Sep 17 00:00:00 2001 From: Ben Gamari Date: Wed, 1 Jul 2009 22:26:53 -0400 Subject: drm/i915: Add i915 register dumping debugfs file Add a debugfs file to dump the entire register range. Here we assume that reading write-only/reserved registers won't make the chip angry. Seems to hold true, thankfully. Signed-off-by: Ben Gamari Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index b4f2d6b..49e0d87 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -363,7 +363,37 @@ out: return 0; } +static int i915_registers_info(struct seq_file *m, void *data) { + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + uint32_t reg; + +#define DUMP_RANGE(start, end) \ + for (reg=start; reg < end; reg += 4) \ + seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg)); + + DUMP_RANGE(0x00000, 0x00fff); /* VGA registers */ + DUMP_RANGE(0x02000, 0x02fff); /* instruction, memory, interrupt control registers */ + DUMP_RANGE(0x03000, 0x031ff); /* FENCE and PPGTT control registers */ + DUMP_RANGE(0x03200, 0x03fff); /* frame buffer compression registers */ + DUMP_RANGE(0x05000, 0x05fff); /* I/O control registers */ + DUMP_RANGE(0x06000, 0x06fff); /* clock control registers */ + DUMP_RANGE(0x07000, 0x07fff); /* 3D internal debug registers */ + DUMP_RANGE(0x07400, 0x088ff); /* GPE debug registers */ + DUMP_RANGE(0x0a000, 0x0afff); /* display palette registers */ + DUMP_RANGE(0x10000, 0x13fff); /* MMIO MCHBAR */ + DUMP_RANGE(0x30000, 0x3ffff); /* overlay registers */ + DUMP_RANGE(0x60000, 0x6ffff); /* display engine pipeline registers */ + DUMP_RANGE(0x70000, 0x72fff); /* display and cursor registers */ + DUMP_RANGE(0x73000, 0x73fff); /* performance counters */ + + return 0; +} + + static struct drm_info_list i915_debugfs_list[] = { + {"i915_regs", i915_registers_info, 0}, {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, -- cgit v0.10.2 From 5f6a169598938d9e5703f06b64c4f4f972561ce5 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Mon, 10 Aug 2009 21:37:24 +0800 Subject: drm/i915: update debugfs interrupt info on IGDNG Signed-off-by: Zhenyu Wang Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 49e0d87..8f28325 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -158,16 +158,37 @@ static int i915_interrupt_info(struct seq_file *m, void *data) struct drm_device *dev = node->minor->dev; drm_i915_private_t *dev_priv = dev->dev_private; - seq_printf(m, "Interrupt enable: %08x\n", - I915_READ(IER)); - seq_printf(m, "Interrupt identity: %08x\n", - I915_READ(IIR)); - seq_printf(m, "Interrupt mask: %08x\n", - I915_READ(IMR)); - seq_printf(m, "Pipe A stat: %08x\n", - I915_READ(PIPEASTAT)); - seq_printf(m, "Pipe B stat: %08x\n", - I915_READ(PIPEBSTAT)); + if (!IS_IGDNG(dev)) { + seq_printf(m, "Interrupt enable: %08x\n", + I915_READ(IER)); + seq_printf(m, "Interrupt identity: %08x\n", + I915_READ(IIR)); + seq_printf(m, "Interrupt mask: %08x\n", + I915_READ(IMR)); + seq_printf(m, "Pipe A stat: %08x\n", + I915_READ(PIPEASTAT)); + seq_printf(m, "Pipe B stat: %08x\n", + I915_READ(PIPEBSTAT)); + } else { + seq_printf(m, "North Display Interrupt enable: %08x\n", + I915_READ(DEIER)); + seq_printf(m, "North Display Interrupt identity: %08x\n", + I915_READ(DEIIR)); + seq_printf(m, "North Display Interrupt mask: %08x\n", + I915_READ(DEIMR)); + seq_printf(m, "South Display Interrupt enable: %08x\n", + I915_READ(SDEIER)); + seq_printf(m, "South Display Interrupt identity: %08x\n", + I915_READ(SDEIIR)); + seq_printf(m, "South Display Interrupt mask: %08x\n", + I915_READ(SDEIMR)); + seq_printf(m, "Graphics Interrupt enable: %08x\n", + I915_READ(GTIER)); + seq_printf(m, "Graphics Interrupt identity: %08x\n", + I915_READ(GTIIR)); + seq_printf(m, "Graphics Interrupt mask: %08x\n", + I915_READ(GTIMR)); + } seq_printf(m, "Interrupts received: %d\n", atomic_read(&dev_priv->irq_received)); if (dev_priv->hw_status_page != NULL) { -- cgit v0.10.2 From 213c2e643145fc7d8a67f2d5d54ee0f6d7193e2e Mon Sep 17 00:00:00 2001 From: Ma Ling Date: Mon, 24 Aug 2009 13:50:25 +0800 Subject: drm/i915: select TV format according to connector type For integrated TV there are 3 connector types: S-VIDEO, Composite and Component(YprPb). Those tv formats whose component flag is true should be assigned to Component connector, others are for S-VIDEO and Composite. The patch intends to find appropriate tv format for each connector. In such case it will return the correct modeline to user space. Otherwise it will return the incorrect modeline when S-video/composite is connected. Signed-off-by: Ma Ling reviewed-by: Zhao Yakui Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 2fbe13a..a6c686c 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -1437,6 +1437,35 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output) return type; } +/* + * Here we set accurate tv format according to connector type + * i.e Component TV should not be assigned by NTSC or PAL + */ +static void intel_tv_find_better_format(struct drm_connector *connector) +{ + struct intel_output *intel_output = to_intel_output(connector); + struct intel_tv_priv *tv_priv = intel_output->dev_priv; + const struct tv_mode *tv_mode = intel_tv_mode_find(intel_output); + int i; + + if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) == + tv_mode->component_only) + return; + + + for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) { + tv_mode = tv_modes + i; + + if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) == + tv_mode->component_only) + break; + } + + tv_priv->tv_format = tv_mode->name; + drm_connector_property_set_value(connector, + connector->dev->mode_config.tv_mode_property, i); +} + /** * Detect the TV connection. * @@ -1473,6 +1502,7 @@ intel_tv_detect(struct drm_connector *connector) if (type < 0) return connector_status_disconnected; + intel_tv_find_better_format(connector); return connector_status_connected; } -- cgit v0.10.2 From ce6feabd1b38f9adf4a962d71bc4762047e8f889 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Mon, 24 Aug 2009 13:50:26 +0800 Subject: drm/i915: Enable PAL and SECAM format and add the propery for SDVO-TV Currently SDVO TV only support NTSC-M format. In this patch we introduce PAL and SECAM formats available and create seting-format property at init time. When user dynamically chose preferred format by xrandr command, it will refine all modelines provided by SDVO device, then instruct SDVO device to execute. At the same time the property is added for SDVO-TV so that the SDVO-TV mode can be changed by using xrandr. https://bugs.freedesktop.org/show_bug.cgi?id=22891 Signed-off-by: Ma Ling review-by: Zhao Yakui Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index d3b74ba..cabe32d 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -38,6 +38,18 @@ #undef SDVO_DEBUG #define I915_SDVO "i915_sdvo" +static char *tv_format_names[] = { + "NTSC_M" , "NTSC_J" , "NTSC_443", + "PAL_B" , "PAL_D" , "PAL_G" , + "PAL_H" , "PAL_I" , "PAL_M" , + "PAL_N" , "PAL_NC" , "PAL_60" , + "SECAM_B" , "SECAM_D" , "SECAM_G" , + "SECAM_K" , "SECAM_K1", "SECAM_L" , + "SECAM_60" +}; + +#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) + struct intel_sdvo_priv { u8 slave_addr; @@ -71,6 +83,15 @@ struct intel_sdvo_priv { */ bool is_tv; + /* This is for current tv format name */ + char *tv_format_name; + + /* This contains all current supported TV format */ + char *tv_format_supported[TV_FORMAT_NUM]; + int format_supported_num; + struct drm_property *tv_format_property; + struct drm_property *tv_format_name_property[TV_FORMAT_NUM]; + /** * This is set if we treat the device as HDMI, instead of DVI. */ @@ -97,14 +118,6 @@ struct intel_sdvo_priv { */ struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions; - /** - * Current selected TV format. - * - * This is stored in the same structure that's passed to the device, for - * convenience. - */ - struct intel_sdvo_tv_format tv_format; - /* * supported encoding mode, used to determine whether HDMI is * supported @@ -945,23 +958,28 @@ static void intel_sdvo_set_avi_infoframe(struct intel_output *output, static void intel_sdvo_set_tv_format(struct intel_output *output) { + + struct intel_sdvo_tv_format format; struct intel_sdvo_priv *sdvo_priv = output->dev_priv; - struct intel_sdvo_tv_format *format, unset; - u8 status; + uint32_t format_map, i; + uint8_t status; - format = &sdvo_priv->tv_format; - memset(&unset, 0, sizeof(unset)); - if (memcmp(format, &unset, sizeof(*format))) { - DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n", - SDVO_NAME(sdvo_priv)); - format->ntsc_m = 1; - intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format, - sizeof(*format)); - status = intel_sdvo_read_response(output, NULL, 0); - if (status != SDVO_CMD_STATUS_SUCCESS) - DRM_DEBUG("%s: Failed to set TV format\n", - SDVO_NAME(sdvo_priv)); - } + for (i = 0; i < TV_FORMAT_NUM; i++) + if (tv_format_names[i] == sdvo_priv->tv_format_name) + break; + + format_map = 1 << i; + memset(&format, 0, sizeof(format)); + memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ? + sizeof(format) : sizeof(format_map)); + + intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map, + sizeof(format)); + + status = intel_sdvo_read_response(output, NULL, 0); + if (status != SDVO_CMD_STATUS_SUCCESS) + DRM_DEBUG("%s: Failed to set TV format\n", + SDVO_NAME(sdvo_priv)); } static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, @@ -1516,7 +1534,8 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect struct intel_output *intel_output = to_intel_output(connector); struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; - intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); + intel_sdvo_write_cmd(intel_output, + SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); status = intel_sdvo_read_response(intel_output, &response, 2); DRM_DEBUG("SDVO response %d %d\n", response & 0xff, response >> 8); @@ -1567,25 +1586,6 @@ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) #endif } -/** - * This function checks the current TV format, and chooses a default if - * it hasn't been set. - */ -static void -intel_sdvo_check_tv_format(struct intel_output *output) -{ - struct intel_sdvo_priv *dev_priv = output->dev_priv; - struct intel_sdvo_tv_format format; - uint8_t status; - - intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0); - status = intel_sdvo_read_response(output, &format, sizeof(format)); - if (status != SDVO_CMD_STATUS_SUCCESS) - return; - - memcpy(&dev_priv->tv_format, &format, sizeof(format)); -} - /* * Set of SDVO TV modes. * Note! This is in reply order (see loop in get_tv_modes). @@ -1656,17 +1656,26 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector) struct intel_output *output = to_intel_output(connector); struct intel_sdvo_priv *sdvo_priv = output->dev_priv; struct intel_sdvo_sdtv_resolution_request tv_res; - uint32_t reply = 0; + uint32_t reply = 0, format_map = 0; + int i; uint8_t status; - int i = 0; - intel_sdvo_check_tv_format(output); /* Read the list of supported input resolutions for the selected TV * format. */ - memset(&tv_res, 0, sizeof(tv_res)); - memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res)); + for (i = 0; i < TV_FORMAT_NUM; i++) + if (tv_format_names[i] == sdvo_priv->tv_format_name) + break; + + format_map = (1 << i); + memcpy(&tv_res, &format_map, + sizeof(struct intel_sdvo_sdtv_resolution_request) > + sizeof(format_map) ? sizeof(format_map) : + sizeof(struct intel_sdvo_sdtv_resolution_request)); + + intel_sdvo_set_target_output(output, sdvo_priv->controlled_output); + intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, &tv_res, sizeof(tv_res)); status = intel_sdvo_read_response(output, &reply, 3); @@ -1681,6 +1690,7 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector) if (nmode) drm_mode_probed_add(connector, nmode); } + } static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) @@ -1753,12 +1763,55 @@ static void intel_sdvo_destroy(struct drm_connector *connector) drm_mode_destroy(connector->dev, sdvo_priv->sdvo_lvds_fixed_mode); + if (sdvo_priv->tv_format_property) + drm_property_destroy(connector->dev, + sdvo_priv->tv_format_property); + drm_sysfs_connector_remove(connector); drm_connector_cleanup(connector); kfree(intel_output); } +static int +intel_sdvo_set_property(struct drm_connector *connector, + struct drm_property *property, + uint64_t val) +{ + struct intel_output *intel_output = to_intel_output(connector); + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + struct drm_encoder *encoder = &intel_output->enc; + struct drm_crtc *crtc = encoder->crtc; + int ret = 0; + bool changed = false; + + ret = drm_connector_property_set_value(connector, property, val); + if (ret < 0) + goto out; + + if (property == sdvo_priv->tv_format_property) { + if (val >= TV_FORMAT_NUM) { + ret = -EINVAL; + goto out; + } + if (sdvo_priv->tv_format_name == + sdvo_priv->tv_format_supported[val]) + goto out; + + sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val]; + changed = true; + } else { + ret = -EINVAL; + goto out; + } + + if (changed && crtc) + drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, + crtc->y, crtc->fb); +out: + return ret; +} + static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { .dpms = intel_sdvo_dpms, .mode_fixup = intel_sdvo_mode_fixup, @@ -1773,6 +1826,7 @@ static const struct drm_connector_funcs intel_sdvo_connector_funcs = { .restore = intel_sdvo_restore, .detect = intel_sdvo_detect, .fill_modes = drm_helper_probe_single_connector_modes, + .set_property = intel_sdvo_set_property, .destroy = intel_sdvo_destroy, }; @@ -2029,6 +2083,55 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags) } +static void intel_sdvo_tv_create_property(struct drm_connector *connector) +{ + struct intel_output *intel_output = to_intel_output(connector); + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + struct intel_sdvo_tv_format format; + uint32_t format_map, i; + uint8_t status; + + intel_sdvo_set_target_output(intel_output, + sdvo_priv->controlled_output); + + intel_sdvo_write_cmd(intel_output, + SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0); + status = intel_sdvo_read_response(intel_output, + &format, sizeof(format)); + if (status != SDVO_CMD_STATUS_SUCCESS) + return; + + memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ? + sizeof(format_map) : sizeof(format)); + + if (format_map == 0) + return; + + sdvo_priv->format_supported_num = 0; + for (i = 0 ; i < TV_FORMAT_NUM; i++) + if (format_map & (1 << i)) { + sdvo_priv->tv_format_supported + [sdvo_priv->format_supported_num++] = + tv_format_names[i]; + } + + + sdvo_priv->tv_format_property = + drm_property_create( + connector->dev, DRM_MODE_PROP_ENUM, + "mode", sdvo_priv->format_supported_num); + + for (i = 0; i < sdvo_priv->format_supported_num; i++) + drm_property_add_enum( + sdvo_priv->tv_format_property, i, + i, sdvo_priv->tv_format_supported[i]); + + sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0]; + drm_connector_attach_property( + connector, sdvo_priv->tv_format_property, 0); + +} + bool intel_sdvo_init(struct drm_device *dev, int output_device) { struct drm_connector *connector; @@ -2111,6 +2214,8 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs); drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); + if (sdvo_priv->is_tv) + intel_sdvo_tv_create_property(connector); drm_sysfs_connector_add(connector); intel_sdvo_select_ddc_bus(sdvo_priv); -- cgit v0.10.2 From 043029655816ed4cfc2ed247020ef97e5d637392 Mon Sep 17 00:00:00 2001 From: Shaohua Li Date: Mon, 24 Aug 2009 10:25:23 +0800 Subject: drm/i915: Support IGD EOS In the event that any one of the DAC analog outputs (R,G,B) were driven at full-scale (white video) or some analog level close to full-scale voltage, and if the video cable were then disconnected, the analog video voltage level would exceed the maximum electrical overstress limit of the native (thin-oxide) transistors thus causing a long-term reliability concern. The electrical overstress condition occurs in this particular case. This patch address the IGD EOS (electrical overstress condition) issue. When the EOS interrupt occurs, OS should disable DAC and then disable EOS, then the normal hotplug operation follows. TODO: it appears the normal unplug interrupt is missed as reported by Li Peng, need more checks here. Signed-off-by: Shaohua Li Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 7ebc84c..6c89f2f 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -565,6 +565,27 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); I915_READ(PORT_HOTPLUG_STAT); + + /* EOS interrupts occurs */ + if (IS_IGD(dev) && + (hotplug_status & CRT_EOS_INT_STATUS)) { + u32 temp; + + DRM_DEBUG("EOS interrupt occurs\n"); + /* status is already cleared */ + temp = I915_READ(ADPA); + temp &= ~ADPA_DAC_ENABLE; + I915_WRITE(ADPA, temp); + + temp = I915_READ(PORT_HOTPLUG_EN); + temp &= ~CRT_EOS_INT_EN; + I915_WRITE(PORT_HOTPLUG_EN, temp); + + temp = I915_READ(PORT_HOTPLUG_STAT); + if (temp & CRT_EOS_INT_STATUS) + I915_WRITE(PORT_HOTPLUG_STAT, + CRT_EOS_INT_STATUS); + } } I915_WRITE(IIR, iir); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2955083..87a737f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -683,6 +683,7 @@ #define SDVOB_HOTPLUG_INT_EN (1 << 26) #define SDVOC_HOTPLUG_INT_EN (1 << 25) #define TV_HOTPLUG_INT_EN (1 << 18) +#define CRT_EOS_INT_EN (1 << 10) #define CRT_HOTPLUG_INT_EN (1 << 9) #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) @@ -717,6 +718,7 @@ #define DPC_HOTPLUG_INT_STATUS (1 << 28) #define HDMID_HOTPLUG_INT_STATUS (1 << 27) #define DPD_HOTPLUG_INT_STATUS (1 << 27) +#define CRT_EOS_INT_STATUS (1 << 12) #define CRT_HOTPLUG_INT_STATUS (1 << 11) #define TV_HOTPLUG_INT_STATUS (1 << 10) #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 590f81c..88814fa 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -64,6 +64,34 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode) } I915_WRITE(reg, temp); + + if (IS_IGD(dev)) { + if (mode == DRM_MODE_DPMS_OFF) { + /* turn off DAC */ + temp = I915_READ(PORT_HOTPLUG_EN); + temp &= ~CRT_EOS_INT_EN; + I915_WRITE(PORT_HOTPLUG_EN, temp); + + temp = I915_READ(PORT_HOTPLUG_STAT); + if (temp & CRT_EOS_INT_STATUS) + I915_WRITE(PORT_HOTPLUG_STAT, + CRT_EOS_INT_STATUS); + } else { + /* turn on DAC. EOS interrupt must be enabled after DAC + * is enabled, so it sounds not good to enable it in + * i915_driver_irq_postinstall() + * wait 12.5ms after DAC is enabled + */ + msleep(13); + temp = I915_READ(PORT_HOTPLUG_STAT); + if (temp & CRT_EOS_INT_STATUS) + I915_WRITE(PORT_HOTPLUG_STAT, + CRT_EOS_INT_STATUS); + temp = I915_READ(PORT_HOTPLUG_EN); + temp |= CRT_EOS_INT_EN; + I915_WRITE(PORT_HOTPLUG_EN, temp); + } + } } static int intel_crt_mode_valid(struct drm_connector *connector, -- cgit v0.10.2 From 652c393a3368af84359da37c45afc35a91144960 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Mon, 17 Aug 2009 13:31:43 -0700 Subject: drm/i915: add dynamic clock frequency control There are several sources of unnecessary power consumption on Intel graphics systems. The first is the LVDS clock. TFTs don't suffer from persistence issues like CRTs, and so we can reduce the LVDS refresh rate when the screen is idle. It will be automatically upclocked when userspace triggers graphical activity. Beyond that, we can enable memory self refresh. This allows the memory to go into a lower power state when the graphics are idle. Finally, we can drop some clocks on the gpu itself. All of these things can be reenabled between frames when GPU activity is triggered, and so there should be no user visible graphical changes. Signed-off-by: Jesse Barnes Signed-off-by: Matthew Garrett Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 263636e..81ab488 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -43,6 +43,9 @@ module_param_named(modeset, i915_modeset, int, 0400); unsigned int i915_fbpercrtc = 0; module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); +unsigned int i915_powersave = 1; +module_param_named(powersave, i915_powersave, int, 0400); + static struct drm_driver driver; static struct pci_device_id pciidlist[] = { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e286f4e..76914ae 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -311,7 +311,7 @@ typedef struct drm_i915_private { u32 saveIMR; u32 saveCACHE_MODE_0; u32 saveD_STATE; - u32 saveCG_2D_DIS; + u32 saveDSPCLK_GATE_D; u32 saveMI_ARB_STATE; u32 saveSWF0[16]; u32 saveSWF1[16]; @@ -443,6 +443,14 @@ typedef struct drm_i915_private { struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; } mm; struct sdvo_device_mapping sdvo_mappings[2]; + + /* Reclocking support */ + bool render_reclock_avail; + bool lvds_downclock_avail; + struct work_struct idle_work; + struct timer_list idle_timer; + bool busy; + u16 orig_clock; } drm_i915_private_t; /** driver private structure attached to each drm_gem_object */ @@ -575,6 +583,7 @@ enum intel_chip_family { extern struct drm_ioctl_desc i915_ioctls[]; extern int i915_max_ioctl; extern unsigned int i915_fbpercrtc; +extern unsigned int i915_powersave; extern int i915_master_create(struct drm_device *dev, struct drm_master *master); extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); @@ -903,6 +912,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); /* dsparb controlled by hw only */ #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev)) +#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) +#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) + #define PRIMARY_RINGBUFFER_SIZE (128*1024) #endif diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 7edb5b9..73b5819 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -29,6 +29,7 @@ #include "drm.h" #include "i915_drm.h" #include "i915_drv.h" +#include "intel_drv.h" #include #include @@ -981,6 +982,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_set_domain *args = data; struct drm_gem_object *obj; + struct drm_i915_gem_object *obj_priv; uint32_t read_domains = args->read_domains; uint32_t write_domain = args->write_domain; int ret; @@ -1004,15 +1006,17 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, obj = drm_gem_object_lookup(dev, file_priv, args->handle); if (obj == NULL) return -EBADF; + obj_priv = obj->driver_private; mutex_lock(&dev->struct_mutex); + + intel_mark_busy(dev, obj); + #if WATCH_BUF DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", obj, obj->size, read_domains, write_domain); #endif if (read_domains & I915_GEM_DOMAIN_GTT) { - struct drm_i915_gem_object *obj_priv = obj->driver_private; - ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); /* Update the LRU on the fence for the CPU access that's @@ -2776,6 +2780,8 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); + intel_mark_busy(dev, obj); + #if WATCH_BUF DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", __func__, obj, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 87a737f..884757c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -55,7 +55,7 @@ /* PCI config space */ #define HPLLCC 0xc0 /* 855 only */ -#define GC_CLOCK_CONTROL_MASK (3 << 0) +#define GC_CLOCK_CONTROL_MASK (0xf << 0) #define GC_CLOCK_133_200 (0 << 0) #define GC_CLOCK_100_200 (1 << 0) #define GC_CLOCK_100_133 (2 << 0) @@ -65,6 +65,25 @@ #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) #define GC_DISPLAY_CLOCK_MASK (7 << 4) +#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) +#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) +#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) +#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) +#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) +#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) +#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) +#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) +#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) +#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) +#define I945_GC_RENDER_CLOCK_MASK (7 << 0) +#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) +#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) +#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) +#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) +#define I915_GC_RENDER_CLOCK_MASK (7 << 0) +#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) +#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) +#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) #define LBB 0xf4 /* VGA stuff */ @@ -553,9 +572,118 @@ #define DPLLA_TEST_M_BYPASS (1 << 2) #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) #define D_STATE 0x6104 -#define CG_2D_DIS 0x6200 -#define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) -#define CG_3D_DIS 0x6204 +#define DSTATE_PLL_D3_OFF (1<<3) +#define DSTATE_GFX_CLOCK_GATING (1<<1) +#define DSTATE_DOT_CLOCK_GATING (1<<0) +#define DSPCLK_GATE_D 0x6200 +# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ +# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ +# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ +# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ +# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ +# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ +# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ +# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ +# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ +# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ +# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ +# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ +# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ +# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ +# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ +# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ +# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ +# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ +# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ +# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) +# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) +# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) +# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) +# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ +# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ +# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ +# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) +# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) +/** + * This bit must be set on the 830 to prevent hangs when turning off the + * overlay scaler. + */ +# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) +# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) +# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) +# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ +# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ + +#define RENCLK_GATE_D1 0x6204 +# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ +# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ +# define PC_FE_CLOCK_GATE_DISABLE (1 << 11) +# define PC_BE_CLOCK_GATE_DISABLE (1 << 10) +# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) +# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) +# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) +# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) +# define MAG_CLOCK_GATE_DISABLE (1 << 5) +/** This bit must be unset on 855,865 */ +# define MECI_CLOCK_GATE_DISABLE (1 << 4) +# define DCMP_CLOCK_GATE_DISABLE (1 << 3) +# define MEC_CLOCK_GATE_DISABLE (1 << 2) +# define MECO_CLOCK_GATE_DISABLE (1 << 1) +/** This bit must be set on 855,865. */ +# define SV_CLOCK_GATE_DISABLE (1 << 0) +# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) +# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) +# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) +# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) +# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) +# define I915_WM_CLOCK_GATE_DISABLE (1 << 11) +# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) +# define I915_PI_CLOCK_GATE_DISABLE (1 << 9) +# define I915_DI_CLOCK_GATE_DISABLE (1 << 8) +# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) +# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) +# define I915_SC_CLOCK_GATE_DISABLE (1 << 5) +# define I915_FL_CLOCK_GATE_DISABLE (1 << 4) +# define I915_DM_CLOCK_GATE_DISABLE (1 << 3) +# define I915_PS_CLOCK_GATE_DISABLE (1 << 2) +# define I915_CC_CLOCK_GATE_DISABLE (1 << 1) +# define I915_BY_CLOCK_GATE_DISABLE (1 << 0) + +# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) +/** This bit must always be set on 965G/965GM */ +# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) +# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) +# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) +# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) +# define I965_GW_CLOCK_GATE_DISABLE (1 << 25) +# define I965_TD_CLOCK_GATE_DISABLE (1 << 24) +/** This bit must always be set on 965G */ +# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) +# define I965_IC_CLOCK_GATE_DISABLE (1 << 22) +# define I965_EU_CLOCK_GATE_DISABLE (1 << 21) +# define I965_IF_CLOCK_GATE_DISABLE (1 << 20) +# define I965_TC_CLOCK_GATE_DISABLE (1 << 19) +# define I965_SO_CLOCK_GATE_DISABLE (1 << 17) +# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) +# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) +# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) +# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) +# define I965_EM_CLOCK_GATE_DISABLE (1 << 12) +# define I965_UC_CLOCK_GATE_DISABLE (1 << 11) +# define I965_SI_CLOCK_GATE_DISABLE (1 << 6) +# define I965_MT_CLOCK_GATE_DISABLE (1 << 5) +# define I965_PL_CLOCK_GATE_DISABLE (1 << 4) +# define I965_DG_CLOCK_GATE_DISABLE (1 << 3) +# define I965_QC_CLOCK_GATE_DISABLE (1 << 2) +# define I965_FT_CLOCK_GATE_DISABLE (1 << 1) +# define I965_DM_CLOCK_GATE_DISABLE (1 << 0) + +#define RENCLK_GATE_D2 0x6208 +#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) +#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) +#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) +#define RAMCLK_GATE_D 0x6210 /* CRL only */ +#define DEUC 0x6214 /* CRL only */ /* * Palette regs @@ -1588,6 +1716,7 @@ #define PIPECONF_PROGRESSIVE (0 << 21) #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) +#define PIPECONF_CXSR_DOWNCLOCK (1<<16) #define PIPEASTAT 0x70024 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) #define PIPE_CRC_ERROR_ENABLE (1UL<<29) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 1d04e19..20d4d19 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -461,7 +461,7 @@ int i915_save_state(struct drm_device *dev) /* Clock gating state */ dev_priv->saveD_STATE = I915_READ(D_STATE); - dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS); + dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Cache mode state */ dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); @@ -588,7 +588,7 @@ int i915_restore_state(struct drm_device *dev) /* Clock gating state */ I915_WRITE (D_STATE, dev_priv->saveD_STATE); - I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS); + I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); /* Cache mode state */ I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index f806fcc..1e28c16 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -355,8 +355,14 @@ parse_driver_features(struct drm_i915_private *dev_priv, } driver = find_section(bdb, BDB_DRIVER_FEATURES); - if (driver && driver->lvds_config == BDB_DRIVER_FEATURE_EDP) + if (!driver) + return; + + if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP) dev_priv->edp_support = 1; + + if (driver->dual_frequency) + dev_priv->render_reclock_avail = true; } /** diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 748ed50..3c94451 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -38,6 +38,7 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type); static void intel_update_watermarks(struct drm_device *dev); +static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule); typedef struct { /* given values */ @@ -67,6 +68,8 @@ struct intel_limit { intel_p2_t p2; bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, int, int, intel_clock_t *); + bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *, + int, int, intel_clock_t *); }; #define I8XX_DOT_MIN 25000 @@ -261,6 +264,9 @@ static bool intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, intel_clock_t *best_clock); static bool +intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, + int target, int refclk, intel_clock_t *best_clock); +static bool intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, intel_clock_t *best_clock); static bool @@ -286,6 +292,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = { .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, .find_pll = intel_find_best_PLL, + .find_reduced_pll = intel_find_best_reduced_PLL, }; static const intel_limit_t intel_limits_i8xx_lvds = { @@ -300,6 +307,7 @@ static const intel_limit_t intel_limits_i8xx_lvds = { .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, .find_pll = intel_find_best_PLL, + .find_reduced_pll = intel_find_best_reduced_PLL, }; static const intel_limit_t intel_limits_i9xx_sdvo = { @@ -314,6 +322,7 @@ static const intel_limit_t intel_limits_i9xx_sdvo = { .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, .find_pll = intel_find_best_PLL, + .find_reduced_pll = intel_find_best_reduced_PLL, }; static const intel_limit_t intel_limits_i9xx_lvds = { @@ -331,6 +340,7 @@ static const intel_limit_t intel_limits_i9xx_lvds = { .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, .find_pll = intel_find_best_PLL, + .find_reduced_pll = intel_find_best_reduced_PLL, }; /* below parameter and function is for G4X Chipset Family*/ @@ -348,6 +358,7 @@ static const intel_limit_t intel_limits_g4x_sdvo = { .p2_fast = G4X_P2_SDVO_FAST }, .find_pll = intel_g4x_find_best_PLL, + .find_reduced_pll = intel_g4x_find_best_PLL, }; static const intel_limit_t intel_limits_g4x_hdmi = { @@ -364,6 +375,7 @@ static const intel_limit_t intel_limits_g4x_hdmi = { .p2_fast = G4X_P2_HDMI_DAC_FAST }, .find_pll = intel_g4x_find_best_PLL, + .find_reduced_pll = intel_g4x_find_best_PLL, }; static const intel_limit_t intel_limits_g4x_single_channel_lvds = { @@ -388,6 +400,7 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = { .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST }, .find_pll = intel_g4x_find_best_PLL, + .find_reduced_pll = intel_g4x_find_best_PLL, }; static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { @@ -412,6 +425,7 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST }, .find_pll = intel_g4x_find_best_PLL, + .find_reduced_pll = intel_g4x_find_best_PLL, }; static const intel_limit_t intel_limits_g4x_display_port = { @@ -449,6 +463,7 @@ static const intel_limit_t intel_limits_igd_sdvo = { .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, .find_pll = intel_find_best_PLL, + .find_reduced_pll = intel_find_best_reduced_PLL, }; static const intel_limit_t intel_limits_igd_lvds = { @@ -464,6 +479,7 @@ static const intel_limit_t intel_limits_igd_lvds = { .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, .find_pll = intel_find_best_PLL, + .find_reduced_pll = intel_find_best_reduced_PLL, }; static const intel_limit_t intel_limits_igdng_sdvo = { @@ -688,15 +704,16 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, memset (best_clock, 0, sizeof (*best_clock)); - for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { - for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { - /* m1 is always 0 in IGD */ - if (clock.m2 >= clock.m1 && !IS_IGD(dev)) - break; - for (clock.n = limit->n.min; clock.n <= limit->n.max; - clock.n++) { - for (clock.p1 = limit->p1.min; - clock.p1 <= limit->p1.max; clock.p1++) { + for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { + for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; + clock.m1++) { + for (clock.m2 = limit->m2.min; + clock.m2 <= limit->m2.max; clock.m2++) { + /* m1 is always 0 in IGD */ + if (clock.m2 >= clock.m1 && !IS_IGD(dev)) + break; + for (clock.n = limit->n.min; + clock.n <= limit->n.max; clock.n++) { int this_err; intel_clock(dev, refclk, &clock); @@ -717,6 +734,46 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, return (err != target); } + +static bool +intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, + int target, int refclk, intel_clock_t *best_clock) + +{ + struct drm_device *dev = crtc->dev; + intel_clock_t clock; + int err = target; + bool found = false; + + memcpy(&clock, best_clock, sizeof(intel_clock_t)); + + for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { + for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { + /* m1 is always 0 in IGD */ + if (clock.m2 >= clock.m1 && !IS_IGD(dev)) + break; + for (clock.n = limit->n.min; clock.n <= limit->n.max; + clock.n++) { + int this_err; + + intel_clock(dev, refclk, &clock); + + if (!intel_PLL_is_valid(crtc, &clock)) + continue; + + this_err = abs(clock.dot - target); + if (this_err < err) { + *best_clock = clock; + err = this_err; + found = true; + } + } + } + } + + return found; +} + static bool intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, intel_clock_t *best_clock) @@ -747,7 +804,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, max_n = limit->n.max; /* based on hardware requriment prefer smaller n to precision */ for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { - /* based on hardware requirment prefere larger m1,m2, p1 */ + /* based on hardware requirment prefere larger m1,m2 */ for (clock.m1 = limit->m1.max; clock.m1 >= limit->m1.min; clock.m1--) { for (clock.m2 = limit->m2.max; @@ -832,15 +889,14 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, memset(best_clock, 0, sizeof(*best_clock)); max_n = limit->n.max; - /* based on hardware requriment prefer smaller n to precision */ - for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { - /* based on hardware requirment prefere larger m1,m2, p1 */ - for (clock.m1 = limit->m1.max; - clock.m1 >= limit->m1.min; clock.m1--) { - for (clock.m2 = limit->m2.max; - clock.m2 >= limit->m2.min; clock.m2--) { - for (clock.p1 = limit->p1.max; - clock.p1 >= limit->p1.min; clock.p1--) { + for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { + /* based on hardware requriment prefer smaller n to precision */ + for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { + /* based on hardware requirment prefere larger m1,m2 */ + for (clock.m1 = limit->m1.max; + clock.m1 >= limit->m1.min; clock.m1--) { + for (clock.m2 = limit->m2.max; + clock.m2 >= limit->m2.min; clock.m2--) { int this_err; intel_clock(dev, refclk, &clock); @@ -1030,8 +1086,11 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, if (old_fb) { intel_fb = to_intel_framebuffer(old_fb); + obj_priv = intel_fb->obj->driver_private; i915_gem_object_unpin(intel_fb->obj); } + intel_increase_pllclock(crtc, true); + mutex_unlock(&dev->struct_mutex); if (!dev->primary->master) @@ -2054,6 +2113,18 @@ static int intel_get_fifo_size(struct drm_device *dev, int plane) return size; } +static void g4x_update_wm(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u32 fw_blc_self = I915_READ(FW_BLC_SELF); + + if (i915_powersave) + fw_blc_self |= FW_BLC_SELF_EN; + else + fw_blc_self &= ~FW_BLC_SELF_EN; + I915_WRITE(FW_BLC_SELF, fw_blc_self); +} + static void i965_update_wm(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -2105,7 +2176,8 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, cwm = 2; /* Calc sr entries for one plane configs */ - if (sr_hdisplay && (!planea_clock || !planeb_clock)) { + if (HAS_FW_BLC(dev) && sr_hdisplay && + (!planea_clock || !planeb_clock)) { /* self-refresh has much higher latency */ const static int sr_latency_ns = 6000; @@ -2120,8 +2192,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, srwm = total_size - sr_entries; if (srwm < 0) srwm = 1; - if (IS_I9XX(dev)) - I915_WRITE(FW_BLC_SELF, (srwm & 0x3f)); + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); } DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", @@ -2195,9 +2266,6 @@ static void intel_update_watermarks(struct drm_device *dev) unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; int enabled = 0, pixel_size = 0; - if (DSPARB_HWCONTROL(dev)) - return; - /* Get the clock config from both planes */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { intel_crtc = to_intel_crtc(crtc); @@ -2230,7 +2298,9 @@ static void intel_update_watermarks(struct drm_device *dev) else if (IS_IGD(dev)) igd_disable_cxsr(dev); - if (IS_I965G(dev)) + if (IS_G4X(dev)) + g4x_update_wm(dev); + else if (IS_I965G(dev)) i965_update_wm(dev); else if (IS_I9XX(dev) || IS_MOBILE(dev)) i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay, @@ -2264,9 +2334,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; int refclk, num_outputs = 0; - intel_clock_t clock; - u32 dpll = 0, fp = 0, dspcntr, pipeconf; - bool ok, is_sdvo = false, is_dvo = false; + intel_clock_t clock, reduced_clock; + u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; + bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; bool is_edp = false; struct drm_mode_config *mode_config = &dev->mode_config; @@ -2349,6 +2419,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, return -EINVAL; } + if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) { + memcpy(&reduced_clock, &clock, sizeof(intel_clock_t)); + has_reduced_clock = limit->find_reduced_pll(limit, crtc, + (adjusted_mode->clock*3/4), + refclk, + &reduced_clock); + } + /* SDVO TV has fixed PLL values depend on its clock range, this mirrors vbios setting. */ if (is_sdvo && is_tv) { @@ -2394,10 +2472,17 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, link_bw, &m_n); } - if (IS_IGD(dev)) + if (IS_IGD(dev)) { fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; - else + if (has_reduced_clock) + fp2 = (1 << reduced_clock.n) << 16 | + reduced_clock.m1 << 8 | reduced_clock.m2; + } else { fp = clock.n << 16 | clock.m1 << 8 | clock.m2; + if (has_reduced_clock) + fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | + reduced_clock.m2; + } if (!IS_IGDNG(dev)) dpll = DPLL_VGA_MODE_DIS; @@ -2426,6 +2511,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, /* also FPA1 */ if (IS_IGDNG(dev)) dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; + if (IS_G4X(dev) && has_reduced_clock) + dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; } switch (clock.p2) { case 5: @@ -2573,6 +2660,22 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, udelay(150); } + if (is_lvds && has_reduced_clock && i915_powersave) { + I915_WRITE(fp_reg + 4, fp2); + intel_crtc->lowfreq_avail = true; + if (HAS_PIPE_CXSR(dev)) { + DRM_DEBUG("enabling CxSR downclocking\n"); + pipeconf |= PIPECONF_CXSR_DOWNCLOCK; + } + } else { + I915_WRITE(fp_reg + 4, fp); + intel_crtc->lowfreq_avail = false; + if (HAS_PIPE_CXSR(dev)) { + DRM_DEBUG("disabling CxSR downclocking\n"); + pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; + } + } + I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | @@ -2769,10 +2872,16 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_framebuffer *intel_fb; int pipe = intel_crtc->pipe; uint32_t temp = 0; uint32_t adder; + if (crtc->fb) { + intel_fb = to_intel_framebuffer(crtc->fb); + intel_mark_busy(dev, intel_fb->obj); + } + if (x < 0) { temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; x = -x; @@ -3070,6 +3179,312 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, return mode; } +#define GPU_IDLE_TIMEOUT 500 /* ms */ + +/* When this timer fires, we've been idle for awhile */ +static void intel_gpu_idle_timer(unsigned long arg) +{ + struct drm_device *dev = (struct drm_device *)arg; + drm_i915_private_t *dev_priv = dev->dev_private; + + DRM_DEBUG("idle timer fired, downclocking\n"); + + dev_priv->busy = false; + + schedule_work(&dev_priv->idle_work); +} + +void intel_increase_renderclock(struct drm_device *dev, bool schedule) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + + if (IS_IGDNG(dev)) + return; + + if (!dev_priv->render_reclock_avail) { + DRM_ERROR("not reclocking render clock\n"); + return; + } + + /* Restore render clock frequency to original value */ + if (IS_G4X(dev) || IS_I9XX(dev)) + pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock); + else if (IS_I85X(dev)) + pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock); + DRM_DEBUG("increasing render clock frequency\n"); + + /* Schedule downclock */ + if (schedule) + mod_timer(&dev_priv->idle_timer, jiffies + + msecs_to_jiffies(GPU_IDLE_TIMEOUT)); +} + +void intel_decrease_renderclock(struct drm_device *dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + + if (IS_IGDNG(dev)) + return; + + if (!dev_priv->render_reclock_avail) { + DRM_ERROR("not reclocking render clock\n"); + return; + } + + if (IS_G4X(dev)) { + u16 gcfgc; + + /* Adjust render clock... */ + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + /* Down to minimum... */ + gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK; + gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ; + + pci_write_config_word(dev->pdev, GCFGC, gcfgc); + } else if (IS_I965G(dev)) { + u16 gcfgc; + + /* Adjust render clock... */ + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + /* Down to minimum... */ + gcfgc &= ~I965_GC_RENDER_CLOCK_MASK; + gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ; + + pci_write_config_word(dev->pdev, GCFGC, gcfgc); + } else if (IS_I945G(dev) || IS_I945GM(dev)) { + u16 gcfgc; + + /* Adjust render clock... */ + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + /* Down to minimum... */ + gcfgc &= ~I945_GC_RENDER_CLOCK_MASK; + gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ; + + pci_write_config_word(dev->pdev, GCFGC, gcfgc); + } else if (IS_I915G(dev)) { + u16 gcfgc; + + /* Adjust render clock... */ + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + /* Down to minimum... */ + gcfgc &= ~I915_GC_RENDER_CLOCK_MASK; + gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ; + + pci_write_config_word(dev->pdev, GCFGC, gcfgc); + } else if (IS_I85X(dev)) { + u16 hpllcc; + + /* Adjust render clock... */ + pci_read_config_word(dev->pdev, HPLLCC, &hpllcc); + + /* Up to maximum... */ + hpllcc &= ~GC_CLOCK_CONTROL_MASK; + hpllcc |= GC_CLOCK_133_200; + + pci_write_config_word(dev->pdev, HPLLCC, hpllcc); + } + DRM_DEBUG("decreasing render clock frequency\n"); +} + +/* Note that no increase function is needed for this - increase_renderclock() + * will also rewrite these bits + */ +void intel_decrease_displayclock(struct drm_device *dev) +{ + if (IS_IGDNG(dev)) + return; + + if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) || + IS_I915GM(dev)) { + u16 gcfgc; + + /* Adjust render clock... */ + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + /* Down to minimum... */ + gcfgc &= ~0xf0; + gcfgc |= 0x80; + + pci_write_config_word(dev->pdev, GCFGC, gcfgc); + } +} + +#define CRTC_IDLE_TIMEOUT 1000 /* ms */ + +static void intel_crtc_idle_timer(unsigned long arg) +{ + struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; + struct drm_crtc *crtc = &intel_crtc->base; + drm_i915_private_t *dev_priv = crtc->dev->dev_private; + + DRM_DEBUG("idle timer fired, downclocking\n"); + + intel_crtc->busy = false; + + schedule_work(&dev_priv->idle_work); +} + +static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule) +{ + struct drm_device *dev = crtc->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; + int dpll = I915_READ(dpll_reg); + + if (IS_IGDNG(dev)) + return; + + if (!dev_priv->lvds_downclock_avail) + return; + + if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { + DRM_DEBUG("upclocking LVDS\n"); + + /* Unlock panel regs */ + I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); + + dpll &= ~DISPLAY_RATE_SELECT_FPA1; + I915_WRITE(dpll_reg, dpll); + dpll = I915_READ(dpll_reg); + intel_wait_for_vblank(dev); + dpll = I915_READ(dpll_reg); + if (dpll & DISPLAY_RATE_SELECT_FPA1) + DRM_DEBUG("failed to upclock LVDS!\n"); + + /* ...and lock them again */ + I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); + } + + /* Schedule downclock */ + if (schedule) + mod_timer(&intel_crtc->idle_timer, jiffies + + msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); +} + +static void intel_decrease_pllclock(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + drm_i915_private_t *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; + int dpll = I915_READ(dpll_reg); + + if (IS_IGDNG(dev)) + return; + + if (!dev_priv->lvds_downclock_avail) + return; + + /* + * Since this is called by a timer, we should never get here in + * the manual case. + */ + if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { + DRM_DEBUG("downclocking LVDS\n"); + + /* Unlock panel regs */ + I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); + + dpll |= DISPLAY_RATE_SELECT_FPA1; + I915_WRITE(dpll_reg, dpll); + dpll = I915_READ(dpll_reg); + intel_wait_for_vblank(dev); + dpll = I915_READ(dpll_reg); + if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) + DRM_DEBUG("failed to downclock LVDS!\n"); + + /* ...and lock them again */ + I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); + } + +} + +/** + * intel_idle_update - adjust clocks for idleness + * @work: work struct + * + * Either the GPU or display (or both) went idle. Check the busy status + * here and adjust the CRTC and GPU clocks as necessary. + */ +static void intel_idle_update(struct work_struct *work) +{ + drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, + idle_work); + struct drm_device *dev = dev_priv->dev; + struct drm_crtc *crtc; + struct intel_crtc *intel_crtc; + + if (!i915_powersave) + return; + + mutex_lock(&dev->struct_mutex); + + /* GPU isn't processing, downclock it. */ + if (!dev_priv->busy) { + intel_decrease_renderclock(dev); + intel_decrease_displayclock(dev); + } + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + /* Skip inactive CRTCs */ + if (!crtc->fb) + continue; + + intel_crtc = to_intel_crtc(crtc); + if (!intel_crtc->busy) + intel_decrease_pllclock(crtc); + } + + mutex_unlock(&dev->struct_mutex); +} + +/** + * intel_mark_busy - mark the GPU and possibly the display busy + * @dev: drm device + * @obj: object we're operating on + * + * Callers can use this function to indicate that the GPU is busy processing + * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout + * buffer), we'll also mark the display as busy, so we know to increase its + * clock frequency. + */ +void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + struct drm_crtc *crtc = NULL; + struct intel_framebuffer *intel_fb; + struct intel_crtc *intel_crtc; + + dev_priv->busy = true; + intel_increase_renderclock(dev, true); + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + if (!crtc->fb) + continue; + + intel_crtc = to_intel_crtc(crtc); + intel_fb = to_intel_framebuffer(crtc->fb); + if (intel_fb->obj == obj) { + if (!intel_crtc->busy) { + /* Non-busy -> busy, upclock */ + intel_increase_pllclock(crtc, true); + intel_crtc->busy = true; + } else { + /* Busy -> busy, put off timer */ + mod_timer(&intel_crtc->idle_timer, jiffies + + msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); + } + } + } +} + static void intel_crtc_destroy(struct drm_crtc *crtc) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); @@ -3125,6 +3540,10 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) intel_crtc->mode_set.crtc = &intel_crtc->base; intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1); intel_crtc->mode_set.num_connectors = 0; + intel_crtc->busy = false; + + setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, + (unsigned long)intel_crtc); if (i915_fbpercrtc) { @@ -3362,8 +3781,56 @@ static const struct drm_mode_config_funcs intel_mode_funcs = { .fb_changed = intelfb_probe, }; +void intel_init_clock_gating(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + /* + * Disable clock gating reported to work incorrectly according to the + * specs, but enable as much else as we can. + */ + if (IS_G4X(dev)) { + uint32_t dspclk_gate; + I915_WRITE(RENCLK_GATE_D1, 0); + I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | + GS_UNIT_CLOCK_GATE_DISABLE | + CL_UNIT_CLOCK_GATE_DISABLE); + I915_WRITE(RAMCLK_GATE_D, 0); + dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | + OVRUNIT_CLOCK_GATE_DISABLE | + OVCUNIT_CLOCK_GATE_DISABLE; + if (IS_GM45(dev)) + dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; + I915_WRITE(DSPCLK_GATE_D, dspclk_gate); + } else if (IS_I965GM(dev)) { + I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); + I915_WRITE(RENCLK_GATE_D2, 0); + I915_WRITE(DSPCLK_GATE_D, 0); + I915_WRITE(RAMCLK_GATE_D, 0); + I915_WRITE16(DEUC, 0); + } else if (IS_I965G(dev)) { + I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | + I965_RCC_CLOCK_GATE_DISABLE | + I965_RCPB_CLOCK_GATE_DISABLE | + I965_ISC_CLOCK_GATE_DISABLE | + I965_FBC_CLOCK_GATE_DISABLE); + I915_WRITE(RENCLK_GATE_D2, 0); + } else if (IS_I9XX(dev)) { + u32 dstate = I915_READ(D_STATE); + + dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | + DSTATE_DOT_CLOCK_GATING; + I915_WRITE(D_STATE, dstate); + } else if (IS_I855(dev) || IS_I865G(dev)) { + I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); + } else if (IS_I830(dev)) { + I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); + } +} + void intel_modeset_init(struct drm_device *dev) { + struct drm_i915_private *dev_priv = dev->dev_private; int num_pipe; int i; @@ -3398,15 +3865,47 @@ void intel_modeset_init(struct drm_device *dev) DRM_DEBUG("%d display pipe%s available.\n", num_pipe, num_pipe > 1 ? "s" : ""); + if (IS_I85X(dev)) + pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock); + else if (IS_I9XX(dev) || IS_G4X(dev)) + pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock); + for (i = 0; i < num_pipe; i++) { intel_crtc_init(dev, i); } intel_setup_outputs(dev); + + intel_init_clock_gating(dev); + + INIT_WORK(&dev_priv->idle_work, intel_idle_update); + setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, + (unsigned long)dev); } void intel_modeset_cleanup(struct drm_device *dev) { + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_crtc *crtc; + struct intel_crtc *intel_crtc; + + mutex_lock(&dev->struct_mutex); + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + /* Skip inactive CRTCs */ + if (!crtc->fb) + continue; + + intel_crtc = to_intel_crtc(crtc); + intel_increase_pllclock(crtc, false); + del_timer_sync(&intel_crtc->idle_timer); + } + + intel_increase_renderclock(dev, false); + del_timer_sync(&dev_priv->idle_timer); + + mutex_unlock(&dev->struct_mutex); + drm_mode_config_cleanup(dev); } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 25aa6fa..495dc95 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -119,6 +119,9 @@ struct intel_crtc { struct intel_framebuffer *fbdev_fb; /* a mode_set for fbdev users on this crtc */ struct drm_mode_set mode_set; + bool busy; /* is scanout buffer being updated frequently? */ + struct timer_list idle_timer; + bool lowfreq_avail; }; #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) @@ -137,6 +140,7 @@ extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg); extern bool intel_sdvo_init(struct drm_device *dev, int output_device); extern void intel_dvo_init(struct drm_device *dev); extern void intel_tv_init(struct drm_device *dev); +extern void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj); extern void intel_lvds_init(struct drm_device *dev); extern void intel_dp_init(struct drm_device *dev, int dp_reg); void diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 62b8bea..c7eab72 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -42,11 +42,11 @@ void intel_i2c_quirk_set(struct drm_device *dev, bool enable) if (!IS_IGD(dev)) return; if (enable) - I915_WRITE(CG_2D_DIS, - I915_READ(CG_2D_DIS) | DPCUNIT_CLOCK_GATE_DISABLE); + I915_WRITE(DSPCLK_GATE_D, + I915_READ(DSPCLK_GATE_D) | DPCUNIT_CLOCK_GATE_DISABLE); else - I915_WRITE(CG_2D_DIS, - I915_READ(CG_2D_DIS) & (~DPCUNIT_CLOCK_GATE_DISABLE)); + I915_WRITE(DSPCLK_GATE_D, + I915_READ(DSPCLK_GATE_D) & (~DPCUNIT_CLOCK_GATE_DISABLE)); } /* -- cgit v0.10.2 From d6073d775c4b26107351cb8d5e21cec4391f6314 Mon Sep 17 00:00:00 2001 From: Kyle McMartin Date: Tue, 26 May 2009 12:27:34 -0400 Subject: drm/i915: i915_modeset is signed Signed-off-by: Kyle McMartin Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 81ab488..dbe568c 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -37,7 +37,7 @@ #include #include "drm_crtc_helper.h" -static unsigned int i915_modeset = -1; +static int i915_modeset = -1; module_param_named(modeset, i915_modeset, int, 0400); unsigned int i915_fbpercrtc = 0; -- cgit v0.10.2 From 67cf781bea52d461b7c8b63b23be19e87c33d7bf Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 31 Aug 2009 08:52:02 -0700 Subject: drm/i915: Make the downclocking debug code be under DRM_DEBUG not DRM_ERROR. Signed-off-by: Eric Anholt Reviewed-by: Jesse Barnes diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3c94451..35e8619 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3202,7 +3202,7 @@ void intel_increase_renderclock(struct drm_device *dev, bool schedule) return; if (!dev_priv->render_reclock_avail) { - DRM_ERROR("not reclocking render clock\n"); + DRM_DEBUG("not reclocking render clock\n"); return; } @@ -3227,7 +3227,7 @@ void intel_decrease_renderclock(struct drm_device *dev) return; if (!dev_priv->render_reclock_avail) { - DRM_ERROR("not reclocking render clock\n"); + DRM_DEBUG("not reclocking render clock\n"); return; } -- cgit v0.10.2 From c05422d52ee6b4cff8b63eab1a7351780518fc5e Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 11 Aug 2009 16:05:30 +0200 Subject: drm/i915: remove open-coded drm_mode_object_find And clean up a small whitespace goof-up in the same function, while I was looking at it. Signed-off-by: Daniel Vetter Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 35e8619..f0f38f5 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3557,30 +3557,26 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, { drm_i915_private_t *dev_priv = dev->dev_private; struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; - struct drm_crtc *crtc = NULL; - int pipe = -1; + struct drm_mode_object *drmmode_obj; + struct intel_crtc *crtc; if (!dev_priv) { DRM_ERROR("called with no initialization\n"); return -EINVAL; } - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - if (crtc->base.id == pipe_from_crtc_id->crtc_id) { - pipe = intel_crtc->pipe; - break; - } - } + drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, + DRM_MODE_OBJECT_CRTC); - if (pipe == -1) { + if (!drmmode_obj) { DRM_ERROR("no such CRTC id\n"); return -EINVAL; } - pipe_from_crtc_id->pipe = pipe; + crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); + pipe_from_crtc_id->pipe = crtc->pipe; - return 0; + return 0; } struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) -- cgit v0.10.2 From 65655d4ab72456c4c3e503fead55fabf8211a79d Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 11 Aug 2009 16:05:31 +0200 Subject: drm/i915: modeset: always set intel_crtc->dpms_mode by moving the assignment up. Signed-off-by: Daniel Vetter Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f0f38f5..867a969 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1640,6 +1640,8 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) else i9xx_crtc_dpms(crtc, mode); + intel_crtc->dpms_mode = mode; + if (!dev->primary->master) return; @@ -1662,8 +1664,6 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); break; } - - intel_crtc->dpms_mode = mode; } static void intel_crtc_prepare (struct drm_crtc *crtc) -- cgit v0.10.2 From 553bd149bb2de7848b2b84642876f27202421368 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Wed, 2 Sep 2009 10:57:52 +0800 Subject: drm/i915: fix tiling on IGDNG It seems that on IGDNG the same swizzling setup always applys. And front buffer tiling needs to set address swizzle in display arb control too. Fix plane tricle feed setting in v1 which should be disable bit, and always setup address swizzle to let hardware care for buffer tiling in all cases. Signed-off-by: Zhenyu Wang Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index a2d527b..e774a4a 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -234,7 +234,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; bool need_disable; - if (!IS_I9XX(dev)) { + if (IS_IGDNG(dev)) { + /* On IGDNG whatever DRAM config, GPU always do + * same swizzling setup. + */ + swizzle_x = I915_BIT_6_SWIZZLE_9_10; + swizzle_y = I915_BIT_6_SWIZZLE_9; + } else if (!IS_I9XX(dev)) { /* As far as we know, the 865 doesn't have these bit 6 * swizzling issues. */ @@ -317,13 +323,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) } } - /* FIXME: check with memory config on IGDNG */ - if (IS_IGDNG(dev)) { - DRM_ERROR("disable tiling on IGDNG...\n"); - swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; - swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - } - dev_priv->mm.bit_6_swizzle_x = swizzle_x; dev_priv->mm.bit_6_swizzle_y = swizzle_y; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 884757c..e38cd21 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1864,6 +1864,7 @@ #define DISPPLANE_NO_LINE_DOUBLE 0 #define DISPPLANE_STEREO_POLARITY_FIRST 0 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) +#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* IGDNG */ #define DISPPLANE_TILED (1<<10) #define DSPAADDR 0x70184 #define DSPASTRIDE 0x70188 @@ -2044,6 +2045,9 @@ #define GTIIR 0x44018 #define GTIER 0x4401c +#define DISP_ARB_CTL 0x45000 +#define DISP_TILE_SURFACE_SWIZZLING (1<<13) + /* PCH */ /* south display engine interrupt */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 867a969..d7c7fa4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1064,6 +1064,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, dspcntr &= ~DISPPLANE_TILED; } + if (IS_IGDNG(dev)) + /* must disable */ + dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; + I915_WRITE(dspcntr_reg, dspcntr); Start = obj_priv->gtt_offset; @@ -2719,6 +2723,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, intel_wait_for_vblank(dev); + if (IS_IGDNG(dev)) { + /* enable address swizzle for tiling buffer */ + temp = I915_READ(DISP_ARB_CTL); + I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); + } + I915_WRITE(dspcntr_reg, dspcntr); /* Flush the plane changes */ -- cgit v0.10.2 From 57cdaf90f5f607eb029356074fefb66c9b1c0659 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 4 Sep 2009 13:07:54 +0800 Subject: drm/I915: Use the CRT DDC to get the EDID for DVI-connector on Mac mac Mini's have a single DDC line on the DVI connector, shared between the analog link and the digital link. So, if DDC isn't detected on GPIOE (the usual SDVO DDC link), try GPIOA (the usual VGA DDC link) when there isn't a VGA monitor connected. Signed-off-by: Keith Packard Signed-off-by: Zhao Yakui Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index cabe32d..c585da8 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -127,6 +127,9 @@ struct intel_sdvo_priv { /* DDC bus used by this SDVO output */ uint8_t ddc_bus; + /* Mac mini hack -- use the same DDC as the analog connector */ + struct i2c_adapter *analog_ddc_bus; + int save_sdvo_mult; u16 save_active_outputs; struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2; @@ -1496,6 +1499,36 @@ intel_sdvo_multifunc_encoder(struct intel_output *intel_output) return (caps > 1); } +static struct drm_connector * +intel_find_analog_connector(struct drm_device *dev) +{ + struct drm_connector *connector; + struct intel_output *intel_output; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + intel_output = to_intel_output(connector); + if (intel_output->type == INTEL_OUTPUT_ANALOG) + return connector; + } + return NULL; +} + +static int +intel_analog_is_connected(struct drm_device *dev) +{ + struct drm_connector *analog_connector; + analog_connector = intel_find_analog_connector(dev); + + if (!analog_connector) + return false; + + if (analog_connector->funcs->detect(analog_connector) == + connector_status_disconnected) + return false; + + return true; +} + enum drm_connector_status intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response) { @@ -1506,6 +1539,15 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response) edid = drm_get_edid(&intel_output->base, intel_output->ddc_bus); + + /* when there is no edid and no monitor is connected with VGA + * port, try to use the CRT ddc to read the EDID for DVI-connector + */ + if (edid == NULL && + sdvo_priv->analog_ddc_bus && + !intel_analog_is_connected(intel_output->base.dev)) + edid = drm_get_edid(&intel_output->base, + sdvo_priv->analog_ddc_bus); if (edid != NULL) { /* Don't report the output as connected if it's a DVI-I * connector with a non-digital EDID coming out. @@ -1559,31 +1601,32 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) { struct intel_output *intel_output = to_intel_output(connector); + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + int num_modes; /* set the bus switch and get the modes */ - intel_ddc_get_modes(intel_output); + num_modes = intel_ddc_get_modes(intel_output); -#if 0 - struct drm_device *dev = encoder->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - /* Mac mini hack. On this device, I get DDC through the analog, which - * load-detects as disconnected. I fail to DDC through the SDVO DDC, - * but it does load-detect as connected. So, just steal the DDC bits - * from analog when we fail at finding it the right way. + /* + * Mac mini hack. On this device, the DVI-I connector shares one DDC + * link between analog and digital outputs. So, if the regular SDVO + * DDC fails, check to see if the analog output is disconnected, in + * which case we'll look there for the digital DDC data. */ - crt = xf86_config->output[0]; - intel_output = crt->driver_private; - if (intel_output->type == I830_OUTPUT_ANALOG && - crt->funcs->detect(crt) == XF86OutputStatusDisconnected) { - I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A"); - edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus); - xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true); - } - if (edid_mon) { - xf86OutputSetEDID(output, edid_mon); - modes = xf86OutputGetEDIDModes(output); + if (num_modes == 0 && + sdvo_priv->analog_ddc_bus && + !intel_analog_is_connected(intel_output->base.dev)) { + struct i2c_adapter *digital_ddc_bus; + + /* Switch to the analog ddc bus and try that + */ + digital_ddc_bus = intel_output->ddc_bus; + intel_output->ddc_bus = sdvo_priv->analog_ddc_bus; + + (void) intel_ddc_get_modes(intel_output); + + intel_output->ddc_bus = digital_ddc_bus; } -#endif } /* @@ -1758,6 +1801,8 @@ static void intel_sdvo_destroy(struct drm_connector *connector) intel_i2c_destroy(intel_output->i2c_bus); if (intel_output->ddc_bus) intel_i2c_destroy(intel_output->ddc_bus); + if (sdvo_priv->analog_ddc_bus) + intel_i2c_destroy(sdvo_priv->analog_ddc_bus); if (sdvo_priv->sdvo_lvds_fixed_mode != NULL) drm_mode_destroy(connector->dev, @@ -2177,10 +2222,15 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) } /* setup the DDC bus. */ - if (output_device == SDVOB) + if (output_device == SDVOB) { intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS"); - else + sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, + "SDVOB/VGA DDC BUS"); + } else { intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS"); + sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, + "SDVOC/VGA DDC BUS"); + } if (intel_output->ddc_bus == NULL) goto err_i2c; @@ -2248,6 +2298,8 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device) return true; err_i2c: + if (sdvo_priv->analog_ddc_bus != NULL) + intel_i2c_destroy(sdvo_priv->analog_ddc_bus); if (intel_output->ddc_bus != NULL) intel_i2c_destroy(intel_output->ddc_bus); if (intel_output->i2c_bus != NULL) -- cgit v0.10.2 From 5e17ee74b541b56b5d4cfab6502a5116f224e32c Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Thu, 3 Sep 2009 09:30:06 +0800 Subject: drm/i915: do dynamic clock freq control only in kernel modesetting Signed-off-by: Zhenyu Wang Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d7c7fa4..9aa1d2d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3472,6 +3472,9 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) struct intel_framebuffer *intel_fb; struct intel_crtc *intel_crtc; + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + return; + dev_priv->busy = true; intel_increase_renderclock(dev, true); -- cgit v0.10.2 From 47460d65a483529b3bc2bf6ccf461ad45f94df83 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Tue, 10 Feb 2009 16:05:07 -0800 Subject: ocfs2: Make the ocfs2_caching_info structure self-contained. We want to use the ocfs2_caching_info structure in places that are not inodes. To do that, it can no longer rely on referencing the inode directly. This patch moves the flags to ocfs2_caching_info->ci_flags, stores pointers to the parent's locks on the ocfs2_caching_info, and renames the constants and flags to reflect its independant state. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/inode.c b/fs/ocfs2/inode.c index 4dc8890..8ec8044 100644 --- a/fs/ocfs2/inode.c +++ b/fs/ocfs2/inode.c @@ -1118,7 +1118,8 @@ void ocfs2_clear_inode(struct inode *inode) "Clear inode of %llu, inode has %u cache items\n", (unsigned long long)oi->ip_blkno, oi->ip_metadata_cache.ci_num_cached); - mlog_bug_on_msg(!(oi->ip_flags & OCFS2_INODE_CACHE_INLINE), + mlog_bug_on_msg(!(oi->ip_metadata_cache.ci_flags & + OCFS2_CACHE_FL_INLINE), "Clear inode of %llu, inode has a bad flag\n", (unsigned long long)oi->ip_blkno); @@ -1145,7 +1146,7 @@ void ocfs2_clear_inode(struct inode *inode) (unsigned long long)oi->ip_blkno, oi->ip_open_count); /* Clear all other flags. */ - oi->ip_flags = OCFS2_INODE_CACHE_INLINE; + oi->ip_flags = 0; oi->ip_created_trans = 0; oi->ip_last_trans = 0; oi->ip_dir_start_lookup = 0; diff --git a/fs/ocfs2/inode.h b/fs/ocfs2/inode.h index ea71525..2f5e1aa 100644 --- a/fs/ocfs2/inode.h +++ b/fs/ocfs2/inode.h @@ -106,8 +106,6 @@ struct ocfs2_inode_info #define OCFS2_INODE_MAYBE_ORPHANED 0x00000020 /* Does someone have the file open O_DIRECT */ #define OCFS2_INODE_OPEN_DIRECT 0x00000040 -/* Indicates that the metadata cache should be used as an array. */ -#define OCFS2_INODE_CACHE_INLINE 0x00000080 static inline struct ocfs2_inode_info *OCFS2_I(struct inode *inode) { diff --git a/fs/ocfs2/ocfs2.h b/fs/ocfs2/ocfs2.h index 39e1d5a..eef3bd0 100644 --- a/fs/ocfs2/ocfs2.h +++ b/fs/ocfs2/ocfs2.h @@ -51,17 +51,36 @@ /* For struct ocfs2_blockcheck_stats */ #include "blockcheck.h" + +/* Caching of metadata buffers */ + /* Most user visible OCFS2 inodes will have very few pieces of * metadata, but larger files (including bitmaps, etc) must be taken * into account when designing an access scheme. We allow a small * amount of inlined blocks to be stored on an array and grow the * structure into a rb tree when necessary. */ -#define OCFS2_INODE_MAX_CACHE_ARRAY 2 +#define OCFS2_CACHE_INFO_MAX_ARRAY 2 + +/* Flags for ocfs2_caching_info */ + +enum ocfs2_caching_info_flags { + /* Indicates that the metadata cache is using the inline array */ + OCFS2_CACHE_FL_INLINE = 1<<1, +}; struct ocfs2_caching_info { + /* + * The parent structure provides the locks, but because the + * parent structure can differ, struct ocfs2_caching_info needs + * its own pointers to them. + */ + spinlock_t *ci_lock; + struct mutex *ci_io_mutex; + + unsigned int ci_flags; unsigned int ci_num_cached; union { - sector_t ci_array[OCFS2_INODE_MAX_CACHE_ARRAY]; + sector_t ci_array[OCFS2_CACHE_INFO_MAX_ARRAY]; struct rb_root ci_tree; } ci_cache; }; diff --git a/fs/ocfs2/super.c b/fs/ocfs2/super.c index a3f8871..8f217f6 100644 --- a/fs/ocfs2/super.c +++ b/fs/ocfs2/super.c @@ -1683,7 +1683,8 @@ static void ocfs2_inode_init_once(void *data) ocfs2_lock_res_init_once(&oi->ip_inode_lockres); ocfs2_lock_res_init_once(&oi->ip_open_lockres); - ocfs2_metadata_cache_init(&oi->vfs_inode); + ocfs2_metadata_cache_init(&oi->ip_metadata_cache, &oi->ip_lock, + &oi->ip_io_mutex); inode_init_once(&oi->vfs_inode); } diff --git a/fs/ocfs2/uptodate.c b/fs/ocfs2/uptodate.c index 187b99f..8dbc457 100644 --- a/fs/ocfs2/uptodate.c +++ b/fs/ocfs2/uptodate.c @@ -75,12 +75,13 @@ struct ocfs2_meta_cache_item { static struct kmem_cache *ocfs2_uptodate_cachep = NULL; -void ocfs2_metadata_cache_init(struct inode *inode) +void ocfs2_metadata_cache_init(struct ocfs2_caching_info *ci, + spinlock_t *cache_lock, + struct mutex *io_mutex) { - struct ocfs2_inode_info *oi = OCFS2_I(inode); - struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; - - oi->ip_flags |= OCFS2_INODE_CACHE_INLINE; + ci->ci_lock = cache_lock; + ci->ci_io_mutex = io_mutex; + ci->ci_flags |= OCFS2_CACHE_FL_INLINE; ci->ci_num_cached = 0; } @@ -119,8 +120,8 @@ void ocfs2_metadata_cache_purge(struct inode *inode) struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; struct rb_root root = RB_ROOT; - spin_lock(&oi->ip_lock); - tree = !(oi->ip_flags & OCFS2_INODE_CACHE_INLINE); + spin_lock(ci->ci_lock); + tree = !(ci->ci_flags & OCFS2_CACHE_FL_INLINE); to_purge = ci->ci_num_cached; mlog(0, "Purge %u %s items from Inode %llu\n", to_purge, @@ -132,8 +133,8 @@ void ocfs2_metadata_cache_purge(struct inode *inode) if (tree) root = ci->ci_cache.ci_tree; - ocfs2_metadata_cache_init(inode); - spin_unlock(&oi->ip_lock); + ocfs2_metadata_cache_init(ci, ci->ci_lock, ci->ci_io_mutex); + spin_unlock(ci->ci_lock); purged = ocfs2_purge_copied_metadata_tree(&root); /* If possible, track the number wiped so that we can more @@ -187,22 +188,23 @@ static int ocfs2_buffer_cached(struct ocfs2_inode_info *oi, { int index = -1; struct ocfs2_meta_cache_item *item = NULL; + struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; - spin_lock(&oi->ip_lock); + spin_lock(ci->ci_lock); mlog(0, "Inode %llu, query block %llu (inline = %u)\n", (unsigned long long)oi->ip_blkno, (unsigned long long) bh->b_blocknr, - !!(oi->ip_flags & OCFS2_INODE_CACHE_INLINE)); + !!(ci->ci_flags & OCFS2_CACHE_FL_INLINE)); - if (oi->ip_flags & OCFS2_INODE_CACHE_INLINE) + if (ci->ci_flags & OCFS2_CACHE_FL_INLINE) index = ocfs2_search_cache_array(&oi->ip_metadata_cache, bh->b_blocknr); else item = ocfs2_search_cache_tree(&oi->ip_metadata_cache, bh->b_blocknr); - spin_unlock(&oi->ip_lock); + spin_unlock(ci->ci_lock); mlog(0, "index = %d, item = %p\n", index, item); @@ -235,7 +237,7 @@ int ocfs2_buffer_uptodate(struct inode *inode, /* * Determine whether a buffer is currently out on a read-ahead request. - * ip_io_sem should be held to serialize submitters with the logic here. + * ci_io_sem should be held to serialize submitters with the logic here. */ int ocfs2_buffer_read_ahead(struct inode *inode, struct buffer_head *bh) @@ -247,7 +249,7 @@ int ocfs2_buffer_read_ahead(struct inode *inode, static void ocfs2_append_cache_array(struct ocfs2_caching_info *ci, sector_t block) { - BUG_ON(ci->ci_num_cached >= OCFS2_INODE_MAX_CACHE_ARRAY); + BUG_ON(ci->ci_num_cached >= OCFS2_CACHE_INFO_MAX_ARRAY); mlog(0, "block %llu takes position %u\n", (unsigned long long) block, ci->ci_num_cached); @@ -295,13 +297,13 @@ static void __ocfs2_insert_cache_tree(struct ocfs2_caching_info *ci, static inline int ocfs2_insert_can_use_array(struct ocfs2_inode_info *oi, struct ocfs2_caching_info *ci) { - assert_spin_locked(&oi->ip_lock); + assert_spin_locked(ci->ci_lock); - return (oi->ip_flags & OCFS2_INODE_CACHE_INLINE) && - (ci->ci_num_cached < OCFS2_INODE_MAX_CACHE_ARRAY); + return (ci->ci_flags & OCFS2_CACHE_FL_INLINE) && + (ci->ci_num_cached < OCFS2_CACHE_INFO_MAX_ARRAY); } -/* tree should be exactly OCFS2_INODE_MAX_CACHE_ARRAY wide. NULL the +/* tree should be exactly OCFS2_CACHE_INFO_MAX_ARRAY wide. NULL the * pointers in tree after we use them - this allows caller to detect * when to free in case of error. */ static void ocfs2_expand_cache(struct ocfs2_inode_info *oi, @@ -310,32 +312,32 @@ static void ocfs2_expand_cache(struct ocfs2_inode_info *oi, int i; struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; - mlog_bug_on_msg(ci->ci_num_cached != OCFS2_INODE_MAX_CACHE_ARRAY, + mlog_bug_on_msg(ci->ci_num_cached != OCFS2_CACHE_INFO_MAX_ARRAY, "Inode %llu, num cached = %u, should be %u\n", (unsigned long long)oi->ip_blkno, ci->ci_num_cached, - OCFS2_INODE_MAX_CACHE_ARRAY); - mlog_bug_on_msg(!(oi->ip_flags & OCFS2_INODE_CACHE_INLINE), + OCFS2_CACHE_INFO_MAX_ARRAY); + mlog_bug_on_msg(!(ci->ci_flags & OCFS2_CACHE_FL_INLINE), "Inode %llu not marked as inline anymore!\n", (unsigned long long)oi->ip_blkno); - assert_spin_locked(&oi->ip_lock); + assert_spin_locked(ci->ci_lock); /* Be careful to initialize the tree members *first* because * once the ci_tree is used, the array is junk... */ - for(i = 0; i < OCFS2_INODE_MAX_CACHE_ARRAY; i++) + for (i = 0; i < OCFS2_CACHE_INFO_MAX_ARRAY; i++) tree[i]->c_block = ci->ci_cache.ci_array[i]; - oi->ip_flags &= ~OCFS2_INODE_CACHE_INLINE; + ci->ci_flags &= ~OCFS2_CACHE_FL_INLINE; ci->ci_cache.ci_tree = RB_ROOT; /* this will be set again by __ocfs2_insert_cache_tree */ ci->ci_num_cached = 0; - for(i = 0; i < OCFS2_INODE_MAX_CACHE_ARRAY; i++) { + for (i = 0; i < OCFS2_CACHE_INFO_MAX_ARRAY; i++) { __ocfs2_insert_cache_tree(ci, tree[i]); tree[i] = NULL; } mlog(0, "Expanded %llu to a tree cache: flags 0x%x, num = %u\n", - (unsigned long long)oi->ip_blkno, oi->ip_flags, ci->ci_num_cached); + (unsigned long long)oi->ip_blkno, ci->ci_flags, ci->ci_num_cached); } /* Slow path function - memory allocation is necessary. See the @@ -347,7 +349,7 @@ static void __ocfs2_set_buffer_uptodate(struct ocfs2_inode_info *oi, int i; struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; struct ocfs2_meta_cache_item *new = NULL; - struct ocfs2_meta_cache_item *tree[OCFS2_INODE_MAX_CACHE_ARRAY] = + struct ocfs2_meta_cache_item *tree[OCFS2_CACHE_INFO_MAX_ARRAY] = { NULL, }; mlog(0, "Inode %llu, block %llu, expand = %d\n", @@ -364,7 +366,7 @@ static void __ocfs2_set_buffer_uptodate(struct ocfs2_inode_info *oi, if (expand_tree) { /* Do *not* allocate an array here - the removal code * has no way of tracking that. */ - for(i = 0; i < OCFS2_INODE_MAX_CACHE_ARRAY; i++) { + for (i = 0; i < OCFS2_CACHE_INFO_MAX_ARRAY; i++) { tree[i] = kmem_cache_alloc(ocfs2_uptodate_cachep, GFP_NOFS); if (!tree[i]) { @@ -376,13 +378,13 @@ static void __ocfs2_set_buffer_uptodate(struct ocfs2_inode_info *oi, } } - spin_lock(&oi->ip_lock); + spin_lock(ci->ci_lock); if (ocfs2_insert_can_use_array(oi, ci)) { mlog(0, "Someone cleared the tree underneath us\n"); /* Ok, items were removed from the cache in between * locks. Detect this and revert back to the fast path */ ocfs2_append_cache_array(ci, block); - spin_unlock(&oi->ip_lock); + spin_unlock(ci->ci_lock); goto out_free; } @@ -390,7 +392,7 @@ static void __ocfs2_set_buffer_uptodate(struct ocfs2_inode_info *oi, ocfs2_expand_cache(oi, tree); __ocfs2_insert_cache_tree(ci, new); - spin_unlock(&oi->ip_lock); + spin_unlock(ci->ci_lock); new = NULL; out_free: @@ -400,14 +402,14 @@ out_free: /* If these were used, then ocfs2_expand_cache re-set them to * NULL for us. */ if (tree[0]) { - for(i = 0; i < OCFS2_INODE_MAX_CACHE_ARRAY; i++) + for (i = 0; i < OCFS2_CACHE_INFO_MAX_ARRAY; i++) if (tree[i]) kmem_cache_free(ocfs2_uptodate_cachep, tree[i]); } } -/* Item insertion is guarded by ip_io_mutex, so the insertion path takes +/* Item insertion is guarded by ci_io_mutex, so the insertion path takes * advantage of this by not rechecking for a duplicate insert during * the slow case. Additionally, if the cache needs to be bumped up to * a tree, the code will not recheck after acquiring the lock -- @@ -442,42 +444,43 @@ void ocfs2_set_buffer_uptodate(struct inode *inode, (unsigned long long)bh->b_blocknr); /* No need to recheck under spinlock - insertion is guarded by - * ip_io_mutex */ - spin_lock(&oi->ip_lock); + * ci_io_mutex */ + spin_lock(ci->ci_lock); if (ocfs2_insert_can_use_array(oi, ci)) { /* Fast case - it's an array and there's a free * spot. */ ocfs2_append_cache_array(ci, bh->b_blocknr); - spin_unlock(&oi->ip_lock); + spin_unlock(ci->ci_lock); return; } expand = 0; - if (oi->ip_flags & OCFS2_INODE_CACHE_INLINE) { + if (ci->ci_flags & OCFS2_CACHE_FL_INLINE) { /* We need to bump things up to a tree. */ expand = 1; } - spin_unlock(&oi->ip_lock); + spin_unlock(ci->ci_lock); __ocfs2_set_buffer_uptodate(oi, bh->b_blocknr, expand); } /* Called against a newly allocated buffer. Most likely nobody should * be able to read this sort of metadata while it's still being - * allocated, but this is careful to take ip_io_mutex anyway. */ + * allocated, but this is careful to take ci_io_mutex anyway. */ void ocfs2_set_new_buffer_uptodate(struct inode *inode, struct buffer_head *bh) { struct ocfs2_inode_info *oi = OCFS2_I(inode); + struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; /* This should definitely *not* exist in our cache */ BUG_ON(ocfs2_buffer_cached(oi, bh)); set_buffer_uptodate(bh); - mutex_lock(&oi->ip_io_mutex); + mutex_lock(ci->ci_io_mutex); ocfs2_set_buffer_uptodate(inode, bh); - mutex_unlock(&oi->ip_io_mutex); + mutex_unlock(ci->ci_io_mutex); } /* Requires ip_lock. */ @@ -487,7 +490,7 @@ static void ocfs2_remove_metadata_array(struct ocfs2_caching_info *ci, sector_t *array = ci->ci_cache.ci_array; int bytes; - BUG_ON(index < 0 || index >= OCFS2_INODE_MAX_CACHE_ARRAY); + BUG_ON(index < 0 || index >= OCFS2_CACHE_INFO_MAX_ARRAY); BUG_ON(index >= ci->ci_num_cached); BUG_ON(!ci->ci_num_cached); @@ -523,13 +526,13 @@ static void ocfs2_remove_block_from_cache(struct inode *inode, struct ocfs2_inode_info *oi = OCFS2_I(inode); struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; - spin_lock(&oi->ip_lock); + spin_lock(ci->ci_lock); mlog(0, "Inode %llu, remove %llu, items = %u, array = %u\n", (unsigned long long)oi->ip_blkno, (unsigned long long) block, ci->ci_num_cached, - oi->ip_flags & OCFS2_INODE_CACHE_INLINE); + ci->ci_flags & OCFS2_CACHE_FL_INLINE); - if (oi->ip_flags & OCFS2_INODE_CACHE_INLINE) { + if (ci->ci_flags & OCFS2_CACHE_FL_INLINE) { index = ocfs2_search_cache_array(ci, block); if (index != -1) ocfs2_remove_metadata_array(ci, index); @@ -538,7 +541,7 @@ static void ocfs2_remove_block_from_cache(struct inode *inode, if (item) ocfs2_remove_metadata_tree(ci, item); } - spin_unlock(&oi->ip_lock); + spin_unlock(ci->ci_lock); if (item) kmem_cache_free(ocfs2_uptodate_cachep, item); @@ -577,7 +580,7 @@ int __init init_ocfs2_uptodate_cache(void) return -ENOMEM; mlog(0, "%u inlined cache items per inode.\n", - OCFS2_INODE_MAX_CACHE_ARRAY); + OCFS2_CACHE_INFO_MAX_ARRAY); return 0; } diff --git a/fs/ocfs2/uptodate.h b/fs/ocfs2/uptodate.h index 531b4b3..bd749e1 100644 --- a/fs/ocfs2/uptodate.h +++ b/fs/ocfs2/uptodate.h @@ -29,7 +29,9 @@ int __init init_ocfs2_uptodate_cache(void); void exit_ocfs2_uptodate_cache(void); -void ocfs2_metadata_cache_init(struct inode *inode); +void ocfs2_metadata_cache_init(struct ocfs2_caching_info *ci, + spinlock_t *cache_lock, + struct mutex *io_mutex); void ocfs2_metadata_cache_purge(struct inode *inode); int ocfs2_buffer_uptodate(struct inode *inode, -- cgit v0.10.2 From 6e5a3d7538ad4e46a976862f593faf65750e37cc Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Tue, 10 Feb 2009 19:00:37 -0800 Subject: ocfs2: Change metadata caching locks to an operations structure. We don't really want to cart around too many new fields on the ocfs2_caching_info structure. So let's wrap all our access of the parent object in a set of operations. One pointer on caching_info, and more flexibility to boot. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/inode.c b/fs/ocfs2/inode.c index 8ec8044..36bb588 100644 --- a/fs/ocfs2/inode.c +++ b/fs/ocfs2/inode.c @@ -1395,3 +1395,52 @@ int ocfs2_read_inode_block(struct inode *inode, struct buffer_head **bh) { return ocfs2_read_inode_block_full(inode, bh, 0); } + +static struct ocfs2_inode_info *cache_info_to_inode(struct ocfs2_caching_info *ci) +{ + return container_of(ci, struct ocfs2_inode_info, ip_metadata_cache); +} + +static u64 ocfs2_inode_cache_owner(struct ocfs2_caching_info *ci) +{ + struct ocfs2_inode_info *oi = cache_info_to_inode(ci); + + return oi->ip_blkno; +} + +static void ocfs2_inode_cache_lock(struct ocfs2_caching_info *ci) +{ + struct ocfs2_inode_info *oi = cache_info_to_inode(ci); + + spin_lock(&oi->ip_lock); +} + +static void ocfs2_inode_cache_unlock(struct ocfs2_caching_info *ci) +{ + struct ocfs2_inode_info *oi = cache_info_to_inode(ci); + + spin_unlock(&oi->ip_lock); +} + +static void ocfs2_inode_cache_io_lock(struct ocfs2_caching_info *ci) +{ + struct ocfs2_inode_info *oi = cache_info_to_inode(ci); + + mutex_lock(&oi->ip_io_mutex); +} + +static void ocfs2_inode_cache_io_unlock(struct ocfs2_caching_info *ci) +{ + struct ocfs2_inode_info *oi = cache_info_to_inode(ci); + + mutex_unlock(&oi->ip_io_mutex); +} + +const struct ocfs2_caching_operations ocfs2_inode_caching_ops = { + .co_owner = ocfs2_inode_cache_owner, + .co_cache_lock = ocfs2_inode_cache_lock, + .co_cache_unlock = ocfs2_inode_cache_unlock, + .co_io_lock = ocfs2_inode_cache_io_lock, + .co_io_unlock = ocfs2_inode_cache_io_unlock, +}; + diff --git a/fs/ocfs2/inode.h b/fs/ocfs2/inode.h index 2f5e1aa..cd1caca 100644 --- a/fs/ocfs2/inode.h +++ b/fs/ocfs2/inode.h @@ -118,6 +118,7 @@ static inline struct ocfs2_inode_info *OCFS2_I(struct inode *inode) extern struct kmem_cache *ocfs2_inode_cache; extern const struct address_space_operations ocfs2_aops; +extern const struct ocfs2_caching_operations ocfs2_inode_caching_ops; void ocfs2_clear_inode(struct inode *inode); void ocfs2_delete_inode(struct inode *inode); diff --git a/fs/ocfs2/ocfs2.h b/fs/ocfs2/ocfs2.h index eef3bd0..6e54a49 100644 --- a/fs/ocfs2/ocfs2.h +++ b/fs/ocfs2/ocfs2.h @@ -68,14 +68,14 @@ enum ocfs2_caching_info_flags { OCFS2_CACHE_FL_INLINE = 1<<1, }; +struct ocfs2_caching_operations; struct ocfs2_caching_info { /* * The parent structure provides the locks, but because the - * parent structure can differ, struct ocfs2_caching_info needs - * its own pointers to them. + * parent structure can differ, it provides locking operations + * to struct ocfs2_caching_info. */ - spinlock_t *ci_lock; - struct mutex *ci_io_mutex; + const struct ocfs2_caching_operations *ci_ops; unsigned int ci_flags; unsigned int ci_num_cached; diff --git a/fs/ocfs2/super.c b/fs/ocfs2/super.c index 8f217f6..746ed5d 100644 --- a/fs/ocfs2/super.c +++ b/fs/ocfs2/super.c @@ -1683,8 +1683,8 @@ static void ocfs2_inode_init_once(void *data) ocfs2_lock_res_init_once(&oi->ip_inode_lockres); ocfs2_lock_res_init_once(&oi->ip_open_lockres); - ocfs2_metadata_cache_init(&oi->ip_metadata_cache, &oi->ip_lock, - &oi->ip_io_mutex); + ocfs2_metadata_cache_init(&oi->ip_metadata_cache, + &ocfs2_inode_caching_ops); inode_init_once(&oi->vfs_inode); } diff --git a/fs/ocfs2/uptodate.c b/fs/ocfs2/uptodate.c index 8dbc457..226d042 100644 --- a/fs/ocfs2/uptodate.c +++ b/fs/ocfs2/uptodate.c @@ -75,12 +75,48 @@ struct ocfs2_meta_cache_item { static struct kmem_cache *ocfs2_uptodate_cachep = NULL; +static u64 ocfs2_metadata_cache_owner(struct ocfs2_caching_info *ci) +{ + BUG_ON(!ci || !ci->ci_ops); + + return ci->ci_ops->co_owner(ci); +} + +static void ocfs2_metadata_cache_lock(struct ocfs2_caching_info *ci) +{ + BUG_ON(!ci || !ci->ci_ops); + + ci->ci_ops->co_cache_lock(ci); +} + +static void ocfs2_metadata_cache_unlock(struct ocfs2_caching_info *ci) +{ + BUG_ON(!ci || !ci->ci_ops); + + ci->ci_ops->co_cache_unlock(ci); +} + +static void ocfs2_metadata_cache_io_lock(struct ocfs2_caching_info *ci) +{ + BUG_ON(!ci || !ci->ci_ops); + + ci->ci_ops->co_io_lock(ci); +} + +static void ocfs2_metadata_cache_io_unlock(struct ocfs2_caching_info *ci) +{ + BUG_ON(!ci || !ci->ci_ops); + + ci->ci_ops->co_io_unlock(ci); +} + + void ocfs2_metadata_cache_init(struct ocfs2_caching_info *ci, - spinlock_t *cache_lock, - struct mutex *io_mutex) + const struct ocfs2_caching_operations *ops) { - ci->ci_lock = cache_lock; - ci->ci_io_mutex = io_mutex; + BUG_ON(!ops); + + ci->ci_ops = ops; ci->ci_flags |= OCFS2_CACHE_FL_INLINE; ci->ci_num_cached = 0; } @@ -120,12 +156,15 @@ void ocfs2_metadata_cache_purge(struct inode *inode) struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; struct rb_root root = RB_ROOT; - spin_lock(ci->ci_lock); + BUG_ON(!ci || !ci->ci_ops); + + ocfs2_metadata_cache_lock(ci); tree = !(ci->ci_flags & OCFS2_CACHE_FL_INLINE); to_purge = ci->ci_num_cached; - mlog(0, "Purge %u %s items from Inode %llu\n", to_purge, - tree ? "array" : "tree", (unsigned long long)oi->ip_blkno); + mlog(0, "Purge %u %s items from Owner %llu\n", to_purge, + tree ? "array" : "tree", + (unsigned long long)ocfs2_metadata_cache_owner(ci)); /* If we're a tree, save off the root so that we can safely * initialize the cache. We do the work to free tree members @@ -133,16 +172,17 @@ void ocfs2_metadata_cache_purge(struct inode *inode) if (tree) root = ci->ci_cache.ci_tree; - ocfs2_metadata_cache_init(ci, ci->ci_lock, ci->ci_io_mutex); - spin_unlock(ci->ci_lock); + ocfs2_metadata_cache_init(ci, ci->ci_ops); + ocfs2_metadata_cache_unlock(ci); purged = ocfs2_purge_copied_metadata_tree(&root); /* If possible, track the number wiped so that we can more * easily detect counting errors. Unfortunately, this is only * meaningful for trees. */ if (tree && purged != to_purge) - mlog(ML_ERROR, "Inode %llu, count = %u, purged = %u\n", - (unsigned long long)oi->ip_blkno, to_purge, purged); + mlog(ML_ERROR, "Owner %llu, count = %u, purged = %u\n", + (unsigned long long)ocfs2_metadata_cache_owner(ci), + to_purge, purged); } /* Returns the index in the cache array, -1 if not found. @@ -190,10 +230,10 @@ static int ocfs2_buffer_cached(struct ocfs2_inode_info *oi, struct ocfs2_meta_cache_item *item = NULL; struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; - spin_lock(ci->ci_lock); + ocfs2_metadata_cache_lock(ci); - mlog(0, "Inode %llu, query block %llu (inline = %u)\n", - (unsigned long long)oi->ip_blkno, + mlog(0, "Owner %llu, query block %llu (inline = %u)\n", + (unsigned long long)ocfs2_metadata_cache_owner(ci), (unsigned long long) bh->b_blocknr, !!(ci->ci_flags & OCFS2_CACHE_FL_INLINE)); @@ -204,7 +244,7 @@ static int ocfs2_buffer_cached(struct ocfs2_inode_info *oi, item = ocfs2_search_cache_tree(&oi->ip_metadata_cache, bh->b_blocknr); - spin_unlock(ci->ci_lock); + ocfs2_metadata_cache_unlock(ci); mlog(0, "index = %d, item = %p\n", index, item); @@ -294,18 +334,19 @@ static void __ocfs2_insert_cache_tree(struct ocfs2_caching_info *ci, ci->ci_num_cached++; } +/* co_cache_lock() must be held */ static inline int ocfs2_insert_can_use_array(struct ocfs2_inode_info *oi, struct ocfs2_caching_info *ci) { - assert_spin_locked(ci->ci_lock); - return (ci->ci_flags & OCFS2_CACHE_FL_INLINE) && (ci->ci_num_cached < OCFS2_CACHE_INFO_MAX_ARRAY); } /* tree should be exactly OCFS2_CACHE_INFO_MAX_ARRAY wide. NULL the * pointers in tree after we use them - this allows caller to detect - * when to free in case of error. */ + * when to free in case of error. + * + * The co_cache_lock() must be held. */ static void ocfs2_expand_cache(struct ocfs2_inode_info *oi, struct ocfs2_meta_cache_item **tree) { @@ -313,13 +354,12 @@ static void ocfs2_expand_cache(struct ocfs2_inode_info *oi, struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; mlog_bug_on_msg(ci->ci_num_cached != OCFS2_CACHE_INFO_MAX_ARRAY, - "Inode %llu, num cached = %u, should be %u\n", - (unsigned long long)oi->ip_blkno, ci->ci_num_cached, - OCFS2_CACHE_INFO_MAX_ARRAY); + "Owner %llu, num cached = %u, should be %u\n", + (unsigned long long)ocfs2_metadata_cache_owner(ci), + ci->ci_num_cached, OCFS2_CACHE_INFO_MAX_ARRAY); mlog_bug_on_msg(!(ci->ci_flags & OCFS2_CACHE_FL_INLINE), - "Inode %llu not marked as inline anymore!\n", - (unsigned long long)oi->ip_blkno); - assert_spin_locked(ci->ci_lock); + "Owner %llu not marked as inline anymore!\n", + (unsigned long long)ocfs2_metadata_cache_owner(ci)); /* Be careful to initialize the tree members *first* because * once the ci_tree is used, the array is junk... */ @@ -337,7 +377,8 @@ static void ocfs2_expand_cache(struct ocfs2_inode_info *oi, } mlog(0, "Expanded %llu to a tree cache: flags 0x%x, num = %u\n", - (unsigned long long)oi->ip_blkno, ci->ci_flags, ci->ci_num_cached); + (unsigned long long)ocfs2_metadata_cache_owner(ci), + ci->ci_flags, ci->ci_num_cached); } /* Slow path function - memory allocation is necessary. See the @@ -352,8 +393,8 @@ static void __ocfs2_set_buffer_uptodate(struct ocfs2_inode_info *oi, struct ocfs2_meta_cache_item *tree[OCFS2_CACHE_INFO_MAX_ARRAY] = { NULL, }; - mlog(0, "Inode %llu, block %llu, expand = %d\n", - (unsigned long long)oi->ip_blkno, + mlog(0, "Owner %llu, block %llu, expand = %d\n", + (unsigned long long)ocfs2_metadata_cache_owner(ci), (unsigned long long)block, expand_tree); new = kmem_cache_alloc(ocfs2_uptodate_cachep, GFP_NOFS); @@ -378,13 +419,13 @@ static void __ocfs2_set_buffer_uptodate(struct ocfs2_inode_info *oi, } } - spin_lock(ci->ci_lock); + ocfs2_metadata_cache_lock(ci); if (ocfs2_insert_can_use_array(oi, ci)) { mlog(0, "Someone cleared the tree underneath us\n"); /* Ok, items were removed from the cache in between * locks. Detect this and revert back to the fast path */ ocfs2_append_cache_array(ci, block); - spin_unlock(ci->ci_lock); + ocfs2_metadata_cache_unlock(ci); goto out_free; } @@ -392,7 +433,7 @@ static void __ocfs2_set_buffer_uptodate(struct ocfs2_inode_info *oi, ocfs2_expand_cache(oi, tree); __ocfs2_insert_cache_tree(ci, new); - spin_unlock(ci->ci_lock); + ocfs2_metadata_cache_unlock(ci); new = NULL; out_free: @@ -409,7 +450,7 @@ out_free: } } -/* Item insertion is guarded by ci_io_mutex, so the insertion path takes +/* Item insertion is guarded by co_io_lock(), so the insertion path takes * advantage of this by not rechecking for a duplicate insert during * the slow case. Additionally, if the cache needs to be bumped up to * a tree, the code will not recheck after acquiring the lock -- @@ -439,18 +480,18 @@ void ocfs2_set_buffer_uptodate(struct inode *inode, if (ocfs2_buffer_cached(oi, bh)) return; - mlog(0, "Inode %llu, inserting block %llu\n", - (unsigned long long)oi->ip_blkno, + mlog(0, "Owner %llu, inserting block %llu\n", + (unsigned long long)ocfs2_metadata_cache_owner(ci), (unsigned long long)bh->b_blocknr); /* No need to recheck under spinlock - insertion is guarded by - * ci_io_mutex */ - spin_lock(ci->ci_lock); + * co_io_lock() */ + ocfs2_metadata_cache_lock(ci); if (ocfs2_insert_can_use_array(oi, ci)) { /* Fast case - it's an array and there's a free * spot. */ ocfs2_append_cache_array(ci, bh->b_blocknr); - spin_unlock(ci->ci_lock); + ocfs2_metadata_cache_unlock(ci); return; } @@ -459,14 +500,14 @@ void ocfs2_set_buffer_uptodate(struct inode *inode, /* We need to bump things up to a tree. */ expand = 1; } - spin_unlock(ci->ci_lock); + ocfs2_metadata_cache_unlock(ci); __ocfs2_set_buffer_uptodate(oi, bh->b_blocknr, expand); } /* Called against a newly allocated buffer. Most likely nobody should * be able to read this sort of metadata while it's still being - * allocated, but this is careful to take ci_io_mutex anyway. */ + * allocated, but this is careful to take co_io_lock() anyway. */ void ocfs2_set_new_buffer_uptodate(struct inode *inode, struct buffer_head *bh) { @@ -478,9 +519,9 @@ void ocfs2_set_new_buffer_uptodate(struct inode *inode, set_buffer_uptodate(bh); - mutex_lock(ci->ci_io_mutex); + ocfs2_metadata_cache_io_lock(ci); ocfs2_set_buffer_uptodate(inode, bh); - mutex_unlock(ci->ci_io_mutex); + ocfs2_metadata_cache_io_unlock(ci); } /* Requires ip_lock. */ @@ -526,9 +567,9 @@ static void ocfs2_remove_block_from_cache(struct inode *inode, struct ocfs2_inode_info *oi = OCFS2_I(inode); struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; - spin_lock(ci->ci_lock); - mlog(0, "Inode %llu, remove %llu, items = %u, array = %u\n", - (unsigned long long)oi->ip_blkno, + ocfs2_metadata_cache_lock(ci); + mlog(0, "Owner %llu, remove %llu, items = %u, array = %u\n", + (unsigned long long)ocfs2_metadata_cache_owner(ci), (unsigned long long) block, ci->ci_num_cached, ci->ci_flags & OCFS2_CACHE_FL_INLINE); @@ -541,7 +582,7 @@ static void ocfs2_remove_block_from_cache(struct inode *inode, if (item) ocfs2_remove_metadata_tree(ci, item); } - spin_unlock(ci->ci_lock); + ocfs2_metadata_cache_unlock(ci); if (item) kmem_cache_free(ocfs2_uptodate_cachep, item); diff --git a/fs/ocfs2/uptodate.h b/fs/ocfs2/uptodate.h index bd749e1..3b33eb8 100644 --- a/fs/ocfs2/uptodate.h +++ b/fs/ocfs2/uptodate.h @@ -26,12 +26,38 @@ #ifndef OCFS2_UPTODATE_H #define OCFS2_UPTODATE_H +/* + * The caching code relies on locking provided by the user of + * struct ocfs2_caching_info. These operations connect that up. + */ +struct ocfs2_caching_operations { + /* + * A u64 representing the owning structure. Usually this + * is the block number (i_blkno or whatnot). This is used so + * that caching log messages can identify the owning structure. + */ + u64 (*co_owner)(struct ocfs2_caching_info *ci); + + /* + * Lock and unlock the caching data. These will not sleep, and + * should probably be spinlocks. + */ + void (*co_cache_lock)(struct ocfs2_caching_info *ci); + void (*co_cache_unlock)(struct ocfs2_caching_info *ci); + + /* + * Lock and unlock for disk I/O. These will sleep, and should + * be mutexes. + */ + void (*co_io_lock)(struct ocfs2_caching_info *ci); + void (*co_io_unlock)(struct ocfs2_caching_info *ci); +}; + int __init init_ocfs2_uptodate_cache(void); void exit_ocfs2_uptodate_cache(void); void ocfs2_metadata_cache_init(struct ocfs2_caching_info *ci, - spinlock_t *cache_lock, - struct mutex *io_mutex); + const struct ocfs2_caching_operations *ops); void ocfs2_metadata_cache_purge(struct inode *inode); int ocfs2_buffer_uptodate(struct inode *inode, -- cgit v0.10.2 From 8cb471e8f82506937fe5e2e9fb0bf90f6b1f1170 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Tue, 10 Feb 2009 20:00:41 -0800 Subject: ocfs2: Take the inode out of the metadata read/write paths. We are really passing the inode into the ocfs2_read/write_blocks() functions to get at the metadata cache. This commit passes the cache directly into the metadata block functions, divorcing them from the inode. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index ab513dd..d5dffcf 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -859,7 +859,7 @@ int ocfs2_read_extent_block(struct inode *inode, u64 eb_blkno, int rc; struct buffer_head *tmp = *bh; - rc = ocfs2_read_block(inode, eb_blkno, &tmp, + rc = ocfs2_read_block(INODE_CACHE(inode), eb_blkno, &tmp, ocfs2_validate_extent_block); /* If ocfs2_read_block() got us a new bh, pass it up. */ @@ -949,7 +949,8 @@ static int ocfs2_create_new_meta_bhs(struct ocfs2_super *osb, mlog_errno(status); goto bail; } - ocfs2_set_new_buffer_uptodate(inode, bhs[i]); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(inode), + bhs[i]); status = ocfs2_journal_access_eb(handle, inode, bhs[i], OCFS2_JOURNAL_ACCESS_CREATE); @@ -2559,7 +2560,7 @@ static void ocfs2_unlink_path(struct inode *inode, handle_t *handle, le16_to_cpu(el->l_next_free_rec)); ocfs2_journal_dirty(handle, bh); - ocfs2_remove_from_cache(inode, bh); + ocfs2_remove_from_cache(INODE_CACHE(inode), bh); continue; } @@ -2572,7 +2573,7 @@ static void ocfs2_unlink_path(struct inode *inode, handle_t *handle, if (ret) mlog_errno(ret); - ocfs2_remove_from_cache(inode, bh); + ocfs2_remove_from_cache(INODE_CACHE(inode), bh); } } @@ -6010,7 +6011,7 @@ int ocfs2_begin_truncate_log_recovery(struct ocfs2_super *osb, tl->tl_used = 0; ocfs2_compute_meta_ecc(osb->sb, tl_bh->b_data, &di->i_check); - status = ocfs2_write_block(osb, tl_bh, tl_inode); + status = ocfs2_write_block(osb, tl_bh, INODE_CACHE(tl_inode)); if (status < 0) { mlog_errno(status); goto bail; @@ -6719,7 +6720,7 @@ delete: mlog(0, "deleting this extent block.\n"); - ocfs2_remove_from_cache(inode, bh); + ocfs2_remove_from_cache(INODE_CACHE(inode), bh); BUG_ON(ocfs2_rec_clusters(el, &el->l_recs[0])); BUG_ON(le32_to_cpu(el->l_recs[0].e_cpos)); diff --git a/fs/ocfs2/buffer_head_io.c b/fs/ocfs2/buffer_head_io.c index 15c8e6d..d43d34a 100644 --- a/fs/ocfs2/buffer_head_io.c +++ b/fs/ocfs2/buffer_head_io.c @@ -52,12 +52,12 @@ enum ocfs2_state_bits { BUFFER_FNS(NeedsValidate, needs_validate); int ocfs2_write_block(struct ocfs2_super *osb, struct buffer_head *bh, - struct inode *inode) + struct ocfs2_caching_info *ci) { int ret = 0; - mlog_entry("(bh->b_blocknr = %llu, inode=%p)\n", - (unsigned long long)bh->b_blocknr, inode); + mlog_entry("(bh->b_blocknr = %llu, ci=%p)\n", + (unsigned long long)bh->b_blocknr, ci); BUG_ON(bh->b_blocknr < OCFS2_SUPER_BLOCK_BLKNO); BUG_ON(buffer_jbd(bh)); @@ -70,7 +70,7 @@ int ocfs2_write_block(struct ocfs2_super *osb, struct buffer_head *bh, goto out; } - mutex_lock(&OCFS2_I(inode)->ip_io_mutex); + ocfs2_metadata_cache_io_lock(ci); lock_buffer(bh); set_buffer_uptodate(bh); @@ -85,7 +85,7 @@ int ocfs2_write_block(struct ocfs2_super *osb, struct buffer_head *bh, wait_on_buffer(bh); if (buffer_uptodate(bh)) { - ocfs2_set_buffer_uptodate(inode, bh); + ocfs2_set_buffer_uptodate(ci, bh); } else { /* We don't need to remove the clustered uptodate * information for this bh as it's not marked locally @@ -94,7 +94,7 @@ int ocfs2_write_block(struct ocfs2_super *osb, struct buffer_head *bh, put_bh(bh); } - mutex_unlock(&OCFS2_I(inode)->ip_io_mutex); + ocfs2_metadata_cache_io_unlock(ci); out: mlog_exit(ret); return ret; @@ -177,7 +177,7 @@ bail: return status; } -int ocfs2_read_blocks(struct inode *inode, u64 block, int nr, +int ocfs2_read_blocks(struct ocfs2_caching_info *ci, u64 block, int nr, struct buffer_head *bhs[], int flags, int (*validate)(struct super_block *sb, struct buffer_head *bh)) @@ -185,11 +185,12 @@ int ocfs2_read_blocks(struct inode *inode, u64 block, int nr, int status = 0; int i, ignore_cache = 0; struct buffer_head *bh; + struct super_block *sb = ocfs2_metadata_cache_get_super(ci); - mlog_entry("(inode=%p, block=(%llu), nr=(%d), flags=%d)\n", - inode, (unsigned long long)block, nr, flags); + mlog_entry("(ci=%p, block=(%llu), nr=(%d), flags=%d)\n", + ci, (unsigned long long)block, nr, flags); - BUG_ON(!inode); + BUG_ON(!ci); BUG_ON((flags & OCFS2_BH_READAHEAD) && (flags & OCFS2_BH_IGNORE_CACHE)); @@ -212,12 +213,12 @@ int ocfs2_read_blocks(struct inode *inode, u64 block, int nr, goto bail; } - mutex_lock(&OCFS2_I(inode)->ip_io_mutex); + ocfs2_metadata_cache_io_lock(ci); for (i = 0 ; i < nr ; i++) { if (bhs[i] == NULL) { - bhs[i] = sb_getblk(inode->i_sb, block++); + bhs[i] = sb_getblk(sb, block++); if (bhs[i] == NULL) { - mutex_unlock(&OCFS2_I(inode)->ip_io_mutex); + ocfs2_metadata_cache_io_unlock(ci); status = -EIO; mlog_errno(status); goto bail; @@ -250,11 +251,11 @@ int ocfs2_read_blocks(struct inode *inode, u64 block, int nr, * before our is-it-in-flight check. */ - if (!ignore_cache && !ocfs2_buffer_uptodate(inode, bh)) { + if (!ignore_cache && !ocfs2_buffer_uptodate(ci, bh)) { mlog(ML_UPTODATE, - "bh (%llu), inode %llu not uptodate\n", + "bh (%llu), owner %llu not uptodate\n", (unsigned long long)bh->b_blocknr, - (unsigned long long)OCFS2_I(inode)->ip_blkno); + (unsigned long long)ocfs2_metadata_cache_owner(ci)); /* We're using ignore_cache here to say * "go to disk" */ ignore_cache = 1; @@ -283,7 +284,7 @@ int ocfs2_read_blocks(struct inode *inode, u64 block, int nr, * previously submitted request than we are * done here. */ if ((flags & OCFS2_BH_READAHEAD) - && ocfs2_buffer_read_ahead(inode, bh)) + && ocfs2_buffer_read_ahead(ci, bh)) continue; lock_buffer(bh); @@ -305,7 +306,7 @@ int ocfs2_read_blocks(struct inode *inode, u64 block, int nr, * buffer lock. */ if (!(flags & OCFS2_BH_IGNORE_CACHE) && !(flags & OCFS2_BH_READAHEAD) - && ocfs2_buffer_uptodate(inode, bh)) { + && ocfs2_buffer_uptodate(ci, bh)) { unlock_buffer(bh); continue; } @@ -327,7 +328,7 @@ int ocfs2_read_blocks(struct inode *inode, u64 block, int nr, if (!(flags & OCFS2_BH_READAHEAD)) { /* We know this can't have changed as we hold the - * inode sem. Avoid doing any work on the bh if the + * owner sem. Avoid doing any work on the bh if the * journal has it. */ if (!buffer_jbd(bh)) wait_on_buffer(bh); @@ -351,7 +352,7 @@ int ocfs2_read_blocks(struct inode *inode, u64 block, int nr, * that better not have changed */ BUG_ON(buffer_jbd(bh)); clear_buffer_needs_validate(bh); - status = validate(inode->i_sb, bh); + status = validate(sb, bh); if (status) { put_bh(bh); bhs[i] = NULL; @@ -363,9 +364,9 @@ int ocfs2_read_blocks(struct inode *inode, u64 block, int nr, /* Always set the buffer in the cache, even if it was * a forced read, or read-ahead which hasn't yet * completed. */ - ocfs2_set_buffer_uptodate(inode, bh); + ocfs2_set_buffer_uptodate(ci, bh); } - mutex_unlock(&OCFS2_I(inode)->ip_io_mutex); + ocfs2_metadata_cache_io_unlock(ci); mlog(ML_BH_IO, "block=(%llu), nr=(%d), cached=%s, flags=0x%x\n", (unsigned long long)block, nr, @@ -399,7 +400,7 @@ static void ocfs2_check_super_or_backup(struct super_block *sb, /* * Write super block and backups doesn't need to collaborate with journal, - * so we don't need to lock ip_io_mutex and inode doesn't need to bea passed + * so we don't need to lock ip_io_mutex and ci doesn't need to bea passed * into this function. */ int ocfs2_write_super_or_backup(struct ocfs2_super *osb, diff --git a/fs/ocfs2/buffer_head_io.h b/fs/ocfs2/buffer_head_io.h index c75d682..b97bcc6 100644 --- a/fs/ocfs2/buffer_head_io.h +++ b/fs/ocfs2/buffer_head_io.h @@ -33,7 +33,7 @@ void ocfs2_end_buffer_io_sync(struct buffer_head *bh, int ocfs2_write_block(struct ocfs2_super *osb, struct buffer_head *bh, - struct inode *inode); + struct ocfs2_caching_info *ci); int ocfs2_read_blocks_sync(struct ocfs2_super *osb, u64 block, unsigned int nr, struct buffer_head *bhs[]); @@ -44,7 +44,7 @@ int ocfs2_read_blocks_sync(struct ocfs2_super *osb, u64 block, * be set even for a READAHEAD call, as it marks the buffer for later * validation. */ -int ocfs2_read_blocks(struct inode *inode, u64 block, int nr, +int ocfs2_read_blocks(struct ocfs2_caching_info *ci, u64 block, int nr, struct buffer_head *bhs[], int flags, int (*validate)(struct super_block *sb, struct buffer_head *bh)); @@ -55,7 +55,7 @@ int ocfs2_write_super_or_backup(struct ocfs2_super *osb, #define OCFS2_BH_IGNORE_CACHE 1 #define OCFS2_BH_READAHEAD 8 -static inline int ocfs2_read_block(struct inode *inode, u64 off, +static inline int ocfs2_read_block(struct ocfs2_caching_info *ci, u64 off, struct buffer_head **bh, int (*validate)(struct super_block *sb, struct buffer_head *bh)) @@ -68,7 +68,7 @@ static inline int ocfs2_read_block(struct inode *inode, u64 off, goto bail; } - status = ocfs2_read_blocks(inode, off, 1, bh, 0, validate); + status = ocfs2_read_blocks(ci, off, 1, bh, 0, validate); bail: return status; diff --git a/fs/ocfs2/dir.c b/fs/ocfs2/dir.c index b358f3b..273fb76 100644 --- a/fs/ocfs2/dir.c +++ b/fs/ocfs2/dir.c @@ -564,7 +564,8 @@ static int ocfs2_read_dir_block_direct(struct inode *dir, u64 phys, int ret; struct buffer_head *tmp = *bh; - ret = ocfs2_read_block(dir, phys, &tmp, ocfs2_validate_dir_block); + ret = ocfs2_read_block(INODE_CACHE(dir), phys, &tmp, + ocfs2_validate_dir_block); if (ret) { mlog_errno(ret); goto out; @@ -622,7 +623,8 @@ static int ocfs2_read_dx_root(struct inode *dir, struct ocfs2_dinode *di, u64 blkno = le64_to_cpu(di->i_dx_root); struct buffer_head *tmp = *dx_root_bh; - ret = ocfs2_read_block(dir, blkno, &tmp, ocfs2_validate_dx_root); + ret = ocfs2_read_block(INODE_CACHE(dir), blkno, &tmp, + ocfs2_validate_dx_root); /* If ocfs2_read_block() got us a new bh, pass it up. */ if (!ret && !*dx_root_bh) @@ -662,7 +664,8 @@ static int ocfs2_read_dx_leaf(struct inode *dir, u64 blkno, int ret; struct buffer_head *tmp = *dx_leaf_bh; - ret = ocfs2_read_block(dir, blkno, &tmp, ocfs2_validate_dx_leaf); + ret = ocfs2_read_block(INODE_CACHE(dir), blkno, &tmp, + ocfs2_validate_dx_leaf); /* If ocfs2_read_block() got us a new bh, pass it up. */ if (!ret && !*dx_leaf_bh) @@ -680,7 +683,7 @@ static int ocfs2_read_dx_leaves(struct inode *dir, u64 start, int num, { int ret; - ret = ocfs2_read_blocks(dir, start, num, dx_leaf_bhs, 0, + ret = ocfs2_read_blocks(INODE_CACHE(dir), start, num, dx_leaf_bhs, 0, ocfs2_validate_dx_leaf); if (ret) mlog_errno(ret); @@ -2332,7 +2335,7 @@ static int ocfs2_fill_new_dir_el(struct ocfs2_super *osb, goto bail; } - ocfs2_set_new_buffer_uptodate(inode, new_bh); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(inode), new_bh); status = ocfs2_journal_access_db(handle, inode, new_bh, OCFS2_JOURNAL_ACCESS_CREATE); @@ -2418,7 +2421,7 @@ static int ocfs2_dx_dir_attach_index(struct ocfs2_super *osb, ret = -EIO; goto out; } - ocfs2_set_new_buffer_uptodate(dir, dx_root_bh); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(dir), dx_root_bh); ret = ocfs2_journal_access_dr(handle, dir, dx_root_bh, OCFS2_JOURNAL_ACCESS_CREATE); @@ -2495,7 +2498,7 @@ static int ocfs2_dx_dir_format_cluster(struct ocfs2_super *osb, } dx_leaves[i] = bh; - ocfs2_set_new_buffer_uptodate(dir, bh); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(dir), bh); ret = ocfs2_journal_access_dl(handle, dir, bh, OCFS2_JOURNAL_ACCESS_CREATE); @@ -3005,7 +3008,7 @@ static int ocfs2_expand_inline_dir(struct inode *dir, struct buffer_head *di_bh, goto out_commit; } - ocfs2_set_new_buffer_uptodate(dir, dirdata_bh); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(dir), dirdata_bh); ret = ocfs2_journal_access_db(handle, dir, dirdata_bh, OCFS2_JOURNAL_ACCESS_CREATE); @@ -3387,7 +3390,7 @@ do_extend: goto bail; } - ocfs2_set_new_buffer_uptodate(dir, new_bh); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(dir), new_bh); status = ocfs2_journal_access_db(handle, dir, new_bh, OCFS2_JOURNAL_ACCESS_CREATE); @@ -4565,7 +4568,7 @@ remove_index: goto out; } - ocfs2_remove_from_cache(dir, dx_root_bh); + ocfs2_remove_from_cache(INODE_CACHE(dir), dx_root_bh); out: ocfs2_schedule_truncate_log_flush(osb, 1); ocfs2_run_deallocs(osb, &dealloc); diff --git a/fs/ocfs2/dlmglue.c b/fs/ocfs2/dlmglue.c index 110bb57..fe15cee 100644 --- a/fs/ocfs2/dlmglue.c +++ b/fs/ocfs2/dlmglue.c @@ -2127,7 +2127,7 @@ static int ocfs2_inode_lock_update(struct inode *inode, /* This will discard any caching information we might have had * for the inode metadata. */ - ocfs2_metadata_cache_purge(inode); + ocfs2_metadata_cache_purge(INODE_CACHE(inode)); ocfs2_extent_map_trunc(inode, 0); diff --git a/fs/ocfs2/extent_map.c b/fs/ocfs2/extent_map.c index f2bb1a0..dbd8a16 100644 --- a/fs/ocfs2/extent_map.c +++ b/fs/ocfs2/extent_map.c @@ -862,8 +862,8 @@ int ocfs2_read_virt_blocks(struct inode *inode, u64 v_block, int nr, BUG_ON(bhs[done + i]->b_blocknr != (p_block + i)); } - rc = ocfs2_read_blocks(inode, p_block, count, bhs + done, - flags, validate); + rc = ocfs2_read_blocks(INODE_CACHE(inode), p_block, count, + bhs + done, flags, validate); if (rc) { mlog_errno(rc); break; diff --git a/fs/ocfs2/inode.c b/fs/ocfs2/inode.c index 36bb588..1c9713c 100644 --- a/fs/ocfs2/inode.c +++ b/fs/ocfs2/inode.c @@ -662,7 +662,7 @@ static int ocfs2_remove_inode(struct inode *inode, goto bail_commit; } - ocfs2_remove_from_cache(inode, di_bh); + ocfs2_remove_from_cache(INODE_CACHE(inode), di_bh); vfs_dq_free_inode(inode); status = ocfs2_free_dinode(handle, inode_alloc_inode, @@ -1112,14 +1112,14 @@ void ocfs2_clear_inode(struct inode *inode) ocfs2_lock_res_free(&oi->ip_inode_lockres); ocfs2_lock_res_free(&oi->ip_open_lockres); - ocfs2_metadata_cache_purge(inode); + ocfs2_metadata_cache_purge(INODE_CACHE(inode)); - mlog_bug_on_msg(oi->ip_metadata_cache.ci_num_cached, + mlog_bug_on_msg(INODE_CACHE(inode)->ci_num_cached, "Clear inode of %llu, inode has %u cache items\n", - (unsigned long long)oi->ip_blkno, oi->ip_metadata_cache.ci_num_cached); + (unsigned long long)oi->ip_blkno, + INODE_CACHE(inode)->ci_num_cached); - mlog_bug_on_msg(!(oi->ip_metadata_cache.ci_flags & - OCFS2_CACHE_FL_INLINE), + mlog_bug_on_msg(!(INODE_CACHE(inode)->ci_flags & OCFS2_CACHE_FL_INLINE), "Clear inode of %llu, inode has a bad flag\n", (unsigned long long)oi->ip_blkno); @@ -1381,8 +1381,8 @@ int ocfs2_read_inode_block_full(struct inode *inode, struct buffer_head **bh, int rc; struct buffer_head *tmp = *bh; - rc = ocfs2_read_blocks(inode, OCFS2_I(inode)->ip_blkno, 1, &tmp, - flags, ocfs2_validate_inode_block); + rc = ocfs2_read_blocks(INODE_CACHE(inode), OCFS2_I(inode)->ip_blkno, + 1, &tmp, flags, ocfs2_validate_inode_block); /* If ocfs2_read_blocks() got us a new bh, pass it up. */ if (!rc && !*bh) @@ -1408,6 +1408,13 @@ static u64 ocfs2_inode_cache_owner(struct ocfs2_caching_info *ci) return oi->ip_blkno; } +static struct super_block *ocfs2_inode_cache_get_super(struct ocfs2_caching_info *ci) +{ + struct ocfs2_inode_info *oi = cache_info_to_inode(ci); + + return oi->vfs_inode.i_sb; +} + static void ocfs2_inode_cache_lock(struct ocfs2_caching_info *ci) { struct ocfs2_inode_info *oi = cache_info_to_inode(ci); @@ -1438,6 +1445,7 @@ static void ocfs2_inode_cache_io_unlock(struct ocfs2_caching_info *ci) const struct ocfs2_caching_operations ocfs2_inode_caching_ops = { .co_owner = ocfs2_inode_cache_owner, + .co_get_super = ocfs2_inode_cache_get_super, .co_cache_lock = ocfs2_inode_cache_lock, .co_cache_unlock = ocfs2_inode_cache_unlock, .co_io_lock = ocfs2_inode_cache_io_lock, diff --git a/fs/ocfs2/inode.h b/fs/ocfs2/inode.h index cd1caca..b0a71b2 100644 --- a/fs/ocfs2/inode.h +++ b/fs/ocfs2/inode.h @@ -120,6 +120,11 @@ extern struct kmem_cache *ocfs2_inode_cache; extern const struct address_space_operations ocfs2_aops; extern const struct ocfs2_caching_operations ocfs2_inode_caching_ops; +static inline struct ocfs2_caching_info *INODE_CACHE(struct inode *inode) +{ + return &OCFS2_I(inode)->ip_metadata_cache; +} + void ocfs2_clear_inode(struct inode *inode); void ocfs2_delete_inode(struct inode *inode); void ocfs2_drop_inode(struct inode *inode); diff --git a/fs/ocfs2/journal.c b/fs/ocfs2/journal.c index c48b93a..ddf08d3 100644 --- a/fs/ocfs2/journal.c +++ b/fs/ocfs2/journal.c @@ -898,7 +898,7 @@ static int ocfs2_journal_toggle_dirty(struct ocfs2_super *osb, ocfs2_bump_recovery_generation(fe); ocfs2_compute_meta_ecc(osb->sb, bh->b_data, &fe->i_check); - status = ocfs2_write_block(osb, bh, journal->j_inode); + status = ocfs2_write_block(osb, bh, INODE_CACHE(journal->j_inode)); if (status < 0) mlog_errno(status); @@ -1642,7 +1642,7 @@ static int ocfs2_replay_journal(struct ocfs2_super *osb, ocfs2_get_recovery_generation(fe); ocfs2_compute_meta_ecc(osb->sb, bh->b_data, &fe->i_check); - status = ocfs2_write_block(osb, bh, inode); + status = ocfs2_write_block(osb, bh, INODE_CACHE(inode)); if (status < 0) mlog_errno(status); diff --git a/fs/ocfs2/localalloc.c b/fs/ocfs2/localalloc.c index bac7e6a..da5dd6a 100644 --- a/fs/ocfs2/localalloc.c +++ b/fs/ocfs2/localalloc.c @@ -392,7 +392,7 @@ int ocfs2_begin_local_alloc_recovery(struct ocfs2_super *osb, ocfs2_clear_local_alloc(alloc); ocfs2_compute_meta_ecc(osb->sb, alloc_bh->b_data, &alloc->i_check); - status = ocfs2_write_block(osb, alloc_bh, inode); + status = ocfs2_write_block(osb, alloc_bh, INODE_CACHE(inode)); if (status < 0) mlog_errno(status); diff --git a/fs/ocfs2/namei.c b/fs/ocfs2/namei.c index 8601f93..689761b 100644 --- a/fs/ocfs2/namei.c +++ b/fs/ocfs2/namei.c @@ -507,7 +507,7 @@ static int ocfs2_mknod_locked(struct ocfs2_super *osb, mlog_errno(status); goto leave; } - ocfs2_set_new_buffer_uptodate(inode, *new_fe_bh); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(inode), *new_fe_bh); status = ocfs2_journal_access_di(handle, inode, *new_fe_bh, OCFS2_JOURNAL_ACCESS_CREATE); @@ -1527,7 +1527,8 @@ static int ocfs2_create_symlink_data(struct ocfs2_super *osb, mlog_errno(status); goto bail; } - ocfs2_set_new_buffer_uptodate(inode, bhs[virtual]); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(inode), + bhs[virtual]); status = ocfs2_journal_access(handle, inode, bhs[virtual], OCFS2_JOURNAL_ACCESS_CREATE); diff --git a/fs/ocfs2/quota_global.c b/fs/ocfs2/quota_global.c index 44f2a5e..0d7125b 100644 --- a/fs/ocfs2/quota_global.c +++ b/fs/ocfs2/quota_global.c @@ -253,7 +253,7 @@ ssize_t ocfs2_quota_write(struct super_block *sb, int type, flush_dcache_page(bh->b_page); set_buffer_uptodate(bh); unlock_buffer(bh); - ocfs2_set_buffer_uptodate(gqinode, bh); + ocfs2_set_buffer_uptodate(INODE_CACHE(gqinode), bh); err = ocfs2_journal_access_dq(handle, gqinode, bh, ja_type); if (err < 0) { brelse(bh); diff --git a/fs/ocfs2/quota_local.c b/fs/ocfs2/quota_local.c index bdb09cb..3df2954 100644 --- a/fs/ocfs2/quota_local.c +++ b/fs/ocfs2/quota_local.c @@ -993,7 +993,7 @@ static struct ocfs2_quota_chunk *ocfs2_local_quota_add_chunk( goto out_trans; } dchunk = (struct ocfs2_local_disk_chunk *)bh->b_data; - ocfs2_set_new_buffer_uptodate(lqinode, bh); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(lqinode), bh); status = ocfs2_journal_access_dq(handle, lqinode, bh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { @@ -1027,7 +1027,7 @@ static struct ocfs2_quota_chunk *ocfs2_local_quota_add_chunk( mlog_errno(status); goto out_trans; } - ocfs2_set_new_buffer_uptodate(lqinode, dbh); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(lqinode), dbh); status = ocfs2_journal_access_dq(handle, lqinode, dbh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { @@ -1131,7 +1131,7 @@ static struct ocfs2_quota_chunk *ocfs2_extend_local_quota_file( mlog_errno(status); goto out; } - ocfs2_set_new_buffer_uptodate(lqinode, bh); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(lqinode), bh); /* Local quota info, chunk header and the new block we initialize */ handle = ocfs2_start_trans(OCFS2_SB(sb), diff --git a/fs/ocfs2/resize.c b/fs/ocfs2/resize.c index 424adaa..7465f0f 100644 --- a/fs/ocfs2/resize.c +++ b/fs/ocfs2/resize.c @@ -514,7 +514,7 @@ int ocfs2_group_add(struct inode *inode, struct ocfs2_new_group_input *input) goto out_unlock; } - ocfs2_set_new_buffer_uptodate(inode, group_bh); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(inode), group_bh); ret = ocfs2_verify_group_and_input(main_bm_inode, fe, input, group_bh); if (ret) { diff --git a/fs/ocfs2/slot_map.c b/fs/ocfs2/slot_map.c index 40661e7..bfbd7e9 100644 --- a/fs/ocfs2/slot_map.c +++ b/fs/ocfs2/slot_map.c @@ -150,8 +150,8 @@ int ocfs2_refresh_slot_info(struct ocfs2_super *osb) * be !NULL. Thus, ocfs2_read_blocks() will ignore blocknr. If * this is not true, the read of -1 (UINT64_MAX) will fail. */ - ret = ocfs2_read_blocks(si->si_inode, -1, si->si_blocks, si->si_bh, - OCFS2_BH_IGNORE_CACHE, NULL); + ret = ocfs2_read_blocks(INODE_CACHE(si->si_inode), -1, si->si_blocks, + si->si_bh, OCFS2_BH_IGNORE_CACHE, NULL); if (ret == 0) { spin_lock(&osb->osb_lock); ocfs2_update_slot_info(si); @@ -213,7 +213,7 @@ static int ocfs2_update_disk_slot(struct ocfs2_super *osb, ocfs2_update_disk_slot_old(si, slot_num, &bh); spin_unlock(&osb->osb_lock); - status = ocfs2_write_block(osb, bh, si->si_inode); + status = ocfs2_write_block(osb, bh, INODE_CACHE(si->si_inode)); if (status < 0) mlog_errno(status); @@ -404,8 +404,8 @@ static int ocfs2_map_slot_buffers(struct ocfs2_super *osb, (unsigned long long)blkno); bh = NULL; /* Acquire a fresh bh */ - status = ocfs2_read_blocks(si->si_inode, blkno, 1, &bh, - OCFS2_BH_IGNORE_CACHE, NULL); + status = ocfs2_read_blocks(INODE_CACHE(si->si_inode), blkno, + 1, &bh, OCFS2_BH_IGNORE_CACHE, NULL); if (status < 0) { mlog_errno(status); goto bail; diff --git a/fs/ocfs2/suballoc.c b/fs/ocfs2/suballoc.c index 73a16d4..21aaaaa 100644 --- a/fs/ocfs2/suballoc.c +++ b/fs/ocfs2/suballoc.c @@ -310,7 +310,7 @@ int ocfs2_read_group_descriptor(struct inode *inode, struct ocfs2_dinode *di, int rc; struct buffer_head *tmp = *bh; - rc = ocfs2_read_block(inode, gd_blkno, &tmp, + rc = ocfs2_read_block(INODE_CACHE(inode), gd_blkno, &tmp, ocfs2_validate_group_descriptor); if (rc) goto out; @@ -476,7 +476,7 @@ static int ocfs2_block_group_alloc(struct ocfs2_super *osb, mlog_errno(status); goto bail; } - ocfs2_set_new_buffer_uptodate(alloc_inode, bg_bh); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(alloc_inode), bg_bh); status = ocfs2_block_group_fill(handle, alloc_inode, diff --git a/fs/ocfs2/super.c b/fs/ocfs2/super.c index 746ed5d..af118ad 100644 --- a/fs/ocfs2/super.c +++ b/fs/ocfs2/super.c @@ -1683,7 +1683,7 @@ static void ocfs2_inode_init_once(void *data) ocfs2_lock_res_init_once(&oi->ip_inode_lockres); ocfs2_lock_res_init_once(&oi->ip_open_lockres); - ocfs2_metadata_cache_init(&oi->ip_metadata_cache, + ocfs2_metadata_cache_init(INODE_CACHE(&oi->vfs_inode), &ocfs2_inode_caching_ops); inode_init_once(&oi->vfs_inode); diff --git a/fs/ocfs2/uptodate.c b/fs/ocfs2/uptodate.c index 226d042..1c829e4 100644 --- a/fs/ocfs2/uptodate.c +++ b/fs/ocfs2/uptodate.c @@ -75,13 +75,20 @@ struct ocfs2_meta_cache_item { static struct kmem_cache *ocfs2_uptodate_cachep = NULL; -static u64 ocfs2_metadata_cache_owner(struct ocfs2_caching_info *ci) +u64 ocfs2_metadata_cache_owner(struct ocfs2_caching_info *ci) { BUG_ON(!ci || !ci->ci_ops); return ci->ci_ops->co_owner(ci); } +struct super_block *ocfs2_metadata_cache_get_super(struct ocfs2_caching_info *ci) +{ + BUG_ON(!ci || !ci->ci_ops); + + return ci->ci_ops->co_get_super(ci); +} + static void ocfs2_metadata_cache_lock(struct ocfs2_caching_info *ci) { BUG_ON(!ci || !ci->ci_ops); @@ -96,14 +103,14 @@ static void ocfs2_metadata_cache_unlock(struct ocfs2_caching_info *ci) ci->ci_ops->co_cache_unlock(ci); } -static void ocfs2_metadata_cache_io_lock(struct ocfs2_caching_info *ci) +void ocfs2_metadata_cache_io_lock(struct ocfs2_caching_info *ci) { BUG_ON(!ci || !ci->ci_ops); ci->ci_ops->co_io_lock(ci); } -static void ocfs2_metadata_cache_io_unlock(struct ocfs2_caching_info *ci) +void ocfs2_metadata_cache_io_unlock(struct ocfs2_caching_info *ci) { BUG_ON(!ci || !ci->ci_ops); @@ -149,11 +156,9 @@ static unsigned int ocfs2_purge_copied_metadata_tree(struct rb_root *root) * This function is a few more lines longer than necessary due to some * accounting done here, but I think it's worth tracking down those * bugs sooner -- Mark */ -void ocfs2_metadata_cache_purge(struct inode *inode) +void ocfs2_metadata_cache_purge(struct ocfs2_caching_info *ci) { - struct ocfs2_inode_info *oi = OCFS2_I(inode); unsigned int tree, to_purge, purged; - struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; struct rb_root root = RB_ROOT; BUG_ON(!ci || !ci->ci_ops); @@ -223,12 +228,11 @@ ocfs2_search_cache_tree(struct ocfs2_caching_info *ci, return NULL; } -static int ocfs2_buffer_cached(struct ocfs2_inode_info *oi, +static int ocfs2_buffer_cached(struct ocfs2_caching_info *ci, struct buffer_head *bh) { int index = -1; struct ocfs2_meta_cache_item *item = NULL; - struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; ocfs2_metadata_cache_lock(ci); @@ -238,11 +242,9 @@ static int ocfs2_buffer_cached(struct ocfs2_inode_info *oi, !!(ci->ci_flags & OCFS2_CACHE_FL_INLINE)); if (ci->ci_flags & OCFS2_CACHE_FL_INLINE) - index = ocfs2_search_cache_array(&oi->ip_metadata_cache, - bh->b_blocknr); + index = ocfs2_search_cache_array(ci, bh->b_blocknr); else - item = ocfs2_search_cache_tree(&oi->ip_metadata_cache, - bh->b_blocknr); + item = ocfs2_search_cache_tree(ci, bh->b_blocknr); ocfs2_metadata_cache_unlock(ci); @@ -256,7 +258,7 @@ static int ocfs2_buffer_cached(struct ocfs2_inode_info *oi, * * This can be called under lock_buffer() */ -int ocfs2_buffer_uptodate(struct inode *inode, +int ocfs2_buffer_uptodate(struct ocfs2_caching_info *ci, struct buffer_head *bh) { /* Doesn't matter if the bh is in our cache or not -- if it's @@ -272,17 +274,17 @@ int ocfs2_buffer_uptodate(struct inode *inode, /* Ok, locally the buffer is marked as up to date, now search * our cache to see if we can trust that. */ - return ocfs2_buffer_cached(OCFS2_I(inode), bh); + return ocfs2_buffer_cached(ci, bh); } -/* +/* * Determine whether a buffer is currently out on a read-ahead request. * ci_io_sem should be held to serialize submitters with the logic here. */ -int ocfs2_buffer_read_ahead(struct inode *inode, +int ocfs2_buffer_read_ahead(struct ocfs2_caching_info *ci, struct buffer_head *bh) { - return buffer_locked(bh) && ocfs2_buffer_cached(OCFS2_I(inode), bh); + return buffer_locked(bh) && ocfs2_buffer_cached(ci, bh); } /* Requires ip_lock */ @@ -335,8 +337,7 @@ static void __ocfs2_insert_cache_tree(struct ocfs2_caching_info *ci, } /* co_cache_lock() must be held */ -static inline int ocfs2_insert_can_use_array(struct ocfs2_inode_info *oi, - struct ocfs2_caching_info *ci) +static inline int ocfs2_insert_can_use_array(struct ocfs2_caching_info *ci) { return (ci->ci_flags & OCFS2_CACHE_FL_INLINE) && (ci->ci_num_cached < OCFS2_CACHE_INFO_MAX_ARRAY); @@ -347,11 +348,10 @@ static inline int ocfs2_insert_can_use_array(struct ocfs2_inode_info *oi, * when to free in case of error. * * The co_cache_lock() must be held. */ -static void ocfs2_expand_cache(struct ocfs2_inode_info *oi, +static void ocfs2_expand_cache(struct ocfs2_caching_info *ci, struct ocfs2_meta_cache_item **tree) { int i; - struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; mlog_bug_on_msg(ci->ci_num_cached != OCFS2_CACHE_INFO_MAX_ARRAY, "Owner %llu, num cached = %u, should be %u\n", @@ -383,12 +383,11 @@ static void ocfs2_expand_cache(struct ocfs2_inode_info *oi, /* Slow path function - memory allocation is necessary. See the * comment above ocfs2_set_buffer_uptodate for more information. */ -static void __ocfs2_set_buffer_uptodate(struct ocfs2_inode_info *oi, +static void __ocfs2_set_buffer_uptodate(struct ocfs2_caching_info *ci, sector_t block, int expand_tree) { int i; - struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; struct ocfs2_meta_cache_item *new = NULL; struct ocfs2_meta_cache_item *tree[OCFS2_CACHE_INFO_MAX_ARRAY] = { NULL, }; @@ -420,7 +419,7 @@ static void __ocfs2_set_buffer_uptodate(struct ocfs2_inode_info *oi, } ocfs2_metadata_cache_lock(ci); - if (ocfs2_insert_can_use_array(oi, ci)) { + if (ocfs2_insert_can_use_array(ci)) { mlog(0, "Someone cleared the tree underneath us\n"); /* Ok, items were removed from the cache in between * locks. Detect this and revert back to the fast path */ @@ -430,7 +429,7 @@ static void __ocfs2_set_buffer_uptodate(struct ocfs2_inode_info *oi, } if (expand_tree) - ocfs2_expand_cache(oi, tree); + ocfs2_expand_cache(ci, tree); __ocfs2_insert_cache_tree(ci, new); ocfs2_metadata_cache_unlock(ci); @@ -468,16 +467,14 @@ out_free: * Readahead buffers can be passed in here before the I/O request is * completed. */ -void ocfs2_set_buffer_uptodate(struct inode *inode, +void ocfs2_set_buffer_uptodate(struct ocfs2_caching_info *ci, struct buffer_head *bh) { int expand; - struct ocfs2_inode_info *oi = OCFS2_I(inode); - struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; /* The block may very well exist in our cache already, so avoid * doing any more work in that case. */ - if (ocfs2_buffer_cached(oi, bh)) + if (ocfs2_buffer_cached(ci, bh)) return; mlog(0, "Owner %llu, inserting block %llu\n", @@ -487,7 +484,7 @@ void ocfs2_set_buffer_uptodate(struct inode *inode, /* No need to recheck under spinlock - insertion is guarded by * co_io_lock() */ ocfs2_metadata_cache_lock(ci); - if (ocfs2_insert_can_use_array(oi, ci)) { + if (ocfs2_insert_can_use_array(ci)) { /* Fast case - it's an array and there's a free * spot. */ ocfs2_append_cache_array(ci, bh->b_blocknr); @@ -502,25 +499,22 @@ void ocfs2_set_buffer_uptodate(struct inode *inode, } ocfs2_metadata_cache_unlock(ci); - __ocfs2_set_buffer_uptodate(oi, bh->b_blocknr, expand); + __ocfs2_set_buffer_uptodate(ci, bh->b_blocknr, expand); } /* Called against a newly allocated buffer. Most likely nobody should * be able to read this sort of metadata while it's still being * allocated, but this is careful to take co_io_lock() anyway. */ -void ocfs2_set_new_buffer_uptodate(struct inode *inode, +void ocfs2_set_new_buffer_uptodate(struct ocfs2_caching_info *ci, struct buffer_head *bh) { - struct ocfs2_inode_info *oi = OCFS2_I(inode); - struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; - /* This should definitely *not* exist in our cache */ - BUG_ON(ocfs2_buffer_cached(oi, bh)); + BUG_ON(ocfs2_buffer_cached(ci, bh)); set_buffer_uptodate(bh); ocfs2_metadata_cache_io_lock(ci); - ocfs2_set_buffer_uptodate(inode, bh); + ocfs2_set_buffer_uptodate(ci, bh); ocfs2_metadata_cache_io_unlock(ci); } @@ -559,13 +553,11 @@ static void ocfs2_remove_metadata_tree(struct ocfs2_caching_info *ci, ci->ci_num_cached--; } -static void ocfs2_remove_block_from_cache(struct inode *inode, +static void ocfs2_remove_block_from_cache(struct ocfs2_caching_info *ci, sector_t block) { int index; struct ocfs2_meta_cache_item *item = NULL; - struct ocfs2_inode_info *oi = OCFS2_I(inode); - struct ocfs2_caching_info *ci = &oi->ip_metadata_cache; ocfs2_metadata_cache_lock(ci); mlog(0, "Owner %llu, remove %llu, items = %u, array = %u\n", @@ -593,23 +585,24 @@ static void ocfs2_remove_block_from_cache(struct inode *inode, * bother reverting things to an inlined array in the case of a remove * which moves us back under the limit. */ -void ocfs2_remove_from_cache(struct inode *inode, +void ocfs2_remove_from_cache(struct ocfs2_caching_info *ci, struct buffer_head *bh) { sector_t block = bh->b_blocknr; - ocfs2_remove_block_from_cache(inode, block); + ocfs2_remove_block_from_cache(ci, block); } /* Called when we remove xattr clusters from an inode. */ -void ocfs2_remove_xattr_clusters_from_cache(struct inode *inode, +void ocfs2_remove_xattr_clusters_from_cache(struct ocfs2_caching_info *ci, sector_t block, u32 c_len) { - unsigned int i, b_len = ocfs2_clusters_to_blocks(inode->i_sb, 1) * c_len; + struct super_block *sb = ocfs2_metadata_cache_get_super(ci); + unsigned int i, b_len = ocfs2_clusters_to_blocks(sb, 1) * c_len; for (i = 0; i < b_len; i++, block++) - ocfs2_remove_block_from_cache(inode, block); + ocfs2_remove_block_from_cache(ci, block); } int __init init_ocfs2_uptodate_cache(void) diff --git a/fs/ocfs2/uptodate.h b/fs/ocfs2/uptodate.h index 3b33eb8..f268273 100644 --- a/fs/ocfs2/uptodate.h +++ b/fs/ocfs2/uptodate.h @@ -38,6 +38,8 @@ struct ocfs2_caching_operations { */ u64 (*co_owner)(struct ocfs2_caching_info *ci); + /* The superblock is needed during I/O. */ + struct super_block *(*co_get_super)(struct ocfs2_caching_info *ci); /* * Lock and unlock the caching data. These will not sleep, and * should probably be spinlocks. @@ -58,20 +60,25 @@ void exit_ocfs2_uptodate_cache(void); void ocfs2_metadata_cache_init(struct ocfs2_caching_info *ci, const struct ocfs2_caching_operations *ops); -void ocfs2_metadata_cache_purge(struct inode *inode); +void ocfs2_metadata_cache_purge(struct ocfs2_caching_info *ci); -int ocfs2_buffer_uptodate(struct inode *inode, +u64 ocfs2_metadata_cache_owner(struct ocfs2_caching_info *ci); +struct super_block *ocfs2_metadata_cache_get_super(struct ocfs2_caching_info *ci); +void ocfs2_metadata_cache_io_lock(struct ocfs2_caching_info *ci); +void ocfs2_metadata_cache_io_unlock(struct ocfs2_caching_info *ci); + +int ocfs2_buffer_uptodate(struct ocfs2_caching_info *ci, struct buffer_head *bh); -void ocfs2_set_buffer_uptodate(struct inode *inode, +void ocfs2_set_buffer_uptodate(struct ocfs2_caching_info *ci, struct buffer_head *bh); -void ocfs2_set_new_buffer_uptodate(struct inode *inode, +void ocfs2_set_new_buffer_uptodate(struct ocfs2_caching_info *ci, struct buffer_head *bh); -void ocfs2_remove_from_cache(struct inode *inode, +void ocfs2_remove_from_cache(struct ocfs2_caching_info *ci, struct buffer_head *bh); -void ocfs2_remove_xattr_clusters_from_cache(struct inode *inode, +void ocfs2_remove_xattr_clusters_from_cache(struct ocfs2_caching_info *ci, sector_t block, u32 c_len); -int ocfs2_buffer_read_ahead(struct inode *inode, +int ocfs2_buffer_read_ahead(struct ocfs2_caching_info *ci, struct buffer_head *bh); #endif /* OCFS2_UPTODATE_H */ diff --git a/fs/ocfs2/xattr.c b/fs/ocfs2/xattr.c index d1a27cd..19de5c4 100644 --- a/fs/ocfs2/xattr.c +++ b/fs/ocfs2/xattr.c @@ -254,9 +254,9 @@ static int ocfs2_init_xattr_bucket(struct ocfs2_xattr_bucket *bucket, break; } - if (!ocfs2_buffer_uptodate(bucket->bu_inode, + if (!ocfs2_buffer_uptodate(INODE_CACHE(bucket->bu_inode), bucket->bu_bhs[i])) - ocfs2_set_new_buffer_uptodate(bucket->bu_inode, + ocfs2_set_new_buffer_uptodate(INODE_CACHE(bucket->bu_inode), bucket->bu_bhs[i]); } @@ -271,7 +271,7 @@ static int ocfs2_read_xattr_bucket(struct ocfs2_xattr_bucket *bucket, { int rc; - rc = ocfs2_read_blocks(bucket->bu_inode, xb_blkno, + rc = ocfs2_read_blocks(INODE_CACHE(bucket->bu_inode), xb_blkno, bucket->bu_blocks, bucket->bu_bhs, 0, NULL); if (!rc) { @@ -399,7 +399,7 @@ static int ocfs2_read_xattr_block(struct inode *inode, u64 xb_blkno, int rc; struct buffer_head *tmp = *bh; - rc = ocfs2_read_block(inode, xb_blkno, &tmp, + rc = ocfs2_read_block(INODE_CACHE(inode), xb_blkno, &tmp, ocfs2_validate_xattr_block); /* If ocfs2_read_block() got us a new bh, pass it up. */ @@ -724,8 +724,8 @@ static int ocfs2_xattr_shrink_size(struct inode *inode, } block = ocfs2_clusters_to_blocks(inode->i_sb, phys_cpos); - ocfs2_remove_xattr_clusters_from_cache(inode, block, - alloc_size); + ocfs2_remove_xattr_clusters_from_cache(INODE_CACHE(inode), + block, alloc_size); cpos += alloc_size; trunc_len -= alloc_size; } @@ -970,7 +970,8 @@ static int ocfs2_xattr_get_value_outside(struct inode *inode, blkno = ocfs2_clusters_to_blocks(inode->i_sb, p_cluster); /* Copy ocfs2_xattr_value */ for (i = 0; i < num_clusters * bpc; i++, blkno++) { - ret = ocfs2_read_block(inode, blkno, &bh, NULL); + ret = ocfs2_read_block(INODE_CACHE(inode), blkno, + &bh, NULL); if (ret) { mlog_errno(ret); goto out; @@ -1208,7 +1209,8 @@ static int __ocfs2_xattr_set_value_outside(struct inode *inode, blkno = ocfs2_clusters_to_blocks(inode->i_sb, p_cluster); for (i = 0; i < num_clusters * bpc; i++, blkno++) { - ret = ocfs2_read_block(inode, blkno, &bh, NULL); + ret = ocfs2_read_block(INODE_CACHE(inode), blkno, + &bh, NULL); if (ret) { mlog_errno(ret); goto out; @@ -2121,7 +2123,7 @@ static int ocfs2_xattr_block_set(struct inode *inode, } new_bh = sb_getblk(inode->i_sb, first_blkno); - ocfs2_set_new_buffer_uptodate(inode, new_bh); + ocfs2_set_new_buffer_uptodate(INODE_CACHE(inode), new_bh); ret = ocfs2_journal_access_xb(handle, inode, new_bh, OCFS2_JOURNAL_ACCESS_CREATE); @@ -4845,7 +4847,8 @@ static int ocfs2_rm_xattr_cluster(struct inode *inode, mlog(0, "rm xattr extent rec at %u len = %u, start from %llu\n", cpos, len, (unsigned long long)blkno); - ocfs2_remove_xattr_clusters_from_cache(inode, blkno, len); + ocfs2_remove_xattr_clusters_from_cache(INODE_CACHE(inode), blkno, + len); ret = ocfs2_lock_allocators(inode, &et, 0, 1, NULL, &meta_ac); if (ret) { -- cgit v0.10.2 From 66fb345ddd2d343e36692da0ff66126d7a99dc1b Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 15:24:40 -0800 Subject: ocfs2: move ip_last_trans to struct ocfs2_caching_info We have the read side of metadata caching isolated to struct ocfs2_caching_info, now we need the write side. This means the journal functions. The journal only does a couple of things with struct inode. This change moves the ip_last_trans field onto struct ocfs2_caching_info as ci_last_trans. This field tells the journal whether a pending journal flush is required. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/inode.c b/fs/ocfs2/inode.c index 1c9713c..a47750d 100644 --- a/fs/ocfs2/inode.c +++ b/fs/ocfs2/inode.c @@ -1112,7 +1112,7 @@ void ocfs2_clear_inode(struct inode *inode) ocfs2_lock_res_free(&oi->ip_inode_lockres); ocfs2_lock_res_free(&oi->ip_open_lockres); - ocfs2_metadata_cache_purge(INODE_CACHE(inode)); + ocfs2_metadata_cache_exit(INODE_CACHE(inode)); mlog_bug_on_msg(INODE_CACHE(inode)->ci_num_cached, "Clear inode of %llu, inode has %u cache items\n", @@ -1148,7 +1148,6 @@ void ocfs2_clear_inode(struct inode *inode) /* Clear all other flags. */ oi->ip_flags = 0; oi->ip_created_trans = 0; - oi->ip_last_trans = 0; oi->ip_dir_start_lookup = 0; oi->ip_blkno = 0ULL; diff --git a/fs/ocfs2/inode.h b/fs/ocfs2/inode.h index b0a71b2..2cae251 100644 --- a/fs/ocfs2/inode.h +++ b/fs/ocfs2/inode.h @@ -63,8 +63,6 @@ struct ocfs2_inode_info /* next two are protected by trans_inc_lock */ /* which transaction were we created on? Zero if none. */ unsigned long ip_created_trans; - /* last transaction we were a part of. */ - unsigned long ip_last_trans; struct ocfs2_caching_info ip_metadata_cache; diff --git a/fs/ocfs2/journal.h b/fs/ocfs2/journal.h index 2c3222a..d4ac197 100644 --- a/fs/ocfs2/journal.h +++ b/fs/ocfs2/journal.h @@ -94,7 +94,7 @@ static inline void ocfs2_set_inode_lock_trans(struct ocfs2_journal *journal, struct inode *inode) { spin_lock(&trans_inc_lock); - OCFS2_I(inode)->ip_last_trans = journal->j_trans_id; + INODE_CACHE(inode)->ci_last_trans = journal->j_trans_id; spin_unlock(&trans_inc_lock); } @@ -109,7 +109,8 @@ static inline int ocfs2_inode_fully_checkpointed(struct inode *inode) struct ocfs2_journal *journal = OCFS2_SB(inode->i_sb)->journal; spin_lock(&trans_inc_lock); - ret = time_after(journal->j_trans_id, OCFS2_I(inode)->ip_last_trans); + ret = time_after(journal->j_trans_id, + INODE_CACHE(inode)->ci_last_trans); spin_unlock(&trans_inc_lock); return ret; } diff --git a/fs/ocfs2/ocfs2.h b/fs/ocfs2/ocfs2.h index 6e54a49..c9bd7ce 100644 --- a/fs/ocfs2/ocfs2.h +++ b/fs/ocfs2/ocfs2.h @@ -77,6 +77,10 @@ struct ocfs2_caching_info { */ const struct ocfs2_caching_operations *ci_ops; + /* last transaction we were a part of. */ + unsigned long ci_last_trans; + + /* Cache structures */ unsigned int ci_flags; unsigned int ci_num_cached; union { diff --git a/fs/ocfs2/super.c b/fs/ocfs2/super.c index af118ad..4212547 100644 --- a/fs/ocfs2/super.c +++ b/fs/ocfs2/super.c @@ -1669,7 +1669,6 @@ static void ocfs2_inode_init_once(void *data) ocfs2_extent_map_init(&oi->vfs_inode); INIT_LIST_HEAD(&oi->ip_io_markers); oi->ip_created_trans = 0; - oi->ip_last_trans = 0; oi->ip_dir_start_lookup = 0; init_rwsem(&oi->ip_alloc_sem); diff --git a/fs/ocfs2/uptodate.c b/fs/ocfs2/uptodate.c index 1c829e4..81c8220 100644 --- a/fs/ocfs2/uptodate.c +++ b/fs/ocfs2/uptodate.c @@ -118,16 +118,32 @@ void ocfs2_metadata_cache_io_unlock(struct ocfs2_caching_info *ci) } +static void ocfs2_metadata_cache_reset(struct ocfs2_caching_info *ci, + int clear) +{ + ci->ci_flags |= OCFS2_CACHE_FL_INLINE; + ci->ci_num_cached = 0; + + if (clear) + ci->ci_last_trans = 0; +} + void ocfs2_metadata_cache_init(struct ocfs2_caching_info *ci, const struct ocfs2_caching_operations *ops) { BUG_ON(!ops); ci->ci_ops = ops; - ci->ci_flags |= OCFS2_CACHE_FL_INLINE; - ci->ci_num_cached = 0; + ocfs2_metadata_cache_reset(ci, 1); +} + +void ocfs2_metadata_cache_exit(struct ocfs2_caching_info *ci) +{ + ocfs2_metadata_cache_purge(ci); + ocfs2_metadata_cache_reset(ci, 1); } + /* No lock taken here as 'root' is not expected to be visible to other * processes. */ static unsigned int ocfs2_purge_copied_metadata_tree(struct rb_root *root) @@ -177,7 +193,7 @@ void ocfs2_metadata_cache_purge(struct ocfs2_caching_info *ci) if (tree) root = ci->ci_cache.ci_tree; - ocfs2_metadata_cache_init(ci, ci->ci_ops); + ocfs2_metadata_cache_reset(ci, 0); ocfs2_metadata_cache_unlock(ci); purged = ocfs2_purge_copied_metadata_tree(&root); diff --git a/fs/ocfs2/uptodate.h b/fs/ocfs2/uptodate.h index f268273..80dbb1d 100644 --- a/fs/ocfs2/uptodate.h +++ b/fs/ocfs2/uptodate.h @@ -61,6 +61,7 @@ void exit_ocfs2_uptodate_cache(void); void ocfs2_metadata_cache_init(struct ocfs2_caching_info *ci, const struct ocfs2_caching_operations *ops); void ocfs2_metadata_cache_purge(struct ocfs2_caching_info *ci); +void ocfs2_metadata_cache_exit(struct ocfs2_caching_info *ci); u64 ocfs2_metadata_cache_owner(struct ocfs2_caching_info *ci); struct super_block *ocfs2_metadata_cache_get_super(struct ocfs2_caching_info *ci); -- cgit v0.10.2 From 292dd27ec76b96cebcef576f330ab121f59ccf05 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 15:41:59 -0800 Subject: ocfs2: move ip_created_trans to struct ocfs2_caching_info Similar ip_last_trans, ip_created_trans tracks the creation of a journal managed inode. This specifically tracks what transaction created the inode. This is so the code can know if the inode has ever been written to disk. This behavior is desirable for any journal managed object. We move it to struct ocfs2_caching_info as ci_created_trans so that any object using ocfs2_caching_info can rely on this behavior. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/inode.c b/fs/ocfs2/inode.c index a47750d..8a9e708 100644 --- a/fs/ocfs2/inode.c +++ b/fs/ocfs2/inode.c @@ -1147,7 +1147,6 @@ void ocfs2_clear_inode(struct inode *inode) /* Clear all other flags. */ oi->ip_flags = 0; - oi->ip_created_trans = 0; oi->ip_dir_start_lookup = 0; oi->ip_blkno = 0ULL; diff --git a/fs/ocfs2/inode.h b/fs/ocfs2/inode.h index 2cae251..67392f6 100644 --- a/fs/ocfs2/inode.h +++ b/fs/ocfs2/inode.h @@ -60,10 +60,6 @@ struct ocfs2_inode_info u32 ip_dir_start_lookup; - /* next two are protected by trans_inc_lock */ - /* which transaction were we created on? Zero if none. */ - unsigned long ip_created_trans; - struct ocfs2_caching_info ip_metadata_cache; struct ocfs2_extent_map ip_extent_map; diff --git a/fs/ocfs2/journal.h b/fs/ocfs2/journal.h index d4ac197..0bb6754 100644 --- a/fs/ocfs2/journal.h +++ b/fs/ocfs2/journal.h @@ -129,9 +129,9 @@ static inline int ocfs2_inode_is_new(struct inode *inode) return 0; spin_lock(&trans_inc_lock); ret = !(time_after(OCFS2_SB(inode->i_sb)->journal->j_trans_id, - OCFS2_I(inode)->ip_created_trans)); + INODE_CACHE(inode)->ci_created_trans)); if (!ret) - OCFS2_I(inode)->ip_created_trans = 0; + INODE_CACHE(inode)->ci_created_trans = 0; spin_unlock(&trans_inc_lock); return ret; } @@ -140,7 +140,7 @@ static inline void ocfs2_inode_set_new(struct ocfs2_super *osb, struct inode *inode) { spin_lock(&trans_inc_lock); - OCFS2_I(inode)->ip_created_trans = osb->journal->j_trans_id; + INODE_CACHE(inode)->ci_created_trans = osb->journal->j_trans_id; spin_unlock(&trans_inc_lock); } diff --git a/fs/ocfs2/ocfs2.h b/fs/ocfs2/ocfs2.h index c9bd7ce..18b5fea 100644 --- a/fs/ocfs2/ocfs2.h +++ b/fs/ocfs2/ocfs2.h @@ -77,6 +77,9 @@ struct ocfs2_caching_info { */ const struct ocfs2_caching_operations *ci_ops; + /* next two are protected by trans_inc_lock */ + /* which transaction were we created on? Zero if none. */ + unsigned long ci_created_trans; /* last transaction we were a part of. */ unsigned long ci_last_trans; diff --git a/fs/ocfs2/super.c b/fs/ocfs2/super.c index 4212547..e35a505 100644 --- a/fs/ocfs2/super.c +++ b/fs/ocfs2/super.c @@ -1668,7 +1668,6 @@ static void ocfs2_inode_init_once(void *data) spin_lock_init(&oi->ip_lock); ocfs2_extent_map_init(&oi->vfs_inode); INIT_LIST_HEAD(&oi->ip_io_markers); - oi->ip_created_trans = 0; oi->ip_dir_start_lookup = 0; init_rwsem(&oi->ip_alloc_sem); diff --git a/fs/ocfs2/uptodate.c b/fs/ocfs2/uptodate.c index 81c8220..b6284f2 100644 --- a/fs/ocfs2/uptodate.c +++ b/fs/ocfs2/uptodate.c @@ -124,8 +124,10 @@ static void ocfs2_metadata_cache_reset(struct ocfs2_caching_info *ci, ci->ci_flags |= OCFS2_CACHE_FL_INLINE; ci->ci_num_cached = 0; - if (clear) + if (clear) { + ci->ci_created_trans = 0; ci->ci_last_trans = 0; + } } void ocfs2_metadata_cache_init(struct ocfs2_caching_info *ci, -- cgit v0.10.2 From 0cf2f7632b1789b811ab20b611c4156e6de2b055 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 16:41:25 -0800 Subject: ocfs2: Pass struct ocfs2_caching_info to the journal functions. The next step in divorcing metadata I/O management from struct inode is to pass struct ocfs2_caching_info to the journal functions. Thus the journal locks a metadata cache with the cache io_lock function. It also can compare ci_last_trans and ci_created_trans directly. This is a large patch because of all the places we change ocfs2_journal_access..(handle, inode, ...) to ocfs2_journal_access..(handle, INODE_CACHE(inode), ...). Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index d5dffcf..616afa9 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -415,11 +415,11 @@ static inline void ocfs2_et_update_clusters(struct inode *inode, } static inline int ocfs2_et_root_journal_access(handle_t *handle, - struct inode *inode, + struct ocfs2_caching_info *ci, struct ocfs2_extent_tree *et, int type) { - return et->et_root_journal_access(handle, inode, et->et_root_bh, + return et->et_root_journal_access(handle, ci, et->et_root_bh, type); } @@ -633,7 +633,7 @@ static struct ocfs2_path *ocfs2_new_path_from_et(struct ocfs2_extent_tree *et) * ocfs2_journal_access_path(), but I don't have a better one. */ static int ocfs2_path_bh_journal_access(handle_t *handle, - struct inode *inode, + struct ocfs2_caching_info *ci, struct ocfs2_path *path, int idx) { @@ -645,14 +645,15 @@ static int ocfs2_path_bh_journal_access(handle_t *handle, if (idx) access = ocfs2_journal_access_eb; - return access(handle, inode, path->p_node[idx].bh, + return access(handle, ci, path->p_node[idx].bh, OCFS2_JOURNAL_ACCESS_WRITE); } /* * Convenience function to journal all components in a path. */ -static int ocfs2_journal_access_path(struct inode *inode, handle_t *handle, +static int ocfs2_journal_access_path(struct ocfs2_caching_info *ci, + handle_t *handle, struct ocfs2_path *path) { int i, ret = 0; @@ -661,7 +662,7 @@ static int ocfs2_journal_access_path(struct inode *inode, handle_t *handle, goto out; for(i = 0; i < path_num_items(path); i++) { - ret = ocfs2_path_bh_journal_access(handle, inode, path, i); + ret = ocfs2_path_bh_journal_access(handle, ci, path, i); if (ret < 0) { mlog_errno(ret); goto out; @@ -952,7 +953,7 @@ static int ocfs2_create_new_meta_bhs(struct ocfs2_super *osb, ocfs2_set_new_buffer_uptodate(INODE_CACHE(inode), bhs[i]); - status = ocfs2_journal_access_eb(handle, inode, bhs[i], + status = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), bhs[i], OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -1051,7 +1052,7 @@ static int ocfs2_adjust_rightmost_branch(handle_t *handle, goto out; } - status = ocfs2_journal_access_path(inode, handle, path); + status = ocfs2_journal_access_path(INODE_CACHE(inode), handle, path); if (status < 0) { mlog_errno(status); goto out; @@ -1162,7 +1163,7 @@ static int ocfs2_add_branch(struct ocfs2_super *osb, BUG_ON(!OCFS2_IS_VALID_EXTENT_BLOCK(eb)); eb_el = &eb->h_list; - status = ocfs2_journal_access_eb(handle, inode, bh, + status = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), bh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -1202,20 +1203,20 @@ static int ocfs2_add_branch(struct ocfs2_super *osb, * journal_dirty erroring as it won't unless we've aborted the * handle (in which case we would never be here) so reserving * the write with journal_access is all we need to do. */ - status = ocfs2_journal_access_eb(handle, inode, *last_eb_bh, + status = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), *last_eb_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); goto bail; } - status = ocfs2_et_root_journal_access(handle, inode, et, + status = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); goto bail; } if (eb_bh) { - status = ocfs2_journal_access_eb(handle, inode, eb_bh, + status = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), eb_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -1305,7 +1306,7 @@ static int ocfs2_shift_tree_depth(struct ocfs2_super *osb, eb_el = &eb->h_list; root_el = et->et_root_el; - status = ocfs2_journal_access_eb(handle, inode, new_eb_bh, + status = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), new_eb_bh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -1324,7 +1325,7 @@ static int ocfs2_shift_tree_depth(struct ocfs2_super *osb, goto bail; } - status = ocfs2_et_root_journal_access(handle, inode, et, + status = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -2095,7 +2096,7 @@ static int ocfs2_rotate_subtree_right(struct inode *inode, root_bh = left_path->p_node[subtree_index].bh; BUG_ON(root_bh != right_path->p_node[subtree_index].bh); - ret = ocfs2_path_bh_journal_access(handle, inode, right_path, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, subtree_index); if (ret) { mlog_errno(ret); @@ -2103,14 +2104,14 @@ static int ocfs2_rotate_subtree_right(struct inode *inode, } for(i = subtree_index + 1; i < path_num_items(right_path); i++) { - ret = ocfs2_path_bh_journal_access(handle, inode, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, i); if (ret) { mlog_errno(ret); goto out; } - ret = ocfs2_path_bh_journal_access(handle, inode, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), left_path, i); if (ret) { mlog_errno(ret); @@ -2503,7 +2504,7 @@ static int ocfs2_update_edge_lengths(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_journal_access_path(inode, handle, path); + ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, path); if (ret) { mlog_errno(ret); goto out; @@ -2654,7 +2655,7 @@ static int ocfs2_rotate_subtree_left(struct inode *inode, handle_t *handle, return -EAGAIN; if (le16_to_cpu(right_leaf_el->l_next_free_rec) > 1) { - ret = ocfs2_journal_access_eb(handle, inode, + ret = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), path_leaf_bh(right_path), OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { @@ -2673,7 +2674,7 @@ static int ocfs2_rotate_subtree_left(struct inode *inode, handle_t *handle, * We have to update i_last_eb_blk during the meta * data delete. */ - ret = ocfs2_et_root_journal_access(handle, inode, et, + ret = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -2689,7 +2690,7 @@ static int ocfs2_rotate_subtree_left(struct inode *inode, handle_t *handle, */ BUG_ON(right_has_empty && !del_right_subtree); - ret = ocfs2_path_bh_journal_access(handle, inode, right_path, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, subtree_index); if (ret) { mlog_errno(ret); @@ -2697,14 +2698,14 @@ static int ocfs2_rotate_subtree_left(struct inode *inode, handle_t *handle, } for(i = subtree_index + 1; i < path_num_items(right_path); i++) { - ret = ocfs2_path_bh_journal_access(handle, inode, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, i); if (ret) { mlog_errno(ret); goto out; } - ret = ocfs2_path_bh_journal_access(handle, inode, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), left_path, i); if (ret) { mlog_errno(ret); @@ -2864,7 +2865,7 @@ static int ocfs2_rotate_rightmost_leaf_left(struct inode *inode, if (!ocfs2_is_empty_extent(&el->l_recs[0])) return 0; - ret = ocfs2_path_bh_journal_access(handle, inode, path, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), path, path_num_items(path) - 1); if (ret) { mlog_errno(ret); @@ -2947,7 +2948,7 @@ static int __ocfs2_rotate_tree_left(struct inode *inode, * Caller might still want to make changes to the * tree root, so re-add it to the journal here. */ - ret = ocfs2_path_bh_journal_access(handle, inode, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), left_path, 0); if (ret) { mlog_errno(ret); @@ -3025,7 +3026,7 @@ static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_journal_access_path(inode, handle, path); + ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, path); if (ret) { mlog_errno(ret); goto out; @@ -3055,7 +3056,7 @@ static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_journal_access_path(inode, handle, left_path); + ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, left_path); if (ret) { mlog_errno(ret); goto out; @@ -3370,7 +3371,7 @@ static int ocfs2_merge_rec_right(struct inode *inode, root_bh = left_path->p_node[subtree_index].bh; BUG_ON(root_bh != right_path->p_node[subtree_index].bh); - ret = ocfs2_path_bh_journal_access(handle, inode, right_path, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, subtree_index); if (ret) { mlog_errno(ret); @@ -3379,14 +3380,14 @@ static int ocfs2_merge_rec_right(struct inode *inode, for (i = subtree_index + 1; i < path_num_items(right_path); i++) { - ret = ocfs2_path_bh_journal_access(handle, inode, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, i); if (ret) { mlog_errno(ret); goto out; } - ret = ocfs2_path_bh_journal_access(handle, inode, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), left_path, i); if (ret) { mlog_errno(ret); @@ -3399,7 +3400,7 @@ static int ocfs2_merge_rec_right(struct inode *inode, right_rec = &el->l_recs[index + 1]; } - ret = ocfs2_path_bh_journal_access(handle, inode, left_path, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), left_path, path_num_items(left_path) - 1); if (ret) { mlog_errno(ret); @@ -3539,7 +3540,7 @@ static int ocfs2_merge_rec_left(struct inode *inode, root_bh = left_path->p_node[subtree_index].bh; BUG_ON(root_bh != right_path->p_node[subtree_index].bh); - ret = ocfs2_path_bh_journal_access(handle, inode, right_path, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, subtree_index); if (ret) { mlog_errno(ret); @@ -3548,14 +3549,14 @@ static int ocfs2_merge_rec_left(struct inode *inode, for (i = subtree_index + 1; i < path_num_items(right_path); i++) { - ret = ocfs2_path_bh_journal_access(handle, inode, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, i); if (ret) { mlog_errno(ret); goto out; } - ret = ocfs2_path_bh_journal_access(handle, inode, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), left_path, i); if (ret) { mlog_errno(ret); @@ -3568,7 +3569,7 @@ static int ocfs2_merge_rec_left(struct inode *inode, has_empty_extent = 1; } - ret = ocfs2_path_bh_journal_access(handle, inode, right_path, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, path_num_items(right_path) - 1); if (ret) { mlog_errno(ret); @@ -4006,7 +4007,7 @@ static int ocfs2_append_rec_to_path(struct inode *inode, handle_t *handle, } } - ret = ocfs2_journal_access_path(inode, handle, right_path); + ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, right_path); if (ret) { mlog_errno(ret); goto out; @@ -4135,7 +4136,7 @@ static int ocfs2_insert_path(struct inode *inode, goto out; } - ret = ocfs2_journal_access_path(inode, handle, left_path); + ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, left_path); if (ret < 0) { mlog_errno(ret); goto out; @@ -4146,7 +4147,7 @@ static int ocfs2_insert_path(struct inode *inode, * Pass both paths to the journal. The majority of inserts * will be touching all components anyway. */ - ret = ocfs2_journal_access_path(inode, handle, right_path); + ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, right_path); if (ret < 0) { mlog_errno(ret); goto out; @@ -4211,7 +4212,7 @@ static int ocfs2_do_insert_extent(struct inode *inode, el = et->et_root_el; - ret = ocfs2_et_root_journal_access(handle, inode, et, + ret = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -4273,7 +4274,7 @@ static int ocfs2_do_insert_extent(struct inode *inode, * ocfs2_rotate_tree_right() might have extended the * transaction without re-journaling our tree root. */ - ret = ocfs2_et_root_journal_access(handle, inode, et, + ret = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -4796,7 +4797,7 @@ int ocfs2_add_clusters_in_btree(struct ocfs2_super *osb, BUG_ON(num_bits > clusters_to_add); /* reserve our write early -- insert_extent may update the tree root */ - status = ocfs2_et_root_journal_access(handle, inode, et, + status = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -4971,7 +4972,7 @@ static int ocfs2_replace_extent_rec(struct inode *inode, { int ret; - ret = ocfs2_path_bh_journal_access(handle, inode, path, + ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), path, path_num_items(path) - 1); if (ret) { mlog_errno(ret); @@ -5333,13 +5334,13 @@ static int ocfs2_truncate_rec(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_journal_access_path(inode, handle, path); + ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, path); if (ret) { mlog_errno(ret); goto out; } - ret = ocfs2_journal_access_path(inode, handle, left_path); + ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, left_path); if (ret) { mlog_errno(ret); goto out; @@ -5574,7 +5575,7 @@ int ocfs2_remove_btree_range(struct inode *inode, goto out; } - ret = ocfs2_et_root_journal_access(handle, inode, et, + ret = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -5691,7 +5692,7 @@ int ocfs2_truncate_log_append(struct ocfs2_super *osb, goto bail; } - status = ocfs2_journal_access_di(handle, tl_inode, tl_bh, + status = ocfs2_journal_access_di(handle, INODE_CACHE(tl_inode), tl_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -5753,7 +5754,7 @@ static int ocfs2_replay_truncate_records(struct ocfs2_super *osb, while (i >= 0) { /* Caller has given us at least enough credits to * update the truncate log dinode */ - status = ocfs2_journal_access_di(handle, tl_inode, tl_bh, + status = ocfs2_journal_access_di(handle, INODE_CACHE(tl_inode), tl_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -6770,14 +6771,14 @@ static int ocfs2_do_truncate(struct ocfs2_super *osb, * Each component will be touched, so we might as well journal * here to avoid having to handle errors later. */ - status = ocfs2_journal_access_path(inode, handle, path); + status = ocfs2_journal_access_path(INODE_CACHE(inode), handle, path); if (status < 0) { mlog_errno(status); goto bail; } if (last_eb_bh) { - status = ocfs2_journal_access_eb(handle, inode, last_eb_bh, + status = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), last_eb_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -7139,7 +7140,7 @@ int ocfs2_convert_inline_data_to_extents(struct inode *inode, goto out_unlock; } - ret = ocfs2_journal_access_di(handle, inode, di_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), di_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -7508,7 +7509,7 @@ int ocfs2_truncate_inline(struct inode *inode, struct buffer_head *di_bh, goto out; } - ret = ocfs2_journal_access_di(handle, inode, di_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), di_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); diff --git a/fs/ocfs2/aops.c b/fs/ocfs2/aops.c index 8a1e615..49eef2c 100644 --- a/fs/ocfs2/aops.c +++ b/fs/ocfs2/aops.c @@ -1528,7 +1528,7 @@ static int ocfs2_write_begin_inline(struct address_space *mapping, goto out; } - ret = ocfs2_journal_access_di(handle, inode, wc->w_di_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), wc->w_di_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { ocfs2_commit_trans(osb, handle); @@ -1773,7 +1773,7 @@ int ocfs2_write_begin_nolock(struct address_space *mapping, * We don't want this to fail in ocfs2_write_end(), so do it * here. */ - ret = ocfs2_journal_access_di(handle, inode, wc->w_di_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), wc->w_di_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); diff --git a/fs/ocfs2/dir.c b/fs/ocfs2/dir.c index 273fb76..073ab34 100644 --- a/fs/ocfs2/dir.c +++ b/fs/ocfs2/dir.c @@ -176,7 +176,7 @@ static int ocfs2_dx_dir_link_trailer(struct inode *dir, handle_t *handle, struct ocfs2_dx_root_block *dx_root; struct ocfs2_dir_block_trailer *trailer; - ret = ocfs2_journal_access_dr(handle, dir, dx_root_bh, + ret = ocfs2_journal_access_dr(handle, INODE_CACHE(dir), dx_root_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -1136,7 +1136,8 @@ int ocfs2_update_entry(struct inode *dir, handle_t *handle, if (OCFS2_I(dir)->ip_dyn_features & OCFS2_INLINE_DATA_FL) access = ocfs2_journal_access_di; - ret = access(handle, dir, de_bh, OCFS2_JOURNAL_ACCESS_WRITE); + ret = access(handle, INODE_CACHE(dir), de_bh, + OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); goto out; @@ -1179,7 +1180,7 @@ static int __ocfs2_delete_entry(handle_t *handle, struct inode *dir, goto bail; } if (de == de_del) { - status = access(handle, dir, bh, + status = access(handle, INODE_CACHE(dir), bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { status = -EIO; @@ -1329,7 +1330,7 @@ static int ocfs2_delete_entry_dx(handle_t *handle, struct inode *dir, * the entry count needs to be updated. Also, we might be * adding to the start of the free list. */ - ret = ocfs2_journal_access_dr(handle, dir, dx_root_bh, + ret = ocfs2_journal_access_dr(handle, INODE_CACHE(dir), dx_root_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -1337,7 +1338,7 @@ static int ocfs2_delete_entry_dx(handle_t *handle, struct inode *dir, } if (!ocfs2_dx_root_inline(dx_root)) { - ret = ocfs2_journal_access_dl(handle, dir, + ret = ocfs2_journal_access_dl(handle, INODE_CACHE(dir), lookup->dl_dx_leaf_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { @@ -1496,7 +1497,7 @@ static int __ocfs2_dx_dir_leaf_insert(struct inode *dir, handle_t *handle, int ret; struct ocfs2_dx_leaf *dx_leaf; - ret = ocfs2_journal_access_dl(handle, dir, dx_leaf_bh, + ret = ocfs2_journal_access_dl(handle, INODE_CACHE(dir), dx_leaf_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -1526,7 +1527,7 @@ static int ocfs2_dx_dir_insert(struct inode *dir, handle_t *handle, struct ocfs2_dx_root_block *dx_root; struct buffer_head *dx_root_bh = lookup->dl_dx_root_bh; - ret = ocfs2_journal_access_dr(handle, dir, dx_root_bh, + ret = ocfs2_journal_access_dr(handle, INODE_CACHE(dir), dx_root_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -1648,11 +1649,13 @@ int __ocfs2_add_entry(handle_t *handle, */ if (ocfs2_free_list_at_root(lookup)) { bh = lookup->dl_dx_root_bh; - retval = ocfs2_journal_access_dr(handle, dir, bh, + retval = ocfs2_journal_access_dr(handle, + INODE_CACHE(dir), bh, OCFS2_JOURNAL_ACCESS_WRITE); } else { bh = lookup->dl_prev_leaf_bh; - retval = ocfs2_journal_access_db(handle, dir, bh, + retval = ocfs2_journal_access_db(handle, + INODE_CACHE(dir), bh, OCFS2_JOURNAL_ACCESS_WRITE); } if (retval) { @@ -1703,11 +1706,13 @@ int __ocfs2_add_entry(handle_t *handle, } if (insert_bh == parent_fe_bh) - status = ocfs2_journal_access_di(handle, dir, + status = ocfs2_journal_access_di(handle, + INODE_CACHE(dir), insert_bh, OCFS2_JOURNAL_ACCESS_WRITE); else { - status = ocfs2_journal_access_db(handle, dir, + status = ocfs2_journal_access_db(handle, + INODE_CACHE(dir), insert_bh, OCFS2_JOURNAL_ACCESS_WRITE); @@ -2283,7 +2288,7 @@ static int ocfs2_fill_new_dir_id(struct ocfs2_super *osb, struct ocfs2_inline_data *data = &di->id2.i_data; unsigned int size = le16_to_cpu(data->id_count); - ret = ocfs2_journal_access_di(handle, inode, di_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), di_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -2337,7 +2342,7 @@ static int ocfs2_fill_new_dir_el(struct ocfs2_super *osb, ocfs2_set_new_buffer_uptodate(INODE_CACHE(inode), new_bh); - status = ocfs2_journal_access_db(handle, inode, new_bh, + status = ocfs2_journal_access_db(handle, INODE_CACHE(inode), new_bh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -2423,7 +2428,7 @@ static int ocfs2_dx_dir_attach_index(struct ocfs2_super *osb, } ocfs2_set_new_buffer_uptodate(INODE_CACHE(dir), dx_root_bh); - ret = ocfs2_journal_access_dr(handle, dir, dx_root_bh, + ret = ocfs2_journal_access_dr(handle, INODE_CACHE(dir), dx_root_bh, OCFS2_JOURNAL_ACCESS_CREATE); if (ret < 0) { mlog_errno(ret); @@ -2457,7 +2462,7 @@ static int ocfs2_dx_dir_attach_index(struct ocfs2_super *osb, if (ret) mlog_errno(ret); - ret = ocfs2_journal_access_di(handle, dir, di_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(dir), di_bh, OCFS2_JOURNAL_ACCESS_CREATE); if (ret) { mlog_errno(ret); @@ -2500,7 +2505,7 @@ static int ocfs2_dx_dir_format_cluster(struct ocfs2_super *osb, ocfs2_set_new_buffer_uptodate(INODE_CACHE(dir), bh); - ret = ocfs2_journal_access_dl(handle, dir, bh, + ret = ocfs2_journal_access_dl(handle, INODE_CACHE(dir), bh, OCFS2_JOURNAL_ACCESS_CREATE); if (ret < 0) { mlog_errno(ret); @@ -3010,7 +3015,7 @@ static int ocfs2_expand_inline_dir(struct inode *dir, struct buffer_head *di_bh, ocfs2_set_new_buffer_uptodate(INODE_CACHE(dir), dirdata_bh); - ret = ocfs2_journal_access_db(handle, dir, dirdata_bh, + ret = ocfs2_journal_access_db(handle, INODE_CACHE(dir), dirdata_bh, OCFS2_JOURNAL_ACCESS_CREATE); if (ret) { mlog_errno(ret); @@ -3063,7 +3068,7 @@ static int ocfs2_expand_inline_dir(struct inode *dir, struct buffer_head *di_bh, * We let the later dirent insert modify c/mtime - to the user * the data hasn't changed. */ - ret = ocfs2_journal_access_di(handle, dir, di_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(dir), di_bh, OCFS2_JOURNAL_ACCESS_CREATE); if (ret) { mlog_errno(ret); @@ -3392,7 +3397,7 @@ do_extend: ocfs2_set_new_buffer_uptodate(INODE_CACHE(dir), new_bh); - status = ocfs2_journal_access_db(handle, dir, new_bh, + status = ocfs2_journal_access_db(handle, INODE_CACHE(dir), new_bh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -3888,7 +3893,7 @@ static int ocfs2_dx_dir_rebalance(struct ocfs2_super *osb, struct inode *dir, } did_quota = 1; - ret = ocfs2_journal_access_dl(handle, dir, dx_leaf_bh, + ret = ocfs2_journal_access_dl(handle, INODE_CACHE(dir), dx_leaf_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -3952,7 +3957,8 @@ static int ocfs2_dx_dir_rebalance(struct ocfs2_super *osb, struct inode *dir, } for (i = 0; i < num_dx_leaves; i++) { - ret = ocfs2_journal_access_dl(handle, dir, orig_dx_leaves[i], + ret = ocfs2_journal_access_dl(handle, INODE_CACHE(dir), + orig_dx_leaves[i], OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -4168,7 +4174,7 @@ static int ocfs2_expand_inline_dx_root(struct inode *dir, * failure to add the dx_root_bh to the journal won't result * us losing clusters. */ - ret = ocfs2_journal_access_dr(handle, dir, dx_root_bh, + ret = ocfs2_journal_access_dr(handle, INODE_CACHE(dir), dx_root_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -4472,7 +4478,7 @@ static int ocfs2_dx_dir_remove_index(struct inode *dir, goto out_unlock; } - ret = ocfs2_journal_access_di(handle, dir, di_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(dir), di_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); diff --git a/fs/ocfs2/dlmglue.c b/fs/ocfs2/dlmglue.c index fe15cee..f518d1b 100644 --- a/fs/ocfs2/dlmglue.c +++ b/fs/ocfs2/dlmglue.c @@ -3499,7 +3499,7 @@ static int ocfs2_check_meta_downconvert(struct ocfs2_lock_res *lockres, int new_level) { struct inode *inode = ocfs2_lock_res_inode(lockres); - int checkpointed = ocfs2_inode_fully_checkpointed(inode); + int checkpointed = ocfs2_ci_fully_checkpointed(INODE_CACHE(inode)); BUG_ON(new_level != DLM_LOCK_NL && new_level != DLM_LOCK_PR); BUG_ON(lockres->l_level != DLM_LOCK_EX && !checkpointed); diff --git a/fs/ocfs2/file.c b/fs/ocfs2/file.c index aa501d3..3ddbc5e 100644 --- a/fs/ocfs2/file.c +++ b/fs/ocfs2/file.c @@ -259,7 +259,7 @@ int ocfs2_update_inode_atime(struct inode *inode, goto out; } - ret = ocfs2_journal_access_di(handle, inode, bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -356,7 +356,7 @@ static int ocfs2_orphan_for_truncate(struct ocfs2_super *osb, goto out; } - status = ocfs2_journal_access_di(handle, inode, fe_bh, + status = ocfs2_journal_access_di(handle, INODE_CACHE(inode), fe_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -593,7 +593,7 @@ restarted_transaction: /* reserve a write to the file entry early on - that we if we * run out of credits in the allocation path, we can still * update i_size. */ - status = ocfs2_journal_access_di(handle, inode, bh, + status = ocfs2_journal_access_di(handle, INODE_CACHE(inode), bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -1131,7 +1131,7 @@ static int __ocfs2_write_remove_suid(struct inode *inode, goto out; } - ret = ocfs2_journal_access_di(handle, inode, bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret < 0) { mlog_errno(ret); diff --git a/fs/ocfs2/inode.c b/fs/ocfs2/inode.c index 8a9e708..179c819 100644 --- a/fs/ocfs2/inode.c +++ b/fs/ocfs2/inode.c @@ -562,7 +562,8 @@ static int ocfs2_truncate_for_delete(struct ocfs2_super *osb, goto out; } - status = ocfs2_journal_access_di(handle, inode, fe_bh, + status = ocfs2_journal_access_di(handle, INODE_CACHE(inode), + fe_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -646,7 +647,7 @@ static int ocfs2_remove_inode(struct inode *inode, } /* set the inodes dtime */ - status = ocfs2_journal_access_di(handle, inode, di_bh, + status = ocfs2_journal_access_di(handle, INODE_CACHE(inode), di_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -1238,7 +1239,7 @@ int ocfs2_mark_inode_dirty(handle_t *handle, mlog_entry("(inode %llu)\n", (unsigned long long)OCFS2_I(inode)->ip_blkno); - status = ocfs2_journal_access_di(handle, inode, bh, + status = ocfs2_journal_access_di(handle, INODE_CACHE(inode), bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); diff --git a/fs/ocfs2/journal.c b/fs/ocfs2/journal.c index ddf08d3..5b6c0e4 100644 --- a/fs/ocfs2/journal.c +++ b/fs/ocfs2/journal.c @@ -48,6 +48,7 @@ #include "slot_map.h" #include "super.h" #include "sysfile.h" +#include "uptodate.h" #include "quota.h" #include "buffer_head_io.h" @@ -601,14 +602,16 @@ static struct ocfs2_triggers dl_triggers = { }; static int __ocfs2_journal_access(handle_t *handle, - struct inode *inode, + struct ocfs2_caching_info *ci, struct buffer_head *bh, struct ocfs2_triggers *triggers, int type) { int status; + struct ocfs2_super *osb = + OCFS2_SB(ocfs2_metadata_cache_get_super(ci)); - BUG_ON(!inode); + BUG_ON(!ci || !ci->ci_ops); BUG_ON(!handle); BUG_ON(!bh); @@ -627,15 +630,15 @@ static int __ocfs2_journal_access(handle_t *handle, BUG(); } - /* Set the current transaction information on the inode so + /* Set the current transaction information on the ci so * that the locking code knows whether it can drop it's locks - * on this inode or not. We're protected from the commit + * on this ci or not. We're protected from the commit * thread updating the current transaction id until * ocfs2_commit_trans() because ocfs2_start_trans() took * j_trans_barrier for us. */ - ocfs2_set_inode_lock_trans(OCFS2_SB(inode->i_sb)->journal, inode); + ocfs2_set_ci_lock_trans(osb->journal, ci); - mutex_lock(&OCFS2_I(inode)->ip_io_mutex); + ocfs2_metadata_cache_io_lock(ci); switch (type) { case OCFS2_JOURNAL_ACCESS_CREATE: case OCFS2_JOURNAL_ACCESS_WRITE: @@ -650,9 +653,9 @@ static int __ocfs2_journal_access(handle_t *handle, status = -EINVAL; mlog(ML_ERROR, "Uknown access type!\n"); } - if (!status && ocfs2_meta_ecc(OCFS2_SB(inode->i_sb)) && triggers) + if (!status && ocfs2_meta_ecc(osb) && triggers) jbd2_journal_set_triggers(bh, &triggers->ot_triggers); - mutex_unlock(&OCFS2_I(inode)->ip_io_mutex); + ocfs2_metadata_cache_io_unlock(ci); if (status < 0) mlog(ML_ERROR, "Error %d getting %d access to buffer!\n", @@ -662,66 +665,58 @@ static int __ocfs2_journal_access(handle_t *handle, return status; } -int ocfs2_journal_access_di(handle_t *handle, struct inode *inode, - struct buffer_head *bh, int type) +int ocfs2_journal_access_di(handle_t *handle, struct ocfs2_caching_info *ci, + struct buffer_head *bh, int type) { - return __ocfs2_journal_access(handle, inode, bh, &di_triggers, - type); + return __ocfs2_journal_access(handle, ci, bh, &di_triggers, type); } -int ocfs2_journal_access_eb(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_eb(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type) { - return __ocfs2_journal_access(handle, inode, bh, &eb_triggers, - type); + return __ocfs2_journal_access(handle, ci, bh, &eb_triggers, type); } -int ocfs2_journal_access_gd(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_gd(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type) { - return __ocfs2_journal_access(handle, inode, bh, &gd_triggers, - type); + return __ocfs2_journal_access(handle, ci, bh, &gd_triggers, type); } -int ocfs2_journal_access_db(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_db(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type) { - return __ocfs2_journal_access(handle, inode, bh, &db_triggers, - type); + return __ocfs2_journal_access(handle, ci, bh, &db_triggers, type); } -int ocfs2_journal_access_xb(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_xb(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type) { - return __ocfs2_journal_access(handle, inode, bh, &xb_triggers, - type); + return __ocfs2_journal_access(handle, ci, bh, &xb_triggers, type); } -int ocfs2_journal_access_dq(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_dq(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type) { - return __ocfs2_journal_access(handle, inode, bh, &dq_triggers, - type); + return __ocfs2_journal_access(handle, ci, bh, &dq_triggers, type); } -int ocfs2_journal_access_dr(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_dr(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type) { - return __ocfs2_journal_access(handle, inode, bh, &dr_triggers, - type); + return __ocfs2_journal_access(handle, ci, bh, &dr_triggers, type); } -int ocfs2_journal_access_dl(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_dl(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type) { - return __ocfs2_journal_access(handle, inode, bh, &dl_triggers, - type); + return __ocfs2_journal_access(handle, ci, bh, &dl_triggers, type); } -int ocfs2_journal_access(handle_t *handle, struct inode *inode, +int ocfs2_journal_access(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type) { - return __ocfs2_journal_access(handle, inode, bh, NULL, type); + return __ocfs2_journal_access(handle, ci, bh, NULL, type); } int ocfs2_journal_dirty(handle_t *handle, diff --git a/fs/ocfs2/journal.h b/fs/ocfs2/journal.h index 0bb6754..6163f28 100644 --- a/fs/ocfs2/journal.h +++ b/fs/ocfs2/journal.h @@ -90,57 +90,66 @@ static inline unsigned long ocfs2_inc_trans_id(struct ocfs2_journal *j) return old_id; } -static inline void ocfs2_set_inode_lock_trans(struct ocfs2_journal *journal, - struct inode *inode) +static inline void ocfs2_set_ci_lock_trans(struct ocfs2_journal *journal, + struct ocfs2_caching_info *ci) { spin_lock(&trans_inc_lock); - INODE_CACHE(inode)->ci_last_trans = journal->j_trans_id; + ci->ci_last_trans = journal->j_trans_id; spin_unlock(&trans_inc_lock); } /* Used to figure out whether it's safe to drop a metadata lock on an - * inode. Returns true if all the inodes changes have been + * cached object. Returns true if all the object's changes have been * checkpointed to disk. You should be holding the spinlock on the * metadata lock while calling this to be sure that nobody can take * the lock and put it on another transaction. */ -static inline int ocfs2_inode_fully_checkpointed(struct inode *inode) +static inline int ocfs2_ci_fully_checkpointed(struct ocfs2_caching_info *ci) { int ret; - struct ocfs2_journal *journal = OCFS2_SB(inode->i_sb)->journal; + struct ocfs2_journal *journal = + OCFS2_SB(ocfs2_metadata_cache_get_super(ci))->journal; spin_lock(&trans_inc_lock); - ret = time_after(journal->j_trans_id, - INODE_CACHE(inode)->ci_last_trans); + ret = time_after(journal->j_trans_id, ci->ci_last_trans); spin_unlock(&trans_inc_lock); return ret; } -/* convenience function to check if an inode is still new (has never - * hit disk) Will do you a favor and set created_trans = 0 when you've - * been checkpointed. returns '1' if the inode is still new. */ -static inline int ocfs2_inode_is_new(struct inode *inode) +/* convenience function to check if an object backed by struct + * ocfs2_caching_info is still new (has never hit disk) Will do you a + * favor and set created_trans = 0 when you've + * been checkpointed. returns '1' if the ci is still new. */ +static inline int ocfs2_ci_is_new(struct ocfs2_caching_info *ci) { int ret; + struct ocfs2_journal *journal = + OCFS2_SB(ocfs2_metadata_cache_get_super(ci))->journal; + + spin_lock(&trans_inc_lock); + ret = !(time_after(journal->j_trans_id, ci->ci_created_trans)); + if (!ret) + ci->ci_created_trans = 0; + spin_unlock(&trans_inc_lock); + return ret; +} +/* Wrapper for inodes so we can check system files */ +static inline int ocfs2_inode_is_new(struct inode *inode) +{ /* System files are never "new" as they're written out by * mkfs. This helps us early during mount, before we have the * journal open and j_trans_id could be junk. */ if (OCFS2_I(inode)->ip_flags & OCFS2_INODE_SYSTEM_FILE) return 0; - spin_lock(&trans_inc_lock); - ret = !(time_after(OCFS2_SB(inode->i_sb)->journal->j_trans_id, - INODE_CACHE(inode)->ci_created_trans)); - if (!ret) - INODE_CACHE(inode)->ci_created_trans = 0; - spin_unlock(&trans_inc_lock); - return ret; + + return ocfs2_ci_is_new(INODE_CACHE(inode)); } -static inline void ocfs2_inode_set_new(struct ocfs2_super *osb, - struct inode *inode) +static inline void ocfs2_ci_set_new(struct ocfs2_super *osb, + struct ocfs2_caching_info *ci) { spin_lock(&trans_inc_lock); - INODE_CACHE(inode)->ci_created_trans = osb->journal->j_trans_id; + ci->ci_created_trans = osb->journal->j_trans_id; spin_unlock(&trans_inc_lock); } @@ -201,7 +210,7 @@ static inline void ocfs2_checkpoint_inode(struct inode *inode) if (ocfs2_mount_local(osb)) return; - if (!ocfs2_inode_fully_checkpointed(inode)) { + if (!ocfs2_ci_fully_checkpointed(INODE_CACHE(inode))) { /* WARNING: This only kicks off a single * checkpoint. If someone races you and adds more * metadata to the journal, you won't know, and will @@ -211,7 +220,7 @@ static inline void ocfs2_checkpoint_inode(struct inode *inode) ocfs2_start_checkpoint(osb); wait_event(osb->journal->j_checkpointed, - ocfs2_inode_fully_checkpointed(inode)); + ocfs2_ci_fully_checkpointed(INODE_CACHE(inode))); } } @@ -267,31 +276,31 @@ int ocfs2_extend_trans(handle_t *handle, int nblocks); /* ocfs2_inode */ -int ocfs2_journal_access_di(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_di(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type); /* ocfs2_extent_block */ -int ocfs2_journal_access_eb(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_eb(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type); /* ocfs2_group_desc */ -int ocfs2_journal_access_gd(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_gd(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type); /* ocfs2_xattr_block */ -int ocfs2_journal_access_xb(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_xb(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type); /* quota blocks */ -int ocfs2_journal_access_dq(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_dq(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type); /* dirblock */ -int ocfs2_journal_access_db(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_db(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type); /* ocfs2_dx_root_block */ -int ocfs2_journal_access_dr(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_dr(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type); /* ocfs2_dx_leaf */ -int ocfs2_journal_access_dl(handle_t *handle, struct inode *inode, +int ocfs2_journal_access_dl(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type); /* Anything that has no ecc */ -int ocfs2_journal_access(handle_t *handle, struct inode *inode, +int ocfs2_journal_access(handle_t *handle, struct ocfs2_caching_info *ci, struct buffer_head *bh, int type); /* diff --git a/fs/ocfs2/localalloc.c b/fs/ocfs2/localalloc.c index da5dd6a..ac10f83 100644 --- a/fs/ocfs2/localalloc.c +++ b/fs/ocfs2/localalloc.c @@ -297,8 +297,8 @@ void ocfs2_shutdown_local_alloc(struct ocfs2_super *osb) } memcpy(alloc_copy, alloc, bh->b_size); - status = ocfs2_journal_access_di(handle, local_alloc_inode, bh, - OCFS2_JOURNAL_ACCESS_WRITE); + status = ocfs2_journal_access_di(handle, INODE_CACHE(local_alloc_inode), + bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); goto out_commit; @@ -678,7 +678,8 @@ int ocfs2_claim_local_alloc_bits(struct ocfs2_super *osb, * delete bits from it! */ *num_bits = bits_wanted; - status = ocfs2_journal_access_di(handle, local_alloc_inode, + status = ocfs2_journal_access_di(handle, + INODE_CACHE(local_alloc_inode), osb->local_alloc_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { @@ -1156,7 +1157,8 @@ static int ocfs2_local_alloc_slide_window(struct ocfs2_super *osb, } memcpy(alloc_copy, alloc, osb->local_alloc_bh->b_size); - status = ocfs2_journal_access_di(handle, local_alloc_inode, + status = ocfs2_journal_access_di(handle, + INODE_CACHE(local_alloc_inode), osb->local_alloc_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { diff --git a/fs/ocfs2/namei.c b/fs/ocfs2/namei.c index 689761b..c07217a 100644 --- a/fs/ocfs2/namei.c +++ b/fs/ocfs2/namei.c @@ -375,7 +375,8 @@ static int ocfs2_mknod(struct inode *dir, goto leave; } - status = ocfs2_journal_access_di(handle, dir, parent_fe_bh, + status = ocfs2_journal_access_di(handle, INODE_CACHE(dir), + parent_fe_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -509,7 +510,8 @@ static int ocfs2_mknod_locked(struct ocfs2_super *osb, } ocfs2_set_new_buffer_uptodate(INODE_CACHE(inode), *new_fe_bh); - status = ocfs2_journal_access_di(handle, inode, *new_fe_bh, + status = ocfs2_journal_access_di(handle, INODE_CACHE(inode), + *new_fe_bh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -565,7 +567,7 @@ static int ocfs2_mknod_locked(struct ocfs2_super *osb, } ocfs2_populate_inode(inode, fe, 1); - ocfs2_inode_set_new(osb, inode); + ocfs2_ci_set_new(osb, INODE_CACHE(inode)); if (!ocfs2_mount_local(osb)) { status = ocfs2_create_new_inode_locks(inode); if (status < 0) @@ -682,7 +684,7 @@ static int ocfs2_link(struct dentry *old_dentry, goto out_unlock_inode; } - err = ocfs2_journal_access_di(handle, inode, fe_bh, + err = ocfs2_journal_access_di(handle, INODE_CACHE(inode), fe_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (err < 0) { mlog_errno(err); @@ -866,7 +868,7 @@ static int ocfs2_unlink(struct inode *dir, goto leave; } - status = ocfs2_journal_access_di(handle, inode, fe_bh, + status = ocfs2_journal_access_di(handle, INODE_CACHE(inode), fe_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -1284,7 +1286,8 @@ static int ocfs2_rename(struct inode *old_dir, goto bail; } } - status = ocfs2_journal_access_di(handle, new_inode, newfe_bh, + status = ocfs2_journal_access_di(handle, INODE_CACHE(new_inode), + newfe_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -1331,7 +1334,8 @@ static int ocfs2_rename(struct inode *old_dir, old_inode->i_ctime = CURRENT_TIME; mark_inode_dirty(old_inode); - status = ocfs2_journal_access_di(handle, old_inode, old_inode_bh, + status = ocfs2_journal_access_di(handle, INODE_CACHE(old_inode), + old_inode_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status >= 0) { old_di = (struct ocfs2_dinode *) old_inode_bh->b_data; @@ -1407,9 +1411,10 @@ static int ocfs2_rename(struct inode *old_dir, (int)old_dir_nlink, old_dir->i_nlink); } else { struct ocfs2_dinode *fe; - status = ocfs2_journal_access_di(handle, old_dir, - old_dir_bh, - OCFS2_JOURNAL_ACCESS_WRITE); + status = ocfs2_journal_access_di(handle, + INODE_CACHE(old_dir), + old_dir_bh, + OCFS2_JOURNAL_ACCESS_WRITE); fe = (struct ocfs2_dinode *) old_dir_bh->b_data; ocfs2_set_links_count(fe, old_dir->i_nlink); status = ocfs2_journal_dirty(handle, old_dir_bh); @@ -1530,7 +1535,8 @@ static int ocfs2_create_symlink_data(struct ocfs2_super *osb, ocfs2_set_new_buffer_uptodate(INODE_CACHE(inode), bhs[virtual]); - status = ocfs2_journal_access(handle, inode, bhs[virtual], + status = ocfs2_journal_access(handle, INODE_CACHE(inode), + bhs[virtual], OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -1918,7 +1924,9 @@ static int ocfs2_orphan_add(struct ocfs2_super *osb, goto leave; } - status = ocfs2_journal_access_di(handle, orphan_dir_inode, orphan_dir_bh, + status = ocfs2_journal_access_di(handle, + INODE_CACHE(orphan_dir_inode), + orphan_dir_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -2003,7 +2011,9 @@ int ocfs2_orphan_del(struct ocfs2_super *osb, goto leave; } - status = ocfs2_journal_access_di(handle,orphan_dir_inode, orphan_dir_bh, + status = ocfs2_journal_access_di(handle, + INODE_CACHE(orphan_dir_inode), + orphan_dir_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); diff --git a/fs/ocfs2/ocfs2.h b/fs/ocfs2/ocfs2.h index 18b5fea..d370262 100644 --- a/fs/ocfs2/ocfs2.h +++ b/fs/ocfs2/ocfs2.h @@ -91,6 +91,11 @@ struct ocfs2_caching_info { struct rb_root ci_tree; } ci_cache; }; +/* + * Need this prototype here instead of in uptodate.h because journal.h + * uses it. + */ +struct super_block *ocfs2_metadata_cache_get_super(struct ocfs2_caching_info *ci); /* this limits us to 256 nodes * if we need more, we can do a kmalloc for the map */ @@ -408,7 +413,8 @@ struct ocfs2_super #define OCFS2_SB(sb) ((struct ocfs2_super *)(sb)->s_fs_info) /* Useful typedef for passing around journal access functions */ -typedef int (*ocfs2_journal_access_func)(handle_t *handle, struct inode *inode, +typedef int (*ocfs2_journal_access_func)(handle_t *handle, + struct ocfs2_caching_info *ci, struct buffer_head *bh, int type); static inline int ocfs2_should_order_data(struct inode *inode) diff --git a/fs/ocfs2/quota_global.c b/fs/ocfs2/quota_global.c index 0d7125b..7eadf8b 100644 --- a/fs/ocfs2/quota_global.c +++ b/fs/ocfs2/quota_global.c @@ -254,7 +254,8 @@ ssize_t ocfs2_quota_write(struct super_block *sb, int type, set_buffer_uptodate(bh); unlock_buffer(bh); ocfs2_set_buffer_uptodate(INODE_CACHE(gqinode), bh); - err = ocfs2_journal_access_dq(handle, gqinode, bh, ja_type); + err = ocfs2_journal_access_dq(handle, INODE_CACHE(gqinode), bh, + ja_type); if (err < 0) { brelse(bh); goto out; diff --git a/fs/ocfs2/quota_local.c b/fs/ocfs2/quota_local.c index 3df2954..1a2c50a 100644 --- a/fs/ocfs2/quota_local.c +++ b/fs/ocfs2/quota_local.c @@ -108,7 +108,7 @@ static int ocfs2_modify_bh(struct inode *inode, struct buffer_head *bh, mlog_errno(status); return status; } - status = ocfs2_journal_access_dq(handle, inode, bh, + status = ocfs2_journal_access_dq(handle, INODE_CACHE(inode), bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -510,7 +510,8 @@ static int ocfs2_recover_local_quota_file(struct inode *lqinode, goto out_commit; } /* Release local quota file entry */ - status = ocfs2_journal_access_dq(handle, lqinode, + status = ocfs2_journal_access_dq(handle, + INODE_CACHE(lqinode), qbh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -619,7 +620,8 @@ int ocfs2_finish_quota_recovery(struct ocfs2_super *osb, mlog_errno(status); goto out_bh; } - status = ocfs2_journal_access_dq(handle, lqinode, bh, + status = ocfs2_journal_access_dq(handle, INODE_CACHE(lqinode), + bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -994,7 +996,7 @@ static struct ocfs2_quota_chunk *ocfs2_local_quota_add_chunk( } dchunk = (struct ocfs2_local_disk_chunk *)bh->b_data; ocfs2_set_new_buffer_uptodate(INODE_CACHE(lqinode), bh); - status = ocfs2_journal_access_dq(handle, lqinode, bh, + status = ocfs2_journal_access_dq(handle, INODE_CACHE(lqinode), bh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -1028,7 +1030,7 @@ static struct ocfs2_quota_chunk *ocfs2_local_quota_add_chunk( goto out_trans; } ocfs2_set_new_buffer_uptodate(INODE_CACHE(lqinode), dbh); - status = ocfs2_journal_access_dq(handle, lqinode, dbh, + status = ocfs2_journal_access_dq(handle, INODE_CACHE(lqinode), dbh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -1143,7 +1145,7 @@ static struct ocfs2_quota_chunk *ocfs2_extend_local_quota_file( goto out; } /* Zero created block */ - status = ocfs2_journal_access_dq(handle, lqinode, bh, + status = ocfs2_journal_access_dq(handle, INODE_CACHE(lqinode), bh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -1158,7 +1160,8 @@ static struct ocfs2_quota_chunk *ocfs2_extend_local_quota_file( goto out_trans; } /* Update chunk header */ - status = ocfs2_journal_access_dq(handle, lqinode, chunk->qc_headerbh, + status = ocfs2_journal_access_dq(handle, INODE_CACHE(lqinode), + chunk->qc_headerbh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -1292,7 +1295,8 @@ static int ocfs2_local_release_dquot(struct dquot *dquot) goto out; } - status = ocfs2_journal_access_dq(handle, sb_dqopt(sb)->files[type], + status = ocfs2_journal_access_dq(handle, + INODE_CACHE(sb_dqopt(sb)->files[type]), od->dq_chunk->qc_headerbh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); diff --git a/fs/ocfs2/resize.c b/fs/ocfs2/resize.c index 7465f0f..3c3d673 100644 --- a/fs/ocfs2/resize.c +++ b/fs/ocfs2/resize.c @@ -106,8 +106,8 @@ static int ocfs2_update_last_group_and_inode(handle_t *handle, mlog_entry("(new_clusters=%d, first_new_cluster = %u)\n", new_clusters, first_new_cluster); - ret = ocfs2_journal_access_gd(handle, bm_inode, group_bh, - OCFS2_JOURNAL_ACCESS_WRITE); + ret = ocfs2_journal_access_gd(handle, INODE_CACHE(bm_inode), + group_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret < 0) { mlog_errno(ret); goto out; @@ -141,7 +141,7 @@ static int ocfs2_update_last_group_and_inode(handle_t *handle, } /* update the inode accordingly. */ - ret = ocfs2_journal_access_di(handle, bm_inode, bm_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(bm_inode), bm_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret < 0) { mlog_errno(ret); @@ -536,8 +536,8 @@ int ocfs2_group_add(struct inode *inode, struct ocfs2_new_group_input *input) cl = &fe->id2.i_chain; cr = &cl->cl_recs[input->chain]; - ret = ocfs2_journal_access_gd(handle, main_bm_inode, group_bh, - OCFS2_JOURNAL_ACCESS_WRITE); + ret = ocfs2_journal_access_gd(handle, INODE_CACHE(main_bm_inode), + group_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret < 0) { mlog_errno(ret); goto out_commit; @@ -552,8 +552,8 @@ int ocfs2_group_add(struct inode *inode, struct ocfs2_new_group_input *input) goto out_commit; } - ret = ocfs2_journal_access_di(handle, main_bm_inode, main_bm_bh, - OCFS2_JOURNAL_ACCESS_WRITE); + ret = ocfs2_journal_access_di(handle, INODE_CACHE(main_bm_inode), + main_bm_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret < 0) { mlog_errno(ret); goto out_commit; diff --git a/fs/ocfs2/suballoc.c b/fs/ocfs2/suballoc.c index 21aaaaa..a6c442c 100644 --- a/fs/ocfs2/suballoc.c +++ b/fs/ocfs2/suballoc.c @@ -352,7 +352,7 @@ static int ocfs2_block_group_fill(handle_t *handle, } status = ocfs2_journal_access_gd(handle, - alloc_inode, + INODE_CACHE(alloc_inode), bg_bh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { @@ -491,7 +491,7 @@ static int ocfs2_block_group_alloc(struct ocfs2_super *osb, bg = (struct ocfs2_group_desc *) bg_bh->b_data; - status = ocfs2_journal_access_di(handle, alloc_inode, + status = ocfs2_journal_access_di(handle, INODE_CACHE(alloc_inode), bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -1033,7 +1033,7 @@ static inline int ocfs2_block_group_set_bits(handle_t *handle, journal_type = OCFS2_JOURNAL_ACCESS_UNDO; status = ocfs2_journal_access_gd(handle, - alloc_inode, + INODE_CACHE(alloc_inode), group_bh, journal_type); if (status < 0) { @@ -1106,7 +1106,8 @@ static int ocfs2_relink_block_group(handle_t *handle, bg_ptr = le64_to_cpu(bg->bg_next_group); prev_bg_ptr = le64_to_cpu(prev_bg->bg_next_group); - status = ocfs2_journal_access_gd(handle, alloc_inode, prev_bg_bh, + status = ocfs2_journal_access_gd(handle, INODE_CACHE(alloc_inode), + prev_bg_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -1121,8 +1122,8 @@ static int ocfs2_relink_block_group(handle_t *handle, goto out_rollback; } - status = ocfs2_journal_access_gd(handle, alloc_inode, bg_bh, - OCFS2_JOURNAL_ACCESS_WRITE); + status = ocfs2_journal_access_gd(handle, INODE_CACHE(alloc_inode), + bg_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); goto out_rollback; @@ -1136,8 +1137,8 @@ static int ocfs2_relink_block_group(handle_t *handle, goto out_rollback; } - status = ocfs2_journal_access_di(handle, alloc_inode, fe_bh, - OCFS2_JOURNAL_ACCESS_WRITE); + status = ocfs2_journal_access_di(handle, INODE_CACHE(alloc_inode), + fe_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); goto out_rollback; @@ -1288,7 +1289,7 @@ static int ocfs2_alloc_dinode_update_counts(struct inode *inode, struct ocfs2_dinode *di = (struct ocfs2_dinode *) di_bh->b_data; struct ocfs2_chain_list *cl = (struct ocfs2_chain_list *) &di->id2.i_chain; - ret = ocfs2_journal_access_di(handle, inode, di_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), di_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret < 0) { mlog_errno(ret); @@ -1461,7 +1462,7 @@ static int ocfs2_search_chain(struct ocfs2_alloc_context *ac, /* Ok, claim our bits now: set the info on dinode, chainlist * and then the group */ status = ocfs2_journal_access_di(handle, - alloc_inode, + INODE_CACHE(alloc_inode), ac->ac_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { @@ -1907,8 +1908,8 @@ static inline int ocfs2_block_group_clear_bits(handle_t *handle, if (ocfs2_is_cluster_bitmap(alloc_inode)) journal_type = OCFS2_JOURNAL_ACCESS_UNDO; - status = ocfs2_journal_access_gd(handle, alloc_inode, group_bh, - journal_type); + status = ocfs2_journal_access_gd(handle, INODE_CACHE(alloc_inode), + group_bh, journal_type); if (status < 0) { mlog_errno(status); goto bail; @@ -1993,8 +1994,8 @@ int ocfs2_free_suballoc_bits(handle_t *handle, goto bail; } - status = ocfs2_journal_access_di(handle, alloc_inode, alloc_bh, - OCFS2_JOURNAL_ACCESS_WRITE); + status = ocfs2_journal_access_di(handle, INODE_CACHE(alloc_inode), + alloc_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); goto bail; diff --git a/fs/ocfs2/uptodate.h b/fs/ocfs2/uptodate.h index 80dbb1d..0d826fe 100644 --- a/fs/ocfs2/uptodate.h +++ b/fs/ocfs2/uptodate.h @@ -64,7 +64,6 @@ void ocfs2_metadata_cache_purge(struct ocfs2_caching_info *ci); void ocfs2_metadata_cache_exit(struct ocfs2_caching_info *ci); u64 ocfs2_metadata_cache_owner(struct ocfs2_caching_info *ci); -struct super_block *ocfs2_metadata_cache_get_super(struct ocfs2_caching_info *ci); void ocfs2_metadata_cache_io_lock(struct ocfs2_caching_info *ci); void ocfs2_metadata_cache_io_unlock(struct ocfs2_caching_info *ci); diff --git a/fs/ocfs2/xattr.c b/fs/ocfs2/xattr.c index 19de5c4..93aae79 100644 --- a/fs/ocfs2/xattr.c +++ b/fs/ocfs2/xattr.c @@ -297,7 +297,8 @@ static int ocfs2_xattr_bucket_journal_access(handle_t *handle, int i, rc = 0; for (i = 0; i < bucket->bu_blocks; i++) { - rc = ocfs2_journal_access(handle, bucket->bu_inode, + rc = ocfs2_journal_access(handle, + INODE_CACHE(bucket->bu_inode), bucket->bu_bhs[i], type); if (rc) { mlog_errno(rc); @@ -604,7 +605,7 @@ static int ocfs2_xattr_extend_allocation(struct inode *inode, ocfs2_init_xattr_value_extent_tree(&et, inode, vb); - status = vb->vb_access(handle, inode, vb->vb_bh, + status = vb->vb_access(handle, INODE_CACHE(inode), vb->vb_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -658,7 +659,7 @@ static int __ocfs2_remove_xattr_range(struct inode *inode, ocfs2_init_xattr_value_extent_tree(&et, inode, vb); - ret = vb->vb_access(handle, inode, vb->vb_bh, + ret = vb->vb_access(handle, INODE_CACHE(inode), vb->vb_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -1217,7 +1218,7 @@ static int __ocfs2_xattr_set_value_outside(struct inode *inode, } ret = ocfs2_journal_access(handle, - inode, + INODE_CACHE(inode), bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret < 0) { @@ -1268,7 +1269,7 @@ static int ocfs2_xattr_cleanup(struct inode *inode, void *val = xs->base + offs; size_t size = OCFS2_XATTR_SIZE(name_len) + OCFS2_XATTR_ROOT_SIZE; - ret = vb->vb_access(handle, inode, vb->vb_bh, + ret = vb->vb_access(handle, INODE_CACHE(inode), vb->vb_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -1296,7 +1297,7 @@ static int ocfs2_xattr_update_entry(struct inode *inode, { int ret; - ret = vb->vb_access(handle, inode, vb->vb_bh, + ret = vb->vb_access(handle, INODE_CACHE(inode), vb->vb_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -1617,7 +1618,7 @@ static int ocfs2_xattr_set_entry(struct inode *inode, } } - ret = ocfs2_journal_access_di(handle, inode, xs->inode_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), xs->inode_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -1625,7 +1626,7 @@ static int ocfs2_xattr_set_entry(struct inode *inode, } if (!(flag & OCFS2_INLINE_XATTR_FL)) { - ret = vb.vb_access(handle, inode, vb.vb_bh, + ret = vb.vb_access(handle, INODE_CACHE(inode), vb.vb_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -1898,7 +1899,7 @@ int ocfs2_xattr_remove(struct inode *inode, struct buffer_head *di_bh) mlog_errno(ret); goto out; } - ret = ocfs2_journal_access_di(handle, inode, di_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), di_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -2107,7 +2108,8 @@ static int ocfs2_xattr_block_set(struct inode *inode, int ret; if (!xs->xattr_bh) { - ret = ocfs2_journal_access_di(handle, inode, xs->inode_bh, + ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), + xs->inode_bh, OCFS2_JOURNAL_ACCESS_CREATE); if (ret < 0) { mlog_errno(ret); @@ -2125,7 +2127,8 @@ static int ocfs2_xattr_block_set(struct inode *inode, new_bh = sb_getblk(inode->i_sb, first_blkno); ocfs2_set_new_buffer_uptodate(INODE_CACHE(inode), new_bh); - ret = ocfs2_journal_access_xb(handle, inode, new_bh, + ret = ocfs2_journal_access_xb(handle, INODE_CACHE(inode), + new_bh, OCFS2_JOURNAL_ACCESS_CREATE); if (ret < 0) { mlog_errno(ret); @@ -2600,7 +2603,7 @@ static int __ocfs2_xattr_set_handle(struct inode *inode, if (!ret) { /* Update inode ctime. */ - ret = ocfs2_journal_access_di(ctxt->handle, inode, + ret = ocfs2_journal_access_di(ctxt->handle, INODE_CACHE(inode), xis->inode_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { @@ -3428,7 +3431,7 @@ static int ocfs2_xattr_create_index_block(struct inode *inode, */ down_write(&oi->ip_alloc_sem); - ret = ocfs2_journal_access_xb(handle, inode, xb_bh, + ret = ocfs2_journal_access_xb(handle, INODE_CACHE(inode), xb_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -4267,7 +4270,7 @@ static int ocfs2_add_new_xattr_cluster(struct inode *inode, ocfs2_init_xattr_tree_extent_tree(&et, inode, root_bh); - ret = ocfs2_journal_access_xb(handle, inode, root_bh, + ret = ocfs2_journal_access_xb(handle, INODE_CACHE(inode), root_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret < 0) { mlog_errno(ret); @@ -4873,7 +4876,7 @@ static int ocfs2_rm_xattr_cluster(struct inode *inode, goto out; } - ret = ocfs2_journal_access_xb(handle, inode, root_bh, + ret = ocfs2_journal_access_xb(handle, INODE_CACHE(inode), root_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); -- cgit v0.10.2 From d9a0a1f83bf083b55b3c1f16efddecc31abace61 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 17:32:34 -0800 Subject: ocfs2: Store the ocfs2_caching_info on ocfs2_extent_tree. What do we cache? Metadata blocks. What are most of our non-inode metadata blocks? Extent blocks for our btrees. struct ocfs2_extent_tree is the main structure for managing those. So let's store the associated ocfs2_caching_info there. This means that ocfs2_et_root_journal_access() doesn't need struct inode anymore, and any place that has an et can refer to et->et_ci instead of INODE_CACHE(inode). Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 616afa9..a26294c 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -352,6 +352,7 @@ static void __ocfs2_init_extent_tree(struct ocfs2_extent_tree *et, { et->et_ops = ops; et->et_root_bh = bh; + et->et_ci = INODE_CACHE(inode); et->et_root_journal_access = access; if (!obj) obj = (void *)bh->b_data; @@ -415,11 +416,10 @@ static inline void ocfs2_et_update_clusters(struct inode *inode, } static inline int ocfs2_et_root_journal_access(handle_t *handle, - struct ocfs2_caching_info *ci, struct ocfs2_extent_tree *et, int type) { - return et->et_root_journal_access(handle, ci, et->et_root_bh, + return et->et_root_journal_access(handle, et->et_ci, et->et_root_bh, type); } @@ -1209,7 +1209,7 @@ static int ocfs2_add_branch(struct ocfs2_super *osb, mlog_errno(status); goto bail; } - status = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, + status = ocfs2_et_root_journal_access(handle, et, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -1325,7 +1325,7 @@ static int ocfs2_shift_tree_depth(struct ocfs2_super *osb, goto bail; } - status = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, + status = ocfs2_et_root_journal_access(handle, et, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -2674,7 +2674,7 @@ static int ocfs2_rotate_subtree_left(struct inode *inode, handle_t *handle, * We have to update i_last_eb_blk during the meta * data delete. */ - ret = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, + ret = ocfs2_et_root_journal_access(handle, et, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -3026,7 +3026,7 @@ static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, path); + ret = ocfs2_journal_access_path(et->et_ci, handle, path); if (ret) { mlog_errno(ret); goto out; @@ -3056,7 +3056,7 @@ static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, left_path); + ret = ocfs2_journal_access_path(et->et_ci, handle, left_path); if (ret) { mlog_errno(ret); goto out; @@ -4212,7 +4212,7 @@ static int ocfs2_do_insert_extent(struct inode *inode, el = et->et_root_el; - ret = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, + ret = ocfs2_et_root_journal_access(handle, et, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -4274,7 +4274,7 @@ static int ocfs2_do_insert_extent(struct inode *inode, * ocfs2_rotate_tree_right() might have extended the * transaction without re-journaling our tree root. */ - ret = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, + ret = ocfs2_et_root_journal_access(handle, et, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); @@ -4797,7 +4797,7 @@ int ocfs2_add_clusters_in_btree(struct ocfs2_super *osb, BUG_ON(num_bits > clusters_to_add); /* reserve our write early -- insert_extent may update the tree root */ - status = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, + status = ocfs2_et_root_journal_access(handle, et, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -5334,13 +5334,13 @@ static int ocfs2_truncate_rec(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, path); + ret = ocfs2_journal_access_path(et->et_ci, handle, path); if (ret) { mlog_errno(ret); goto out; } - ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, left_path); + ret = ocfs2_journal_access_path(et->et_ci, handle, left_path); if (ret) { mlog_errno(ret); goto out; @@ -5575,7 +5575,7 @@ int ocfs2_remove_btree_range(struct inode *inode, goto out; } - ret = ocfs2_et_root_journal_access(handle, INODE_CACHE(inode), et, + ret = ocfs2_et_root_journal_access(handle, et, OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { mlog_errno(ret); diff --git a/fs/ocfs2/alloc.h b/fs/ocfs2/alloc.h index 353254b..285d40b 100644 --- a/fs/ocfs2/alloc.h +++ b/fs/ocfs2/alloc.h @@ -45,7 +45,8 @@ * * ocfs2_extent_tree contains info for the root of the b-tree, it must have a * root ocfs2_extent_list and a root_bh so that they can be used in the b-tree - * functions. With metadata ecc, we now call different journal_access + * functions. It needs the ocfs2_caching_info structure associated with + * I/O on the tree. With metadata ecc, we now call different journal_access * functions for each type of metadata, so it must have the * root_journal_access function. * ocfs2_extent_tree_operations abstract the normal operations we do for @@ -56,6 +57,7 @@ struct ocfs2_extent_tree { struct ocfs2_extent_tree_operations *et_ops; struct buffer_head *et_root_bh; struct ocfs2_extent_list *et_root_el; + struct ocfs2_caching_info *et_ci; ocfs2_journal_access_func et_root_journal_access; void *et_object; unsigned int et_max_leaf_clusters; -- cgit v0.10.2 From 3d03a305ded8057155bd3c801e64ffef9f534827 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 17:49:26 -0800 Subject: ocfs2: Pass ocfs2_caching_info to ocfs2_read_extent_block(). extent blocks belong to btrees on more than just inodes, so we want to pass the ocfs2_caching_info structure directly to ocfs2_read_extent_block(). A number of places in alloc.c can now drop struct inode from their argument list. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index a26294c..1ff13d3 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -854,13 +854,13 @@ static int ocfs2_validate_extent_block(struct super_block *sb, return 0; } -int ocfs2_read_extent_block(struct inode *inode, u64 eb_blkno, +int ocfs2_read_extent_block(struct ocfs2_caching_info *ci, u64 eb_blkno, struct buffer_head **bh) { int rc; struct buffer_head *tmp = *bh; - rc = ocfs2_read_block(INODE_CACHE(inode), eb_blkno, &tmp, + rc = ocfs2_read_block(ci, eb_blkno, &tmp, ocfs2_validate_extent_block); /* If ocfs2_read_block() got us a new bh, pass it up. */ @@ -875,7 +875,6 @@ int ocfs2_read_extent_block(struct inode *inode, u64 eb_blkno, * How many free extents have we got before we need more meta data? */ int ocfs2_num_free_extents(struct ocfs2_super *osb, - struct inode *inode, struct ocfs2_extent_tree *et) { int retval; @@ -890,7 +889,8 @@ int ocfs2_num_free_extents(struct ocfs2_super *osb, last_eb_blk = ocfs2_et_get_last_eb_blk(et); if (last_eb_blk) { - retval = ocfs2_read_extent_block(inode, last_eb_blk, &eb_bh); + retval = ocfs2_read_extent_block(et->et_ci, last_eb_blk, + &eb_bh); if (retval < 0) { mlog_errno(retval); goto bail; @@ -1382,7 +1382,6 @@ bail: * return status < 0 indicates an error. */ static int ocfs2_find_branch_target(struct ocfs2_super *osb, - struct inode *inode, struct ocfs2_extent_tree *et, struct buffer_head **target_bh) { @@ -1401,19 +1400,21 @@ static int ocfs2_find_branch_target(struct ocfs2_super *osb, while(le16_to_cpu(el->l_tree_depth) > 1) { if (le16_to_cpu(el->l_next_free_rec) == 0) { - ocfs2_error(inode->i_sb, "Dinode %llu has empty " + ocfs2_error(ocfs2_metadata_cache_get_super(et->et_ci), + "Owner %llu has empty " "extent list (next_free_rec == 0)", - (unsigned long long)OCFS2_I(inode)->ip_blkno); + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci)); status = -EIO; goto bail; } i = le16_to_cpu(el->l_next_free_rec) - 1; blkno = le64_to_cpu(el->l_recs[i].e_blkno); if (!blkno) { - ocfs2_error(inode->i_sb, "Dinode %llu has extent " + ocfs2_error(ocfs2_metadata_cache_get_super(et->et_ci), + "Owner %llu has extent " "list where extent # %d has no physical " "block start", - (unsigned long long)OCFS2_I(inode)->ip_blkno, i); + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci), i); status = -EIO; goto bail; } @@ -1421,7 +1422,7 @@ static int ocfs2_find_branch_target(struct ocfs2_super *osb, brelse(bh); bh = NULL; - status = ocfs2_read_extent_block(inode, blkno, &bh); + status = ocfs2_read_extent_block(et->et_ci, blkno, &bh); if (status < 0) { mlog_errno(status); goto bail; @@ -1475,7 +1476,7 @@ static int ocfs2_grow_tree(struct inode *inode, handle_t *handle, BUG_ON(meta_ac == NULL); - shift = ocfs2_find_branch_target(osb, inode, et, &bh); + shift = ocfs2_find_branch_target(osb, et, &bh); if (shift < 0) { ret = shift; mlog_errno(ret); @@ -1780,7 +1781,7 @@ static int __ocfs2_find_path(struct inode *inode, brelse(bh); bh = NULL; - ret = ocfs2_read_extent_block(inode, blkno, &bh); + ret = ocfs2_read_extent_block(INODE_CACHE(inode), blkno, &bh); if (ret) { mlog_errno(ret); goto out; @@ -3032,7 +3033,8 @@ static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_find_cpos_for_left_leaf(inode->i_sb, path, &cpos); + ret = ocfs2_find_cpos_for_left_leaf(ocfs2_metadata_cache_get_super(et->et_ci), + path, &cpos); if (ret) { mlog_errno(ret); goto out; @@ -4557,7 +4559,7 @@ static int ocfs2_figure_insert_type(struct inode *inode, * ocfs2_figure_insert_type() and ocfs2_add_branch() * may want it later. */ - ret = ocfs2_read_extent_block(inode, + ret = ocfs2_read_extent_block(et->et_ci, ocfs2_et_get_last_eb_blk(et), &bh); if (ret) { @@ -4760,7 +4762,7 @@ int ocfs2_add_clusters_in_btree(struct ocfs2_super *osb, if (mark_unwritten) flags = OCFS2_EXT_UNWRITTEN; - free_extents = ocfs2_num_free_extents(osb, inode, et); + free_extents = ocfs2_num_free_extents(osb, et); if (free_extents < 0) { status = free_extents; mlog_errno(status); @@ -5048,7 +5050,7 @@ static int __ocfs2_mark_extent_written(struct inode *inode, if (path->p_tree_depth) { struct ocfs2_extent_block *eb; - ret = ocfs2_read_extent_block(inode, + ret = ocfs2_read_extent_block(et->et_ci, ocfs2_et_get_last_eb_blk(et), &last_eb_bh); if (ret) { @@ -5203,7 +5205,7 @@ static int ocfs2_split_tree(struct inode *inode, struct ocfs2_extent_tree *et, depth = path->p_tree_depth; if (depth > 0) { - ret = ocfs2_read_extent_block(inode, + ret = ocfs2_read_extent_block(et->et_ci, ocfs2_et_get_last_eb_blk(et), &last_eb_bh); if (ret < 0) { @@ -7447,7 +7449,7 @@ int ocfs2_prepare_truncate(struct ocfs2_super *osb, ocfs2_init_dealloc_ctxt(&(*tc)->tc_dealloc); if (fe->id2.i_list.l_tree_depth) { - status = ocfs2_read_extent_block(inode, + status = ocfs2_read_extent_block(INODE_CACHE(inode), le64_to_cpu(fe->i_last_eb_blk), &last_eb_bh); if (status < 0) { diff --git a/fs/ocfs2/alloc.h b/fs/ocfs2/alloc.h index 285d40b..ed78ee5 100644 --- a/fs/ocfs2/alloc.h +++ b/fs/ocfs2/alloc.h @@ -86,7 +86,7 @@ void ocfs2_init_dx_root_extent_tree(struct ocfs2_extent_tree *et, * allocated. This is a cached read. The extent block will be validated * with ocfs2_validate_extent_block(). */ -int ocfs2_read_extent_block(struct inode *inode, u64 eb_blkno, +int ocfs2_read_extent_block(struct ocfs2_caching_info *ci, u64 eb_blkno, struct buffer_head **bh); struct ocfs2_alloc_context; @@ -132,7 +132,6 @@ int ocfs2_remove_btree_range(struct inode *inode, struct ocfs2_cached_dealloc_ctxt *dealloc); int ocfs2_num_free_extents(struct ocfs2_super *osb, - struct inode *inode, struct ocfs2_extent_tree *et); /* diff --git a/fs/ocfs2/dir.c b/fs/ocfs2/dir.c index 073ab34..00e4328 100644 --- a/fs/ocfs2/dir.c +++ b/fs/ocfs2/dir.c @@ -3346,7 +3346,7 @@ static int ocfs2_extend_dir(struct ocfs2_super *osb, if (dir_i_size == ocfs2_clusters_to_bytes(sb, OCFS2_I(dir)->ip_clusters)) { spin_unlock(&OCFS2_I(dir)->ip_lock); ocfs2_init_dinode_extent_tree(&et, dir, parent_fe_bh); - num_free_extents = ocfs2_num_free_extents(osb, dir, &et); + num_free_extents = ocfs2_num_free_extents(osb, &et); if (num_free_extents < 0) { status = num_free_extents; mlog_errno(status); diff --git a/fs/ocfs2/extent_map.c b/fs/ocfs2/extent_map.c index dbd8a16..a5dc13e 100644 --- a/fs/ocfs2/extent_map.c +++ b/fs/ocfs2/extent_map.c @@ -293,7 +293,7 @@ static int ocfs2_last_eb_is_empty(struct inode *inode, struct ocfs2_extent_block *eb; struct ocfs2_extent_list *el; - ret = ocfs2_read_extent_block(inode, last_eb_blk, &eb_bh); + ret = ocfs2_read_extent_block(INODE_CACHE(inode), last_eb_blk, &eb_bh); if (ret) { mlog_errno(ret); goto out; @@ -375,7 +375,7 @@ static int ocfs2_figure_hole_clusters(struct inode *inode, if (le64_to_cpu(eb->h_next_leaf_blk) == 0ULL) goto no_more_extents; - ret = ocfs2_read_extent_block(inode, + ret = ocfs2_read_extent_block(INODE_CACHE(inode), le64_to_cpu(eb->h_next_leaf_blk), &next_eb_bh); if (ret) { diff --git a/fs/ocfs2/suballoc.c b/fs/ocfs2/suballoc.c index a6c442c..c30b644 100644 --- a/fs/ocfs2/suballoc.c +++ b/fs/ocfs2/suballoc.c @@ -2152,7 +2152,7 @@ int ocfs2_lock_allocators(struct inode *inode, BUG_ON(clusters_to_add != 0 && data_ac == NULL); - num_free_extents = ocfs2_num_free_extents(osb, inode, et); + num_free_extents = ocfs2_num_free_extents(osb, et); if (num_free_extents < 0) { ret = num_free_extents; mlog_errno(ret); -- cgit v0.10.2 From facdb77f54f09a33baf6b649496f5dd1d7922a7e Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 18:08:48 -0800 Subject: ocfs2: ocfs2_find_path() only needs the caching info ocfs2_find_path and ocfs2_find_leaf() walk our btrees, reading extent blocks. They need struct ocfs2_caching_info for that, but not struct inode. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 1ff13d3..ecd9730 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -475,8 +475,8 @@ struct ocfs2_path { #define path_leaf_el(_path) ((_path)->p_node[(_path)->p_tree_depth].el) #define path_num_items(_path) ((_path)->p_tree_depth + 1) -static int ocfs2_find_path(struct inode *inode, struct ocfs2_path *path, - u32 cpos); +static int ocfs2_find_path(struct ocfs2_caching_info *ci, + struct ocfs2_path *path, u32 cpos); static void ocfs2_adjust_rightmost_records(struct inode *inode, handle_t *handle, struct ocfs2_path *path, @@ -1039,7 +1039,7 @@ static int ocfs2_adjust_rightmost_branch(handle_t *handle, return status; } - status = ocfs2_find_path(inode, path, UINT_MAX); + status = ocfs2_find_path(et->et_ci, path, UINT_MAX); if (status < 0) { mlog_errno(status); goto out; @@ -1728,7 +1728,7 @@ typedef void (path_insert_t)(void *, struct buffer_head *); * This code can be called with a cpos larger than the tree, in which * case it will return the rightmost path. */ -static int __ocfs2_find_path(struct inode *inode, +static int __ocfs2_find_path(struct ocfs2_caching_info *ci, struct ocfs2_extent_list *root_el, u32 cpos, path_insert_t *func, void *data) { @@ -1739,15 +1739,14 @@ static int __ocfs2_find_path(struct inode *inode, struct ocfs2_extent_block *eb; struct ocfs2_extent_list *el; struct ocfs2_extent_rec *rec; - struct ocfs2_inode_info *oi = OCFS2_I(inode); el = root_el; while (el->l_tree_depth) { if (le16_to_cpu(el->l_next_free_rec) == 0) { - ocfs2_error(inode->i_sb, - "Inode %llu has empty extent list at " + ocfs2_error(ocfs2_metadata_cache_get_super(ci), + "Owner %llu has empty extent list at " "depth %u\n", - (unsigned long long)oi->ip_blkno, + (unsigned long long)ocfs2_metadata_cache_owner(ci), le16_to_cpu(el->l_tree_depth)); ret = -EROFS; goto out; @@ -1770,10 +1769,10 @@ static int __ocfs2_find_path(struct inode *inode, blkno = le64_to_cpu(el->l_recs[i].e_blkno); if (blkno == 0) { - ocfs2_error(inode->i_sb, - "Inode %llu has bad blkno in extent list " + ocfs2_error(ocfs2_metadata_cache_get_super(ci), + "Owner %llu has bad blkno in extent list " "at depth %u (index %d)\n", - (unsigned long long)oi->ip_blkno, + (unsigned long long)ocfs2_metadata_cache_owner(ci), le16_to_cpu(el->l_tree_depth), i); ret = -EROFS; goto out; @@ -1781,7 +1780,7 @@ static int __ocfs2_find_path(struct inode *inode, brelse(bh); bh = NULL; - ret = ocfs2_read_extent_block(INODE_CACHE(inode), blkno, &bh); + ret = ocfs2_read_extent_block(ci, blkno, &bh); if (ret) { mlog_errno(ret); goto out; @@ -1792,10 +1791,10 @@ static int __ocfs2_find_path(struct inode *inode, if (le16_to_cpu(el->l_next_free_rec) > le16_to_cpu(el->l_count)) { - ocfs2_error(inode->i_sb, - "Inode %llu has bad count in extent list " + ocfs2_error(ocfs2_metadata_cache_get_super(ci), + "Owner %llu has bad count in extent list " "at block %llu (next free=%u, count=%u)\n", - (unsigned long long)oi->ip_blkno, + (unsigned long long)ocfs2_metadata_cache_owner(ci), (unsigned long long)bh->b_blocknr, le16_to_cpu(el->l_next_free_rec), le16_to_cpu(el->l_count)); @@ -1839,14 +1838,14 @@ static void find_path_ins(void *data, struct buffer_head *bh) ocfs2_path_insert_eb(fp->path, fp->index, bh); fp->index++; } -static int ocfs2_find_path(struct inode *inode, struct ocfs2_path *path, - u32 cpos) +static int ocfs2_find_path(struct ocfs2_caching_info *ci, + struct ocfs2_path *path, u32 cpos) { struct find_path_data data; data.index = 1; data.path = path; - return __ocfs2_find_path(inode, path_root_el(path), cpos, + return __ocfs2_find_path(ci, path_root_el(path), cpos, find_path_ins, &data); } @@ -1871,13 +1870,14 @@ static void find_leaf_ins(void *data, struct buffer_head *bh) * * This function doesn't handle non btree extent lists. */ -int ocfs2_find_leaf(struct inode *inode, struct ocfs2_extent_list *root_el, - u32 cpos, struct buffer_head **leaf_bh) +int ocfs2_find_leaf(struct ocfs2_caching_info *ci, + struct ocfs2_extent_list *root_el, u32 cpos, + struct buffer_head **leaf_bh) { int ret; struct buffer_head *bh = NULL; - ret = __ocfs2_find_path(inode, root_el, cpos, find_leaf_ins, &bh); + ret = __ocfs2_find_path(ci, root_el, cpos, find_leaf_ins, &bh); if (ret) { mlog_errno(ret); goto out; @@ -2382,7 +2382,7 @@ static int ocfs2_rotate_tree_right(struct inode *inode, mlog(0, "Rotating a tree: ins. cpos: %u, left path cpos: %u\n", insert_cpos, cpos); - ret = ocfs2_find_path(inode, left_path, cpos); + ret = ocfs2_find_path(INODE_CACHE(inode), left_path, cpos); if (ret) { mlog_errno(ret); goto out; @@ -2923,7 +2923,7 @@ static int __ocfs2_rotate_tree_left(struct inode *inode, } while (right_cpos) { - ret = ocfs2_find_path(inode, right_path, right_cpos); + ret = ocfs2_find_path(et->et_ci, right_path, right_cpos); if (ret) { mlog_errno(ret); goto out; @@ -3052,7 +3052,7 @@ static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_find_path(inode, left_path, cpos); + ret = ocfs2_find_path(et->et_ci, left_path, cpos); if (ret) { mlog_errno(ret); goto out; @@ -3297,7 +3297,7 @@ static int ocfs2_get_right_path(struct inode *inode, goto out; } - ret = ocfs2_find_path(inode, right_path, right_cpos); + ret = ocfs2_find_path(INODE_CACHE(inode), right_path, right_cpos); if (ret) { mlog_errno(ret); goto out; @@ -3466,7 +3466,7 @@ static int ocfs2_get_left_path(struct inode *inode, goto out; } - ret = ocfs2_find_path(inode, left_path, left_cpos); + ret = ocfs2_find_path(INODE_CACHE(inode), left_path, left_cpos); if (ret) { mlog_errno(ret); goto out; @@ -3996,7 +3996,8 @@ static int ocfs2_append_rec_to_path(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_find_path(inode, left_path, left_cpos); + ret = ocfs2_find_path(INODE_CACHE(inode), left_path, + left_cpos); if (ret) { mlog_errno(ret); goto out; @@ -4245,7 +4246,7 @@ static int ocfs2_do_insert_extent(struct inode *inode, cpos = UINT_MAX; } - ret = ocfs2_find_path(inode, right_path, cpos); + ret = ocfs2_find_path(et->et_ci, right_path, cpos); if (ret) { mlog_errno(ret); goto out; @@ -4342,7 +4343,8 @@ ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, if (!left_path) goto out; - status = ocfs2_find_path(inode, left_path, left_cpos); + status = ocfs2_find_path(INODE_CACHE(inode), + left_path, left_cpos); if (status) goto out; @@ -4398,7 +4400,7 @@ ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, if (!right_path) goto out; - status = ocfs2_find_path(inode, right_path, right_cpos); + status = ocfs2_find_path(INODE_CACHE(inode), right_path, right_cpos); if (status) goto out; @@ -4600,7 +4602,7 @@ static int ocfs2_figure_insert_type(struct inode *inode, * us the rightmost tree path. This is accounted for below in * the appending code. */ - ret = ocfs2_find_path(inode, path, le32_to_cpu(insert_rec->e_cpos)); + ret = ocfs2_find_path(et->et_ci, path, le32_to_cpu(insert_rec->e_cpos)); if (ret) { mlog_errno(ret); goto out; @@ -4950,7 +4952,7 @@ leftright: ocfs2_reinit_path(path, 1); cpos = le32_to_cpu(split_rec.e_cpos); - ret = ocfs2_find_path(inode, path, cpos); + ret = ocfs2_find_path(et->et_ci, path, cpos); if (ret) { mlog_errno(ret); goto out; @@ -5148,7 +5150,7 @@ int ocfs2_mark_extent_written(struct inode *inode, goto out; } - ret = ocfs2_find_path(inode, left_path, cpos); + ret = ocfs2_find_path(et->et_ci, left_path, cpos); if (ret) { mlog_errno(ret); goto out; @@ -5320,7 +5322,8 @@ static int ocfs2_truncate_rec(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_find_path(inode, left_path, left_cpos); + ret = ocfs2_find_path(et->et_ci, left_path, + left_cpos); if (ret) { mlog_errno(ret); goto out; @@ -5429,7 +5432,7 @@ int ocfs2_remove_extent(struct inode *inode, goto out; } - ret = ocfs2_find_path(inode, path, cpos); + ret = ocfs2_find_path(et->et_ci, path, cpos); if (ret) { mlog_errno(ret); goto out; @@ -5494,7 +5497,7 @@ int ocfs2_remove_extent(struct inode *inode, */ ocfs2_reinit_path(path, 1); - ret = ocfs2_find_path(inode, path, cpos); + ret = ocfs2_find_path(et->et_ci, path, cpos); if (ret) { mlog_errno(ret); goto out; @@ -6522,7 +6525,7 @@ static int ocfs2_find_new_last_ext_blk(struct inode *inode, goto out; } - ret = ocfs2_find_leaf(inode, path_root_el(path), cpos, &bh); + ret = ocfs2_find_leaf(INODE_CACHE(inode), path_root_el(path), cpos, &bh); if (ret) { mlog_errno(ret); goto out; @@ -7299,7 +7302,7 @@ start: /* * Truncate always works against the rightmost tree branch. */ - status = ocfs2_find_path(inode, path, UINT_MAX); + status = ocfs2_find_path(INODE_CACHE(inode), path, UINT_MAX); if (status) { mlog_errno(status); goto bail; diff --git a/fs/ocfs2/alloc.h b/fs/ocfs2/alloc.h index ed78ee5..8718e57 100644 --- a/fs/ocfs2/alloc.h +++ b/fs/ocfs2/alloc.h @@ -223,8 +223,9 @@ int ocfs2_commit_truncate(struct ocfs2_super *osb, int ocfs2_truncate_inline(struct inode *inode, struct buffer_head *di_bh, unsigned int start, unsigned int end, int trunc); -int ocfs2_find_leaf(struct inode *inode, struct ocfs2_extent_list *root_el, - u32 cpos, struct buffer_head **leaf_bh); +int ocfs2_find_leaf(struct ocfs2_caching_info *ci, + struct ocfs2_extent_list *root_el, u32 cpos, + struct buffer_head **leaf_bh); int ocfs2_search_extent_list(struct ocfs2_extent_list *el, u32 v_cluster); /* diff --git a/fs/ocfs2/dir.c b/fs/ocfs2/dir.c index 00e4328..088a1b5 100644 --- a/fs/ocfs2/dir.c +++ b/fs/ocfs2/dir.c @@ -805,7 +805,8 @@ static int ocfs2_dx_dir_lookup_rec(struct inode *inode, struct ocfs2_extent_rec *rec = NULL; if (el->l_tree_depth) { - ret = ocfs2_find_leaf(inode, el, major_hash, &eb_bh); + ret = ocfs2_find_leaf(INODE_CACHE(inode), el, major_hash, + &eb_bh); if (ret) { mlog_errno(ret); goto out; diff --git a/fs/ocfs2/extent_map.c b/fs/ocfs2/extent_map.c index a5dc13e..dc9482cb 100644 --- a/fs/ocfs2/extent_map.c +++ b/fs/ocfs2/extent_map.c @@ -428,7 +428,8 @@ static int ocfs2_get_clusters_nocache(struct inode *inode, tree_height = le16_to_cpu(el->l_tree_depth); if (tree_height > 0) { - ret = ocfs2_find_leaf(inode, el, v_cluster, &eb_bh); + ret = ocfs2_find_leaf(INODE_CACHE(inode), el, v_cluster, + &eb_bh); if (ret) { mlog_errno(ret); goto out; @@ -548,7 +549,8 @@ int ocfs2_xattr_get_clusters(struct inode *inode, u32 v_cluster, u32 coff; if (el->l_tree_depth) { - ret = ocfs2_find_leaf(inode, el, v_cluster, &eb_bh); + ret = ocfs2_find_leaf(INODE_CACHE(inode), el, v_cluster, + &eb_bh); if (ret) { mlog_errno(ret); goto out; diff --git a/fs/ocfs2/xattr.c b/fs/ocfs2/xattr.c index 93aae79..61819b2 100644 --- a/fs/ocfs2/xattr.c +++ b/fs/ocfs2/xattr.c @@ -2854,7 +2854,8 @@ static int ocfs2_xattr_get_rec(struct inode *inode, u64 e_blkno = 0; if (el->l_tree_depth) { - ret = ocfs2_find_leaf(inode, el, name_hash, &eb_bh); + ret = ocfs2_find_leaf(INODE_CACHE(inode), el, name_hash, + &eb_bh); if (ret) { mlog_errno(ret); goto out; -- cgit v0.10.2 From 42a5a7a9a5abf9a566b91c51137921957b9a14e4 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 18:49:19 -0800 Subject: ocfs2: ocfs2_create_new_meta_bhs() doesn't need struct inode. Pass struct ocfs2_extent_tree into ocfs2_create_new_meta_bhs(). It no longer needs struct inode or ocfs2_super. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index ecd9730..ad41eab 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -914,9 +914,8 @@ bail: * sets h_signature, h_blkno, h_suballoc_bit, h_suballoc_slot, and * l_count for you */ -static int ocfs2_create_new_meta_bhs(struct ocfs2_super *osb, - handle_t *handle, - struct inode *inode, +static int ocfs2_create_new_meta_bhs(handle_t *handle, + struct ocfs2_extent_tree *et, int wanted, struct ocfs2_alloc_context *meta_ac, struct buffer_head *bhs[]) @@ -925,6 +924,8 @@ static int ocfs2_create_new_meta_bhs(struct ocfs2_super *osb, u16 suballoc_bit_start; u32 num_got; u64 first_blkno; + struct ocfs2_super *osb = + OCFS2_SB(ocfs2_metadata_cache_get_super(et->et_ci)); struct ocfs2_extent_block *eb; mlog_entry_void(); @@ -950,10 +951,10 @@ static int ocfs2_create_new_meta_bhs(struct ocfs2_super *osb, mlog_errno(status); goto bail; } - ocfs2_set_new_buffer_uptodate(INODE_CACHE(inode), - bhs[i]); + ocfs2_set_new_buffer_uptodate(et->et_ci, bhs[i]); - status = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), bhs[i], + status = ocfs2_journal_access_eb(handle, et->et_ci, + bhs[i], OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -1141,7 +1142,7 @@ static int ocfs2_add_branch(struct ocfs2_super *osb, goto bail; } - status = ocfs2_create_new_meta_bhs(osb, handle, inode, new_blocks, + status = ocfs2_create_new_meta_bhs(handle, et, new_blocks, meta_ac, new_eb_bhs); if (status < 0) { mlog_errno(status); @@ -1292,7 +1293,7 @@ static int ocfs2_shift_tree_depth(struct ocfs2_super *osb, mlog_entry_void(); - status = ocfs2_create_new_meta_bhs(osb, handle, inode, 1, meta_ac, + status = ocfs2_create_new_meta_bhs(handle, et, 1, meta_ac, &new_eb_bh); if (status < 0) { mlog_errno(status); -- cgit v0.10.2 From 6641b0ce3274d979338cb67b2f562189dcbc1c28 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 18:57:52 -0800 Subject: ocfs2: Pass ocfs2_extent_tree to ocfs2_unlink_path() ocfs2_unlink_path() doesn't need struct inode, so let's pass it struct ocfs2_extent_tree. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index ad41eab..18762f5 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -2536,7 +2536,8 @@ out: return ret; } -static void ocfs2_unlink_path(struct inode *inode, handle_t *handle, +static void ocfs2_unlink_path(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_cached_dealloc_ctxt *dealloc, struct ocfs2_path *path, int unlink_start) { @@ -2558,12 +2559,12 @@ static void ocfs2_unlink_path(struct inode *inode, handle_t *handle, mlog(ML_ERROR, "Inode %llu, attempted to remove extent block " "%llu with %u records\n", - (unsigned long long)OCFS2_I(inode)->ip_blkno, + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci), (unsigned long long)le64_to_cpu(eb->h_blkno), le16_to_cpu(el->l_next_free_rec)); ocfs2_journal_dirty(handle, bh); - ocfs2_remove_from_cache(INODE_CACHE(inode), bh); + ocfs2_remove_from_cache(et->et_ci, bh); continue; } @@ -2576,11 +2577,12 @@ static void ocfs2_unlink_path(struct inode *inode, handle_t *handle, if (ret) mlog_errno(ret); - ocfs2_remove_from_cache(INODE_CACHE(inode), bh); + ocfs2_remove_from_cache(et->et_ci, bh); } } -static void ocfs2_unlink_subtree(struct inode *inode, handle_t *handle, +static void ocfs2_unlink_subtree(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_path *left_path, struct ocfs2_path *right_path, int subtree_index, @@ -2611,7 +2613,7 @@ static void ocfs2_unlink_subtree(struct inode *inode, handle_t *handle, ocfs2_journal_dirty(handle, root_bh); ocfs2_journal_dirty(handle, path_leaf_bh(left_path)); - ocfs2_unlink_path(inode, handle, dealloc, right_path, + ocfs2_unlink_path(handle, et, dealloc, right_path, subtree_index + 1); } @@ -2744,7 +2746,7 @@ static int ocfs2_rotate_subtree_left(struct inode *inode, handle_t *handle, mlog_errno(ret); if (del_right_subtree) { - ocfs2_unlink_subtree(inode, handle, left_path, right_path, + ocfs2_unlink_subtree(handle, et, left_path, right_path, subtree_index, dealloc); ret = ocfs2_update_edge_lengths(inode, handle, subtree_index, left_path); @@ -3067,7 +3069,7 @@ static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, subtree_index = ocfs2_find_subtree_root(inode, left_path, path); - ocfs2_unlink_subtree(inode, handle, left_path, path, + ocfs2_unlink_subtree(handle, et, left_path, path, subtree_index, dealloc); ret = ocfs2_update_edge_lengths(inode, handle, subtree_index, left_path); @@ -3086,7 +3088,7 @@ static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, * revert the inode back to having extents * in-line. */ - ocfs2_unlink_path(inode, handle, dealloc, path, 1); + ocfs2_unlink_path(handle, et, dealloc, path, 1); el = et->et_root_el; el->l_tree_depth = 0; -- cgit v0.10.2 From 4619c73e7c9bd10bac6b60925fa28d5a2eeaf6ed Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 19:02:36 -0800 Subject: ocfs2: ocfs2_complete_edge_insert() doesn't need struct inode at all. Completely unused argument. Get rid of it. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 18762f5..4a8e971 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -1984,7 +1984,7 @@ static void ocfs2_adjust_root_records(struct ocfs2_extent_list *root_el, * - When we've adjusted the last extent record in the left path leaf and the * 1st extent record in the right path leaf during cross extent block merge. */ -static void ocfs2_complete_edge_insert(struct inode *inode, handle_t *handle, +static void ocfs2_complete_edge_insert(handle_t *handle, struct ocfs2_path *left_path, struct ocfs2_path *right_path, int subtree_index) @@ -2161,8 +2161,8 @@ static int ocfs2_rotate_subtree_right(struct inode *inode, goto out; } - ocfs2_complete_edge_insert(inode, handle, left_path, right_path, - subtree_index); + ocfs2_complete_edge_insert(handle, left_path, right_path, + subtree_index); out: return ret; @@ -2772,7 +2772,7 @@ static int ocfs2_rotate_subtree_left(struct inode *inode, handle_t *handle, *deleted = 1; } else - ocfs2_complete_edge_insert(inode, handle, left_path, right_path, + ocfs2_complete_edge_insert(handle, left_path, right_path, subtree_index); out: @@ -3430,8 +3430,8 @@ static int ocfs2_merge_rec_right(struct inode *inode, if (ret) mlog_errno(ret); - ocfs2_complete_edge_insert(inode, handle, left_path, - right_path, subtree_index); + ocfs2_complete_edge_insert(handle, left_path, right_path, + subtree_index); } out: if (right_path) @@ -3629,7 +3629,7 @@ static int ocfs2_merge_rec_left(struct inode *inode, ocfs2_mv_path(right_path, left_path); left_path = NULL; } else - ocfs2_complete_edge_insert(inode, handle, left_path, + ocfs2_complete_edge_insert(handle, left_path, right_path, subtree_index); } out: @@ -4195,8 +4195,8 @@ static int ocfs2_insert_path(struct inode *inode, */ subtree_index = ocfs2_find_subtree_root(inode, left_path, right_path); - ocfs2_complete_edge_insert(inode, handle, left_path, - right_path, subtree_index); + ocfs2_complete_edge_insert(handle, left_path, right_path, + subtree_index); } ret = 0; @@ -5397,7 +5397,7 @@ static int ocfs2_truncate_rec(struct inode *inode, handle_t *handle, int subtree_index; subtree_index = ocfs2_find_subtree_root(inode, left_path, path); - ocfs2_complete_edge_insert(inode, handle, left_path, path, + ocfs2_complete_edge_insert(handle, left_path, path, subtree_index); } -- cgit v0.10.2 From 5c601aba8c5d9d5f944cf02b59e3288dd72ae6cf Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 19:10:13 -0800 Subject: ocfs2: Get inode out of ocfs2_rotate_subtree_root_right(). Pass the ocfs2_extent_list down through ocfs2_rotate_tree_right() and get rid of struct inode in ocfs2_rotate_subtree_root_right(). Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 4a8e971..7a04e17 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -2062,8 +2062,8 @@ static void ocfs2_complete_edge_insert(handle_t *handle, mlog_errno(ret); } -static int ocfs2_rotate_subtree_right(struct inode *inode, - handle_t *handle, +static int ocfs2_rotate_subtree_right(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_path *left_path, struct ocfs2_path *right_path, int subtree_index) @@ -2079,10 +2079,10 @@ static int ocfs2_rotate_subtree_right(struct inode *inode, left_el = path_leaf_el(left_path); if (left_el->l_next_free_rec != left_el->l_count) { - ocfs2_error(inode->i_sb, + ocfs2_error(ocfs2_metadata_cache_get_super(et->et_ci), "Inode %llu has non-full interior leaf node %llu" "(next free = %u)", - (unsigned long long)OCFS2_I(inode)->ip_blkno, + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci), (unsigned long long)left_leaf_bh->b_blocknr, le16_to_cpu(left_el->l_next_free_rec)); return -EROFS; @@ -2098,7 +2098,7 @@ static int ocfs2_rotate_subtree_right(struct inode *inode, root_bh = left_path->p_node[subtree_index].bh; BUG_ON(root_bh != right_path->p_node[subtree_index].bh); - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, right_path, subtree_index); if (ret) { mlog_errno(ret); @@ -2106,14 +2106,14 @@ static int ocfs2_rotate_subtree_right(struct inode *inode, } for(i = subtree_index + 1; i < path_num_items(right_path); i++) { - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, right_path, i); if (ret) { mlog_errno(ret); goto out; } - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, left_path, i); if (ret) { mlog_errno(ret); @@ -2127,7 +2127,7 @@ static int ocfs2_rotate_subtree_right(struct inode *inode, /* This is a code error, not a disk corruption. */ mlog_bug_on_msg(!right_el->l_next_free_rec, "Inode %llu: Rotate fails " "because rightmost leaf block %llu is empty\n", - (unsigned long long)OCFS2_I(inode)->ip_blkno, + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci), (unsigned long long)right_leaf_bh->b_blocknr); ocfs2_create_empty_extent(right_el); @@ -2325,8 +2325,8 @@ static int ocfs2_leftmost_rec_contains(struct ocfs2_extent_list *el, u32 cpos) * *ret_left_path will contain a valid path which can be passed to * ocfs2_insert_path(). */ -static int ocfs2_rotate_tree_right(struct inode *inode, - handle_t *handle, +static int ocfs2_rotate_tree_right(struct inode *inode, handle_t *handle, + struct ocfs2_extent_tree *et, enum ocfs2_split_type split, u32 insert_cpos, struct ocfs2_path *right_path, @@ -2335,6 +2335,7 @@ static int ocfs2_rotate_tree_right(struct inode *inode, int ret, start, orig_credits = handle->h_buffer_credits; u32 cpos; struct ocfs2_path *left_path = NULL; + struct super_block *sb = ocfs2_metadata_cache_get_super(et->et_ci); *ret_left_path = NULL; @@ -2345,7 +2346,7 @@ static int ocfs2_rotate_tree_right(struct inode *inode, goto out; } - ret = ocfs2_find_cpos_for_left_leaf(inode->i_sb, right_path, &cpos); + ret = ocfs2_find_cpos_for_left_leaf(sb, right_path, &cpos); if (ret) { mlog_errno(ret); goto out; @@ -2383,7 +2384,7 @@ static int ocfs2_rotate_tree_right(struct inode *inode, mlog(0, "Rotating a tree: ins. cpos: %u, left path cpos: %u\n", insert_cpos, cpos); - ret = ocfs2_find_path(INODE_CACHE(inode), left_path, cpos); + ret = ocfs2_find_path(et->et_ci, left_path, cpos); if (ret) { mlog_errno(ret); goto out; @@ -2391,10 +2392,11 @@ static int ocfs2_rotate_tree_right(struct inode *inode, mlog_bug_on_msg(path_leaf_bh(left_path) == path_leaf_bh(right_path), - "Inode %lu: error during insert of %u " + "Owner %llu: error during insert of %u " "(left path cpos %u) results in two identical " "paths ending at %llu\n", - inode->i_ino, insert_cpos, cpos, + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci), + insert_cpos, cpos, (unsigned long long) path_leaf_bh(left_path)->b_blocknr); @@ -2434,7 +2436,7 @@ static int ocfs2_rotate_tree_right(struct inode *inode, goto out; } - ret = ocfs2_rotate_subtree_right(inode, handle, left_path, + ret = ocfs2_rotate_subtree_right(handle, et, left_path, right_path, start); if (ret) { mlog_errno(ret); @@ -2466,8 +2468,7 @@ static int ocfs2_rotate_tree_right(struct inode *inode, */ ocfs2_mv_path(right_path, left_path); - ret = ocfs2_find_cpos_for_left_leaf(inode->i_sb, right_path, - &cpos); + ret = ocfs2_find_cpos_for_left_leaf(sb, right_path, &cpos); if (ret) { mlog_errno(ret); goto out; @@ -4268,7 +4269,7 @@ static int ocfs2_do_insert_extent(struct inode *inode, * can wind up skipping both of these two special cases... */ if (rotate) { - ret = ocfs2_rotate_tree_right(inode, handle, type->ins_split, + ret = ocfs2_rotate_tree_right(inode, handle, et, type->ins_split, le32_to_cpu(insert_rec->e_cpos), right_path, &left_path); if (ret) { -- cgit v0.10.2 From 7dc028056750328e74ca807041c822068384fe16 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 19:20:13 -0800 Subject: ocfs2: Pass ocfs2_extent_tree to ocfs2_get_subtree_root() Get rid of the inode argument. Use extent_tree instead. This means a few more functions have to pass an extent_tree around. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 7a04e17..c3edd02 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -1691,7 +1691,7 @@ set_and_inc: * * The array index of the subtree root is passed back. */ -static int ocfs2_find_subtree_root(struct inode *inode, +static int ocfs2_find_subtree_root(struct ocfs2_extent_tree *et, struct ocfs2_path *left, struct ocfs2_path *right) { @@ -1709,10 +1709,10 @@ static int ocfs2_find_subtree_root(struct inode *inode, * The caller didn't pass two adjacent paths. */ mlog_bug_on_msg(i > left->p_tree_depth, - "Inode %lu, left depth %u, right depth %u\n" + "Owner %llu, left depth %u, right depth %u\n" "left leaf blk %llu, right leaf blk %llu\n", - inode->i_ino, left->p_tree_depth, - right->p_tree_depth, + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci), + left->p_tree_depth, right->p_tree_depth, (unsigned long long)path_leaf_bh(left)->b_blocknr, (unsigned long long)path_leaf_bh(right)->b_blocknr); } while (left->p_node[i].bh->b_blocknr == @@ -2422,7 +2422,7 @@ static int ocfs2_rotate_tree_right(struct inode *inode, handle_t *handle, goto out_ret_path; } - start = ocfs2_find_subtree_root(inode, left_path, right_path); + start = ocfs2_find_subtree_root(et, left_path, right_path); mlog(0, "Subtree root at index %d (blk %llu, depth %d)\n", start, @@ -2933,7 +2933,7 @@ static int __ocfs2_rotate_tree_left(struct inode *inode, goto out; } - subtree_root = ocfs2_find_subtree_root(inode, left_path, + subtree_root = ocfs2_find_subtree_root(et, left_path, right_path); mlog(0, "Subtree root at index %d (blk %llu, depth %d)\n", @@ -3068,7 +3068,7 @@ static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, goto out; } - subtree_index = ocfs2_find_subtree_root(inode, left_path, path); + subtree_index = ocfs2_find_subtree_root(et, left_path, path); ocfs2_unlink_subtree(handle, et, left_path, path, subtree_index, dealloc); @@ -3324,6 +3324,7 @@ out: static int ocfs2_merge_rec_right(struct inode *inode, struct ocfs2_path *left_path, handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_extent_rec *split_rec, int index) { @@ -3363,8 +3364,8 @@ static int ocfs2_merge_rec_right(struct inode *inode, le16_to_cpu(left_rec->e_leaf_clusters) != le32_to_cpu(right_rec->e_cpos)); - subtree_index = ocfs2_find_subtree_root(inode, - left_path, right_path); + subtree_index = ocfs2_find_subtree_root(et, left_path, + right_path); ret = ocfs2_extend_rotate_transaction(handle, subtree_index, handle->h_buffer_credits, @@ -3377,7 +3378,7 @@ static int ocfs2_merge_rec_right(struct inode *inode, root_bh = left_path->p_node[subtree_index].bh; BUG_ON(root_bh != right_path->p_node[subtree_index].bh); - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, right_path, subtree_index); if (ret) { mlog_errno(ret); @@ -3386,14 +3387,14 @@ static int ocfs2_merge_rec_right(struct inode *inode, for (i = subtree_index + 1; i < path_num_items(right_path); i++) { - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, right_path, i); if (ret) { mlog_errno(ret); goto out; } - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, left_path, i); if (ret) { mlog_errno(ret); @@ -3406,7 +3407,7 @@ static int ocfs2_merge_rec_right(struct inode *inode, right_rec = &el->l_recs[index + 1]; } - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), left_path, + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, left_path, path_num_items(left_path) - 1); if (ret) { mlog_errno(ret); @@ -3417,7 +3418,8 @@ static int ocfs2_merge_rec_right(struct inode *inode, le32_add_cpu(&right_rec->e_cpos, -split_clusters); le64_add_cpu(&right_rec->e_blkno, - -ocfs2_clusters_to_blocks(inode->i_sb, split_clusters)); + -ocfs2_clusters_to_blocks(ocfs2_metadata_cache_get_super(et->et_ci), + split_clusters)); le16_add_cpu(&right_rec->e_leaf_clusters, split_clusters); ocfs2_cleanup_merge(el, index); @@ -3532,8 +3534,8 @@ static int ocfs2_merge_rec_left(struct inode *inode, le16_to_cpu(left_rec->e_leaf_clusters) != le32_to_cpu(split_rec->e_cpos)); - subtree_index = ocfs2_find_subtree_root(inode, - left_path, right_path); + subtree_index = ocfs2_find_subtree_root(et, left_path, + right_path); ret = ocfs2_extend_rotate_transaction(handle, subtree_index, handle->h_buffer_credits, @@ -3694,7 +3696,7 @@ static int ocfs2_try_to_merge_extent(struct inode *inode, * if we do merge_right first and merge_left later. */ ret = ocfs2_merge_rec_right(inode, path, - handle, split_rec, + handle, et, split_rec, split_index); if (ret) { mlog_errno(ret); @@ -3758,9 +3760,8 @@ static int ocfs2_try_to_merge_extent(struct inode *inode, goto out; } } else { - ret = ocfs2_merge_rec_right(inode, - path, - handle, split_rec, + ret = ocfs2_merge_rec_right(inode, path, handle, + et, split_rec, split_index); if (ret) { mlog_errno(ret); @@ -4118,6 +4119,7 @@ static void ocfs2_split_record(struct inode *inode, */ static int ocfs2_insert_path(struct inode *inode, handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_path *left_path, struct ocfs2_path *right_path, struct ocfs2_extent_rec *insert_rec, @@ -4143,7 +4145,7 @@ static int ocfs2_insert_path(struct inode *inode, goto out; } - ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, left_path); + ret = ocfs2_journal_access_path(et->et_ci, handle, left_path); if (ret < 0) { mlog_errno(ret); goto out; @@ -4154,7 +4156,7 @@ static int ocfs2_insert_path(struct inode *inode, * Pass both paths to the journal. The majority of inserts * will be touching all components anyway. */ - ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, right_path); + ret = ocfs2_journal_access_path(et->et_ci, handle, right_path); if (ret < 0) { mlog_errno(ret); goto out; @@ -4194,7 +4196,7 @@ static int ocfs2_insert_path(struct inode *inode, * * XXX: Should we extend the transaction here? */ - subtree_index = ocfs2_find_subtree_root(inode, left_path, + subtree_index = ocfs2_find_subtree_root(et, left_path, right_path); ocfs2_complete_edge_insert(handle, left_path, right_path, subtree_index); @@ -4297,7 +4299,7 @@ static int ocfs2_do_insert_extent(struct inode *inode, } } - ret = ocfs2_insert_path(inode, handle, left_path, right_path, + ret = ocfs2_insert_path(inode, handle, et, left_path, right_path, insert_rec, type); if (ret) { mlog_errno(ret); @@ -5397,7 +5399,7 @@ static int ocfs2_truncate_rec(struct inode *inode, handle_t *handle, if (left_path) { int subtree_index; - subtree_index = ocfs2_find_subtree_root(inode, left_path, path); + subtree_index = ocfs2_find_subtree_root(et, left_path, path); ocfs2_complete_edge_insert(handle, left_path, path, subtree_index); } -- cgit v0.10.2 From 6136ca5f5f9fd38da399e9ff9380f537c1b3b901 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 19:32:43 -0800 Subject: ocfs2: Drop struct inode from ocfs2_extent_tree_operations. We can get to the inode from the caching information. Other parent types don't need it. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index c3edd02..072f7fe 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -79,18 +79,16 @@ struct ocfs2_extent_tree_operations { * that value. new_clusters is the delta, and must be * added to the total. Required. */ - void (*eo_update_clusters)(struct inode *inode, - struct ocfs2_extent_tree *et, + void (*eo_update_clusters)(struct ocfs2_extent_tree *et, u32 new_clusters); /* * If ->eo_insert_check() exists, it is called before rec is * inserted into the extent tree. It is optional. */ - int (*eo_insert_check)(struct inode *inode, - struct ocfs2_extent_tree *et, + int (*eo_insert_check)(struct ocfs2_extent_tree *et, struct ocfs2_extent_rec *rec); - int (*eo_sanity_check)(struct inode *inode, struct ocfs2_extent_tree *et); + int (*eo_sanity_check)(struct ocfs2_extent_tree *et); /* * -------------------------------------------------------------- @@ -109,8 +107,7 @@ struct ocfs2_extent_tree_operations { * it exists. If it does not, et->et_max_leaf_clusters is set * to 0 (unlimited). Optional. */ - void (*eo_fill_max_leaf_clusters)(struct inode *inode, - struct ocfs2_extent_tree *et); + void (*eo_fill_max_leaf_clusters)(struct ocfs2_extent_tree *et); }; @@ -121,14 +118,11 @@ struct ocfs2_extent_tree_operations { static u64 ocfs2_dinode_get_last_eb_blk(struct ocfs2_extent_tree *et); static void ocfs2_dinode_set_last_eb_blk(struct ocfs2_extent_tree *et, u64 blkno); -static void ocfs2_dinode_update_clusters(struct inode *inode, - struct ocfs2_extent_tree *et, +static void ocfs2_dinode_update_clusters(struct ocfs2_extent_tree *et, u32 clusters); -static int ocfs2_dinode_insert_check(struct inode *inode, - struct ocfs2_extent_tree *et, +static int ocfs2_dinode_insert_check(struct ocfs2_extent_tree *et, struct ocfs2_extent_rec *rec); -static int ocfs2_dinode_sanity_check(struct inode *inode, - struct ocfs2_extent_tree *et); +static int ocfs2_dinode_sanity_check(struct ocfs2_extent_tree *et); static void ocfs2_dinode_fill_root_el(struct ocfs2_extent_tree *et); static struct ocfs2_extent_tree_operations ocfs2_dinode_et_ops = { .eo_set_last_eb_blk = ocfs2_dinode_set_last_eb_blk, @@ -156,40 +150,37 @@ static u64 ocfs2_dinode_get_last_eb_blk(struct ocfs2_extent_tree *et) return le64_to_cpu(di->i_last_eb_blk); } -static void ocfs2_dinode_update_clusters(struct inode *inode, - struct ocfs2_extent_tree *et, +static void ocfs2_dinode_update_clusters(struct ocfs2_extent_tree *et, u32 clusters) { + struct ocfs2_inode_info *oi = cache_info_to_inode(et->et_ci); struct ocfs2_dinode *di = et->et_object; le32_add_cpu(&di->i_clusters, clusters); - spin_lock(&OCFS2_I(inode)->ip_lock); - OCFS2_I(inode)->ip_clusters = le32_to_cpu(di->i_clusters); - spin_unlock(&OCFS2_I(inode)->ip_lock); + spin_lock(&oi->ip_lock); + oi->ip_clusters = le32_to_cpu(di->i_clusters); + spin_unlock(&oi->ip_lock); } -static int ocfs2_dinode_insert_check(struct inode *inode, - struct ocfs2_extent_tree *et, +static int ocfs2_dinode_insert_check(struct ocfs2_extent_tree *et, struct ocfs2_extent_rec *rec) { - struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); + struct ocfs2_inode_info *oi = cache_info_to_inode(et->et_ci); + struct ocfs2_super *osb = OCFS2_SB(oi->vfs_inode.i_sb); - BUG_ON(OCFS2_I(inode)->ip_dyn_features & OCFS2_INLINE_DATA_FL); + BUG_ON(oi->ip_dyn_features & OCFS2_INLINE_DATA_FL); mlog_bug_on_msg(!ocfs2_sparse_alloc(osb) && - (OCFS2_I(inode)->ip_clusters != - le32_to_cpu(rec->e_cpos)), + (oi->ip_clusters != le32_to_cpu(rec->e_cpos)), "Device %s, asking for sparse allocation: inode %llu, " "cpos %u, clusters %u\n", osb->dev_str, - (unsigned long long)OCFS2_I(inode)->ip_blkno, - rec->e_cpos, - OCFS2_I(inode)->ip_clusters); + (unsigned long long)oi->ip_blkno, + rec->e_cpos, oi->ip_clusters); return 0; } -static int ocfs2_dinode_sanity_check(struct inode *inode, - struct ocfs2_extent_tree *et) +static int ocfs2_dinode_sanity_check(struct ocfs2_extent_tree *et) { struct ocfs2_dinode *di = et->et_object; @@ -229,8 +220,7 @@ static u64 ocfs2_xattr_value_get_last_eb_blk(struct ocfs2_extent_tree *et) return le64_to_cpu(vb->vb_xv->xr_last_eb_blk); } -static void ocfs2_xattr_value_update_clusters(struct inode *inode, - struct ocfs2_extent_tree *et, +static void ocfs2_xattr_value_update_clusters(struct ocfs2_extent_tree *et, u32 clusters) { struct ocfs2_xattr_value_buf *vb = et->et_object; @@ -252,12 +242,11 @@ static void ocfs2_xattr_tree_fill_root_el(struct ocfs2_extent_tree *et) et->et_root_el = &xb->xb_attrs.xb_root.xt_list; } -static void ocfs2_xattr_tree_fill_max_leaf_clusters(struct inode *inode, - struct ocfs2_extent_tree *et) +static void ocfs2_xattr_tree_fill_max_leaf_clusters(struct ocfs2_extent_tree *et) { + struct super_block *sb = ocfs2_metadata_cache_get_super(et->et_ci); et->et_max_leaf_clusters = - ocfs2_clusters_for_bytes(inode->i_sb, - OCFS2_MAX_XATTR_TREE_LEAF_SIZE); + ocfs2_clusters_for_bytes(sb, OCFS2_MAX_XATTR_TREE_LEAF_SIZE); } static void ocfs2_xattr_tree_set_last_eb_blk(struct ocfs2_extent_tree *et, @@ -277,8 +266,7 @@ static u64 ocfs2_xattr_tree_get_last_eb_blk(struct ocfs2_extent_tree *et) return le64_to_cpu(xt->xt_last_eb_blk); } -static void ocfs2_xattr_tree_update_clusters(struct inode *inode, - struct ocfs2_extent_tree *et, +static void ocfs2_xattr_tree_update_clusters(struct ocfs2_extent_tree *et, u32 clusters) { struct ocfs2_xattr_block *xb = et->et_object; @@ -309,8 +297,7 @@ static u64 ocfs2_dx_root_get_last_eb_blk(struct ocfs2_extent_tree *et) return le64_to_cpu(dx_root->dr_last_eb_blk); } -static void ocfs2_dx_root_update_clusters(struct inode *inode, - struct ocfs2_extent_tree *et, +static void ocfs2_dx_root_update_clusters(struct ocfs2_extent_tree *et, u32 clusters) { struct ocfs2_dx_root_block *dx_root = et->et_object; @@ -318,8 +305,7 @@ static void ocfs2_dx_root_update_clusters(struct inode *inode, le32_add_cpu(&dx_root->dr_clusters, clusters); } -static int ocfs2_dx_root_sanity_check(struct inode *inode, - struct ocfs2_extent_tree *et) +static int ocfs2_dx_root_sanity_check(struct ocfs2_extent_tree *et) { struct ocfs2_dx_root_block *dx_root = et->et_object; @@ -362,7 +348,7 @@ static void __ocfs2_init_extent_tree(struct ocfs2_extent_tree *et, if (!et->et_ops->eo_fill_max_leaf_clusters) et->et_max_leaf_clusters = 0; else - et->et_ops->eo_fill_max_leaf_clusters(inode, et); + et->et_ops->eo_fill_max_leaf_clusters(et); } void ocfs2_init_dinode_extent_tree(struct ocfs2_extent_tree *et, @@ -408,11 +394,10 @@ static inline u64 ocfs2_et_get_last_eb_blk(struct ocfs2_extent_tree *et) return et->et_ops->eo_get_last_eb_blk(et); } -static inline void ocfs2_et_update_clusters(struct inode *inode, - struct ocfs2_extent_tree *et, +static inline void ocfs2_et_update_clusters(struct ocfs2_extent_tree *et, u32 clusters) { - et->et_ops->eo_update_clusters(inode, et, clusters); + et->et_ops->eo_update_clusters(et, clusters); } static inline int ocfs2_et_root_journal_access(handle_t *handle, @@ -423,24 +408,22 @@ static inline int ocfs2_et_root_journal_access(handle_t *handle, type); } -static inline int ocfs2_et_insert_check(struct inode *inode, - struct ocfs2_extent_tree *et, +static inline int ocfs2_et_insert_check(struct ocfs2_extent_tree *et, struct ocfs2_extent_rec *rec) { int ret = 0; if (et->et_ops->eo_insert_check) - ret = et->et_ops->eo_insert_check(inode, et, rec); + ret = et->et_ops->eo_insert_check(et, rec); return ret; } -static inline int ocfs2_et_sanity_check(struct inode *inode, - struct ocfs2_extent_tree *et) +static inline int ocfs2_et_sanity_check(struct ocfs2_extent_tree *et) { int ret = 0; if (et->et_ops->eo_sanity_check) - ret = et->et_ops->eo_sanity_check(inode, et); + ret = et->et_ops->eo_sanity_check(et); return ret; } @@ -3016,7 +2999,7 @@ static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, struct ocfs2_extent_list *el; - ret = ocfs2_et_sanity_check(inode, et); + ret = ocfs2_et_sanity_check(et); if (ret) goto out; /* @@ -4308,7 +4291,7 @@ static int ocfs2_do_insert_extent(struct inode *inode, out_update_clusters: if (type->ins_split == SPLIT_NONE) - ocfs2_et_update_clusters(inode, et, + ocfs2_et_update_clusters(et, le16_to_cpu(insert_rec->e_leaf_clusters)); ret = ocfs2_journal_dirty(handle, et->et_root_bh); @@ -4697,7 +4680,7 @@ int ocfs2_insert_extent(struct ocfs2_super *osb, rec.e_blkno = cpu_to_le64(start_blk); rec.e_leaf_clusters = cpu_to_le16(new_clusters); rec.e_flags = flags; - status = ocfs2_et_insert_check(inode, et, &rec); + status = ocfs2_et_insert_check(et, &rec); if (status) { mlog_errno(status); goto bail; @@ -5603,7 +5586,7 @@ int ocfs2_remove_btree_range(struct inode *inode, goto out_commit; } - ocfs2_et_update_clusters(inode, et, -len); + ocfs2_et_update_clusters(et, -len); ret = ocfs2_journal_dirty(handle, et->et_root_bh); if (ret) { diff --git a/fs/ocfs2/inode.c b/fs/ocfs2/inode.c index 179c819..e82ceb3 100644 --- a/fs/ocfs2/inode.c +++ b/fs/ocfs2/inode.c @@ -1395,10 +1395,6 @@ int ocfs2_read_inode_block(struct inode *inode, struct buffer_head **bh) return ocfs2_read_inode_block_full(inode, bh, 0); } -static struct ocfs2_inode_info *cache_info_to_inode(struct ocfs2_caching_info *ci) -{ - return container_of(ci, struct ocfs2_inode_info, ip_metadata_cache); -} static u64 ocfs2_inode_cache_owner(struct ocfs2_caching_info *ci) { diff --git a/fs/ocfs2/inode.h b/fs/ocfs2/inode.h index 67392f6..ba4fe07 100644 --- a/fs/ocfs2/inode.h +++ b/fs/ocfs2/inode.h @@ -170,4 +170,10 @@ int ocfs2_read_inode_block(struct inode *inode, struct buffer_head **bh); /* The same, but can be passed OCFS2_BH_* flags */ int ocfs2_read_inode_block_full(struct inode *inode, struct buffer_head **bh, int flags); + +static inline struct ocfs2_inode_info *cache_info_to_inode(struct ocfs2_caching_info *ci) +{ + return container_of(ci, struct ocfs2_inode_info, ip_metadata_cache); +} + #endif /* OCFS2_INODE_H */ -- cgit v0.10.2 From 1bbf0b8d606645c7596ee641acfbf042765c9719 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 19:42:08 -0800 Subject: ocfs2: ocfs2_rotate_tree_right() doesn't need struct inode. We don't need struct inode in ocfs2_rotate_tree_right() anymore. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 072f7fe..93f02a1 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -2308,7 +2308,7 @@ static int ocfs2_leftmost_rec_contains(struct ocfs2_extent_list *el, u32 cpos) * *ret_left_path will contain a valid path which can be passed to * ocfs2_insert_path(). */ -static int ocfs2_rotate_tree_right(struct inode *inode, handle_t *handle, +static int ocfs2_rotate_tree_right(handle_t *handle, struct ocfs2_extent_tree *et, enum ocfs2_split_type split, u32 insert_cpos, @@ -4254,7 +4254,7 @@ static int ocfs2_do_insert_extent(struct inode *inode, * can wind up skipping both of these two special cases... */ if (rotate) { - ret = ocfs2_rotate_tree_right(inode, handle, et, type->ins_split, + ret = ocfs2_rotate_tree_right(handle, et, type->ins_split, le32_to_cpu(insert_rec->e_cpos), right_path, &left_path); if (ret) { -- cgit v0.10.2 From 09106bae05c3350e8d0ef0ede90b1c3da4bda2f8 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 19:43:57 -0800 Subject: ocfs2: ocfs2_update_edge_lengths() doesn't need struct inode. Pass in the extent tree, which is all we need. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 93f02a1..8efcfac 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -2465,7 +2465,8 @@ out_ret_path: return ret; } -static int ocfs2_update_edge_lengths(struct inode *inode, handle_t *handle, +static int ocfs2_update_edge_lengths(handle_t *handle, + struct ocfs2_extent_tree *et, int subtree_index, struct ocfs2_path *path) { int i, idx, ret; @@ -2490,7 +2491,7 @@ static int ocfs2_update_edge_lengths(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, path); + ret = ocfs2_journal_access_path(et->et_ci, handle, path); if (ret) { mlog_errno(ret); goto out; @@ -2732,7 +2733,7 @@ static int ocfs2_rotate_subtree_left(struct inode *inode, handle_t *handle, if (del_right_subtree) { ocfs2_unlink_subtree(handle, et, left_path, right_path, subtree_index, dealloc); - ret = ocfs2_update_edge_lengths(inode, handle, subtree_index, + ret = ocfs2_update_edge_lengths(handle, et, subtree_index, left_path); if (ret) { mlog_errno(ret); @@ -3055,7 +3056,7 @@ static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, ocfs2_unlink_subtree(handle, et, left_path, path, subtree_index, dealloc); - ret = ocfs2_update_edge_lengths(inode, handle, subtree_index, + ret = ocfs2_update_edge_lengths(handle, et, subtree_index, left_path); if (ret) { mlog_errno(ret); -- cgit v0.10.2 From 1e2dd63fe0b6e99b81904a61090db801978b9520 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 19:45:28 -0800 Subject: ocfs2: ocfs2_rotate_subtree_left() doesn't need struct inode. It already has struct ocfs2_extent_tree, which has the caching info. So we don't need to pass it struct inode. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 8efcfac..b358d56 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -2602,13 +2602,13 @@ static void ocfs2_unlink_subtree(handle_t *handle, subtree_index + 1); } -static int ocfs2_rotate_subtree_left(struct inode *inode, handle_t *handle, +static int ocfs2_rotate_subtree_left(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_path *left_path, struct ocfs2_path *right_path, int subtree_index, struct ocfs2_cached_dealloc_ctxt *dealloc, - int *deleted, - struct ocfs2_extent_tree *et) + int *deleted) { int ret, i, del_right_subtree = 0, right_has_empty = 0; struct buffer_head *root_bh, *et_root_bh = path_root_bh(right_path); @@ -2644,7 +2644,7 @@ static int ocfs2_rotate_subtree_left(struct inode *inode, handle_t *handle, return -EAGAIN; if (le16_to_cpu(right_leaf_el->l_next_free_rec) > 1) { - ret = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), + ret = ocfs2_journal_access_eb(handle, et->et_ci, path_leaf_bh(right_path), OCFS2_JOURNAL_ACCESS_WRITE); if (ret) { @@ -2679,7 +2679,7 @@ static int ocfs2_rotate_subtree_left(struct inode *inode, handle_t *handle, */ BUG_ON(right_has_empty && !del_right_subtree); - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, right_path, subtree_index); if (ret) { mlog_errno(ret); @@ -2687,14 +2687,14 @@ static int ocfs2_rotate_subtree_left(struct inode *inode, handle_t *handle, } for(i = subtree_index + 1; i < path_num_items(right_path); i++) { - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, right_path, i); if (ret) { mlog_errno(ret); goto out; } - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, left_path, i); if (ret) { mlog_errno(ret); @@ -2944,9 +2944,9 @@ static int __ocfs2_rotate_tree_left(struct inode *inode, goto out; } - ret = ocfs2_rotate_subtree_left(inode, handle, left_path, + ret = ocfs2_rotate_subtree_left(handle, et, left_path, right_path, subtree_root, - dealloc, &deleted, et); + dealloc, &deleted); if (ret == -EAGAIN) { /* * The rotation has to temporarily stop due to -- cgit v0.10.2 From e46f74dc357947e2aed9bdd63cf335c5fd23810b Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Thu, 12 Feb 2009 19:47:43 -0800 Subject: ocfs2: __ocfs2_rotate_tree_left() doesn't need struct inode. It already has struct ocfs2_extent_tree, which has the caching info. So we don't need to pass it struct inode. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index b358d56..12dbd6e 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -2871,24 +2871,24 @@ out: return ret; } -static int __ocfs2_rotate_tree_left(struct inode *inode, - handle_t *handle, int orig_credits, +static int __ocfs2_rotate_tree_left(handle_t *handle, + struct ocfs2_extent_tree *et, + int orig_credits, struct ocfs2_path *path, struct ocfs2_cached_dealloc_ctxt *dealloc, - struct ocfs2_path **empty_extent_path, - struct ocfs2_extent_tree *et) + struct ocfs2_path **empty_extent_path) { int ret, subtree_root, deleted; u32 right_cpos; struct ocfs2_path *left_path = NULL; struct ocfs2_path *right_path = NULL; + struct super_block *sb = ocfs2_metadata_cache_get_super(et->et_ci); BUG_ON(!ocfs2_is_empty_extent(&(path_leaf_el(path)->l_recs[0]))); *empty_extent_path = NULL; - ret = ocfs2_find_cpos_for_right_leaf(inode->i_sb, path, - &right_cpos); + ret = ocfs2_find_cpos_for_right_leaf(sb, path, &right_cpos); if (ret) { mlog_errno(ret); goto out; @@ -2937,7 +2937,7 @@ static int __ocfs2_rotate_tree_left(struct inode *inode, * Caller might still want to make changes to the * tree root, so re-add it to the journal here. */ - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, left_path, 0); if (ret) { mlog_errno(ret); @@ -2973,7 +2973,7 @@ static int __ocfs2_rotate_tree_left(struct inode *inode, ocfs2_mv_path(left_path, right_path); - ret = ocfs2_find_cpos_for_right_leaf(inode->i_sb, left_path, + ret = ocfs2_find_cpos_for_right_leaf(sb, left_path, &right_cpos); if (ret) { mlog_errno(ret); @@ -3187,8 +3187,8 @@ rightmost_no_delete: * and restarting from there. */ try_rotate: - ret = __ocfs2_rotate_tree_left(inode, handle, orig_credits, path, - dealloc, &restart_path, et); + ret = __ocfs2_rotate_tree_left(handle, et, orig_credits, path, + dealloc, &restart_path); if (ret && ret != -EAGAIN) { mlog_errno(ret); goto out; @@ -3198,9 +3198,9 @@ try_rotate: tmp_path = restart_path; restart_path = NULL; - ret = __ocfs2_rotate_tree_left(inode, handle, orig_credits, + ret = __ocfs2_rotate_tree_left(handle, et, orig_credits, tmp_path, dealloc, - &restart_path, et); + &restart_path); if (ret && ret != -EAGAIN) { mlog_errno(ret); goto out; -- cgit v0.10.2 From 70f18c08b476e315c8ee17ea34b55ea1957e7e7d Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 02:09:31 -0800 Subject: ocfs2: ocfs2_rotate_tree_left() no longer needs struct inode. It already gets ocfs2_extent_tree, so we can just use that. This chains to the same modification for ocfs2_remove_rightmost_path() and ocfs2_rotate_rightmost_leaf_left(). Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 12dbd6e..d348cfb 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -2843,8 +2843,8 @@ out: return ret; } -static int ocfs2_rotate_rightmost_leaf_left(struct inode *inode, - handle_t *handle, +static int ocfs2_rotate_rightmost_leaf_left(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_path *path) { int ret; @@ -2854,7 +2854,7 @@ static int ocfs2_rotate_rightmost_leaf_left(struct inode *inode, if (!ocfs2_is_empty_extent(&el->l_recs[0])) return 0; - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), path, + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, path, path_num_items(path) - 1); if (ret) { mlog_errno(ret); @@ -2988,10 +2988,10 @@ out: return ret; } -static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, +static int ocfs2_remove_rightmost_path(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_path *path, - struct ocfs2_cached_dealloc_ctxt *dealloc, - struct ocfs2_extent_tree *et) + struct ocfs2_cached_dealloc_ctxt *dealloc) { int ret, subtree_index; u32 cpos; @@ -3070,7 +3070,7 @@ static int ocfs2_remove_rightmost_path(struct inode *inode, handle_t *handle, * 'path' is also the leftmost path which * means it must be the only one. This gets * handled differently because we want to - * revert the inode back to having extents + * revert the root back to having extents * in-line. */ ocfs2_unlink_path(handle, et, dealloc, path, 1); @@ -3106,10 +3106,10 @@ out: * the rightmost tree leaf record is removed so the caller is * responsible for detecting and correcting that. */ -static int ocfs2_rotate_tree_left(struct inode *inode, handle_t *handle, +static int ocfs2_rotate_tree_left(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_path *path, - struct ocfs2_cached_dealloc_ctxt *dealloc, - struct ocfs2_extent_tree *et) + struct ocfs2_cached_dealloc_ctxt *dealloc) { int ret, orig_credits = handle->h_buffer_credits; struct ocfs2_path *tmp_path = NULL, *restart_path = NULL; @@ -3126,8 +3126,7 @@ rightmost_no_delete: * Inline extents. This is trivially handled, so do * it up front. */ - ret = ocfs2_rotate_rightmost_leaf_left(inode, handle, - path); + ret = ocfs2_rotate_rightmost_leaf_left(handle, et, path); if (ret) mlog_errno(ret); goto out; @@ -3143,7 +3142,7 @@ rightmost_no_delete: * * 1) is handled via ocfs2_rotate_rightmost_leaf_left() * 2a) we need the left branch so that we can update it with the unlink - * 2b) we need to bring the inode back to inline extents. + * 2b) we need to bring the root back to inline extents. */ eb = (struct ocfs2_extent_block *)path_leaf_bh(path)->b_data; @@ -3159,9 +3158,9 @@ rightmost_no_delete: if (le16_to_cpu(el->l_next_free_rec) == 0) { ret = -EIO; - ocfs2_error(inode->i_sb, - "Inode %llu has empty extent block at %llu", - (unsigned long long)OCFS2_I(inode)->ip_blkno, + ocfs2_error(ocfs2_metadata_cache_get_super(et->et_ci), + "Owner %llu has empty extent block at %llu", + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci), (unsigned long long)le64_to_cpu(eb->h_blkno)); goto out; } @@ -3175,8 +3174,8 @@ rightmost_no_delete: * nonempty list. */ - ret = ocfs2_remove_rightmost_path(inode, handle, path, - dealloc, et); + ret = ocfs2_remove_rightmost_path(handle, et, path, + dealloc); if (ret) mlog_errno(ret); goto out; @@ -3602,9 +3601,9 @@ static int ocfs2_merge_rec_left(struct inode *inode, if (le16_to_cpu(right_rec->e_leaf_clusters) == 0 && le16_to_cpu(el->l_next_free_rec) == 1) { - ret = ocfs2_remove_rightmost_path(inode, handle, + ret = ocfs2_remove_rightmost_path(handle, et, right_path, - dealloc, et); + dealloc); if (ret) { mlog_errno(ret); goto out; @@ -3649,8 +3648,7 @@ static int ocfs2_try_to_merge_extent(struct inode *inode, * extents - having more than one in a leaf is * illegal. */ - ret = ocfs2_rotate_tree_left(inode, handle, path, - dealloc, et); + ret = ocfs2_rotate_tree_left(handle, et, path, dealloc); if (ret) { mlog_errno(ret); goto out; @@ -3693,8 +3691,7 @@ static int ocfs2_try_to_merge_extent(struct inode *inode, BUG_ON(!ocfs2_is_empty_extent(&el->l_recs[0])); /* The merge left us with an empty extent, remove it. */ - ret = ocfs2_rotate_tree_left(inode, handle, path, - dealloc, et); + ret = ocfs2_rotate_tree_left(handle, et, path, dealloc); if (ret) { mlog_errno(ret); goto out; @@ -3716,8 +3713,7 @@ static int ocfs2_try_to_merge_extent(struct inode *inode, goto out; } - ret = ocfs2_rotate_tree_left(inode, handle, path, - dealloc, et); + ret = ocfs2_rotate_tree_left(handle, et, path, dealloc); /* * Error from this last rotate is not critical, so * print but don't bubble it up. @@ -3758,8 +3754,8 @@ static int ocfs2_try_to_merge_extent(struct inode *inode, * The merge may have left an empty extent in * our leaf. Try to rotate it away. */ - ret = ocfs2_rotate_tree_left(inode, handle, path, - dealloc, et); + ret = ocfs2_rotate_tree_left(handle, et, path, + dealloc); if (ret) mlog_errno(ret); ret = 0; @@ -5259,7 +5255,7 @@ static int ocfs2_truncate_rec(struct inode *inode, handle_t *handle, struct ocfs2_extent_block *eb; if (ocfs2_is_empty_extent(&el->l_recs[0]) && index > 0) { - ret = ocfs2_rotate_tree_left(inode, handle, path, dealloc, et); + ret = ocfs2_rotate_tree_left(handle, et, path, dealloc); if (ret) { mlog_errno(ret); goto out; @@ -5390,7 +5386,7 @@ static int ocfs2_truncate_rec(struct inode *inode, handle_t *handle, ocfs2_journal_dirty(handle, path_leaf_bh(path)); - ret = ocfs2_rotate_tree_left(inode, handle, path, dealloc, et); + ret = ocfs2_rotate_tree_left(handle, et, path, dealloc); if (ret) { mlog_errno(ret); goto out; -- cgit v0.10.2 From 4fe82c312a7d975a9d0f591dc9180c1197ee4270 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 02:16:08 -0800 Subject: ocfs2: ocfs2_merge_rec_left/right() no longer need struct inode. Drop it from the parameters - they already have ocfs2_extent_list. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index d348cfb..bac6ca0 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -3250,7 +3250,7 @@ static void ocfs2_cleanup_merge(struct ocfs2_extent_list *el, } } -static int ocfs2_get_right_path(struct inode *inode, +static int ocfs2_get_right_path(struct ocfs2_extent_tree *et, struct ocfs2_path *left_path, struct ocfs2_path **ret_right_path) { @@ -3267,8 +3267,8 @@ static int ocfs2_get_right_path(struct inode *inode, left_el = path_leaf_el(left_path); BUG_ON(left_el->l_next_free_rec != left_el->l_count); - ret = ocfs2_find_cpos_for_right_leaf(inode->i_sb, left_path, - &right_cpos); + ret = ocfs2_find_cpos_for_right_leaf(ocfs2_metadata_cache_get_super(et->et_ci), + left_path, &right_cpos); if (ret) { mlog_errno(ret); goto out; @@ -3284,7 +3284,7 @@ static int ocfs2_get_right_path(struct inode *inode, goto out; } - ret = ocfs2_find_path(INODE_CACHE(inode), right_path, right_cpos); + ret = ocfs2_find_path(et->et_ci, right_path, right_cpos); if (ret) { mlog_errno(ret); goto out; @@ -3304,8 +3304,7 @@ out: * For index == l_count - 1, the "next" means the 1st extent rec of the * next extent block. */ -static int ocfs2_merge_rec_right(struct inode *inode, - struct ocfs2_path *left_path, +static int ocfs2_merge_rec_right(struct ocfs2_path *left_path, handle_t *handle, struct ocfs2_extent_tree *et, struct ocfs2_extent_rec *split_rec, @@ -3328,7 +3327,7 @@ static int ocfs2_merge_rec_right(struct inode *inode, if (index == le16_to_cpu(el->l_next_free_rec) - 1 && le16_to_cpu(el->l_next_free_rec) == le16_to_cpu(el->l_count)) { /* we meet with a cross extent block merge. */ - ret = ocfs2_get_right_path(inode, left_path, &right_path); + ret = ocfs2_get_right_path(et, left_path, &right_path); if (ret) { mlog_errno(ret); goto out; @@ -3425,7 +3424,7 @@ out: return ret; } -static int ocfs2_get_left_path(struct inode *inode, +static int ocfs2_get_left_path(struct ocfs2_extent_tree *et, struct ocfs2_path *right_path, struct ocfs2_path **ret_left_path) { @@ -3438,7 +3437,7 @@ static int ocfs2_get_left_path(struct inode *inode, /* This function shouldn't be called for non-trees. */ BUG_ON(right_path->p_tree_depth == 0); - ret = ocfs2_find_cpos_for_left_leaf(inode->i_sb, + ret = ocfs2_find_cpos_for_left_leaf(ocfs2_metadata_cache_get_super(et->et_ci), right_path, &left_cpos); if (ret) { mlog_errno(ret); @@ -3455,7 +3454,7 @@ static int ocfs2_get_left_path(struct inode *inode, goto out; } - ret = ocfs2_find_path(INODE_CACHE(inode), left_path, left_cpos); + ret = ocfs2_find_path(et->et_ci, left_path, left_cpos); if (ret) { mlog_errno(ret); goto out; @@ -3478,12 +3477,11 @@ out: * remove the rightmost leaf extent block in the right_path and change * the right path to indicate the new rightmost path. */ -static int ocfs2_merge_rec_left(struct inode *inode, - struct ocfs2_path *right_path, +static int ocfs2_merge_rec_left(struct ocfs2_path *right_path, handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_extent_rec *split_rec, struct ocfs2_cached_dealloc_ctxt *dealloc, - struct ocfs2_extent_tree *et, int index) { int ret, i, subtree_index = 0, has_empty_extent = 0; @@ -3501,7 +3499,7 @@ static int ocfs2_merge_rec_left(struct inode *inode, right_rec = &el->l_recs[index]; if (index == 0) { /* we meet with a cross extent block merge. */ - ret = ocfs2_get_left_path(inode, right_path, &left_path); + ret = ocfs2_get_left_path(et, right_path, &left_path); if (ret) { mlog_errno(ret); goto out; @@ -3531,7 +3529,7 @@ static int ocfs2_merge_rec_left(struct inode *inode, root_bh = left_path->p_node[subtree_index].bh; BUG_ON(root_bh != right_path->p_node[subtree_index].bh); - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, right_path, subtree_index); if (ret) { mlog_errno(ret); @@ -3540,14 +3538,14 @@ static int ocfs2_merge_rec_left(struct inode *inode, for (i = subtree_index + 1; i < path_num_items(right_path); i++) { - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, right_path, i); if (ret) { mlog_errno(ret); goto out; } - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, left_path, i); if (ret) { mlog_errno(ret); @@ -3560,7 +3558,7 @@ static int ocfs2_merge_rec_left(struct inode *inode, has_empty_extent = 1; } - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), right_path, + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, right_path, path_num_items(right_path) - 1); if (ret) { mlog_errno(ret); @@ -3579,7 +3577,8 @@ static int ocfs2_merge_rec_left(struct inode *inode, le32_add_cpu(&right_rec->e_cpos, split_clusters); le64_add_cpu(&right_rec->e_blkno, - ocfs2_clusters_to_blocks(inode->i_sb, split_clusters)); + ocfs2_clusters_to_blocks(ocfs2_metadata_cache_get_super(et->et_ci), + split_clusters)); le16_add_cpu(&right_rec->e_leaf_clusters, -split_clusters); ocfs2_cleanup_merge(el, index); @@ -3677,8 +3676,7 @@ static int ocfs2_try_to_merge_extent(struct inode *inode, * prevoius extent block. It is more efficient and easier * if we do merge_right first and merge_left later. */ - ret = ocfs2_merge_rec_right(inode, path, - handle, et, split_rec, + ret = ocfs2_merge_rec_right(path, handle, et, split_rec, split_index); if (ret) { mlog_errno(ret); @@ -3703,10 +3701,8 @@ static int ocfs2_try_to_merge_extent(struct inode *inode, * Note that we don't pass split_rec here on purpose - * we've merged it into the rec already. */ - ret = ocfs2_merge_rec_left(inode, path, - handle, rec, - dealloc, et, - split_index); + ret = ocfs2_merge_rec_left(path, handle, et, rec, + dealloc, split_index); if (ret) { mlog_errno(ret); @@ -3730,17 +3726,15 @@ static int ocfs2_try_to_merge_extent(struct inode *inode, * the record on the left (hence the left merge). */ if (ctxt->c_contig_type == CONTIG_RIGHT) { - ret = ocfs2_merge_rec_left(inode, - path, - handle, split_rec, - dealloc, et, + ret = ocfs2_merge_rec_left(path, handle, et, + split_rec, dealloc, split_index); if (ret) { mlog_errno(ret); goto out; } } else { - ret = ocfs2_merge_rec_right(inode, path, handle, + ret = ocfs2_merge_rec_right(path, handle, et, split_rec, split_index); if (ret) { -- cgit v0.10.2 From c495dd24ac00654f99540f533185e1fcc9534009 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 02:19:11 -0800 Subject: ocfs2: ocfs2_try_to_merge_extent() doesn't need struct inode. It's not using it, so remove it from the parameter list. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index bac6ca0..2c4967f7b 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -3623,15 +3623,13 @@ out: return ret; } -static int ocfs2_try_to_merge_extent(struct inode *inode, - handle_t *handle, +static int ocfs2_try_to_merge_extent(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_path *path, int split_index, struct ocfs2_extent_rec *split_rec, struct ocfs2_cached_dealloc_ctxt *dealloc, - struct ocfs2_merge_ctxt *ctxt, - struct ocfs2_extent_tree *et) - + struct ocfs2_merge_ctxt *ctxt) { int ret = 0; struct ocfs2_extent_list *el = path_leaf_el(path); @@ -5069,9 +5067,9 @@ static int __ocfs2_mark_extent_written(struct inode *inode, if (ret) mlog_errno(ret); } else { - ret = ocfs2_try_to_merge_extent(inode, handle, path, + ret = ocfs2_try_to_merge_extent(handle, et, path, split_index, split_rec, - dealloc, &ctxt, et); + dealloc, &ctxt); if (ret) mlog_errno(ret); } -- cgit v0.10.2 From d401dc12fcced123909eba10334fb5d78866d1a9 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 02:24:10 -0800 Subject: ocfs2: ocfs2_grow_branch() and ocfs2_append_rec_to_path() lose struct inode. ocfs2_grow_branch() not really using it other than to pass it to the subfunctions ocfs2_shift_tree_depth(), ocfs2_find_branch_target(), and ocfs2_add_branch(). The first two weren't it either, so they drop the argument. ocfs2_add_branch() only passed it to ocfs2_adjust_rightmost_branch(), which drops the inode argument and uses the ocfs2_extent_tree as well. ocfs2_append_rec_to_path() can be take an ocfs2_extent_tree instead of the inode. The function ocfs2_adjust_rightmost_records() goes along for the ride. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 2c4967f7b..e1479fa 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -460,8 +460,8 @@ struct ocfs2_path { static int ocfs2_find_path(struct ocfs2_caching_info *ci, struct ocfs2_path *path, u32 cpos); -static void ocfs2_adjust_rightmost_records(struct inode *inode, - handle_t *handle, +static void ocfs2_adjust_rightmost_records(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_path *path, struct ocfs2_extent_rec *insert_rec); /* @@ -1009,7 +1009,6 @@ static inline u32 ocfs2_sum_rightmost_rec(struct ocfs2_extent_list *el) * extent block's rightmost record. */ static int ocfs2_adjust_rightmost_branch(handle_t *handle, - struct inode *inode, struct ocfs2_extent_tree *et) { int status; @@ -1036,7 +1035,7 @@ static int ocfs2_adjust_rightmost_branch(handle_t *handle, goto out; } - status = ocfs2_journal_access_path(INODE_CACHE(inode), handle, path); + status = ocfs2_journal_access_path(et->et_ci, handle, path); if (status < 0) { mlog_errno(status); goto out; @@ -1045,7 +1044,7 @@ static int ocfs2_adjust_rightmost_branch(handle_t *handle, el = path_leaf_el(path); rec = &el->l_recs[le32_to_cpu(el->l_next_free_rec) - 1]; - ocfs2_adjust_rightmost_records(inode, handle, path, rec); + ocfs2_adjust_rightmost_records(handle, et, path, rec); out: ocfs2_free_path(path); @@ -1054,7 +1053,7 @@ out: /* * Add an entire tree branch to our inode. eb_bh is the extent block - * to start at, if we don't want to start the branch at the dinode + * to start at, if we don't want to start the branch at the root * structure. * * last_eb_bh is required as we have to update it's next_leaf pointer @@ -1063,9 +1062,7 @@ out: * the new branch will be 'empty' in the sense that every block will * contain a single record with cluster count == 0. */ -static int ocfs2_add_branch(struct ocfs2_super *osb, - handle_t *handle, - struct inode *inode, +static int ocfs2_add_branch(handle_t *handle, struct ocfs2_extent_tree *et, struct buffer_head *eb_bh, struct buffer_head **last_eb_bh, @@ -1109,7 +1106,7 @@ static int ocfs2_add_branch(struct ocfs2_super *osb, if (root_end > new_cpos) { mlog(0, "adjust the cluster end from %u to %u\n", root_end, new_cpos); - status = ocfs2_adjust_rightmost_branch(handle, inode, et); + status = ocfs2_adjust_rightmost_branch(handle, et); if (status) { mlog_errno(status); goto bail; @@ -1147,7 +1144,7 @@ static int ocfs2_add_branch(struct ocfs2_super *osb, BUG_ON(!OCFS2_IS_VALID_EXTENT_BLOCK(eb)); eb_el = &eb->h_list; - status = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), bh, + status = ocfs2_journal_access_eb(handle, et->et_ci, bh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -1187,7 +1184,7 @@ static int ocfs2_add_branch(struct ocfs2_super *osb, * journal_dirty erroring as it won't unless we've aborted the * handle (in which case we would never be here) so reserving * the write with journal_access is all we need to do. */ - status = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), *last_eb_bh, + status = ocfs2_journal_access_eb(handle, et->et_ci, *last_eb_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -1200,7 +1197,7 @@ static int ocfs2_add_branch(struct ocfs2_super *osb, goto bail; } if (eb_bh) { - status = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), eb_bh, + status = ocfs2_journal_access_eb(handle, et->et_ci, eb_bh, OCFS2_JOURNAL_ACCESS_WRITE); if (status < 0) { mlog_errno(status); @@ -1260,9 +1257,7 @@ bail: * returns back the new extent block so you can add a branch to it * after this call. */ -static int ocfs2_shift_tree_depth(struct ocfs2_super *osb, - handle_t *handle, - struct inode *inode, +static int ocfs2_shift_tree_depth(handle_t *handle, struct ocfs2_extent_tree *et, struct ocfs2_alloc_context *meta_ac, struct buffer_head **ret_new_eb_bh) @@ -1290,7 +1285,7 @@ static int ocfs2_shift_tree_depth(struct ocfs2_super *osb, eb_el = &eb->h_list; root_el = et->et_root_el; - status = ocfs2_journal_access_eb(handle, INODE_CACHE(inode), new_eb_bh, + status = ocfs2_journal_access_eb(handle, et->et_ci, new_eb_bh, OCFS2_JOURNAL_ACCESS_CREATE); if (status < 0) { mlog_errno(status); @@ -1365,8 +1360,7 @@ bail: * * return status < 0 indicates an error. */ -static int ocfs2_find_branch_target(struct ocfs2_super *osb, - struct ocfs2_extent_tree *et, +static int ocfs2_find_branch_target(struct ocfs2_extent_tree *et, struct buffer_head **target_bh) { int status = 0, i; @@ -1447,20 +1441,18 @@ bail: * * *last_eb_bh will be updated by ocfs2_add_branch(). */ -static int ocfs2_grow_tree(struct inode *inode, handle_t *handle, - struct ocfs2_extent_tree *et, int *final_depth, - struct buffer_head **last_eb_bh, +static int ocfs2_grow_tree(handle_t *handle, struct ocfs2_extent_tree *et, + int *final_depth, struct buffer_head **last_eb_bh, struct ocfs2_alloc_context *meta_ac) { int ret, shift; struct ocfs2_extent_list *el = et->et_root_el; int depth = le16_to_cpu(el->l_tree_depth); - struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); struct buffer_head *bh = NULL; BUG_ON(meta_ac == NULL); - shift = ocfs2_find_branch_target(osb, et, &bh); + shift = ocfs2_find_branch_target(et, &bh); if (shift < 0) { ret = shift; mlog_errno(ret); @@ -1477,8 +1469,7 @@ static int ocfs2_grow_tree(struct inode *inode, handle_t *handle, /* ocfs2_shift_tree_depth will return us a buffer with * the new extent block (so we can pass that to * ocfs2_add_branch). */ - ret = ocfs2_shift_tree_depth(osb, handle, inode, et, - meta_ac, &bh); + ret = ocfs2_shift_tree_depth(handle, et, meta_ac, &bh); if (ret < 0) { mlog_errno(ret); goto out; @@ -1504,7 +1495,7 @@ static int ocfs2_grow_tree(struct inode *inode, handle_t *handle, /* call ocfs2_add_branch to add the final part of the tree with * the new data. */ mlog(0, "add branch. bh = %p\n", bh); - ret = ocfs2_add_branch(osb, handle, inode, et, bh, last_eb_bh, + ret = ocfs2_add_branch(handle, et, bh, last_eb_bh, meta_ac); if (ret < 0) { mlog_errno(ret); @@ -3881,8 +3872,8 @@ rotate: ocfs2_rotate_leaf(el, insert_rec); } -static void ocfs2_adjust_rightmost_records(struct inode *inode, - handle_t *handle, +static void ocfs2_adjust_rightmost_records(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_path *path, struct ocfs2_extent_rec *insert_rec) { @@ -3900,9 +3891,9 @@ static void ocfs2_adjust_rightmost_records(struct inode *inode, next_free = le16_to_cpu(el->l_next_free_rec); if (next_free == 0) { - ocfs2_error(inode->i_sb, - "Dinode %llu has a bad extent list", - (unsigned long long)OCFS2_I(inode)->ip_blkno); + ocfs2_error(ocfs2_metadata_cache_get_super(et->et_ci), + "Owner %llu has a bad extent list", + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci)); ret = -EIO; return; } @@ -3922,7 +3913,8 @@ static void ocfs2_adjust_rightmost_records(struct inode *inode, } } -static int ocfs2_append_rec_to_path(struct inode *inode, handle_t *handle, +static int ocfs2_append_rec_to_path(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_extent_rec *insert_rec, struct ocfs2_path *right_path, struct ocfs2_path **ret_left_path) @@ -3950,8 +3942,8 @@ static int ocfs2_append_rec_to_path(struct inode *inode, handle_t *handle, (next_free == 1 && ocfs2_is_empty_extent(&el->l_recs[0]))) { u32 left_cpos; - ret = ocfs2_find_cpos_for_left_leaf(inode->i_sb, right_path, - &left_cpos); + ret = ocfs2_find_cpos_for_left_leaf(ocfs2_metadata_cache_get_super(et->et_ci), + right_path, &left_cpos); if (ret) { mlog_errno(ret); goto out; @@ -3973,7 +3965,7 @@ static int ocfs2_append_rec_to_path(struct inode *inode, handle_t *handle, goto out; } - ret = ocfs2_find_path(INODE_CACHE(inode), left_path, + ret = ocfs2_find_path(et->et_ci, left_path, left_cpos); if (ret) { mlog_errno(ret); @@ -3987,13 +3979,13 @@ static int ocfs2_append_rec_to_path(struct inode *inode, handle_t *handle, } } - ret = ocfs2_journal_access_path(INODE_CACHE(inode), handle, right_path); + ret = ocfs2_journal_access_path(et->et_ci, handle, right_path); if (ret) { mlog_errno(ret); goto out; } - ocfs2_adjust_rightmost_records(inode, handle, right_path, insert_rec); + ocfs2_adjust_rightmost_records(handle, et, right_path, insert_rec); *ret_left_path = left_path; ret = 0; @@ -4263,7 +4255,7 @@ static int ocfs2_do_insert_extent(struct inode *inode, } } else if (type->ins_appending == APPEND_TAIL && type->ins_contig != CONTIG_LEFT) { - ret = ocfs2_append_rec_to_path(inode, handle, insert_rec, + ret = ocfs2_append_rec_to_path(handle, et, insert_rec, right_path, &left_path); if (ret) { mlog_errno(ret); @@ -4689,7 +4681,7 @@ int ocfs2_insert_extent(struct ocfs2_super *osb, free_records, insert.ins_tree_depth); if (insert.ins_contig == CONTIG_NONE && free_records == 0) { - status = ocfs2_grow_tree(inode, handle, et, + status = ocfs2_grow_tree(handle, et, &insert.ins_tree_depth, &last_eb_bh, meta_ac); if (status) { @@ -4876,7 +4868,7 @@ leftright: if (le16_to_cpu(rightmost_el->l_next_free_rec) == le16_to_cpu(rightmost_el->l_count)) { - ret = ocfs2_grow_tree(inode, handle, et, + ret = ocfs2_grow_tree(handle, et, &depth, last_eb_bh, meta_ac); if (ret) { mlog_errno(ret); @@ -5208,7 +5200,7 @@ static int ocfs2_split_tree(struct inode *inode, struct ocfs2_extent_tree *et, if (le16_to_cpu(rightmost_el->l_next_free_rec) == le16_to_cpu(rightmost_el->l_count)) { - ret = ocfs2_grow_tree(inode, handle, et, &depth, &last_eb_bh, + ret = ocfs2_grow_tree(handle, et, &depth, &last_eb_bh, meta_ac); if (ret) { mlog_errno(ret); @@ -5346,7 +5338,7 @@ static int ocfs2_truncate_rec(struct inode *inode, handle_t *handle, * be deleted by the rotate code. */ rec = &el->l_recs[next_free - 1]; - ocfs2_adjust_rightmost_records(inode, handle, path, + ocfs2_adjust_rightmost_records(handle, et, path, rec); } } else if (le32_to_cpu(rec->e_cpos) == cpos) { @@ -5358,7 +5350,7 @@ static int ocfs2_truncate_rec(struct inode *inode, handle_t *handle, /* Remove rightmost portion of the record */ le16_add_cpu(&rec->e_leaf_clusters, -len); if (is_rightmost_tree_rec) - ocfs2_adjust_rightmost_records(inode, handle, path, rec); + ocfs2_adjust_rightmost_records(handle, et, path, rec); } else { /* Caller should have trapped this. */ mlog(ML_ERROR, "Inode %llu: Invalid record truncate: (%u, %u) " -- cgit v0.10.2 From 043beebb6c467a07ccd7aa666095f87fade1c28e Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 02:42:30 -0800 Subject: ocfs2: ocfs2_truncate_rec() doesn't need struct inode. It's not using it anymore. Remove it from the parameter list. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index e1479fa..4022fa4 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -5223,16 +5223,16 @@ out: return ret; } -static int ocfs2_truncate_rec(struct inode *inode, handle_t *handle, +static int ocfs2_truncate_rec(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_path *path, int index, struct ocfs2_cached_dealloc_ctxt *dealloc, - u32 cpos, u32 len, - struct ocfs2_extent_tree *et) + u32 cpos, u32 len) { int ret; u32 left_cpos, rec_range, trunc_range; int wants_rotate = 0, is_rightmost_tree_rec = 0; - struct super_block *sb = inode->i_sb; + struct super_block *sb = ocfs2_metadata_cache_get_super(et->et_ci); struct ocfs2_path *left_path = NULL; struct ocfs2_extent_list *el = path_leaf_el(path); struct ocfs2_extent_rec *rec; @@ -5271,14 +5271,13 @@ static int ocfs2_truncate_rec(struct inode *inode, handle_t *handle, * by this leaf and the one to it's left. * * There are two cases we can skip: - * 1) Path is the leftmost one in our inode tree. + * 1) Path is the leftmost one in our btree. * 2) The leaf is rightmost and will be empty after * we remove the extent record - the rotate code * knows how to update the newly formed edge. */ - ret = ocfs2_find_cpos_for_left_leaf(inode->i_sb, path, - &left_cpos); + ret = ocfs2_find_cpos_for_left_leaf(sb, path, &left_cpos); if (ret) { mlog_errno(ret); goto out; @@ -5353,8 +5352,9 @@ static int ocfs2_truncate_rec(struct inode *inode, handle_t *handle, ocfs2_adjust_rightmost_records(handle, et, path, rec); } else { /* Caller should have trapped this. */ - mlog(ML_ERROR, "Inode %llu: Invalid record truncate: (%u, %u) " - "(%u, %u)\n", (unsigned long long)OCFS2_I(inode)->ip_blkno, + mlog(ML_ERROR, "Owner %llu: Invalid record truncate: (%u, %u) " + "(%u, %u)\n", + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci), le32_to_cpu(rec->e_cpos), le16_to_cpu(rec->e_leaf_clusters), cpos, len); BUG(); @@ -5447,8 +5447,8 @@ int ocfs2_remove_extent(struct inode *inode, le32_to_cpu(rec->e_cpos), ocfs2_rec_clusters(el, rec)); if (le32_to_cpu(rec->e_cpos) == cpos || rec_range == trunc_range) { - ret = ocfs2_truncate_rec(inode, handle, path, index, dealloc, - cpos, len, et); + ret = ocfs2_truncate_rec(handle, et, path, index, dealloc, + cpos, len); if (ret) { mlog_errno(ret); goto out; @@ -5502,8 +5502,8 @@ int ocfs2_remove_extent(struct inode *inode, goto out; } - ret = ocfs2_truncate_rec(inode, handle, path, index, dealloc, - cpos, len, et); + ret = ocfs2_truncate_rec(handle, et, path, index, dealloc, + cpos, len); if (ret) { mlog_errno(ret); goto out; -- cgit v0.10.2 From 4c911eefca316f580f174940cd67d561b4b7e6e8 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 02:50:12 -0800 Subject: ocfs2: Make truncating the extent map an extent_tree_operation. ocfs2_remove_extent() wants to truncate the extent map if it's truncating an inode data extent. But since many btrees can call that function, let's make it an op on ocfs2_extent_tree. Other tree types can leave it empty. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 4022fa4..cdf9697 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -83,6 +83,13 @@ struct ocfs2_extent_tree_operations { u32 new_clusters); /* + * If this extent tree is supported by an extent map, truncate the + * map to clusters, + */ + void (*eo_extent_map_truncate)(struct ocfs2_extent_tree *et, + u32 clusters); + + /* * If ->eo_insert_check() exists, it is called before rec is * inserted into the extent tree. It is optional. */ @@ -120,6 +127,8 @@ static void ocfs2_dinode_set_last_eb_blk(struct ocfs2_extent_tree *et, u64 blkno); static void ocfs2_dinode_update_clusters(struct ocfs2_extent_tree *et, u32 clusters); +static void ocfs2_dinode_extent_map_truncate(struct ocfs2_extent_tree *et, + u32 clusters); static int ocfs2_dinode_insert_check(struct ocfs2_extent_tree *et, struct ocfs2_extent_rec *rec); static int ocfs2_dinode_sanity_check(struct ocfs2_extent_tree *et); @@ -128,6 +137,7 @@ static struct ocfs2_extent_tree_operations ocfs2_dinode_et_ops = { .eo_set_last_eb_blk = ocfs2_dinode_set_last_eb_blk, .eo_get_last_eb_blk = ocfs2_dinode_get_last_eb_blk, .eo_update_clusters = ocfs2_dinode_update_clusters, + .eo_extent_map_truncate = ocfs2_dinode_extent_map_truncate, .eo_insert_check = ocfs2_dinode_insert_check, .eo_sanity_check = ocfs2_dinode_sanity_check, .eo_fill_root_el = ocfs2_dinode_fill_root_el, @@ -162,6 +172,14 @@ static void ocfs2_dinode_update_clusters(struct ocfs2_extent_tree *et, spin_unlock(&oi->ip_lock); } +static void ocfs2_dinode_extent_map_truncate(struct ocfs2_extent_tree *et, + u32 clusters) +{ + struct inode *inode = &cache_info_to_inode(et->et_ci)->vfs_inode; + + ocfs2_extent_map_trunc(inode, clusters); +} + static int ocfs2_dinode_insert_check(struct ocfs2_extent_tree *et, struct ocfs2_extent_rec *rec) { @@ -400,6 +418,13 @@ static inline void ocfs2_et_update_clusters(struct ocfs2_extent_tree *et, et->et_ops->eo_update_clusters(et, clusters); } +static inline void ocfs2_et_extent_map_truncate(struct ocfs2_extent_tree *et, + u32 clusters) +{ + if (et->et_ops->eo_extent_map_truncate) + et->et_ops->eo_extent_map_truncate(et, clusters); +} + static inline int ocfs2_et_root_journal_access(handle_t *handle, struct ocfs2_extent_tree *et, int type) @@ -5106,12 +5131,8 @@ int ocfs2_mark_extent_written(struct inode *inode, /* * XXX: This should be fixed up so that we just re-insert the * next extent records. - * - * XXX: This is a hack on the extent tree, maybe it should be - * an op? */ - if (et->et_ops == &ocfs2_dinode_et_ops) - ocfs2_extent_map_trunc(inode, 0); + ocfs2_et_extent_map_truncate(et, 0); left_path = ocfs2_new_path_from_et(et); if (!left_path) { @@ -5393,7 +5414,11 @@ int ocfs2_remove_extent(struct inode *inode, struct ocfs2_extent_list *el; struct ocfs2_path *path = NULL; - ocfs2_extent_map_trunc(inode, 0); + /* + * XXX: Why are we truncating to 0 instead of wherever this + * affects us? + */ + ocfs2_et_extent_map_truncate(et, 0); path = ocfs2_new_path_from_et(et); if (!path) { -- cgit v0.10.2 From d562862314a7b131a630f7b912490312387542fb Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 02:54:36 -0800 Subject: ocfs2: ocfs2_insert_at_leaf() doesn't need struct inode. Give it an ocfs2_extent_tree and it is happy. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index cdf9697..ec9c2ce 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -3809,10 +3809,10 @@ static void ocfs2_subtract_from_rec(struct super_block *sb, * list. If this leaf is part of an allocation tree, it is assumed * that the tree above has been prepared. */ -static void ocfs2_insert_at_leaf(struct ocfs2_extent_rec *insert_rec, +static void ocfs2_insert_at_leaf(struct ocfs2_extent_tree *et, + struct ocfs2_extent_rec *insert_rec, struct ocfs2_extent_list *el, - struct ocfs2_insert_type *insert, - struct inode *inode) + struct ocfs2_insert_type *insert) { int i = insert->ins_contig_index; unsigned int range; @@ -3824,7 +3824,8 @@ static void ocfs2_insert_at_leaf(struct ocfs2_extent_rec *insert_rec, i = ocfs2_search_extent_list(el, le32_to_cpu(insert_rec->e_cpos)); BUG_ON(i == -1); rec = &el->l_recs[i]; - ocfs2_subtract_from_rec(inode->i_sb, insert->ins_split, rec, + ocfs2_subtract_from_rec(ocfs2_metadata_cache_get_super(et->et_ci), + insert->ins_split, rec, insert_rec); goto rotate; } @@ -3866,10 +3867,10 @@ static void ocfs2_insert_at_leaf(struct ocfs2_extent_rec *insert_rec, mlog_bug_on_msg(le16_to_cpu(el->l_next_free_rec) >= le16_to_cpu(el->l_count), - "inode %lu, depth %u, count %u, next free %u, " + "owner %llu, depth %u, count %u, next free %u, " "rec.cpos %u, rec.clusters %u, " "insert.cpos %u, insert.clusters %u\n", - inode->i_ino, + ocfs2_metadata_cache_owner(et->et_ci), le16_to_cpu(el->l_tree_depth), le16_to_cpu(el->l_count), le16_to_cpu(el->l_next_free_rec), @@ -4171,8 +4172,8 @@ static int ocfs2_insert_path(struct inode *inode, if (ret) mlog_errno(ret); } else - ocfs2_insert_at_leaf(insert_rec, path_leaf_el(right_path), - insert, inode); + ocfs2_insert_at_leaf(et, insert_rec, path_leaf_el(right_path), + insert); ret = ocfs2_journal_dirty(handle, leaf_bh); if (ret) @@ -4218,7 +4219,7 @@ static int ocfs2_do_insert_extent(struct inode *inode, } if (le16_to_cpu(el->l_tree_depth) == 0) { - ocfs2_insert_at_leaf(insert_rec, el, type, inode); + ocfs2_insert_at_leaf(et, insert_rec, el, type); goto out_update_clusters; } -- cgit v0.10.2 From c38e52bb1c0187186bd3c4a2b318ffe69cd2fdf8 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 02:56:23 -0800 Subject: ocfs2: Give ocfs2_split_record() an extent_tree instead of an inode. Another on the way to generic btree functions. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index ec9c2ce..b57f976 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -4022,7 +4022,7 @@ out: return ret; } -static void ocfs2_split_record(struct inode *inode, +static void ocfs2_split_record(struct ocfs2_extent_tree *et, struct ocfs2_path *left_path, struct ocfs2_path *right_path, struct ocfs2_extent_rec *split_rec, @@ -4095,7 +4095,8 @@ static void ocfs2_split_record(struct inode *inode, } rec = &el->l_recs[index]; - ocfs2_subtract_from_rec(inode->i_sb, split, rec, split_rec); + ocfs2_subtract_from_rec(ocfs2_metadata_cache_get_super(et->et_ci), + split, rec, split_rec); ocfs2_rotate_leaf(insert_el, split_rec); } @@ -4158,7 +4159,7 @@ static int ocfs2_insert_path(struct inode *inode, * of splits, but it's easier to just let one separate * function sort it all out. */ - ocfs2_split_record(inode, left_path, right_path, + ocfs2_split_record(et, left_path, right_path, insert_rec, insert->ins_split); /* -- cgit v0.10.2 From 3505bec01829a8f690259517add55c7941a4d3d5 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 02:57:58 -0800 Subject: ocfs2: ocfs2_do_insert_extent() and ocfs2_insert_path() no longer need an inode. They aren't using it, so remove it from their parameter lists. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index b57f976..cced176 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -4108,8 +4108,7 @@ static void ocfs2_split_record(struct ocfs2_extent_tree *et, * in. left_path should only be passed in if we need to update that * portion of the tree after an edge insert. */ -static int ocfs2_insert_path(struct inode *inode, - handle_t *handle, +static int ocfs2_insert_path(handle_t *handle, struct ocfs2_extent_tree *et, struct ocfs2_path *left_path, struct ocfs2_path *right_path, @@ -4198,8 +4197,7 @@ out: return ret; } -static int ocfs2_do_insert_extent(struct inode *inode, - handle_t *handle, +static int ocfs2_do_insert_extent(handle_t *handle, struct ocfs2_extent_tree *et, struct ocfs2_extent_rec *insert_rec, struct ocfs2_insert_type *type) @@ -4290,7 +4288,7 @@ static int ocfs2_do_insert_extent(struct inode *inode, } } - ret = ocfs2_insert_path(inode, handle, et, left_path, right_path, + ret = ocfs2_insert_path(handle, et, left_path, right_path, insert_rec, type); if (ret) { mlog_errno(ret); @@ -4718,7 +4716,7 @@ int ocfs2_insert_extent(struct ocfs2_super *osb, } /* Finally, we can add clusters. This might rotate the tree for us. */ - status = ocfs2_do_insert_extent(inode, handle, et, &rec, &insert); + status = ocfs2_do_insert_extent(handle, et, &rec, &insert); if (status < 0) mlog_errno(status); else if (et->et_ops == &ocfs2_dinode_et_ops) @@ -4933,7 +4931,7 @@ leftright: do_leftright = 1; } - ret = ocfs2_do_insert_extent(inode, handle, et, &split_rec, &insert); + ret = ocfs2_do_insert_extent(handle, et, &split_rec, &insert); if (ret) { mlog_errno(ret); goto out; @@ -5237,7 +5235,7 @@ static int ocfs2_split_tree(struct inode *inode, struct ocfs2_extent_tree *et, insert.ins_split = SPLIT_RIGHT; insert.ins_tree_depth = depth; - ret = ocfs2_do_insert_extent(inode, handle, et, &split_rec, &insert); + ret = ocfs2_do_insert_extent(handle, et, &split_rec, &insert); if (ret) mlog_errno(ret); -- cgit v0.10.2 From b4a176515c715f0c6db1759a39cd9c4175e5a23a Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 03:07:09 -0800 Subject: ocfs2: ocfs2_extent_contig() only requires the superblock. Don't pass the inode in. We don't want it around for generic btree operations. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index cced176..2431bbb 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -747,7 +747,7 @@ static int ocfs2_extents_adjacent(struct ocfs2_extent_rec *left, } static enum ocfs2_contig_type - ocfs2_extent_contig(struct inode *inode, + ocfs2_extent_contig(struct super_block *sb, struct ocfs2_extent_rec *ext, struct ocfs2_extent_rec *insert_rec) { @@ -762,12 +762,12 @@ static enum ocfs2_contig_type return CONTIG_NONE; if (ocfs2_extents_adjacent(ext, insert_rec) && - ocfs2_block_extent_contig(inode->i_sb, ext, blkno)) + ocfs2_block_extent_contig(sb, ext, blkno)) return CONTIG_RIGHT; blkno = le64_to_cpu(ext->e_blkno); if (ocfs2_extents_adjacent(insert_rec, ext) && - ocfs2_block_extent_contig(inode->i_sb, insert_rec, blkno)) + ocfs2_block_extent_contig(sb, insert_rec, blkno)) return CONTIG_LEFT; return CONTIG_NONE; @@ -4374,7 +4374,7 @@ ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, if (split_rec->e_cpos == el->l_recs[index].e_cpos) ret = CONTIG_RIGHT; } else { - ret = ocfs2_extent_contig(inode, rec, split_rec); + ret = ocfs2_extent_contig(inode->i_sb, rec, split_rec); } } @@ -4420,7 +4420,7 @@ ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, if (rec) { enum ocfs2_contig_type contig_type; - contig_type = ocfs2_extent_contig(inode, rec, split_rec); + contig_type = ocfs2_extent_contig(inode->i_sb, rec, split_rec); if (contig_type == CONTIG_LEFT && ret == CONTIG_RIGHT) ret = CONTIG_LEFTRIGHT; @@ -4449,7 +4449,7 @@ static void ocfs2_figure_contig_type(struct inode *inode, BUG_ON(le16_to_cpu(el->l_tree_depth) != 0); for(i = 0; i < le16_to_cpu(el->l_next_free_rec); i++) { - contig_type = ocfs2_extent_contig(inode, &el->l_recs[i], + contig_type = ocfs2_extent_contig(inode->i_sb, &el->l_recs[i], insert_rec); if (contig_type != CONTIG_NONE) { insert->ins_contig_index = i; -- cgit v0.10.2 From a29702914ad36443d83b5250b3bfa1bf91e6b239 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 03:09:54 -0800 Subject: ocfs2: Swap inode for extent_tree in ocfs2_figure_merge_contig_type(). We don't want struct inode in generic btree operations. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 2431bbb..9b79150 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -4312,7 +4312,8 @@ out: } static enum ocfs2_contig_type -ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, +ocfs2_figure_merge_contig_type(struct ocfs2_extent_tree *et, + struct ocfs2_path *path, struct ocfs2_extent_list *el, int index, struct ocfs2_extent_rec *split_rec) { @@ -4324,12 +4325,12 @@ ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, struct ocfs2_path *left_path = NULL, *right_path = NULL; struct buffer_head *bh; struct ocfs2_extent_block *eb; + struct super_block *sb = ocfs2_metadata_cache_get_super(et->et_ci); if (index > 0) { rec = &el->l_recs[index - 1]; } else if (path->p_tree_depth > 0) { - status = ocfs2_find_cpos_for_left_leaf(inode->i_sb, - path, &left_cpos); + status = ocfs2_find_cpos_for_left_leaf(sb, path, &left_cpos); if (status) goto out; @@ -4338,8 +4339,8 @@ ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, if (!left_path) goto out; - status = ocfs2_find_path(INODE_CACHE(inode), - left_path, left_cpos); + status = ocfs2_find_path(et->et_ci, left_path, + left_cpos); if (status) goto out; @@ -4349,7 +4350,7 @@ ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, le16_to_cpu(new_el->l_count)) { bh = path_leaf_bh(left_path); eb = (struct ocfs2_extent_block *)bh->b_data; - ocfs2_error(inode->i_sb, + ocfs2_error(sb, "Extent block #%llu has an " "invalid l_next_free_rec of " "%d. It should have " @@ -4374,7 +4375,7 @@ ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, if (split_rec->e_cpos == el->l_recs[index].e_cpos) ret = CONTIG_RIGHT; } else { - ret = ocfs2_extent_contig(inode->i_sb, rec, split_rec); + ret = ocfs2_extent_contig(sb, rec, split_rec); } } @@ -4383,8 +4384,7 @@ ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, rec = &el->l_recs[index + 1]; else if (le16_to_cpu(el->l_next_free_rec) == le16_to_cpu(el->l_count) && path->p_tree_depth > 0) { - status = ocfs2_find_cpos_for_right_leaf(inode->i_sb, - path, &right_cpos); + status = ocfs2_find_cpos_for_right_leaf(sb, path, &right_cpos); if (status) goto out; @@ -4395,7 +4395,7 @@ ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, if (!right_path) goto out; - status = ocfs2_find_path(INODE_CACHE(inode), right_path, right_cpos); + status = ocfs2_find_path(et->et_ci, right_path, right_cpos); if (status) goto out; @@ -4405,7 +4405,7 @@ ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, if (le16_to_cpu(new_el->l_next_free_rec) <= 1) { bh = path_leaf_bh(right_path); eb = (struct ocfs2_extent_block *)bh->b_data; - ocfs2_error(inode->i_sb, + ocfs2_error(sb, "Extent block #%llu has an " "invalid l_next_free_rec of %d", (unsigned long long)le64_to_cpu(eb->h_blkno), @@ -4420,7 +4420,7 @@ ocfs2_figure_merge_contig_type(struct inode *inode, struct ocfs2_path *path, if (rec) { enum ocfs2_contig_type contig_type; - contig_type = ocfs2_extent_contig(inode->i_sb, rec, split_rec); + contig_type = ocfs2_extent_contig(sb, rec, split_rec); if (contig_type == CONTIG_LEFT && ret == CONTIG_RIGHT) ret = CONTIG_LEFTRIGHT; @@ -5035,7 +5035,7 @@ static int __ocfs2_mark_extent_written(struct inode *inode, goto out; } - ctxt.c_contig_type = ocfs2_figure_merge_contig_type(inode, path, el, + ctxt.c_contig_type = ocfs2_figure_merge_contig_type(et, path, el, split_index, split_rec); -- cgit v0.10.2 From 1ef61b33148a6b32b6d28383cd72ceeddfc7054d Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 03:12:33 -0800 Subject: ocfs2: Remove inode from ocfs2_figure_extent_contig(). It already has an ocfs2_extent_tree and doesn't need the inode. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 9b79150..38b1fea 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -4437,11 +4437,10 @@ out: return ret; } -static void ocfs2_figure_contig_type(struct inode *inode, +static void ocfs2_figure_contig_type(struct ocfs2_extent_tree *et, struct ocfs2_insert_type *insert, struct ocfs2_extent_list *el, - struct ocfs2_extent_rec *insert_rec, - struct ocfs2_extent_tree *et) + struct ocfs2_extent_rec *insert_rec) { int i; enum ocfs2_contig_type contig_type = CONTIG_NONE; @@ -4449,8 +4448,8 @@ static void ocfs2_figure_contig_type(struct inode *inode, BUG_ON(le16_to_cpu(el->l_tree_depth) != 0); for(i = 0; i < le16_to_cpu(el->l_next_free_rec); i++) { - contig_type = ocfs2_extent_contig(inode->i_sb, &el->l_recs[i], - insert_rec); + contig_type = ocfs2_extent_contig(ocfs2_metadata_cache_get_super(et->et_ci), + &el->l_recs[i], insert_rec); if (contig_type != CONTIG_NONE) { insert->ins_contig_index = i; break; @@ -4579,7 +4578,7 @@ static int ocfs2_figure_insert_type(struct inode *inode, le16_to_cpu(el->l_next_free_rec); if (!insert->ins_tree_depth) { - ocfs2_figure_contig_type(inode, insert, el, insert_rec, et); + ocfs2_figure_contig_type(et, insert, el, insert_rec); ocfs2_figure_appending_type(insert, el, insert_rec); return 0; } @@ -4613,7 +4612,7 @@ static int ocfs2_figure_insert_type(struct inode *inode, * into two types of appends: simple record append, or a * rotate inside the tail leaf. */ - ocfs2_figure_contig_type(inode, insert, el, insert_rec, et); + ocfs2_figure_contig_type(et, insert, el, insert_rec); /* * The insert code isn't quite ready to deal with all cases of -- cgit v0.10.2 From 627961b77e68b725851cb227db10084bf15f6920 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 03:14:38 -0800 Subject: ocfs2: ocfs2_figure_insert_type() no longer needs struct inode. It's not using it, so remove it from the parameter list. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 38b1fea..3d09f4ba 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -4530,8 +4530,7 @@ set_tail_append: * All of the information is stored on the ocfs2_insert_type * structure. */ -static int ocfs2_figure_insert_type(struct inode *inode, - struct ocfs2_extent_tree *et, +static int ocfs2_figure_insert_type(struct ocfs2_extent_tree *et, struct buffer_head **last_eb_bh, struct ocfs2_extent_rec *insert_rec, int *free_records, @@ -4691,7 +4690,7 @@ int ocfs2_insert_extent(struct ocfs2_super *osb, goto bail; } - status = ocfs2_figure_insert_type(inode, et, &last_eb_bh, &rec, + status = ocfs2_figure_insert_type(et, &last_eb_bh, &rec, &free_records, &insert); if (status < 0) { mlog_errno(status); -- cgit v0.10.2 From 92ba470c44c1404ff18ca0f4ecce1e5b116bb933 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 03:18:34 -0800 Subject: ocfs2: Make extent map insertion an extent_tree_operation. ocfs2_insert_extent() wants to insert a record into the extent map if it's an inode data extent. But since many btrees can call that function, let's make it an op on ocfs2_extent_tree. Other tree types can leave it empty. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 3d09f4ba..ed86988 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -83,6 +83,13 @@ struct ocfs2_extent_tree_operations { u32 new_clusters); /* + * If this extent tree is supported by an extent map, insert + * a record into the map. + */ + void (*eo_extent_map_insert)(struct ocfs2_extent_tree *et, + struct ocfs2_extent_rec *rec); + + /* * If this extent tree is supported by an extent map, truncate the * map to clusters, */ @@ -127,6 +134,8 @@ static void ocfs2_dinode_set_last_eb_blk(struct ocfs2_extent_tree *et, u64 blkno); static void ocfs2_dinode_update_clusters(struct ocfs2_extent_tree *et, u32 clusters); +static void ocfs2_dinode_extent_map_insert(struct ocfs2_extent_tree *et, + struct ocfs2_extent_rec *rec); static void ocfs2_dinode_extent_map_truncate(struct ocfs2_extent_tree *et, u32 clusters); static int ocfs2_dinode_insert_check(struct ocfs2_extent_tree *et, @@ -137,6 +146,7 @@ static struct ocfs2_extent_tree_operations ocfs2_dinode_et_ops = { .eo_set_last_eb_blk = ocfs2_dinode_set_last_eb_blk, .eo_get_last_eb_blk = ocfs2_dinode_get_last_eb_blk, .eo_update_clusters = ocfs2_dinode_update_clusters, + .eo_extent_map_insert = ocfs2_dinode_extent_map_insert, .eo_extent_map_truncate = ocfs2_dinode_extent_map_truncate, .eo_insert_check = ocfs2_dinode_insert_check, .eo_sanity_check = ocfs2_dinode_sanity_check, @@ -172,6 +182,14 @@ static void ocfs2_dinode_update_clusters(struct ocfs2_extent_tree *et, spin_unlock(&oi->ip_lock); } +static void ocfs2_dinode_extent_map_insert(struct ocfs2_extent_tree *et, + struct ocfs2_extent_rec *rec) +{ + struct inode *inode = &cache_info_to_inode(et->et_ci)->vfs_inode; + + ocfs2_extent_map_insert_rec(inode, rec); +} + static void ocfs2_dinode_extent_map_truncate(struct ocfs2_extent_tree *et, u32 clusters) { @@ -418,6 +436,13 @@ static inline void ocfs2_et_update_clusters(struct ocfs2_extent_tree *et, et->et_ops->eo_update_clusters(et, clusters); } +static inline void ocfs2_et_extent_map_insert(struct ocfs2_extent_tree *et, + struct ocfs2_extent_rec *rec) +{ + if (et->et_ops->eo_extent_map_insert) + et->et_ops->eo_extent_map_insert(et, rec); +} + static inline void ocfs2_et_extent_map_truncate(struct ocfs2_extent_tree *et, u32 clusters) { @@ -4717,8 +4742,8 @@ int ocfs2_insert_extent(struct ocfs2_super *osb, status = ocfs2_do_insert_extent(handle, et, &rec, &insert); if (status < 0) mlog_errno(status); - else if (et->et_ops == &ocfs2_dinode_et_ops) - ocfs2_extent_map_insert_rec(inode, &rec); + else + ocfs2_et_extent_map_insert(et, &rec); bail: brelse(last_eb_bh); -- cgit v0.10.2 From cc79d8c19e9d39446525a1026f1a21761f5d3cd2 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 03:24:43 -0800 Subject: ocfs2: ocfs2_insert_extent() no longer needs struct inode. One more function down, no inode in the entire insert-extent chain. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index ed86988..c4943b9 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -4681,13 +4681,11 @@ out: } /* - * Insert an extent into an inode btree. + * Insert an extent into a btree. * - * The caller needs to update fe->i_clusters + * The caller needs to update the owning btree's cluster count. */ -int ocfs2_insert_extent(struct ocfs2_super *osb, - handle_t *handle, - struct inode *inode, +int ocfs2_insert_extent(handle_t *handle, struct ocfs2_extent_tree *et, u32 cpos, u64 start_blk, @@ -4701,8 +4699,9 @@ int ocfs2_insert_extent(struct ocfs2_super *osb, struct ocfs2_insert_type insert = {0, }; struct ocfs2_extent_rec rec; - mlog(0, "add %u clusters at position %u to inode %llu\n", - new_clusters, cpos, (unsigned long long)OCFS2_I(inode)->ip_blkno); + mlog(0, "add %u clusters at position %u to owner %llu\n", + new_clusters, cpos, + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci)); memset(&rec, 0, sizeof(rec)); rec.e_cpos = cpu_to_le32(cpos); @@ -4829,8 +4828,7 @@ int ocfs2_add_clusters_in_btree(struct ocfs2_super *osb, block = ocfs2_clusters_to_blocks(osb->sb, bit_off); mlog(0, "Allocating %u clusters at block %u for inode %llu\n", num_bits, bit_off, (unsigned long long)OCFS2_I(inode)->ip_blkno); - status = ocfs2_insert_extent(osb, handle, inode, et, - *logical_offset, block, + status = ocfs2_insert_extent(handle, et, *logical_offset, block, num_bits, flags, meta_ac); if (status < 0) { mlog_errno(status); @@ -7244,8 +7242,7 @@ int ocfs2_convert_inline_data_to_extents(struct inode *inode, * the in-inode data from our pages. */ ocfs2_init_dinode_extent_tree(&et, inode, di_bh); - ret = ocfs2_insert_extent(osb, handle, inode, &et, - 0, block, 1, 0, NULL); + ret = ocfs2_insert_extent(handle, &et, 0, block, 1, 0, NULL); if (ret) { mlog_errno(ret); goto out_commit; diff --git a/fs/ocfs2/alloc.h b/fs/ocfs2/alloc.h index 8718e57..99accd3 100644 --- a/fs/ocfs2/alloc.h +++ b/fs/ocfs2/alloc.h @@ -90,9 +90,7 @@ int ocfs2_read_extent_block(struct ocfs2_caching_info *ci, u64 eb_blkno, struct buffer_head **bh); struct ocfs2_alloc_context; -int ocfs2_insert_extent(struct ocfs2_super *osb, - handle_t *handle, - struct inode *inode, +int ocfs2_insert_extent(handle_t *handle, struct ocfs2_extent_tree *et, u32 cpos, u64 start_blk, diff --git a/fs/ocfs2/dir.c b/fs/ocfs2/dir.c index 088a1b5..de490a6 100644 --- a/fs/ocfs2/dir.c +++ b/fs/ocfs2/dir.c @@ -2591,7 +2591,6 @@ static int ocfs2_dx_dir_new_cluster(struct inode *dir, { int ret; u64 phys_blkno; - struct ocfs2_super *osb = OCFS2_SB(dir->i_sb); ret = __ocfs2_dx_dir_new_cluster(dir, cpos, handle, data_ac, dx_leaves, num_dx_leaves, &phys_blkno); @@ -2600,7 +2599,7 @@ static int ocfs2_dx_dir_new_cluster(struct inode *dir, goto out; } - ret = ocfs2_insert_extent(osb, handle, dir, et, cpos, phys_blkno, 1, 0, + ret = ocfs2_insert_extent(handle, et, cpos, phys_blkno, 1, 0, meta_ac); if (ret) mlog_errno(ret); @@ -3094,7 +3093,7 @@ static int ocfs2_expand_inline_dir(struct inode *dir, struct buffer_head *di_bh, * This should never fail as our extent list is empty and all * related blocks have been journaled already. */ - ret = ocfs2_insert_extent(osb, handle, dir, &et, 0, blkno, len, + ret = ocfs2_insert_extent(handle, &et, 0, blkno, len, 0, NULL); if (ret) { mlog_errno(ret); @@ -3127,7 +3126,7 @@ static int ocfs2_expand_inline_dir(struct inode *dir, struct buffer_head *di_bh, dirdata_bh); } else { ocfs2_init_dx_root_extent_tree(&dx_et, dir, dx_root_bh); - ret = ocfs2_insert_extent(osb, handle, dir, &dx_et, 0, + ret = ocfs2_insert_extent(handle, &dx_et, 0, dx_insert_blkno, 1, 0, NULL); if (ret) mlog_errno(ret); @@ -3147,7 +3146,7 @@ static int ocfs2_expand_inline_dir(struct inode *dir, struct buffer_head *di_bh, } blkno = ocfs2_clusters_to_blocks(dir->i_sb, bit_off); - ret = ocfs2_insert_extent(osb, handle, dir, &et, 1, + ret = ocfs2_insert_extent(handle, &et, 1, blkno, len, 0, NULL); if (ret) { mlog_errno(ret); @@ -4218,8 +4217,7 @@ static int ocfs2_expand_inline_dx_root(struct inode *dir, /* This should never fail considering we start with an empty * dx_root. */ ocfs2_init_dx_root_extent_tree(&et, dir, dx_root_bh); - ret = ocfs2_insert_extent(osb, handle, dir, &et, 0, - insert_blkno, 1, 0, NULL); + ret = ocfs2_insert_extent(handle, &et, 0, insert_blkno, 1, 0, NULL); if (ret) mlog_errno(ret); did_quota = 0; diff --git a/fs/ocfs2/xattr.c b/fs/ocfs2/xattr.c index 61819b2..38db12a 100644 --- a/fs/ocfs2/xattr.c +++ b/fs/ocfs2/xattr.c @@ -4325,7 +4325,7 @@ static int ocfs2_add_new_xattr_cluster(struct inode *inode, mlog(0, "Insert %u clusters at block %llu for xattr at %u\n", num_bits, (unsigned long long)block, v_start); - ret = ocfs2_insert_extent(osb, handle, inode, &et, v_start, block, + ret = ocfs2_insert_extent(handle, &et, v_start, block, num_bits, 0, ctxt->meta_ac); if (ret < 0) { mlog_errno(ret); -- cgit v0.10.2 From cbee7e1a6a1a2a3d6eda1f76ffc38a3ed3eeb6cc Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 03:34:15 -0800 Subject: ocfs2: ocfs2_add_clusters_in_btree() no longer needs struct inode. One more function that doesn't need a struct inode to pass to its children. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index c4943b9..29095e1 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -4758,13 +4758,11 @@ bail: * it is not limited to the file storage. Any extent tree can use this * function if it implements the proper ocfs2_extent_tree. */ -int ocfs2_add_clusters_in_btree(struct ocfs2_super *osb, - struct inode *inode, +int ocfs2_add_clusters_in_btree(handle_t *handle, + struct ocfs2_extent_tree *et, u32 *logical_offset, u32 clusters_to_add, int mark_unwritten, - struct ocfs2_extent_tree *et, - handle_t *handle, struct ocfs2_alloc_context *data_ac, struct ocfs2_alloc_context *meta_ac, enum ocfs2_alloc_restarted *reason_ret) @@ -4775,6 +4773,8 @@ int ocfs2_add_clusters_in_btree(struct ocfs2_super *osb, u32 bit_off, num_bits; u64 block; u8 flags = 0; + struct ocfs2_super *osb = + OCFS2_SB(ocfs2_metadata_cache_get_super(et->et_ci)); BUG_ON(!clusters_to_add); @@ -4826,8 +4826,9 @@ int ocfs2_add_clusters_in_btree(struct ocfs2_super *osb, } block = ocfs2_clusters_to_blocks(osb->sb, bit_off); - mlog(0, "Allocating %u clusters at block %u for inode %llu\n", - num_bits, bit_off, (unsigned long long)OCFS2_I(inode)->ip_blkno); + mlog(0, "Allocating %u clusters at block %u for owner %llu\n", + num_bits, bit_off, + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci)); status = ocfs2_insert_extent(handle, et, *logical_offset, block, num_bits, flags, meta_ac); if (status < 0) { diff --git a/fs/ocfs2/alloc.h b/fs/ocfs2/alloc.h index 99accd3..d1d196e 100644 --- a/fs/ocfs2/alloc.h +++ b/fs/ocfs2/alloc.h @@ -103,13 +103,11 @@ enum ocfs2_alloc_restarted { RESTART_TRANS, RESTART_META }; -int ocfs2_add_clusters_in_btree(struct ocfs2_super *osb, - struct inode *inode, +int ocfs2_add_clusters_in_btree(handle_t *handle, + struct ocfs2_extent_tree *et, u32 *logical_offset, u32 clusters_to_add, int mark_unwritten, - struct ocfs2_extent_tree *et, - handle_t *handle, struct ocfs2_alloc_context *data_ac, struct ocfs2_alloc_context *meta_ac, enum ocfs2_alloc_restarted *reason_ret); diff --git a/fs/ocfs2/file.c b/fs/ocfs2/file.c index 3ddbc5e..891e2c1e 100644 --- a/fs/ocfs2/file.c +++ b/fs/ocfs2/file.c @@ -516,10 +516,9 @@ int ocfs2_add_inode_data(struct ocfs2_super *osb, struct ocfs2_extent_tree et; ocfs2_init_dinode_extent_tree(&et, inode, fe_bh); - ret = ocfs2_add_clusters_in_btree(osb, inode, logical_offset, - clusters_to_add, mark_unwritten, - &et, handle, - data_ac, meta_ac, reason_ret); + ret = ocfs2_add_clusters_in_btree(handle, &et, logical_offset, + clusters_to_add, mark_unwritten, + data_ac, meta_ac, reason_ret); return ret; } diff --git a/fs/ocfs2/xattr.c b/fs/ocfs2/xattr.c index 38db12a..fdd02c4 100644 --- a/fs/ocfs2/xattr.c +++ b/fs/ocfs2/xattr.c @@ -597,7 +597,6 @@ static int ocfs2_xattr_extend_allocation(struct inode *inode, int status = 0; handle_t *handle = ctxt->handle; enum ocfs2_alloc_restarted why; - struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); u32 prev_clusters, logical_start = le32_to_cpu(vb->vb_xv->xr_clusters); struct ocfs2_extent_tree et; @@ -613,13 +612,11 @@ static int ocfs2_xattr_extend_allocation(struct inode *inode, } prev_clusters = le32_to_cpu(vb->vb_xv->xr_clusters); - status = ocfs2_add_clusters_in_btree(osb, - inode, + status = ocfs2_add_clusters_in_btree(handle, + &et, &logical_start, clusters_to_add, 0, - &et, - handle, ctxt->data_ac, ctxt->meta_ac, &why); -- cgit v0.10.2 From dbdcf6a48a40e6c9d7081393d793c4f1c5bb4fcf Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 03:41:26 -0800 Subject: ocfs2: ocfs2_remove_extent() no longer needs struct inode. One more generic btree function that is isolated from struct inode. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 29095e1..bfead60 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -5198,8 +5198,8 @@ out: return ret; } -static int ocfs2_split_tree(struct inode *inode, struct ocfs2_extent_tree *et, - handle_t *handle, struct ocfs2_path *path, +static int ocfs2_split_tree(handle_t *handle, struct ocfs2_extent_tree *et, + struct ocfs2_path *path, int index, u32 new_range, struct ocfs2_alloc_context *meta_ac) { @@ -5216,7 +5216,8 @@ static int ocfs2_split_tree(struct inode *inode, struct ocfs2_extent_tree *et, */ el = path_leaf_el(path); rec = &el->l_recs[index]; - ocfs2_make_right_split_rec(inode->i_sb, &split_rec, new_range, rec); + ocfs2_make_right_split_rec(ocfs2_metadata_cache_get_super(et->et_ci), + &split_rec, new_range, rec); depth = path->p_tree_depth; if (depth > 0) { @@ -5424,9 +5425,9 @@ out: return ret; } -int ocfs2_remove_extent(struct inode *inode, +int ocfs2_remove_extent(handle_t *handle, struct ocfs2_extent_tree *et, - u32 cpos, u32 len, handle_t *handle, + u32 cpos, u32 len, struct ocfs2_alloc_context *meta_ac, struct ocfs2_cached_dealloc_ctxt *dealloc) { @@ -5458,10 +5459,11 @@ int ocfs2_remove_extent(struct inode *inode, el = path_leaf_el(path); index = ocfs2_search_extent_list(el, cpos); if (index == -1 || index >= le16_to_cpu(el->l_next_free_rec)) { - ocfs2_error(inode->i_sb, - "Inode %llu has an extent at cpos %u which can no " + ocfs2_error(ocfs2_metadata_cache_get_super(et->et_ci), + "Owner %llu has an extent at cpos %u which can no " "longer be found.\n", - (unsigned long long)OCFS2_I(inode)->ip_blkno, cpos); + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci), + cpos); ret = -EROFS; goto out; } @@ -5488,9 +5490,10 @@ int ocfs2_remove_extent(struct inode *inode, BUG_ON(cpos < le32_to_cpu(rec->e_cpos) || trunc_range > rec_range); - mlog(0, "Inode %llu, remove (cpos %u, len %u). Existing index %d " + mlog(0, "Owner %llu, remove (cpos %u, len %u). Existing index %d " "(cpos %u, len %u)\n", - (unsigned long long)OCFS2_I(inode)->ip_blkno, cpos, len, index, + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci), + cpos, len, index, le32_to_cpu(rec->e_cpos), ocfs2_rec_clusters(el, rec)); if (le32_to_cpu(rec->e_cpos) == cpos || rec_range == trunc_range) { @@ -5501,7 +5504,7 @@ int ocfs2_remove_extent(struct inode *inode, goto out; } } else { - ret = ocfs2_split_tree(inode, et, handle, path, index, + ret = ocfs2_split_tree(handle, et, path, index, trunc_range, meta_ac); if (ret) { mlog_errno(ret); @@ -5523,9 +5526,9 @@ int ocfs2_remove_extent(struct inode *inode, el = path_leaf_el(path); index = ocfs2_search_extent_list(el, cpos); if (index == -1 || index >= le16_to_cpu(el->l_next_free_rec)) { - ocfs2_error(inode->i_sb, - "Inode %llu: split at cpos %u lost record.", - (unsigned long long)OCFS2_I(inode)->ip_blkno, + ocfs2_error(ocfs2_metadata_cache_get_super(et->et_ci), + "Owner %llu: split at cpos %u lost record.", + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci), cpos); ret = -EROFS; goto out; @@ -5539,10 +5542,10 @@ int ocfs2_remove_extent(struct inode *inode, rec_range = le32_to_cpu(rec->e_cpos) + ocfs2_rec_clusters(el, rec); if (rec_range != trunc_range) { - ocfs2_error(inode->i_sb, - "Inode %llu: error after split at cpos %u" + ocfs2_error(ocfs2_metadata_cache_get_super(et->et_ci), + "Owner %llu: error after split at cpos %u" "trunc len %u, existing record is (%u,%u)", - (unsigned long long)OCFS2_I(inode)->ip_blkno, + (unsigned long long)ocfs2_metadata_cache_owner(et->et_ci), cpos, len, le32_to_cpu(rec->e_cpos), ocfs2_rec_clusters(el, rec)); ret = -EROFS; @@ -5607,8 +5610,7 @@ int ocfs2_remove_btree_range(struct inode *inode, vfs_dq_free_space_nodirty(inode, ocfs2_clusters_to_bytes(inode->i_sb, len)); - ret = ocfs2_remove_extent(inode, et, cpos, len, handle, meta_ac, - dealloc); + ret = ocfs2_remove_extent(handle, et, cpos, len, meta_ac, dealloc); if (ret) { mlog_errno(ret); goto out_commit; diff --git a/fs/ocfs2/alloc.h b/fs/ocfs2/alloc.h index d1d196e..abc66ce 100644 --- a/fs/ocfs2/alloc.h +++ b/fs/ocfs2/alloc.h @@ -117,9 +117,8 @@ int ocfs2_mark_extent_written(struct inode *inode, handle_t *handle, u32 cpos, u32 len, u32 phys, struct ocfs2_alloc_context *meta_ac, struct ocfs2_cached_dealloc_ctxt *dealloc); -int ocfs2_remove_extent(struct inode *inode, - struct ocfs2_extent_tree *et, - u32 cpos, u32 len, handle_t *handle, +int ocfs2_remove_extent(handle_t *handle, struct ocfs2_extent_tree *et, + u32 cpos, u32 len, struct ocfs2_alloc_context *meta_ac, struct ocfs2_cached_dealloc_ctxt *dealloc); int ocfs2_remove_btree_range(struct inode *inode, diff --git a/fs/ocfs2/xattr.c b/fs/ocfs2/xattr.c index fdd02c4..96f973a 100644 --- a/fs/ocfs2/xattr.c +++ b/fs/ocfs2/xattr.c @@ -663,7 +663,7 @@ static int __ocfs2_remove_xattr_range(struct inode *inode, goto out; } - ret = ocfs2_remove_extent(inode, &et, cpos, len, handle, ctxt->meta_ac, + ret = ocfs2_remove_extent(handle, &et, cpos, len, ctxt->meta_ac, &ctxt->dealloc); if (ret) { mlog_errno(ret); @@ -4881,7 +4881,7 @@ static int ocfs2_rm_xattr_cluster(struct inode *inode, goto out_commit; } - ret = ocfs2_remove_extent(inode, &et, cpos, len, handle, meta_ac, + ret = ocfs2_remove_extent(handle, &et, cpos, len, meta_ac, &dealloc); if (ret) { mlog_errno(ret); -- cgit v0.10.2 From d231129f44e7ead14f5f496e664ff1e3883a7b25 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 03:43:22 -0800 Subject: ocfs2: ocfs2_split_and_insert() no longer needs struct inode. It already has an extent_tree. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index bfead60..85cd2ad 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -4879,10 +4879,9 @@ static void ocfs2_make_right_split_rec(struct super_block *sb, split_rec->e_flags = rec->e_flags; } -static int ocfs2_split_and_insert(struct inode *inode, - handle_t *handle, - struct ocfs2_path *path, +static int ocfs2_split_and_insert(handle_t *handle, struct ocfs2_extent_tree *et, + struct ocfs2_path *path, struct buffer_head **last_eb_bh, int split_index, struct ocfs2_extent_rec *orig_split_rec, @@ -4944,8 +4943,8 @@ leftright: */ insert.ins_split = SPLIT_RIGHT; - ocfs2_make_right_split_rec(inode->i_sb, &tmprec, insert_range, - &rec); + ocfs2_make_right_split_rec(ocfs2_metadata_cache_get_super(et->et_ci), + &tmprec, insert_range, &rec); split_rec = tmprec; @@ -5100,7 +5099,7 @@ static int __ocfs2_mark_extent_written(struct inode *inode, path, el, split_index, split_rec); else - ret = ocfs2_split_and_insert(inode, handle, path, et, + ret = ocfs2_split_and_insert(handle, et, path, &last_eb_bh, split_index, split_rec, meta_ac); if (ret) -- cgit v0.10.2 From f3868d0fa2e20d923087a8296fda47b0afe7f9ba Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Tue, 17 Feb 2009 19:46:04 -0800 Subject: ocfs2: Teach ocfs2_replace_extent_rec() to use an extent_tree. Don't use a struct inode anymore. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 85cd2ad..7b0f2cd 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -4983,8 +4983,8 @@ out: return ret; } -static int ocfs2_replace_extent_rec(struct inode *inode, - handle_t *handle, +static int ocfs2_replace_extent_rec(handle_t *handle, + struct ocfs2_extent_tree *et, struct ocfs2_path *path, struct ocfs2_extent_list *el, int split_index, @@ -4992,7 +4992,7 @@ static int ocfs2_replace_extent_rec(struct inode *inode, { int ret; - ret = ocfs2_path_bh_journal_access(handle, INODE_CACHE(inode), path, + ret = ocfs2_path_bh_journal_access(handle, et->et_ci, path, path_num_items(path) - 1); if (ret) { mlog_errno(ret); @@ -5095,8 +5095,7 @@ static int __ocfs2_mark_extent_written(struct inode *inode, if (ctxt.c_contig_type == CONTIG_NONE) { if (ctxt.c_split_covers_rec) - ret = ocfs2_replace_extent_rec(inode, handle, - path, el, + ret = ocfs2_replace_extent_rec(handle, et, path, el, split_index, split_rec); else ret = ocfs2_split_and_insert(handle, et, path, -- cgit v0.10.2 From a1cf076ba93f9fdf3eb4195f9f43d1e7cb7550f2 Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 03:45:49 -0800 Subject: ocfs2: __ocfs2_mark_extent_written() doesn't need struct inode. We only allow unwritten extents on data, so the toplevel ocfs2_mark_extent_written() can use an inode all it wants. But the subfunction isn't even using the inode argument. Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 7b0f2cd..4488685 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -5026,9 +5026,8 @@ out: * have been brought into cache (and pinned via the journal), so the * extra overhead is not expressed in terms of disk reads. */ -static int __ocfs2_mark_extent_written(struct inode *inode, +static int __ocfs2_mark_extent_written(handle_t *handle, struct ocfs2_extent_tree *et, - handle_t *handle, struct ocfs2_path *path, int split_index, struct ocfs2_extent_rec *split_rec, @@ -5062,7 +5061,7 @@ static int __ocfs2_mark_extent_written(struct inode *inode, /* * The core merge / split code wants to know how much room is - * left in this inodes allocation tree, so we pass the + * left in this allocation tree, so we pass the * rightmost extent list. */ if (path->p_tree_depth) { @@ -5185,7 +5184,7 @@ int ocfs2_mark_extent_written(struct inode *inode, split_rec.e_flags = path_leaf_el(left_path)->l_recs[index].e_flags; split_rec.e_flags &= ~OCFS2_EXT_UNWRITTEN; - ret = __ocfs2_mark_extent_written(inode, et, handle, left_path, + ret = __ocfs2_mark_extent_written(handle, et, left_path, index, &split_rec, meta_ac, dealloc); if (ret) -- cgit v0.10.2 From 5e404e9ed1b05cafb044bd46792e50197df805ed Mon Sep 17 00:00:00 2001 From: Joel Becker Date: Fri, 13 Feb 2009 03:54:22 -0800 Subject: ocfs2: Pass ocfs2_caching_info into ocfs_init_*_extent_tree(). With this commit, extent tree operations are divorced from inodes and rely on ocfs2_caching_info. Phew! Signed-off-by: Joel Becker diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 4488685..ab4d2b5 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -366,7 +366,7 @@ static struct ocfs2_extent_tree_operations ocfs2_dx_root_et_ops = { }; static void __ocfs2_init_extent_tree(struct ocfs2_extent_tree *et, - struct inode *inode, + struct ocfs2_caching_info *ci, struct buffer_head *bh, ocfs2_journal_access_func access, void *obj, @@ -374,7 +374,7 @@ static void __ocfs2_init_extent_tree(struct ocfs2_extent_tree *et, { et->et_ops = ops; et->et_root_bh = bh; - et->et_ci = INODE_CACHE(inode); + et->et_ci = ci; et->et_root_journal_access = access; if (!obj) obj = (void *)bh->b_data; @@ -388,34 +388,34 @@ static void __ocfs2_init_extent_tree(struct ocfs2_extent_tree *et, } void ocfs2_init_dinode_extent_tree(struct ocfs2_extent_tree *et, - struct inode *inode, + struct ocfs2_caching_info *ci, struct buffer_head *bh) { - __ocfs2_init_extent_tree(et, inode, bh, ocfs2_journal_access_di, + __ocfs2_init_extent_tree(et, ci, bh, ocfs2_journal_access_di, NULL, &ocfs2_dinode_et_ops); } void ocfs2_init_xattr_tree_extent_tree(struct ocfs2_extent_tree *et, - struct inode *inode, + struct ocfs2_caching_info *ci, struct buffer_head *bh) { - __ocfs2_init_extent_tree(et, inode, bh, ocfs2_journal_access_xb, + __ocfs2_init_extent_tree(et, ci, bh, ocfs2_journal_access_xb, NULL, &ocfs2_xattr_tree_et_ops); } void ocfs2_init_xattr_value_extent_tree(struct ocfs2_extent_tree *et, - struct inode *inode, + struct ocfs2_caching_info *ci, struct ocfs2_xattr_value_buf *vb) { - __ocfs2_init_extent_tree(et, inode, vb->vb_bh, vb->vb_access, vb, + __ocfs2_init_extent_tree(et, ci, vb->vb_bh, vb->vb_access, vb, &ocfs2_xattr_value_et_ops); } void ocfs2_init_dx_root_extent_tree(struct ocfs2_extent_tree *et, - struct inode *inode, + struct ocfs2_caching_info *ci, struct buffer_head *bh) { - __ocfs2_init_extent_tree(et, inode, bh, ocfs2_journal_access_dr, + __ocfs2_init_extent_tree(et, ci, bh, ocfs2_journal_access_dr, NULL, &ocfs2_dx_root_et_ops); } @@ -7241,7 +7241,7 @@ int ocfs2_convert_inline_data_to_extents(struct inode *inode, * this proves to be false, we could always re-build * the in-inode data from our pages. */ - ocfs2_init_dinode_extent_tree(&et, inode, di_bh); + ocfs2_init_dinode_extent_tree(&et, INODE_CACHE(inode), di_bh); ret = ocfs2_insert_extent(handle, &et, 0, block, 1, 0, NULL); if (ret) { mlog_errno(ret); diff --git a/fs/ocfs2/alloc.h b/fs/ocfs2/alloc.h index abc66ce..bcf6aa4 100644 --- a/fs/ocfs2/alloc.h +++ b/fs/ocfs2/alloc.h @@ -68,17 +68,17 @@ struct ocfs2_extent_tree { * specified object buffer. */ void ocfs2_init_dinode_extent_tree(struct ocfs2_extent_tree *et, - struct inode *inode, + struct ocfs2_caching_info *ci, struct buffer_head *bh); void ocfs2_init_xattr_tree_extent_tree(struct ocfs2_extent_tree *et, - struct inode *inode, + struct ocfs2_caching_info *ci, struct buffer_head *bh); struct ocfs2_xattr_value_buf; void ocfs2_init_xattr_value_extent_tree(struct ocfs2_extent_tree *et, - struct inode *inode, + struct ocfs2_caching_info *ci, struct ocfs2_xattr_value_buf *vb); void ocfs2_init_dx_root_extent_tree(struct ocfs2_extent_tree *et, - struct inode *inode, + struct ocfs2_caching_info *ci, struct buffer_head *bh); /* diff --git a/fs/ocfs2/aops.c b/fs/ocfs2/aops.c index 49eef2c..15c594d 100644 --- a/fs/ocfs2/aops.c +++ b/fs/ocfs2/aops.c @@ -1259,7 +1259,8 @@ static int ocfs2_write_cluster(struct address_space *mapping, goto out; } } else if (unwritten) { - ocfs2_init_dinode_extent_tree(&et, inode, wc->w_di_bh); + ocfs2_init_dinode_extent_tree(&et, INODE_CACHE(inode), + wc->w_di_bh); ret = ocfs2_mark_extent_written(inode, &et, wc->w_handle, cpos, 1, phys, meta_ac, &wc->w_dealloc); @@ -1726,7 +1727,8 @@ int ocfs2_write_begin_nolock(struct address_space *mapping, (long long)i_size_read(inode), le32_to_cpu(di->i_clusters), clusters_to_alloc, extents_to_split); - ocfs2_init_dinode_extent_tree(&et, inode, wc->w_di_bh); + ocfs2_init_dinode_extent_tree(&et, INODE_CACHE(inode), + wc->w_di_bh); ret = ocfs2_lock_allocators(inode, &et, clusters_to_alloc, extents_to_split, &data_ac, &meta_ac); diff --git a/fs/ocfs2/dir.c b/fs/ocfs2/dir.c index de490a6..28c3ec2 100644 --- a/fs/ocfs2/dir.c +++ b/fs/ocfs2/dir.c @@ -2903,7 +2903,7 @@ static int ocfs2_expand_inline_dir(struct inode *dir, struct buffer_head *di_bh, struct ocfs2_extent_tree dx_et; int did_quota = 0, bytes_allocated = 0; - ocfs2_init_dinode_extent_tree(&et, dir, di_bh); + ocfs2_init_dinode_extent_tree(&et, INODE_CACHE(dir), di_bh); alloc = ocfs2_clusters_for_bytes(sb, bytes); dx_alloc = 0; @@ -3125,7 +3125,9 @@ static int ocfs2_expand_inline_dir(struct inode *dir, struct buffer_head *di_bh, ocfs2_dx_dir_index_root_block(dir, dx_root_bh, dirdata_bh); } else { - ocfs2_init_dx_root_extent_tree(&dx_et, dir, dx_root_bh); + ocfs2_init_dx_root_extent_tree(&dx_et, + INODE_CACHE(dir), + dx_root_bh); ret = ocfs2_insert_extent(handle, &dx_et, 0, dx_insert_blkno, 1, 0, NULL); if (ret) @@ -3345,7 +3347,8 @@ static int ocfs2_extend_dir(struct ocfs2_super *osb, spin_lock(&OCFS2_I(dir)->ip_lock); if (dir_i_size == ocfs2_clusters_to_bytes(sb, OCFS2_I(dir)->ip_clusters)) { spin_unlock(&OCFS2_I(dir)->ip_lock); - ocfs2_init_dinode_extent_tree(&et, dir, parent_fe_bh); + ocfs2_init_dinode_extent_tree(&et, INODE_CACHE(dir), + parent_fe_bh); num_free_extents = ocfs2_num_free_extents(osb, &et); if (num_free_extents < 0) { status = num_free_extents; @@ -3837,7 +3840,7 @@ static int ocfs2_dx_dir_rebalance(struct ocfs2_super *osb, struct inode *dir, (unsigned long long)OCFS2_I(dir)->ip_blkno, (unsigned long long)leaf_blkno, insert_hash); - ocfs2_init_dx_root_extent_tree(&et, dir, dx_root_bh); + ocfs2_init_dx_root_extent_tree(&et, INODE_CACHE(dir), dx_root_bh); dx_root = (struct ocfs2_dx_root_block *)dx_root_bh->b_data; /* @@ -4216,7 +4219,7 @@ static int ocfs2_expand_inline_dx_root(struct inode *dir, /* This should never fail considering we start with an empty * dx_root. */ - ocfs2_init_dx_root_extent_tree(&et, dir, dx_root_bh); + ocfs2_init_dx_root_extent_tree(&et, INODE_CACHE(dir), dx_root_bh); ret = ocfs2_insert_extent(handle, &et, 0, insert_blkno, 1, 0, NULL); if (ret) mlog_errno(ret); @@ -4540,7 +4543,7 @@ int ocfs2_dx_dir_truncate(struct inode *dir, struct buffer_head *di_bh) if (ocfs2_dx_root_inline(dx_root)) goto remove_index; - ocfs2_init_dx_root_extent_tree(&et, dir, dx_root_bh); + ocfs2_init_dx_root_extent_tree(&et, INODE_CACHE(dir), dx_root_bh); /* XXX: What if dr_clusters is too large? */ while (le32_to_cpu(dx_root->dr_clusters)) { diff --git a/fs/ocfs2/file.c b/fs/ocfs2/file.c index 891e2c1e..4921b4e 100644 --- a/fs/ocfs2/file.c +++ b/fs/ocfs2/file.c @@ -515,7 +515,7 @@ int ocfs2_add_inode_data(struct ocfs2_super *osb, int ret; struct ocfs2_extent_tree et; - ocfs2_init_dinode_extent_tree(&et, inode, fe_bh); + ocfs2_init_dinode_extent_tree(&et, INODE_CACHE(inode), fe_bh); ret = ocfs2_add_clusters_in_btree(handle, &et, logical_offset, clusters_to_add, mark_unwritten, data_ac, meta_ac, reason_ret); @@ -563,7 +563,7 @@ restart_all: (unsigned long long)OCFS2_I(inode)->ip_blkno, (long long)i_size_read(inode), le32_to_cpu(fe->i_clusters), clusters_to_add); - ocfs2_init_dinode_extent_tree(&et, inode, bh); + ocfs2_init_dinode_extent_tree(&et, INODE_CACHE(inode), bh); status = ocfs2_lock_allocators(inode, &et, clusters_to_add, 0, &data_ac, &meta_ac); if (status) { @@ -1394,7 +1394,7 @@ static int ocfs2_remove_inode_range(struct inode *inode, struct address_space *mapping = inode->i_mapping; struct ocfs2_extent_tree et; - ocfs2_init_dinode_extent_tree(&et, inode, di_bh); + ocfs2_init_dinode_extent_tree(&et, INODE_CACHE(inode), di_bh); ocfs2_init_dealloc_ctxt(&dealloc); if (byte_len == 0) diff --git a/fs/ocfs2/xattr.c b/fs/ocfs2/xattr.c index 96f973a..1bf12c4 100644 --- a/fs/ocfs2/xattr.c +++ b/fs/ocfs2/xattr.c @@ -602,7 +602,7 @@ static int ocfs2_xattr_extend_allocation(struct inode *inode, mlog(0, "(clusters_to_add for xattr= %u)\n", clusters_to_add); - ocfs2_init_xattr_value_extent_tree(&et, inode, vb); + ocfs2_init_xattr_value_extent_tree(&et, INODE_CACHE(inode), vb); status = vb->vb_access(handle, INODE_CACHE(inode), vb->vb_bh, OCFS2_JOURNAL_ACCESS_WRITE); @@ -654,7 +654,7 @@ static int __ocfs2_remove_xattr_range(struct inode *inode, handle_t *handle = ctxt->handle; struct ocfs2_extent_tree et; - ocfs2_init_xattr_value_extent_tree(&et, inode, vb); + ocfs2_init_xattr_value_extent_tree(&et, INODE_CACHE(inode), vb); ret = vb->vb_access(handle, INODE_CACHE(inode), vb->vb_bh, OCFS2_JOURNAL_ACCESS_WRITE); @@ -4266,7 +4266,7 @@ static int ocfs2_add_new_xattr_cluster(struct inode *inode, (unsigned long long)OCFS2_I(inode)->ip_blkno, prev_cpos, (unsigned long long)bucket_blkno(first)); - ocfs2_init_xattr_tree_extent_tree(&et, inode, root_bh); + ocfs2_init_xattr_tree_extent_tree(&et, INODE_CACHE(inode), root_bh); ret = ocfs2_journal_access_xb(handle, INODE_CACHE(inode), root_bh, OCFS2_JOURNAL_ACCESS_WRITE); @@ -4841,7 +4841,7 @@ static int ocfs2_rm_xattr_cluster(struct inode *inode, struct ocfs2_cached_dealloc_ctxt dealloc; struct ocfs2_extent_tree et; - ocfs2_init_xattr_tree_extent_tree(&et, inode, root_bh); + ocfs2_init_xattr_tree_extent_tree(&et, INODE_CACHE(inode), root_bh); ocfs2_init_dealloc_ctxt(&dealloc); -- cgit v0.10.2 From f61f925859c57f6175082aeeee17743c68558a6e Mon Sep 17 00:00:00 2001 From: Len Brown Date: Sat, 5 Sep 2009 13:33:23 -0400 Subject: Revert "ACPI: Attach the ACPI device to the ACPI handle as early as possible" This reverts commit eab4b645769fa2f8703f5a3cb0cc4ac090d347af. http://bugzilla.kernel.org/show_bug.cgi?id=13002 Signed-off-by: Len Brown diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 781435d..5dd702c 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1264,16 +1264,6 @@ acpi_add_single_object(struct acpi_device **child, acpi_device_set_id(device, parent, handle, type); /* - * The ACPI device is attached to acpi handle before getting - * the power/wakeup/peformance flags. Otherwise OS can't get - * the corresponding ACPI device by the acpi handle in the course - * of getting the power/wakeup/performance flags. - */ - result = acpi_device_set_context(device, type); - if (result) - goto end; - - /* * Power Management * ---------------- */ @@ -1303,6 +1293,8 @@ acpi_add_single_object(struct acpi_device **child, goto end; } + if ((result = acpi_device_set_context(device, type))) + goto end; result = acpi_device_register(device, parent); -- cgit v0.10.2 From 0ef82af7253c1929a3995f271b8b0db462d1a0c3 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 5 Sep 2009 18:07:06 +0100 Subject: drm/i915: Pad ringbuffer with NOOPs before wrapping MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the docs, the ringbuffer is not allowed to wrap in the middle of an instruction. G45 PRM, Vol 1b, p101: While the “free space†wrap may allow commands to be wrapped around the end of the Ring Buffer, the wrap should only occur between commands. Padding (with NOP) may be required to follow this restriction. Do as commanded. [Having seen bug reports where there is evidence of split commands, but apparently the GPU has continued on merrily before a bizarre and untimely death, this may or may not fix a few random hangs.] Signed-off-by: Chris Wilson CC: Eric Anholt Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8f28325..1e3bdce 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -333,15 +333,13 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_device *dev = node->minor->dev; drm_i915_private_t *dev_priv = dev->dev_private; - unsigned int head, tail, mask; + unsigned int head, tail; head = I915_READ(PRB0_HEAD) & HEAD_ADDR; tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; - mask = dev_priv->ring.tail_mask; seq_printf(m, "RingHead : %08x\n", head); seq_printf(m, "RingTail : %08x\n", tail); - seq_printf(m, "RingMask : %08x\n", mask); seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size); seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD)); diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 50d1f78..f135bdc 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -80,6 +80,34 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller) return -EBUSY; } +/* As a ringbuffer is only allowed to wrap between instructions, fill + * the tail with NOOPs. + */ +int i915_wrap_ring(struct drm_device *dev) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + volatile unsigned int *virt; + int rem; + + rem = dev_priv->ring.Size - dev_priv->ring.tail; + if (dev_priv->ring.space < rem) { + int ret = i915_wait_ring(dev, rem, __func__); + if (ret) + return ret; + } + dev_priv->ring.space -= rem; + + virt = (unsigned int *) + (dev_priv->ring.virtual_start + dev_priv->ring.tail); + rem /= 4; + while (rem--) + *virt++ = MI_NOOP; + + dev_priv->ring.tail = 0; + + return 0; +} + /** * Sets up the hardware status page for devices that need a physical address * in the register. @@ -200,7 +228,6 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) } dev_priv->ring.Size = init->ring_size; - dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; dev_priv->ring.map.offset = init->ring_start; dev_priv->ring.map.size = init->ring_size; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 76914ae..2d5bce6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -85,7 +85,6 @@ struct drm_i915_gem_phys_object { }; typedef struct _drm_i915_ring_buffer { - int tail_mask; unsigned long Size; u8 *virtual_start; int head; @@ -790,33 +789,32 @@ extern void intel_modeset_cleanup(struct drm_device *dev); #define I915_VERBOSE 0 -#define RING_LOCALS unsigned int outring, ringmask, outcount; \ - volatile char *virt; - -#define BEGIN_LP_RING(n) do { \ - if (I915_VERBOSE) \ - DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ - if (dev_priv->ring.space < (n)*4) \ - i915_wait_ring(dev, (n)*4, __func__); \ - outcount = 0; \ - outring = dev_priv->ring.tail; \ - ringmask = dev_priv->ring.tail_mask; \ - virt = dev_priv->ring.virtual_start; \ +#define RING_LOCALS volatile unsigned int *ring_virt__; + +#define BEGIN_LP_RING(n) do { \ + int bytes__ = 4*(n); \ + if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ + /* a wrap must occur between instructions so pad beforehand */ \ + if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \ + i915_wrap_ring(dev); \ + if (unlikely (dev_priv->ring.space < bytes__)) \ + i915_wait_ring(dev, bytes__, __func__); \ + ring_virt__ = (unsigned int *) \ + (dev_priv->ring.virtual_start + dev_priv->ring.tail); \ + dev_priv->ring.tail += bytes__; \ + dev_priv->ring.tail &= dev_priv->ring.Size - 1; \ + dev_priv->ring.space -= bytes__; \ } while (0) -#define OUT_RING(n) do { \ +#define OUT_RING(n) do { \ if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ - *(volatile unsigned int *)(virt + outring) = (n); \ - outcount++; \ - outring += 4; \ - outring &= ringmask; \ + *ring_virt__++ = (n); \ } while (0) #define ADVANCE_LP_RING() do { \ - if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ - dev_priv->ring.tail = outring; \ - dev_priv->ring.space -= outcount * 4; \ - I915_WRITE(PRB0_TAIL, outring); \ + if (I915_VERBOSE) \ + DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \ + I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \ } while(0) /** @@ -839,6 +837,7 @@ extern void intel_modeset_cleanup(struct drm_device *dev); #define I915_GEM_HWS_INDEX 0x20 #define I915_BREADCRUMB_INDEX 0x21 +extern int i915_wrap_ring(struct drm_device * dev); extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define IS_I830(dev) ((dev)->pci_device == 0x3577) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 73b5819..0767521 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4099,7 +4099,6 @@ i915_gem_init_ringbuffer(struct drm_device *dev) /* Set up the kernel mapping for the ring. */ ring->Size = obj->size; - ring->tail_mask = obj->size - 1; ring->map.offset = dev->agp->base + obj_priv->gtt_offset; ring->map.size = obj->size; -- cgit v0.10.2 From 01dfba93d9dfcf6d7abfc55ff5d9d6e76fa01ba0 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Sun, 6 Sep 2009 15:18:53 -0700 Subject: drm/i915: Put the idle reclocking work on our private workqueue as well. Fixes (again) whole-system lockups due to GPU lockups. Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9aa1d2d..f674103 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3201,7 +3201,7 @@ static void intel_gpu_idle_timer(unsigned long arg) dev_priv->busy = false; - schedule_work(&dev_priv->idle_work); + queue_work(dev_priv->wq, &dev_priv->idle_work); } void intel_increase_renderclock(struct drm_device *dev, bool schedule) @@ -3335,7 +3335,7 @@ static void intel_crtc_idle_timer(unsigned long arg) intel_crtc->busy = false; - schedule_work(&dev_priv->idle_work); + queue_work(dev_priv->wq, &dev_priv->idle_work); } static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule) -- cgit v0.10.2 From a498b8210f2f6ee0529c28048b5c4cecc17937c2 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 1 Sep 2009 14:40:41 +1000 Subject: drm/radeon/kms: block depthxy offset from use from userspace. This could be used to bypass CS checks. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300 index 16f8f38..d927005 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/r300 +++ b/drivers/gpu/drm/radeon/reg_srcs/r300 @@ -725,4 +725,3 @@ r300 0x4f60 0x4F50 ZB_HIZ_RDINDEX 0x4F54 ZB_HIZ_PITCH 0x4F58 ZB_ZPASS_DATA -0x4F60 ZB_DEPTHXY_OFFSET diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600 index 498c581..344405a 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/rs600 +++ b/drivers/gpu/drm/radeon/reg_srcs/rs600 @@ -725,4 +725,3 @@ rs600 0x6d40 0x4F50 ZB_HIZ_RDINDEX 0x4F54 ZB_HIZ_PITCH 0x4F58 ZB_ZPASS_DATA -0x4F60 ZB_DEPTHXY_OFFSET diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515 index 7432df7..9602026 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/rv515 +++ b/drivers/gpu/drm/radeon/reg_srcs/rv515 @@ -483,4 +483,3 @@ rv515 0x6d40 0x4F50 ZB_HIZ_RDINDEX 0x4F54 ZB_HIZ_PITCH 0x4F58 ZB_ZPASS_DATA -0x4F60 ZB_DEPTHXY_OFFSET -- cgit v0.10.2 From adf551bb25bfb83b79ce3c3887557ed817e26cc9 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 7 Sep 2009 13:49:07 +1000 Subject: drm/radeon/kms: add updated registers from drm-fixes. Fixes up the DISCARD + 2 sided stencil in the new generator scripts. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300 index d927005..19c4663 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/r300 +++ b/drivers/gpu/drm/radeon/reg_srcs/r300 @@ -708,6 +708,8 @@ r300 0x4f60 0x4E80 RB3D_AARESOLVE_OFFSET 0x4E84 RB3D_AARESOLVE_PITCH 0x4E88 RB3D_AARESOLVE_CTL +0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD +0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 0x4F04 ZB_ZSTENCILCNTL 0x4F08 ZB_STENCILREFMASK 0x4F14 ZB_ZTOP diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600 index 344405a..8e3c0b8 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/rs600 +++ b/drivers/gpu/drm/radeon/reg_srcs/rs600 @@ -708,6 +708,8 @@ rs600 0x6d40 0x4E80 RB3D_AARESOLVE_OFFSET 0x4E84 RB3D_AARESOLVE_PITCH 0x4E88 RB3D_AARESOLVE_CTL +0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD +0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 0x4F04 ZB_ZSTENCILCNTL 0x4F08 ZB_STENCILREFMASK 0x4F14 ZB_ZTOP diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515 index 9602026..0102a0d 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/rv515 +++ b/drivers/gpu/drm/radeon/reg_srcs/rv515 @@ -483,3 +483,4 @@ rv515 0x6d40 0x4F50 ZB_HIZ_RDINDEX 0x4F54 ZB_HIZ_PITCH 0x4F58 ZB_ZPASS_DATA +0x4FD4 ZB_STENCILREFMASK_BF -- cgit v0.10.2 From 13a8195b148615b15a4f4385f695f2a232095414 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 7 Sep 2009 15:45:33 +1000 Subject: drm: split crtc/fb helpers into a separate module I really don't want to have core drm module rely on CONFIG_FB, so this is the easiest answer. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index ebafad1..8c73091 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -18,6 +18,13 @@ menuconfig DRM details. You should also select and configure AGP (/dev/agpgart) support. +config DRM_MODE_HELPER + tristate + depends on DRM + select FB + help + FB and CRTC helpers for kms drivers. + config DRM_TTM tristate depends on DRM @@ -48,7 +55,6 @@ config DRM_RADEON select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT - select FB select FRAMEBUFFER_CONSOLE if !EMBEDDED select FW_LOADER help @@ -84,10 +90,10 @@ config DRM_I830 config DRM_I915 tristate "i915 driver" depends on AGP_INTEL + select DRM_MODE_HELPER select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT - select FB select FRAMEBUFFER_CONSOLE if !EMBEDDED # i915 depends on ACPI_VIDEO when ACPI is enabled # but for select to work, need to select ACPI_VIDEO's dependencies, ick diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 9907168..7e96d74 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -10,12 +10,15 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \ drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \ drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \ drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \ - drm_crtc.o drm_crtc_helper.o drm_modes.o drm_edid.o \ - drm_info.o drm_debugfs.o drm_encoder_slave.o \ - drm_fb_helper.o + drm_crtc.o drm_modes.o drm_edid.o \ + drm_info.o drm_debugfs.o drm_encoder_slave.o drm-$(CONFIG_COMPAT) += drm_ioc32.o +drm_helper-y := drm_fb_helper.o drm_crtc_helper.o + +obj-$(CONFIG_DRM_MODE_HELPER) += drm_helper.o + obj-$(CONFIG_DRM) += drm.o obj-$(CONFIG_DRM_TTM) += ttm/ obj-$(CONFIG_DRM_TDFX) += tdfx/ diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index c20fcdc..ba728ad 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -168,6 +168,7 @@ char *drm_get_encoder_name(struct drm_encoder *encoder) encoder->base.id); return buf; } +EXPORT_SYMBOL(drm_get_encoder_name); char *drm_get_connector_name(struct drm_connector *connector) { diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig index 2168d67..fdd9c89 100644 --- a/drivers/gpu/drm/radeon/Kconfig +++ b/drivers/gpu/drm/radeon/Kconfig @@ -1,6 +1,7 @@ config DRM_RADEON_KMS bool "Enable modesetting on radeon by default" depends on DRM_RADEON + select DRM_MODE_HELPER select DRM_TTM help Choose this option if you want kernel modesetting enabled by default, -- cgit v0.10.2 From aa9eaa1f0962152d0bde821149d82fe7b70a6f92 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Thu, 3 Sep 2009 09:33:46 +0800 Subject: drm/kms: Add the default mode table When we add a standard timing mode in UMS, we will first check whether it can be found in default mode table. If it can't be found, then we will use cvt/gtf to add the standard timing mode. Add the default mode table so that we can check whether the given mode can be found in the default mode table as what we have done in UMS mode. If the status of one output device is connected but there is no EDID, it will have no correct mode. In such case we can add some default modes for it. Of course we only add the modes in the default modes list that visible part is not greater than 1024x768. The default mode is autogenerated from the DMT spec. And it is copied from xserver/hw/xfree86/modes/xf86EdidModes.c. But the mode with reduced blank feature is removed. Signed-off-by: Zhao Yakui Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index e4f1cb5..e64eb6b 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -243,6 +243,243 @@ static void edid_fixup_preferred(struct drm_connector *connector, preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; } +/* + * Add the Autogenerated from the DMT spec. + * This table is copied from xfree86/modes/xf86EdidModes.c. + * But the mode with Reduced blank feature is deleted. + */ +static struct drm_display_mode drm_dmt_modes[] = { + /* 640x350@85Hz */ + { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, + 736, 832, 0, 350, 382, 385, 445, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 640x400@85Hz */ + { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, + 736, 832, 0, 400, 401, 404, 445, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 720x400@85Hz */ + { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, + 828, 936, 0, 400, 401, 404, 446, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 640x480@60Hz */ + { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, + 752, 800, 0, 480, 489, 492, 525, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 640x480@72Hz */ + { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, + 704, 832, 0, 480, 489, 492, 520, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 640x480@75Hz */ + { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, + 720, 840, 0, 480, 481, 484, 500, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 640x480@85Hz */ + { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, + 752, 832, 0, 480, 481, 484, 509, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 800x600@56Hz */ + { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, + 896, 1024, 0, 600, 601, 603, 625, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 800x600@60Hz */ + { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, + 968, 1056, 0, 600, 601, 605, 628, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 800x600@72Hz */ + { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, + 976, 1040, 0, 600, 637, 643, 666, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 800x600@75Hz */ + { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, + 896, 1056, 0, 600, 601, 604, 625, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 800x600@85Hz */ + { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, + 896, 1048, 0, 600, 601, 604, 631, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 848x480@60Hz */ + { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, + 976, 1088, 0, 480, 486, 494, 517, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1024x768@43Hz, interlace */ + { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, + 1208, 1264, 0, 768, 768, 772, 817, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | + DRM_MODE_FLAG_INTERLACE) }, + /* 1024x768@60Hz */ + { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, + 1184, 1344, 0, 768, 771, 777, 806, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1024x768@70Hz */ + { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, + 1184, 1328, 0, 768, 771, 777, 806, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1024x768@75Hz */ + { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, + 1136, 1312, 0, 768, 769, 772, 800, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1024x768@85Hz */ + { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, + 1072, 1376, 0, 768, 769, 772, 808, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1152x864@75Hz */ + { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, + 1344, 1600, 0, 864, 865, 868, 900, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x768@60Hz */ + { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, + 1472, 1664, 0, 768, 771, 778, 798, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x768@75Hz */ + { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, + 1488, 1696, 0, 768, 771, 778, 805, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1280x768@85Hz */ + { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, + 1496, 1712, 0, 768, 771, 778, 809, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x800@60Hz */ + { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, + 1480, 1680, 0, 800, 803, 809, 831, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 1280x800@75Hz */ + { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, + 1488, 1696, 0, 800, 803, 809, 838, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x800@85Hz */ + { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, + 1496, 1712, 0, 800, 803, 809, 843, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x960@60Hz */ + { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, + 1488, 1800, 0, 960, 961, 964, 1000, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x960@85Hz */ + { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, + 1504, 1728, 0, 960, 961, 964, 1011, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x1024@60Hz */ + { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, + 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x1024@75Hz */ + { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, + 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1280x1024@85Hz */ + { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, + 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1360x768@60Hz */ + { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, + 1536, 1792, 0, 768, 771, 777, 795, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1440x1050@60Hz */ + { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, + 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1440x1050@75Hz */ + { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, + 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1440x1050@85Hz */ + { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, + 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1440x900@60Hz */ + { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, + 1672, 1904, 0, 900, 903, 909, 934, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1440x900@75Hz */ + { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, + 1688, 1936, 0, 900, 903, 909, 942, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1440x900@85Hz */ + { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, + 1696, 1952, 0, 900, 903, 909, 948, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1600x1200@60Hz */ + { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, + 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1600x1200@65Hz */ + { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, + 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1600x1200@70Hz */ + { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, + 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1600x1200@75Hz */ + { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 2025000, 1600, 1664, + 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1600x1200@85Hz */ + { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, + 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1680x1050@60Hz */ + { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, + 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1680x1050@75Hz */ + { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, + 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1680x1050@85Hz */ + { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, + 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1792x1344@60Hz */ + { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, + 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1729x1344@75Hz */ + { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, + 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1853x1392@60Hz */ + { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, + 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1856x1392@75Hz */ + { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, + 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1920x1200@60Hz */ + { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, + 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1920x1200@75Hz */ + { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, + 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1920x1200@85Hz */ + { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, + 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1920x1440@60Hz */ + { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, + 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 1920x1440@75Hz */ + { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, + 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 2560x1600@60Hz */ + { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, + 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 2560x1600@75HZ */ + { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, + 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 2560x1600@85HZ */ + { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, + 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, +}; + /** * drm_mode_std - convert standard mode info (width, height, refresh) into mode * @t: standard timing params -- cgit v0.10.2 From 559ee21d261a54c42594ef9405d27e9008eedf44 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Thu, 3 Sep 2009 09:33:47 +0800 Subject: drm/kms: try to find the std mode in DMT table When we need to add the standard timing mode, we will firstly check whether it can be found in DMT table by comparing the hdisplay/vdisplay/vfresh_rate. If it can't be found, then we will use the cvt/gtf to add the required mode. If it can be found, it will be returned. At the same time the function of drm_mode_vrefresh is also fixed. It will return the result of actual refresh_rate plus 0.5. For example: When the calculated value is 84.9, then the fresh_rate is 85. When the calculated value is 70.02, then the fresh_rate is 70. Signed-off-by: Zhao Yakui Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index e64eb6b..f84a98f 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -480,6 +480,26 @@ static struct drm_display_mode drm_dmt_modes[] = { DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, }; +static struct drm_display_mode *drm_find_dmt(struct drm_device *dev, + int hsize, int vsize, int fresh) +{ + int i, count; + struct drm_display_mode *ptr, *mode; + + count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); + mode = NULL; + for (i = 0; i < count; i++) { + ptr = &drm_dmt_modes[i]; + if (hsize == ptr->hdisplay && + vsize == ptr->vdisplay && + fresh == drm_mode_vrefresh(ptr)) { + /* get the expected default mode */ + mode = drm_mode_duplicate(dev, ptr); + break; + } + } + return mode; +} /** * drm_mode_std - convert standard mode info (width, height, refresh) into mode * @t: standard timing params @@ -516,16 +536,22 @@ struct drm_display_mode *drm_mode_std(struct drm_device *dev, vsize = (hsize * 4) / 5; else vsize = (hsize * 9) / 16; - + /* HDTV hack */ + if (hsize == 1360 && vsize == 765 && vrefresh_rate == 60) { + mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); + mode->hdisplay = 1366; + mode->vsync_start = mode->vsync_start - 1; + mode->vsync_end = mode->vsync_end - 1; + return mode; + } mode = NULL; + /* check whether it can be found in default mode table */ + mode = drm_find_dmt(dev, hsize, vsize, vrefresh_rate); + if (mode) + return mode; + switch (timing_level) { case LEVEL_DMT: - mode = drm_mode_create(dev); - if (mode) { - mode->hdisplay = hsize; - mode->vdisplay = vsize; - drm_mode_set_name(mode); - } break; case LEVEL_GTF: mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index ab6e70e..49404ce 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -566,7 +566,9 @@ EXPORT_SYMBOL(drm_mode_height); * FIXME: why is this needed? shouldn't vrefresh be set already? * * RETURNS: - * Vertical refresh rate of @mode x 1000. For precision reasons. + * Vertical refresh rate. It will be the result of actual value plus 0.5. + * If it is 70.288, it will return 70Hz. + * If it is 59.6, it will return 60Hz. */ int drm_mode_vrefresh(struct drm_display_mode *mode) { @@ -576,14 +578,13 @@ int drm_mode_vrefresh(struct drm_display_mode *mode) if (mode->vrefresh > 0) refresh = mode->vrefresh; else if (mode->htotal > 0 && mode->vtotal > 0) { + int vtotal; + vtotal = mode->vtotal; /* work out vrefresh the value will be x1000 */ calc_val = (mode->clock * 1000); - calc_val /= mode->htotal; - calc_val *= 1000; - calc_val /= mode->vtotal; + refresh = (calc_val + vtotal / 2) / vtotal; - refresh = calc_val; if (mode->flags & DRM_MODE_FLAG_INTERLACE) refresh *= 2; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) -- cgit v0.10.2 From f0fda0a47b26aba986fe65897891956c1792b526 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Thu, 3 Sep 2009 09:33:48 +0800 Subject: drm/kms: add a function that can add the mode for the output device without EDID Add a function that can be used to add the default mode for the output device without EDID. It will add the default mode that meets with the requirements of given hdisplay/vdisplay limit. Signed-off-by: Zhao Yakui Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index f84a98f..e2d5f51 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1215,3 +1215,49 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) return num_modes; } EXPORT_SYMBOL(drm_add_edid_modes); + +/** + * drm_add_modes_noedid - add modes for the connectors without EDID + * @connector: connector we're probing + * @hdisplay: the horizontal display limit + * @vdisplay: the vertical display limit + * + * Add the specified modes to the connector's mode list. Only when the + * hdisplay/vdisplay is not beyond the given limit, it will be added. + * + * Return number of modes added or 0 if we couldn't find any. + */ +int drm_add_modes_noedid(struct drm_connector *connector, + int hdisplay, int vdisplay) +{ + int i, count, num_modes = 0; + struct drm_display_mode *mode, *ptr; + struct drm_device *dev = connector->dev; + + count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); + if (hdisplay < 0) + hdisplay = 0; + if (vdisplay < 0) + vdisplay = 0; + + for (i = 0; i < count; i++) { + ptr = &drm_dmt_modes[i]; + if (hdisplay && vdisplay) { + /* + * Only when two are valid, they will be used to check + * whether the mode should be added to the mode list of + * the connector. + */ + if (ptr->hdisplay > hdisplay || + ptr->vdisplay > vdisplay) + continue; + } + mode = drm_mode_duplicate(dev, ptr); + if (mode) { + drm_mode_probed_add(connector, mode); + num_modes++; + } + } + return num_modes; +} +EXPORT_SYMBOL(drm_add_modes_noedid); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index b0427a7..ae1e9e1 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -750,4 +750,6 @@ extern struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, extern struct drm_display_mode *drm_gtf_mode(struct drm_device *dev, int hdisplay, int vdisplay, int vrefresh, bool interlaced, int margins); +extern int drm_add_modes_noedid(struct drm_connector *connector, + int hdisplay, int vdisplay); #endif /* __DRM_CRTC_H__ */ -- cgit v0.10.2 From 50fe4cfdc759fb3c0cffc3b90281efb139631fb7 Mon Sep 17 00:00:00 2001 From: ykzhao Date: Thu, 3 Sep 2009 14:30:04 +0800 Subject: drm/kms/i915: Add the default mode for CRT output without EDID Add the default mode for every output device when there is no mode for it. Signed-off-by: Zhao Yakui Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index e7e6c25..6f4b444 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -109,8 +109,11 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, } count = (*connector_funcs->get_modes)(connector); - if (!count) - return 0; + if (!count) { + count = drm_add_modes_noedid(connector, 800, 600); + if (!count) + return 0; + } drm_mode_connector_list_update(connector); -- cgit v0.10.2 From 575dc34ee0de867ba83abf25998e0963bff451fa Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 7 Sep 2009 18:43:26 +1000 Subject: drm/kms: remove old std mode fallback code. The new code adds modes in the helper, which makes more sense I disliked the non-driver code adding modes. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index 6f4b444..c9a50c7 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -33,15 +33,6 @@ #include "drm_crtc.h" #include "drm_crtc_helper.h" -/* - * Detailed mode info for 800x600@60Hz - */ -static struct drm_display_mode std_modes[] = { - { DRM_MODE("800x600", DRM_MODE_TYPE_DEFAULT, 40000, 800, 840, - 968, 1056, 0, 600, 601, 605, 628, 0, - DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, -}; - static void drm_mode_validate_flag(struct drm_connector *connector, int flags) { @@ -133,7 +124,6 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, mode); } - drm_mode_prune_invalid(dev, &connector->modes, true); if (list_empty(&connector->modes)) @@ -169,40 +159,6 @@ int drm_helper_probe_connector_modes(struct drm_device *dev, uint32_t maxX, } EXPORT_SYMBOL(drm_helper_probe_connector_modes); -static void drm_helper_add_std_modes(struct drm_device *dev, - struct drm_connector *connector) -{ - struct drm_display_mode *mode, *t; - int i; - - for (i = 0; i < ARRAY_SIZE(std_modes); i++) { - struct drm_display_mode *stdmode; - - /* - * When no valid EDID modes are available we end up - * here and bailed in the past, now we add some standard - * modes and move on. - */ - stdmode = drm_mode_duplicate(dev, &std_modes[i]); - drm_mode_probed_add(connector, stdmode); - drm_mode_list_concat(&connector->probed_modes, - &connector->modes); - - DRM_DEBUG_KMS("Adding mode %s to %s\n", stdmode->name, - drm_get_connector_name(connector)); - } - drm_mode_sort(&connector->modes); - - DRM_DEBUG_KMS("Added std modes on %s\n", - drm_get_connector_name(connector)); - list_for_each_entry_safe(mode, t, &connector->modes, head) { - mode->vrefresh = drm_mode_vrefresh(mode); - - drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V); - drm_mode_debug_printmodeline(mode); - } -} - /** * drm_helper_encoder_in_use - check if a given encoder is in use * @encoder: encoder to check @@ -982,7 +938,6 @@ bool drm_helper_plugged_event(struct drm_device *dev) */ bool drm_helper_initial_config(struct drm_device *dev) { - struct drm_connector *connector; int count = 0; count = drm_helper_probe_connector_modes(dev, @@ -990,16 +945,9 @@ bool drm_helper_initial_config(struct drm_device *dev) dev->mode_config.max_height); /* - * None of the available connectors had any modes, so add some - * and try to light them up anyway + * we shouldn't end up with no modes here. */ - if (!count) { - DRM_ERROR("connectors have no modes, using standard modes\n"); - list_for_each_entry(connector, - &dev->mode_config.connector_list, - head) - drm_helper_add_std_modes(dev, connector); - } + WARN(!count, "Connected connector with 0 modes\n"); drm_setup_crtcs(dev); -- cgit v0.10.2 From a4f3d55cb0b8e1199e352c30ea9a264cef9c1ae1 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sat, 5 Sep 2009 14:09:20 +0100 Subject: backlight: Add WM831x backlight driver The WM831x series of PMICs provide DC-DC boost convertors and current sinks which can be used together to drive LEDs for use as backlights. Expose this functionality via the backlight API. Since when used in this configuration the current sink and boost convertor are very tightly coupled with a multi-stage startup for the current sink which overlaps with the boost convertor startup this driver bypasses the regulator API. Machine inititialisation is responsible for ensuring that the regulators are not accessed via both APIs. Signed-off-by: Mark Brown Signed-off-by: Richard Purdie diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig index f9d19be..f86dbfd 100644 --- a/drivers/video/backlight/Kconfig +++ b/drivers/video/backlight/Kconfig @@ -229,3 +229,10 @@ config BACKLIGHT_SAHARA help If you have a Tabletkiosk Sahara Touch-iT, say y to enable the backlight driver. + +config BACKLIGHT_WM831X + tristate "WM831x PMIC Backlight Driver" + depends on BACKLIGHT_CLASS_DEVICE && MFD_WM831X + help + If you have a backlight driven by the ISINK and DCDC of a + WM831x PMIC say y to enable the backlight driver for it. diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile index 4eb178c..df0b67c 100644 --- a/drivers/video/backlight/Makefile +++ b/drivers/video/backlight/Makefile @@ -24,4 +24,5 @@ obj-$(CONFIG_BACKLIGHT_DA903X) += da903x_bl.o obj-$(CONFIG_BACKLIGHT_MBP_NVIDIA) += mbp_nvidia_bl.o obj-$(CONFIG_BACKLIGHT_TOSA) += tosa_bl.o obj-$(CONFIG_BACKLIGHT_SAHARA) += kb3886_bl.o +obj-$(CONFIG_BACKLIGHT_WM831X) += wm831x_bl.o diff --git a/drivers/video/backlight/wm831x_bl.c b/drivers/video/backlight/wm831x_bl.c new file mode 100644 index 0000000..467bdb7 --- /dev/null +++ b/drivers/video/backlight/wm831x_bl.c @@ -0,0 +1,250 @@ +/* + * Backlight driver for Wolfson Microelectronics WM831x PMICs + * + * Copyright 2009 Wolfson Microelectonics plc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +struct wm831x_backlight_data { + struct wm831x *wm831x; + int isink_reg; + int current_brightness; +}; + +static int wm831x_backlight_set(struct backlight_device *bl, int brightness) +{ + struct wm831x_backlight_data *data = bl_get_data(bl); + struct wm831x *wm831x = data->wm831x; + int power_up = !data->current_brightness && brightness; + int power_down = data->current_brightness && !brightness; + int ret; + + if (power_up) { + /* Enable the ISINK */ + ret = wm831x_set_bits(wm831x, data->isink_reg, + WM831X_CS1_ENA, WM831X_CS1_ENA); + if (ret < 0) + goto err; + + /* Enable the DC-DC */ + ret = wm831x_set_bits(wm831x, WM831X_DCDC_ENABLE, + WM831X_DC4_ENA, WM831X_DC4_ENA); + if (ret < 0) + goto err; + } + + if (power_down) { + /* DCDC first */ + ret = wm831x_set_bits(wm831x, WM831X_DCDC_ENABLE, + WM831X_DC4_ENA, 0); + if (ret < 0) + goto err; + + /* ISINK */ + ret = wm831x_set_bits(wm831x, data->isink_reg, + WM831X_CS1_DRIVE | WM831X_CS1_ENA, 0); + if (ret < 0) + goto err; + } + + /* Set the new brightness */ + ret = wm831x_set_bits(wm831x, data->isink_reg, + WM831X_CS1_ISEL_MASK, brightness); + if (ret < 0) + goto err; + + if (power_up) { + /* Drive current through the ISINK */ + ret = wm831x_set_bits(wm831x, data->isink_reg, + WM831X_CS1_DRIVE, WM831X_CS1_DRIVE); + if (ret < 0) + return ret; + } + + data->current_brightness = brightness; + + return 0; + +err: + /* If we were in the middle of a power transition always shut down + * for safety. + */ + if (power_up || power_down) { + wm831x_set_bits(wm831x, WM831X_DCDC_ENABLE, WM831X_DC4_ENA, 0); + wm831x_set_bits(wm831x, data->isink_reg, WM831X_CS1_ENA, 0); + } + + return ret; +} + +static int wm831x_backlight_update_status(struct backlight_device *bl) +{ + int brightness = bl->props.brightness; + + if (bl->props.power != FB_BLANK_UNBLANK) + brightness = 0; + + if (bl->props.fb_blank != FB_BLANK_UNBLANK) + brightness = 0; + + if (bl->props.state & BL_CORE_SUSPENDED) + brightness = 0; + + return wm831x_backlight_set(bl, brightness); +} + +static int wm831x_backlight_get_brightness(struct backlight_device *bl) +{ + struct wm831x_backlight_data *data = bl_get_data(bl); + return data->current_brightness; +} + +static struct backlight_ops wm831x_backlight_ops = { + .options = BL_CORE_SUSPENDRESUME, + .update_status = wm831x_backlight_update_status, + .get_brightness = wm831x_backlight_get_brightness, +}; + +static int wm831x_backlight_probe(struct platform_device *pdev) +{ + struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); + struct wm831x_pdata *wm831x_pdata; + struct wm831x_backlight_pdata *pdata; + struct wm831x_backlight_data *data; + struct backlight_device *bl; + int ret, i, max_isel, isink_reg, dcdc_cfg; + + /* We need platform data */ + if (pdev->dev.parent->platform_data) { + wm831x_pdata = pdev->dev.parent->platform_data; + pdata = wm831x_pdata->backlight; + } else { + pdata = NULL; + } + + if (!pdata) { + dev_err(&pdev->dev, "No platform data supplied\n"); + return -EINVAL; + } + + /* Figure out the maximum current we can use */ + for (i = 0; i < WM831X_ISINK_MAX_ISEL; i++) { + if (wm831x_isinkv_values[i] > pdata->max_uA) + break; + } + + if (i == 0) { + dev_err(&pdev->dev, "Invalid max_uA: %duA\n", pdata->max_uA); + return -EINVAL; + } + max_isel = i - 1; + + if (pdata->max_uA != wm831x_isinkv_values[max_isel]) + dev_warn(&pdev->dev, + "Maximum current is %duA not %duA as requested\n", + wm831x_isinkv_values[max_isel], pdata->max_uA); + + switch (pdata->isink) { + case 1: + isink_reg = WM831X_CURRENT_SINK_1; + dcdc_cfg = 0; + break; + case 2: + isink_reg = WM831X_CURRENT_SINK_2; + dcdc_cfg = WM831X_DC4_FBSRC; + break; + default: + dev_err(&pdev->dev, "Invalid ISINK %d\n", pdata->isink); + return -EINVAL; + } + + /* Configure the ISINK to use for feedback */ + ret = wm831x_reg_unlock(wm831x); + if (ret < 0) + return ret; + + ret = wm831x_set_bits(wm831x, WM831X_DC4_CONTROL, WM831X_DC4_FBSRC, + dcdc_cfg); + + wm831x_reg_lock(wm831x); + if (ret < 0) + return ret; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + + data->wm831x = wm831x; + data->current_brightness = 0; + data->isink_reg = isink_reg; + + bl = backlight_device_register("wm831x", &pdev->dev, + data, &wm831x_backlight_ops); + if (IS_ERR(bl)) { + dev_err(&pdev->dev, "failed to register backlight\n"); + kfree(data); + return PTR_ERR(bl); + } + + bl->props.max_brightness = max_isel; + bl->props.brightness = max_isel; + + platform_set_drvdata(pdev, bl); + + /* Disable the DCDC if it was started so we can bootstrap */ + wm831x_set_bits(wm831x, WM831X_DCDC_ENABLE, WM831X_DC4_ENA, 0); + + + backlight_update_status(bl); + + return 0; +} + +static int wm831x_backlight_remove(struct platform_device *pdev) +{ + struct backlight_device *bl = platform_get_drvdata(pdev); + struct wm831x_backlight_data *data = bl_get_data(bl); + + backlight_device_unregister(bl); + kfree(data); + return 0; +} + +static struct platform_driver wm831x_backlight_driver = { + .driver = { + .name = "wm831x-backlight", + .owner = THIS_MODULE, + }, + .probe = wm831x_backlight_probe, + .remove = wm831x_backlight_remove, +}; + +static int __init wm831x_backlight_init(void) +{ + return platform_driver_register(&wm831x_backlight_driver); +} +module_init(wm831x_backlight_init); + +static void __exit wm831x_backlight_exit(void) +{ + platform_driver_unregister(&wm831x_backlight_driver); +} +module_exit(wm831x_backlight_exit); + +MODULE_DESCRIPTION("Backlight Driver for WM831x PMICs"); +MODULE_AUTHOR("Mark Brown Date: Mon, 7 Sep 2009 14:19:54 +0100 Subject: backlight: mbp_nvidia_bl: add support for MacBookAir 1,1 Add LCD backlight support for the Intel GMA965 found in the MacBookAir 1,1. Signed-off-by: Henrik Rydberg Acked-by: Matthew Garrett Signed-off-by: Andrew Morton Signed-off-by: Richard Purdie diff --git a/drivers/video/backlight/mbp_nvidia_bl.c b/drivers/video/backlight/mbp_nvidia_bl.c index 3bb4c0a..9fc7a53 100644 --- a/drivers/video/backlight/mbp_nvidia_bl.c +++ b/drivers/video/backlight/mbp_nvidia_bl.c @@ -166,6 +166,15 @@ static const struct dmi_system_id __initdata mbp_device_table[] = { }, { .callback = mbp_dmi_match, + .ident = "MacBookAir 1,1", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "MacBookAir1,1"), + }, + .driver_data = (void *)&intel_chipset_data, + }, + { + .callback = mbp_dmi_match, .ident = "MacBook 5,1", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), -- cgit v0.10.2 From c746b5519a88b8803d43946ad06326ece4829116 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sat, 5 Sep 2009 14:09:21 +0100 Subject: leds: Add WM831x status LED driver The WM831x devices feature two software controlled status LEDs with hardware assisted blinking. The device can also autonomously control the LEDs based on a selection of sources. This can be configured at boot time using either platform data or the chip OTP. A sysfs file in the style of that for triggers allowing the control source to be configured at run time. Triggers can't be used here since they can't depend on the implementation details of a specific LED type. Signed-off-by: Mark Brown Signed-off-by: Richard Purdie diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 7c8e7122a..edfd4e3 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -195,6 +195,13 @@ config LEDS_PCA955X LED driver chips accessed via the I2C bus. Supported devices include PCA9550, PCA9551, PCA9552, and PCA9553. +config LEDS_WM831X_STATUS + tristate "LED support for status LEDs on WM831x PMICs" + depends on LEDS_CLASS && MFD_WM831X + help + This option enables support for the status LEDs of the WM831x + series of PMICs. + config LEDS_WM8350 tristate "LED Support for WM8350 AudioPlus PMIC" depends on LEDS_CLASS && MFD_WM8350 diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index e8cdcf7..46d7270 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o obj-$(CONFIG_LEDS_FSG) += leds-fsg.o obj-$(CONFIG_LEDS_PCA955X) += leds-pca955x.o obj-$(CONFIG_LEDS_DA903X) += leds-da903x.o +obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o obj-$(CONFIG_LEDS_PWM) += leds-pwm.o diff --git a/drivers/leds/leds-wm831x-status.c b/drivers/leds/leds-wm831x-status.c new file mode 100644 index 0000000..c586d05 --- /dev/null +++ b/drivers/leds/leds-wm831x-status.c @@ -0,0 +1,341 @@ +/* + * LED driver for WM831x status LEDs + * + * Copyright(C) 2009 Wolfson Microelectronics PLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +struct wm831x_status { + struct led_classdev cdev; + struct wm831x *wm831x; + struct work_struct work; + struct mutex mutex; + + spinlock_t value_lock; + int reg; /* Control register */ + int reg_val; /* Control register value */ + + int blink; + int blink_time; + int blink_cyc; + int src; + enum led_brightness brightness; +}; + +#define to_wm831x_status(led_cdev) \ + container_of(led_cdev, struct wm831x_status, cdev) + +static void wm831x_status_work(struct work_struct *work) +{ + struct wm831x_status *led = container_of(work, struct wm831x_status, + work); + unsigned long flags; + + mutex_lock(&led->mutex); + + led->reg_val &= ~(WM831X_LED_SRC_MASK | WM831X_LED_MODE_MASK | + WM831X_LED_DUTY_CYC_MASK | WM831X_LED_DUR_MASK); + + spin_lock_irqsave(&led->value_lock, flags); + + led->reg_val |= led->src << WM831X_LED_SRC_SHIFT; + if (led->blink) { + led->reg_val |= 2 << WM831X_LED_MODE_SHIFT; + led->reg_val |= led->blink_time << WM831X_LED_DUR_SHIFT; + led->reg_val |= led->blink_cyc; + } else { + if (led->brightness != LED_OFF) + led->reg_val |= 1 << WM831X_LED_MODE_SHIFT; + } + + spin_unlock_irqrestore(&led->value_lock, flags); + + wm831x_reg_write(led->wm831x, led->reg, led->reg_val); + + mutex_unlock(&led->mutex); +} + +static void wm831x_status_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + struct wm831x_status *led = to_wm831x_status(led_cdev); + unsigned long flags; + + spin_lock_irqsave(&led->value_lock, flags); + led->brightness = value; + if (value == LED_OFF) + led->blink = 0; + schedule_work(&led->work); + spin_unlock_irqrestore(&led->value_lock, flags); +} + +static int wm831x_status_blink_set(struct led_classdev *led_cdev, + unsigned long *delay_on, + unsigned long *delay_off) +{ + struct wm831x_status *led = to_wm831x_status(led_cdev); + unsigned long flags; + int ret = 0; + + /* Pick some defaults if we've not been given times */ + if (*delay_on == 0 && *delay_off == 0) { + *delay_on = 250; + *delay_off = 250; + } + + spin_lock_irqsave(&led->value_lock, flags); + + /* We only have a limited selection of settings, see if we can + * support the configuration we're being given */ + switch (*delay_on) { + case 1000: + led->blink_time = 0; + break; + case 250: + led->blink_time = 1; + break; + case 125: + led->blink_time = 2; + break; + case 62: + case 63: + /* Actually 62.5ms */ + led->blink_time = 3; + break; + default: + ret = -EINVAL; + break; + } + + if (ret == 0) { + switch (*delay_off / *delay_on) { + case 1: + led->blink_cyc = 0; + break; + case 3: + led->blink_cyc = 1; + break; + case 4: + led->blink_cyc = 2; + break; + case 8: + led->blink_cyc = 3; + break; + default: + ret = -EINVAL; + break; + } + } + + if (ret == 0) + led->blink = 1; + else + led->blink = 0; + + /* Always update; if we fail turn off blinking since we expect + * a software fallback. */ + schedule_work(&led->work); + + spin_unlock_irqrestore(&led->value_lock, flags); + + return ret; +} + +static const char *led_src_texts[] = { + "otp", + "power", + "charger", + "soft", +}; + +static ssize_t wm831x_status_src_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct wm831x_status *led = to_wm831x_status(led_cdev); + int i; + ssize_t ret = 0; + + mutex_lock(&led->mutex); + + for (i = 0; i < ARRAY_SIZE(led_src_texts); i++) + if (i == led->src) + ret += sprintf(&buf[ret], "[%s] ", led_src_texts[i]); + else + ret += sprintf(&buf[ret], "%s ", led_src_texts[i]); + + mutex_unlock(&led->mutex); + + ret += sprintf(&buf[ret], "\n"); + + return ret; +} + +static ssize_t wm831x_status_src_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct wm831x_status *led = to_wm831x_status(led_cdev); + char name[20]; + int i; + size_t len; + + name[sizeof(name) - 1] = '\0'; + strncpy(name, buf, sizeof(name) - 1); + len = strlen(name); + + if (len && name[len - 1] == '\n') + name[len - 1] = '\0'; + + for (i = 0; i < ARRAY_SIZE(led_src_texts); i++) { + if (!strcmp(name, led_src_texts[i])) { + mutex_lock(&led->mutex); + + led->src = i; + schedule_work(&led->work); + + mutex_unlock(&led->mutex); + } + } + + return size; +} + +static DEVICE_ATTR(src, 0644, wm831x_status_src_show, wm831x_status_src_store); + +static int wm831x_status_probe(struct platform_device *pdev) +{ + struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); + struct wm831x_pdata *chip_pdata; + struct wm831x_status_pdata pdata; + struct wm831x_status *drvdata; + struct resource *res; + int id = pdev->id % ARRAY_SIZE(chip_pdata->status); + int ret; + + res = platform_get_resource(pdev, IORESOURCE_IO, 0); + if (res == NULL) { + dev_err(&pdev->dev, "No I/O resource\n"); + ret = -EINVAL; + goto err; + } + + drvdata = kzalloc(sizeof(struct wm831x_status), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + dev_set_drvdata(&pdev->dev, drvdata); + + drvdata->wm831x = wm831x; + drvdata->reg = res->start; + + if (wm831x->dev->platform_data) + chip_pdata = wm831x->dev->platform_data; + else + chip_pdata = NULL; + + memset(&pdata, 0, sizeof(pdata)); + if (chip_pdata && chip_pdata->status[id]) + memcpy(&pdata, chip_pdata->status[id], sizeof(pdata)); + else + pdata.name = dev_name(&pdev->dev); + + mutex_init(&drvdata->mutex); + INIT_WORK(&drvdata->work, wm831x_status_work); + spin_lock_init(&drvdata->value_lock); + + /* We cache the configuration register and read startup values + * from it. */ + drvdata->reg_val = wm831x_reg_read(wm831x, drvdata->reg); + + if (drvdata->reg_val & WM831X_LED_MODE_MASK) + drvdata->brightness = LED_FULL; + else + drvdata->brightness = LED_OFF; + + /* Set a default source if configured, otherwise leave the + * current hardware setting. + */ + if (pdata.default_src == WM831X_STATUS_PRESERVE) { + drvdata->src = drvdata->reg_val; + drvdata->src &= WM831X_LED_SRC_MASK; + drvdata->src >>= WM831X_LED_SRC_SHIFT; + } else { + drvdata->src = pdata.default_src - 1; + } + + drvdata->cdev.name = pdata.name; + drvdata->cdev.default_trigger = pdata.default_trigger; + drvdata->cdev.brightness_set = wm831x_status_set; + drvdata->cdev.blink_set = wm831x_status_blink_set; + + ret = led_classdev_register(wm831x->dev, &drvdata->cdev); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to register LED: %d\n", ret); + goto err_led; + } + + ret = device_create_file(drvdata->cdev.dev, &dev_attr_src); + if (ret != 0) + dev_err(&pdev->dev, + "No source control for LED: %d\n", ret); + + return 0; + +err_led: + led_classdev_unregister(&drvdata->cdev); + kfree(drvdata); +err: + return ret; +} + +static int wm831x_status_remove(struct platform_device *pdev) +{ + struct wm831x_status *drvdata = platform_get_drvdata(pdev); + + device_remove_file(drvdata->cdev.dev, &dev_attr_src); + led_classdev_unregister(&drvdata->cdev); + kfree(drvdata); + + return 0; +} + +static struct platform_driver wm831x_status_driver = { + .driver = { + .name = "wm831x-status", + .owner = THIS_MODULE, + }, + .probe = wm831x_status_probe, + .remove = wm831x_status_remove, +}; + +static int __devinit wm831x_status_init(void) +{ + return platform_driver_register(&wm831x_status_driver); +} +module_init(wm831x_status_init); + +static void wm831x_status_exit(void) +{ + platform_driver_unregister(&wm831x_status_driver); +} +module_exit(wm831x_status_exit); + +MODULE_AUTHOR("Mark Brown "); +MODULE_DESCRIPTION("WM831x status LED driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:wm831x-status"); diff --git a/include/linux/mfd/wm831x/status.h b/include/linux/mfd/wm831x/status.h new file mode 100644 index 0000000..6bc090d --- /dev/null +++ b/include/linux/mfd/wm831x/status.h @@ -0,0 +1,34 @@ +/* + * include/linux/mfd/wm831x/status.h -- Status LEDs for WM831x + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __MFD_WM831X_STATUS_H__ +#define __MFD_WM831X_STATUS_H__ + +#define WM831X_LED_SRC_MASK 0xC000 /* LED_SRC - [15:14] */ +#define WM831X_LED_SRC_SHIFT 14 /* LED_SRC - [15:14] */ +#define WM831X_LED_SRC_WIDTH 2 /* LED_SRC - [15:14] */ +#define WM831X_LED_MODE_MASK 0x0300 /* LED_MODE - [9:8] */ +#define WM831X_LED_MODE_SHIFT 8 /* LED_MODE - [9:8] */ +#define WM831X_LED_MODE_WIDTH 2 /* LED_MODE - [9:8] */ +#define WM831X_LED_SEQ_LEN_MASK 0x0030 /* LED_SEQ_LEN - [5:4] */ +#define WM831X_LED_SEQ_LEN_SHIFT 4 /* LED_SEQ_LEN - [5:4] */ +#define WM831X_LED_SEQ_LEN_WIDTH 2 /* LED_SEQ_LEN - [5:4] */ +#define WM831X_LED_DUR_MASK 0x000C /* LED_DUR - [3:2] */ +#define WM831X_LED_DUR_SHIFT 2 /* LED_DUR - [3:2] */ +#define WM831X_LED_DUR_WIDTH 2 /* LED_DUR - [3:2] */ +#define WM831X_LED_DUTY_CYC_MASK 0x0003 /* LED_DUTY_CYC - [1:0] */ +#define WM831X_LED_DUTY_CYC_SHIFT 0 /* LED_DUTY_CYC - [1:0] */ +#define WM831X_LED_DUTY_CYC_WIDTH 2 /* LED_DUTY_CYC - [1:0] */ + +#endif -- cgit v0.10.2 From 2fea09222ab48517d729a7fb4542092cf428f528 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 6 Aug 2009 16:04:51 -0700 Subject: leds: gpio-leds: fix typographics fault [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Michal Simek Signed-off-by: Andrew Morton Signed-off-by: Richard Purdie diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c index 6b06638..7467980 100644 --- a/drivers/leds/leds-gpio.c +++ b/drivers/leds/leds-gpio.c @@ -80,7 +80,7 @@ static int __devinit create_gpio_led(const struct gpio_led *template, /* skip leds that aren't available */ if (!gpio_is_valid(template->gpio)) { - printk(KERN_INFO "Skipping unavilable LED gpio %d (%s)\n", + printk(KERN_INFO "Skipping unavailable LED gpio %d (%s)\n", template->gpio, template->name); return 0; } -- cgit v0.10.2 From 74cbe20294c9f54a0926d19235395cf8e22b7830 Mon Sep 17 00:00:00 2001 From: Thadeu Lima de Souza Cascardo Date: Thu, 6 Aug 2009 16:04:51 -0700 Subject: leds: fix coding style in worker thread code for ledtrig-gpio. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Thadeu Lima de Souza Cascardo Signed-off-by: Samuel R. C. Vale Signed-off-by: Andrew Morton Signed-off-by: Richard Purdie diff --git a/drivers/leds/ledtrig-gpio.c b/drivers/leds/ledtrig-gpio.c index 1bc5db4..f591337 100644 --- a/drivers/leds/ledtrig-gpio.c +++ b/drivers/leds/ledtrig-gpio.c @@ -44,22 +44,22 @@ static void gpio_trig_work(struct work_struct *work) struct gpio_trig_data, work); int tmp; - if (!gpio_data->gpio) - return; - - tmp = gpio_get_value(gpio_data->gpio); - if (gpio_data->inverted) - tmp = !tmp; - - if (tmp) { - if (gpio_data->desired_brightness) - led_set_brightness(gpio_data->led, - gpio_data->desired_brightness); - else - led_set_brightness(gpio_data->led, LED_FULL); - } else { - led_set_brightness(gpio_data->led, LED_OFF); - } + if (!gpio_data->gpio) + return; + + tmp = gpio_get_value(gpio_data->gpio); + if (gpio_data->inverted) + tmp = !tmp; + + if (tmp) { + if (gpio_data->desired_brightness) + led_set_brightness(gpio_data->led, + gpio_data->desired_brightness); + else + led_set_brightness(gpio_data->led, LED_FULL); + } else { + led_set_brightness(gpio_data->led, LED_OFF); + } } static ssize_t gpio_trig_brightness_show(struct device *dev, -- cgit v0.10.2 From 1e9bd9426c3dfc4a5383b224cebbced9c5e05998 Mon Sep 17 00:00:00 2001 From: Mario Schwalbe Date: Thu, 20 Aug 2009 12:39:48 +0200 Subject: backlight: Add support for new Apple machines. This patch adds support for the new Apple models MacBook 5,1, MacBook Pro 5,1, MacBook Pro 5,2, MacBook Pro 5,5. It's just a device table update. Signed-off-by: Mario Schwalbe Signed-off-by: Richard Purdie diff --git a/drivers/video/backlight/mbp_nvidia_bl.c b/drivers/video/backlight/mbp_nvidia_bl.c index 9fc7a53..9edb8d7 100644 --- a/drivers/video/backlight/mbp_nvidia_bl.c +++ b/drivers/video/backlight/mbp_nvidia_bl.c @@ -184,6 +184,15 @@ static const struct dmi_system_id __initdata mbp_device_table[] = { }, { .callback = mbp_dmi_match, + .ident = "MacBook 5,2", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "MacBook5,2"), + }, + .driver_data = (void *)&nvidia_chipset_data, + }, + { + .callback = mbp_dmi_match, .ident = "MacBookAir 2,1", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), @@ -200,6 +209,24 @@ static const struct dmi_system_id __initdata mbp_device_table[] = { }, .driver_data = (void *)&nvidia_chipset_data, }, + { + .callback = mbp_dmi_match, + .ident = "MacBookPro 5,2", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5,2"), + }, + .driver_data = (void *)&nvidia_chipset_data, + }, + { + .callback = mbp_dmi_match, + .ident = "MacBookPro 5,5", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5,5"), + }, + .driver_data = (void *)&nvidia_chipset_data, + }, { } }; -- cgit v0.10.2 From 85c5204a677bc1053cb636590859c32fd0cf6bf9 Mon Sep 17 00:00:00 2001 From: Richard Purdie Date: Mon, 7 Sep 2009 14:35:04 +0100 Subject: leds: Fix leds-pca9532 whitespace issues Signed-off-by: Richard Purdie 1690 || *delay_on < 6) @@ -227,7 +227,7 @@ static int pca9532_configure(struct i2c_client *client, break; case PCA9532_TYPE_LED: led->state = pled->state; - led->name = pled->name; + led->name = pled->name; led->ldev.name = led->name; led->ldev.brightness = LED_OFF; led->ldev.brightness_set = pca9532_set_brightness; @@ -254,7 +254,7 @@ static int pca9532_configure(struct i2c_client *client, data->idev->name = pled->name; data->idev->phys = "i2c/pca9532"; data->idev->id.bustype = BUS_HOST; - data->idev->id.vendor = 0x001f; + data->idev->id.vendor = 0x001f; data->idev->id.product = 0x0001; data->idev->id.version = 0x0100; data->idev->evbit[0] = BIT_MASK(EV_SND); -- cgit v0.10.2 From db3f520738a8c5bf593e13d4ac71f8da9ffcb964 Mon Sep 17 00:00:00 2001 From: Olaf Hering Date: Mon, 7 Sep 2009 14:37:27 +0100 Subject: leds: Fix LED names This is needed to get kde-powersave to work properly on some g4 powerbooks. From: Olaf Hering Signed-off-by: Greg Kroah-Hartman Signed-off-by: Richard Purdie diff --git a/drivers/leds/leds-cobalt-qube.c b/drivers/leds/leds-cobalt-qube.c index 059aa29..8816806 100644 --- a/drivers/leds/leds-cobalt-qube.c +++ b/drivers/leds/leds-cobalt-qube.c @@ -28,7 +28,7 @@ static void qube_front_led_set(struct led_classdev *led_cdev, } static struct led_classdev qube_front_led = { - .name = "qube-front", + .name = "qube::front", .brightness = LED_FULL, .brightness_set = qube_front_led_set, .default_trigger = "ide-disk", diff --git a/drivers/leds/leds-cobalt-raq.c b/drivers/leds/leds-cobalt-raq.c index 5f1ce81..defc212 100644 --- a/drivers/leds/leds-cobalt-raq.c +++ b/drivers/leds/leds-cobalt-raq.c @@ -49,7 +49,7 @@ static void raq_web_led_set(struct led_classdev *led_cdev, } static struct led_classdev raq_web_led = { - .name = "raq-web", + .name = "raq::web", .brightness_set = raq_web_led_set, }; @@ -70,7 +70,7 @@ static void raq_power_off_led_set(struct led_classdev *led_cdev, } static struct led_classdev raq_power_off_led = { - .name = "raq-power-off", + .name = "raq::power-off", .brightness_set = raq_power_off_led_set, .default_trigger = "power-off", }; diff --git a/drivers/macintosh/via-pmu-led.c b/drivers/macintosh/via-pmu-led.c index 55ad956..d242976 100644 --- a/drivers/macintosh/via-pmu-led.c +++ b/drivers/macintosh/via-pmu-led.c @@ -72,7 +72,7 @@ static void pmu_led_set(struct led_classdev *led_cdev, } static struct led_classdev pmu_led = { - .name = "pmu-front-led", + .name = "pmu-led::front", #ifdef CONFIG_ADB_PMU_LED_IDE .default_trigger = "ide-disk", #endif -- cgit v0.10.2 From 7f1be819cccea65dcd2a8c86de6369946b91c224 Mon Sep 17 00:00:00 2001 From: Antonio Ospite Date: Fri, 3 Jul 2009 16:18:45 +0200 Subject: leds: Fix indentation in LEDS_LP3944 Kconfig entry Signed-off-by: Antonio Ospite Signed-off-by: Richard Purdie diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index edfd4e3..e4f599f 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -150,9 +150,9 @@ config LEDS_LP3944 tristate "LED Support for N.S. LP3944 (Fun Light) I2C chip" depends on LEDS_CLASS && I2C help - This option enables support for LEDs connected to the National - Semiconductor LP3944 Lighting Management Unit (LMU) also known as - Fun Light Chip. + This option enables support for LEDs connected to the National + Semiconductor LP3944 Lighting Management Unit (LMU) also known as + Fun Light Chip. To compile this driver as a module, choose M here: the module will be called leds-lp3944. -- cgit v0.10.2 From 156ff0d473d3f5a11ba66e0b3debd9e50bd946e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 11 Jul 2009 22:52:44 +0200 Subject: backlight: move hp680-bl's probe function to .devinit.text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A pointer to hp680bl_probe is passed to the core via platform_driver_register and so the function must not disappear when the .init sections are discarded. Otherwise (if also having HOTPLUG=y) unbinding and binding a device to the driver via sysfs will result in an oops as does a device being registered late. Signed-off-by: Uwe Kleine-König Acked-by: Kristoffer Ericson Signed-off-by: Richard Purdie diff --git a/drivers/video/backlight/hp680_bl.c b/drivers/video/backlight/hp680_bl.c index 5be55a2..7fb4eef 100644 --- a/drivers/video/backlight/hp680_bl.c +++ b/drivers/video/backlight/hp680_bl.c @@ -103,7 +103,7 @@ static struct backlight_ops hp680bl_ops = { .update_status = hp680bl_set_intensity, }; -static int __init hp680bl_probe(struct platform_device *pdev) +static int __devinit hp680bl_probe(struct platform_device *pdev) { struct backlight_device *bd; -- cgit v0.10.2 From f16a5dba01ed942f427f56b0d1128251721275a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 11 Jul 2009 22:52:34 +0200 Subject: leds: move leds-clevo-mail's probe function to .devinit.text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A pointer to clevo_mail_led_probe is passed to the core via platform_driver_register and so the function must not disappear when the .init sections are discarded. Otherwise (if also having HOTPLUG=y) unbinding and binding a device to the driver via sysfs will result in an oops as does a device being registered late. Signed-off-by: Uwe Kleine-König Signed-off-by: Richard Purdie diff --git a/drivers/leds/leds-clevo-mail.c b/drivers/leds/leds-clevo-mail.c index 1813c84..8ee83ce 100644 --- a/drivers/leds/leds-clevo-mail.c +++ b/drivers/leds/leds-clevo-mail.c @@ -145,7 +145,7 @@ static struct led_classdev clevo_mail_led = { .flags = LED_CORE_SUSPENDRESUME, }; -static int __init clevo_mail_led_probe(struct platform_device *pdev) +static int __devinit clevo_mail_led_probe(struct platform_device *pdev) { return led_classdev_register(&pdev->dev, &clevo_mail_led); } -- cgit v0.10.2 From 5036cc41e07d6614350e329666ee8a79cea6f793 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 6 Aug 2009 16:07:10 -0700 Subject: backlight: spi driver for LMS283GF05 LCD ADd support for the SPI part of LMS283GF05 LCD. The LCD uses SPI for initialization and powerdown sequences. No further defails are specified in the datasheet about the initialization/powerdown sequence, just the magic numbers that have to be sent over SPI bus. This LCD can be found in the Aeronix Zipit Z2 handheld. Signed-off-by: Marek Vasut Signed-off-by: Andrew Morton Signed-off-by: Richard Purdie diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig index f86dbfd..c0d4a53 100644 --- a/drivers/video/backlight/Kconfig +++ b/drivers/video/backlight/Kconfig @@ -31,6 +31,13 @@ config LCD_CORGI Say y here to support the LCD panels usually found on SHARP corgi (C7x0) and spitz (Cxx00) models. +config LCD_LMS283GF05 + tristate "Samsung LMS283GF05 LCD" + depends on LCD_CLASS_DEVICE && SPI_MASTER && GENERIC_GPIO + help + SPI driver for Samsung LMS283GF05. This provides basic support + for powering the LCD up/down through a sysfs interface. + config LCD_LTV350QV tristate "Samsung LTV350QV LCD Panel" depends on LCD_CLASS_DEVICE && SPI_MASTER diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile index df0b67c..0abc014 100644 --- a/drivers/video/backlight/Makefile +++ b/drivers/video/backlight/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_LCD_CLASS_DEVICE) += lcd.o obj-$(CONFIG_LCD_CORGI) += corgi_lcd.o obj-$(CONFIG_LCD_HP700) += jornada720_lcd.o +obj-$(CONFIG_LCD_LMS283GF05) += lms283gf05.o obj-$(CONFIG_LCD_LTV350QV) += ltv350qv.o obj-$(CONFIG_LCD_ILI9320) += ili9320.o obj-$(CONFIG_LCD_PLATFORM) += platform_lcd.o diff --git a/drivers/video/backlight/lms283gf05.c b/drivers/video/backlight/lms283gf05.c new file mode 100644 index 0000000..447b542 --- /dev/null +++ b/drivers/video/backlight/lms283gf05.c @@ -0,0 +1,242 @@ +/* + * lms283gf05.c -- support for Samsung LMS283GF05 LCD + * + * Copyright (c) 2009 Marek Vasut + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include + +struct lms283gf05_state { + struct spi_device *spi; + struct lcd_device *ld; +}; + +struct lms283gf05_seq { + unsigned char reg; + unsigned short value; + unsigned char delay; +}; + +/* Magic sequences supplied by manufacturer, for details refer to datasheet */ +static struct lms283gf05_seq disp_initseq[] = { + /* REG, VALUE, DELAY */ + { 0x07, 0x0000, 0 }, + { 0x13, 0x0000, 10 }, + + { 0x11, 0x3004, 0 }, + { 0x14, 0x200F, 0 }, + { 0x10, 0x1a20, 0 }, + { 0x13, 0x0040, 50 }, + + { 0x13, 0x0060, 0 }, + { 0x13, 0x0070, 200 }, + + { 0x01, 0x0127, 0 }, + { 0x02, 0x0700, 0 }, + { 0x03, 0x1030, 0 }, + { 0x08, 0x0208, 0 }, + { 0x0B, 0x0620, 0 }, + { 0x0C, 0x0110, 0 }, + { 0x30, 0x0120, 0 }, + { 0x31, 0x0127, 0 }, + { 0x32, 0x0000, 0 }, + { 0x33, 0x0503, 0 }, + { 0x34, 0x0727, 0 }, + { 0x35, 0x0124, 0 }, + { 0x36, 0x0706, 0 }, + { 0x37, 0x0701, 0 }, + { 0x38, 0x0F00, 0 }, + { 0x39, 0x0F00, 0 }, + { 0x40, 0x0000, 0 }, + { 0x41, 0x0000, 0 }, + { 0x42, 0x013f, 0 }, + { 0x43, 0x0000, 0 }, + { 0x44, 0x013f, 0 }, + { 0x45, 0x0000, 0 }, + { 0x46, 0xef00, 0 }, + { 0x47, 0x013f, 0 }, + { 0x48, 0x0000, 0 }, + { 0x07, 0x0015, 30 }, + + { 0x07, 0x0017, 0 }, + + { 0x20, 0x0000, 0 }, + { 0x21, 0x0000, 0 }, + { 0x22, 0x0000, 0 } +}; + +static struct lms283gf05_seq disp_pdwnseq[] = { + { 0x07, 0x0016, 30 }, + + { 0x07, 0x0004, 0 }, + { 0x10, 0x0220, 20 }, + + { 0x13, 0x0060, 50 }, + + { 0x13, 0x0040, 50 }, + + { 0x13, 0x0000, 0 }, + { 0x10, 0x0000, 0 } +}; + + +static void lms283gf05_reset(unsigned long gpio, bool inverted) +{ + gpio_set_value(gpio, !inverted); + mdelay(100); + gpio_set_value(gpio, inverted); + mdelay(20); + gpio_set_value(gpio, !inverted); + mdelay(20); +} + +static void lms283gf05_toggle(struct spi_device *spi, + struct lms283gf05_seq *seq, int sz) +{ + char buf[3]; + int i; + + for (i = 0; i < sz; i++) { + buf[0] = 0x74; + buf[1] = 0x00; + buf[2] = seq[i].reg; + spi_write(spi, buf, 3); + + buf[0] = 0x76; + buf[1] = seq[i].value >> 8; + buf[2] = seq[i].value & 0xff; + spi_write(spi, buf, 3); + + mdelay(seq[i].delay); + } +} + +static int lms283gf05_power_set(struct lcd_device *ld, int power) +{ + struct lms283gf05_state *st = lcd_get_data(ld); + struct spi_device *spi = st->spi; + struct lms283gf05_pdata *pdata = spi->dev.platform_data; + + if (power) { + if (pdata) + lms283gf05_reset(pdata->reset_gpio, + pdata->reset_inverted); + lms283gf05_toggle(spi, disp_initseq, ARRAY_SIZE(disp_initseq)); + } else { + lms283gf05_toggle(spi, disp_pdwnseq, ARRAY_SIZE(disp_pdwnseq)); + if (pdata) + gpio_set_value(pdata->reset_gpio, + pdata->reset_inverted); + } + + return 0; +} + +static struct lcd_ops lms_ops = { + .set_power = lms283gf05_power_set, + .get_power = NULL, +}; + +static int __devinit lms283gf05_probe(struct spi_device *spi) +{ + struct lms283gf05_state *st; + struct lms283gf05_pdata *pdata = spi->dev.platform_data; + struct lcd_device *ld; + int ret = 0; + + if (pdata != NULL) { + ret = gpio_request(pdata->reset_gpio, "LMS285GF05 RESET"); + if (ret) + return ret; + + ret = gpio_direction_output(pdata->reset_gpio, + !pdata->reset_inverted); + if (ret) + goto err; + } + + st = kzalloc(sizeof(struct lms283gf05_state), GFP_KERNEL); + if (st == NULL) { + dev_err(&spi->dev, "No memory for device state\n"); + ret = -ENOMEM; + goto err; + } + + ld = lcd_device_register("lms283gf05", &spi->dev, st, &lms_ops); + if (IS_ERR(ld)) { + ret = PTR_ERR(ld); + goto err2; + } + + st->spi = spi; + st->ld = ld; + + dev_set_drvdata(&spi->dev, st); + + /* kick in the LCD */ + if (pdata) + lms283gf05_reset(pdata->reset_gpio, pdata->reset_inverted); + lms283gf05_toggle(spi, disp_initseq, ARRAY_SIZE(disp_initseq)); + + return 0; + +err2: + kfree(st); +err: + if (pdata != NULL) + gpio_free(pdata->reset_gpio); + + return ret; +} + +static int __devexit lms283gf05_remove(struct spi_device *spi) +{ + struct lms283gf05_state *st = dev_get_drvdata(&spi->dev); + struct lms283gf05_pdata *pdata = st->spi->dev.platform_data; + + lcd_device_unregister(st->ld); + + if (pdata != NULL) + gpio_free(pdata->reset_gpio); + + kfree(st); + + return 0; +} + +static struct spi_driver lms283gf05_driver = { + .driver = { + .name = "lms283gf05", + .owner = THIS_MODULE, + }, + .probe = lms283gf05_probe, + .remove = __devexit_p(lms283gf05_remove), +}; + +static __init int lms283gf05_init(void) +{ + return spi_register_driver(&lms283gf05_driver); +} + +static __exit void lms283gf05_exit(void) +{ + spi_unregister_driver(&lms283gf05_driver); +} + +module_init(lms283gf05_init); +module_exit(lms283gf05_exit); + +MODULE_AUTHOR("Marek Vasut "); +MODULE_DESCRIPTION("LCD283GF05 LCD"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/spi/lms283gf05.h b/include/linux/spi/lms283gf05.h new file mode 100644 index 0000000..555d254 --- /dev/null +++ b/include/linux/spi/lms283gf05.h @@ -0,0 +1,28 @@ +/* + * lms283gf05.h - Platform glue for Samsung LMS283GF05 LCD + * + * Copyright (C) 2009 Marek Vasut + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#ifndef _INCLUDE_LINUX_SPI_LMS283GF05_H_ +#define _INCLUDE_LINUX_SPI_LMS283GF05_H_ + +struct lms283gf05_pdata { + unsigned long reset_gpio; + bool reset_inverted; +}; + +#endif /* _INCLUDE_LINUX_SPI_LMS283GF05_H_ */ -- cgit v0.10.2 From 3b96ea9ef837c010f2187e0618d823fbdd8eeb54 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 14 Aug 2009 15:58:56 +0200 Subject: backlight: Add support for the Avionic Design Xanthos backlight device. This patch adds support for the backlight device found on Avionic Design Xanthos-based boards. Signed-off-by: Thierry Reding Signed-off-by: Richard Purdie diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig index c0d4a53..22a4994 100644 --- a/drivers/video/backlight/Kconfig +++ b/drivers/video/backlight/Kconfig @@ -243,3 +243,11 @@ config BACKLIGHT_WM831X help If you have a backlight driven by the ISINK and DCDC of a WM831x PMIC say y to enable the backlight driver for it. + +config BACKLIGHT_ADX + tristate "Avionic Design Xanthos Backlight Driver" + depends on BACKLIGHT_CLASS_DEVICE && ARCH_PXA_ADX + default y + help + Say Y to enable the backlight driver on Avionic Design Xanthos-based + boards. diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile index 0abc014..a483709 100644 --- a/drivers/video/backlight/Makefile +++ b/drivers/video/backlight/Makefile @@ -26,4 +26,4 @@ obj-$(CONFIG_BACKLIGHT_MBP_NVIDIA) += mbp_nvidia_bl.o obj-$(CONFIG_BACKLIGHT_TOSA) += tosa_bl.o obj-$(CONFIG_BACKLIGHT_SAHARA) += kb3886_bl.o obj-$(CONFIG_BACKLIGHT_WM831X) += wm831x_bl.o - +obj-$(CONFIG_BACKLIGHT_ADX) += adx_bl.o diff --git a/drivers/video/backlight/adx_bl.c b/drivers/video/backlight/adx_bl.c new file mode 100644 index 0000000..2c3bdfc --- /dev/null +++ b/drivers/video/backlight/adx_bl.c @@ -0,0 +1,178 @@ +/* + * linux/drivers/video/backlight/adx.c + * + * Copyright (C) 2009 Avionic Design GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Written by Thierry Reding + */ + +#include +#include +#include +#include +#include + +/* register definitions */ +#define ADX_BACKLIGHT_CONTROL 0x00 +#define ADX_BACKLIGHT_CONTROL_ENABLE (1 << 0) +#define ADX_BACKLIGHT_BRIGHTNESS 0x08 +#define ADX_BACKLIGHT_STATUS 0x10 +#define ADX_BACKLIGHT_ERROR 0x18 + +struct adxbl { + void __iomem *base; +}; + +static int adx_backlight_update_status(struct backlight_device *bldev) +{ + struct adxbl *bl = bl_get_data(bldev); + u32 value; + + value = bldev->props.brightness; + writel(value, bl->base + ADX_BACKLIGHT_BRIGHTNESS); + + value = readl(bl->base + ADX_BACKLIGHT_CONTROL); + + if (bldev->props.state & BL_CORE_FBBLANK) + value &= ~ADX_BACKLIGHT_CONTROL_ENABLE; + else + value |= ADX_BACKLIGHT_CONTROL_ENABLE; + + writel(value, bl->base + ADX_BACKLIGHT_CONTROL); + + return 0; +} + +static int adx_backlight_get_brightness(struct backlight_device *bldev) +{ + struct adxbl *bl = bl_get_data(bldev); + u32 brightness; + + brightness = readl(bl->base + ADX_BACKLIGHT_BRIGHTNESS); + return brightness & 0xff; +} + +static int adx_backlight_check_fb(struct fb_info *fb) +{ + return 1; +} + +static struct backlight_ops adx_backlight_ops = { + .options = 0, + .update_status = adx_backlight_update_status, + .get_brightness = adx_backlight_get_brightness, + .check_fb = adx_backlight_check_fb, +}; + +static int __devinit adx_backlight_probe(struct platform_device *pdev) +{ + struct backlight_device *bldev; + struct resource *res; + struct adxbl *bl; + int ret = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENXIO; + goto out; + } + + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), res->name); + if (!res) { + ret = -ENXIO; + goto out; + } + + bl = devm_kzalloc(&pdev->dev, sizeof(*bl), GFP_KERNEL); + if (!bl) { + ret = -ENOMEM; + goto out; + } + + bl->base = devm_ioremap_nocache(&pdev->dev, res->start, + resource_size(res)); + if (!bl->base) { + ret = -ENXIO; + goto out; + } + + bldev = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, bl, + &adx_backlight_ops); + if (!bldev) { + ret = -ENOMEM; + goto out; + } + + bldev->props.max_brightness = 0xff; + bldev->props.brightness = 0xff; + bldev->props.power = FB_BLANK_UNBLANK; + + platform_set_drvdata(pdev, bldev); + +out: + return ret; +} + +static int __devexit adx_backlight_remove(struct platform_device *pdev) +{ + struct backlight_device *bldev; + int ret = 0; + + bldev = platform_get_drvdata(pdev); + bldev->props.power = FB_BLANK_UNBLANK; + bldev->props.brightness = 0xff; + backlight_update_status(bldev); + backlight_device_unregister(bldev); + platform_set_drvdata(pdev, NULL); + + return ret; +} + +#ifdef CONFIG_PM +static int adx_backlight_suspend(struct platform_device *pdev, + pm_message_t state) +{ + return 0; +} + +static int adx_backlight_resume(struct platform_device *pdev) +{ + return 0; +} +#else +#define adx_backlight_suspend NULL +#define adx_backlight_resume NULL +#endif + +static struct platform_driver adx_backlight_driver = { + .probe = adx_backlight_probe, + .remove = __devexit_p(adx_backlight_remove), + .suspend = adx_backlight_suspend, + .resume = adx_backlight_resume, + .driver = { + .name = "adx-backlight", + .owner = THIS_MODULE, + }, +}; + +static int __init adx_backlight_init(void) +{ + return platform_driver_register(&adx_backlight_driver); +} + +static void __exit adx_backlight_exit(void) +{ + platform_driver_unregister(&adx_backlight_driver); +} + +module_init(adx_backlight_init); +module_exit(adx_backlight_exit); + +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("Avionic Design Xanthos Backlight Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v0.10.2 From 551ebd837c75fc75df81811a18b7136c39cab487 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 1 Sep 2009 15:25:57 +1000 Subject: drm/radeon/kms: add rn50/r100/r200 CS tracker. This adds the command stream checker for the RN50, R100 and R200 cards. It stops any access to 3D registers on RN50, and does checks on buffer sizes on the r100/r200 cards. It also fixes some texture sizing checks on r300. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index b2213a5..6fb8429 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -11,6 +11,15 @@ hostprogs-y := mkregtable quiet_cmd_mkregtable = MKREGTABLE $@ cmd_mkregtable = $(obj)/mkregtable $< > $@ +$(obj)/rn50_reg_safe.h: $(src)/reg_srcs/rn50 $(obj)/mkregtable + $(call if_changed,mkregtable) + +$(obj)/r100_reg_safe.h: $(src)/reg_srcs/r100 $(obj)/mkregtable + $(call if_changed,mkregtable) + +$(obj)/r200_reg_safe.h: $(src)/reg_srcs/r200 $(obj)/mkregtable + $(call if_changed,mkregtable) + $(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable $(call if_changed,mkregtable) @@ -20,6 +29,10 @@ $(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable $(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable $(call if_changed,mkregtable) +$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h + +$(obj)/r200.o: $(obj)/r200_reg_safe.h + $(obj)/rv515.o: $(obj)/rv515_reg_safe.h $(obj)/r300.o: $(obj)/r300_reg_safe.h @@ -34,7 +47,7 @@ radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \ radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \ radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \ - radeon_test.o + radeon_test.o r200.o radeon-$(CONFIG_COMPAT) += radeon_ioc32.o diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 44f34f8..ee3ab62 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -34,6 +34,9 @@ #include #include +#include "r100_reg_safe.h" +#include "rn50_reg_safe.h" + /* Firmware Names */ #define FIRMWARE_R100 "radeon/R100_cp.bin" #define FIRMWARE_R200 "radeon/R200_cp.bin" @@ -51,11 +54,14 @@ MODULE_FIRMWARE(FIRMWARE_RS690); MODULE_FIRMWARE(FIRMWARE_RS600); MODULE_FIRMWARE(FIRMWARE_R520); +#include "r100_track.h" + /* This files gather functions specifics to: * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 * * Some of these functions might be used by newer ASICs. */ +int r200_init(struct radeon_device *rdev); void r100_hdp_reset(struct radeon_device *rdev); void r100_gpu_init(struct radeon_device *rdev); int r100_gui_wait_for_idle(struct radeon_device *rdev); @@ -1017,147 +1023,356 @@ int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, return 0; } +static int r100_get_vtx_size(uint32_t vtx_fmt) +{ + int vtx_size; + vtx_size = 2; + /* ordered according to bits in spec */ + if (vtx_fmt & RADEON_SE_VTX_FMT_W0) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) + vtx_size += 3; + if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) + vtx_size += 3; + if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) + vtx_size += 2; + if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) + vtx_size += 2; + if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) + vtx_size += 2; + if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) + vtx_size += 2; + if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) + vtx_size++; + /* blend weight */ + if (vtx_fmt & (0x7 << 15)) + vtx_size += (vtx_fmt >> 15) & 0x7; + if (vtx_fmt & RADEON_SE_VTX_FMT_N0) + vtx_size += 3; + if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) + vtx_size += 2; + if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_W1) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_N1) + vtx_size++; + if (vtx_fmt & RADEON_SE_VTX_FMT_Z) + vtx_size++; + return vtx_size; +} + static int r100_packet0_check(struct radeon_cs_parser *p, - struct radeon_cs_packet *pkt) + struct radeon_cs_packet *pkt, + unsigned idx, unsigned reg) { struct radeon_cs_chunk *ib_chunk; struct radeon_cs_reloc *reloc; + struct r100_cs_track *track; volatile uint32_t *ib; uint32_t tmp; - unsigned reg; - unsigned i; - unsigned idx; - bool onereg; int r; + int i, face; u32 tile_flags = 0; ib = p->ib->ptr; ib_chunk = &p->chunks[p->chunk_ib_idx]; - idx = pkt->idx + 1; - reg = pkt->reg; - onereg = false; - if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) { - onereg = true; - } - for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { - switch (reg) { - case RADEON_CRTC_GUI_TRIG_VLINE: - r = r100_cs_packet_parse_vline(p); - if (r) { - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", - idx, reg); - r100_cs_dump_packet(p, pkt); - return r; - } - break; + track = (struct r100_cs_track *)p->track; + + switch (reg) { + case RADEON_CRTC_GUI_TRIG_VLINE: + r = r100_cs_packet_parse_vline(p); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + break; /* FIXME: only allow PACKET3 blit? easier to check for out of * range access */ - case RADEON_DST_PITCH_OFFSET: - case RADEON_SRC_PITCH_OFFSET: - r = r100_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", - idx, reg); - r100_cs_dump_packet(p, pkt); - return r; - } - tmp = ib_chunk->kdata[idx] & 0x003fffff; - tmp += (((u32)reloc->lobj.gpu_offset) >> 10); - - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) - tile_flags |= RADEON_DST_TILE_MACRO; - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { - if (reg == RADEON_SRC_PITCH_OFFSET) { - DRM_ERROR("Cannot src blit from microtiled surface\n"); - r100_cs_dump_packet(p, pkt); - return -EINVAL; - } - tile_flags |= RADEON_DST_TILE_MICRO; - } + case RADEON_DST_PITCH_OFFSET: + case RADEON_SRC_PITCH_OFFSET: + r = r100_reloc_pitch_offset(p, pkt, idx, reg); + if (r) + return r; + break; + case RADEON_RB3D_DEPTHOFFSET: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->zb.robj = reloc->robj; + track->zb.offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + break; + case RADEON_RB3D_COLOROFFSET: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->cb[0].robj = reloc->robj; + track->cb[0].offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + break; + case RADEON_PP_TXOFFSET_0: + case RADEON_PP_TXOFFSET_1: + case RADEON_PP_TXOFFSET_2: + i = (reg - RADEON_PP_TXOFFSET_0) / 24; + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->textures[i].robj = reloc->robj; + break; + case RADEON_PP_CUBIC_OFFSET_T0_0: + case RADEON_PP_CUBIC_OFFSET_T0_1: + case RADEON_PP_CUBIC_OFFSET_T0_2: + case RADEON_PP_CUBIC_OFFSET_T0_3: + case RADEON_PP_CUBIC_OFFSET_T0_4: + i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->textures[0].cube_info[i].offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->textures[0].cube_info[i].robj = reloc->robj; + break; + case RADEON_PP_CUBIC_OFFSET_T1_0: + case RADEON_PP_CUBIC_OFFSET_T1_1: + case RADEON_PP_CUBIC_OFFSET_T1_2: + case RADEON_PP_CUBIC_OFFSET_T1_3: + case RADEON_PP_CUBIC_OFFSET_T1_4: + i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->textures[1].cube_info[i].offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->textures[1].cube_info[i].robj = reloc->robj; + break; + case RADEON_PP_CUBIC_OFFSET_T2_0: + case RADEON_PP_CUBIC_OFFSET_T2_1: + case RADEON_PP_CUBIC_OFFSET_T2_2: + case RADEON_PP_CUBIC_OFFSET_T2_3: + case RADEON_PP_CUBIC_OFFSET_T2_4: + i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->textures[2].cube_info[i].offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->textures[2].cube_info[i].robj = reloc->robj; + break; + case RADEON_RE_WIDTH_HEIGHT: + track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF); + break; + case RADEON_RB3D_COLORPITCH: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } - tmp |= tile_flags; - ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; - break; - case RADEON_RB3D_DEPTHOFFSET: - case RADEON_RB3D_COLOROFFSET: - case R300_RB3D_COLOROFFSET0: - case R300_ZB_DEPTHOFFSET: - case R200_PP_TXOFFSET_0: - case R200_PP_TXOFFSET_1: - case R200_PP_TXOFFSET_2: - case R200_PP_TXOFFSET_3: - case R200_PP_TXOFFSET_4: - case R200_PP_TXOFFSET_5: - case RADEON_PP_TXOFFSET_0: - case RADEON_PP_TXOFFSET_1: - case RADEON_PP_TXOFFSET_2: - case R300_TX_OFFSET_0: - case R300_TX_OFFSET_0+4: - case R300_TX_OFFSET_0+8: - case R300_TX_OFFSET_0+12: - case R300_TX_OFFSET_0+16: - case R300_TX_OFFSET_0+20: - case R300_TX_OFFSET_0+24: - case R300_TX_OFFSET_0+28: - case R300_TX_OFFSET_0+32: - case R300_TX_OFFSET_0+36: - case R300_TX_OFFSET_0+40: - case R300_TX_OFFSET_0+44: - case R300_TX_OFFSET_0+48: - case R300_TX_OFFSET_0+52: - case R300_TX_OFFSET_0+56: - case R300_TX_OFFSET_0+60: - /* rn50 has no 3D engine so fail on any 3d setup */ - if (ASIC_IS_RN50(p->rdev)) { - DRM_ERROR("attempt to use RN50 3D engine failed\n"); - return -EINVAL; - } - r = r100_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", - idx, reg); - r100_cs_dump_packet(p, pkt); - return r; - } - ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); - break; - case R300_RB3D_COLORPITCH0: - case RADEON_RB3D_COLORPITCH: - r = r100_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", - idx, reg); - r100_cs_dump_packet(p, pkt); - return r; - } + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) + tile_flags |= RADEON_COLOR_TILE_ENABLE; + if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) + tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) - tile_flags |= RADEON_COLOR_TILE_ENABLE; - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) - tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; + tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); + tmp |= tile_flags; + ib[idx] = tmp; - tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); - tmp |= tile_flags; - ib[idx] = tmp; + track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK; + break; + case RADEON_RB3D_DEPTHPITCH: + track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK; + break; + case RADEON_RB3D_CNTL: + switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { + case 7: + case 8: + case 9: + case 11: + case 12: + track->cb[0].cpp = 1; break; - case RADEON_RB3D_ZPASS_ADDR: - r = r100_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", - idx, reg); - r100_cs_dump_packet(p, pkt); - return r; - } - ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + case 3: + case 4: + case 15: + track->cb[0].cpp = 2; + break; + case 6: + track->cb[0].cpp = 4; + break; + default: + DRM_ERROR("Invalid color buffer format (%d) !\n", + ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); + return -EINVAL; + } + track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE); + break; + case RADEON_RB3D_ZSTENCILCNTL: + switch (ib_chunk->kdata[idx] & 0xf) { + case 0: + track->zb.cpp = 2; + break; + case 2: + case 3: + case 4: + case 5: + case 9: + case 11: + track->zb.cpp = 4; break; default: - /* FIXME: we don't want to allow anyothers packet */ break; } - if (onereg) { - /* FIXME: forbid onereg write to register on relocate */ + break; + case RADEON_RB3D_ZPASS_ADDR: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + break; + case RADEON_PP_CNTL: + { + uint32_t temp = ib_chunk->kdata[idx] >> 4; + for (i = 0; i < track->num_texture; i++) + track->textures[i].enabled = !!(temp & (1 << i)); + } + break; + case RADEON_SE_VF_CNTL: + track->vap_vf_cntl = ib_chunk->kdata[idx]; + break; + case RADEON_SE_VTX_FMT: + track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx]); + break; + case RADEON_PP_TEX_SIZE_0: + case RADEON_PP_TEX_SIZE_1: + case RADEON_PP_TEX_SIZE_2: + i = (reg - RADEON_PP_TEX_SIZE_0) / 8; + track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1; + track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; + break; + case RADEON_PP_TEX_PITCH_0: + case RADEON_PP_TEX_PITCH_1: + case RADEON_PP_TEX_PITCH_2: + i = (reg - RADEON_PP_TEX_PITCH_0) / 8; + track->textures[i].pitch = ib_chunk->kdata[idx] + 32; + break; + case RADEON_PP_TXFILTER_0: + case RADEON_PP_TXFILTER_1: + case RADEON_PP_TXFILTER_2: + i = (reg - RADEON_PP_TXFILTER_0) / 24; + track->textures[i].num_levels = ((ib_chunk->kdata[idx] & RADEON_MAX_MIP_LEVEL_MASK) + >> RADEON_MAX_MIP_LEVEL_SHIFT); + tmp = (ib_chunk->kdata[idx] >> 23) & 0x7; + if (tmp == 2 || tmp == 6) + track->textures[i].roundup_w = false; + tmp = (ib_chunk->kdata[idx] >> 27) & 0x7; + if (tmp == 2 || tmp == 6) + track->textures[i].roundup_h = false; + break; + case RADEON_PP_TXFORMAT_0: + case RADEON_PP_TXFORMAT_1: + case RADEON_PP_TXFORMAT_2: + i = (reg - RADEON_PP_TXFORMAT_0) / 24; + if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_NON_POWER2) { + track->textures[i].use_pitch = 1; + } else { + track->textures[i].use_pitch = 0; + track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); + track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); + } + if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) + track->textures[i].tex_coord_type = 2; + switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) { + case RADEON_TXFORMAT_I8: + case RADEON_TXFORMAT_RGB332: + case RADEON_TXFORMAT_Y8: + track->textures[i].cpp = 1; + break; + case RADEON_TXFORMAT_AI88: + case RADEON_TXFORMAT_ARGB1555: + case RADEON_TXFORMAT_RGB565: + case RADEON_TXFORMAT_ARGB4444: + case RADEON_TXFORMAT_VYUY422: + case RADEON_TXFORMAT_YVYU422: + case RADEON_TXFORMAT_DXT1: + case RADEON_TXFORMAT_SHADOW16: + case RADEON_TXFORMAT_LDUDV655: + case RADEON_TXFORMAT_DUDV88: + track->textures[i].cpp = 2; break; + case RADEON_TXFORMAT_ARGB8888: + case RADEON_TXFORMAT_RGBA8888: + case RADEON_TXFORMAT_DXT23: + case RADEON_TXFORMAT_DXT45: + case RADEON_TXFORMAT_SHADOW32: + case RADEON_TXFORMAT_LDUDUV8888: + track->textures[i].cpp = 4; + break; + } + track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf); + track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf); + break; + case RADEON_PP_CUBIC_FACES_0: + case RADEON_PP_CUBIC_FACES_1: + case RADEON_PP_CUBIC_FACES_2: + tmp = ib_chunk->kdata[idx]; + i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; + for (face = 0; face < 4; face++) { + track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); + track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); } + break; + default: + printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", + reg, idx); + return -EINVAL; } return 0; } @@ -1186,6 +1401,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p, { struct radeon_cs_chunk *ib_chunk; struct radeon_cs_reloc *reloc; + struct r100_cs_track *track; unsigned idx; unsigned i, c; volatile uint32_t *ib; @@ -1194,9 +1410,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p, ib = p->ib->ptr; ib_chunk = &p->chunks[p->chunk_ib_idx]; idx = pkt->idx + 1; + track = (struct r100_cs_track *)p->track; switch (pkt->opcode) { case PACKET3_3D_LOAD_VBPNTR: c = ib_chunk->kdata[idx++]; + track->num_arrays = c; for (i = 0; i < (c - 1); i += 2, idx += 3) { r = r100_cs_packet_next_reloc(p, &reloc); if (r) { @@ -1206,6 +1424,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p, return r; } ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); + track->arrays[i + 0].robj = reloc->robj; + track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; + track->arrays[i + 0].esize &= 0x7F; r = r100_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("No reloc for packet3 %d\n", @@ -1214,6 +1435,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p, return r; } ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); + track->arrays[i + 1].robj = reloc->robj; + track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24; + track->arrays[i + 1].esize &= 0x7F; } if (c & 1) { r = r100_cs_packet_next_reloc(p, &reloc); @@ -1224,6 +1448,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p, return r; } ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); + track->arrays[i + 0].robj = reloc->robj; + track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; + track->arrays[i + 0].esize &= 0x7F; } break; case PACKET3_INDX_BUFFER: @@ -1240,7 +1467,6 @@ static int r100_packet3_check(struct radeon_cs_parser *p, } break; case 0x23: - /* FIXME: cleanup */ /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ r = r100_cs_packet_next_reloc(p, &reloc); if (r) { @@ -1249,18 +1475,71 @@ static int r100_packet3_check(struct radeon_cs_parser *p, return r; } ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->num_arrays = 1; + track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx+2]); + + track->arrays[0].robj = reloc->robj; + track->arrays[0].esize = track->vtx_size; + + track->max_indx = ib_chunk->kdata[idx+1]; + + track->vap_vf_cntl = ib_chunk->kdata[idx+3]; + track->immd_dwords = pkt->count - 1; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; break; case PACKET3_3D_DRAW_IMMD: + if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) { + DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); + return -EINVAL; + } + track->vap_vf_cntl = ib_chunk->kdata[idx+1]; + track->immd_dwords = pkt->count - 1; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; + break; /* triggers drawing using in-packet vertex data */ case PACKET3_3D_DRAW_IMMD_2: + if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) { + DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); + return -EINVAL; + } + track->vap_vf_cntl = ib_chunk->kdata[idx]; + track->immd_dwords = pkt->count; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; + break; /* triggers drawing using in-packet vertex data */ case PACKET3_3D_DRAW_VBUF_2: + track->vap_vf_cntl = ib_chunk->kdata[idx]; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; + break; /* triggers drawing of vertex buffers setup elsewhere */ case PACKET3_3D_DRAW_INDX_2: + track->vap_vf_cntl = ib_chunk->kdata[idx]; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; + break; /* triggers drawing using indices to vertex buffer */ case PACKET3_3D_DRAW_VBUF: + track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; + break; /* triggers drawing of vertex buffers setup elsewhere */ case PACKET3_3D_DRAW_INDX: + track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; + r = r100_cs_track_check(p->rdev, track); + if (r) + return r; + break; /* triggers drawing using indices to vertex buffer */ case PACKET3_NOP: break; @@ -1274,8 +1553,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p, int r100_cs_parse(struct radeon_cs_parser *p) { struct radeon_cs_packet pkt; + struct r100_cs_track track; int r; + r100_cs_track_clear(p->rdev, &track); + p->track = &track; do { r = r100_cs_packet_parse(p, &pkt, p->idx); if (r) { @@ -1284,7 +1566,16 @@ int r100_cs_parse(struct radeon_cs_parser *p) p->idx += pkt.count + 2; switch (pkt.type) { case PACKET_TYPE0: - r = r100_packet0_check(p, &pkt); + if (p->rdev->family >= CHIP_R200) + r = r100_cs_parse_packet0(p, &pkt, + p->rdev->config.r100.reg_safe_bm, + p->rdev->config.r100.reg_safe_bm_size, + &r200_packet0_check); + else + r = r100_cs_parse_packet0(p, &pkt, + p->rdev->config.r100.reg_safe_bm, + p->rdev->config.r100.reg_safe_bm_size, + &r100_packet0_check); break; case PACKET_TYPE2: break; @@ -1683,6 +1974,15 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) int r100_init(struct radeon_device *rdev) { + if (ASIC_IS_RN50(rdev)) { + rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; + rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); + } else if (rdev->family < CHIP_R200) { + rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; + rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); + } else { + return r200_init(rdev); + } return 0; } @@ -2383,3 +2683,274 @@ void r100_bandwidth_update(struct radeon_device *rdev) (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); } } + +static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) +{ + DRM_ERROR("pitch %d\n", t->pitch); + DRM_ERROR("width %d\n", t->width); + DRM_ERROR("height %d\n", t->height); + DRM_ERROR("num levels %d\n", t->num_levels); + DRM_ERROR("depth %d\n", t->txdepth); + DRM_ERROR("bpp %d\n", t->cpp); + DRM_ERROR("coordinate type %d\n", t->tex_coord_type); + DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); + DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); +} + +static int r100_cs_track_cube(struct radeon_device *rdev, + struct r100_cs_track *track, unsigned idx) +{ + unsigned face, w, h; + struct radeon_object *cube_robj; + unsigned long size; + + for (face = 0; face < 5; face++) { + cube_robj = track->textures[idx].cube_info[face].robj; + w = track->textures[idx].cube_info[face].width; + h = track->textures[idx].cube_info[face].height; + + size = w * h; + size *= track->textures[idx].cpp; + + size += track->textures[idx].cube_info[face].offset; + + if (size > radeon_object_size(cube_robj)) { + DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", + size, radeon_object_size(cube_robj)); + r100_cs_track_texture_print(&track->textures[idx]); + return -1; + } + } + return 0; +} + +static int r100_cs_track_texture_check(struct radeon_device *rdev, + struct r100_cs_track *track) +{ + struct radeon_object *robj; + unsigned long size; + unsigned u, i, w, h; + int ret; + + for (u = 0; u < track->num_texture; u++) { + if (!track->textures[u].enabled) + continue; + robj = track->textures[u].robj; + if (robj == NULL) { + DRM_ERROR("No texture bound to unit %u\n", u); + return -EINVAL; + } + size = 0; + for (i = 0; i <= track->textures[u].num_levels; i++) { + if (track->textures[u].use_pitch) { + if (rdev->family < CHIP_R300) + w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); + else + w = track->textures[u].pitch / (1 << i); + } else { + w = track->textures[u].width / (1 << i); + if (rdev->family >= CHIP_RV515) + w |= track->textures[u].width_11; + if (track->textures[u].roundup_w) + w = roundup_pow_of_two(w); + } + h = track->textures[u].height / (1 << i); + if (rdev->family >= CHIP_RV515) + h |= track->textures[u].height_11; + if (track->textures[u].roundup_h) + h = roundup_pow_of_two(h); + size += w * h; + } + size *= track->textures[u].cpp; + switch (track->textures[u].tex_coord_type) { + case 0: + break; + case 1: + size *= (1 << track->textures[u].txdepth); + break; + case 2: + if (track->separate_cube) { + ret = r100_cs_track_cube(rdev, track, u); + if (ret) + return ret; + } else + size *= 6; + break; + default: + DRM_ERROR("Invalid texture coordinate type %u for unit " + "%u\n", track->textures[u].tex_coord_type, u); + return -EINVAL; + } + if (size > radeon_object_size(robj)) { + DRM_ERROR("Texture of unit %u needs %lu bytes but is " + "%lu\n", u, size, radeon_object_size(robj)); + r100_cs_track_texture_print(&track->textures[u]); + return -EINVAL; + } + } + return 0; +} + +int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) +{ + unsigned i; + unsigned long size; + unsigned prim_walk; + unsigned nverts; + + for (i = 0; i < track->num_cb; i++) { + if (track->cb[i].robj == NULL) { + DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); + return -EINVAL; + } + size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; + size += track->cb[i].offset; + if (size > radeon_object_size(track->cb[i].robj)) { + DRM_ERROR("[drm] Buffer too small for color buffer %d " + "(need %lu have %lu) !\n", i, size, + radeon_object_size(track->cb[i].robj)); + DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", + i, track->cb[i].pitch, track->cb[i].cpp, + track->cb[i].offset, track->maxy); + return -EINVAL; + } + } + if (track->z_enabled) { + if (track->zb.robj == NULL) { + DRM_ERROR("[drm] No buffer for z buffer !\n"); + return -EINVAL; + } + size = track->zb.pitch * track->zb.cpp * track->maxy; + size += track->zb.offset; + if (size > radeon_object_size(track->zb.robj)) { + DRM_ERROR("[drm] Buffer too small for z buffer " + "(need %lu have %lu) !\n", size, + radeon_object_size(track->zb.robj)); + DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", + track->zb.pitch, track->zb.cpp, + track->zb.offset, track->maxy); + return -EINVAL; + } + } + prim_walk = (track->vap_vf_cntl >> 4) & 0x3; + nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; + switch (prim_walk) { + case 1: + for (i = 0; i < track->num_arrays; i++) { + size = track->arrays[i].esize * track->max_indx * 4; + if (track->arrays[i].robj == NULL) { + DRM_ERROR("(PW %u) Vertex array %u no buffer " + "bound\n", prim_walk, i); + return -EINVAL; + } + if (size > radeon_object_size(track->arrays[i].robj)) { + DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " + "have %lu dwords\n", prim_walk, i, + size >> 2, + radeon_object_size(track->arrays[i].robj) >> 2); + DRM_ERROR("Max indices %u\n", track->max_indx); + return -EINVAL; + } + } + break; + case 2: + for (i = 0; i < track->num_arrays; i++) { + size = track->arrays[i].esize * (nverts - 1) * 4; + if (track->arrays[i].robj == NULL) { + DRM_ERROR("(PW %u) Vertex array %u no buffer " + "bound\n", prim_walk, i); + return -EINVAL; + } + if (size > radeon_object_size(track->arrays[i].robj)) { + DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " + "have %lu dwords\n", prim_walk, i, size >> 2, + radeon_object_size(track->arrays[i].robj) >> 2); + return -EINVAL; + } + } + break; + case 3: + size = track->vtx_size * nverts; + if (size != track->immd_dwords) { + DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", + track->immd_dwords, size); + DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", + nverts, track->vtx_size); + return -EINVAL; + } + break; + default: + DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", + prim_walk); + return -EINVAL; + } + return r100_cs_track_texture_check(rdev, track); +} + +void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) +{ + unsigned i, face; + + if (rdev->family < CHIP_R300) { + track->num_cb = 1; + if (rdev->family <= CHIP_RS200) + track->num_texture = 3; + else + track->num_texture = 6; + track->maxy = 2048; + track->separate_cube = 1; + } else { + track->num_cb = 4; + track->num_texture = 16; + track->maxy = 4096; + track->separate_cube = 0; + } + + for (i = 0; i < track->num_cb; i++) { + track->cb[i].robj = NULL; + track->cb[i].pitch = 8192; + track->cb[i].cpp = 16; + track->cb[i].offset = 0; + } + track->z_enabled = true; + track->zb.robj = NULL; + track->zb.pitch = 8192; + track->zb.cpp = 4; + track->zb.offset = 0; + track->vtx_size = 0x7F; + track->immd_dwords = 0xFFFFFFFFUL; + track->num_arrays = 11; + track->max_indx = 0x00FFFFFFUL; + for (i = 0; i < track->num_arrays; i++) { + track->arrays[i].robj = NULL; + track->arrays[i].esize = 0x7F; + } + for (i = 0; i < track->num_texture; i++) { + track->textures[i].pitch = 16536; + track->textures[i].width = 16536; + track->textures[i].height = 16536; + track->textures[i].width_11 = 1 << 11; + track->textures[i].height_11 = 1 << 11; + track->textures[i].num_levels = 12; + if (rdev->family <= CHIP_RS200) { + track->textures[i].tex_coord_type = 0; + track->textures[i].txdepth = 0; + } else { + track->textures[i].txdepth = 16; + track->textures[i].tex_coord_type = 1; + } + track->textures[i].cpp = 64; + track->textures[i].robj = NULL; + /* CS IB emission code makes sure texture unit are disabled */ + track->textures[i].enabled = false; + track->textures[i].roundup_w = true; + track->textures[i].roundup_h = true; + if (track->separate_cube) + for (face = 0; face < 5; face++) { + track->textures[i].cube_info[face].robj = NULL; + track->textures[i].cube_info[face].width = 16536; + track->textures[i].cube_info[face].height = 16536; + track->textures[i].cube_info[face].offset = 0; + } + } +} diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h new file mode 100644 index 0000000..70a82ed --- /dev/null +++ b/drivers/gpu/drm/radeon/r100_track.h @@ -0,0 +1,124 @@ + +#define R100_TRACK_MAX_TEXTURE 3 +#define R200_TRACK_MAX_TEXTURE 6 +#define R300_TRACK_MAX_TEXTURE 16 + +#define R100_MAX_CB 1 +#define R300_MAX_CB 4 + +/* + * CS functions + */ +struct r100_cs_track_cb { + struct radeon_object *robj; + unsigned pitch; + unsigned cpp; + unsigned offset; +}; + +struct r100_cs_track_array { + struct radeon_object *robj; + unsigned esize; +}; + +struct r100_cs_cube_info { + struct radeon_object *robj; + unsigned offset; + unsigned width; + unsigned height; +}; + +struct r100_cs_track_texture { + struct radeon_object *robj; + struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ + unsigned pitch; + unsigned width; + unsigned height; + unsigned num_levels; + unsigned cpp; + unsigned tex_coord_type; + unsigned txdepth; + unsigned width_11; + unsigned height_11; + bool use_pitch; + bool enabled; + bool roundup_w; + bool roundup_h; +}; + +struct r100_cs_track_limits { + unsigned num_cb; + unsigned num_texture; + unsigned max_levels; +}; + +struct r100_cs_track { + struct radeon_device *rdev; + unsigned num_cb; + unsigned num_texture; + unsigned maxy; + unsigned vtx_size; + unsigned vap_vf_cntl; + unsigned immd_dwords; + unsigned num_arrays; + unsigned max_indx; + struct r100_cs_track_array arrays[11]; + struct r100_cs_track_cb cb[R300_MAX_CB]; + struct r100_cs_track_cb zb; + struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; + bool z_enabled; + bool separate_cube; + +}; + +int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); +void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); +int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, + struct radeon_cs_reloc **cs_reloc); +void r100_cs_dump_packet(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt); + +int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); + +int r200_packet0_check(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + unsigned idx, unsigned reg); + +static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + unsigned idx, + unsigned reg) +{ + int r; + u32 tile_flags = 0; + u32 tmp; + struct radeon_cs_reloc *reloc; + struct radeon_cs_chunk *ib_chunk; + + ib_chunk = &p->chunks[p->chunk_ib_idx]; + + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + tmp = ib_chunk->kdata[idx] & 0x003fffff; + tmp += (((u32)reloc->lobj.gpu_offset) >> 10); + + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) + tile_flags |= RADEON_DST_TILE_MACRO; + if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { + if (reg == RADEON_SRC_PITCH_OFFSET) { + DRM_ERROR("Cannot src blit from microtiled surface\n"); + r100_cs_dump_packet(p, pkt); + return -EINVAL; + } + tile_flags |= RADEON_DST_TILE_MICRO; + } + + tmp |= tile_flags; + p->ib->ptr[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; + return 0; +} diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c new file mode 100644 index 0000000..568c74b --- /dev/null +++ b/drivers/gpu/drm/radeon/r200.c @@ -0,0 +1,456 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" +#include "radeon_reg.h" +#include "radeon.h" + +#include "r200_reg_safe.h" + +#include "r100_track.h" + +static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) +{ + int vtx_size, i; + vtx_size = 2; + + if (vtx_fmt_0 & R200_VTX_Z0) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_W0) + vtx_size++; + /* blend weight */ + if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT)) + vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7; + if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_N0) + vtx_size += 3; + if (vtx_fmt_0 & R200_VTX_POINT_SIZE) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_SHININESS_0) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_SHININESS_1) + vtx_size++; + for (i = 0; i < 8; i++) { + int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3; + switch (color_size) { + case 0: break; + case 1: vtx_size++; break; + case 2: vtx_size += 3; break; + case 3: vtx_size += 4; break; + } + } + if (vtx_fmt_0 & R200_VTX_XY1) + vtx_size += 2; + if (vtx_fmt_0 & R200_VTX_Z1) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_W1) + vtx_size++; + if (vtx_fmt_0 & R200_VTX_N1) + vtx_size += 3; + return vtx_size; +} + +static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) +{ + int vtx_size, i, tex_size; + vtx_size = 0; + for (i = 0; i < 6; i++) { + tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7; + if (tex_size > 4) + continue; + vtx_size += tex_size; + } + return vtx_size; +} + +int r200_packet0_check(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + unsigned idx, unsigned reg) +{ + struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_reloc *reloc; + struct r100_cs_track *track; + volatile uint32_t *ib; + uint32_t tmp; + int r; + int i; + int face; + u32 tile_flags = 0; + + ib = p->ib->ptr; + ib_chunk = &p->chunks[p->chunk_ib_idx]; + track = (struct r100_cs_track *)p->track; + + switch (reg) { + case RADEON_CRTC_GUI_TRIG_VLINE: + r = r100_cs_packet_parse_vline(p); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + break; + /* FIXME: only allow PACKET3 blit? easier to check for out of + * range access */ + case RADEON_DST_PITCH_OFFSET: + case RADEON_SRC_PITCH_OFFSET: + r = r100_reloc_pitch_offset(p, pkt, idx, reg); + if (r) + return r; + break; + case RADEON_RB3D_DEPTHOFFSET: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->zb.robj = reloc->robj; + track->zb.offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + break; + case RADEON_RB3D_COLOROFFSET: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->cb[0].robj = reloc->robj; + track->cb[0].offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + break; + case R200_PP_TXOFFSET_0: + case R200_PP_TXOFFSET_1: + case R200_PP_TXOFFSET_2: + case R200_PP_TXOFFSET_3: + case R200_PP_TXOFFSET_4: + case R200_PP_TXOFFSET_5: + i = (reg - R200_PP_TXOFFSET_0) / 24; + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->textures[i].robj = reloc->robj; + break; + case R200_PP_CUBIC_OFFSET_F1_0: + case R200_PP_CUBIC_OFFSET_F2_0: + case R200_PP_CUBIC_OFFSET_F3_0: + case R200_PP_CUBIC_OFFSET_F4_0: + case R200_PP_CUBIC_OFFSET_F5_0: + case R200_PP_CUBIC_OFFSET_F1_1: + case R200_PP_CUBIC_OFFSET_F2_1: + case R200_PP_CUBIC_OFFSET_F3_1: + case R200_PP_CUBIC_OFFSET_F4_1: + case R200_PP_CUBIC_OFFSET_F5_1: + case R200_PP_CUBIC_OFFSET_F1_2: + case R200_PP_CUBIC_OFFSET_F2_2: + case R200_PP_CUBIC_OFFSET_F3_2: + case R200_PP_CUBIC_OFFSET_F4_2: + case R200_PP_CUBIC_OFFSET_F5_2: + case R200_PP_CUBIC_OFFSET_F1_3: + case R200_PP_CUBIC_OFFSET_F2_3: + case R200_PP_CUBIC_OFFSET_F3_3: + case R200_PP_CUBIC_OFFSET_F4_3: + case R200_PP_CUBIC_OFFSET_F5_3: + case R200_PP_CUBIC_OFFSET_F1_4: + case R200_PP_CUBIC_OFFSET_F2_4: + case R200_PP_CUBIC_OFFSET_F3_4: + case R200_PP_CUBIC_OFFSET_F4_4: + case R200_PP_CUBIC_OFFSET_F5_4: + case R200_PP_CUBIC_OFFSET_F1_5: + case R200_PP_CUBIC_OFFSET_F2_5: + case R200_PP_CUBIC_OFFSET_F3_5: + case R200_PP_CUBIC_OFFSET_F4_5: + case R200_PP_CUBIC_OFFSET_F5_5: + i = (reg - R200_PP_TXOFFSET_0) / 24; + face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4; + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx]; + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + track->textures[i].cube_info[face - 1].robj = reloc->robj; + break; + case RADEON_RE_WIDTH_HEIGHT: + track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF); + break; + case RADEON_RB3D_COLORPITCH: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) + tile_flags |= RADEON_COLOR_TILE_ENABLE; + if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) + tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; + + tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); + tmp |= tile_flags; + ib[idx] = tmp; + + track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK; + break; + case RADEON_RB3D_DEPTHPITCH: + track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK; + break; + case RADEON_RB3D_CNTL: + switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { + case 7: + case 8: + case 9: + case 11: + case 12: + track->cb[0].cpp = 1; + break; + case 3: + case 4: + case 15: + track->cb[0].cpp = 2; + break; + case 6: + track->cb[0].cpp = 4; + break; + default: + DRM_ERROR("Invalid color buffer format (%d) !\n", + ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); + return -EINVAL; + } + if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) { + DRM_ERROR("No support for depth xy offset in kms\n"); + return -EINVAL; + } + + track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE); + break; + case RADEON_RB3D_ZSTENCILCNTL: + switch (ib_chunk->kdata[idx] & 0xf) { + case 0: + track->zb.cpp = 2; + break; + case 2: + case 3: + case 4: + case 5: + case 9: + case 11: + track->zb.cpp = 4; + break; + default: + break; + } + break; + case RADEON_RB3D_ZPASS_ADDR: + r = r100_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", + idx, reg); + r100_cs_dump_packet(p, pkt); + return r; + } + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); + break; + case RADEON_PP_CNTL: + { + uint32_t temp = ib_chunk->kdata[idx] >> 4; + for (i = 0; i < track->num_texture; i++) + track->textures[i].enabled = !!(temp & (1 << i)); + } + break; + case RADEON_SE_VF_CNTL: + track->vap_vf_cntl = ib_chunk->kdata[idx]; + break; + case 0x210c: + /* VAP_VF_MAX_VTX_INDX */ + track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; + break; + case R200_SE_VTX_FMT_0: + track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]); + break; + case R200_SE_VTX_FMT_1: + track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]); + break; + case R200_PP_TXSIZE_0: + case R200_PP_TXSIZE_1: + case R200_PP_TXSIZE_2: + case R200_PP_TXSIZE_3: + case R200_PP_TXSIZE_4: + case R200_PP_TXSIZE_5: + i = (reg - R200_PP_TXSIZE_0) / 32; + track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1; + track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; + break; + case R200_PP_TXPITCH_0: + case R200_PP_TXPITCH_1: + case R200_PP_TXPITCH_2: + case R200_PP_TXPITCH_3: + case R200_PP_TXPITCH_4: + case R200_PP_TXPITCH_5: + i = (reg - R200_PP_TXPITCH_0) / 32; + track->textures[i].pitch = ib_chunk->kdata[idx] + 32; + break; + case R200_PP_TXFILTER_0: + case R200_PP_TXFILTER_1: + case R200_PP_TXFILTER_2: + case R200_PP_TXFILTER_3: + case R200_PP_TXFILTER_4: + case R200_PP_TXFILTER_5: + i = (reg - R200_PP_TXFILTER_0) / 32; + track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK) + >> R200_MAX_MIP_LEVEL_SHIFT); + tmp = (ib_chunk->kdata[idx] >> 23) & 0x7; + if (tmp == 2 || tmp == 6) + track->textures[i].roundup_w = false; + tmp = (ib_chunk->kdata[idx] >> 27) & 0x7; + if (tmp == 2 || tmp == 6) + track->textures[i].roundup_h = false; + break; + case R200_PP_TXMULTI_CTL_0: + case R200_PP_TXMULTI_CTL_1: + case R200_PP_TXMULTI_CTL_2: + case R200_PP_TXMULTI_CTL_3: + case R200_PP_TXMULTI_CTL_4: + case R200_PP_TXMULTI_CTL_5: + i = (reg - R200_PP_TXMULTI_CTL_0) / 32; + break; + case R200_PP_TXFORMAT_X_0: + case R200_PP_TXFORMAT_X_1: + case R200_PP_TXFORMAT_X_2: + case R200_PP_TXFORMAT_X_3: + case R200_PP_TXFORMAT_X_4: + case R200_PP_TXFORMAT_X_5: + i = (reg - R200_PP_TXFORMAT_X_0) / 32; + track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7; + tmp = (ib_chunk->kdata[idx] >> 16) & 0x3; + /* 2D, 3D, CUBE */ + switch (tmp) { + case 0: + case 5: + case 6: + case 7: + track->textures[i].tex_coord_type = 0; + break; + case 1: + track->textures[i].tex_coord_type = 1; + break; + case 2: + track->textures[i].tex_coord_type = 2; + break; + } + break; + case R200_PP_TXFORMAT_0: + case R200_PP_TXFORMAT_1: + case R200_PP_TXFORMAT_2: + case R200_PP_TXFORMAT_3: + case R200_PP_TXFORMAT_4: + case R200_PP_TXFORMAT_5: + i = (reg - R200_PP_TXFORMAT_0) / 32; + if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) { + track->textures[i].use_pitch = 1; + } else { + track->textures[i].use_pitch = 0; + track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); + track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); + } + switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) { + case R200_TXFORMAT_I8: + case R200_TXFORMAT_RGB332: + case R200_TXFORMAT_Y8: + track->textures[i].cpp = 1; + break; + case R200_TXFORMAT_DXT1: + case R200_TXFORMAT_AI88: + case R200_TXFORMAT_ARGB1555: + case R200_TXFORMAT_RGB565: + case R200_TXFORMAT_ARGB4444: + case R200_TXFORMAT_VYUY422: + case R200_TXFORMAT_YVYU422: + case R200_TXFORMAT_LDVDU655: + case R200_TXFORMAT_DVDU88: + case R200_TXFORMAT_AVYU4444: + track->textures[i].cpp = 2; + break; + case R200_TXFORMAT_ARGB8888: + case R200_TXFORMAT_RGBA8888: + case R200_TXFORMAT_ABGR8888: + case R200_TXFORMAT_BGR111110: + case R200_TXFORMAT_LDVDU8888: + case R200_TXFORMAT_DXT23: + case R200_TXFORMAT_DXT45: + track->textures[i].cpp = 4; + break; + } + track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf); + track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf); + break; + case R200_PP_CUBIC_FACES_0: + case R200_PP_CUBIC_FACES_1: + case R200_PP_CUBIC_FACES_2: + case R200_PP_CUBIC_FACES_3: + case R200_PP_CUBIC_FACES_4: + case R200_PP_CUBIC_FACES_5: + tmp = ib_chunk->kdata[idx]; + i = (reg - R200_PP_CUBIC_FACES_0) / 32; + for (face = 0; face < 4; face++) { + track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); + track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); + } + break; + default: + printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", + reg, idx); + return -EINVAL; + } + return 0; +} + +int r200_init(struct radeon_device *rdev) +{ + rdev->config.r100.reg_safe_bm = r200_reg_safe_bm; + rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm); + return 0; +} diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 9f2460c..33a2c55 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -32,6 +32,7 @@ #include "radeon.h" #include "radeon_drm.h" #include "radeon_share.h" +#include "r100_track.h" #include "r300_reg_safe.h" @@ -49,14 +50,10 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, unsigned idx); int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); -int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, - struct radeon_cs_reloc **cs_reloc); int r100_cs_parse_packet0(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, const unsigned *auth, unsigned n, radeon_packet0_check_t check); -void r100_cs_dump_packet(struct radeon_cs_parser *p, - struct radeon_cs_packet *pkt); int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, struct radeon_object *robj); @@ -706,264 +703,13 @@ int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) /* * CS functions */ -struct r300_cs_track_cb { - struct radeon_object *robj; - unsigned pitch; - unsigned cpp; - unsigned offset; -}; - -struct r300_cs_track_array { - struct radeon_object *robj; - unsigned esize; -}; - -struct r300_cs_track_texture { - struct radeon_object *robj; - unsigned pitch; - unsigned width; - unsigned height; - unsigned num_levels; - unsigned cpp; - unsigned tex_coord_type; - unsigned txdepth; - unsigned width_11; - unsigned height_11; - bool use_pitch; - bool enabled; - bool roundup_w; - bool roundup_h; -}; - -struct r300_cs_track { - unsigned num_cb; - unsigned maxy; - unsigned vtx_size; - unsigned vap_vf_cntl; - unsigned immd_dwords; - unsigned num_arrays; - unsigned max_indx; - struct r300_cs_track_array arrays[11]; - struct r300_cs_track_cb cb[4]; - struct r300_cs_track_cb zb; - struct r300_cs_track_texture textures[16]; - bool z_enabled; -}; - -static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t) -{ - DRM_ERROR("pitch %d\n", t->pitch); - DRM_ERROR("width %d\n", t->width); - DRM_ERROR("height %d\n", t->height); - DRM_ERROR("num levels %d\n", t->num_levels); - DRM_ERROR("depth %d\n", t->txdepth); - DRM_ERROR("bpp %d\n", t->cpp); - DRM_ERROR("coordinate type %d\n", t->tex_coord_type); - DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); - DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); -} - -static inline int r300_cs_track_texture_check(struct radeon_device *rdev, - struct r300_cs_track *track) -{ - struct radeon_object *robj; - unsigned long size; - unsigned u, i, w, h; - - for (u = 0; u < 16; u++) { - if (!track->textures[u].enabled) - continue; - robj = track->textures[u].robj; - if (robj == NULL) { - DRM_ERROR("No texture bound to unit %u\n", u); - return -EINVAL; - } - size = 0; - for (i = 0; i <= track->textures[u].num_levels; i++) { - if (track->textures[u].use_pitch) { - w = track->textures[u].pitch / (1 << i); - } else { - w = track->textures[u].width / (1 << i); - if (rdev->family >= CHIP_RV515) - w |= track->textures[u].width_11; - if (track->textures[u].roundup_w) - w = roundup_pow_of_two(w); - } - h = track->textures[u].height / (1 << i); - if (rdev->family >= CHIP_RV515) - h |= track->textures[u].height_11; - if (track->textures[u].roundup_h) - h = roundup_pow_of_two(h); - size += w * h; - } - size *= track->textures[u].cpp; - switch (track->textures[u].tex_coord_type) { - case 0: - break; - case 1: - size *= (1 << track->textures[u].txdepth); - break; - case 2: - size *= 6; - break; - default: - DRM_ERROR("Invalid texture coordinate type %u for unit " - "%u\n", track->textures[u].tex_coord_type, u); - return -EINVAL; - } - if (size > radeon_object_size(robj)) { - DRM_ERROR("Texture of unit %u needs %lu bytes but is " - "%lu\n", u, size, radeon_object_size(robj)); - r300_cs_track_texture_print(&track->textures[u]); - return -EINVAL; - } - } - return 0; -} - -int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track) -{ - unsigned i; - unsigned long size; - unsigned prim_walk; - unsigned nverts; - - for (i = 0; i < track->num_cb; i++) { - if (track->cb[i].robj == NULL) { - DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); - return -EINVAL; - } - size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; - size += track->cb[i].offset; - if (size > radeon_object_size(track->cb[i].robj)) { - DRM_ERROR("[drm] Buffer too small for color buffer %d " - "(need %lu have %lu) !\n", i, size, - radeon_object_size(track->cb[i].robj)); - DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", - i, track->cb[i].pitch, track->cb[i].cpp, - track->cb[i].offset, track->maxy); - return -EINVAL; - } - } - if (track->z_enabled) { - if (track->zb.robj == NULL) { - DRM_ERROR("[drm] No buffer for z buffer !\n"); - return -EINVAL; - } - size = track->zb.pitch * track->zb.cpp * track->maxy; - size += track->zb.offset; - if (size > radeon_object_size(track->zb.robj)) { - DRM_ERROR("[drm] Buffer too small for z buffer " - "(need %lu have %lu) !\n", size, - radeon_object_size(track->zb.robj)); - return -EINVAL; - } - } - prim_walk = (track->vap_vf_cntl >> 4) & 0x3; - nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; - switch (prim_walk) { - case 1: - for (i = 0; i < track->num_arrays; i++) { - size = track->arrays[i].esize * track->max_indx * 4; - if (track->arrays[i].robj == NULL) { - DRM_ERROR("(PW %u) Vertex array %u no buffer " - "bound\n", prim_walk, i); - return -EINVAL; - } - if (size > radeon_object_size(track->arrays[i].robj)) { - DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " - "have %lu dwords\n", prim_walk, i, - size >> 2, - radeon_object_size(track->arrays[i].robj) >> 2); - DRM_ERROR("Max indices %u\n", track->max_indx); - return -EINVAL; - } - } - break; - case 2: - for (i = 0; i < track->num_arrays; i++) { - size = track->arrays[i].esize * (nverts - 1) * 4; - if (track->arrays[i].robj == NULL) { - DRM_ERROR("(PW %u) Vertex array %u no buffer " - "bound\n", prim_walk, i); - return -EINVAL; - } - if (size > radeon_object_size(track->arrays[i].robj)) { - DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " - "have %lu dwords\n", prim_walk, i, size >> 2, - radeon_object_size(track->arrays[i].robj) >> 2); - return -EINVAL; - } - } - break; - case 3: - size = track->vtx_size * nverts; - if (size != track->immd_dwords) { - DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", - track->immd_dwords, size); - DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", - nverts, track->vtx_size); - return -EINVAL; - } - break; - default: - DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", - prim_walk); - return -EINVAL; - } - return r300_cs_track_texture_check(rdev, track); -} - -static inline void r300_cs_track_clear(struct r300_cs_track *track) -{ - unsigned i; - - track->num_cb = 4; - track->maxy = 4096; - for (i = 0; i < track->num_cb; i++) { - track->cb[i].robj = NULL; - track->cb[i].pitch = 8192; - track->cb[i].cpp = 16; - track->cb[i].offset = 0; - } - track->z_enabled = true; - track->zb.robj = NULL; - track->zb.pitch = 8192; - track->zb.cpp = 4; - track->zb.offset = 0; - track->vtx_size = 0x7F; - track->immd_dwords = 0xFFFFFFFFUL; - track->num_arrays = 11; - track->max_indx = 0x00FFFFFFUL; - for (i = 0; i < track->num_arrays; i++) { - track->arrays[i].robj = NULL; - track->arrays[i].esize = 0x7F; - } - for (i = 0; i < 16; i++) { - track->textures[i].pitch = 16536; - track->textures[i].width = 16536; - track->textures[i].height = 16536; - track->textures[i].width_11 = 1 << 11; - track->textures[i].height_11 = 1 << 11; - track->textures[i].num_levels = 12; - track->textures[i].txdepth = 16; - track->textures[i].cpp = 64; - track->textures[i].tex_coord_type = 1; - track->textures[i].robj = NULL; - /* CS IB emission code makes sure texture unit are disabled */ - track->textures[i].enabled = false; - track->textures[i].roundup_w = true; - track->textures[i].roundup_h = true; - } -} - static int r300_packet0_check(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, unsigned idx, unsigned reg) { struct radeon_cs_chunk *ib_chunk; struct radeon_cs_reloc *reloc; - struct r300_cs_track *track; + struct r100_cs_track *track; volatile uint32_t *ib; uint32_t tmp, tile_flags = 0; unsigned i; @@ -971,7 +717,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, ib = p->ib->ptr; ib_chunk = &p->chunks[p->chunk_ib_idx]; - track = (struct r300_cs_track*)p->track; + track = (struct r100_cs_track *)p->track; switch(reg) { case AVIVO_D1MODE_VLINE_START_END: case RADEON_CRTC_GUI_TRIG_VLINE: @@ -985,28 +731,9 @@ static int r300_packet0_check(struct radeon_cs_parser *p, break; case RADEON_DST_PITCH_OFFSET: case RADEON_SRC_PITCH_OFFSET: - r = r100_cs_packet_next_reloc(p, &reloc); - if (r) { - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", - idx, reg); - r100_cs_dump_packet(p, pkt); + r = r100_reloc_pitch_offset(p, pkt, idx, reg); + if (r) return r; - } - tmp = ib_chunk->kdata[idx] & 0x003fffff; - tmp += (((u32)reloc->lobj.gpu_offset) >> 10); - - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) - tile_flags |= RADEON_DST_TILE_MACRO; - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { - if (reg == RADEON_SRC_PITCH_OFFSET) { - DRM_ERROR("Cannot src blit from microtiled surface\n"); - r100_cs_dump_packet(p, pkt); - return -EINVAL; - } - tile_flags |= RADEON_DST_TILE_MICRO; - } - tmp |= tile_flags; - ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; break; case R300_RB3D_COLOROFFSET0: case R300_RB3D_COLOROFFSET1: @@ -1215,42 +942,41 @@ static int r300_packet0_check(struct radeon_cs_parser *p, tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; track->textures[i].tex_coord_type = tmp; switch ((ib_chunk->kdata[idx] & 0x1F)) { - case 0: - case 2: - case 5: - case 18: - case 20: - case 21: + case R300_TX_FORMAT_X8: + case R300_TX_FORMAT_Y4X4: + case R300_TX_FORMAT_Z3Y3X2: track->textures[i].cpp = 1; break; - case 1: - case 3: - case 6: - case 7: - case 10: - case 11: - case 19: - case 22: - case 24: + case R300_TX_FORMAT_X16: + case R300_TX_FORMAT_Y8X8: + case R300_TX_FORMAT_Z5Y6X5: + case R300_TX_FORMAT_Z6Y5X5: + case R300_TX_FORMAT_W4Z4Y4X4: + case R300_TX_FORMAT_W1Z5Y5X5: + case R300_TX_FORMAT_DXT1: + case R300_TX_FORMAT_D3DMFT_CxV8U8: + case R300_TX_FORMAT_B8G8_B8G8: + case R300_TX_FORMAT_G8R8_G8B8: track->textures[i].cpp = 2; break; - case 4: - case 8: - case 9: - case 12: - case 13: - case 23: - case 25: - case 27: - case 30: + case R300_TX_FORMAT_Y16X16: + case R300_TX_FORMAT_Z11Y11X10: + case R300_TX_FORMAT_Z10Y11X11: + case R300_TX_FORMAT_W8Z8Y8X8: + case R300_TX_FORMAT_W2Z10Y10X10: + case 0x17: + case R300_TX_FORMAT_FL_I32: + case 0x1e: + case R300_TX_FORMAT_DXT3: + case R300_TX_FORMAT_DXT5: track->textures[i].cpp = 4; break; - case 14: - case 26: - case 28: + case R300_TX_FORMAT_W16Z16Y16X16: + case R300_TX_FORMAT_FL_R16G16B16A16: + case R300_TX_FORMAT_FL_I32A32: track->textures[i].cpp = 8; break; - case 29: + case R300_TX_FORMAT_FL_R32G32B32A32: track->textures[i].cpp = 16; break; default: @@ -1278,11 +1004,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p, case 0x443C: /* TX_FILTER0_[0-15] */ i = (reg - 0x4400) >> 2; - tmp = ib_chunk->kdata[idx] & 0x7;; + tmp = ib_chunk->kdata[idx] & 0x7; if (tmp == 2 || tmp == 4 || tmp == 6) { track->textures[i].roundup_w = false; } - tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;; + tmp = (ib_chunk->kdata[idx] >> 3) & 0x7; if (tmp == 2 || tmp == 4 || tmp == 6) { track->textures[i].roundup_h = false; } @@ -1370,8 +1096,9 @@ static int r300_packet3_check(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt) { struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_reloc *reloc; - struct r300_cs_track *track; + struct r100_cs_track *track; volatile uint32_t *ib; unsigned idx; unsigned i, c; @@ -1380,7 +1107,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p, ib = p->ib->ptr; ib_chunk = &p->chunks[p->chunk_ib_idx]; idx = pkt->idx + 1; - track = (struct r300_cs_track*)p->track; + track = (struct r100_cs_track *)p->track; switch(pkt->opcode) { case PACKET3_3D_LOAD_VBPNTR: c = ib_chunk->kdata[idx++] & 0x1F; @@ -1447,7 +1174,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p, } track->vap_vf_cntl = ib_chunk->kdata[idx+1]; track->immd_dwords = pkt->count - 1; - r = r300_cs_track_check(p->rdev, track); + r = r100_cs_track_check(p->rdev, track); if (r) { return r; } @@ -1462,35 +1189,35 @@ static int r300_packet3_check(struct radeon_cs_parser *p, } track->vap_vf_cntl = ib_chunk->kdata[idx]; track->immd_dwords = pkt->count; - r = r300_cs_track_check(p->rdev, track); + r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_VBUF: track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; - r = r300_cs_track_check(p->rdev, track); + r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_VBUF_2: track->vap_vf_cntl = ib_chunk->kdata[idx]; - r = r300_cs_track_check(p->rdev, track); + r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_INDX: track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; - r = r300_cs_track_check(p->rdev, track); + r = r100_cs_track_check(p->rdev, track); if (r) { return r; } break; case PACKET3_3D_DRAW_INDX_2: track->vap_vf_cntl = ib_chunk->kdata[idx]; - r = r300_cs_track_check(p->rdev, track); + r = r100_cs_track_check(p->rdev, track); if (r) { return r; } @@ -1507,10 +1234,10 @@ static int r300_packet3_check(struct radeon_cs_parser *p, int r300_cs_parse(struct radeon_cs_parser *p) { struct radeon_cs_packet pkt; - struct r300_cs_track track; + struct r100_cs_track track; int r; - r300_cs_track_clear(&track); + r100_cs_track_clear(p->rdev, &track); p->track = &track; do { r = r100_cs_packet_parse(p, &pkt, p->idx); diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 149974d..6c35c3c 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -604,8 +604,14 @@ struct radeon_asic { void (*bandwidth_update)(struct radeon_device *rdev); }; +struct r100_asic { + const unsigned *reg_safe_bm; + unsigned reg_safe_bm_size; +}; + union radeon_asic_config { struct r300_asic r300; + struct r100_asic r100; }; diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 8ace151..c9cbd8a 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -42,6 +42,7 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ int r100_init(struct radeon_device *rdev); +int r200_init(struct radeon_device *rdev); uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); void r100_errata(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 4df43f6..404b39b 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h @@ -1945,6 +1945,11 @@ # define RADEON_TXFORMAT_DXT1 (12 << 0) # define RADEON_TXFORMAT_DXT23 (14 << 0) # define RADEON_TXFORMAT_DXT45 (15 << 0) +# define RADEON_TXFORMAT_SHADOW16 (16 << 0) +# define RADEON_TXFORMAT_SHADOW32 (17 << 0) +# define RADEON_TXFORMAT_DUDV88 (18 << 0) +# define RADEON_TXFORMAT_LDUDV655 (19 << 0) +# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0) # define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) # define RADEON_TXFORMAT_FORMAT_SHIFT 0 # define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) @@ -2203,7 +2208,7 @@ # define RADEON_ROP_ENABLE (1 << 6) # define RADEON_STENCIL_ENABLE (1 << 7) # define RADEON_Z_ENABLE (1 << 8) -# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) +# define RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9) # define RADEON_RB3D_COLOR_FORMAT_SHIFT 10 # define RADEON_COLOR_FORMAT_ARGB1555 3 @@ -2773,7 +2778,12 @@ # define R200_TXFORMAT_DXT1 (12 << 0) # define R200_TXFORMAT_DXT23 (14 << 0) # define R200_TXFORMAT_DXT45 (15 << 0) +# define R200_TXFORMAT_DVDU88 (18 << 0) +# define R200_TXFORMAT_LDVDU655 (19 << 0) +# define R200_TXFORMAT_LDVDU8888 (20 << 0) +# define R200_TXFORMAT_GR1616 (21 << 0) # define R200_TXFORMAT_ABGR8888 (22 << 0) +# define R200_TXFORMAT_BGR111110 (23 << 0) # define R200_TXFORMAT_FORMAT_MASK (31 << 0) # define R200_TXFORMAT_FORMAT_SHIFT 0 # define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) @@ -2818,6 +2828,13 @@ #define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ #define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ +#define R200_PP_CUBIC_FACES_0 0x2c18 +#define R200_PP_CUBIC_FACES_1 0x2c38 +#define R200_PP_CUBIC_FACES_2 0x2c58 +#define R200_PP_CUBIC_FACES_3 0x2c78 +#define R200_PP_CUBIC_FACES_4 0x2c98 +#define R200_PP_CUBIC_FACES_5 0x2cb8 + #define R200_PP_TXOFFSET_0 0x2d00 # define R200_TXO_ENDIAN_NO_SWAP (0 << 0) # define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) @@ -2829,11 +2846,44 @@ # define R200_TXO_MICRO_TILE (1 << 3) # define R200_TXO_OFFSET_MASK 0xffffffe0 # define R200_TXO_OFFSET_SHIFT 5 +#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 +#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 +#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c +#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 +#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 + #define R200_PP_TXOFFSET_1 0x2d18 +#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c +#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 +#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 +#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 +#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c + #define R200_PP_TXOFFSET_2 0x2d30 +#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 +#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 +#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c +#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 +#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 + #define R200_PP_TXOFFSET_3 0x2d48 +#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c +#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 +#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 +#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 +#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c #define R200_PP_TXOFFSET_4 0x2d60 +#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 +#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 +#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c +#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 +#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 #define R200_PP_TXOFFSET_5 0x2d78 +#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c +#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 +#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 +#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 +#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c #define R200_PP_TFACTOR_0 0x2ee0 #define R200_PP_TFACTOR_1 0x2ee4 @@ -3175,6 +3225,11 @@ # define R200_FORCE_INORDER_PROC (1<<31) #define R200_PP_CNTL_X 0x2cc4 #define R200_PP_TXMULTI_CTL_0 0x2c1c +#define R200_PP_TXMULTI_CTL_1 0x2c3c +#define R200_PP_TXMULTI_CTL_2 0x2c5c +#define R200_PP_TXMULTI_CTL_3 0x2c7c +#define R200_PP_TXMULTI_CTL_4 0x2c9c +#define R200_PP_TXMULTI_CTL_5 0x2cbc #define R200_SE_VTX_STATE_CNTL 0x2180 # define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) diff --git a/drivers/gpu/drm/radeon/reg_srcs/r100 b/drivers/gpu/drm/radeon/reg_srcs/r100 new file mode 100644 index 0000000..f7ee062 --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/r100 @@ -0,0 +1,105 @@ +r100 0x3294 +0x1434 SRC_Y_X +0x1438 DST_Y_X +0x143C DST_HEIGHT_WIDTH +0x146C DP_GUI_MASTER_CNTL +0x1474 BRUSH_Y_X +0x1478 DP_BRUSH_BKGD_CLR +0x147C DP_BRUSH_FRGD_CLR +0x1480 BRUSH_DATA0 +0x1484 BRUSH_DATA1 +0x1598 DST_WIDTH_HEIGHT +0x15C0 CLR_CMP_CNTL +0x15C4 CLR_CMP_CLR_SRC +0x15C8 CLR_CMP_CLR_DST +0x15CC CLR_CMP_MSK +0x15D8 DP_SRC_FRGD_CLR +0x15DC DP_SRC_BKGD_CLR +0x1600 DST_LINE_START +0x1604 DST_LINE_END +0x1608 DST_LINE_PATCOUNT +0x16C0 DP_CNTL +0x16CC DP_WRITE_MSK +0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR +0x16E8 DEFAULT_SC_BOTTOM_RIGHT +0x16EC SC_TOP_LEFT +0x16F0 SC_BOTTOM_RIGHT +0x16F4 SRC_SC_BOTTOM_RIGHT +0x1714 DSTCACHE_CTLSTAT +0x1720 WAIT_UNTIL +0x172C RBBM_GUICNTL +0x1810 FOG_3D_TABLE_START +0x1814 FOG_3D_TABLE_END +0x1a14 FOG_TABLE_INDEX +0x1a18 FOG_TABLE_DATA +0x1c14 PP_MISC +0x1c18 PP_FOG_COLOR +0x1c1c RE_SOLID_COLOR +0x1c20 RB3D_BLENDCNTL +0x1c4c SE_CNTL +0x1c50 SE_COORD_FMT +0x1c60 PP_TXCBLEND_0 +0x1c64 PP_TXABLEND_0 +0x1c68 PP_TFACTOR_0 +0x1c78 PP_TXCBLEND_1 +0x1c7c PP_TXABLEND_1 +0x1c80 PP_TFACTOR_1 +0x1c90 PP_TXCBLEND_2 +0x1c94 PP_TXABLEND_2 +0x1c98 PP_TFACTOR_2 +0x1cc8 RE_STIPPLE_ADDR +0x1ccc RE_STIPPLE_DATA +0x1cd0 RE_LINE_PATTERN +0x1cd4 RE_LINE_STATE +0x1d40 PP_BORDER_COLOR0 +0x1d44 PP_BORDER_COLOR1 +0x1d48 PP_BORDER_COLOR2 +0x1d7c RB3D_STENCILREFMASK +0x1d80 RB3D_ROPCNTL +0x1d84 RB3D_PLANEMASK +0x1d98 VAP_VPORT_XSCALE +0x1d9C VAP_VPORT_XOFFSET +0x1da0 VAP_VPORT_YSCALE +0x1da4 VAP_VPORT_YOFFSET +0x1da8 VAP_VPORT_ZSCALE +0x1dac VAP_VPORT_ZOFFSET +0x1db0 SE_ZBIAS_FACTOR +0x1db4 SE_ZBIAS_CONSTANT +0x1db8 SE_LINE_WIDTH +0x2140 SE_CNTL_STATUS +0x2200 SE_TCL_VECTOR_INDX_REG +0x2204 SE_TCL_VECTOR_DATA_REG +0x2208 SE_TCL_SCALAR_INDX_REG +0x220c SE_TCL_SCALAR_DATA_REG +0x2210 SE_TCL_MATERIAL_EMISSIVE_RED +0x2214 SE_TCL_MATERIAL_EMISSIVE_GREEN +0x2218 SE_TCL_MATERIAL_EMISSIVE_BLUE +0x221c SE_TCL_MATERIAL_EMISSIVE_ALPHA +0x2220 SE_TCL_MATERIAL_AMBIENT_RED +0x2224 SE_TCL_MATERIAL_AMBIENT_GREEN +0x2228 SE_TCL_MATERIAL_AMBIENT_BLUE +0x222c SE_TCL_MATERIAL_AMBIENT_ALPHA +0x2230 SE_TCL_MATERIAL_DIFFUSE_RED +0x2234 SE_TCL_MATERIAL_DIFFUSE_GREEN +0x2238 SE_TCL_MATERIAL_DIFFUSE_BLUE +0x223c SE_TCL_MATERIAL_DIFFUSE_ALPHA +0x2240 SE_TCL_MATERIAL_SPECULAR_RED +0x2244 SE_TCL_MATERIAL_SPECULAR_GREEN +0x2248 SE_TCL_MATERIAL_SPECULAR_BLUE +0x224c SE_TCL_MATERIAL_SPECULAR_ALPHA +0x2250 SE_TCL_SHININESS +0x2254 SE_TCL_OUTPUT_VTX_FMT +0x2258 SE_TCL_OUTPUT_VTX_SEL +0x225c SE_TCL_MATRIX_SELECT_0 +0x2260 SE_TCL_MATRIX_SELECT_1 +0x2264 SE_TCL_UCP_VERT_BLEND_CNTL +0x2268 SE_TCL_TEXTURE_PROC_CTL +0x226c SE_TCL_LIGHT_MODEL_CTL +0x2270 SE_TCL_PER_LIGHT_CTL_0 +0x2274 SE_TCL_PER_LIGHT_CTL_1 +0x2278 SE_TCL_PER_LIGHT_CTL_2 +0x227c SE_TCL_PER_LIGHT_CTL_3 +0x2284 SE_TCL_STATE_FLUSH +0x26c0 RE_TOP_LEFT +0x26c4 RE_MISC +0x3290 RB3D_ZPASS_DATA diff --git a/drivers/gpu/drm/radeon/reg_srcs/r200 b/drivers/gpu/drm/radeon/reg_srcs/r200 new file mode 100644 index 0000000..6021c88 --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/r200 @@ -0,0 +1,184 @@ +r200 0x3294 +0x1434 SRC_Y_X +0x1438 DST_Y_X +0x143C DST_HEIGHT_WIDTH +0x146C DP_GUI_MASTER_CNTL +0x1474 BRUSH_Y_X +0x1478 DP_BRUSH_BKGD_CLR +0x147C DP_BRUSH_FRGD_CLR +0x1480 BRUSH_DATA0 +0x1484 BRUSH_DATA1 +0x1598 DST_WIDTH_HEIGHT +0x15C0 CLR_CMP_CNTL +0x15C4 CLR_CMP_CLR_SRC +0x15C8 CLR_CMP_CLR_DST +0x15CC CLR_CMP_MSK +0x15D8 DP_SRC_FRGD_CLR +0x15DC DP_SRC_BKGD_CLR +0x1600 DST_LINE_START +0x1604 DST_LINE_END +0x1608 DST_LINE_PATCOUNT +0x16C0 DP_CNTL +0x16CC DP_WRITE_MSK +0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR +0x16E8 DEFAULT_SC_BOTTOM_RIGHT +0x16EC SC_TOP_LEFT +0x16F0 SC_BOTTOM_RIGHT +0x16F4 SRC_SC_BOTTOM_RIGHT +0x1714 DSTCACHE_CTLSTAT +0x1720 WAIT_UNTIL +0x172C RBBM_GUICNTL +0x1c14 PP_MISC +0x1c18 PP_FOG_COLOR +0x1c1c RE_SOLID_COLOR +0x1c20 RB3D_BLENDCNTL +0x1c4c SE_CNTL +0x1c50 RE_CNTL +0x1cc8 RE_STIPPLE_ADDR +0x1ccc RE_STIPPLE_DATA +0x1cd0 RE_LINE_PATTERN +0x1cd4 RE_LINE_STATE +0x1cd8 RE_SCISSOR_TL_0 +0x1cdc RE_SCISSOR_BR_0 +0x1ce0 RE_SCISSOR_TL_1 +0x1ce4 RE_SCISSOR_BR_1 +0x1ce8 RE_SCISSOR_TL_2 +0x1cec RE_SCISSOR_BR_2 +0x1d60 RB3D_DEPTHXY_OFFSET +0x1d7c RB3D_STENCILREFMASK +0x1d80 RB3D_ROPCNTL +0x1d84 RB3D_PLANEMASK +0x1d98 VAP_VPORT_XSCALE +0x1d9c VAP_VPORT_XOFFSET +0x1da0 VAP_VPORT_YSCALE +0x1da4 VAP_VPORT_YOFFSET +0x1da8 VAP_VPORT_ZSCALE +0x1dac VAP_VPORT_ZOFFSET +0x1db0 SE_ZBIAS_FACTOR +0x1db4 SE_ZBIAS_CONSTANT +0x1db8 SE_LINE_WIDTH +0x2080 SE_VAP_CNTL +0x2090 SE_TCL_OUTPUT_VTX_FMT_0 +0x2094 SE_TCL_OUTPUT_VTX_FMT_1 +0x20b0 SE_VTE_CNTL +0x2140 SE_CNTL_STATUS +0x2180 SE_VTX_STATE_CNTL +0x2200 SE_TCL_VECTOR_INDX_REG +0x2204 SE_TCL_VECTOR_DATA_REG +0x2208 SE_TCL_SCALAR_INDX_REG +0x220c SE_TCL_SCALAR_DATA_REG +0x2230 SE_TCL_MATRIX_SEL_0 +0x2234 SE_TCL_MATRIX_SEL_1 +0x2238 SE_TCL_MATRIX_SEL_2 +0x223c SE_TCL_MATRIX_SEL_3 +0x2240 SE_TCL_MATRIX_SEL_4 +0x2250 SE_TCL_OUTPUT_VTX_COMP_SEL +0x2254 SE_TCL_INPUT_VTX_VECTOR_ADDR_0 +0x2258 SE_TCL_INPUT_VTX_VECTOR_ADDR_1 +0x225c SE_TCL_INPUT_VTX_VECTOR_ADDR_2 +0x2260 SE_TCL_INPUT_VTX_VECTOR_ADDR_3 +0x2268 SE_TCL_LIGHT_MODEL_CTL_0 +0x226c SE_TCL_LIGHT_MODEL_CTL_1 +0x2270 SE_TCL_PER_LIGHT_CTL_0 +0x2274 SE_TCL_PER_LIGHT_CTL_1 +0x2278 SE_TCL_PER_LIGHT_CTL_2 +0x227c SE_TCL_PER_LIGHT_CTL_3 +0x2284 VAP_PVS_STATE_FLUSH_REG +0x22a8 SE_TCL_TEX_PROC_CTL_2 +0x22ac SE_TCL_TEX_PROC_CTL_3 +0x22b0 SE_TCL_TEX_PROC_CTL_0 +0x22b4 SE_TCL_TEX_PROC_CTL_1 +0x22b8 SE_TCL_TEX_CYL_WRAP_CTL +0x22c0 SE_TCL_UCP_VERT_BLEND_CNTL +0x22c4 SE_TCL_POINT_SPRITE_CNTL +0x2648 RE_POINTSIZE +0x26c0 RE_TOP_LEFT +0x26c4 RE_MISC +0x26f0 RE_AUX_SCISSOR_CNTL +0x2c14 PP_BORDER_COLOR_0 +0x2c34 PP_BORDER_COLOR_1 +0x2c54 PP_BORDER_COLOR_2 +0x2c74 PP_BORDER_COLOR_3 +0x2c94 PP_BORDER_COLOR_4 +0x2cb4 PP_BORDER_COLOR_5 +0x2cc4 PP_CNTL_X +0x2cf8 PP_TRI_PERF +0x2cfc PP_PERF_CNTL +0x2d9c PP_TAM_DEBUG3 +0x2ee0 PP_TFACTOR_0 +0x2ee4 PP_TFACTOR_1 +0x2ee8 PP_TFACTOR_2 +0x2eec PP_TFACTOR_3 +0x2ef0 PP_TFACTOR_4 +0x2ef4 PP_TFACTOR_5 +0x2ef8 PP_TFACTOR_6 +0x2efc PP_TFACTOR_7 +0x2f00 PP_TXCBLEND_0 +0x2f04 PP_TXCBLEND2_0 +0x2f08 PP_TXABLEND_0 +0x2f0c PP_TXABLEND2_0 +0x2f10 PP_TXCBLEND_1 +0x2f14 PP_TXCBLEND2_1 +0x2f18 PP_TXABLEND_1 +0x2f1c PP_TXABLEND2_1 +0x2f20 PP_TXCBLEND_2 +0x2f24 PP_TXCBLEND2_2 +0x2f28 PP_TXABLEND_2 +0x2f2c PP_TXABLEND2_2 +0x2f30 PP_TXCBLEND_3 +0x2f34 PP_TXCBLEND2_3 +0x2f38 PP_TXABLEND_3 +0x2f3c PP_TXABLEND2_3 +0x2f40 PP_TXCBLEND_4 +0x2f44 PP_TXCBLEND2_4 +0x2f48 PP_TXABLEND_4 +0x2f4c PP_TXABLEND2_4 +0x2f50 PP_TXCBLEND_5 +0x2f54 PP_TXCBLEND2_5 +0x2f58 PP_TXABLEND_5 +0x2f5c PP_TXABLEND2_5 +0x2f60 PP_TXCBLEND_6 +0x2f64 PP_TXCBLEND2_6 +0x2f68 PP_TXABLEND_6 +0x2f6c PP_TXABLEND2_6 +0x2f70 PP_TXCBLEND_7 +0x2f74 PP_TXCBLEND2_7 +0x2f78 PP_TXABLEND_7 +0x2f7c PP_TXABLEND2_7 +0x2f80 PP_TXCBLEND_8 +0x2f84 PP_TXCBLEND2_8 +0x2f88 PP_TXABLEND_8 +0x2f8c PP_TXABLEND2_8 +0x2f90 PP_TXCBLEND_9 +0x2f94 PP_TXCBLEND2_9 +0x2f98 PP_TXABLEND_9 +0x2f9c PP_TXABLEND2_9 +0x2fa0 PP_TXCBLEND_10 +0x2fa4 PP_TXCBLEND2_10 +0x2fa8 PP_TXABLEND_10 +0x2fac PP_TXABLEND2_10 +0x2fb0 PP_TXCBLEND_11 +0x2fb4 PP_TXCBLEND2_11 +0x2fb8 PP_TXABLEND_11 +0x2fbc PP_TXABLEND2_11 +0x2fc0 PP_TXCBLEND_12 +0x2fc4 PP_TXCBLEND2_12 +0x2fc8 PP_TXABLEND_12 +0x2fcc PP_TXABLEND2_12 +0x2fd0 PP_TXCBLEND_13 +0x2fd4 PP_TXCBLEND2_13 +0x2fd8 PP_TXABLEND_13 +0x2fdc PP_TXABLEND2_13 +0x2fe0 PP_TXCBLEND_14 +0x2fe4 PP_TXCBLEND2_14 +0x2fe8 PP_TXABLEND_14 +0x2fec PP_TXABLEND2_14 +0x2ff0 PP_TXCBLEND_15 +0x2ff4 PP_TXCBLEND2_15 +0x2ff8 PP_TXABLEND_15 +0x2ffc PP_TXABLEND2_15 +0x3218 RB3D_BLENCOLOR +0x321c RB3D_ABLENDCNTL +0x3220 RB3D_CBLENDCNTL +0x3290 RB3D_ZPASS_DATA + diff --git a/drivers/gpu/drm/radeon/reg_srcs/rn50 b/drivers/gpu/drm/radeon/reg_srcs/rn50 new file mode 100644 index 0000000..2687b63 --- /dev/null +++ b/drivers/gpu/drm/radeon/reg_srcs/rn50 @@ -0,0 +1,30 @@ +rn50 0x3294 +0x1434 SRC_Y_X +0x1438 DST_Y_X +0x143C DST_HEIGHT_WIDTH +0x146C DP_GUI_MASTER_CNTL +0x1474 BRUSH_Y_X +0x1478 DP_BRUSH_BKGD_CLR +0x147C DP_BRUSH_FRGD_CLR +0x1480 BRUSH_DATA0 +0x1484 BRUSH_DATA1 +0x1598 DST_WIDTH_HEIGHT +0x15C0 CLR_CMP_CNTL +0x15C4 CLR_CMP_CLR_SRC +0x15C8 CLR_CMP_CLR_DST +0x15CC CLR_CMP_MSK +0x15D8 DP_SRC_FRGD_CLR +0x15DC DP_SRC_BKGD_CLR +0x1600 DST_LINE_START +0x1604 DST_LINE_END +0x1608 DST_LINE_PATCOUNT +0x16C0 DP_CNTL +0x16CC DP_WRITE_MSK +0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR +0x16E8 DEFAULT_SC_BOTTOM_RIGHT +0x16EC SC_TOP_LEFT +0x16F0 SC_BOTTOM_RIGHT +0x16F4 SRC_SC_BOTTOM_RIGHT +0x1714 DSTCACHE_CTLSTAT +0x1720 WAIT_UNTIL +0x172C RBBM_GUICNTL -- cgit v0.10.2 From 4ce001abafafe77e5dd943d1480fc9f87894e96f Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 13 Aug 2009 16:32:14 +1000 Subject: drm/radeon/kms: add initial radeon tv-out support. This ports the tv-out code from the DDX to KMS. adds a radeon.tv module option, radeon.tv=0 to disable tv Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 6fb8429..c5db0c4 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -47,7 +47,7 @@ radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \ radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \ radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \ - radeon_test.o r200.o + radeon_test.o r200.o radeon_legacy_tv.o radeon-$(CONFIG_COMPAT) += radeon_ioc32.o diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h index cf67928..5d40208 100644 --- a/drivers/gpu/drm/radeon/atombios.h +++ b/drivers/gpu/drm/radeon/atombios.h @@ -2374,6 +2374,17 @@ typedef struct _ATOM_ANALOG_TV_INFO { ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; } ATOM_ANALOG_TV_INFO; +#define MAX_SUPPORTED_TV_TIMING_V1_2 3 + +typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucTV_SupportedStandard; + UCHAR ucTV_BootUpDefaultStandard; + UCHAR ucExt_TV_ASIC_ID; + UCHAR ucExt_TV_ASIC_SlaveAddr; + ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; +} ATOM_ANALOG_TV_INFO_V1_2; + /**************************************************************************/ /* VRAM usage and their defintions */ diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 74d034f..8e31e99 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -31,6 +31,10 @@ #include "atom.h" #include "atom-bits.h" +/* evil but including atombios.h is much worse */ +bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, + SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, + int32_t *pixel_clock); static void atombios_overscan_setup(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) @@ -89,17 +93,32 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); ENABLE_SCALER_PS_ALLOCATION args; int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); + /* fixme - fill in enc_priv for atom dac */ enum radeon_tv_std tv_std = TV_STD_NTSC; + bool is_tv = false, is_cv = false; + struct drm_encoder *encoder; if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) return; + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + /* find tv std */ + if (encoder->crtc == crtc) { + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { + struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; + tv_std = tv_dac->tv_std; + is_tv = true; + } + } + } + memset(&args, 0, sizeof(args)); args.ucScaler = radeon_crtc->crtc_id; - if (radeon_crtc->devices & (ATOM_DEVICE_TV_SUPPORT)) { + if (is_tv) { switch (tv_std) { case TV_STD_NTSC: default: @@ -128,7 +147,7 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) break; } args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; - } else if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT)) { + } else if (is_cv) { args.ucTVStandard = ATOM_TV_CV; args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; } else { @@ -151,9 +170,9 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) } } atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); - if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT) - && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) { - atom_rv515_force_tv_scaler(rdev); + if ((is_tv || is_cv) + && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { + atom_rv515_force_tv_scaler(rdev, radeon_crtc); } } @@ -551,42 +570,68 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, struct radeon_device *rdev = dev->dev_private; struct drm_encoder *encoder; SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; + int need_tv_timings = 0; + bool ret; /* TODO color tiling */ memset(&crtc_timing, 0, sizeof(crtc_timing)); - /* TODO tv */ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - + /* find tv std */ + if (encoder->crtc == crtc) { + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + + if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { + struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; + if (tv_dac) { + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M) + need_tv_timings = 1; + else + need_tv_timings = 2; + break; + } + } + } } crtc_timing.ucCRTC = radeon_crtc->crtc_id; - crtc_timing.usH_Total = adjusted_mode->crtc_htotal; - crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay; - crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start; - crtc_timing.usH_SyncWidth = - adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; + if (need_tv_timings) { + ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1, + &crtc_timing, &adjusted_mode->clock); + if (ret == false) + need_tv_timings = 0; + } + + if (!need_tv_timings) { + crtc_timing.usH_Total = adjusted_mode->crtc_htotal; + crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay; + crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start; + crtc_timing.usH_SyncWidth = + adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; - crtc_timing.usV_Total = adjusted_mode->crtc_vtotal; - crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay; - crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start; - crtc_timing.usV_SyncWidth = - adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; + crtc_timing.usV_Total = adjusted_mode->crtc_vtotal; + crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay; + crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start; + crtc_timing.usV_SyncWidth = + adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; - if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) - crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; + if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) + crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; - if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) - crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; + if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) + crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; - if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) - crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; + if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) + crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) - crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) + crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; - if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) - crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; + if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) + crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; + } atombios_crtc_set_pll(crtc, adjusted_mode); atombios_crtc_set_timing(crtc, &crtc_timing); diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 6c35c3c..e47f2fc 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -66,6 +66,7 @@ extern int radeon_gart_size; extern int radeon_benchmarking; extern int radeon_testing; extern int radeon_connector_table; +extern int radeon_tv; /* * Copy from radeon_drv.h so we don't have to include both and have conflicting diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index fcfe5c0..bba9b4b 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -471,11 +471,6 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct continue; } - if (i == ATOM_DEVICE_TV1_INDEX) { - DRM_DEBUG("Skipping TV Out\n"); - continue; - } - bios_connectors[i].connector_type = supported_devices_connector_convert[ci.sucConnectorInfo. sbfAccess. @@ -858,6 +853,72 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) return p_dac; } +bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, + SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, + int32_t *pixel_clock) +{ + struct radeon_mode_info *mode_info = &rdev->mode_info; + ATOM_ANALOG_TV_INFO *tv_info; + ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; + ATOM_DTD_FORMAT *dtd_timings; + int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); + u8 frev, crev; + uint16_t data_offset; + + atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset); + + switch (crev) { + case 1: + tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); + if (index > MAX_SUPPORTED_TV_TIMING) + return false; + + crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); + crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); + crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); + crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); + + crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); + crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); + crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); + crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); + + crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo; + + crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight); + crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft); + crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom); + crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop); + *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; + + if (index == 1) { + /* PAL timings appear to have wrong values for totals */ + crtc_timing->usH_Total -= 1; + crtc_timing->usV_Total -= 1; + } + break; + case 2: + tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); + if (index > MAX_SUPPORTED_TV_TIMING_V1_2) + return false; + + dtd_timings = &tv_info_v1_2->aModeTimings[index]; + crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time); + crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive); + crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset); + crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth); + crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time); + crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive); + crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset); + crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth); + + crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); + *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10; + break; + } + return true; +} + struct radeon_encoder_tv_dac * radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) { @@ -948,10 +1009,10 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) uint32_t bios_2_scratch, bios_6_scratch; if (rdev->family >= CHIP_R600) { - bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH); + bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); } else { - bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH); + bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); } diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index 70ede6a..6a2b029 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c @@ -94,6 +94,54 @@ struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector) return NULL; } + +/* + * radeon_connector_analog_encoder_conflict_solve + * - search for other connectors sharing this encoder + * if priority is true, then set them disconnected if this is connected + * if priority is false, set us disconnected if they are connected + */ +static enum drm_connector_status +radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector, + struct drm_encoder *encoder, + enum drm_connector_status current_status, + bool priority) +{ + struct drm_device *dev = connector->dev; + struct drm_connector *conflict; + int i; + + list_for_each_entry(conflict, &dev->mode_config.connector_list, head) { + if (conflict == connector) + continue; + + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { + if (conflict->encoder_ids[i] == 0) + break; + + /* if the IDs match */ + if (conflict->encoder_ids[i] == encoder->base.id) { + if (conflict->status != connector_status_connected) + continue; + + if (priority == true) { + DRM_INFO("1: conflicting encoders switching off %s\n", drm_get_connector_name(conflict)); + DRM_INFO("in favor of %s\n", drm_get_connector_name(connector)); + conflict->status = connector_status_disconnected; + radeon_connector_update_scratch_regs(conflict, connector_status_disconnected); + } else { + DRM_INFO("2: conflicting encoders switching off %s\n", drm_get_connector_name(connector)); + DRM_INFO("in favor of %s\n", drm_get_connector_name(conflict)); + current_status = connector_status_disconnected; + } + break; + } + } + } + return current_status; + +} + static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder) { struct drm_device *dev = encoder->dev; @@ -213,7 +261,6 @@ static int radeon_vga_get_modes(struct drm_connector *connector) static int radeon_vga_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { - return MODE_OK; } @@ -225,22 +272,22 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect bool dret; enum drm_connector_status ret = connector_status_disconnected; + encoder = radeon_best_single_encoder(connector); + if (!encoder) + ret = connector_status_disconnected; + radeon_i2c_do_lock(radeon_connector, 1); dret = radeon_ddc_probe(radeon_connector); radeon_i2c_do_lock(radeon_connector, 0); if (dret) ret = connector_status_connected; else { - /* if EDID fails to a load detect */ - encoder = radeon_best_single_encoder(connector); - if (!encoder) - ret = connector_status_disconnected; - else { - encoder_funcs = encoder->helper_private; - ret = encoder_funcs->detect(encoder, connector); - } + encoder_funcs = encoder->helper_private; + ret = encoder_funcs->detect(encoder, connector); } + if (ret == connector_status_connected) + ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true); radeon_connector_update_scratch_regs(connector, ret); return ret; } @@ -259,21 +306,87 @@ struct drm_connector_funcs radeon_vga_connector_funcs = { .set_property = radeon_connector_set_property, }; +static struct drm_display_mode tv_fixed_mode = { + DRM_MODE("800x600", DRM_MODE_TYPE_DEFAULT, 38250, 800, 832, + 912, 1024, 0, 600, 603, 607, 624, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC), +}; + +static int radeon_tv_get_modes(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct drm_display_mode *tv_mode; + + tv_mode = drm_mode_duplicate(dev, &tv_fixed_mode); + tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + + drm_mode_probed_add(connector, tv_mode); + + return 1; +} + +static int radeon_tv_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + return MODE_OK; +} + +static enum drm_connector_status radeon_tv_detect(struct drm_connector *connector) +{ + struct drm_encoder *encoder; + struct drm_encoder_helper_funcs *encoder_funcs; + int ret; + + encoder = radeon_best_single_encoder(connector); + if (!encoder) + ret = connector_status_disconnected; + else { + encoder_funcs = encoder->helper_private; + ret = encoder_funcs->detect(encoder, connector); + } + if (ret == connector_status_connected) + ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false); + radeon_connector_update_scratch_regs(connector, ret); + return ret; +} + +struct drm_connector_helper_funcs radeon_tv_connector_helper_funcs = { + .get_modes = radeon_tv_get_modes, + .mode_valid = radeon_tv_mode_valid, + .best_encoder = radeon_best_single_encoder, +}; + +struct drm_connector_funcs radeon_tv_connector_funcs = { + .dpms = drm_helper_connector_dpms, + .detect = radeon_tv_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = radeon_connector_destroy, + .set_property = radeon_connector_set_property, +}; + static int radeon_dvi_get_modes(struct drm_connector *connector) { struct radeon_connector *radeon_connector = to_radeon_connector(connector); int ret; ret = radeon_ddc_get_modes(radeon_connector); - /* reset scratch regs here since radeon_dvi_detect doesn't check digital bit */ - radeon_connector_update_scratch_regs(connector, connector_status_connected); return ret; } +/* + * DVI is complicated + * Do a DDC probe, if DDC probe passes, get the full EDID so + * we can do analog/digital monitor detection at this point. + * If the monitor is an analog monitor or we got no DDC, + * we need to find the DAC encoder object for this connector. + * If we got no DDC, we do load detection on the DAC encoder object. + * If we got analog DDC or load detection passes on the DAC encoder + * we have to check if this analog encoder is shared with anyone else (TV) + * if its shared we have to set the other connector to disconnected. + */ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connector) { struct radeon_connector *radeon_connector = to_radeon_connector(connector); - struct drm_encoder *encoder; + struct drm_encoder *encoder = NULL; struct drm_encoder_helper_funcs *encoder_funcs; struct drm_mode_object *obj; int i; @@ -283,32 +396,58 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect radeon_i2c_do_lock(radeon_connector, 1); dret = radeon_ddc_probe(radeon_connector); radeon_i2c_do_lock(radeon_connector, 0); - if (dret) - ret = connector_status_connected; - else { - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { - if (connector->encoder_ids[i] == 0) - break; + if (dret) { + radeon_i2c_do_lock(radeon_connector, 1); + radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); + radeon_i2c_do_lock(radeon_connector, 0); + + if (!radeon_connector->edid) { + DRM_ERROR("DDC responded but not EDID found for %s\n", + drm_get_connector_name(connector)); + } else { + radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); + + /* if this isn't a digital monitor + then we need to make sure we don't have any + TV conflicts */ + ret = connector_status_connected; + } + } + + if ((ret == connector_status_connected) && (radeon_connector->use_digital == true)) + goto out; + + /* find analog encoder */ + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { + if (connector->encoder_ids[i] == 0) + break; - obj = drm_mode_object_find(connector->dev, - connector->encoder_ids[i], - DRM_MODE_OBJECT_ENCODER); - if (!obj) - continue; + obj = drm_mode_object_find(connector->dev, + connector->encoder_ids[i], + DRM_MODE_OBJECT_ENCODER); + if (!obj) + continue; - encoder = obj_to_encoder(obj); + encoder = obj_to_encoder(obj); - encoder_funcs = encoder->helper_private; - if (encoder_funcs->detect) { + encoder_funcs = encoder->helper_private; + if (encoder_funcs->detect) { + if (ret != connector_status_connected) { ret = encoder_funcs->detect(encoder, connector); if (ret == connector_status_connected) { - radeon_connector->use_digital = 0; - break; + radeon_connector->use_digital = false; } } + break; } } + if ((ret == connector_status_connected) && (radeon_connector->use_digital == false) && + encoder) { + ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true); + } + +out: /* updated in get modes as well since we need to know if it's analog or digital */ radeon_connector_update_scratch_regs(connector, ret); return ret; @@ -332,7 +471,7 @@ struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector) encoder = obj_to_encoder(obj); - if (radeon_connector->use_digital) { + if (radeon_connector->use_digital == true) { if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) return encoder; } else { @@ -385,10 +524,7 @@ radeon_add_atom_connector(struct drm_device *dev, uint32_t subpixel_order = SubPixelNone; /* fixme - tv/cv/din */ - if ((connector_type == DRM_MODE_CONNECTOR_Unknown) || - (connector_type == DRM_MODE_CONNECTOR_SVIDEO) || - (connector_type == DRM_MODE_CONNECTOR_Composite) || - (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) + if (connector_type == DRM_MODE_CONNECTOR_Unknown) return; /* see if we already added it */ @@ -480,6 +616,10 @@ radeon_add_atom_connector(struct drm_device *dev, case DRM_MODE_CONNECTOR_SVIDEO: case DRM_MODE_CONNECTOR_Composite: case DRM_MODE_CONNECTOR_9PinDIN: + if (radeon_tv == 1) { + drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); + drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); + } break; case DRM_MODE_CONNECTOR_LVDS: radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); @@ -522,10 +662,7 @@ radeon_add_legacy_connector(struct drm_device *dev, uint32_t subpixel_order = SubPixelNone; /* fixme - tv/cv/din */ - if ((connector_type == DRM_MODE_CONNECTOR_Unknown) || - (connector_type == DRM_MODE_CONNECTOR_SVIDEO) || - (connector_type == DRM_MODE_CONNECTOR_Composite) || - (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) + if (connector_type == DRM_MODE_CONNECTOR_Unknown) return; /* see if we already added it */ @@ -578,6 +715,10 @@ radeon_add_legacy_connector(struct drm_device *dev, case DRM_MODE_CONNECTOR_SVIDEO: case DRM_MODE_CONNECTOR_Composite: case DRM_MODE_CONNECTOR_9PinDIN: + if (radeon_tv == 1) { + drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); + drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); + } break; case DRM_MODE_CONNECTOR_LVDS: drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index af03560..9d817a6 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -312,7 +312,7 @@ static void radeon_print_display_setup(struct drm_device *dev) } } -bool radeon_setup_enc_conn(struct drm_device *dev) +static bool radeon_setup_enc_conn(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; struct drm_connector *drm_connector; @@ -346,9 +346,13 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) if (!radeon_connector->ddc_bus) return -1; - radeon_i2c_do_lock(radeon_connector, 1); - edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); - radeon_i2c_do_lock(radeon_connector, 0); + if (!radeon_connector->edid) { + radeon_i2c_do_lock(radeon_connector, 1); + edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); + radeon_i2c_do_lock(radeon_connector, 0); + } else + edid = radeon_connector->edid; + if (edid) { /* update digital bits here */ if (edid->input & DRM_EDID_INPUT_DIGITAL) @@ -677,7 +681,6 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, continue; if (first) { radeon_crtc->rmx_type = radeon_encoder->rmx_type; - radeon_crtc->devices = radeon_encoder->devices; memcpy(&radeon_crtc->native_mode, &radeon_encoder->native_mode, sizeof(struct radeon_native_mode)); diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 0bd5879..133e975 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -91,6 +91,7 @@ int radeon_gart_size = 512; /* default gart size */ int radeon_benchmarking = 0; int radeon_testing = 0; int radeon_connector_table = 0; +int radeon_tv = 1; #endif MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); @@ -123,6 +124,9 @@ module_param_named(test, radeon_testing, int, 0444); MODULE_PARM_DESC(connector_table, "Force connector table"); module_param_named(connector_table, radeon_connector_table, int, 0444); + +MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); +module_param_named(tv, radeon_tv, int, 0444); #endif static int radeon_suspend(struct drm_device *dev, pm_message_t state) diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index 0a92706..5c4ede7c 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c @@ -126,6 +126,23 @@ radeon_link_encoder_connector(struct drm_device *dev) } } +void radeon_encoder_set_active_device(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct drm_connector *connector; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + struct radeon_connector *radeon_connector = to_radeon_connector(connector); + radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; + DRM_INFO("setting active device to %08x from %08x %08x for encoder %d\n", + radeon_encoder->active_device, radeon_encoder->devices, + radeon_connector->devices, encoder->encoder_type); + } + } +} + static struct drm_connector * radeon_get_connector_for_encoder(struct drm_encoder *encoder) { @@ -244,9 +261,9 @@ atombios_dac_setup(struct drm_encoder *encoder, int action) args.ucAction = action; - if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) args.ucDacStandard = ATOM_DAC1_PS2; - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) args.ucDacStandard = ATOM_DAC1_CV; else { switch (tv_std) { @@ -288,7 +305,7 @@ atombios_tv_setup(struct drm_encoder *encoder, int action) args.sTVEncoder.ucAction = action; - if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) args.sTVEncoder.ucTvStandard = ATOM_TV_CV; else { switch (tv_std) { @@ -825,10 +842,10 @@ atombios_yuv_setup(struct drm_encoder *encoder, bool enable) /* XXX: fix up scratch reg handling */ temp = RREG32(reg); - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) WREG32(reg, (ATOM_S3_TV1_ACTIVE | (radeon_crtc->crtc_id << 18))); - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); else WREG32(reg, 0); @@ -851,9 +868,19 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; int index = 0; bool is_dig = false; + int devices; memset(&args, 0, sizeof(args)); + /* on DPMS off we have no idea if active device is meaningful */ + if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device) + devices = radeon_encoder->devices; + else + devices = radeon_encoder->active_device; + + DRM_INFO("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", + radeon_encoder->encoder_id, mode, radeon_encoder->devices, + radeon_encoder->active_device); switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_TMDS1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: @@ -881,18 +908,18 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) break; case ENCODER_OBJECT_ID_INTERNAL_DAC1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (devices & (ATOM_DEVICE_TV_SUPPORT)) index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (devices & (ATOM_DEVICE_CV_SUPPORT)) index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); else index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); break; case ENCODER_OBJECT_ID_INTERNAL_DAC2: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (devices & (ATOM_DEVICE_TV_SUPPORT)) index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (devices & (ATOM_DEVICE_CV_SUPPORT)) index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); else index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); @@ -979,18 +1006,18 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) break; case ENCODER_OBJECT_ID_INTERNAL_DAC1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; else args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; break; case ENCODER_OBJECT_ID_INTERNAL_DAC2: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; else args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; @@ -1019,17 +1046,17 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; else args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; - else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) + else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; else args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; @@ -1097,7 +1124,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, atombios_set_encoder_crtc_source(encoder); if (ASIC_IS_AVIVO(rdev)) { - if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) atombios_yuv_setup(encoder, true); else atombios_yuv_setup(encoder, false); @@ -1135,7 +1162,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, case ENCODER_OBJECT_ID_INTERNAL_DAC2: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: atombios_dac_setup(encoder, ATOM_ENABLE); - if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) atombios_tv_setup(encoder, ATOM_ENABLE); break; } @@ -1143,11 +1170,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, } static bool -atombios_dac_load_detect(struct drm_encoder *encoder) +atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_connector *radeon_connector = to_radeon_connector(connector); if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT | @@ -1168,15 +1196,15 @@ atombios_dac_load_detect(struct drm_encoder *encoder) else args.sDacload.ucDacType = ATOM_DAC_B; - if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) + if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); - else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) + else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); - else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { + else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); if (crev >= 3) args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; - } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { + } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); if (crev >= 3) args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; @@ -1195,9 +1223,10 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_connector *radeon_connector = to_radeon_connector(connector); uint32_t bios_0_scratch; - if (!atombios_dac_load_detect(encoder)) { + if (!atombios_dac_load_detect(encoder, connector)) { DRM_DEBUG("detect returned false \n"); return connector_status_unknown; } @@ -1207,17 +1236,20 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec else bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); - DRM_DEBUG("Bios 0 scratch %x\n", bios_0_scratch); - if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { + DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); + if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { if (bios_0_scratch & ATOM_S0_CRT1_MASK) return connector_status_connected; - } else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { + } + if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { if (bios_0_scratch & ATOM_S0_CRT2_MASK) return connector_status_connected; - } else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { + } + if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) return connector_status_connected; - } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { + } + if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) return connector_status_connected; /* CTV */ else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) @@ -1230,6 +1262,8 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) { radeon_atom_output_lock(encoder, true); radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); + + radeon_encoder_set_active_device(encoder); } static void radeon_atom_encoder_commit(struct drm_encoder *encoder) @@ -1238,12 +1272,21 @@ static void radeon_atom_encoder_commit(struct drm_encoder *encoder) radeon_atom_output_lock(encoder, false); } +static void radeon_atom_encoder_disable(struct drm_encoder *encoder) +{ + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); + DRM_INFO("setting active device to 0 for encoder %d\n", encoder->encoder_type); + radeon_encoder->active_device = 0; +} + static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { .dpms = radeon_atom_encoder_dpms, .mode_fixup = radeon_atom_mode_fixup, .prepare = radeon_atom_encoder_prepare, .mode_set = radeon_atom_encoder_mode_set, .commit = radeon_atom_encoder_commit, + .disable = radeon_atom_encoder_disable, /* no detect for TMDS/LVDS yet */ }; @@ -1268,6 +1311,18 @@ static const struct drm_encoder_funcs radeon_atom_enc_funcs = { .destroy = radeon_enc_destroy, }; +struct radeon_encoder_atom_dac * +radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) +{ + struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); + + if (!dac) + return NULL; + + dac->tv_std = TV_STD_NTSC; + return dac; +} + struct radeon_encoder_atom_dig * radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) { @@ -1336,6 +1391,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); + radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); break; case ENCODER_OBJECT_ID_INTERNAL_DVO1: diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index 0da72f1..0d29d15 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c @@ -28,6 +28,7 @@ #include #include "radeon_fixed.h" #include "radeon.h" +#include "atom.h" static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, @@ -501,6 +502,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod struct drm_device *dev = crtc->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct drm_encoder *encoder; int format; int hsync_start; int hsync_wid; @@ -509,8 +511,19 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod uint32_t crtc_h_sync_strt_wid; uint32_t crtc_v_total_disp; uint32_t crtc_v_sync_strt_wid; + bool is_tv = false; DRM_DEBUG("\n"); + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { + is_tv = true; + DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); + break; + } + } + } switch (crtc->fb->bits_per_pixel) { case 15: /* 555 */ @@ -642,6 +655,11 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); } + if (is_tv) + radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, + &crtc_h_sync_strt_wid, &crtc_v_total_disp, + &crtc_v_sync_strt_wid); + WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); @@ -668,7 +686,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) uint32_t pll_ref_div = 0; uint32_t pll_fb_post_div = 0; uint32_t htotal_cntl = 0; - + bool is_tv = false; struct radeon_pll *pll; struct { @@ -703,6 +721,13 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { if (encoder->crtc == crtc) { + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + + if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { + is_tv = true; + break; + } + if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { @@ -766,6 +791,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); + if (is_tv) { + radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, + &pll_ref_div, &pll_fb_post_div, + &pixclks_cntl); + } + WREG32_PLL_P(RADEON_PIXCLKS_CNTL, RADEON_PIX2CLK_SRC_SEL_CPUCLK, ~(RADEON_PIX2CLK_SRC_SEL_MASK)); @@ -820,6 +851,15 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); } else { + uint32_t pixclks_cntl; + + + if (is_tv) { + pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); + radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, + &pll_fb_post_div, &pixclks_cntl); + } + if (rdev->flags & RADEON_IS_MOBILITY) { /* A temporal workaround for the occational blanking on certain laptop panels. This appears to related to the PLL divider registers (fail to lock?). @@ -914,6 +954,8 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) RADEON_VCLK_SRC_SEL_PPLLCLK, ~(RADEON_VCLK_SRC_SEL_MASK)); + if (is_tv) + WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); } } diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 9322675..0aaafcd 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c @@ -29,6 +29,15 @@ #include "radeon.h" #include "atom.h" +static void radeon_legacy_encoder_disable(struct drm_encoder *encoder) +{ + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct drm_encoder_helper_funcs *encoder_funcs; + + encoder_funcs = encoder->helper_private; + encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); + radeon_encoder->active_device = 0; +} static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) { @@ -98,6 +107,8 @@ static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) else radeon_combios_output_lock(encoder, true); radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); + + radeon_encoder_set_active_device(encoder); } static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) @@ -195,6 +206,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = { .prepare = radeon_legacy_lvds_prepare, .mode_set = radeon_legacy_lvds_mode_set, .commit = radeon_legacy_lvds_commit, + .disable = radeon_legacy_encoder_disable, }; @@ -260,6 +272,7 @@ static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) else radeon_combios_output_lock(encoder, true); radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); + radeon_encoder_set_active_device(encoder); } static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) @@ -402,6 +415,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_fu .mode_set = radeon_legacy_primary_dac_mode_set, .commit = radeon_legacy_primary_dac_commit, .detect = radeon_legacy_primary_dac_detect, + .disable = radeon_legacy_encoder_disable, }; @@ -454,6 +468,7 @@ static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) else radeon_combios_output_lock(encoder, true); radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); + radeon_encoder_set_active_device(encoder); } static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) @@ -566,6 +581,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs .prepare = radeon_legacy_tmds_int_prepare, .mode_set = radeon_legacy_tmds_int_mode_set, .commit = radeon_legacy_tmds_int_commit, + .disable = radeon_legacy_encoder_disable, }; @@ -620,6 +636,7 @@ static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) else radeon_combios_output_lock(encoder, true); radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); + radeon_encoder_set_active_device(encoder); } static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) @@ -706,6 +723,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs .prepare = radeon_legacy_tmds_ext_prepare, .mode_set = radeon_legacy_tmds_ext_mode_set, .commit = radeon_legacy_tmds_ext_commit, + .disable = radeon_legacy_encoder_disable, }; @@ -727,17 +745,21 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; - /* uint32_t tv_master_cntl = 0; */ - + uint32_t tv_master_cntl = 0; + bool is_tv; DRM_DEBUG("\n"); + is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; + if (rdev->family == CHIP_R200) fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); else { - crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); - /* FIXME TV */ - /* tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); */ + if (is_tv) + tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); + else + crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); } @@ -746,20 +768,23 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) if (rdev->family == CHIP_R200) { fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); } else { - crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; - /* tv_master_cntl |= RADEON_TV_ON; */ + if (is_tv) + tv_master_cntl |= RADEON_TV_ON; + else + crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; + if (rdev->family == CHIP_R420 || - rdev->family == CHIP_R423 || - rdev->family == CHIP_RV410) + rdev->family == CHIP_R423 || + rdev->family == CHIP_RV410) tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | - R420_TV_DAC_GDACPD | - R420_TV_DAC_BDACPD | - RADEON_TV_DAC_BGSLEEP); + R420_TV_DAC_GDACPD | + R420_TV_DAC_BDACPD | + RADEON_TV_DAC_BGSLEEP); else tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | - RADEON_TV_DAC_GDACPD | - RADEON_TV_DAC_BDACPD | - RADEON_TV_DAC_BGSLEEP); + RADEON_TV_DAC_GDACPD | + RADEON_TV_DAC_BDACPD | + RADEON_TV_DAC_BGSLEEP); } break; case DRM_MODE_DPMS_STANDBY: @@ -768,8 +793,11 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) if (rdev->family == CHIP_R200) fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); else { - crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; - /* tv_master_cntl &= ~RADEON_TV_ON; */ + if (is_tv) + tv_master_cntl &= ~RADEON_TV_ON; + else + crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; + if (rdev->family == CHIP_R420 || rdev->family == CHIP_R423 || rdev->family == CHIP_RV410) @@ -789,8 +817,10 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) if (rdev->family == CHIP_R200) { WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); } else { - WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); - /* WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); */ + if (is_tv) + WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); + else + WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); } @@ -809,6 +839,7 @@ static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) else radeon_combios_output_lock(encoder, true); radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); + radeon_encoder_set_active_device(encoder); } static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) @@ -831,11 +862,15 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, struct radeon_device *rdev = dev->dev_private; struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; - uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0; + uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; + bool is_tv = false; DRM_DEBUG("\n"); + is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; + if (rdev->family != CHIP_R200) { tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); if (rdev->family == CHIP_R420 || @@ -858,7 +893,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, } /* FIXME TV */ - if (radeon_encoder->enc_priv) { + if (tv_dac) { struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | @@ -875,44 +910,93 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, if (ASIC_IS_R300(rdev)) { gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); - } else if (rdev->family == CHIP_R200) - fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); + } + + if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) + disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); else disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); - dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; + if (rdev->family == CHIP_R200) + fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); - if (radeon_crtc->crtc_id == 0) { - if (ASIC_IS_R300(rdev)) { - disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; - disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; - } else if (rdev->family == CHIP_R200) { - fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | - RADEON_FP2_DVO_RATE_SEL_SDR); - } else - disp_hw_debug |= RADEON_CRT2_DISP1_SEL; + if (is_tv) { + uint32_t dac_cntl; + + dac_cntl = RREG32(RADEON_DAC_CNTL); + dac_cntl &= ~RADEON_DAC_TVO_EN; + WREG32(RADEON_DAC_CNTL, dac_cntl); + + if (ASIC_IS_R300(rdev)) + gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; + + dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; + if (radeon_crtc->crtc_id == 0) { + if (ASIC_IS_R300(rdev)) { + disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; + disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC | + RADEON_DISP_TV_SOURCE_CRTC); + } + if (rdev->family >= CHIP_R200) { + disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; + } else { + disp_hw_debug |= RADEON_CRT2_DISP1_SEL; + } + } else { + if (ASIC_IS_R300(rdev)) { + disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; + disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; + } + if (rdev->family >= CHIP_R200) { + disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; + } else { + disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; + } + } + WREG32(RADEON_DAC_CNTL2, dac2_cntl); } else { - if (ASIC_IS_R300(rdev)) { - disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; - disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; - } else if (rdev->family == CHIP_R200) { - fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | - RADEON_FP2_DVO_RATE_SEL_SDR); - fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; - } else - disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; - } - WREG32(RADEON_DAC_CNTL2, dac2_cntl); + dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; + + if (radeon_crtc->crtc_id == 0) { + if (ASIC_IS_R300(rdev)) { + disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; + disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; + } else if (rdev->family == CHIP_R200) { + fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | + RADEON_FP2_DVO_RATE_SEL_SDR); + } else + disp_hw_debug |= RADEON_CRT2_DISP1_SEL; + } else { + if (ASIC_IS_R300(rdev)) { + disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; + disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; + } else if (rdev->family == CHIP_R200) { + fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | + RADEON_FP2_DVO_RATE_SEL_SDR); + fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; + } else + disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; + } + WREG32(RADEON_DAC_CNTL2, dac2_cntl); + } if (ASIC_IS_R300(rdev)) { WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); - WREG32(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl); - } else if (rdev->family == CHIP_R200) - WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); + WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); + } + + if (rdev->family >= CHIP_R200) + WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); else WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); + if (rdev->family == CHIP_R200) + WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); + + if (is_tv) + radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode); + if (rdev->is_atom_bios) radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); else @@ -920,6 +1004,141 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, } +static bool r300_legacy_tv_detect(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; + uint32_t disp_output_cntl, gpiopad_a, tmp; + bool found = false; + + /* save regs needed */ + gpiopad_a = RREG32(RADEON_GPIOPAD_A); + dac_cntl2 = RREG32(RADEON_DAC_CNTL2); + crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); + dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); + tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); + disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); + + WREG32_P(RADEON_GPIOPAD_A, 0, ~1); + + WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); + + WREG32(RADEON_CRTC2_GEN_CNTL, + RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); + + tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; + tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; + WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); + + WREG32(RADEON_DAC_EXT_CNTL, + RADEON_DAC2_FORCE_BLANK_OFF_EN | + RADEON_DAC2_FORCE_DATA_EN | + RADEON_DAC_FORCE_DATA_SEL_RGB | + (0xec << RADEON_DAC_FORCE_DATA_SHIFT)); + + WREG32(RADEON_TV_DAC_CNTL, + RADEON_TV_DAC_STD_NTSC | + (8 << RADEON_TV_DAC_BGADJ_SHIFT) | + (6 << RADEON_TV_DAC_DACADJ_SHIFT)); + + RREG32(RADEON_TV_DAC_CNTL); + mdelay(4); + + WREG32(RADEON_TV_DAC_CNTL, + RADEON_TV_DAC_NBLANK | + RADEON_TV_DAC_NHOLD | + RADEON_TV_MONITOR_DETECT_EN | + RADEON_TV_DAC_STD_NTSC | + (8 << RADEON_TV_DAC_BGADJ_SHIFT) | + (6 << RADEON_TV_DAC_DACADJ_SHIFT)); + + RREG32(RADEON_TV_DAC_CNTL); + mdelay(6); + + tmp = RREG32(RADEON_TV_DAC_CNTL); + if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { + found = true; + DRM_DEBUG("S-video TV connection detected\n"); + } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { + found = true; + DRM_DEBUG("Composite TV connection detected\n"); + } + + WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); + WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); + WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); + WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); + WREG32(RADEON_DAC_CNTL2, dac_cntl2); + WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); + return found; +} + +static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + uint32_t tv_dac_cntl, dac_cntl2; + uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; + bool found = false; + + if (ASIC_IS_R300(rdev)) + return r300_legacy_tv_detect(encoder, connector); + + dac_cntl2 = RREG32(RADEON_DAC_CNTL2); + tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); + tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); + config_cntl = RREG32(RADEON_CONFIG_CNTL); + tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); + + tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; + WREG32(RADEON_DAC_CNTL2, tmp); + + tmp = tv_master_cntl | RADEON_TV_ON; + tmp &= ~(RADEON_TV_ASYNC_RST | + RADEON_RESTART_PHASE_FIX | + RADEON_CRT_FIFO_CE_EN | + RADEON_TV_FIFO_CE_EN | + RADEON_RE_SYNC_NOW_SEL_MASK); + tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; + WREG32(RADEON_TV_MASTER_CNTL, tmp); + + tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | + RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | + (8 << RADEON_TV_DAC_BGADJ_SHIFT); + + if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) + tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); + else + tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); + WREG32(RADEON_TV_DAC_CNTL, tmp); + + tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | + RADEON_RED_MX_FORCE_DAC_DATA | + RADEON_GRN_MX_FORCE_DAC_DATA | + RADEON_BLU_MX_FORCE_DAC_DATA | + (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); + WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); + + mdelay(3); + tmp = RREG32(RADEON_TV_DAC_CNTL); + if (tmp & RADEON_TV_DAC_GDACDET) { + found = true; + DRM_DEBUG("S-video TV connection detected\n"); + } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { + found = true; + DRM_DEBUG("Composite TV connection detected\n"); + } + + WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); + WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); + WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); + WREG32(RADEON_DAC_CNTL2, dac_cntl2); + return found; +} + static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) { @@ -928,9 +1147,29 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; enum drm_connector_status found = connector_status_disconnected; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; bool color = true; - /* FIXME tv */ + if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || + connector->connector_type == DRM_MODE_CONNECTOR_Composite || + connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) { + bool tv_detect; + + if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT)) + return connector_status_disconnected; + + tv_detect = radeon_legacy_tv_detect(encoder, connector); + if (tv_detect && tv_dac) + found = connector_status_connected; + return found; + } + + /* don't probe if the encoder is being used for something else not CRT related */ + if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) { + DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device); + return connector_status_disconnected; + } /* save the regs we need */ pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); @@ -1013,8 +1252,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder } WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); - /* return found; */ - return connector_status_disconnected; + return found; } @@ -1025,6 +1263,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = .mode_set = radeon_legacy_tv_dac_mode_set, .commit = radeon_legacy_tv_dac_commit, .detect = radeon_legacy_tv_dac_detect, + .disable = radeon_legacy_encoder_disable, }; diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c new file mode 100644 index 0000000..3a12bb0 --- /dev/null +++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c @@ -0,0 +1,904 @@ +#include "drmP.h" +#include "drm_crtc_helper.h" +#include "radeon.h" + +/* + * Integrated TV out support based on the GATOS code by + * Federico Ulivi + */ + + +/* + * Limits of h/v positions (hPos & vPos) + */ +#define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */ +#define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */ + +/* + * Unit for hPos (in TV clock periods) + */ +#define H_POS_UNIT 10 + +/* + * Indexes in h. code timing table for horizontal line position adjustment + */ +#define H_TABLE_POS1 6 +#define H_TABLE_POS2 8 + +/* + * Limits of hor. size (hSize) + */ +#define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */ + +/* tv standard constants */ +#define NTSC_TV_CLOCK_T 233 +#define NTSC_TV_VFTOTAL 1 +#define NTSC_TV_LINES_PER_FRAME 525 +#define NTSC_TV_ZERO_H_SIZE 479166 +#define NTSC_TV_H_SIZE_UNIT 9478 + +#define PAL_TV_CLOCK_T 188 +#define PAL_TV_VFTOTAL 3 +#define PAL_TV_LINES_PER_FRAME 625 +#define PAL_TV_ZERO_H_SIZE 473200 +#define PAL_TV_H_SIZE_UNIT 9360 + +/* tv pll setting for 27 mhz ref clk */ +#define NTSC_TV_PLL_M_27 22 +#define NTSC_TV_PLL_N_27 175 +#define NTSC_TV_PLL_P_27 5 + +#define PAL_TV_PLL_M_27 113 +#define PAL_TV_PLL_N_27 668 +#define PAL_TV_PLL_P_27 3 + +/* tv pll setting for 14 mhz ref clk */ +#define NTSC_TV_PLL_M_14 33 +#define NTSC_TV_PLL_N_14 693 +#define NTSC_TV_PLL_P_14 7 + +#define VERT_LEAD_IN_LINES 2 +#define FRAC_BITS 0xe +#define FRAC_MASK 0x3fff + +struct radeon_tv_mode_constants { + uint16_t hor_resolution; + uint16_t ver_resolution; + enum radeon_tv_std standard; + uint16_t hor_total; + uint16_t ver_total; + uint16_t hor_start; + uint16_t hor_syncstart; + uint16_t ver_syncstart; + unsigned def_restart; + uint16_t crtcPLL_N; + uint8_t crtcPLL_M; + uint8_t crtcPLL_post_div; + unsigned pix_to_tv; +}; + +static const uint16_t hor_timing_NTSC[] = { + 0x0007, + 0x003f, + 0x0263, + 0x0a24, + 0x2a6b, + 0x0a36, + 0x126d, /* H_TABLE_POS1 */ + 0x1bfe, + 0x1a8f, /* H_TABLE_POS2 */ + 0x1ec7, + 0x3863, + 0x1bfe, + 0x1bfe, + 0x1a2a, + 0x1e95, + 0x0e31, + 0x201b, + 0 +}; + +static const uint16_t vert_timing_NTSC[] = { + 0x2001, + 0x200d, + 0x1006, + 0x0c06, + 0x1006, + 0x1818, + 0x21e3, + 0x1006, + 0x0c06, + 0x1006, + 0x1817, + 0x21d4, + 0x0002, + 0 +}; + +static const uint16_t hor_timing_PAL[] = { + 0x0007, + 0x0058, + 0x027c, + 0x0a31, + 0x2a77, + 0x0a95, + 0x124f, /* H_TABLE_POS1 */ + 0x1bfe, + 0x1b22, /* H_TABLE_POS2 */ + 0x1ef9, + 0x387c, + 0x1bfe, + 0x1bfe, + 0x1b31, + 0x1eb5, + 0x0e43, + 0x201b, + 0 +}; + +static const uint16_t vert_timing_PAL[] = { + 0x2001, + 0x200c, + 0x1005, + 0x0c05, + 0x1005, + 0x1401, + 0x1821, + 0x2240, + 0x1005, + 0x0c05, + 0x1005, + 0x1401, + 0x1822, + 0x2230, + 0x0002, + 0 +}; + +/********************************************************************** + * + * availableModes + * + * Table of all allowed modes for tv output + * + **********************************************************************/ +static const struct radeon_tv_mode_constants available_tv_modes[] = { + { /* NTSC timing for 27 Mhz ref clk */ + 800, /* horResolution */ + 600, /* verResolution */ + TV_STD_NTSC, /* standard */ + 990, /* horTotal */ + 740, /* verTotal */ + 813, /* horStart */ + 824, /* horSyncStart */ + 632, /* verSyncStart */ + 625592, /* defRestart */ + 592, /* crtcPLL_N */ + 91, /* crtcPLL_M */ + 4, /* crtcPLL_postDiv */ + 1022, /* pixToTV */ + }, + { /* PAL timing for 27 Mhz ref clk */ + 800, /* horResolution */ + 600, /* verResolution */ + TV_STD_PAL, /* standard */ + 1144, /* horTotal */ + 706, /* verTotal */ + 812, /* horStart */ + 824, /* horSyncStart */ + 669, /* verSyncStart */ + 696700, /* defRestart */ + 1382, /* crtcPLL_N */ + 231, /* crtcPLL_M */ + 4, /* crtcPLL_postDiv */ + 759, /* pixToTV */ + }, + { /* NTSC timing for 14 Mhz ref clk */ + 800, /* horResolution */ + 600, /* verResolution */ + TV_STD_NTSC, /* standard */ + 1018, /* horTotal */ + 727, /* verTotal */ + 813, /* horStart */ + 840, /* horSyncStart */ + 633, /* verSyncStart */ + 630627, /* defRestart */ + 347, /* crtcPLL_N */ + 14, /* crtcPLL_M */ + 8, /* crtcPLL_postDiv */ + 1022, /* pixToTV */ + }, +}; + +#define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes) + +static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder, + uint16_t *pll_ref_freq) +{ + struct drm_device *dev = radeon_encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_crtc *radeon_crtc; + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + const struct radeon_tv_mode_constants *const_ptr; + struct radeon_pll *pll; + + radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); + if (radeon_crtc->crtc_id == 1) + pll = &rdev->clock.p2pll; + else + pll = &rdev->clock.p1pll; + + if (pll_ref_freq) + *pll_ref_freq = pll->reference_freq; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M) { + if (pll->reference_freq == 2700) + const_ptr = &available_tv_modes[0]; + else + const_ptr = &available_tv_modes[2]; + } else { + if (pll->reference_freq == 2700) + const_ptr = &available_tv_modes[1]; + else + const_ptr = &available_tv_modes[1]; /* FIX ME */ + } + return const_ptr; +} + +static long YCOEF_value[5] = { 2, 2, 0, 4, 0 }; +static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 }; +static long SLOPE_value[5] = { 1, 2, 2, 4, 8 }; +static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 }; + +static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests, + unsigned n_wait_loops, unsigned cnt_threshold) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + uint32_t save_pll_test; + unsigned int i, j; + + WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); + save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); + WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B); + + WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); + for (i = 0; i < n_tests; i++) { + WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); + for (j = 0; j < n_wait_loops; j++) + if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) + break; + } + WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test); + WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); +} + + +static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder, + uint16_t addr, uint32_t value) +{ + struct drm_device *dev = radeon_encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; + uint32_t tmp; + int i = 0; + + WREG32(RADEON_TV_HOST_WRITE_DATA, value); + + WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); + WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); + + do { + tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); + if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0) + break; + i++; + } while (i < 10000); + WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); +} + +#if 0 /* included for completeness */ +static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr) +{ + struct drm_device *dev = radeon_encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; + uint32_t tmp; + int i = 0; + + WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); + WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); + + do { + tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); + if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0) + break; + i++; + } while (i < 10000); + WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); + return RREG32(RADEON_TV_HOST_READ_DATA); +} +#endif + +static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr) +{ + uint16_t h_table; + + switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { + case 0: + h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL; + break; + case 1: + h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2; + break; + case 2: + h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2; + break; + default: + h_table = 0; + break; + } + return h_table; +} + +static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr) +{ + uint16_t v_table; + + switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { + case 0: + v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1; + break; + case 1: + v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1; + break; + case 2: + v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1; + break; + default: + v_table = 0; + break; + } + return v_table; +} + +static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder) +{ + struct drm_device *dev = radeon_encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + uint16_t h_table, v_table; + uint32_t tmp; + int i; + + WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); + h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr); + v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr); + + for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) { + tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]); + radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp); + if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0) + break; + } + for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) { + tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]); + radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp); + if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0) + break; + } +} + +static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder) +{ + struct drm_device *dev = radeon_encoder->base.dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart); + WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart); + WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart); +} + +static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + struct radeon_crtc *radeon_crtc; + int restart; + unsigned int h_total, v_total, f_total; + int v_offset, h_offset; + u16 p1, p2, h_inc; + bool h_changed; + const struct radeon_tv_mode_constants *const_ptr; + struct radeon_pll *pll; + + radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); + if (radeon_crtc->crtc_id == 1) + pll = &rdev->clock.p2pll; + else + pll = &rdev->clock.p1pll; + + const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); + if (!const_ptr) + return false; + + h_total = const_ptr->hor_total; + v_total = const_ptr->ver_total; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M || + tv_dac->tv_std == TV_STD_PAL_60) + f_total = NTSC_TV_VFTOTAL + 1; + else + f_total = PAL_TV_VFTOTAL + 1; + + /* adjust positions 1&2 in hor. cod timing table */ + h_offset = tv_dac->h_pos * H_POS_UNIT; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M) { + h_offset -= 50; + p1 = hor_timing_NTSC[H_TABLE_POS1]; + p2 = hor_timing_NTSC[H_TABLE_POS2]; + } else { + p1 = hor_timing_PAL[H_TABLE_POS1]; + p2 = hor_timing_PAL[H_TABLE_POS2]; + } + + p1 = (u16)((int)p1 + h_offset); + p2 = (u16)((int)p2 - h_offset); + + h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] || + p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]); + + tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1; + tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2; + + /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */ + h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000; + + /* adjust restart */ + restart = const_ptr->def_restart; + + /* + * convert v_pos TV lines to n. of CRTC pixels + */ + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M || + tv_dac->tv_std == TV_STD_PAL_60) + v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); + else + v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); + + restart -= v_offset + h_offset; + + DRM_DEBUG("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n", + const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); + + tv_dac->tv.hrestart = restart % h_total; + restart /= h_total; + tv_dac->tv.vrestart = restart % v_total; + restart /= v_total; + tv_dac->tv.frestart = restart % f_total; + + DRM_DEBUG("compute_restart: F/H/V=%u,%u,%u\n", + (unsigned)tv_dac->tv.frestart, + (unsigned)tv_dac->tv.vrestart, + (unsigned)tv_dac->tv.hrestart); + + /* compute h_inc from hsize */ + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M) + h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) / + (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); + else + h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) / + (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); + + tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | + ((u32)h_inc << RADEON_H_INC_SHIFT); + + DRM_DEBUG("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc); + + return h_changed; +} + +void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; + const struct radeon_tv_mode_constants *const_ptr; + struct radeon_crtc *radeon_crtc; + int i; + uint16_t pll_ref_freq; + uint32_t vert_space, flicker_removal, tmp; + uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl; + uint32_t tv_modulator_cntl1, tv_modulator_cntl2; + uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2; + uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal; + uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl; + uint32_t m, n, p; + const uint16_t *hor_timing; + const uint16_t *vert_timing; + + const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq); + if (!const_ptr) + return; + + radeon_crtc = to_radeon_crtc(encoder->crtc); + + tv_master_cntl = (RADEON_VIN_ASYNC_RST | + RADEON_CRT_FIFO_CE_EN | + RADEON_TV_FIFO_CE_EN | + RADEON_TV_ON); + + if (!ASIC_IS_R300(rdev)) + tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J) + tv_master_cntl |= RADEON_RESTART_PHASE_FIX; + + tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT | + RADEON_SYNC_TIP_LEVEL | + RADEON_YFLT_EN | + RADEON_UVFLT_EN | + (6 << RADEON_CY_FILT_BLEND_SHIFT)); + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J) { + tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) | + (0x3b << RADEON_BLANK_LEVEL_SHIFT); + tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) | + ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); + } else if (tv_dac->tv_std == TV_STD_SCART_PAL) { + tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN; + tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) | + ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); + } else { + tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN | + (0x3b << RADEON_SET_UP_LEVEL_SHIFT) | + (0x3b << RADEON_BLANK_LEVEL_SHIFT); + tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) | + ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); + } + + + tv_rgb_cntl = (RADEON_RGB_DITHER_EN + | RADEON_TVOUT_SCALE_EN + | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT) + | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT) + | RADEON_RGB_ATTEN_SEL(0x3) + | RADEON_RGB_ATTEN_VAL(0xc)); + + if (radeon_crtc->crtc_id == 1) + tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2; + else { + if (radeon_crtc->rmx_type != RMX_OFF) + tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX; + else + tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1; + } + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M || + tv_dac->tv_std == TV_STD_PAL_60) + vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME; + else + vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME; + + tmp = RREG32(RADEON_TV_VSCALER_CNTL1); + tmp &= 0xe3ff0000; + tmp |= (vert_space * (1 << FRAC_BITS) / 10000); + tv_vscaler_cntl1 = tmp; + + if (pll_ref_freq == 2700) + tv_vscaler_cntl1 |= RADEON_RESTART_FIELD; + + if (const_ptr->hor_resolution == 1024) + tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT); + else + tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT); + + /* scale up for int divide */ + tmp = const_ptr->ver_total * 2 * 1000; + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M || + tv_dac->tv_std == TV_STD_PAL_60) { + tmp /= NTSC_TV_LINES_PER_FRAME; + } else { + tmp /= PAL_TV_LINES_PER_FRAME; + } + flicker_removal = (tmp + 500) / 1000; + + if (flicker_removal < 3) + flicker_removal = 3; + for (i = 0; i < 6; ++i) { + if (flicker_removal == SLOPE_limit[i]) + break; + } + + tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) + + 5001) / 10000 / 8 | ((SLOPE_value[i] * + (1 << (FRAC_BITS - 1)) / 8) << 16); + tv_y_fall_cntl = + (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) | + RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) / + 1024; + tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG| + (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024; + + tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0; + tv_vscaler_cntl2 |= (0x10 << 24) | + RADEON_DITHER_MODE | + RADEON_Y_OUTPUT_DITHER_EN | + RADEON_UV_OUTPUT_DITHER_EN | + RADEON_UV_TO_BUF_DITHER_EN; + + tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK; + tmp = ((16384 * 256 * 10) / tmp + 5) / 10; + tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000; + tv_dac->tv.timing_cntl = tmp; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M || + tv_dac->tv_std == TV_STD_PAL_60) + tv_dac_cntl = tv_dac->ntsc_tvdac_adj; + else + tv_dac_cntl = tv_dac->pal_tvdac_adj; + + tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J) + tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; + else + tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J) { + if (pll_ref_freq == 2700) { + m = NTSC_TV_PLL_M_27; + n = NTSC_TV_PLL_N_27; + p = NTSC_TV_PLL_P_27; + } else { + m = NTSC_TV_PLL_M_14; + n = NTSC_TV_PLL_N_14; + p = NTSC_TV_PLL_P_14; + } + } else { + if (pll_ref_freq == 2700) { + m = PAL_TV_PLL_M_27; + n = PAL_TV_PLL_N_27; + p = PAL_TV_PLL_P_27; + } else { + m = PAL_TV_PLL_M_27; + n = PAL_TV_PLL_N_27; + p = PAL_TV_PLL_P_27; + } + } + + tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) | + (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | + ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | + (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | + ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); + + tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) | + ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) | + ((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) | + RADEON_TVCLK_SRC_SEL_TVPLL | + RADEON_TVPLL_TEST_DIS); + + tv_dac->tv.tv_uv_adr = 0xc8; + + if (tv_dac->tv_std == TV_STD_NTSC || + tv_dac->tv_std == TV_STD_NTSC_J || + tv_dac->tv_std == TV_STD_PAL_M || + tv_dac->tv_std == TV_STD_PAL_60) { + tv_ftotal = NTSC_TV_VFTOTAL; + hor_timing = hor_timing_NTSC; + vert_timing = vert_timing_NTSC; + } else { + hor_timing = hor_timing_PAL; + vert_timing = vert_timing_PAL; + tv_ftotal = PAL_TV_VFTOTAL; + } + + for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) { + if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0) + break; + } + + for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) { + if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) + break; + } + + radeon_legacy_tv_init_restarts(encoder); + + /* play with DAC_CNTL */ + /* play with GPIOPAD_A */ + /* DISP_OUTPUT_CNTL */ + /* use reference freq */ + + /* program the TV registers */ + WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | + RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST)); + + tmp = RREG32(RADEON_TV_DAC_CNTL); + tmp &= ~RADEON_TV_DAC_NBLANK; + tmp |= RADEON_TV_DAC_BGSLEEP | + RADEON_TV_DAC_RDACPD | + RADEON_TV_DAC_GDACPD | + RADEON_TV_DAC_BDACPD; + WREG32(RADEON_TV_DAC_CNTL, tmp); + + /* TV PLL */ + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); + WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl); + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); + + radeon_wait_pll_lock(encoder, 200, 800, 135); + + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); + + radeon_wait_pll_lock(encoder, 300, 160, 27); + radeon_wait_pll_lock(encoder, 200, 800, 135); + + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf); + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); + + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); + WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); + + /* TV HV */ + WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl); + WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1); + WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1); + WREG32(RADEON_TV_HSTART, const_ptr->hor_start); + + WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1); + WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1); + WREG32(RADEON_TV_FTOTAL, tv_ftotal); + WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1); + WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2); + + WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl); + WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl); + WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl); + + WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | + RADEON_CRT_ASYNC_RST)); + + /* TV restarts */ + radeon_legacy_write_tv_restarts(radeon_encoder); + + /* tv timings */ + radeon_restore_tv_timing_tables(radeon_encoder); + + WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST)); + + /* tv std */ + WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE)); + WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl); + WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1); + WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2); + WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN | + RADEON_C_GRN_EN | + RADEON_CMP_BLU_EN | + RADEON_DAC_DITHER_EN)); + + WREG32(RADEON_TV_CRC_CNTL, 0); + + WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); + + WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) | + (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT))); + WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) | + (0x100 << RADEON_Y_GAIN_SHIFT))); + + WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); + +} + +void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, + uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, + uint32_t *v_total_disp, uint32_t *v_sync_strt_wid) +{ + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + const struct radeon_tv_mode_constants *const_ptr; + uint32_t tmp; + + const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); + if (!const_ptr) + return; + + *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | + (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); + + tmp = *h_sync_strt_wid; + tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR); + tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) | + (const_ptr->hor_syncstart & 7); + *h_sync_strt_wid = tmp; + + *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) | + ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT); + + tmp = *v_sync_strt_wid; + tmp &= ~RADEON_CRTC_V_SYNC_STRT; + tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT); + *v_sync_strt_wid = tmp; +} + +static inline int get_post_div(int value) +{ + int post_div; + switch (value) { + case 1: post_div = 0; break; + case 2: post_div = 1; break; + case 3: post_div = 4; break; + case 4: post_div = 2; break; + case 6: post_div = 6; break; + case 8: post_div = 3; break; + case 12: post_div = 7; break; + case 16: + default: post_div = 5; break; + } + return post_div; +} + +void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, + uint32_t *htotal_cntl, uint32_t *ppll_ref_div, + uint32_t *ppll_div_3, uint32_t *pixclks_cntl) +{ + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + const struct radeon_tv_mode_constants *const_ptr; + + const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); + if (!const_ptr) + return; + + *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN; + + *ppll_ref_div = const_ptr->crtcPLL_M; + + *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); + *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL); + *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK; +} + +void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, + uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, + uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) +{ + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + const struct radeon_tv_mode_constants *const_ptr; + + const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); + if (!const_ptr) + return; + + *htotal2_cntl = (const_ptr->hor_total & 0x7); + + *p2pll_ref_div = const_ptr->crtcPLL_M; + + *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); + *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK; + *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL; +} + diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 20e9509..523d6cb 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -188,6 +188,21 @@ struct radeon_native_mode { uint32_t flags; }; +#define MAX_H_CODE_TIMING_LEN 32 +#define MAX_V_CODE_TIMING_LEN 32 + +/* need to store these as reading + back code tables is excessive */ +struct radeon_tv_regs { + uint32_t tv_uv_adr; + uint32_t timing_cntl; + uint32_t hrestart; + uint32_t vrestart; + uint32_t frestart; + uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; + uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; +}; + struct radeon_crtc { struct drm_crtc base; int crtc_id; @@ -202,7 +217,6 @@ struct radeon_crtc { uint32_t legacy_display_base_addr; uint32_t legacy_cursor_offset; enum radeon_rmx_type rmx_type; - uint32_t devices; fixed20_12 vsc; fixed20_12 hsc; struct radeon_native_mode native_mode; @@ -234,7 +248,13 @@ struct radeon_encoder_tv_dac { uint32_t ntsc_tvdac_adj; uint32_t pal_tvdac_adj; + int h_pos; + int v_pos; + int h_size; + int supported_tv_stds; + bool tv_on; enum radeon_tv_std tv_std; + struct radeon_tv_regs tv; }; struct radeon_encoder_int_tmds { @@ -253,10 +273,15 @@ struct radeon_encoder_atom_dig { struct radeon_native_mode native_mode; }; +struct radeon_encoder_atom_dac { + enum radeon_tv_std tv_std; +}; + struct radeon_encoder { struct drm_encoder base; uint32_t encoder_id; uint32_t devices; + uint32_t active_device; uint32_t flags; uint32_t pixel_clock; enum radeon_rmx_type rmx_type; @@ -274,7 +299,10 @@ struct radeon_connector { uint32_t connector_id; uint32_t devices; struct radeon_i2c_chan *ddc_bus; - int use_digital; + bool use_digital; + /* we need to mind the EDID between detect + and get modes due to analog/digital/tvencoder */ + struct edid *edid; void *con_priv; }; @@ -308,6 +336,7 @@ struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, i struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); extern int atombios_get_encoder_mode(struct drm_encoder *encoder); +extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); extern void radeon_crtc_load_lut(struct drm_crtc *crtc); extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, @@ -394,6 +423,19 @@ extern int radeon_static_clocks_init(struct drm_device *dev); bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); -void atom_rv515_force_tv_scaler(struct radeon_device *rdev); - +void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); + +/* legacy tv */ +void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, + uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, + uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); +void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, + uint32_t *htotal_cntl, uint32_t *ppll_ref_div, + uint32_t *ppll_div_3, uint32_t *pixclks_cntl); +void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, + uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, + uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); +void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); #endif diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 404b39b..28be2f1 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h @@ -3462,7 +3462,9 @@ # define RADEON_RGB_CONVERT_BY_PASS (1 << 10) # define RADEON_UVRAM_READ_MARGIN_SHIFT 16 # define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 -# define RADEON_TVOUT_SCALE_EN (1 << 26) +# define RADEON_RGB_ATTEN_SEL(x) ((x) << 24) +# define RADEON_TVOUT_SCALE_EN (1 << 26) +# define RADEON_RGB_ATTEN_VAL(x) ((x) << 28) #define RADEON_TV_SYNC_CNTL 0x0808 # define RADEON_SYNC_OE (1 << 0) # define RADEON_SYNC_OUT (1 << 1) diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 60a194f..97965c4 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c @@ -475,232 +475,234 @@ int rv515_init(struct radeon_device *rdev) return 0; } -void atom_rv515_force_tv_scaler(struct radeon_device *rdev) +void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) { - - WREG32(0x659C, 0x0); - WREG32(0x6594, 0x705); - WREG32(0x65A4, 0x10001); - WREG32(0x65D8, 0x0); - WREG32(0x65B0, 0x0); - WREG32(0x65C0, 0x0); - WREG32(0x65D4, 0x0); - WREG32(0x6578, 0x0); - WREG32(0x657C, 0x841880A8); - WREG32(0x6578, 0x1); - WREG32(0x657C, 0x84208680); - WREG32(0x6578, 0x2); - WREG32(0x657C, 0xBFF880B0); - WREG32(0x6578, 0x100); - WREG32(0x657C, 0x83D88088); - WREG32(0x6578, 0x101); - WREG32(0x657C, 0x84608680); - WREG32(0x6578, 0x102); - WREG32(0x657C, 0xBFF080D0); - WREG32(0x6578, 0x200); - WREG32(0x657C, 0x83988068); - WREG32(0x6578, 0x201); - WREG32(0x657C, 0x84A08680); - WREG32(0x6578, 0x202); - WREG32(0x657C, 0xBFF080F8); - WREG32(0x6578, 0x300); - WREG32(0x657C, 0x83588058); - WREG32(0x6578, 0x301); - WREG32(0x657C, 0x84E08660); - WREG32(0x6578, 0x302); - WREG32(0x657C, 0xBFF88120); - WREG32(0x6578, 0x400); - WREG32(0x657C, 0x83188040); - WREG32(0x6578, 0x401); - WREG32(0x657C, 0x85008660); - WREG32(0x6578, 0x402); - WREG32(0x657C, 0xBFF88150); - WREG32(0x6578, 0x500); - WREG32(0x657C, 0x82D88030); - WREG32(0x6578, 0x501); - WREG32(0x657C, 0x85408640); - WREG32(0x6578, 0x502); - WREG32(0x657C, 0xBFF88180); - WREG32(0x6578, 0x600); - WREG32(0x657C, 0x82A08018); - WREG32(0x6578, 0x601); - WREG32(0x657C, 0x85808620); - WREG32(0x6578, 0x602); - WREG32(0x657C, 0xBFF081B8); - WREG32(0x6578, 0x700); - WREG32(0x657C, 0x82608010); - WREG32(0x6578, 0x701); - WREG32(0x657C, 0x85A08600); - WREG32(0x6578, 0x702); - WREG32(0x657C, 0x800081F0); - WREG32(0x6578, 0x800); - WREG32(0x657C, 0x8228BFF8); - WREG32(0x6578, 0x801); - WREG32(0x657C, 0x85E085E0); - WREG32(0x6578, 0x802); - WREG32(0x657C, 0xBFF88228); - WREG32(0x6578, 0x10000); - WREG32(0x657C, 0x82A8BF00); - WREG32(0x6578, 0x10001); - WREG32(0x657C, 0x82A08CC0); - WREG32(0x6578, 0x10002); - WREG32(0x657C, 0x8008BEF8); - WREG32(0x6578, 0x10100); - WREG32(0x657C, 0x81F0BF28); - WREG32(0x6578, 0x10101); - WREG32(0x657C, 0x83608CA0); - WREG32(0x6578, 0x10102); - WREG32(0x657C, 0x8018BED0); - WREG32(0x6578, 0x10200); - WREG32(0x657C, 0x8148BF38); - WREG32(0x6578, 0x10201); - WREG32(0x657C, 0x84408C80); - WREG32(0x6578, 0x10202); - WREG32(0x657C, 0x8008BEB8); - WREG32(0x6578, 0x10300); - WREG32(0x657C, 0x80B0BF78); - WREG32(0x6578, 0x10301); - WREG32(0x657C, 0x85008C20); - WREG32(0x6578, 0x10302); - WREG32(0x657C, 0x8020BEA0); - WREG32(0x6578, 0x10400); - WREG32(0x657C, 0x8028BF90); - WREG32(0x6578, 0x10401); - WREG32(0x657C, 0x85E08BC0); - WREG32(0x6578, 0x10402); - WREG32(0x657C, 0x8018BE90); - WREG32(0x6578, 0x10500); - WREG32(0x657C, 0xBFB8BFB0); - WREG32(0x6578, 0x10501); - WREG32(0x657C, 0x86C08B40); - WREG32(0x6578, 0x10502); - WREG32(0x657C, 0x8010BE90); - WREG32(0x6578, 0x10600); - WREG32(0x657C, 0xBF58BFC8); - WREG32(0x6578, 0x10601); - WREG32(0x657C, 0x87A08AA0); - WREG32(0x6578, 0x10602); - WREG32(0x657C, 0x8010BE98); - WREG32(0x6578, 0x10700); - WREG32(0x657C, 0xBF10BFF0); - WREG32(0x6578, 0x10701); - WREG32(0x657C, 0x886089E0); - WREG32(0x6578, 0x10702); - WREG32(0x657C, 0x8018BEB0); - WREG32(0x6578, 0x10800); - WREG32(0x657C, 0xBED8BFE8); - WREG32(0x6578, 0x10801); - WREG32(0x657C, 0x89408940); - WREG32(0x6578, 0x10802); - WREG32(0x657C, 0xBFE8BED8); - WREG32(0x6578, 0x20000); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x20001); - WREG32(0x657C, 0x90008000); - WREG32(0x6578, 0x20002); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x20003); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x20100); - WREG32(0x657C, 0x80108000); - WREG32(0x6578, 0x20101); - WREG32(0x657C, 0x8FE0BF70); - WREG32(0x6578, 0x20102); - WREG32(0x657C, 0xBFE880C0); - WREG32(0x6578, 0x20103); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x20200); - WREG32(0x657C, 0x8018BFF8); - WREG32(0x6578, 0x20201); - WREG32(0x657C, 0x8F80BF08); - WREG32(0x6578, 0x20202); - WREG32(0x657C, 0xBFD081A0); - WREG32(0x6578, 0x20203); - WREG32(0x657C, 0xBFF88000); - WREG32(0x6578, 0x20300); - WREG32(0x657C, 0x80188000); - WREG32(0x6578, 0x20301); - WREG32(0x657C, 0x8EE0BEC0); - WREG32(0x6578, 0x20302); - WREG32(0x657C, 0xBFB082A0); - WREG32(0x6578, 0x20303); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x20400); - WREG32(0x657C, 0x80188000); - WREG32(0x6578, 0x20401); - WREG32(0x657C, 0x8E00BEA0); - WREG32(0x6578, 0x20402); - WREG32(0x657C, 0xBF8883C0); - WREG32(0x6578, 0x20403); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x20500); - WREG32(0x657C, 0x80188000); - WREG32(0x6578, 0x20501); - WREG32(0x657C, 0x8D00BE90); - WREG32(0x6578, 0x20502); - WREG32(0x657C, 0xBF588500); - WREG32(0x6578, 0x20503); - WREG32(0x657C, 0x80008008); - WREG32(0x6578, 0x20600); - WREG32(0x657C, 0x80188000); - WREG32(0x6578, 0x20601); - WREG32(0x657C, 0x8BC0BE98); - WREG32(0x6578, 0x20602); - WREG32(0x657C, 0xBF308660); - WREG32(0x6578, 0x20603); - WREG32(0x657C, 0x80008008); - WREG32(0x6578, 0x20700); - WREG32(0x657C, 0x80108000); - WREG32(0x6578, 0x20701); - WREG32(0x657C, 0x8A80BEB0); - WREG32(0x6578, 0x20702); - WREG32(0x657C, 0xBF0087C0); - WREG32(0x6578, 0x20703); - WREG32(0x657C, 0x80008008); - WREG32(0x6578, 0x20800); - WREG32(0x657C, 0x80108000); - WREG32(0x6578, 0x20801); - WREG32(0x657C, 0x8920BED0); - WREG32(0x6578, 0x20802); - WREG32(0x657C, 0xBED08920); - WREG32(0x6578, 0x20803); - WREG32(0x657C, 0x80008010); - WREG32(0x6578, 0x30000); - WREG32(0x657C, 0x90008000); - WREG32(0x6578, 0x30001); - WREG32(0x657C, 0x80008000); - WREG32(0x6578, 0x30100); - WREG32(0x657C, 0x8FE0BF90); - WREG32(0x6578, 0x30101); - WREG32(0x657C, 0xBFF880A0); - WREG32(0x6578, 0x30200); - WREG32(0x657C, 0x8F60BF40); - WREG32(0x6578, 0x30201); - WREG32(0x657C, 0xBFE88180); - WREG32(0x6578, 0x30300); - WREG32(0x657C, 0x8EC0BF00); - WREG32(0x6578, 0x30301); - WREG32(0x657C, 0xBFC88280); - WREG32(0x6578, 0x30400); - WREG32(0x657C, 0x8DE0BEE0); - WREG32(0x6578, 0x30401); - WREG32(0x657C, 0xBFA083A0); - WREG32(0x6578, 0x30500); - WREG32(0x657C, 0x8CE0BED0); - WREG32(0x6578, 0x30501); - WREG32(0x657C, 0xBF7884E0); - WREG32(0x6578, 0x30600); - WREG32(0x657C, 0x8BA0BED8); - WREG32(0x6578, 0x30601); - WREG32(0x657C, 0xBF508640); - WREG32(0x6578, 0x30700); - WREG32(0x657C, 0x8A60BEE8); - WREG32(0x6578, 0x30701); - WREG32(0x657C, 0xBF2087A0); - WREG32(0x6578, 0x30800); - WREG32(0x657C, 0x8900BF00); - WREG32(0x6578, 0x30801); - WREG32(0x657C, 0xBF008900); + int index_reg = 0x6578 + crtc->crtc_offset; + int data_reg = 0x657c + crtc->crtc_offset; + + WREG32(0x659C + crtc->crtc_offset, 0x0); + WREG32(0x6594 + crtc->crtc_offset, 0x705); + WREG32(0x65A4 + crtc->crtc_offset, 0x10001); + WREG32(0x65D8 + crtc->crtc_offset, 0x0); + WREG32(0x65B0 + crtc->crtc_offset, 0x0); + WREG32(0x65C0 + crtc->crtc_offset, 0x0); + WREG32(0x65D4 + crtc->crtc_offset, 0x0); + WREG32(index_reg, 0x0); + WREG32(data_reg, 0x841880A8); + WREG32(index_reg, 0x1); + WREG32(data_reg, 0x84208680); + WREG32(index_reg, 0x2); + WREG32(data_reg, 0xBFF880B0); + WREG32(index_reg, 0x100); + WREG32(data_reg, 0x83D88088); + WREG32(index_reg, 0x101); + WREG32(data_reg, 0x84608680); + WREG32(index_reg, 0x102); + WREG32(data_reg, 0xBFF080D0); + WREG32(index_reg, 0x200); + WREG32(data_reg, 0x83988068); + WREG32(index_reg, 0x201); + WREG32(data_reg, 0x84A08680); + WREG32(index_reg, 0x202); + WREG32(data_reg, 0xBFF080F8); + WREG32(index_reg, 0x300); + WREG32(data_reg, 0x83588058); + WREG32(index_reg, 0x301); + WREG32(data_reg, 0x84E08660); + WREG32(index_reg, 0x302); + WREG32(data_reg, 0xBFF88120); + WREG32(index_reg, 0x400); + WREG32(data_reg, 0x83188040); + WREG32(index_reg, 0x401); + WREG32(data_reg, 0x85008660); + WREG32(index_reg, 0x402); + WREG32(data_reg, 0xBFF88150); + WREG32(index_reg, 0x500); + WREG32(data_reg, 0x82D88030); + WREG32(index_reg, 0x501); + WREG32(data_reg, 0x85408640); + WREG32(index_reg, 0x502); + WREG32(data_reg, 0xBFF88180); + WREG32(index_reg, 0x600); + WREG32(data_reg, 0x82A08018); + WREG32(index_reg, 0x601); + WREG32(data_reg, 0x85808620); + WREG32(index_reg, 0x602); + WREG32(data_reg, 0xBFF081B8); + WREG32(index_reg, 0x700); + WREG32(data_reg, 0x82608010); + WREG32(index_reg, 0x701); + WREG32(data_reg, 0x85A08600); + WREG32(index_reg, 0x702); + WREG32(data_reg, 0x800081F0); + WREG32(index_reg, 0x800); + WREG32(data_reg, 0x8228BFF8); + WREG32(index_reg, 0x801); + WREG32(data_reg, 0x85E085E0); + WREG32(index_reg, 0x802); + WREG32(data_reg, 0xBFF88228); + WREG32(index_reg, 0x10000); + WREG32(data_reg, 0x82A8BF00); + WREG32(index_reg, 0x10001); + WREG32(data_reg, 0x82A08CC0); + WREG32(index_reg, 0x10002); + WREG32(data_reg, 0x8008BEF8); + WREG32(index_reg, 0x10100); + WREG32(data_reg, 0x81F0BF28); + WREG32(index_reg, 0x10101); + WREG32(data_reg, 0x83608CA0); + WREG32(index_reg, 0x10102); + WREG32(data_reg, 0x8018BED0); + WREG32(index_reg, 0x10200); + WREG32(data_reg, 0x8148BF38); + WREG32(index_reg, 0x10201); + WREG32(data_reg, 0x84408C80); + WREG32(index_reg, 0x10202); + WREG32(data_reg, 0x8008BEB8); + WREG32(index_reg, 0x10300); + WREG32(data_reg, 0x80B0BF78); + WREG32(index_reg, 0x10301); + WREG32(data_reg, 0x85008C20); + WREG32(index_reg, 0x10302); + WREG32(data_reg, 0x8020BEA0); + WREG32(index_reg, 0x10400); + WREG32(data_reg, 0x8028BF90); + WREG32(index_reg, 0x10401); + WREG32(data_reg, 0x85E08BC0); + WREG32(index_reg, 0x10402); + WREG32(data_reg, 0x8018BE90); + WREG32(index_reg, 0x10500); + WREG32(data_reg, 0xBFB8BFB0); + WREG32(index_reg, 0x10501); + WREG32(data_reg, 0x86C08B40); + WREG32(index_reg, 0x10502); + WREG32(data_reg, 0x8010BE90); + WREG32(index_reg, 0x10600); + WREG32(data_reg, 0xBF58BFC8); + WREG32(index_reg, 0x10601); + WREG32(data_reg, 0x87A08AA0); + WREG32(index_reg, 0x10602); + WREG32(data_reg, 0x8010BE98); + WREG32(index_reg, 0x10700); + WREG32(data_reg, 0xBF10BFF0); + WREG32(index_reg, 0x10701); + WREG32(data_reg, 0x886089E0); + WREG32(index_reg, 0x10702); + WREG32(data_reg, 0x8018BEB0); + WREG32(index_reg, 0x10800); + WREG32(data_reg, 0xBED8BFE8); + WREG32(index_reg, 0x10801); + WREG32(data_reg, 0x89408940); + WREG32(index_reg, 0x10802); + WREG32(data_reg, 0xBFE8BED8); + WREG32(index_reg, 0x20000); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x20001); + WREG32(data_reg, 0x90008000); + WREG32(index_reg, 0x20002); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x20003); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x20100); + WREG32(data_reg, 0x80108000); + WREG32(index_reg, 0x20101); + WREG32(data_reg, 0x8FE0BF70); + WREG32(index_reg, 0x20102); + WREG32(data_reg, 0xBFE880C0); + WREG32(index_reg, 0x20103); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x20200); + WREG32(data_reg, 0x8018BFF8); + WREG32(index_reg, 0x20201); + WREG32(data_reg, 0x8F80BF08); + WREG32(index_reg, 0x20202); + WREG32(data_reg, 0xBFD081A0); + WREG32(index_reg, 0x20203); + WREG32(data_reg, 0xBFF88000); + WREG32(index_reg, 0x20300); + WREG32(data_reg, 0x80188000); + WREG32(index_reg, 0x20301); + WREG32(data_reg, 0x8EE0BEC0); + WREG32(index_reg, 0x20302); + WREG32(data_reg, 0xBFB082A0); + WREG32(index_reg, 0x20303); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x20400); + WREG32(data_reg, 0x80188000); + WREG32(index_reg, 0x20401); + WREG32(data_reg, 0x8E00BEA0); + WREG32(index_reg, 0x20402); + WREG32(data_reg, 0xBF8883C0); + WREG32(index_reg, 0x20403); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x20500); + WREG32(data_reg, 0x80188000); + WREG32(index_reg, 0x20501); + WREG32(data_reg, 0x8D00BE90); + WREG32(index_reg, 0x20502); + WREG32(data_reg, 0xBF588500); + WREG32(index_reg, 0x20503); + WREG32(data_reg, 0x80008008); + WREG32(index_reg, 0x20600); + WREG32(data_reg, 0x80188000); + WREG32(index_reg, 0x20601); + WREG32(data_reg, 0x8BC0BE98); + WREG32(index_reg, 0x20602); + WREG32(data_reg, 0xBF308660); + WREG32(index_reg, 0x20603); + WREG32(data_reg, 0x80008008); + WREG32(index_reg, 0x20700); + WREG32(data_reg, 0x80108000); + WREG32(index_reg, 0x20701); + WREG32(data_reg, 0x8A80BEB0); + WREG32(index_reg, 0x20702); + WREG32(data_reg, 0xBF0087C0); + WREG32(index_reg, 0x20703); + WREG32(data_reg, 0x80008008); + WREG32(index_reg, 0x20800); + WREG32(data_reg, 0x80108000); + WREG32(index_reg, 0x20801); + WREG32(data_reg, 0x8920BED0); + WREG32(index_reg, 0x20802); + WREG32(data_reg, 0xBED08920); + WREG32(index_reg, 0x20803); + WREG32(data_reg, 0x80008010); + WREG32(index_reg, 0x30000); + WREG32(data_reg, 0x90008000); + WREG32(index_reg, 0x30001); + WREG32(data_reg, 0x80008000); + WREG32(index_reg, 0x30100); + WREG32(data_reg, 0x8FE0BF90); + WREG32(index_reg, 0x30101); + WREG32(data_reg, 0xBFF880A0); + WREG32(index_reg, 0x30200); + WREG32(data_reg, 0x8F60BF40); + WREG32(index_reg, 0x30201); + WREG32(data_reg, 0xBFE88180); + WREG32(index_reg, 0x30300); + WREG32(data_reg, 0x8EC0BF00); + WREG32(index_reg, 0x30301); + WREG32(data_reg, 0xBFC88280); + WREG32(index_reg, 0x30400); + WREG32(data_reg, 0x8DE0BEE0); + WREG32(index_reg, 0x30401); + WREG32(data_reg, 0xBFA083A0); + WREG32(index_reg, 0x30500); + WREG32(data_reg, 0x8CE0BED0); + WREG32(index_reg, 0x30501); + WREG32(data_reg, 0xBF7884E0); + WREG32(index_reg, 0x30600); + WREG32(data_reg, 0x8BA0BED8); + WREG32(index_reg, 0x30601); + WREG32(data_reg, 0xBF508640); + WREG32(index_reg, 0x30700); + WREG32(data_reg, 0x8A60BEE8); + WREG32(index_reg, 0x30701); + WREG32(data_reg, 0xBF2087A0); + WREG32(index_reg, 0x30800); + WREG32(data_reg, 0x8900BF00); + WREG32(index_reg, 0x30801); + WREG32(data_reg, 0xBF008900); } struct rv515_watermark { -- cgit v0.10.2 From 3ce0a23d2d253185df24e22e3d5f89800bb3dd1c Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Tue, 8 Sep 2009 10:10:24 +1000 Subject: drm/radeon/kms: add r600 KMS support This adds the r600 KMS + CS support to the Linux kernel. The r600 TTM support is quite basic and still needs more work esp around using interrupts, but the polled fencing should work okay for now. Also currently TTM is using memcpy to do VRAM moves, the code is here to use a 3D blit to do this, but isn't fully debugged yet. Authors: Alex Deucher Dave Airlie Jerome Glisse Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index c5db0c4..14c3fe6 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -46,8 +46,9 @@ radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \ radeon_encoders.o radeon_display.o radeon_cursor.o radeon_i2c.o \ radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \ radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ - rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \ - radeon_test.o r200.o radeon_legacy_tv.o + rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \ + r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ + r600_blit_kms.o radeon-$(CONFIG_COMPAT) += radeon_ioc32.o diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 8e31e99..a7edd0f 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -389,6 +389,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) pll_flags |= RADEON_PLL_USE_REF_DIV; } radeon_encoder = to_radeon_encoder(encoder); + break; } } diff --git a/drivers/gpu/drm/radeon/avivod.h b/drivers/gpu/drm/radeon/avivod.h new file mode 100644 index 0000000..d4e6e6e --- /dev/null +++ b/drivers/gpu/drm/radeon/avivod.h @@ -0,0 +1,60 @@ +/* + * Copyright 2009 Advanced Micro Devices, Inc. + * Copyright 2009 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef AVIVOD_H +#define AVIVOD_H + + +#define D1CRTC_CONTROL 0x6080 +#define CRTC_EN (1 << 0) +#define D1CRTC_UPDATE_LOCK 0x60E8 +#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 +#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 + +#define D2CRTC_CONTROL 0x6880 +#define D2CRTC_UPDATE_LOCK 0x68E8 +#define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 +#define D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 + +#define D1VGA_CONTROL 0x0330 +#define DVGA_CONTROL_MODE_ENABLE (1 << 0) +#define DVGA_CONTROL_TIMING_SELECT (1 << 8) +#define DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9) +#define DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10) +#define DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16) +#define DVGA_CONTROL_ROTATE (1 << 24) +#define D2VGA_CONTROL 0x0338 + +#define VGA_HDP_CONTROL 0x328 +#define VGA_MEM_PAGE_SELECT_EN (1 << 0) +#define VGA_MEMORY_DISABLE (1 << 4) +#define VGA_RBBM_LOCK_DISABLE (1 << 8) +#define VGA_SOFT_RESET (1 << 16) +#define VGA_MEMORY_BASE_ADDRESS 0x0310 +#define VGA_RENDER_CONTROL 0x0300 +#define VGA_VSTATUS_CNTL_MASK 0x00030000 + +#endif diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index ee3ab62..5708c07 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -31,6 +31,8 @@ #include "radeon_drm.h" #include "radeon_reg.h" #include "radeon.h" +#include "r100d.h" + #include #include @@ -391,9 +393,9 @@ int r100_wb_init(struct radeon_device *rdev) return r; } } - WREG32(0x774, rdev->wb.gpu_addr); - WREG32(0x70C, rdev->wb.gpu_addr + 1024); - WREG32(0x770, 0xff); + WREG32(RADEON_SCRATCH_ADDR, rdev->wb.gpu_addr); + WREG32(RADEON_CP_RB_RPTR_ADDR, rdev->wb.gpu_addr + 1024); + WREG32(RADEON_SCRATCH_UMSK, 0xff); return 0; } @@ -559,18 +561,18 @@ static int r100_cp_init_microcode(struct radeon_device *rdev) fw_name = FIRMWARE_R520; } - err = request_firmware(&rdev->fw, fw_name, &pdev->dev); + err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); platform_device_unregister(pdev); if (err) { printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", fw_name); - } else if (rdev->fw->size % 8) { + } else if (rdev->me_fw->size % 8) { printk(KERN_ERR "radeon_cp: Bogus length %zu in firmware \"%s\"\n", - rdev->fw->size, fw_name); + rdev->me_fw->size, fw_name); err = -EINVAL; - release_firmware(rdev->fw); - rdev->fw = NULL; + release_firmware(rdev->me_fw); + rdev->me_fw = NULL; } return err; } @@ -584,9 +586,9 @@ static void r100_cp_load_microcode(struct radeon_device *rdev) "programming pipes. Bad things might happen.\n"); } - if (rdev->fw) { - size = rdev->fw->size / 4; - fw_data = (const __be32 *)&rdev->fw->data[0]; + if (rdev->me_fw) { + size = rdev->me_fw->size / 4; + fw_data = (const __be32 *)&rdev->me_fw->data[0]; WREG32(RADEON_CP_ME_RAM_ADDR, 0); for (i = 0; i < size; i += 2) { WREG32(RADEON_CP_ME_RAM_DATAH, @@ -632,7 +634,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) DRM_INFO("radeon: cp idle (0x%08X)\n", tmp); } - if (!rdev->fw) { + if (!rdev->me_fw) { r = r100_cp_init_microcode(rdev); if (r) { DRM_ERROR("Failed to load firmware!\n"); @@ -765,6 +767,12 @@ int r100_cp_reset(struct radeon_device *rdev) return -1; } +void r100_cp_commit(struct radeon_device *rdev) +{ + WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); + (void)RREG32(RADEON_CP_RB_WPTR); +} + /* * CS functions @@ -2954,3 +2962,106 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track } } } + +int r100_ring_test(struct radeon_device *rdev) +{ + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = radeon_scratch_get(rdev, &scratch); + if (r) { + DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = radeon_ring_lock(rdev, 2); + if (r) { + DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); + radeon_scratch_free(rdev, scratch); + return r; + } + radeon_ring_write(rdev, PACKET0(scratch, 0)); + radeon_ring_write(rdev, 0xDEADBEEF); + radeon_ring_unlock_commit(rdev); + for (i = 0; i < rdev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) { + break; + } + DRM_UDELAY(1); + } + if (i < rdev->usec_timeout) { + DRM_INFO("ring test succeeded in %d usecs\n", i); + } else { + DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } + radeon_scratch_free(rdev, scratch); + return r; +} + +void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) +{ + radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); + radeon_ring_write(rdev, ib->gpu_addr); + radeon_ring_write(rdev, ib->length_dw); +} + +int r100_ib_test(struct radeon_device *rdev) +{ + struct radeon_ib *ib; + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = radeon_scratch_get(rdev, &scratch); + if (r) { + DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = radeon_ib_get(rdev, &ib); + if (r) { + return r; + } + ib->ptr[0] = PACKET0(scratch, 0); + ib->ptr[1] = 0xDEADBEEF; + ib->ptr[2] = PACKET2(0); + ib->ptr[3] = PACKET2(0); + ib->ptr[4] = PACKET2(0); + ib->ptr[5] = PACKET2(0); + ib->ptr[6] = PACKET2(0); + ib->ptr[7] = PACKET2(0); + ib->length_dw = 8; + r = radeon_ib_schedule(rdev, ib); + if (r) { + radeon_scratch_free(rdev, scratch); + radeon_ib_free(rdev, &ib); + return r; + } + r = radeon_fence_wait(ib->fence, false); + if (r) { + return r; + } + for (i = 0; i < rdev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) { + break; + } + DRM_UDELAY(1); + } + if (i < rdev->usec_timeout) { + DRM_INFO("ib test succeeded in %u usecs\n", i); + } else { + DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } + radeon_scratch_free(rdev, scratch); + radeon_ib_free(rdev, &ib); + return r; +} diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h new file mode 100644 index 0000000..6da7d92 --- /dev/null +++ b/drivers/gpu/drm/radeon/r100d.h @@ -0,0 +1,76 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef __R100D_H__ +#define __R100D_H__ + +#define CP_PACKET0 0x00000000 +#define PACKET0_BASE_INDEX_SHIFT 0 +#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) +#define PACKET0_COUNT_SHIFT 16 +#define PACKET0_COUNT_MASK (0x3fff << 16) +#define CP_PACKET1 0x40000000 +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) +#define CP_PACKET3 0xC0000000 +#define PACKET3_IT_OPCODE_SHIFT 8 +#define PACKET3_IT_OPCODE_MASK (0xff << 8) +#define PACKET3_COUNT_SHIFT 16 +#define PACKET3_COUNT_MASK (0x3fff << 16) +/* PACKET3 op code */ +#define PACKET3_NOP 0x10 +#define PACKET3_3D_DRAW_VBUF 0x28 +#define PACKET3_3D_DRAW_IMMD 0x29 +#define PACKET3_3D_DRAW_INDX 0x2A +#define PACKET3_3D_LOAD_VBPNTR 0x2F +#define PACKET3_INDX_BUFFER 0x33 +#define PACKET3_3D_DRAW_VBUF_2 0x34 +#define PACKET3_3D_DRAW_IMMD_2 0x35 +#define PACKET3_3D_DRAW_INDX_2 0x36 +#define PACKET3_BITBLT_MULTI 0x9B + +#define PACKET0(reg, n) (CP_PACKET0 | \ + REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ + REG_SET(PACKET0_COUNT, (n))) +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) +#define PACKET3(op, n) (CP_PACKET3 | \ + REG_SET(PACKET3_IT_OPCODE, (op)) | \ + REG_SET(PACKET3_COUNT, (n))) + +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) +#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) + +#endif diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 33a2c55..a5f82f7 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -33,6 +33,7 @@ #include "radeon_drm.h" #include "radeon_share.h" #include "r100_track.h" +#include "r300d.h" #include "r300_reg_safe.h" @@ -127,7 +128,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev) WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); rv370_pcie_gart_tlb_flush(rdev); DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", - rdev->mc.gtt_size >> 20, table_addr); + (unsigned)(rdev->mc.gtt_size >> 20), table_addr); rdev->gart.ready = true; return 0; } diff --git a/drivers/gpu/drm/radeon/r300.h b/drivers/gpu/drm/radeon/r300.h deleted file mode 100644 index 8486b4d..0000000 --- a/drivers/gpu/drm/radeon/r300.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2008 Advanced Micro Devices, Inc. - * Copyright 2008 Red Hat Inc. - * Copyright 2009 Jerome Glisse. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Dave Airlie - * Alex Deucher - * Jerome Glisse - */ -#ifndef R300_H -#define R300_H - -struct r300_asic { - const unsigned *reg_safe_bm; - unsigned reg_safe_bm_size; -}; - -#endif diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h new file mode 100644 index 0000000..63ec076 --- /dev/null +++ b/drivers/gpu/drm/radeon/r300d.h @@ -0,0 +1,76 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef __R300D_H__ +#define __R300D_H__ + +#define CP_PACKET0 0x00000000 +#define PACKET0_BASE_INDEX_SHIFT 0 +#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) +#define PACKET0_COUNT_SHIFT 16 +#define PACKET0_COUNT_MASK (0x3fff << 16) +#define CP_PACKET1 0x40000000 +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) +#define CP_PACKET3 0xC0000000 +#define PACKET3_IT_OPCODE_SHIFT 8 +#define PACKET3_IT_OPCODE_MASK (0xff << 8) +#define PACKET3_COUNT_SHIFT 16 +#define PACKET3_COUNT_MASK (0x3fff << 16) +/* PACKET3 op code */ +#define PACKET3_NOP 0x10 +#define PACKET3_3D_DRAW_VBUF 0x28 +#define PACKET3_3D_DRAW_IMMD 0x29 +#define PACKET3_3D_DRAW_INDX 0x2A +#define PACKET3_3D_LOAD_VBPNTR 0x2F +#define PACKET3_INDX_BUFFER 0x33 +#define PACKET3_3D_DRAW_VBUF_2 0x34 +#define PACKET3_3D_DRAW_IMMD_2 0x35 +#define PACKET3_3D_DRAW_INDX_2 0x36 +#define PACKET3_BITBLT_MULTI 0x9B + +#define PACKET0(reg, n) (CP_PACKET0 | \ + REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ + REG_SET(PACKET0_COUNT, (n))) +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) +#define PACKET3(op, n) (CP_PACKET3 | \ + REG_SET(PACKET3_IT_OPCODE, (op)) | \ + REG_SET(PACKET3_COUNT, (n))) + +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) +#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) + +#endif diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 538cd90..d8fcef4 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -25,12 +25,46 @@ * Alex Deucher * Jerome Glisse */ +#include +#include +#include #include "drmP.h" -#include "radeon_reg.h" +#include "radeon_drm.h" #include "radeon.h" +#include "radeon_mode.h" +#include "radeon_share.h" +#include "r600d.h" +#include "avivod.h" +#include "atom.h" -/* r600,rv610,rv630,rv620,rv635,rv670 depends on : */ -void rs600_mc_disable_clients(struct radeon_device *rdev); +#define PFP_UCODE_SIZE 576 +#define PM4_UCODE_SIZE 1792 +#define R700_PFP_UCODE_SIZE 848 +#define R700_PM4_UCODE_SIZE 1360 + +/* Firmware Names */ +MODULE_FIRMWARE("radeon/R600_pfp.bin"); +MODULE_FIRMWARE("radeon/R600_me.bin"); +MODULE_FIRMWARE("radeon/RV610_pfp.bin"); +MODULE_FIRMWARE("radeon/RV610_me.bin"); +MODULE_FIRMWARE("radeon/RV630_pfp.bin"); +MODULE_FIRMWARE("radeon/RV630_me.bin"); +MODULE_FIRMWARE("radeon/RV620_pfp.bin"); +MODULE_FIRMWARE("radeon/RV620_me.bin"); +MODULE_FIRMWARE("radeon/RV635_pfp.bin"); +MODULE_FIRMWARE("radeon/RV635_me.bin"); +MODULE_FIRMWARE("radeon/RV670_pfp.bin"); +MODULE_FIRMWARE("radeon/RV670_me.bin"); +MODULE_FIRMWARE("radeon/RS780_pfp.bin"); +MODULE_FIRMWARE("radeon/RS780_me.bin"); +MODULE_FIRMWARE("radeon/RV770_pfp.bin"); +MODULE_FIRMWARE("radeon/RV770_me.bin"); +MODULE_FIRMWARE("radeon/RV730_pfp.bin"); +MODULE_FIRMWARE("radeon/RV730_me.bin"); +MODULE_FIRMWARE("radeon/RV710_pfp.bin"); +MODULE_FIRMWARE("radeon/RV710_me.bin"); + +int r600_debugfs_mc_info_init(struct radeon_device *rdev); /* This files gather functions specifics to: * r600,rv610,rv630,rv620,rv635,rv670 @@ -39,87 +73,270 @@ void rs600_mc_disable_clients(struct radeon_device *rdev); */ int r600_mc_wait_for_idle(struct radeon_device *rdev); void r600_gpu_init(struct radeon_device *rdev); +void r600_fini(struct radeon_device *rdev); /* - * MC + * R600 PCIE GART */ -int r600_mc_init(struct radeon_device *rdev) +int r600_gart_clear_page(struct radeon_device *rdev, int i) { - uint32_t tmp; + void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; + u64 pte; - r600_gpu_init(rdev); + if (i < 0 || i > rdev->gart.num_gpu_pages) + return -EINVAL; + pte = 0; + writeq(pte, ((void __iomem *)ptr) + (i * 8)); + return 0; +} - /* setup the gart before changing location so we can ask to - * discard unmapped mc request - */ - /* FIXME: disable out of gart access */ - tmp = rdev->mc.gtt_location / 4096; - tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); - WREG32(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp); - tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096; - tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); - WREG32(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp); - - rs600_mc_disable_clients(rdev); - if (r600_mc_wait_for_idle(rdev)) { - printk(KERN_WARNING "Failed to wait MC idle while " - "programming pipes. Bad things might happen.\n"); +void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) +{ + unsigned i; + u32 tmp; + + WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); + WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); + WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); + for (i = 0; i < rdev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); + tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; + if (tmp == 2) { + printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); + return; + } + if (tmp) { + return; + } + udelay(1); + } +} + +int r600_pcie_gart_enable(struct radeon_device *rdev) +{ + u32 tmp; + int r, i; + + /* Initialize common gart structure */ + r = radeon_gart_init(rdev); + if (r) { + return r; + } + rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; + r = radeon_gart_table_vram_alloc(rdev); + if (r) { + return r; } + for (i = 0; i < rdev->gart.num_gpu_pages; i++) + r600_gart_clear_page(rdev, i); + /* Setup L2 cache */ + WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | + ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | + EFFECTIVE_L2_QUEUE_SIZE(7)); + WREG32(VM_L2_CNTL2, 0); + WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); + /* Setup TLB control */ + tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | + SYSTEM_ACCESS_MODE_NOT_IN_SYS | + EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | + ENABLE_WAIT_L2_QUERY; + WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); + WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); + WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); + WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12); + WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); + WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); + WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, + (u32)(rdev->dummy_page.addr >> 12)); + for (i = 1; i < 7; i++) + WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); - tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; - tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24); - tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24); - WREG32(R600_MC_VM_FB_LOCATION, tmp); - tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; - tmp = REG_SET(R600_MC_AGP_TOP, tmp >> 22); - WREG32(R600_MC_VM_AGP_TOP, tmp); - tmp = REG_SET(R600_MC_AGP_BOT, rdev->mc.gtt_location >> 22); - WREG32(R600_MC_VM_AGP_BOT, tmp); + r600_pcie_gart_tlb_flush(rdev); + rdev->gart.ready = true; return 0; } -void r600_mc_fini(struct radeon_device *rdev) +void r600_pcie_gart_disable(struct radeon_device *rdev) { - /* FIXME: implement */ -} + u32 tmp; + int i; + /* Clear ptes*/ + for (i = 0; i < rdev->gart.num_gpu_pages; i++) + r600_gart_clear_page(rdev, i); + r600_pcie_gart_tlb_flush(rdev); + /* Disable all tables */ + for (i = 0; i < 7; i++) + WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); -/* - * Global GPU functions - */ -void r600_errata(struct radeon_device *rdev) -{ - rdev->pll_errata = 0; + /* Disable L2 cache */ + WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | + EFFECTIVE_L2_QUEUE_SIZE(7)); + WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); + /* Setup L1 TLB control */ + tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | + ENABLE_WAIT_L2_QUERY; + WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); + WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); } int r600_mc_wait_for_idle(struct radeon_device *rdev) { - /* FIXME: implement */ - return 0; + unsigned i; + u32 tmp; + + for (i = 0; i < rdev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; + if (!tmp) + return 0; + udelay(1); + } + return -1; } -void r600_gpu_init(struct radeon_device *rdev) +static void r600_mc_resume(struct radeon_device *rdev) { - /* FIXME: implement */ -} + u32 d1vga_control, d2vga_control; + u32 vga_render_control, vga_hdp_control; + u32 d1crtc_control, d2crtc_control; + u32 new_d1grph_primary, new_d1grph_secondary; + u32 new_d2grph_primary, new_d2grph_secondary; + u64 old_vram_start; + u32 tmp; + int i, j; + /* Initialize HDP */ + for (i = 0, j = 0; i < 32; i++, j += 0x18) { + WREG32((0x2c14 + j), 0x00000000); + WREG32((0x2c18 + j), 0x00000000); + WREG32((0x2c1c + j), 0x00000000); + WREG32((0x2c20 + j), 0x00000000); + WREG32((0x2c24 + j), 0x00000000); + } + WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); -/* - * VRAM info - */ -void r600_vram_get_type(struct radeon_device *rdev) + d1vga_control = RREG32(D1VGA_CONTROL); + d2vga_control = RREG32(D2VGA_CONTROL); + vga_render_control = RREG32(VGA_RENDER_CONTROL); + vga_hdp_control = RREG32(VGA_HDP_CONTROL); + d1crtc_control = RREG32(D1CRTC_CONTROL); + d2crtc_control = RREG32(D2CRTC_CONTROL); + old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; + new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS); + new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS); + new_d1grph_primary += rdev->mc.vram_start - old_vram_start; + new_d1grph_secondary += rdev->mc.vram_start - old_vram_start; + new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS); + new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS); + new_d2grph_primary += rdev->mc.vram_start - old_vram_start; + new_d2grph_secondary += rdev->mc.vram_start - old_vram_start; + + /* Stop all video */ + WREG32(D1VGA_CONTROL, 0); + WREG32(D2VGA_CONTROL, 0); + WREG32(VGA_RENDER_CONTROL, 0); + WREG32(D1CRTC_UPDATE_LOCK, 1); + WREG32(D2CRTC_UPDATE_LOCK, 1); + WREG32(D1CRTC_CONTROL, 0); + WREG32(D2CRTC_CONTROL, 0); + WREG32(D1CRTC_UPDATE_LOCK, 0); + WREG32(D2CRTC_UPDATE_LOCK, 0); + + mdelay(1); + if (r600_mc_wait_for_idle(rdev)) { + printk(KERN_WARNING "[drm] MC not idle !\n"); + } + + /* Lockout access through VGA aperture*/ + WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); + + /* Update configuration */ + WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); + WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12); + WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); + tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16; + tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); + WREG32(MC_VM_FB_LOCATION, tmp); + WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); + WREG32(HDP_NONSURFACE_INFO, (2 << 7)); + WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); + if (rdev->flags & RADEON_IS_AGP) { + WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16); + WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); + WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); + } else { + WREG32(MC_VM_AGP_BASE, 0); + WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); + WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); + } + WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary); + WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary); + WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary); + WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary); + WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); + + /* Unlock host access */ + WREG32(VGA_HDP_CONTROL, vga_hdp_control); + + mdelay(1); + if (r600_mc_wait_for_idle(rdev)) { + printk(KERN_WARNING "[drm] MC not idle !\n"); + } + + /* Restore video state */ + WREG32(D1CRTC_UPDATE_LOCK, 1); + WREG32(D2CRTC_UPDATE_LOCK, 1); + WREG32(D1CRTC_CONTROL, d1crtc_control); + WREG32(D2CRTC_CONTROL, d2crtc_control); + WREG32(D1CRTC_UPDATE_LOCK, 0); + WREG32(D2CRTC_UPDATE_LOCK, 0); + WREG32(D1VGA_CONTROL, d1vga_control); + WREG32(D2VGA_CONTROL, d2vga_control); + WREG32(VGA_RENDER_CONTROL, vga_render_control); +} + +int r600_mc_init(struct radeon_device *rdev) { - uint32_t tmp; + fixed20_12 a; + u32 tmp; int chansize; + int r; + /* Get VRAM informations */ rdev->mc.vram_width = 128; rdev->mc.vram_is_ddr = true; - - tmp = RREG32(R600_RAMCFG); - if (tmp & R600_CHANSIZE_OVERRIDE) { + tmp = RREG32(RAMCFG); + if (tmp & CHANSIZE_OVERRIDE) { chansize = 16; - } else if (tmp & R600_CHANSIZE) { + } else if (tmp & CHANSIZE_MASK) { chansize = 64; } else { chansize = 32; @@ -135,36 +352,1391 @@ void r600_vram_get_type(struct radeon_device *rdev) (rdev->family == CHIP_RV635)) { rdev->mc.vram_width = 2 * chansize; } + /* Could aper size report 0 ? */ + rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); + rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); + /* Setup GPU memory space */ + rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); + rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); + if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) + return r; + /* gtt_size is setup by radeon_agp_init */ + rdev->mc.gtt_location = rdev->mc.agp_base; + tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; + /* Try to put vram before or after AGP because we + * we want SYSTEM_APERTURE to cover both VRAM and + * AGP so that GPU can catch out of VRAM/AGP access + */ + if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { + /* Enought place before */ + rdev->mc.vram_location = rdev->mc.gtt_location - + rdev->mc.mc_vram_size; + } else if (tmp > rdev->mc.mc_vram_size) { + /* Enought place after */ + rdev->mc.vram_location = rdev->mc.gtt_location + + rdev->mc.gtt_size; + } else { + /* Try to setup VRAM then AGP might not + * not work on some card + */ + rdev->mc.vram_location = 0x00000000UL; + rdev->mc.gtt_location = rdev->mc.mc_vram_size; + } + } else { + if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { + rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) & + 0xFFFF) << 24; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; + tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; + if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { + /* Enough place after vram */ + rdev->mc.gtt_location = tmp; + } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) { + /* Enough place before vram */ + rdev->mc.gtt_location = 0; + } else { + /* Not enough place after or before shrink + * gart size + */ + if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) { + rdev->mc.gtt_location = 0; + rdev->mc.gtt_size = rdev->mc.vram_location; + } else { + rdev->mc.gtt_location = tmp; + rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp; + } + } + rdev->mc.gtt_location = rdev->mc.mc_vram_size; + } else { + rdev->mc.vram_location = 0x00000000UL; + rdev->mc.gtt_location = rdev->mc.mc_vram_size; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; + } + } + rdev->mc.vram_start = rdev->mc.vram_location; + rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size; + rdev->mc.gtt_start = rdev->mc.gtt_location; + rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size; + /* FIXME: we should enforce default clock in case GPU is not in + * default setup + */ + a.full = rfixed_const(100); + rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); + rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); + return 0; } -void r600_vram_info(struct radeon_device *rdev) +/* We doesn't check that the GPU really needs a reset we simply do the + * reset, it's up to the caller to determine if the GPU needs one. We + * might add an helper function to check that. + */ +int r600_gpu_soft_reset(struct radeon_device *rdev) { - r600_vram_get_type(rdev); - rdev->mc.real_vram_size = RREG32(R600_CONFIG_MEMSIZE); - rdev->mc.mc_vram_size = rdev->mc.real_vram_size; + u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | + S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | + S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | + S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | + S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | + S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | + S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | + S_008010_GUI_ACTIVE(1); + u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | + S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | + S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | + S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | + S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | + S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | + S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | + S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); + u32 srbm_reset = 0; - /* Could aper size report 0 ? */ - rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); - rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); + /* Disable CP parsing/prefetching */ + WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff)); + /* Check if any of the rendering block is busy and reset it */ + if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || + (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { + WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) | + S_008020_SOFT_RESET_DB(1) | + S_008020_SOFT_RESET_CB(1) | + S_008020_SOFT_RESET_PA(1) | + S_008020_SOFT_RESET_SC(1) | + S_008020_SOFT_RESET_SMX(1) | + S_008020_SOFT_RESET_SPI(1) | + S_008020_SOFT_RESET_SX(1) | + S_008020_SOFT_RESET_SH(1) | + S_008020_SOFT_RESET_TC(1) | + S_008020_SOFT_RESET_TA(1) | + S_008020_SOFT_RESET_VC(1) | + S_008020_SOFT_RESET_VGT(1)); + (void)RREG32(R_008020_GRBM_SOFT_RESET); + udelay(50); + WREG32(R_008020_GRBM_SOFT_RESET, 0); + (void)RREG32(R_008020_GRBM_SOFT_RESET); + } + /* Reset CP (we always reset CP) */ + WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1)); + (void)RREG32(R_008020_GRBM_SOFT_RESET); + udelay(50); + WREG32(R_008020_GRBM_SOFT_RESET, 0); + (void)RREG32(R_008020_GRBM_SOFT_RESET); + /* Reset others GPU block if necessary */ + if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_RLC(1); + if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_GRBM(1); + if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_IH(1); + if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_VMC(1); + if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_MC(1); + if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_MC(1); + if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_MC(1); + if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_MC(1); + if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_MC(1); + if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_RLC(1); + if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS))) + srbm_reset |= S_000E60_SOFT_RESET_SEM(1); + WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset); + (void)RREG32(R_000E60_SRBM_SOFT_RESET); + udelay(50); + WREG32(R_000E60_SRBM_SOFT_RESET, 0); + (void)RREG32(R_000E60_SRBM_SOFT_RESET); + /* Wait a little for things to settle down */ + udelay(50); + return 0; +} + +int r600_gpu_reset(struct radeon_device *rdev) +{ + return r600_gpu_soft_reset(rdev); +} + +static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, + u32 num_backends, + u32 backend_disable_mask) +{ + u32 backend_map = 0; + u32 enabled_backends_mask; + u32 enabled_backends_count; + u32 cur_pipe; + u32 swizzle_pipe[R6XX_MAX_PIPES]; + u32 cur_backend; + u32 i; + + if (num_tile_pipes > R6XX_MAX_PIPES) + num_tile_pipes = R6XX_MAX_PIPES; + if (num_tile_pipes < 1) + num_tile_pipes = 1; + if (num_backends > R6XX_MAX_BACKENDS) + num_backends = R6XX_MAX_BACKENDS; + if (num_backends < 1) + num_backends = 1; + + enabled_backends_mask = 0; + enabled_backends_count = 0; + for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { + if (((backend_disable_mask >> i) & 1) == 0) { + enabled_backends_mask |= (1 << i); + ++enabled_backends_count; + } + if (enabled_backends_count == num_backends) + break; + } + + if (enabled_backends_count == 0) { + enabled_backends_mask = 1; + enabled_backends_count = 1; + } + + if (enabled_backends_count != num_backends) + num_backends = enabled_backends_count; + + memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); + switch (num_tile_pipes) { + case 1: + swizzle_pipe[0] = 0; + break; + case 2: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + break; + case 3: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + break; + case 4: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + break; + case 5: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + swizzle_pipe[2] = 2; + swizzle_pipe[3] = 3; + swizzle_pipe[4] = 4; + break; + case 6: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 5; + swizzle_pipe[4] = 1; + swizzle_pipe[5] = 3; + break; + case 7: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 6; + swizzle_pipe[4] = 1; + swizzle_pipe[5] = 3; + swizzle_pipe[6] = 5; + break; + case 8: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 6; + swizzle_pipe[4] = 1; + swizzle_pipe[5] = 3; + swizzle_pipe[6] = 5; + swizzle_pipe[7] = 7; + break; + } + + cur_backend = 0; + for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { + while (((1 << cur_backend) & enabled_backends_mask) == 0) + cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; + + backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); + + cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; + } + + return backend_map; +} + +int r600_count_pipe_bits(uint32_t val) +{ + int i, ret = 0; + + for (i = 0; i < 32; i++) { + ret += val & 1; + val >>= 1; + } + return ret; } +void r600_gpu_init(struct radeon_device *rdev) +{ + u32 tiling_config; + u32 ramcfg; + u32 tmp; + int i, j; + u32 sq_config; + u32 sq_gpr_resource_mgmt_1 = 0; + u32 sq_gpr_resource_mgmt_2 = 0; + u32 sq_thread_resource_mgmt = 0; + u32 sq_stack_resource_mgmt_1 = 0; + u32 sq_stack_resource_mgmt_2 = 0; + + /* FIXME: implement */ + switch (rdev->family) { + case CHIP_R600: + rdev->config.r600.max_pipes = 4; + rdev->config.r600.max_tile_pipes = 8; + rdev->config.r600.max_simds = 4; + rdev->config.r600.max_backends = 4; + rdev->config.r600.max_gprs = 256; + rdev->config.r600.max_threads = 192; + rdev->config.r600.max_stack_entries = 256; + rdev->config.r600.max_hw_contexts = 8; + rdev->config.r600.max_gs_threads = 16; + rdev->config.r600.sx_max_export_size = 128; + rdev->config.r600.sx_max_export_pos_size = 16; + rdev->config.r600.sx_max_export_smx_size = 128; + rdev->config.r600.sq_num_cf_insts = 2; + break; + case CHIP_RV630: + case CHIP_RV635: + rdev->config.r600.max_pipes = 2; + rdev->config.r600.max_tile_pipes = 2; + rdev->config.r600.max_simds = 3; + rdev->config.r600.max_backends = 1; + rdev->config.r600.max_gprs = 128; + rdev->config.r600.max_threads = 192; + rdev->config.r600.max_stack_entries = 128; + rdev->config.r600.max_hw_contexts = 8; + rdev->config.r600.max_gs_threads = 4; + rdev->config.r600.sx_max_export_size = 128; + rdev->config.r600.sx_max_export_pos_size = 16; + rdev->config.r600.sx_max_export_smx_size = 128; + rdev->config.r600.sq_num_cf_insts = 2; + break; + case CHIP_RV610: + case CHIP_RV620: + case CHIP_RS780: + case CHIP_RS880: + rdev->config.r600.max_pipes = 1; + rdev->config.r600.max_tile_pipes = 1; + rdev->config.r600.max_simds = 2; + rdev->config.r600.max_backends = 1; + rdev->config.r600.max_gprs = 128; + rdev->config.r600.max_threads = 192; + rdev->config.r600.max_stack_entries = 128; + rdev->config.r600.max_hw_contexts = 4; + rdev->config.r600.max_gs_threads = 4; + rdev->config.r600.sx_max_export_size = 128; + rdev->config.r600.sx_max_export_pos_size = 16; + rdev->config.r600.sx_max_export_smx_size = 128; + rdev->config.r600.sq_num_cf_insts = 1; + break; + case CHIP_RV670: + rdev->config.r600.max_pipes = 4; + rdev->config.r600.max_tile_pipes = 4; + rdev->config.r600.max_simds = 4; + rdev->config.r600.max_backends = 4; + rdev->config.r600.max_gprs = 192; + rdev->config.r600.max_threads = 192; + rdev->config.r600.max_stack_entries = 256; + rdev->config.r600.max_hw_contexts = 8; + rdev->config.r600.max_gs_threads = 16; + rdev->config.r600.sx_max_export_size = 128; + rdev->config.r600.sx_max_export_pos_size = 16; + rdev->config.r600.sx_max_export_smx_size = 128; + rdev->config.r600.sq_num_cf_insts = 2; + break; + default: + break; + } + + /* Initialize HDP */ + for (i = 0, j = 0; i < 32; i++, j += 0x18) { + WREG32((0x2c14 + j), 0x00000000); + WREG32((0x2c18 + j), 0x00000000); + WREG32((0x2c1c + j), 0x00000000); + WREG32((0x2c20 + j), 0x00000000); + WREG32((0x2c24 + j), 0x00000000); + } + + WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); + + /* Setup tiling */ + tiling_config = 0; + ramcfg = RREG32(RAMCFG); + switch (rdev->config.r600.max_tile_pipes) { + case 1: + tiling_config |= PIPE_TILING(0); + break; + case 2: + tiling_config |= PIPE_TILING(1); + break; + case 4: + tiling_config |= PIPE_TILING(2); + break; + case 8: + tiling_config |= PIPE_TILING(3); + break; + default: + break; + } + tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); + tiling_config |= GROUP_SIZE(0); + tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; + if (tmp > 3) { + tiling_config |= ROW_TILING(3); + tiling_config |= SAMPLE_SPLIT(3); + } else { + tiling_config |= ROW_TILING(tmp); + tiling_config |= SAMPLE_SPLIT(tmp); + } + tiling_config |= BANK_SWAPS(1); + tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, + rdev->config.r600.max_backends, + (0xff << rdev->config.r600.max_backends) & 0xff); + tiling_config |= BACKEND_MAP(tmp); + WREG32(GB_TILING_CONFIG, tiling_config); + WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); + WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); + + tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); + WREG32(CC_RB_BACKEND_DISABLE, tmp); + + /* Setup pipes */ + tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); + tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); + WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp); + WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp); + + tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK); + WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); + WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); + + /* Setup some CP states */ + WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); + WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); + + WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | + SYNC_WALKER | SYNC_ALIGNER)); + /* Setup various GPU states */ + if (rdev->family == CHIP_RV670) + WREG32(ARB_GDEC_RD_CNTL, 0x00000021); + + tmp = RREG32(SX_DEBUG_1); + tmp |= SMX_EVENT_RELEASE; + if ((rdev->family > CHIP_R600)) + tmp |= ENABLE_NEW_SMX_ADDRESS; + WREG32(SX_DEBUG_1, tmp); + + if (((rdev->family) == CHIP_R600) || + ((rdev->family) == CHIP_RV630) || + ((rdev->family) == CHIP_RV610) || + ((rdev->family) == CHIP_RV620) || + ((rdev->family) == CHIP_RS780)) { + WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); + } else { + WREG32(DB_DEBUG, 0); + } + WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | + DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); + + WREG32(PA_SC_MULTI_CHIP_CNTL, 0); + WREG32(VGT_NUM_INSTANCES, 0); + + WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); + WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); + + tmp = RREG32(SQ_MS_FIFO_SIZES); + if (((rdev->family) == CHIP_RV610) || + ((rdev->family) == CHIP_RV620) || + ((rdev->family) == CHIP_RS780)) { + tmp = (CACHE_FIFO_SIZE(0xa) | + FETCH_FIFO_HIWATER(0xa) | + DONE_FIFO_HIWATER(0xe0) | + ALU_UPDATE_FIFO_HIWATER(0x8)); + } else if (((rdev->family) == CHIP_R600) || + ((rdev->family) == CHIP_RV630)) { + tmp &= ~DONE_FIFO_HIWATER(0xff); + tmp |= DONE_FIFO_HIWATER(0x4); + } + WREG32(SQ_MS_FIFO_SIZES, tmp); + + /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT + * should be adjusted as needed by the 2D/3D drivers. This just sets default values + */ + sq_config = RREG32(SQ_CONFIG); + sq_config &= ~(PS_PRIO(3) | + VS_PRIO(3) | + GS_PRIO(3) | + ES_PRIO(3)); + sq_config |= (DX9_CONSTS | + VC_ENABLE | + PS_PRIO(0) | + VS_PRIO(1) | + GS_PRIO(2) | + ES_PRIO(3)); + + if ((rdev->family) == CHIP_R600) { + sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | + NUM_VS_GPRS(124) | + NUM_CLAUSE_TEMP_GPRS(4)); + sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | + NUM_ES_GPRS(0)); + sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | + NUM_VS_THREADS(48) | + NUM_GS_THREADS(4) | + NUM_ES_THREADS(4)); + sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | + NUM_VS_STACK_ENTRIES(128)); + sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | + NUM_ES_STACK_ENTRIES(0)); + } else if (((rdev->family) == CHIP_RV610) || + ((rdev->family) == CHIP_RV620) || + ((rdev->family) == CHIP_RS780)) { + /* no vertex cache */ + sq_config &= ~VC_ENABLE; + + sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | + NUM_VS_GPRS(44) | + NUM_CLAUSE_TEMP_GPRS(2)); + sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | + NUM_ES_GPRS(17)); + sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | + NUM_VS_THREADS(78) | + NUM_GS_THREADS(4) | + NUM_ES_THREADS(31)); + sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | + NUM_VS_STACK_ENTRIES(40)); + sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | + NUM_ES_STACK_ENTRIES(16)); + } else if (((rdev->family) == CHIP_RV630) || + ((rdev->family) == CHIP_RV635)) { + sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | + NUM_VS_GPRS(44) | + NUM_CLAUSE_TEMP_GPRS(2)); + sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | + NUM_ES_GPRS(18)); + sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | + NUM_VS_THREADS(78) | + NUM_GS_THREADS(4) | + NUM_ES_THREADS(31)); + sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | + NUM_VS_STACK_ENTRIES(40)); + sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | + NUM_ES_STACK_ENTRIES(16)); + } else if ((rdev->family) == CHIP_RV670) { + sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | + NUM_VS_GPRS(44) | + NUM_CLAUSE_TEMP_GPRS(2)); + sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | + NUM_ES_GPRS(17)); + sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | + NUM_VS_THREADS(78) | + NUM_GS_THREADS(4) | + NUM_ES_THREADS(31)); + sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | + NUM_VS_STACK_ENTRIES(64)); + sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | + NUM_ES_STACK_ENTRIES(64)); + } + + WREG32(SQ_CONFIG, sq_config); + WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); + WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); + WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); + WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); + WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); + + if (((rdev->family) == CHIP_RV610) || + ((rdev->family) == CHIP_RV620) || + ((rdev->family) == CHIP_RS780)) { + WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); + } else { + WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); + } + + /* More default values. 2D/3D driver should adjust as needed */ + WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | + S1_X(0x4) | S1_Y(0xc))); + WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | + S1_X(0x2) | S1_Y(0x2) | + S2_X(0xa) | S2_Y(0x6) | + S3_X(0x6) | S3_Y(0xa))); + WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | + S1_X(0x4) | S1_Y(0xc) | + S2_X(0x1) | S2_Y(0x6) | + S3_X(0xa) | S3_Y(0xe))); + WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | + S5_X(0x0) | S5_Y(0x0) | + S6_X(0xb) | S6_Y(0x4) | + S7_X(0x7) | S7_Y(0x8))); + + WREG32(VGT_STRMOUT_EN, 0); + tmp = rdev->config.r600.max_pipes * 16; + switch (rdev->family) { + case CHIP_RV610: + case CHIP_RS780: + case CHIP_RV620: + tmp += 32; + break; + case CHIP_RV670: + tmp += 128; + break; + default: + break; + } + if (tmp > 256) { + tmp = 256; + } + WREG32(VGT_ES_PER_GS, 128); + WREG32(VGT_GS_PER_ES, tmp); + WREG32(VGT_GS_PER_VS, 2); + WREG32(VGT_GS_VERTEX_REUSE, 16); + + /* more default values. 2D/3D driver should adjust as needed */ + WREG32(PA_SC_LINE_STIPPLE_STATE, 0); + WREG32(VGT_STRMOUT_EN, 0); + WREG32(SX_MISC, 0); + WREG32(PA_SC_MODE_CNTL, 0); + WREG32(PA_SC_AA_CONFIG, 0); + WREG32(PA_SC_LINE_STIPPLE, 0); + WREG32(SPI_INPUT_Z, 0); + WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); + WREG32(CB_COLOR7_FRAG, 0); + + /* Clear render buffer base addresses */ + WREG32(CB_COLOR0_BASE, 0); + WREG32(CB_COLOR1_BASE, 0); + WREG32(CB_COLOR2_BASE, 0); + WREG32(CB_COLOR3_BASE, 0); + WREG32(CB_COLOR4_BASE, 0); + WREG32(CB_COLOR5_BASE, 0); + WREG32(CB_COLOR6_BASE, 0); + WREG32(CB_COLOR7_BASE, 0); + WREG32(CB_COLOR7_FRAG, 0); + + switch (rdev->family) { + case CHIP_RV610: + case CHIP_RS780: + case CHIP_RV620: + tmp = TC_L2_SIZE(8); + break; + case CHIP_RV630: + case CHIP_RV635: + tmp = TC_L2_SIZE(4); + break; + case CHIP_R600: + tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; + break; + default: + tmp = TC_L2_SIZE(0); + break; + } + WREG32(TC_CNTL, tmp); + + tmp = RREG32(HDP_HOST_PATH_CNTL); + WREG32(HDP_HOST_PATH_CNTL, tmp); + + tmp = RREG32(ARB_POP); + tmp |= ENABLE_TC128; + WREG32(ARB_POP, tmp); + + WREG32(PA_SC_MULTI_CHIP_CNTL, 0); + WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | + NUM_CLIP_SEQ(3))); + WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); +} + + /* * Indirect registers accessor */ -uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg) +u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) +{ + u32 r; + + WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); + (void)RREG32(PCIE_PORT_INDEX); + r = RREG32(PCIE_PORT_DATA); + return r; +} + +void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); + (void)RREG32(PCIE_PORT_INDEX); + WREG32(PCIE_PORT_DATA, (v)); + (void)RREG32(PCIE_PORT_DATA); +} + + +/* + * CP & Ring + */ +void r600_cp_stop(struct radeon_device *rdev) +{ + WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); +} + +int r600_cp_init_microcode(struct radeon_device *rdev) +{ + struct platform_device *pdev; + const char *chip_name; + size_t pfp_req_size, me_req_size; + char fw_name[30]; + int err; + + DRM_DEBUG("\n"); + + pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); + err = IS_ERR(pdev); + if (err) { + printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); + return -EINVAL; + } + + switch (rdev->family) { + case CHIP_R600: chip_name = "R600"; break; + case CHIP_RV610: chip_name = "RV610"; break; + case CHIP_RV630: chip_name = "RV630"; break; + case CHIP_RV620: chip_name = "RV620"; break; + case CHIP_RV635: chip_name = "RV635"; break; + case CHIP_RV670: chip_name = "RV670"; break; + case CHIP_RS780: + case CHIP_RS880: chip_name = "RS780"; break; + case CHIP_RV770: chip_name = "RV770"; break; + case CHIP_RV730: + case CHIP_RV740: chip_name = "RV730"; break; + case CHIP_RV710: chip_name = "RV710"; break; + default: BUG(); + } + + if (rdev->family >= CHIP_RV770) { + pfp_req_size = R700_PFP_UCODE_SIZE * 4; + me_req_size = R700_PM4_UCODE_SIZE * 4; + } else { + pfp_req_size = PFP_UCODE_SIZE * 4; + me_req_size = PM4_UCODE_SIZE * 12; + } + + DRM_INFO("Loading %s CP Microcode\n", chip_name); + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); + err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); + if (err) + goto out; + if (rdev->pfp_fw->size != pfp_req_size) { + printk(KERN_ERR + "r600_cp: Bogus length %zu in firmware \"%s\"\n", + rdev->pfp_fw->size, fw_name); + err = -EINVAL; + goto out; + } + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); + err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); + if (err) + goto out; + if (rdev->me_fw->size != me_req_size) { + printk(KERN_ERR + "r600_cp: Bogus length %zu in firmware \"%s\"\n", + rdev->me_fw->size, fw_name); + err = -EINVAL; + } +out: + platform_device_unregister(pdev); + + if (err) { + if (err != -EINVAL) + printk(KERN_ERR + "r600_cp: Failed to load firmware \"%s\"\n", + fw_name); + release_firmware(rdev->pfp_fw); + rdev->pfp_fw = NULL; + release_firmware(rdev->me_fw); + rdev->me_fw = NULL; + } + return err; +} + +static int r600_cp_load_microcode(struct radeon_device *rdev) +{ + const __be32 *fw_data; + int i; + + if (!rdev->me_fw || !rdev->pfp_fw) + return -EINVAL; + + r600_cp_stop(rdev); + + WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); + + /* Reset cp */ + WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); + RREG32(GRBM_SOFT_RESET); + mdelay(15); + WREG32(GRBM_SOFT_RESET, 0); + + WREG32(CP_ME_RAM_WADDR, 0); + + fw_data = (const __be32 *)rdev->me_fw->data; + WREG32(CP_ME_RAM_WADDR, 0); + for (i = 0; i < PM4_UCODE_SIZE * 3; i++) + WREG32(CP_ME_RAM_DATA, + be32_to_cpup(fw_data++)); + + fw_data = (const __be32 *)rdev->pfp_fw->data; + WREG32(CP_PFP_UCODE_ADDR, 0); + for (i = 0; i < PFP_UCODE_SIZE; i++) + WREG32(CP_PFP_UCODE_DATA, + be32_to_cpup(fw_data++)); + + WREG32(CP_PFP_UCODE_ADDR, 0); + WREG32(CP_ME_RAM_WADDR, 0); + WREG32(CP_ME_RAM_RADDR, 0); + return 0; +} + +int r600_cp_start(struct radeon_device *rdev) +{ + int r; + uint32_t cp_me; + + r = radeon_ring_lock(rdev, 7); + if (r) { + DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); + return r; + } + radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); + radeon_ring_write(rdev, 0x1); + if (rdev->family < CHIP_RV770) { + radeon_ring_write(rdev, 0x3); + radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); + } else { + radeon_ring_write(rdev, 0x0); + radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); + } + radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); + radeon_ring_write(rdev, 0); + radeon_ring_write(rdev, 0); + radeon_ring_unlock_commit(rdev); + + cp_me = 0xff; + WREG32(R_0086D8_CP_ME_CNTL, cp_me); + return 0; +} + +int r600_cp_resume(struct radeon_device *rdev) +{ + u32 tmp; + u32 rb_bufsz; + int r; + + /* Reset cp */ + WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); + RREG32(GRBM_SOFT_RESET); + mdelay(15); + WREG32(GRBM_SOFT_RESET, 0); + + /* Set ring buffer size */ + rb_bufsz = drm_order(rdev->cp.ring_size / 8); +#ifdef __BIG_ENDIAN + WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE | + (drm_order(4096/8) << 8) | rb_bufsz); +#else + WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz); +#endif + WREG32(CP_SEM_WAIT_TIMER, 0x4); + + /* Set the write pointer delay */ + WREG32(CP_RB_WPTR_DELAY, 0); + + /* Initialize the ring buffer's read and write pointers */ + tmp = RREG32(CP_RB_CNTL); + WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); + WREG32(CP_RB_RPTR_WR, 0); + WREG32(CP_RB_WPTR, 0); + WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF); + WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr)); + mdelay(1); + WREG32(CP_RB_CNTL, tmp); + + WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); + WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); + + rdev->cp.rptr = RREG32(CP_RB_RPTR); + rdev->cp.wptr = RREG32(CP_RB_WPTR); + + r600_cp_start(rdev); + rdev->cp.ready = true; + r = radeon_ring_test(rdev); + if (r) { + rdev->cp.ready = false; + return r; + } + return 0; +} + +void r600_cp_commit(struct radeon_device *rdev) +{ + WREG32(CP_RB_WPTR, rdev->cp.wptr); + (void)RREG32(CP_RB_WPTR); +} + +void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) +{ + u32 rb_bufsz; + + /* Align ring size */ + rb_bufsz = drm_order(ring_size / 8); + ring_size = (1 << (rb_bufsz + 1)) * 4; + rdev->cp.ring_size = ring_size; + rdev->cp.align_mask = 16 - 1; +} + + +/* + * GPU scratch registers helpers function. + */ +void r600_scratch_init(struct radeon_device *rdev) +{ + int i; + + rdev->scratch.num_reg = 7; + for (i = 0; i < rdev->scratch.num_reg; i++) { + rdev->scratch.free[i] = true; + rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4); + } +} + +int r600_ring_test(struct radeon_device *rdev) +{ + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = radeon_scratch_get(rdev, &scratch); + if (r) { + DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = radeon_ring_lock(rdev, 3); + if (r) { + DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); + radeon_scratch_free(rdev, scratch); + return r; + } + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); + radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); + radeon_ring_write(rdev, 0xDEADBEEF); + radeon_ring_unlock_commit(rdev); + for (i = 0; i < rdev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i < rdev->usec_timeout) { + DRM_INFO("ring test succeeded in %d usecs\n", i); + } else { + DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } + radeon_scratch_free(rdev, scratch); + return r; +} + +/* + * Writeback + */ +int r600_wb_init(struct radeon_device *rdev) +{ + int r; + + if (rdev->wb.wb_obj == NULL) { + r = radeon_object_create(rdev, NULL, 4096, + true, + RADEON_GEM_DOMAIN_GTT, + false, &rdev->wb.wb_obj); + if (r) { + DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r); + return r; + } + r = radeon_object_pin(rdev->wb.wb_obj, + RADEON_GEM_DOMAIN_GTT, + &rdev->wb.gpu_addr); + if (r) { + DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r); + return r; + } + r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); + if (r) { + DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r); + return r; + } + } + WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF); + WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC); + WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF); + WREG32(SCRATCH_UMSK, 0xff); + return 0; +} + +void r600_wb_fini(struct radeon_device *rdev) +{ + if (rdev->wb.wb_obj) { + radeon_object_kunmap(rdev->wb.wb_obj); + radeon_object_unpin(rdev->wb.wb_obj); + radeon_object_unref(&rdev->wb.wb_obj); + rdev->wb.wb = NULL; + rdev->wb.wb_obj = NULL; + } +} + + +/* + * CS + */ +void r600_fence_ring_emit(struct radeon_device *rdev, + struct radeon_fence *fence) +{ + /* Emit fence sequence & fire IRQ */ + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); + radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); + radeon_ring_write(rdev, fence->seq); +} + +int r600_copy_dma(struct radeon_device *rdev, + uint64_t src_offset, + uint64_t dst_offset, + unsigned num_pages, + struct radeon_fence *fence) +{ + /* FIXME: implement */ + return 0; +} + +int r600_copy_blit(struct radeon_device *rdev, + uint64_t src_offset, uint64_t dst_offset, + unsigned num_pages, struct radeon_fence *fence) +{ + r600_blit_prepare_copy(rdev, num_pages * 4096); + r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096); + r600_blit_done_copy(rdev, fence); + return 0; +} + +int r600_irq_process(struct radeon_device *rdev) +{ + /* FIXME: implement */ + return 0; +} + +int r600_irq_set(struct radeon_device *rdev) +{ + /* FIXME: implement */ + return 0; +} + +int r600_set_surface_reg(struct radeon_device *rdev, int reg, + uint32_t tiling_flags, uint32_t pitch, + uint32_t offset, uint32_t obj_size) +{ + /* FIXME: implement */ + return 0; +} + +void r600_clear_surface_reg(struct radeon_device *rdev, int reg) +{ + /* FIXME: implement */ +} + + +bool r600_card_posted(struct radeon_device *rdev) +{ + uint32_t reg; + + /* first check CRTCs */ + reg = RREG32(D1CRTC_CONTROL) | + RREG32(D2CRTC_CONTROL); + if (reg & CRTC_EN) + return true; + + /* then check MEM_SIZE, in case the crtcs are off */ + if (RREG32(CONFIG_MEMSIZE)) + return true; + + return false; +} + +int r600_resume(struct radeon_device *rdev) +{ + int r; + + r600_gpu_reset(rdev); + r600_mc_resume(rdev); + r = r600_pcie_gart_enable(rdev); + if (r) + return r; + r600_gpu_init(rdev); + r = radeon_ring_init(rdev, rdev->cp.ring_size); + if (r) + return r; + r = r600_cp_load_microcode(rdev); + if (r) + return r; + r = r600_cp_resume(rdev); + if (r) + return r; + r = r600_wb_init(rdev); + if (r) + return r; + return 0; +} + +int r600_suspend(struct radeon_device *rdev) +{ + /* FIXME: we should wait for ring to be empty */ + r600_cp_stop(rdev); + return 0; +} + +/* Plan is to move initialization in that function and use + * helper function so that radeon_device_init pretty much + * do nothing more than calling asic specific function. This + * should also allow to remove a bunch of callback function + * like vram_info. + */ +int r600_init(struct radeon_device *rdev) { - uint32_t r; + int r; - WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); - (void)RREG32(R600_PCIE_PORT_INDEX); - r = RREG32(R600_PCIE_PORT_DATA); + rdev->new_init_path = true; + r = radeon_dummy_page_init(rdev); + if (r) + return r; + if (r600_debugfs_mc_info_init(rdev)) { + DRM_ERROR("Failed to register debugfs file for mc !\n"); + } + /* This don't do much */ + r = radeon_gem_init(rdev); + if (r) + return r; + /* Read BIOS */ + if (!radeon_get_bios(rdev)) { + if (ASIC_IS_AVIVO(rdev)) + return -EINVAL; + } + /* Must be an ATOMBIOS */ + if (!rdev->is_atom_bios) + return -EINVAL; + r = radeon_atombios_init(rdev); + if (r) + return r; + /* Post card if necessary */ + if (!r600_card_posted(rdev) && rdev->bios) { + DRM_INFO("GPU not posted. posting now...\n"); + atom_asic_init(rdev->mode_info.atom_context); + } + /* Initialize scratch registers */ + r600_scratch_init(rdev); + /* Initialize surface registers */ + radeon_surface_init(rdev); + r = radeon_clocks_init(rdev); + if (r) + return r; + /* Fence driver */ + r = radeon_fence_driver_init(rdev); + if (r) + return r; + r = r600_mc_init(rdev); + if (r) { + if (rdev->flags & RADEON_IS_AGP) { + /* Retry with disabling AGP */ + r600_fini(rdev); + rdev->flags &= ~RADEON_IS_AGP; + return r600_init(rdev); + } + return r; + } + /* Memory manager */ + r = radeon_object_init(rdev); + if (r) + return r; + rdev->cp.ring_obj = NULL; + r600_ring_init(rdev, 1024 * 1024); + + if (!rdev->me_fw || !rdev->pfp_fw) { + r = r600_cp_init_microcode(rdev); + if (r) { + DRM_ERROR("Failed to load firmware!\n"); + return r; + } + } + + r = r600_resume(rdev); + if (r) { + if (rdev->flags & RADEON_IS_AGP) { + /* Retry with disabling AGP */ + r600_fini(rdev); + rdev->flags &= ~RADEON_IS_AGP; + return r600_init(rdev); + } + return r; + } + r = radeon_ib_pool_init(rdev); + if (r) { + DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); + return r; + } + r = r600_blit_init(rdev); + if (r) { + DRM_ERROR("radeon: failled blitter (%d).\n", r); + return r; + } + r = radeon_ib_test(rdev); + if (r) { + DRM_ERROR("radeon: failled testing IB (%d).\n", r); + return r; + } + return 0; +} + +void r600_fini(struct radeon_device *rdev) +{ + /* Suspend operations */ + r600_suspend(rdev); + + r600_blit_fini(rdev); + radeon_ring_fini(rdev); + r600_pcie_gart_disable(rdev); + radeon_gart_table_vram_free(rdev); + radeon_gart_fini(rdev); + radeon_gem_fini(rdev); + radeon_fence_driver_fini(rdev); + radeon_clocks_fini(rdev); +#if __OS_HAS_AGP + if (rdev->flags & RADEON_IS_AGP) + radeon_agp_fini(rdev); +#endif + radeon_object_fini(rdev); + if (rdev->is_atom_bios) + radeon_atombios_fini(rdev); + else + radeon_combios_fini(rdev); + kfree(rdev->bios); + rdev->bios = NULL; + radeon_dummy_page_fini(rdev); +} + + +/* + * CS stuff + */ +void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) +{ + /* FIXME: implement */ + radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); + radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); + radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); + radeon_ring_write(rdev, ib->length_dw); +} + +int r600_ib_test(struct radeon_device *rdev) +{ + struct radeon_ib *ib; + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = radeon_scratch_get(rdev, &scratch); + if (r) { + DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = radeon_ib_get(rdev, &ib); + if (r) { + DRM_ERROR("radeon: failed to get ib (%d).\n", r); + return r; + } + ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); + ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); + ib->ptr[2] = 0xDEADBEEF; + ib->ptr[3] = PACKET2(0); + ib->ptr[4] = PACKET2(0); + ib->ptr[5] = PACKET2(0); + ib->ptr[6] = PACKET2(0); + ib->ptr[7] = PACKET2(0); + ib->ptr[8] = PACKET2(0); + ib->ptr[9] = PACKET2(0); + ib->ptr[10] = PACKET2(0); + ib->ptr[11] = PACKET2(0); + ib->ptr[12] = PACKET2(0); + ib->ptr[13] = PACKET2(0); + ib->ptr[14] = PACKET2(0); + ib->ptr[15] = PACKET2(0); + ib->length_dw = 16; + r = radeon_ib_schedule(rdev, ib); + if (r) { + radeon_scratch_free(rdev, scratch); + radeon_ib_free(rdev, &ib); + DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); + return r; + } + r = radeon_fence_wait(ib->fence, false); + if (r) { + DRM_ERROR("radeon: fence wait failed (%d).\n", r); + return r; + } + for (i = 0; i < rdev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i < rdev->usec_timeout) { + DRM_INFO("ib test succeeded in %u usecs\n", i); + } else { + DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } + radeon_scratch_free(rdev, scratch); + radeon_ib_free(rdev, &ib); return r; } -void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) + + + +/* + * Debugfs info + */ +#if defined(CONFIG_DEBUG_FS) + +static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) { - WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); - (void)RREG32(R600_PCIE_PORT_INDEX); - WREG32(R600_PCIE_PORT_DATA, (v)); - (void)RREG32(R600_PCIE_PORT_DATA); + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct radeon_device *rdev = dev->dev_private; + uint32_t rdp, wdp; + unsigned count, i, j; + + radeon_ring_free_size(rdev); + rdp = RREG32(CP_RB_RPTR); + wdp = RREG32(CP_RB_WPTR); + count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; + seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); + seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); + seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); + seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); + seq_printf(m, "%u dwords in ring\n", count); + for (j = 0; j <= count; j++) { + i = (rdp + j) & rdev->cp.ptr_mask; + seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); + } + return 0; +} + +static int r600_debugfs_mc_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct radeon_device *rdev = dev->dev_private; + + DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); + DREG32_SYS(m, rdev, VM_L2_STATUS); + return 0; +} + +static struct drm_info_list r600_mc_info_list[] = { + {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, + {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL}, +}; +#endif + +int r600_debugfs_mc_info_init(struct radeon_device *rdev) +{ +#if defined(CONFIG_DEBUG_FS) + return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); +#else + return 0; +#endif } diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c new file mode 100644 index 0000000..c51402e --- /dev/null +++ b/drivers/gpu/drm/radeon/r600_blit.c @@ -0,0 +1,855 @@ +/* + * Copyright 2009 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Alex Deucher + */ +#include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" +#include "radeon_drv.h" + +#include "r600_blit_shaders.h" + +#define DI_PT_RECTLIST 0x11 +#define DI_INDEX_SIZE_16_BIT 0x0 +#define DI_SRC_SEL_AUTO_INDEX 0x2 + +#define FMT_8 0x1 +#define FMT_5_6_5 0x8 +#define FMT_8_8_8_8 0x1a +#define COLOR_8 0x1 +#define COLOR_5_6_5 0x8 +#define COLOR_8_8_8_8 0x1a + +static inline void +set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr) +{ + u32 cb_color_info; + int pitch, slice; + RING_LOCALS; + DRM_DEBUG("\n"); + + h = (h + 7) & ~7; + if (h < 8) + h = 8; + + cb_color_info = ((format << 2) | (1 << 27)); + pitch = (w / 8) - 1; + slice = ((w * h) / 64) - 1; + + if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) && + ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) { + BEGIN_RING(21 + 2); + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(gpu_addr >> 8); + OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); + OUT_RING(2 << 0); + } else { + BEGIN_RING(21); + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(gpu_addr >> 8); + } + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING((pitch << 0) | (slice << 10)); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(0); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(cb_color_info); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(0); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(0); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(0); + + ADVANCE_RING(); +} + +static inline void +cp_set_surface_sync(drm_radeon_private_t *dev_priv, + u32 sync_type, u32 size, u64 mc_addr) +{ + u32 cp_coher_size; + RING_LOCALS; + DRM_DEBUG("\n"); + + if (size == 0xffffffff) + cp_coher_size = 0xffffffff; + else + cp_coher_size = ((size + 255) >> 8); + + BEGIN_RING(5); + OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3)); + OUT_RING(sync_type); + OUT_RING(cp_coher_size); + OUT_RING((mc_addr >> 8)); + OUT_RING(10); /* poll interval */ + ADVANCE_RING(); +} + +static inline void +set_shaders(struct drm_device *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + u64 gpu_addr; + int shader_size, i; + u32 *vs, *ps; + uint32_t sq_pgm_resources; + RING_LOCALS; + DRM_DEBUG("\n"); + + /* load shaders */ + vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset); + ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256); + + shader_size = r6xx_vs_size; + for (i = 0; i < shader_size; i++) + vs[i] = r6xx_vs[i]; + shader_size = r6xx_ps_size; + for (i = 0; i < shader_size; i++) + ps[i] = r6xx_ps[i]; + + dev_priv->blit_vb->used = 512; + + gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset; + + /* setup shader regs */ + sq_pgm_resources = (1 << 0); + + BEGIN_RING(9 + 12); + /* VS */ + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(gpu_addr >> 8); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(sq_pgm_resources); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(0); + + /* PS */ + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING((gpu_addr + 256) >> 8); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(sq_pgm_resources | (1 << 28)); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(2); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); + OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING(0); + ADVANCE_RING(); + + cp_set_surface_sync(dev_priv, + R600_SH_ACTION_ENA, 512, gpu_addr); +} + +static inline void +set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr) +{ + uint32_t sq_vtx_constant_word2; + RING_LOCALS; + DRM_DEBUG("\n"); + + sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8)); + + BEGIN_RING(9); + OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + OUT_RING(0x460); + OUT_RING(gpu_addr & 0xffffffff); + OUT_RING(48 - 1); + OUT_RING(sq_vtx_constant_word2); + OUT_RING(1 << 0); + OUT_RING(0); + OUT_RING(0); + OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30); + ADVANCE_RING(); + + if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) + cp_set_surface_sync(dev_priv, + R600_TC_ACTION_ENA, 48, gpu_addr); + else + cp_set_surface_sync(dev_priv, + R600_VC_ACTION_ENA, 48, gpu_addr); +} + +static inline void +set_tex_resource(drm_radeon_private_t *dev_priv, + int format, int w, int h, int pitch, u64 gpu_addr) +{ + uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; + RING_LOCALS; + DRM_DEBUG("\n"); + + if (h < 1) + h = 1; + + sq_tex_resource_word0 = (1 << 0); + sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | + ((w - 1) << 19)); + + sq_tex_resource_word1 = (format << 26); + sq_tex_resource_word1 |= ((h - 1) << 0); + + sq_tex_resource_word4 = ((1 << 14) | + (0 << 16) | + (1 << 19) | + (2 << 22) | + (3 << 25)); + + BEGIN_RING(9); + OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + OUT_RING(0); + OUT_RING(sq_tex_resource_word0); + OUT_RING(sq_tex_resource_word1); + OUT_RING(gpu_addr >> 8); + OUT_RING(gpu_addr >> 8); + OUT_RING(sq_tex_resource_word4); + OUT_RING(0); + OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30); + ADVANCE_RING(); + +} + +static inline void +set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2) +{ + RING_LOCALS; + DRM_DEBUG("\n"); + + BEGIN_RING(12); + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); + OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING((x1 << 0) | (y1 << 16)); + OUT_RING((x2 << 0) | (y2 << 16)); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); + OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); + OUT_RING((x2 << 0) | (y2 << 16)); + + OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); + OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); + OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); + OUT_RING((x2 << 0) | (y2 << 16)); + ADVANCE_RING(); +} + +static inline void +draw_auto(drm_radeon_private_t *dev_priv) +{ + RING_LOCALS; + DRM_DEBUG("\n"); + + BEGIN_RING(10); + OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2); + OUT_RING(DI_PT_RECTLIST); + + OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); + OUT_RING(DI_INDEX_SIZE_16_BIT); + + OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); + OUT_RING(1); + + OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1)); + OUT_RING(3); + OUT_RING(DI_SRC_SEL_AUTO_INDEX); + + ADVANCE_RING(); + COMMIT_RING(); +} + +static inline void +set_default_state(drm_radeon_private_t *dev_priv) +{ + int default_state_dw, i; + u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; + u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; + int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; + int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; + int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; + RING_LOCALS; + + switch ((dev_priv->flags & RADEON_FAMILY_MASK)) { + case CHIP_R600: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV630: + case CHIP_RV635: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 144; + num_vs_threads = 40; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV610: + case CHIP_RV620: + case CHIP_RS780: + case CHIP_RS880: + default: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV670: + num_ps_gprs = 144; + num_vs_gprs = 40; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV770: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 188; + num_vs_threads = 60; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 256; + num_vs_stack_entries = 256; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV730: + case CHIP_RV740: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 188; + num_vs_threads = 60; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV710: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 144; + num_vs_threads = 48; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + } + + if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) + sq_config = 0; + else + sq_config = R600_VC_ENABLE; + + sq_config |= (R600_DX9_CONSTS | + R600_ALU_INST_PREFER_VECTOR | + R600_PS_PRIO(0) | + R600_VS_PRIO(1) | + R600_GS_PRIO(2) | + R600_ES_PRIO(3)); + + sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) | + R600_NUM_VS_GPRS(num_vs_gprs) | + R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); + sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(num_gs_gprs) | + R600_NUM_ES_GPRS(num_es_gprs)); + sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(num_ps_threads) | + R600_NUM_VS_THREADS(num_vs_threads) | + R600_NUM_GS_THREADS(num_gs_threads) | + R600_NUM_ES_THREADS(num_es_threads)); + sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | + R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); + sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | + R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries)); + + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { + default_state_dw = r7xx_default_size * 4; + BEGIN_RING(default_state_dw + 10); + for (i = 0; i < default_state_dw; i++) + OUT_RING(r7xx_default_state[i]); + } else { + default_state_dw = r6xx_default_size * 4; + BEGIN_RING(default_state_dw + 10); + for (i = 0; i < default_state_dw; i++) + OUT_RING(r6xx_default_state[i]); + } + OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); + OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); + /* SQ config */ + OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6)); + OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2); + OUT_RING(sq_config); + OUT_RING(sq_gpr_resource_mgmt_1); + OUT_RING(sq_gpr_resource_mgmt_2); + OUT_RING(sq_thread_resource_mgmt); + OUT_RING(sq_stack_resource_mgmt_1); + OUT_RING(sq_stack_resource_mgmt_2); + ADVANCE_RING(); +} + +static inline uint32_t i2f(uint32_t input) +{ + u32 result, i, exponent, fraction; + + if ((input & 0x3fff) == 0) + result = 0; /* 0 is a special case */ + else { + exponent = 140; /* exponent biased by 127; */ + fraction = (input & 0x3fff) << 10; /* cheat and only + handle numbers below 2^^15 */ + for (i = 0; i < 14; i++) { + if (fraction & 0x800000) + break; + else { + fraction = fraction << 1; /* keep + shifting left until top bit = 1 */ + exponent = exponent - 1; + } + } + result = exponent << 23 | (fraction & 0x7fffff); /* mask + off top bit; assumed 1 */ + } + return result; +} + + +int r600_nomm_get_vb(struct drm_device *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + dev_priv->blit_vb = radeon_freelist_get(dev); + if (!dev_priv->blit_vb) { + DRM_ERROR("Unable to allocate vertex buffer for blit\n"); + return -EAGAIN; + } + return 0; +} + +void r600_nomm_put_vb(struct drm_device *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + + dev_priv->blit_vb->used = 0; + radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb); +} + +void *r600_nomm_get_vb_ptr(struct drm_device *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + return (((char *)dev->agp_buffer_map->handle + + dev_priv->blit_vb->offset + dev_priv->blit_vb->used)); +} + +int +r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + DRM_DEBUG("\n"); + + r600_nomm_get_vb(dev); + + dev_priv->blit_vb->file_priv = file_priv; + + set_default_state(dev_priv); + set_shaders(dev); + + return 0; +} + + +void +r600_done_blit_copy(struct drm_device *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + DRM_DEBUG("\n"); + + BEGIN_RING(5); + OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); + OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); + /* wait for 3D idle clean */ + OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); + OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); + OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); + + ADVANCE_RING(); + COMMIT_RING(); + + r600_nomm_put_vb(dev); +} + +void +r600_blit_copy(struct drm_device *dev, + uint64_t src_gpu_addr, uint64_t dst_gpu_addr, + int size_bytes) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + int max_bytes; + u64 vb_addr; + u32 *vb; + + vb = r600_nomm_get_vb_ptr(dev); + + if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { + max_bytes = 8192; + + while (size_bytes) { + int cur_size = size_bytes; + int src_x = src_gpu_addr & 255; + int dst_x = dst_gpu_addr & 255; + int h = 1; + src_gpu_addr = src_gpu_addr & ~255; + dst_gpu_addr = dst_gpu_addr & ~255; + + if (!src_x && !dst_x) { + h = (cur_size / max_bytes); + if (h > 8192) + h = 8192; + if (h == 0) + h = 1; + else + cur_size = max_bytes; + } else { + if (cur_size > max_bytes) + cur_size = max_bytes; + if (cur_size > (max_bytes - dst_x)) + cur_size = (max_bytes - dst_x); + if (cur_size > (max_bytes - src_x)) + cur_size = (max_bytes - src_x); + } + + if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { + + r600_nomm_put_vb(dev); + r600_nomm_get_vb(dev); + if (!dev_priv->blit_vb) + return; + set_shaders(dev); + vb = r600_nomm_get_vb_ptr(dev); + } + + vb[0] = i2f(dst_x); + vb[1] = 0; + vb[2] = i2f(src_x); + vb[3] = 0; + + vb[4] = i2f(dst_x); + vb[5] = i2f(h); + vb[6] = i2f(src_x); + vb[7] = i2f(h); + + vb[8] = i2f(dst_x + cur_size); + vb[9] = i2f(h); + vb[10] = i2f(src_x + cur_size); + vb[11] = i2f(h); + + /* src */ + set_tex_resource(dev_priv, FMT_8, + src_x + cur_size, h, src_x + cur_size, + src_gpu_addr); + + cp_set_surface_sync(dev_priv, + R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); + + /* dst */ + set_render_target(dev_priv, COLOR_8, + dst_x + cur_size, h, + dst_gpu_addr); + + /* scissors */ + set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h); + + /* Vertex buffer setup */ + vb_addr = dev_priv->gart_buffers_offset + + dev_priv->blit_vb->offset + + dev_priv->blit_vb->used; + set_vtx_resource(dev_priv, vb_addr); + + /* draw */ + draw_auto(dev_priv); + + cp_set_surface_sync(dev_priv, + R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA, + cur_size * h, dst_gpu_addr); + + vb += 12; + dev_priv->blit_vb->used += 12 * 4; + + src_gpu_addr += cur_size * h; + dst_gpu_addr += cur_size * h; + size_bytes -= cur_size * h; + } + } else { + max_bytes = 8192 * 4; + + while (size_bytes) { + int cur_size = size_bytes; + int src_x = (src_gpu_addr & 255); + int dst_x = (dst_gpu_addr & 255); + int h = 1; + src_gpu_addr = src_gpu_addr & ~255; + dst_gpu_addr = dst_gpu_addr & ~255; + + if (!src_x && !dst_x) { + h = (cur_size / max_bytes); + if (h > 8192) + h = 8192; + if (h == 0) + h = 1; + else + cur_size = max_bytes; + } else { + if (cur_size > max_bytes) + cur_size = max_bytes; + if (cur_size > (max_bytes - dst_x)) + cur_size = (max_bytes - dst_x); + if (cur_size > (max_bytes - src_x)) + cur_size = (max_bytes - src_x); + } + + if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { + r600_nomm_put_vb(dev); + r600_nomm_get_vb(dev); + if (!dev_priv->blit_vb) + return; + + set_shaders(dev); + vb = r600_nomm_get_vb_ptr(dev); + } + + vb[0] = i2f(dst_x / 4); + vb[1] = 0; + vb[2] = i2f(src_x / 4); + vb[3] = 0; + + vb[4] = i2f(dst_x / 4); + vb[5] = i2f(h); + vb[6] = i2f(src_x / 4); + vb[7] = i2f(h); + + vb[8] = i2f((dst_x + cur_size) / 4); + vb[9] = i2f(h); + vb[10] = i2f((src_x + cur_size) / 4); + vb[11] = i2f(h); + + /* src */ + set_tex_resource(dev_priv, FMT_8_8_8_8, + (src_x + cur_size) / 4, + h, (src_x + cur_size) / 4, + src_gpu_addr); + + cp_set_surface_sync(dev_priv, + R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); + + /* dst */ + set_render_target(dev_priv, COLOR_8_8_8_8, + dst_x + cur_size, h, + dst_gpu_addr); + + /* scissors */ + set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h); + + /* Vertex buffer setup */ + vb_addr = dev_priv->gart_buffers_offset + + dev_priv->blit_vb->offset + + dev_priv->blit_vb->used; + set_vtx_resource(dev_priv, vb_addr); + + /* draw */ + draw_auto(dev_priv); + + cp_set_surface_sync(dev_priv, + R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA, + cur_size * h, dst_gpu_addr); + + vb += 12; + dev_priv->blit_vb->used += 12 * 4; + + src_gpu_addr += cur_size * h; + dst_gpu_addr += cur_size * h; + size_bytes -= cur_size * h; + } + } +} + +void +r600_blit_swap(struct drm_device *dev, + uint64_t src_gpu_addr, uint64_t dst_gpu_addr, + int sx, int sy, int dx, int dy, + int w, int h, int src_pitch, int dst_pitch, int cpp) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + int cb_format, tex_format; + u64 vb_addr; + u32 *vb; + + vb = (u32 *) ((char *)dev->agp_buffer_map->handle + + dev_priv->blit_vb->offset + dev_priv->blit_vb->used); + + if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { + + r600_nomm_put_vb(dev); + r600_nomm_get_vb(dev); + if (!dev_priv->blit_vb) + return; + + set_shaders(dev); + vb = r600_nomm_get_vb_ptr(dev); + } + + if (cpp == 4) { + cb_format = COLOR_8_8_8_8; + tex_format = FMT_8_8_8_8; + } else if (cpp == 2) { + cb_format = COLOR_5_6_5; + tex_format = FMT_5_6_5; + } else { + cb_format = COLOR_8; + tex_format = FMT_8; + } + + vb[0] = i2f(dx); + vb[1] = i2f(dy); + vb[2] = i2f(sx); + vb[3] = i2f(sy); + + vb[4] = i2f(dx); + vb[5] = i2f(dy + h); + vb[6] = i2f(sx); + vb[7] = i2f(sy + h); + + vb[8] = i2f(dx + w); + vb[9] = i2f(dy + h); + vb[10] = i2f(sx + w); + vb[11] = i2f(sy + h); + + /* src */ + set_tex_resource(dev_priv, tex_format, + src_pitch / cpp, + sy + h, src_pitch / cpp, + src_gpu_addr); + + cp_set_surface_sync(dev_priv, + R600_TC_ACTION_ENA, (src_pitch * (sy + h)), src_gpu_addr); + + /* dst */ + set_render_target(dev_priv, cb_format, + dst_pitch / cpp, dy + h, + dst_gpu_addr); + + /* scissors */ + set_scissors(dev_priv, dx, dy, dx + w, dy + h); + + /* Vertex buffer setup */ + vb_addr = dev_priv->gart_buffers_offset + + dev_priv->blit_vb->offset + + dev_priv->blit_vb->used; + set_vtx_resource(dev_priv, vb_addr); + + /* draw */ + draw_auto(dev_priv); + + cp_set_surface_sync(dev_priv, + R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA, + dst_pitch * (dy + h), dst_gpu_addr); + + dev_priv->blit_vb->used += 12 * 4; +} diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c new file mode 100644 index 0000000..5755647 --- /dev/null +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c @@ -0,0 +1,777 @@ +#include "drmP.h" +#include "drm.h" +#include "radeon_drm.h" +#include "radeon.h" + +#include "r600d.h" +#include "r600_blit_shaders.h" + +#define DI_PT_RECTLIST 0x11 +#define DI_INDEX_SIZE_16_BIT 0x0 +#define DI_SRC_SEL_AUTO_INDEX 0x2 + +#define FMT_8 0x1 +#define FMT_5_6_5 0x8 +#define FMT_8_8_8_8 0x1a +#define COLOR_8 0x1 +#define COLOR_5_6_5 0x8 +#define COLOR_8_8_8_8 0x1a + +/* emits 21 on rv770+, 23 on r600 */ +static void +set_render_target(struct radeon_device *rdev, int format, + int w, int h, u64 gpu_addr) +{ + u32 cb_color_info; + int pitch, slice; + + h = (h + 7) & ~7; + if (h < 8) + h = 8; + + cb_color_info = ((format << 2) | (1 << 27)); + pitch = (w / 8) - 1; + slice = ((w * h) / 64) - 1; + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, gpu_addr >> 8); + + if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { + radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); + radeon_ring_write(rdev, 2 << 0); + } + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 0); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, cb_color_info); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 0); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 0); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 0); +} + +/* emits 5dw */ +static void +cp_set_surface_sync(struct radeon_device *rdev, + u32 sync_type, u32 size, + u64 mc_addr) +{ + u32 cp_coher_size; + + if (size == 0xffffffff) + cp_coher_size = 0xffffffff; + else + cp_coher_size = ((size + 255) >> 8); + + radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); + radeon_ring_write(rdev, sync_type); + radeon_ring_write(rdev, cp_coher_size); + radeon_ring_write(rdev, mc_addr >> 8); + radeon_ring_write(rdev, 10); /* poll interval */ +} + +/* emits 21dw + 1 surface sync = 26dw */ +static void +set_shaders(struct radeon_device *rdev) +{ + u64 gpu_addr; + u32 sq_pgm_resources; + + /* setup shader regs */ + sq_pgm_resources = (1 << 0); + + /* VS */ + gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, gpu_addr >> 8); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, sq_pgm_resources); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 0); + + /* PS */ + gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, gpu_addr >> 8); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 2); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, 0); + + cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); +} + +/* emits 9 + 1 sync (5) = 14*/ +static void +set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) +{ + u32 sq_vtx_constant_word2; + + sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); + radeon_ring_write(rdev, 0x460); + radeon_ring_write(rdev, gpu_addr & 0xffffffff); + radeon_ring_write(rdev, 48 - 1); + radeon_ring_write(rdev, sq_vtx_constant_word2); + radeon_ring_write(rdev, 1 << 0); + radeon_ring_write(rdev, 0); + radeon_ring_write(rdev, 0); + radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); + + if ((rdev->family == CHIP_RV610) || + (rdev->family == CHIP_RV620) || + (rdev->family == CHIP_RS780) || + (rdev->family == CHIP_RS880) || + (rdev->family == CHIP_RV710)) + cp_set_surface_sync(rdev, + PACKET3_TC_ACTION_ENA, 48, gpu_addr); + else + cp_set_surface_sync(rdev, + PACKET3_VC_ACTION_ENA, 48, gpu_addr); +} + +/* emits 9 */ +static void +set_tex_resource(struct radeon_device *rdev, + int format, int w, int h, int pitch, + u64 gpu_addr) +{ + uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; + + if (h < 1) + h = 1; + + sq_tex_resource_word0 = (1 << 0); + sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | + ((w - 1) << 19)); + + sq_tex_resource_word1 = (format << 26); + sq_tex_resource_word1 |= ((h - 1) << 0); + + sq_tex_resource_word4 = ((1 << 14) | + (0 << 16) | + (1 << 19) | + (2 << 22) | + (3 << 25)); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); + radeon_ring_write(rdev, 0); + radeon_ring_write(rdev, sq_tex_resource_word0); + radeon_ring_write(rdev, sq_tex_resource_word1); + radeon_ring_write(rdev, gpu_addr >> 8); + radeon_ring_write(rdev, gpu_addr >> 8); + radeon_ring_write(rdev, sq_tex_resource_word4); + radeon_ring_write(rdev, 0); + radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30); +} + +/* emits 12 */ +static void +set_scissors(struct radeon_device *rdev, int x1, int y1, + int x2, int y2) +{ + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); + radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); + radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); + + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); + radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); +} + +/* emits 10 */ +static void +draw_auto(struct radeon_device *rdev) +{ + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); + radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); + radeon_ring_write(rdev, DI_PT_RECTLIST); + + radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); + radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT); + + radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); + radeon_ring_write(rdev, 1); + + radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); + radeon_ring_write(rdev, 3); + radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); + +} + +/* emits 14 */ +static void +set_default_state(struct radeon_device *rdev) +{ + u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; + u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; + int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; + int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; + int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; + u64 gpu_addr; + + switch (rdev->family) { + case CHIP_R600: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV630: + case CHIP_RV635: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 144; + num_vs_threads = 40; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV610: + case CHIP_RV620: + case CHIP_RS780: + case CHIP_RS880: + default: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV670: + num_ps_gprs = 144; + num_vs_gprs = 40; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 136; + num_vs_threads = 48; + num_gs_threads = 4; + num_es_threads = 4; + num_ps_stack_entries = 40; + num_vs_stack_entries = 40; + num_gs_stack_entries = 32; + num_es_stack_entries = 16; + break; + case CHIP_RV770: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 188; + num_vs_threads = 60; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 256; + num_vs_stack_entries = 256; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV730: + case CHIP_RV740: + num_ps_gprs = 84; + num_vs_gprs = 36; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 188; + num_vs_threads = 60; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + case CHIP_RV710: + num_ps_gprs = 192; + num_vs_gprs = 56; + num_temp_gprs = 4; + num_gs_gprs = 0; + num_es_gprs = 0; + num_ps_threads = 144; + num_vs_threads = 48; + num_gs_threads = 0; + num_es_threads = 0; + num_ps_stack_entries = 128; + num_vs_stack_entries = 128; + num_gs_stack_entries = 0; + num_es_stack_entries = 0; + break; + } + + if ((rdev->family == CHIP_RV610) || + (rdev->family == CHIP_RV620) || + (rdev->family == CHIP_RS780) || + (rdev->family == CHIP_RS780) || + (rdev->family == CHIP_RV710)) + sq_config = 0; + else + sq_config = VC_ENABLE; + + sq_config |= (DX9_CONSTS | + ALU_INST_PREFER_VECTOR | + PS_PRIO(0) | + VS_PRIO(1) | + GS_PRIO(2) | + ES_PRIO(3)); + + sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | + NUM_VS_GPRS(num_vs_gprs) | + NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); + sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | + NUM_ES_GPRS(num_es_gprs)); + sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | + NUM_VS_THREADS(num_vs_threads) | + NUM_GS_THREADS(num_gs_threads) | + NUM_ES_THREADS(num_es_threads)); + sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | + NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); + sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | + NUM_ES_STACK_ENTRIES(num_es_stack_entries)); + + /* emit an IB pointing at default state */ + gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; + radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); + radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); + radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); + radeon_ring_write(rdev, (rdev->r600_blit.state_len / 4)); + + radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); + radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); + /* SQ config */ + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); + radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); + radeon_ring_write(rdev, sq_config); + radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); + radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); + radeon_ring_write(rdev, sq_thread_resource_mgmt); + radeon_ring_write(rdev, sq_stack_resource_mgmt_1); + radeon_ring_write(rdev, sq_stack_resource_mgmt_2); +} + +static inline uint32_t i2f(uint32_t input) +{ + u32 result, i, exponent, fraction; + + if ((input & 0x3fff) == 0) + result = 0; /* 0 is a special case */ + else { + exponent = 140; /* exponent biased by 127; */ + fraction = (input & 0x3fff) << 10; /* cheat and only + handle numbers below 2^^15 */ + for (i = 0; i < 14; i++) { + if (fraction & 0x800000) + break; + else { + fraction = fraction << 1; /* keep + shifting left until top bit = 1 */ + exponent = exponent - 1; + } + } + result = exponent << 23 | (fraction & 0x7fffff); /* mask + off top bit; assumed 1 */ + } + return result; +} + +int r600_blit_init(struct radeon_device *rdev) +{ + u32 obj_size; + int r; + void *ptr; + + rdev->r600_blit.state_offset = 0; + + if (rdev->family >= CHIP_RV770) + rdev->r600_blit.state_len = r7xx_default_size * 4; + else + rdev->r600_blit.state_len = r6xx_default_size * 4; + + obj_size = rdev->r600_blit.state_len; + obj_size = ALIGN(obj_size, 256); + + rdev->r600_blit.vs_offset = obj_size; + obj_size += r6xx_vs_size * 4; + obj_size = ALIGN(obj_size, 256); + + rdev->r600_blit.ps_offset = obj_size; + obj_size += r6xx_ps_size * 4; + obj_size = ALIGN(obj_size, 256); + + r = radeon_object_create(rdev, NULL, obj_size, + true, RADEON_GEM_DOMAIN_VRAM, + false, &rdev->r600_blit.shader_obj); + if (r) { + DRM_ERROR("r600 failed to allocate shader\n"); + return r; + } + + r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, + &rdev->r600_blit.shader_gpu_addr); + if (r) { + DRM_ERROR("failed to pin blit object %d\n", r); + return r; + } + + DRM_DEBUG("r6xx blit allocated bo @ 0x%16llx %08x vs %08x ps %08x\n", + rdev->r600_blit.shader_gpu_addr, obj_size, + rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); + + r = radeon_object_kmap(rdev->r600_blit.shader_obj, &ptr); + if (r) { + DRM_ERROR("failed to map blit object %d\n", r); + return r; + } + + if (rdev->family >= CHIP_RV770) + memcpy_toio(ptr + rdev->r600_blit.state_offset, r7xx_default_state, rdev->r600_blit.state_len); + else + memcpy_toio(ptr + rdev->r600_blit.state_offset, r6xx_default_state, rdev->r600_blit.state_len); + + memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4); + memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); + + radeon_object_kunmap(rdev->r600_blit.shader_obj); + return 0; +} + +void r600_blit_fini(struct radeon_device *rdev) +{ + radeon_object_unpin(rdev->r600_blit.shader_obj); + radeon_object_unref(&rdev->r600_blit.shader_obj); +} + +int r600_vb_ib_get(struct radeon_device *rdev) +{ + int r; + r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib); + if (r) { + DRM_ERROR("failed to get IB for vertex buffer\n"); + return r; + } + + rdev->r600_blit.vb_total = 64*1024; + rdev->r600_blit.vb_used = 0; + return 0; +} + +void r600_vb_ib_put(struct radeon_device *rdev) +{ + mutex_lock(&rdev->ib_pool.mutex); + radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence); + list_add_tail(&rdev->r600_blit.vb_ib->list, &rdev->ib_pool.scheduled_ibs); + mutex_unlock(&rdev->ib_pool.mutex); + radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); +} + +int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) +{ + int r; + int ring_size; + const int max_size = 8192*8192; + + r = r600_vb_ib_get(rdev); + WARN_ON(r); + + /* loops of emits 64 + fence emit possible */ + ring_size = ((size_bytes + max_size) / max_size) * 78; + /* set default + shaders */ + ring_size += 40; /* shaders + def state */ + ring_size += 3; /* fence emit for VB IB */ + ring_size += 5; /* done copy */ + ring_size += 3; /* fence emit for done copy */ + r = radeon_ring_lock(rdev, ring_size); + WARN_ON(r); + + set_default_state(rdev); /* 14 */ + set_shaders(rdev); /* 26 */ + return 0; +} + +void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) +{ + int r; + + radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); + radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); + /* wait for 3D idle clean */ + radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); + radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); + radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); + + if (rdev->r600_blit.vb_ib) + r600_vb_ib_put(rdev); + + if (fence) + r = radeon_fence_emit(rdev, fence); + + radeon_ring_unlock_commit(rdev); +} + +void r600_kms_blit_copy(struct radeon_device *rdev, + u64 src_gpu_addr, u64 dst_gpu_addr, + int size_bytes) +{ + int max_bytes; + u64 vb_gpu_addr; + u32 *vb; + + DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr, + size_bytes, rdev->r600_blit.vb_used); + vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used); + if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { + max_bytes = 8192; + + while (size_bytes) { + int cur_size = size_bytes; + int src_x = src_gpu_addr & 255; + int dst_x = dst_gpu_addr & 255; + int h = 1; + src_gpu_addr = src_gpu_addr & ~255; + dst_gpu_addr = dst_gpu_addr & ~255; + + if (!src_x && !dst_x) { + h = (cur_size / max_bytes); + if (h > 8192) + h = 8192; + if (h == 0) + h = 1; + else + cur_size = max_bytes; + } else { + if (cur_size > max_bytes) + cur_size = max_bytes; + if (cur_size > (max_bytes - dst_x)) + cur_size = (max_bytes - dst_x); + if (cur_size > (max_bytes - src_x)) + cur_size = (max_bytes - src_x); + } + + if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { + WARN_ON(1); + +#if 0 + r600_vb_ib_put(rdev); + + r600_nomm_put_vb(dev); + r600_nomm_get_vb(dev); + if (!dev_priv->blit_vb) + return; + set_shaders(dev); + vb = r600_nomm_get_vb_ptr(dev); +#endif + } + + vb[0] = i2f(dst_x); + vb[1] = 0; + vb[2] = i2f(src_x); + vb[3] = 0; + + vb[4] = i2f(dst_x); + vb[5] = i2f(h); + vb[6] = i2f(src_x); + vb[7] = i2f(h); + + vb[8] = i2f(dst_x + cur_size); + vb[9] = i2f(h); + vb[10] = i2f(src_x + cur_size); + vb[11] = i2f(h); + + /* src 9 */ + set_tex_resource(rdev, FMT_8, + src_x + cur_size, h, src_x + cur_size, + src_gpu_addr); + + /* 5 */ + cp_set_surface_sync(rdev, + PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); + + /* dst 23 */ + set_render_target(rdev, COLOR_8, + dst_x + cur_size, h, + dst_gpu_addr); + + /* scissors 12 */ + set_scissors(rdev, dst_x, 0, dst_x + cur_size, h); + + /* 14 */ + vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; + set_vtx_resource(rdev, vb_gpu_addr); + + /* draw 10 */ + draw_auto(rdev); + + /* 5 */ + cp_set_surface_sync(rdev, + PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, + cur_size * h, dst_gpu_addr); + + vb += 12; + rdev->r600_blit.vb_used += 12 * 4; + + src_gpu_addr += cur_size * h; + dst_gpu_addr += cur_size * h; + size_bytes -= cur_size * h; + } + } else { + max_bytes = 8192 * 4; + + while (size_bytes) { + int cur_size = size_bytes; + int src_x = (src_gpu_addr & 255); + int dst_x = (dst_gpu_addr & 255); + int h = 1; + src_gpu_addr = src_gpu_addr & ~255; + dst_gpu_addr = dst_gpu_addr & ~255; + + if (!src_x && !dst_x) { + h = (cur_size / max_bytes); + if (h > 8192) + h = 8192; + if (h == 0) + h = 1; + else + cur_size = max_bytes; + } else { + if (cur_size > max_bytes) + cur_size = max_bytes; + if (cur_size > (max_bytes - dst_x)) + cur_size = (max_bytes - dst_x); + if (cur_size > (max_bytes - src_x)) + cur_size = (max_bytes - src_x); + } + + if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { + WARN_ON(1); + } +#if 0 + if ((rdev->blit_vb->used + 48) > rdev->blit_vb->total) { + r600_nomm_put_vb(dev); + r600_nomm_get_vb(dev); + if (!rdev->blit_vb) + return; + + set_shaders(dev); + vb = r600_nomm_get_vb_ptr(dev); + } +#endif + + vb[0] = i2f(dst_x / 4); + vb[1] = 0; + vb[2] = i2f(src_x / 4); + vb[3] = 0; + + vb[4] = i2f(dst_x / 4); + vb[5] = i2f(h); + vb[6] = i2f(src_x / 4); + vb[7] = i2f(h); + + vb[8] = i2f((dst_x + cur_size) / 4); + vb[9] = i2f(h); + vb[10] = i2f((src_x + cur_size) / 4); + vb[11] = i2f(h); + + /* src 9 */ + set_tex_resource(rdev, FMT_8_8_8_8, + (src_x + cur_size) / 4, + h, (src_x + cur_size) / 4, + src_gpu_addr); + /* 5 */ + cp_set_surface_sync(rdev, + PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); + + /* dst 23 */ + set_render_target(rdev, COLOR_8_8_8_8, + dst_x + cur_size, h, + dst_gpu_addr); + + /* scissors 12 */ + set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h); + + /* Vertex buffer setup 14 */ + vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; + set_vtx_resource(rdev, vb_gpu_addr); + + /* draw 10 */ + draw_auto(rdev); + + /* 5 */ + cp_set_surface_sync(rdev, + PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, + cur_size * h, dst_gpu_addr); + + /* 78 ring dwords per loop */ + vb += 12; + rdev->r600_blit.vb_used += 12 * 4; + + src_gpu_addr += cur_size * h; + dst_gpu_addr += cur_size * h; + size_bytes -= cur_size * h; + } + } +} + diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c new file mode 100644 index 0000000..d745e81 --- /dev/null +++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c @@ -0,0 +1,1072 @@ + +#include +#include + +const u32 r6xx_default_state[] = +{ + 0xc0002400, + 0x00000000, + 0xc0012800, + 0x80000000, + 0x80000000, + 0xc0004600, + 0x00000016, + 0xc0016800, + 0x00000010, + 0x00028000, + 0xc0016800, + 0x00000010, + 0x00008000, + 0xc0016800, + 0x00000542, + 0x07000003, + 0xc0016800, + 0x000005c5, + 0x00000000, + 0xc0016800, + 0x00000363, + 0x00000000, + 0xc0016800, + 0x0000060c, + 0x82000000, + 0xc0016800, + 0x0000060e, + 0x01020204, + 0xc0016f00, + 0x00000000, + 0x00000000, + 0xc0016f00, + 0x00000001, + 0x00000000, + 0xc0096900, + 0x0000022a, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x00000004, + 0x00000000, + 0xc0016900, + 0x0000000a, + 0x00000000, + 0xc0016900, + 0x0000000b, + 0x00000000, + 0xc0016900, + 0x0000010c, + 0x00000000, + 0xc0016900, + 0x0000010d, + 0x00000000, + 0xc0016900, + 0x00000200, + 0x00000000, + 0xc0016900, + 0x00000343, + 0x00000060, + 0xc0016900, + 0x00000344, + 0x00000040, + 0xc0016900, + 0x00000351, + 0x0000aa00, + 0xc0016900, + 0x00000104, + 0x00000000, + 0xc0016900, + 0x0000010e, + 0x00000000, + 0xc0046900, + 0x00000105, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0036900, + 0x00000109, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0046900, + 0x0000030c, + 0x01000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0046900, + 0x00000048, + 0x3f800000, + 0x00000000, + 0x3f800000, + 0x3f800000, + 0xc0016900, + 0x0000008e, + 0x0000000f, + 0xc0016900, + 0x00000080, + 0x00000000, + 0xc0016900, + 0x00000083, + 0x0000ffff, + 0xc0016900, + 0x00000084, + 0x00000000, + 0xc0016900, + 0x00000085, + 0x20002000, + 0xc0016900, + 0x00000086, + 0x00000000, + 0xc0016900, + 0x00000087, + 0x20002000, + 0xc0016900, + 0x00000088, + 0x00000000, + 0xc0016900, + 0x00000089, + 0x20002000, + 0xc0016900, + 0x0000008a, + 0x00000000, + 0xc0016900, + 0x0000008b, + 0x20002000, + 0xc0016900, + 0x0000008c, + 0x00000000, + 0xc0016900, + 0x00000094, + 0x80000000, + 0xc0016900, + 0x00000095, + 0x20002000, + 0xc0026900, + 0x000000b4, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x00000096, + 0x80000000, + 0xc0016900, + 0x00000097, + 0x20002000, + 0xc0026900, + 0x000000b6, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x00000098, + 0x80000000, + 0xc0016900, + 0x00000099, + 0x20002000, + 0xc0026900, + 0x000000b8, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x0000009a, + 0x80000000, + 0xc0016900, + 0x0000009b, + 0x20002000, + 0xc0026900, + 0x000000ba, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x0000009c, + 0x80000000, + 0xc0016900, + 0x0000009d, + 0x20002000, + 0xc0026900, + 0x000000bc, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x0000009e, + 0x80000000, + 0xc0016900, + 0x0000009f, + 0x20002000, + 0xc0026900, + 0x000000be, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a0, + 0x80000000, + 0xc0016900, + 0x000000a1, + 0x20002000, + 0xc0026900, + 0x000000c0, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a2, + 0x80000000, + 0xc0016900, + 0x000000a3, + 0x20002000, + 0xc0026900, + 0x000000c2, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a4, + 0x80000000, + 0xc0016900, + 0x000000a5, + 0x20002000, + 0xc0026900, + 0x000000c4, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a6, + 0x80000000, + 0xc0016900, + 0x000000a7, + 0x20002000, + 0xc0026900, + 0x000000c6, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a8, + 0x80000000, + 0xc0016900, + 0x000000a9, + 0x20002000, + 0xc0026900, + 0x000000c8, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000aa, + 0x80000000, + 0xc0016900, + 0x000000ab, + 0x20002000, + 0xc0026900, + 0x000000ca, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000ac, + 0x80000000, + 0xc0016900, + 0x000000ad, + 0x20002000, + 0xc0026900, + 0x000000cc, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000ae, + 0x80000000, + 0xc0016900, + 0x000000af, + 0x20002000, + 0xc0026900, + 0x000000ce, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000b0, + 0x80000000, + 0xc0016900, + 0x000000b1, + 0x20002000, + 0xc0026900, + 0x000000d0, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000b2, + 0x80000000, + 0xc0016900, + 0x000000b3, + 0x20002000, + 0xc0026900, + 0x000000d2, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x00000293, + 0x00004010, + 0xc0016900, + 0x00000300, + 0x00000000, + 0xc0016900, + 0x00000301, + 0x00000000, + 0xc0016900, + 0x00000312, + 0xffffffff, + 0xc0016900, + 0x00000307, + 0x00000000, + 0xc0016900, + 0x00000308, + 0x00000000, + 0xc0016900, + 0x00000283, + 0x00000000, + 0xc0016900, + 0x00000292, + 0x00000000, + 0xc0066900, + 0x0000010f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x00000206, + 0x00000000, + 0xc0016900, + 0x00000207, + 0x00000000, + 0xc0016900, + 0x00000208, + 0x00000000, + 0xc0046900, + 0x00000303, + 0x3f800000, + 0x3f800000, + 0x3f800000, + 0x3f800000, + 0xc0016900, + 0x00000205, + 0x00000004, + 0xc0016900, + 0x00000280, + 0x00000000, + 0xc0016900, + 0x00000281, + 0x00000000, + 0xc0016900, + 0x0000037e, + 0x00000000, + 0xc0016900, + 0x00000382, + 0x00000000, + 0xc0016900, + 0x00000380, + 0x00000000, + 0xc0016900, + 0x00000383, + 0x00000000, + 0xc0016900, + 0x00000381, + 0x00000000, + 0xc0016900, + 0x00000282, + 0x00000008, + 0xc0016900, + 0x00000302, + 0x0000002d, + 0xc0016900, + 0x0000037f, + 0x00000000, + 0xc0016900, + 0x000001b2, + 0x00000000, + 0xc0016900, + 0x000001b6, + 0x00000000, + 0xc0016900, + 0x000001b7, + 0x00000000, + 0xc0016900, + 0x000001b8, + 0x00000000, + 0xc0016900, + 0x000001b9, + 0x00000000, + 0xc0016900, + 0x00000225, + 0x00000000, + 0xc0016900, + 0x00000229, + 0x00000000, + 0xc0016900, + 0x00000237, + 0x00000000, + 0xc0016900, + 0x00000100, + 0x00000800, + 0xc0016900, + 0x00000101, + 0x00000000, + 0xc0016900, + 0x00000102, + 0x00000000, + 0xc0016900, + 0x000002a8, + 0x00000000, + 0xc0016900, + 0x000002a9, + 0x00000000, + 0xc0016900, + 0x00000103, + 0x00000000, + 0xc0016900, + 0x00000284, + 0x00000000, + 0xc0016900, + 0x00000290, + 0x00000000, + 0xc0016900, + 0x00000285, + 0x00000000, + 0xc0016900, + 0x00000286, + 0x00000000, + 0xc0016900, + 0x00000287, + 0x00000000, + 0xc0016900, + 0x00000288, + 0x00000000, + 0xc0016900, + 0x00000289, + 0x00000000, + 0xc0016900, + 0x0000028a, + 0x00000000, + 0xc0016900, + 0x0000028b, + 0x00000000, + 0xc0016900, + 0x0000028c, + 0x00000000, + 0xc0016900, + 0x0000028d, + 0x00000000, + 0xc0016900, + 0x0000028e, + 0x00000000, + 0xc0016900, + 0x0000028f, + 0x00000000, + 0xc0016900, + 0x000002a1, + 0x00000000, + 0xc0016900, + 0x000002a5, + 0x00000000, + 0xc0016900, + 0x000002ac, + 0x00000000, + 0xc0016900, + 0x000002ad, + 0x00000000, + 0xc0016900, + 0x000002ae, + 0x00000000, + 0xc0016900, + 0x000002c8, + 0x00000000, + 0xc0016900, + 0x00000206, + 0x00000100, + 0xc0016900, + 0x00000204, + 0x00010000, + 0xc0036e00, + 0x00000000, + 0x00000012, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x0000008f, + 0x0000000f, + 0xc0016900, + 0x000001e8, + 0x00000001, + 0xc0016900, + 0x00000202, + 0x00cc0000, + 0xc0016900, + 0x00000205, + 0x00000244, + 0xc0016900, + 0x00000203, + 0x00000210, + 0xc0016900, + 0x000001b1, + 0x00000000, + 0xc0016900, + 0x00000185, + 0x00000000, + 0xc0016900, + 0x000001b3, + 0x00000001, + 0xc0016900, + 0x000001b4, + 0x00000000, + 0xc0016900, + 0x00000191, + 0x00000b00, + 0xc0016900, + 0x000001b5, + 0x00000000, +}; + +const u32 r7xx_default_state[] = +{ + 0xc0012800, + 0x80000000, + 0x80000000, + 0xc0004600, + 0x00000016, + 0xc0016800, + 0x00000010, + 0x00028000, + 0xc0016800, + 0x00000010, + 0x00008000, + 0xc0016800, + 0x00000542, + 0x07000002, + 0xc0016800, + 0x000005c5, + 0x00000000, + 0xc0016800, + 0x00000363, + 0x00004000, + 0xc0016800, + 0x0000060c, + 0x00000000, + 0xc0016800, + 0x0000060e, + 0x00420204, + 0xc0016f00, + 0x00000000, + 0x00000000, + 0xc0016f00, + 0x00000001, + 0x00000000, + 0xc0096900, + 0x0000022a, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x00000004, + 0x00000000, + 0xc0016900, + 0x0000000a, + 0x00000000, + 0xc0016900, + 0x0000000b, + 0x00000000, + 0xc0016900, + 0x0000010c, + 0x00000000, + 0xc0016900, + 0x0000010d, + 0x00000000, + 0xc0016900, + 0x00000200, + 0x00000000, + 0xc0016900, + 0x00000343, + 0x00000060, + 0xc0016900, + 0x00000344, + 0x00000000, + 0xc0016900, + 0x00000351, + 0x0000aa00, + 0xc0016900, + 0x00000104, + 0x00000000, + 0xc0016900, + 0x0000010e, + 0x00000000, + 0xc0046900, + 0x00000105, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0046900, + 0x0000030c, + 0x01000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x0000008e, + 0x0000000f, + 0xc0016900, + 0x00000080, + 0x00000000, + 0xc0016900, + 0x00000083, + 0x0000ffff, + 0xc0016900, + 0x00000084, + 0x00000000, + 0xc0016900, + 0x00000085, + 0x20002000, + 0xc0016900, + 0x00000086, + 0x00000000, + 0xc0016900, + 0x00000087, + 0x20002000, + 0xc0016900, + 0x00000088, + 0x00000000, + 0xc0016900, + 0x00000089, + 0x20002000, + 0xc0016900, + 0x0000008a, + 0x00000000, + 0xc0016900, + 0x0000008b, + 0x20002000, + 0xc0016900, + 0x0000008c, + 0xaaaaaaaa, + 0xc0016900, + 0x00000094, + 0x80000000, + 0xc0016900, + 0x00000095, + 0x20002000, + 0xc0026900, + 0x000000b4, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x00000096, + 0x80000000, + 0xc0016900, + 0x00000097, + 0x20002000, + 0xc0026900, + 0x000000b6, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x00000098, + 0x80000000, + 0xc0016900, + 0x00000099, + 0x20002000, + 0xc0026900, + 0x000000b8, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x0000009a, + 0x80000000, + 0xc0016900, + 0x0000009b, + 0x20002000, + 0xc0026900, + 0x000000ba, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x0000009c, + 0x80000000, + 0xc0016900, + 0x0000009d, + 0x20002000, + 0xc0026900, + 0x000000bc, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x0000009e, + 0x80000000, + 0xc0016900, + 0x0000009f, + 0x20002000, + 0xc0026900, + 0x000000be, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a0, + 0x80000000, + 0xc0016900, + 0x000000a1, + 0x20002000, + 0xc0026900, + 0x000000c0, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a2, + 0x80000000, + 0xc0016900, + 0x000000a3, + 0x20002000, + 0xc0026900, + 0x000000c2, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a4, + 0x80000000, + 0xc0016900, + 0x000000a5, + 0x20002000, + 0xc0026900, + 0x000000c4, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a6, + 0x80000000, + 0xc0016900, + 0x000000a7, + 0x20002000, + 0xc0026900, + 0x000000c6, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000a8, + 0x80000000, + 0xc0016900, + 0x000000a9, + 0x20002000, + 0xc0026900, + 0x000000c8, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000aa, + 0x80000000, + 0xc0016900, + 0x000000ab, + 0x20002000, + 0xc0026900, + 0x000000ca, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000ac, + 0x80000000, + 0xc0016900, + 0x000000ad, + 0x20002000, + 0xc0026900, + 0x000000cc, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000ae, + 0x80000000, + 0xc0016900, + 0x000000af, + 0x20002000, + 0xc0026900, + 0x000000ce, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000b0, + 0x80000000, + 0xc0016900, + 0x000000b1, + 0x20002000, + 0xc0026900, + 0x000000d0, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x000000b2, + 0x80000000, + 0xc0016900, + 0x000000b3, + 0x20002000, + 0xc0026900, + 0x000000d2, + 0x00000000, + 0x3f800000, + 0xc0016900, + 0x00000293, + 0x00514000, + 0xc0016900, + 0x00000300, + 0x00000000, + 0xc0016900, + 0x00000301, + 0x00000000, + 0xc0016900, + 0x00000312, + 0xffffffff, + 0xc0016900, + 0x00000307, + 0x00000000, + 0xc0016900, + 0x00000308, + 0x00000000, + 0xc0016900, + 0x00000283, + 0x00000000, + 0xc0016900, + 0x00000292, + 0x00000000, + 0xc0066900, + 0x0000010f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x00000206, + 0x00000000, + 0xc0016900, + 0x00000207, + 0x00000000, + 0xc0016900, + 0x00000208, + 0x00000000, + 0xc0046900, + 0x00000303, + 0x3f800000, + 0x3f800000, + 0x3f800000, + 0x3f800000, + 0xc0016900, + 0x00000205, + 0x00000004, + 0xc0016900, + 0x00000280, + 0x00000000, + 0xc0016900, + 0x00000281, + 0x00000000, + 0xc0016900, + 0x0000037e, + 0x00000000, + 0xc0016900, + 0x00000382, + 0x00000000, + 0xc0016900, + 0x00000380, + 0x00000000, + 0xc0016900, + 0x00000383, + 0x00000000, + 0xc0016900, + 0x00000381, + 0x00000000, + 0xc0016900, + 0x00000282, + 0x00000008, + 0xc0016900, + 0x00000302, + 0x0000002d, + 0xc0016900, + 0x0000037f, + 0x00000000, + 0xc0016900, + 0x000001b2, + 0x00000001, + 0xc0016900, + 0x000001b6, + 0x00000000, + 0xc0016900, + 0x000001b7, + 0x00000000, + 0xc0016900, + 0x000001b8, + 0x00000000, + 0xc0016900, + 0x000001b9, + 0x00000000, + 0xc0016900, + 0x00000225, + 0x00000000, + 0xc0016900, + 0x00000229, + 0x00000000, + 0xc0016900, + 0x00000237, + 0x00000000, + 0xc0016900, + 0x00000100, + 0x00000800, + 0xc0016900, + 0x00000101, + 0x00000000, + 0xc0016900, + 0x00000102, + 0x00000000, + 0xc0016900, + 0x000002a8, + 0x00000000, + 0xc0016900, + 0x000002a9, + 0x00000000, + 0xc0016900, + 0x00000103, + 0x00000000, + 0xc0016900, + 0x00000284, + 0x00000000, + 0xc0016900, + 0x00000290, + 0x00000000, + 0xc0016900, + 0x00000285, + 0x00000000, + 0xc0016900, + 0x00000286, + 0x00000000, + 0xc0016900, + 0x00000287, + 0x00000000, + 0xc0016900, + 0x00000288, + 0x00000000, + 0xc0016900, + 0x00000289, + 0x00000000, + 0xc0016900, + 0x0000028a, + 0x00000000, + 0xc0016900, + 0x0000028b, + 0x00000000, + 0xc0016900, + 0x0000028c, + 0x00000000, + 0xc0016900, + 0x0000028d, + 0x00000000, + 0xc0016900, + 0x0000028e, + 0x00000000, + 0xc0016900, + 0x0000028f, + 0x00000000, + 0xc0016900, + 0x000002a1, + 0x00000000, + 0xc0016900, + 0x000002a5, + 0x00000000, + 0xc0016900, + 0x000002ac, + 0x00000000, + 0xc0016900, + 0x000002ad, + 0x00000000, + 0xc0016900, + 0x000002ae, + 0x00000000, + 0xc0016900, + 0x000002c8, + 0x00000000, + 0xc0016900, + 0x00000206, + 0x00000100, + 0xc0016900, + 0x00000204, + 0x00010000, + 0xc0036e00, + 0x00000000, + 0x00000012, + 0x00000000, + 0x00000000, + 0xc0016900, + 0x0000008f, + 0x0000000f, + 0xc0016900, + 0x000001e8, + 0x00000001, + 0xc0016900, + 0x00000202, + 0x00cc0000, + 0xc0016900, + 0x00000205, + 0x00000244, + 0xc0016900, + 0x00000203, + 0x00000210, + 0xc0016900, + 0x000001b1, + 0x00000000, + 0xc0016900, + 0x00000185, + 0x00000000, + 0xc0016900, + 0x000001b3, + 0x00000001, + 0xc0016900, + 0x000001b4, + 0x00000000, + 0xc0016900, + 0x00000191, + 0x00000b00, + 0xc0016900, + 0x000001b5, + 0x00000000, +}; + +/* same for r6xx/r7xx */ +const u32 r6xx_vs[] = +{ + 0x00000004, + 0x81000000, + 0x0000203c, + 0x94000b08, + 0x00004000, + 0x14200b1a, + 0x00000000, + 0x00000000, + 0x3c000000, + 0x68cd1000, + 0x00080000, + 0x00000000, +}; + +const u32 r6xx_ps[] = +{ + 0x00000002, + 0x80800000, + 0x00000000, + 0x94200688, + 0x00000010, + 0x000d1000, + 0xb0800000, + 0x00000000, +}; + +const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps); +const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs); +const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state); +const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state); diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.h b/drivers/gpu/drm/radeon/r600_blit_shaders.h new file mode 100644 index 0000000..fdc3b37 --- /dev/null +++ b/drivers/gpu/drm/radeon/r600_blit_shaders.h @@ -0,0 +1,14 @@ + +#ifndef R600_BLIT_SHADERS_H +#define R600_BLIT_SHADERS_H + +extern const u32 r6xx_ps[]; +extern const u32 r6xx_vs[]; +extern const u32 r7xx_default_state[]; +extern const u32 r6xx_default_state[]; + + +extern const u32 r6xx_ps_size, r6xx_vs_size; +extern const u32 r6xx_default_size, r7xx_default_size; + +#endif diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c index 8327912..6d5a711 100644 --- a/drivers/gpu/drm/radeon/r600_cp.c +++ b/drivers/gpu/drm/radeon/r600_cp.c @@ -58,6 +58,12 @@ MODULE_FIRMWARE("radeon/RV730_me.bin"); MODULE_FIRMWARE("radeon/RV710_pfp.bin"); MODULE_FIRMWARE("radeon/RV710_me.bin"); + +int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, + unsigned family, u32 *ib, int *l); +void r600_cs_legacy_init(void); + + # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) @@ -1857,6 +1863,8 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, DRM_DEBUG("\n"); + mutex_init(&dev_priv->cs_mutex); + r600_cs_legacy_init(); /* if we require new memory map but we don't have it fail */ if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); @@ -1888,7 +1896,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, /* Enable vblank on CRTC1 for older X servers */ dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; - + dev_priv->do_boxes = 0; dev_priv->cp_mode = init->cp_mode; /* We don't support anything other than bus-mastering ring mode, @@ -1974,11 +1982,11 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, } else #endif { - dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; + dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset; dev_priv->ring_rptr->handle = - (void *)dev_priv->ring_rptr->offset; + (void *)(unsigned long)dev_priv->ring_rptr->offset; dev->agp_buffer_map->handle = - (void *)dev->agp_buffer_map->offset; + (void *)(unsigned long)dev->agp_buffer_map->offset; DRM_DEBUG("dev_priv->cp_ring->handle %p\n", dev_priv->cp_ring->handle); @@ -2282,3 +2290,239 @@ int r600_cp_dispatch_indirect(struct drm_device *dev, return 0; } + +void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + struct drm_master *master = file_priv->master; + struct drm_radeon_master_private *master_priv = master->driver_priv; + drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; + int nbox = sarea_priv->nbox; + struct drm_clip_rect *pbox = sarea_priv->boxes; + int i, cpp, src_pitch, dst_pitch; + uint64_t src, dst; + RING_LOCALS; + DRM_DEBUG("\n"); + + if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) + cpp = 4; + else + cpp = 2; + + if (sarea_priv->pfCurrentPage == 0) { + src_pitch = dev_priv->back_pitch; + dst_pitch = dev_priv->front_pitch; + src = dev_priv->back_offset + dev_priv->fb_location; + dst = dev_priv->front_offset + dev_priv->fb_location; + } else { + src_pitch = dev_priv->front_pitch; + dst_pitch = dev_priv->back_pitch; + src = dev_priv->front_offset + dev_priv->fb_location; + dst = dev_priv->back_offset + dev_priv->fb_location; + } + + if (r600_prepare_blit_copy(dev, file_priv)) { + DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); + return; + } + for (i = 0; i < nbox; i++) { + int x = pbox[i].x1; + int y = pbox[i].y1; + int w = pbox[i].x2 - x; + int h = pbox[i].y2 - y; + + DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); + + r600_blit_swap(dev, + src, dst, + x, y, x, y, w, h, + src_pitch, dst_pitch, cpp); + } + r600_done_blit_copy(dev); + + /* Increment the frame counter. The client-side 3D driver must + * throttle the framerate by waiting for this value before + * performing the swapbuffer ioctl. + */ + sarea_priv->last_frame++; + + BEGIN_RING(3); + R600_FRAME_AGE(sarea_priv->last_frame); + ADVANCE_RING(); +} + +int r600_cp_dispatch_texture(struct drm_device *dev, + struct drm_file *file_priv, + drm_radeon_texture_t *tex, + drm_radeon_tex_image_t *image) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + struct drm_buf *buf; + u32 *buffer; + const u8 __user *data; + int size, pass_size; + u64 src_offset, dst_offset; + + if (!radeon_check_offset(dev_priv, tex->offset)) { + DRM_ERROR("Invalid destination offset\n"); + return -EINVAL; + } + + /* this might fail for zero-sized uploads - are those illegal? */ + if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { + DRM_ERROR("Invalid final destination offset\n"); + return -EINVAL; + } + + size = tex->height * tex->pitch; + + if (size == 0) + return 0; + + dst_offset = tex->offset; + + if (r600_prepare_blit_copy(dev, file_priv)) { + DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); + return -EAGAIN; + } + do { + data = (const u8 __user *)image->data; + pass_size = size; + + buf = radeon_freelist_get(dev); + if (!buf) { + DRM_DEBUG("EAGAIN\n"); + if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) + return -EFAULT; + return -EAGAIN; + } + + if (pass_size > buf->total) + pass_size = buf->total; + + /* Dispatch the indirect buffer. + */ + buffer = + (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); + + if (DRM_COPY_FROM_USER(buffer, data, pass_size)) { + DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size); + return -EFAULT; + } + + buf->file_priv = file_priv; + buf->used = pass_size; + src_offset = dev_priv->gart_buffers_offset + buf->offset; + + r600_blit_copy(dev, src_offset, dst_offset, pass_size); + + radeon_cp_discard_buffer(dev, file_priv->master, buf); + + /* Update the input parameters for next time */ + image->data = (const u8 __user *)image->data + pass_size; + dst_offset += pass_size; + size -= pass_size; + } while (size > 0); + r600_done_blit_copy(dev); + + return 0; +} + +/* + * Legacy cs ioctl + */ +static u32 radeon_cs_id_get(struct drm_radeon_private *radeon) +{ + /* FIXME: check if wrap affect last reported wrap & sequence */ + radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF; + if (!radeon->cs_id_scnt) { + /* increment wrap counter */ + radeon->cs_id_wcnt += 0x01000000; + /* valid sequence counter start at 1 */ + radeon->cs_id_scnt = 1; + } + return (radeon->cs_id_scnt | radeon->cs_id_wcnt); +} + +static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id) +{ + RING_LOCALS; + + *id = radeon_cs_id_get(dev_priv); + + /* SCRATCH 2 */ + BEGIN_RING(3); + R600_CLEAR_AGE(*id); + ADVANCE_RING(); + COMMIT_RING(); +} + +static int r600_ib_get(struct drm_device *dev, + struct drm_file *fpriv, + struct drm_buf **buffer) +{ + struct drm_buf *buf; + + *buffer = NULL; + buf = radeon_freelist_get(dev); + if (!buf) { + return -EBUSY; + } + buf->file_priv = fpriv; + *buffer = buf; + return 0; +} + +static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf, + struct drm_file *fpriv, int l, int r) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + + if (buf) { + if (!r) + r600_cp_dispatch_indirect(dev, buf, 0, l * 4); + radeon_cp_discard_buffer(dev, fpriv->master, buf); + COMMIT_RING(); + } +} + +int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv) +{ + struct drm_radeon_private *dev_priv = dev->dev_private; + struct drm_radeon_cs *cs = data; + struct drm_buf *buf; + unsigned family; + int l, r = 0; + u32 *ib, cs_id = 0; + + if (dev_priv == NULL) { + DRM_ERROR("called with no initialization\n"); + return -EINVAL; + } + family = dev_priv->flags & RADEON_FAMILY_MASK; + if (family < CHIP_R600) { + DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n"); + return -EINVAL; + } + mutex_lock(&dev_priv->cs_mutex); + /* get ib */ + r = r600_ib_get(dev, fpriv, &buf); + if (r) { + DRM_ERROR("ib_get failed\n"); + goto out; + } + ib = dev->agp_buffer_map->handle + buf->offset; + /* now parse command stream */ + r = r600_cs_legacy(dev, data, fpriv, family, ib, &l); + if (r) { + goto out; + } + +out: + r600_ib_free(dev, buf, fpriv, l, r); + /* emit cs id sequence */ + r600_cs_id_emit(dev_priv, &cs_id); + cs->cs_id = cs_id; + mutex_unlock(&dev_priv->cs_mutex); + return r; +} diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c new file mode 100644 index 0000000..39bf634 --- /dev/null +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -0,0 +1,658 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include "drmP.h" +#include "radeon.h" +#include "radeon_share.h" +#include "r600d.h" +#include "avivod.h" + +static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, + struct radeon_cs_reloc **cs_reloc); +static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, + struct radeon_cs_reloc **cs_reloc); +typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**); +static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm; + +/** + * r600_cs_packet_parse() - parse cp packet and point ib index to next packet + * @parser: parser structure holding parsing context. + * @pkt: where to store packet informations + * + * Assume that chunk_ib_index is properly set. Will return -EINVAL + * if packet is bigger than remaining ib size. or if packets is unknown. + **/ +int r600_cs_packet_parse(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + unsigned idx) +{ + struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; + uint32_t header; + + if (idx >= ib_chunk->length_dw) { + DRM_ERROR("Can not parse packet at %d after CS end %d !\n", + idx, ib_chunk->length_dw); + return -EINVAL; + } + header = ib_chunk->kdata[idx]; + pkt->idx = idx; + pkt->type = CP_PACKET_GET_TYPE(header); + pkt->count = CP_PACKET_GET_COUNT(header); + pkt->one_reg_wr = 0; + switch (pkt->type) { + case PACKET_TYPE0: + pkt->reg = CP_PACKET0_GET_REG(header); + break; + case PACKET_TYPE3: + pkt->opcode = CP_PACKET3_GET_OPCODE(header); + break; + case PACKET_TYPE2: + pkt->count = -1; + break; + default: + DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); + return -EINVAL; + } + if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { + DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", + pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); + return -EINVAL; + } + return 0; +} + +/** + * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3 + * @parser: parser structure holding parsing context. + * @data: pointer to relocation data + * @offset_start: starting offset + * @offset_mask: offset mask (to align start offset on) + * @reloc: reloc informations + * + * Check next packet is relocation packet3, do bo validation and compute + * GPU offset using the provided start. + **/ +static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, + struct radeon_cs_reloc **cs_reloc) +{ + struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_chunk *relocs_chunk; + struct radeon_cs_packet p3reloc; + unsigned idx; + int r; + + if (p->chunk_relocs_idx == -1) { + DRM_ERROR("No relocation chunk !\n"); + return -EINVAL; + } + *cs_reloc = NULL; + ib_chunk = &p->chunks[p->chunk_ib_idx]; + relocs_chunk = &p->chunks[p->chunk_relocs_idx]; + r = r600_cs_packet_parse(p, &p3reloc, p->idx); + if (r) { + return r; + } + p->idx += p3reloc.count + 2; + if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { + DRM_ERROR("No packet3 for relocation for packet at %d.\n", + p3reloc.idx); + return -EINVAL; + } + idx = ib_chunk->kdata[p3reloc.idx + 1]; + if (idx >= relocs_chunk->length_dw) { + DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", + idx, relocs_chunk->length_dw); + return -EINVAL; + } + /* FIXME: we assume reloc size is 4 dwords */ + *cs_reloc = p->relocs_ptr[(idx / 4)]; + return 0; +} + +/** + * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3 + * @parser: parser structure holding parsing context. + * @data: pointer to relocation data + * @offset_start: starting offset + * @offset_mask: offset mask (to align start offset on) + * @reloc: reloc informations + * + * Check next packet is relocation packet3, do bo validation and compute + * GPU offset using the provided start. + **/ +static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, + struct radeon_cs_reloc **cs_reloc) +{ + struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_chunk *relocs_chunk; + struct radeon_cs_packet p3reloc; + unsigned idx; + int r; + + if (p->chunk_relocs_idx == -1) { + DRM_ERROR("No relocation chunk !\n"); + return -EINVAL; + } + *cs_reloc = NULL; + ib_chunk = &p->chunks[p->chunk_ib_idx]; + relocs_chunk = &p->chunks[p->chunk_relocs_idx]; + r = r600_cs_packet_parse(p, &p3reloc, p->idx); + if (r) { + return r; + } + p->idx += p3reloc.count + 2; + if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { + DRM_ERROR("No packet3 for relocation for packet at %d.\n", + p3reloc.idx); + return -EINVAL; + } + idx = ib_chunk->kdata[p3reloc.idx + 1]; + if (idx >= relocs_chunk->length_dw) { + DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", + idx, relocs_chunk->length_dw); + return -EINVAL; + } + *cs_reloc = &p->relocs[0]; + (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32; + (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; + return 0; +} + +static int r600_packet0_check(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt, + unsigned idx, unsigned reg) +{ + switch (reg) { + case AVIVO_D1MODE_VLINE_START_END: + case AVIVO_D2MODE_VLINE_START_END: + break; + default: + printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", + reg, idx); + return -EINVAL; + } + return 0; +} + +static int r600_cs_parse_packet0(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt) +{ + unsigned reg, i; + unsigned idx; + int r; + + idx = pkt->idx + 1; + reg = pkt->reg; + for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { + r = r600_packet0_check(p, pkt, idx, reg); + if (r) { + return r; + } + } + return 0; +} + +static int r600_packet3_check(struct radeon_cs_parser *p, + struct radeon_cs_packet *pkt) +{ + struct radeon_cs_chunk *ib_chunk; + struct radeon_cs_reloc *reloc; + volatile u32 *ib; + unsigned idx; + unsigned i; + unsigned start_reg, end_reg, reg; + int r; + + ib = p->ib->ptr; + ib_chunk = &p->chunks[p->chunk_ib_idx]; + idx = pkt->idx + 1; + switch (pkt->opcode) { + case PACKET3_START_3D_CMDBUF: + if (p->family >= CHIP_RV770 || pkt->count) { + DRM_ERROR("bad START_3D\n"); + return -EINVAL; + } + break; + case PACKET3_CONTEXT_CONTROL: + if (pkt->count != 1) { + DRM_ERROR("bad CONTEXT_CONTROL\n"); + return -EINVAL; + } + break; + case PACKET3_INDEX_TYPE: + case PACKET3_NUM_INSTANCES: + if (pkt->count) { + DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n"); + return -EINVAL; + } + break; + case PACKET3_DRAW_INDEX: + if (pkt->count != 3) { + DRM_ERROR("bad DRAW_INDEX\n"); + return -EINVAL; + } + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad DRAW_INDEX\n"); + return -EINVAL; + } + ib[idx+0] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + break; + case PACKET3_DRAW_INDEX_AUTO: + if (pkt->count != 1) { + DRM_ERROR("bad DRAW_INDEX_AUTO\n"); + return -EINVAL; + } + break; + case PACKET3_DRAW_INDEX_IMMD_BE: + case PACKET3_DRAW_INDEX_IMMD: + if (pkt->count < 2) { + DRM_ERROR("bad DRAW_INDEX_IMMD\n"); + return -EINVAL; + } + break; + case PACKET3_WAIT_REG_MEM: + if (pkt->count != 5) { + DRM_ERROR("bad WAIT_REG_MEM\n"); + return -EINVAL; + } + /* bit 4 is reg (0) or mem (1) */ + if (ib_chunk->kdata[idx+0] & 0x10) { + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad WAIT_REG_MEM\n"); + return -EINVAL; + } + ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + } + break; + case PACKET3_SURFACE_SYNC: + if (pkt->count != 3) { + DRM_ERROR("bad SURFACE_SYNC\n"); + return -EINVAL; + } + /* 0xffffffff/0x0 is flush all cache flag */ + if (ib_chunk->kdata[idx+1] != 0xffffffff || + ib_chunk->kdata[idx+2] != 0) { + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad SURFACE_SYNC\n"); + return -EINVAL; + } + ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + } + break; + case PACKET3_EVENT_WRITE: + if (pkt->count != 2 && pkt->count != 0) { + DRM_ERROR("bad EVENT_WRITE\n"); + return -EINVAL; + } + if (pkt->count) { + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad EVENT_WRITE\n"); + return -EINVAL; + } + ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + } + break; + case PACKET3_EVENT_WRITE_EOP: + if (pkt->count != 4) { + DRM_ERROR("bad EVENT_WRITE_EOP\n"); + return -EINVAL; + } + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad EVENT_WRITE\n"); + return -EINVAL; + } + ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); + ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + break; + case PACKET3_SET_CONFIG_REG: + start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONFIG_REG_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) || + (start_reg >= PACKET3_SET_CONFIG_REG_END) || + (end_reg >= PACKET3_SET_CONFIG_REG_END)) { + DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); + return -EINVAL; + } + for (i = 0; i < pkt->count; i++) { + reg = start_reg + (4 * i); + switch (reg) { + case CP_COHER_BASE: + /* use PACKET3_SURFACE_SYNC */ + return -EINVAL; + default: + break; + } + } + break; + case PACKET3_SET_CONTEXT_REG: + start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) || + (start_reg >= PACKET3_SET_CONTEXT_REG_END) || + (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { + DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); + return -EINVAL; + } + for (i = 0; i < pkt->count; i++) { + reg = start_reg + (4 * i); + switch (reg) { + case DB_DEPTH_BASE: + case CB_COLOR0_BASE: + case CB_COLOR1_BASE: + case CB_COLOR2_BASE: + case CB_COLOR3_BASE: + case CB_COLOR4_BASE: + case CB_COLOR5_BASE: + case CB_COLOR6_BASE: + case CB_COLOR7_BASE: + case SQ_PGM_START_FS: + case SQ_PGM_START_ES: + case SQ_PGM_START_VS: + case SQ_PGM_START_GS: + case SQ_PGM_START_PS: + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad SET_CONTEXT_REG " + "0x%04X\n", reg); + return -EINVAL; + } + ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + break; + case VGT_DMA_BASE: + case VGT_DMA_BASE_HI: + /* These should be handled by DRAW_INDEX packet 3 */ + case VGT_STRMOUT_BASE_OFFSET_0: + case VGT_STRMOUT_BASE_OFFSET_1: + case VGT_STRMOUT_BASE_OFFSET_2: + case VGT_STRMOUT_BASE_OFFSET_3: + case VGT_STRMOUT_BASE_OFFSET_HI_0: + case VGT_STRMOUT_BASE_OFFSET_HI_1: + case VGT_STRMOUT_BASE_OFFSET_HI_2: + case VGT_STRMOUT_BASE_OFFSET_HI_3: + case VGT_STRMOUT_BUFFER_BASE_0: + case VGT_STRMOUT_BUFFER_BASE_1: + case VGT_STRMOUT_BUFFER_BASE_2: + case VGT_STRMOUT_BUFFER_BASE_3: + case VGT_STRMOUT_BUFFER_OFFSET_0: + case VGT_STRMOUT_BUFFER_OFFSET_1: + case VGT_STRMOUT_BUFFER_OFFSET_2: + case VGT_STRMOUT_BUFFER_OFFSET_3: + /* These should be handled by STRMOUT_BUFFER packet 3 */ + DRM_ERROR("bad context reg: 0x%08x\n", reg); + return -EINVAL; + default: + break; + } + } + break; + case PACKET3_SET_RESOURCE: + if (pkt->count % 7) { + DRM_ERROR("bad SET_RESOURCE\n"); + return -EINVAL; + } + start_reg = (ib[idx+0] << 2) + PACKET3_SET_RESOURCE_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) || + (start_reg >= PACKET3_SET_RESOURCE_END) || + (end_reg >= PACKET3_SET_RESOURCE_END)) { + DRM_ERROR("bad SET_RESOURCE\n"); + return -EINVAL; + } + for (i = 0; i < (pkt->count / 7); i++) { + switch (G__SQ_VTX_CONSTANT_TYPE(ib[idx+(i*7)+6+1])) { + case SQ_TEX_VTX_VALID_TEXTURE: + /* tex base */ + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad SET_RESOURCE\n"); + return -EINVAL; + } + ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + /* tex mip base */ + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad SET_RESOURCE\n"); + return -EINVAL; + } + ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + break; + case SQ_TEX_VTX_VALID_BUFFER: + /* vtx base */ + r = r600_cs_packet_next_reloc(p, &reloc); + if (r) { + DRM_ERROR("bad SET_RESOURCE\n"); + return -EINVAL; + } + ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); + ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + break; + case SQ_TEX_VTX_INVALID_TEXTURE: + case SQ_TEX_VTX_INVALID_BUFFER: + default: + DRM_ERROR("bad SET_RESOURCE\n"); + return -EINVAL; + } + } + break; + case PACKET3_SET_ALU_CONST: + start_reg = (ib[idx+0] << 2) + PACKET3_SET_ALU_CONST_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) || + (start_reg >= PACKET3_SET_ALU_CONST_END) || + (end_reg >= PACKET3_SET_ALU_CONST_END)) { + DRM_ERROR("bad SET_ALU_CONST\n"); + return -EINVAL; + } + break; + case PACKET3_SET_BOOL_CONST: + start_reg = (ib[idx+0] << 2) + PACKET3_SET_BOOL_CONST_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) || + (start_reg >= PACKET3_SET_BOOL_CONST_END) || + (end_reg >= PACKET3_SET_BOOL_CONST_END)) { + DRM_ERROR("bad SET_BOOL_CONST\n"); + return -EINVAL; + } + break; + case PACKET3_SET_LOOP_CONST: + start_reg = (ib[idx+0] << 2) + PACKET3_SET_LOOP_CONST_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) || + (start_reg >= PACKET3_SET_LOOP_CONST_END) || + (end_reg >= PACKET3_SET_LOOP_CONST_END)) { + DRM_ERROR("bad SET_LOOP_CONST\n"); + return -EINVAL; + } + break; + case PACKET3_SET_CTL_CONST: + start_reg = (ib[idx+0] << 2) + PACKET3_SET_CTL_CONST_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) || + (start_reg >= PACKET3_SET_CTL_CONST_END) || + (end_reg >= PACKET3_SET_CTL_CONST_END)) { + DRM_ERROR("bad SET_CTL_CONST\n"); + return -EINVAL; + } + break; + case PACKET3_SET_SAMPLER: + if (pkt->count % 3) { + DRM_ERROR("bad SET_SAMPLER\n"); + return -EINVAL; + } + start_reg = (ib[idx+0] << 2) + PACKET3_SET_SAMPLER_OFFSET; + end_reg = 4 * pkt->count + start_reg - 4; + if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) || + (start_reg >= PACKET3_SET_SAMPLER_END) || + (end_reg >= PACKET3_SET_SAMPLER_END)) { + DRM_ERROR("bad SET_SAMPLER\n"); + return -EINVAL; + } + break; + case PACKET3_SURFACE_BASE_UPDATE: + if (p->family >= CHIP_RV770 || p->family == CHIP_R600) { + DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); + return -EINVAL; + } + if (pkt->count) { + DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); + return -EINVAL; + } + break; + case PACKET3_NOP: + break; + default: + DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); + return -EINVAL; + } + return 0; +} + +int r600_cs_parse(struct radeon_cs_parser *p) +{ + struct radeon_cs_packet pkt; + int r; + + do { + r = r600_cs_packet_parse(p, &pkt, p->idx); + if (r) { + return r; + } + p->idx += pkt.count + 2; + switch (pkt.type) { + case PACKET_TYPE0: + r = r600_cs_parse_packet0(p, &pkt); + break; + case PACKET_TYPE2: + break; + case PACKET_TYPE3: + r = r600_packet3_check(p, &pkt); + break; + default: + DRM_ERROR("Unknown packet type %d !\n", pkt.type); + return -EINVAL; + } + if (r) { + return r; + } + } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); +#if 0 + for (r = 0; r < p->ib->length_dw; r++) { + printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]); + mdelay(1); + } +#endif + return 0; +} + +static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p) +{ + if (p->chunk_relocs_idx == -1) { + return 0; + } + p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL); + if (p->relocs == NULL) { + return -ENOMEM; + } + return 0; +} + +/** + * cs_parser_fini() - clean parser states + * @parser: parser structure holding parsing context. + * @error: error number + * + * If error is set than unvalidate buffer, otherwise just free memory + * used by parsing context. + **/ +static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error) +{ + unsigned i; + + kfree(parser->relocs); + for (i = 0; i < parser->nchunks; i++) { + kfree(parser->chunks[i].kdata); + } + kfree(parser->chunks); + kfree(parser->chunks_array); +} + +int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, + unsigned family, u32 *ib, int *l) +{ + struct radeon_cs_parser parser; + struct radeon_cs_chunk *ib_chunk; + struct radeon_ib fake_ib; + int r; + + /* initialize parser */ + memset(&parser, 0, sizeof(struct radeon_cs_parser)); + parser.filp = filp; + parser.rdev = NULL; + parser.family = family; + parser.ib = &fake_ib; + fake_ib.ptr = ib; + r = radeon_cs_parser_init(&parser, data); + if (r) { + DRM_ERROR("Failed to initialize parser !\n"); + r600_cs_parser_fini(&parser, r); + return r; + } + r = r600_cs_parser_relocs_legacy(&parser); + if (r) { + DRM_ERROR("Failed to parse relocation !\n"); + r600_cs_parser_fini(&parser, r); + return r; + } + /* Copy the packet into the IB, the parser will read from the + * input memory (cached) and write to the IB (which can be + * uncached). */ + ib_chunk = &parser.chunks[parser.chunk_ib_idx]; + parser.ib->length_dw = ib_chunk->length_dw; + memcpy((void *)parser.ib->ptr, ib_chunk->kdata, ib_chunk->length_dw*4); + *l = parser.ib->length_dw; + r = r600_cs_parse(&parser); + if (r) { + DRM_ERROR("Invalid command stream !\n"); + r600_cs_parser_fini(&parser, r); + return r; + } + r600_cs_parser_fini(&parser, r); + return r; +} + +void r600_cs_legacy_init(void) +{ + r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm; +} diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h new file mode 100644 index 0000000..723295f --- /dev/null +++ b/drivers/gpu/drm/radeon/r600d.h @@ -0,0 +1,661 @@ +/* + * Copyright 2009 Advanced Micro Devices, Inc. + * Copyright 2009 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef R600D_H +#define R600D_H + +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) + +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) + +#define R6XX_MAX_SH_GPRS 256 +#define R6XX_MAX_TEMP_GPRS 16 +#define R6XX_MAX_SH_THREADS 256 +#define R6XX_MAX_SH_STACK_ENTRIES 4096 +#define R6XX_MAX_BACKENDS 8 +#define R6XX_MAX_BACKENDS_MASK 0xff +#define R6XX_MAX_SIMDS 8 +#define R6XX_MAX_SIMDS_MASK 0xff +#define R6XX_MAX_PIPES 8 +#define R6XX_MAX_PIPES_MASK 0xff + +/* PTE flags */ +#define PTE_VALID (1 << 0) +#define PTE_SYSTEM (1 << 1) +#define PTE_SNOOPED (1 << 2) +#define PTE_READABLE (1 << 5) +#define PTE_WRITEABLE (1 << 6) + +/* Registers */ +#define ARB_POP 0x2418 +#define ENABLE_TC128 (1 << 30) +#define ARB_GDEC_RD_CNTL 0x246C + +#define CC_GC_SHADER_PIPE_CONFIG 0x8950 +#define CC_RB_BACKEND_DISABLE 0x98F4 +#define BACKEND_DISABLE(x) ((x) << 16) + +#define CB_COLOR0_BASE 0x28040 +#define CB_COLOR1_BASE 0x28044 +#define CB_COLOR2_BASE 0x28048 +#define CB_COLOR3_BASE 0x2804C +#define CB_COLOR4_BASE 0x28050 +#define CB_COLOR5_BASE 0x28054 +#define CB_COLOR6_BASE 0x28058 +#define CB_COLOR7_BASE 0x2805C +#define CB_COLOR7_FRAG 0x280FC + +#define CB_COLOR0_SIZE 0x28060 +#define CB_COLOR0_VIEW 0x28080 +#define CB_COLOR0_INFO 0x280a0 +#define CB_COLOR0_TILE 0x280c0 +#define CB_COLOR0_FRAG 0x280e0 +#define CB_COLOR0_MASK 0x28100 + +#define CONFIG_MEMSIZE 0x5428 +#define CP_STAT 0x8680 +#define CP_COHER_BASE 0x85F8 +#define CP_DEBUG 0xC1FC +#define R_0086D8_CP_ME_CNTL 0x86D8 +#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) +#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) +#define CP_ME_RAM_DATA 0xC160 +#define CP_ME_RAM_RADDR 0xC158 +#define CP_ME_RAM_WADDR 0xC15C +#define CP_MEQ_THRESHOLDS 0x8764 +#define MEQ_END(x) ((x) << 16) +#define ROQ_END(x) ((x) << 24) +#define CP_PERFMON_CNTL 0x87FC +#define CP_PFP_UCODE_ADDR 0xC150 +#define CP_PFP_UCODE_DATA 0xC154 +#define CP_QUEUE_THRESHOLDS 0x8760 +#define ROQ_IB1_START(x) ((x) << 0) +#define ROQ_IB2_START(x) ((x) << 8) +#define CP_RB_BASE 0xC100 +#define CP_RB_CNTL 0xC104 +#define RB_BUFSZ(x) ((x)<<0) +#define RB_BLKSZ(x) ((x)<<8) +#define RB_NO_UPDATE (1<<27) +#define RB_RPTR_WR_ENA (1<<31) +#define BUF_SWAP_32BIT (2 << 16) +#define CP_RB_RPTR 0x8700 +#define CP_RB_RPTR_ADDR 0xC10C +#define CP_RB_RPTR_ADDR_HI 0xC110 +#define CP_RB_RPTR_WR 0xC108 +#define CP_RB_WPTR 0xC114 +#define CP_RB_WPTR_ADDR 0xC118 +#define CP_RB_WPTR_ADDR_HI 0xC11C +#define CP_RB_WPTR_DELAY 0x8704 +#define CP_ROQ_IB1_STAT 0x8784 +#define CP_ROQ_IB2_STAT 0x8788 +#define CP_SEM_WAIT_TIMER 0x85BC + +#define DB_DEBUG 0x9830 +#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) +#define DB_DEPTH_BASE 0x2800C +#define DB_WATERMARKS 0x9838 +#define DEPTH_FREE(x) ((x) << 0) +#define DEPTH_FLUSH(x) ((x) << 5) +#define DEPTH_PENDING_FREE(x) ((x) << 15) +#define DEPTH_CACHELINE_FREE(x) ((x) << 20) + +#define DCP_TILING_CONFIG 0x6CA0 +#define PIPE_TILING(x) ((x) << 1) +#define BANK_TILING(x) ((x) << 4) +#define GROUP_SIZE(x) ((x) << 6) +#define ROW_TILING(x) ((x) << 8) +#define BANK_SWAPS(x) ((x) << 11) +#define SAMPLE_SPLIT(x) ((x) << 14) +#define BACKEND_MAP(x) ((x) << 16) + +#define GB_TILING_CONFIG 0x98F0 + +#define GC_USER_SHADER_PIPE_CONFIG 0x8954 +#define INACTIVE_QD_PIPES(x) ((x) << 8) +#define INACTIVE_QD_PIPES_MASK 0x0000FF00 +#define INACTIVE_SIMDS(x) ((x) << 16) +#define INACTIVE_SIMDS_MASK 0x00FF0000 + +#define SQ_CONFIG 0x8c00 +# define VC_ENABLE (1 << 0) +# define EXPORT_SRC_C (1 << 1) +# define DX9_CONSTS (1 << 2) +# define ALU_INST_PREFER_VECTOR (1 << 3) +# define DX10_CLAMP (1 << 4) +# define CLAUSE_SEQ_PRIO(x) ((x) << 8) +# define PS_PRIO(x) ((x) << 24) +# define VS_PRIO(x) ((x) << 26) +# define GS_PRIO(x) ((x) << 28) +# define ES_PRIO(x) ((x) << 30) +#define SQ_GPR_RESOURCE_MGMT_1 0x8c04 +# define NUM_PS_GPRS(x) ((x) << 0) +# define NUM_VS_GPRS(x) ((x) << 16) +# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) +#define SQ_GPR_RESOURCE_MGMT_2 0x8c08 +# define NUM_GS_GPRS(x) ((x) << 0) +# define NUM_ES_GPRS(x) ((x) << 16) +#define SQ_THREAD_RESOURCE_MGMT 0x8c0c +# define NUM_PS_THREADS(x) ((x) << 0) +# define NUM_VS_THREADS(x) ((x) << 8) +# define NUM_GS_THREADS(x) ((x) << 16) +# define NUM_ES_THREADS(x) ((x) << 24) +#define SQ_STACK_RESOURCE_MGMT_1 0x8c10 +# define NUM_PS_STACK_ENTRIES(x) ((x) << 0) +# define NUM_VS_STACK_ENTRIES(x) ((x) << 16) +#define SQ_STACK_RESOURCE_MGMT_2 0x8c14 +# define NUM_GS_STACK_ENTRIES(x) ((x) << 0) +# define NUM_ES_STACK_ENTRIES(x) ((x) << 16) + +#define GRBM_CNTL 0x8000 +# define GRBM_READ_TIMEOUT(x) ((x) << 0) +#define GRBM_STATUS 0x8010 +#define CMDFIFO_AVAIL_MASK 0x0000001F +#define GUI_ACTIVE (1<<31) +#define GRBM_STATUS2 0x8014 +#define GRBM_SOFT_RESET 0x8020 +#define SOFT_RESET_CP (1<<0) + +#define HDP_HOST_PATH_CNTL 0x2C00 +#define HDP_NONSURFACE_BASE 0x2C04 +#define HDP_NONSURFACE_INFO 0x2C08 +#define HDP_NONSURFACE_SIZE 0x2C0C +#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 +#define HDP_TILING_CONFIG 0x2F3C + +#define MC_VM_AGP_TOP 0x2184 +#define MC_VM_AGP_BOT 0x2188 +#define MC_VM_AGP_BASE 0x218C +#define MC_VM_FB_LOCATION 0x2180 +#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C +#define ENABLE_L1_TLB (1 << 0) +#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) +#define ENABLE_L1_STRICT_ORDERING (1 << 2) +#define SYSTEM_ACCESS_MODE_MASK 0x000000C0 +#define SYSTEM_ACCESS_MODE_SHIFT 6 +#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) +#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) +#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) +#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) +#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) +#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) +#define ENABLE_SEMAPHORE_MODE (1 << 10) +#define ENABLE_WAIT_L2_QUERY (1 << 11) +#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) +#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 +#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 +#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) +#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 +#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 +#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 +#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC +#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 +#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 +#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C +#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 +#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 +#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 +#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 +#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 +#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C +#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 +#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 +#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF +#define LOGICAL_PAGE_NUMBER_SHIFT 0 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 + +#define PA_CL_ENHANCE 0x8A14 +#define CLIP_VTX_REORDER_ENA (1 << 0) +#define NUM_CLIP_SEQ(x) ((x) << 1) +#define PA_SC_AA_CONFIG 0x28C04 +#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 +#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 +#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C +#define S0_X(x) ((x) << 0) +#define S0_Y(x) ((x) << 4) +#define S1_X(x) ((x) << 8) +#define S1_Y(x) ((x) << 12) +#define S2_X(x) ((x) << 16) +#define S2_Y(x) ((x) << 20) +#define S3_X(x) ((x) << 24) +#define S3_Y(x) ((x) << 28) +#define S4_X(x) ((x) << 0) +#define S4_Y(x) ((x) << 4) +#define S5_X(x) ((x) << 8) +#define S5_Y(x) ((x) << 12) +#define S6_X(x) ((x) << 16) +#define S6_Y(x) ((x) << 20) +#define S7_X(x) ((x) << 24) +#define S7_Y(x) ((x) << 28) +#define PA_SC_CLIPRECT_RULE 0x2820c +#define PA_SC_ENHANCE 0x8BF0 +#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) +#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) +#define PA_SC_LINE_STIPPLE 0x28A0C +#define PA_SC_LINE_STIPPLE_STATE 0x8B10 +#define PA_SC_MODE_CNTL 0x28A4C +#define PA_SC_MULTI_CHIP_CNTL 0x8B20 + +#define PA_SC_SCREEN_SCISSOR_TL 0x28030 +#define PA_SC_GENERIC_SCISSOR_TL 0x28240 +#define PA_SC_WINDOW_SCISSOR_TL 0x28204 + +#define PCIE_PORT_INDEX 0x0038 +#define PCIE_PORT_DATA 0x003C + +#define RAMCFG 0x2408 +#define NOOFBANK_SHIFT 0 +#define NOOFBANK_MASK 0x00000001 +#define NOOFRANK_SHIFT 1 +#define NOOFRANK_MASK 0x00000002 +#define NOOFROWS_SHIFT 2 +#define NOOFROWS_MASK 0x0000001C +#define NOOFCOLS_SHIFT 5 +#define NOOFCOLS_MASK 0x00000060 +#define CHANSIZE_SHIFT 7 +#define CHANSIZE_MASK 0x00000080 +#define BURSTLENGTH_SHIFT 8 +#define BURSTLENGTH_MASK 0x00000100 +#define CHANSIZE_OVERRIDE (1 << 10) + +#define SCRATCH_REG0 0x8500 +#define SCRATCH_REG1 0x8504 +#define SCRATCH_REG2 0x8508 +#define SCRATCH_REG3 0x850C +#define SCRATCH_REG4 0x8510 +#define SCRATCH_REG5 0x8514 +#define SCRATCH_REG6 0x8518 +#define SCRATCH_REG7 0x851C +#define SCRATCH_UMSK 0x8540 +#define SCRATCH_ADDR 0x8544 + +#define SPI_CONFIG_CNTL 0x9100 +#define GPR_WRITE_PRIORITY(x) ((x) << 0) +#define DISABLE_INTERP_1 (1 << 5) +#define SPI_CONFIG_CNTL_1 0x913C +#define VTX_DONE_DELAY(x) ((x) << 0) +#define INTERP_ONE_PRIM_PER_ROW (1 << 4) +#define SPI_INPUT_Z 0x286D8 +#define SPI_PS_IN_CONTROL_0 0x286CC +#define NUM_INTERP(x) ((x)<<0) +#define POSITION_ENA (1<<8) +#define POSITION_CENTROID (1<<9) +#define POSITION_ADDR(x) ((x)<<10) +#define PARAM_GEN(x) ((x)<<15) +#define PARAM_GEN_ADDR(x) ((x)<<19) +#define BARYC_SAMPLE_CNTL(x) ((x)<<26) +#define PERSP_GRADIENT_ENA (1<<28) +#define LINEAR_GRADIENT_ENA (1<<29) +#define POSITION_SAMPLE (1<<30) +#define BARYC_AT_SAMPLE_ENA (1<<31) +#define SPI_PS_IN_CONTROL_1 0x286D0 +#define GEN_INDEX_PIX (1<<0) +#define GEN_INDEX_PIX_ADDR(x) ((x)<<1) +#define FRONT_FACE_ENA (1<<8) +#define FRONT_FACE_CHAN(x) ((x)<<9) +#define FRONT_FACE_ALL_BITS (1<<11) +#define FRONT_FACE_ADDR(x) ((x)<<12) +#define FOG_ADDR(x) ((x)<<17) +#define FIXED_PT_POSITION_ENA (1<<24) +#define FIXED_PT_POSITION_ADDR(x) ((x)<<25) + +#define SQ_MS_FIFO_SIZES 0x8CF0 +#define CACHE_FIFO_SIZE(x) ((x) << 0) +#define FETCH_FIFO_HIWATER(x) ((x) << 8) +#define DONE_FIFO_HIWATER(x) ((x) << 16) +#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) +#define SQ_PGM_START_ES 0x28880 +#define SQ_PGM_START_FS 0x28894 +#define SQ_PGM_START_GS 0x2886C +#define SQ_PGM_START_PS 0x28840 +#define SQ_PGM_RESOURCES_PS 0x28850 +#define SQ_PGM_EXPORTS_PS 0x28854 +#define SQ_PGM_CF_OFFSET_PS 0x288cc +#define SQ_PGM_START_VS 0x28858 +#define SQ_PGM_RESOURCES_VS 0x28868 +#define SQ_PGM_CF_OFFSET_VS 0x288d0 +#define SQ_VTX_CONSTANT_WORD6_0 0x38018 +#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) +#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) +#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 +#define SQ_TEX_VTX_INVALID_BUFFER 0x1 +#define SQ_TEX_VTX_VALID_TEXTURE 0x2 +#define SQ_TEX_VTX_VALID_BUFFER 0x3 + + +#define SX_MISC 0x28350 +#define SX_DEBUG_1 0x9054 +#define SMX_EVENT_RELEASE (1 << 0) +#define ENABLE_NEW_SMX_ADDRESS (1 << 16) + +#define TA_CNTL_AUX 0x9508 +#define DISABLE_CUBE_WRAP (1 << 0) +#define DISABLE_CUBE_ANISO (1 << 1) +#define SYNC_GRADIENT (1 << 24) +#define SYNC_WALKER (1 << 25) +#define SYNC_ALIGNER (1 << 26) +#define BILINEAR_PRECISION_6_BIT (0 << 31) +#define BILINEAR_PRECISION_8_BIT (1 << 31) + +#define TC_CNTL 0x9608 +#define TC_L2_SIZE(x) ((x)<<5) +#define L2_DISABLE_LATE_HIT (1<<9) + + +#define VGT_CACHE_INVALIDATION 0x88C4 +#define CACHE_INVALIDATION(x) ((x)<<0) +#define VC_ONLY 0 +#define TC_ONLY 1 +#define VC_AND_TC 2 +#define VGT_DMA_BASE 0x287E8 +#define VGT_DMA_BASE_HI 0x287E4 +#define VGT_ES_PER_GS 0x88CC +#define VGT_GS_PER_ES 0x88C8 +#define VGT_GS_PER_VS 0x88E8 +#define VGT_GS_VERTEX_REUSE 0x88D4 +#define VGT_PRIMITIVE_TYPE 0x8958 +#define VGT_NUM_INSTANCES 0x8974 +#define VGT_OUT_DEALLOC_CNTL 0x28C5C +#define DEALLOC_DIST_MASK 0x0000007F +#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 +#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 +#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 +#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c +#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 +#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 +#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c +#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 +#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 +#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 +#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 +#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 +#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC +#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC +#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC +#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C +#define VGT_STRMOUT_EN 0x28AB0 +#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 +#define VTX_REUSE_DEPTH_MASK 0x000000FF +#define VGT_EVENT_INITIATOR 0x28a90 +# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) + +#define VM_CONTEXT0_CNTL 0x1410 +#define ENABLE_CONTEXT (1 << 0) +#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) +#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) +#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 +#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 +#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 +#define REQUEST_TYPE(x) (((x) & 0xf) << 0) +#define RESPONSE_TYPE_MASK 0x000000F0 +#define RESPONSE_TYPE_SHIFT 4 +#define VM_L2_CNTL 0x1400 +#define ENABLE_L2_CACHE (1 << 0) +#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) +#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) +#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) +#define VM_L2_CNTL2 0x1404 +#define INVALIDATE_ALL_L1_TLBS (1 << 0) +#define INVALIDATE_L2_CACHE (1 << 1) +#define VM_L2_CNTL3 0x1408 +#define BANK_SELECT_0(x) (((x) & 0x1f) << 0) +#define BANK_SELECT_1(x) (((x) & 0x1f) << 5) +#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) +#define VM_L2_STATUS 0x140C +#define L2_BUSY (1 << 0) + +#define WAIT_UNTIL 0x8040 +#define WAIT_2D_IDLE_bit (1 << 14) +#define WAIT_3D_IDLE_bit (1 << 15) +#define WAIT_2D_IDLECLEAN_bit (1 << 16) +#define WAIT_3D_IDLECLEAN_bit (1 << 17) + + + +/* + * PM4 + */ +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) +#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ + (((reg) >> 2) & 0xFFFF) | \ + ((n) & 0x3FFF) << 16) +#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ + (((op) & 0xFF) << 8) | \ + ((n) & 0x3FFF) << 16) + +/* Packet 3 types */ +#define PACKET3_NOP 0x10 +#define PACKET3_INDIRECT_BUFFER_END 0x17 +#define PACKET3_SET_PREDICATION 0x20 +#define PACKET3_REG_RMW 0x21 +#define PACKET3_COND_EXEC 0x22 +#define PACKET3_PRED_EXEC 0x23 +#define PACKET3_START_3D_CMDBUF 0x24 +#define PACKET3_DRAW_INDEX_2 0x27 +#define PACKET3_CONTEXT_CONTROL 0x28 +#define PACKET3_DRAW_INDEX_IMMD_BE 0x29 +#define PACKET3_INDEX_TYPE 0x2A +#define PACKET3_DRAW_INDEX 0x2B +#define PACKET3_DRAW_INDEX_AUTO 0x2D +#define PACKET3_DRAW_INDEX_IMMD 0x2E +#define PACKET3_NUM_INSTANCES 0x2F +#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 +#define PACKET3_INDIRECT_BUFFER_MP 0x38 +#define PACKET3_MEM_SEMAPHORE 0x39 +#define PACKET3_MPEG_INDEX 0x3A +#define PACKET3_WAIT_REG_MEM 0x3C +#define PACKET3_MEM_WRITE 0x3D +#define PACKET3_INDIRECT_BUFFER 0x32 +#define PACKET3_CP_INTERRUPT 0x40 +#define PACKET3_SURFACE_SYNC 0x43 +# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) +# define PACKET3_TC_ACTION_ENA (1 << 23) +# define PACKET3_VC_ACTION_ENA (1 << 24) +# define PACKET3_CB_ACTION_ENA (1 << 25) +# define PACKET3_DB_ACTION_ENA (1 << 26) +# define PACKET3_SH_ACTION_ENA (1 << 27) +# define PACKET3_SMX_ACTION_ENA (1 << 28) +#define PACKET3_ME_INITIALIZE 0x44 +#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) +#define PACKET3_COND_WRITE 0x45 +#define PACKET3_EVENT_WRITE 0x46 +#define PACKET3_EVENT_WRITE_EOP 0x47 +#define PACKET3_ONE_REG_WRITE 0x57 +#define PACKET3_SET_CONFIG_REG 0x68 +#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 +#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 +#define PACKET3_SET_CONTEXT_REG 0x69 +#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 +#define PACKET3_SET_CONTEXT_REG_END 0x00029000 +#define PACKET3_SET_ALU_CONST 0x6A +#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 +#define PACKET3_SET_ALU_CONST_END 0x00032000 +#define PACKET3_SET_BOOL_CONST 0x6B +#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 +#define PACKET3_SET_BOOL_CONST_END 0x00040000 +#define PACKET3_SET_LOOP_CONST 0x6C +#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 +#define PACKET3_SET_LOOP_CONST_END 0x0003e380 +#define PACKET3_SET_RESOURCE 0x6D +#define PACKET3_SET_RESOURCE_OFFSET 0x00038000 +#define PACKET3_SET_RESOURCE_END 0x0003c000 +#define PACKET3_SET_SAMPLER 0x6E +#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 +#define PACKET3_SET_SAMPLER_END 0x0003cff0 +#define PACKET3_SET_CTL_CONST 0x6F +#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 +#define PACKET3_SET_CTL_CONST_END 0x0003e200 +#define PACKET3_SURFACE_BASE_UPDATE 0x73 + + +#define R_008020_GRBM_SOFT_RESET 0x8020 +#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) +#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) +#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) +#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) +#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) +#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) +#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) +#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) +#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) +#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) +#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) +#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) +#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) +#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) +#define R_008010_GRBM_STATUS 0x8010 +#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) +#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) +#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) +#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) +#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) +#define S_008010_VC_BUSY(x) (((x) & 1) << 11) +#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) +#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) +#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) +#define S_008010_VGT_BUSY(x) (((x) & 1) << 17) +#define S_008010_TA03_BUSY(x) (((x) & 1) << 18) +#define S_008010_TC_BUSY(x) (((x) & 1) << 19) +#define S_008010_SX_BUSY(x) (((x) & 1) << 20) +#define S_008010_SH_BUSY(x) (((x) & 1) << 21) +#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) +#define S_008010_SMX_BUSY(x) (((x) & 1) << 23) +#define S_008010_SC_BUSY(x) (((x) & 1) << 24) +#define S_008010_PA_BUSY(x) (((x) & 1) << 25) +#define S_008010_DB03_BUSY(x) (((x) & 1) << 26) +#define S_008010_CR_BUSY(x) (((x) & 1) << 27) +#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) +#define S_008010_CP_BUSY(x) (((x) & 1) << 29) +#define S_008010_CB03_BUSY(x) (((x) & 1) << 30) +#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) +#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) +#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) +#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) +#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) +#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) +#define G_008010_VC_BUSY(x) (((x) >> 11) & 1) +#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) +#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) +#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) +#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) +#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) +#define G_008010_TC_BUSY(x) (((x) >> 19) & 1) +#define G_008010_SX_BUSY(x) (((x) >> 20) & 1) +#define G_008010_SH_BUSY(x) (((x) >> 21) & 1) +#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) +#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) +#define G_008010_SC_BUSY(x) (((x) >> 24) & 1) +#define G_008010_PA_BUSY(x) (((x) >> 25) & 1) +#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) +#define G_008010_CR_BUSY(x) (((x) >> 27) & 1) +#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) +#define G_008010_CP_BUSY(x) (((x) >> 29) & 1) +#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) +#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) +#define R_008014_GRBM_STATUS2 0x8014 +#define S_008014_CR_CLEAN(x) (((x) & 1) << 0) +#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) +#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) +#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) +#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) +#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) +#define S_008014_TA0_BUSY(x) (((x) & 1) << 12) +#define S_008014_TA1_BUSY(x) (((x) & 1) << 13) +#define S_008014_TA2_BUSY(x) (((x) & 1) << 14) +#define S_008014_TA3_BUSY(x) (((x) & 1) << 15) +#define S_008014_DB0_BUSY(x) (((x) & 1) << 16) +#define S_008014_DB1_BUSY(x) (((x) & 1) << 17) +#define S_008014_DB2_BUSY(x) (((x) & 1) << 18) +#define S_008014_DB3_BUSY(x) (((x) & 1) << 19) +#define S_008014_CB0_BUSY(x) (((x) & 1) << 20) +#define S_008014_CB1_BUSY(x) (((x) & 1) << 21) +#define S_008014_CB2_BUSY(x) (((x) & 1) << 22) +#define S_008014_CB3_BUSY(x) (((x) & 1) << 23) +#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) +#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) +#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) +#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) +#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) +#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) +#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) +#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) +#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) +#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) +#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) +#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) +#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) +#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) +#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) +#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) +#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) +#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) +#define R_000E50_SRBM_STATUS 0x0E50 +#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) +#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) +#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) +#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) +#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) +#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) +#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) +#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) +#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) +#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) +#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) +#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) +#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) +#define R_000E60_SRBM_SOFT_RESET 0x0E60 +#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) +#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) +#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) +#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) +#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) +#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) +#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) +#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) +#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) +#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) +#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) +#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) +#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) +#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) + +#endif diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index e47f2fc..3299733 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -50,8 +50,8 @@ #include #include "radeon_mode.h" +#include "radeon_share.h" #include "radeon_reg.h" -#include "r300.h" /* * Modules parameters. @@ -112,10 +112,11 @@ enum radeon_family { CHIP_RV635, CHIP_RV670, CHIP_RS780, + CHIP_RS880, CHIP_RV770, CHIP_RV730, CHIP_RV710, - CHIP_RS880, + CHIP_RV740, CHIP_LAST, }; @@ -152,10 +153,21 @@ struct radeon_device; */ bool radeon_get_bios(struct radeon_device *rdev); + /* - * Clocks + * Dummy page */ +struct radeon_dummy_page { + struct page *page; + dma_addr_t addr; +}; +int radeon_dummy_page_init(struct radeon_device *rdev); +void radeon_dummy_page_fini(struct radeon_device *rdev); + +/* + * Clocks + */ struct radeon_clock { struct radeon_pll p1pll; struct radeon_pll p2pll; @@ -166,6 +178,7 @@ struct radeon_clock { uint32_t default_sclk; }; + /* * Fences. */ @@ -332,14 +345,18 @@ struct radeon_mc { resource_size_t aper_size; resource_size_t aper_base; resource_size_t agp_base; - unsigned gtt_location; - unsigned gtt_size; - unsigned vram_location; /* for some chips with <= 32MB we need to lie * about vram size near mc fb location */ - unsigned mc_vram_size; + u64 mc_vram_size; + u64 gtt_location; + u64 gtt_size; + u64 gtt_start; + u64 gtt_end; + u64 vram_location; + u64 vram_start; + u64 vram_end; unsigned vram_width; - unsigned real_vram_size; + u64 real_vram_size; int vram_mtrr; bool vram_is_ddr; }; @@ -411,6 +428,16 @@ struct radeon_cp { bool ready; }; +struct r600_blit { + struct radeon_object *shader_obj; + u64 shader_gpu_addr; + u32 vs_offset, ps_offset; + u32 state_offset; + u32 state_len; + u32 vb_used, vb_total; + struct radeon_ib *vb_ib; +}; + int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); @@ -463,6 +490,7 @@ struct radeon_cs_parser { int chunk_relocs_idx; struct radeon_ib *ib; void *track; + unsigned family; }; struct radeon_cs_packet { @@ -559,6 +587,9 @@ int r100_debugfs_cp_init(struct radeon_device *rdev); */ struct radeon_asic { int (*init)(struct radeon_device *rdev); + void (*fini)(struct radeon_device *rdev); + int (*resume)(struct radeon_device *rdev); + int (*suspend)(struct radeon_device *rdev); void (*errata)(struct radeon_device *rdev); void (*vram_info)(struct radeon_device *rdev); int (*gpu_reset)(struct radeon_device *rdev); @@ -573,7 +604,11 @@ struct radeon_asic { int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); void (*cp_fini)(struct radeon_device *rdev); void (*cp_disable)(struct radeon_device *rdev); + void (*cp_commit)(struct radeon_device *rdev); void (*ring_start)(struct radeon_device *rdev); + int (*ring_test)(struct radeon_device *rdev); + void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); + int (*ib_test)(struct radeon_device *rdev); int (*irq_set)(struct radeon_device *rdev); int (*irq_process)(struct radeon_device *rdev); u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); @@ -613,6 +648,8 @@ struct r100_asic { union radeon_asic_config { struct r300_asic r300; struct r100_asic r100; + struct r600_asic r600; + struct rv770_asic rv770; }; @@ -698,12 +735,16 @@ struct radeon_device { struct radeon_pm pm; struct mutex cs_mutex; struct radeon_wb wb; + struct radeon_dummy_page dummy_page; bool gpu_lockup; bool shutdown; bool suspend; bool need_dma32; + bool new_init_path; struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; - const struct firmware *fw; /* firmware */ + const struct firmware *me_fw; /* all family ME firmware */ + const struct firmware *pfp_fw; /* r6/700 PFP firmware */ + struct r600_blit r600_blit; }; int radeon_device_init(struct radeon_device *rdev, @@ -713,6 +754,13 @@ int radeon_device_init(struct radeon_device *rdev, void radeon_device_fini(struct radeon_device *rdev); int radeon_gpu_wait_for_idle(struct radeon_device *rdev); +/* r600 blit */ +int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); +void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); +void r600_kms_blit_copy(struct radeon_device *rdev, + u64 src_gpu_addr, u64 dst_gpu_addr, + int size_bytes); + static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) { if (reg < 0x10000) @@ -740,6 +788,7 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) #define RREG32(reg) r100_mm_rreg(rdev, (reg)) +#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) @@ -763,6 +812,7 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32 tmp_ |= ((val) & ~(mask)); \ WREG32_PLL(reg, tmp_); \ } while (0) +#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) /* * Indirect registers accessor @@ -827,51 +877,6 @@ void radeon_atombios_fini(struct radeon_device *rdev); /* * RING helpers. */ -#define CP_PACKET0 0x00000000 -#define PACKET0_BASE_INDEX_SHIFT 0 -#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) -#define PACKET0_COUNT_SHIFT 16 -#define PACKET0_COUNT_MASK (0x3fff << 16) -#define CP_PACKET1 0x40000000 -#define CP_PACKET2 0x80000000 -#define PACKET2_PAD_SHIFT 0 -#define PACKET2_PAD_MASK (0x3fffffff << 0) -#define CP_PACKET3 0xC0000000 -#define PACKET3_IT_OPCODE_SHIFT 8 -#define PACKET3_IT_OPCODE_MASK (0xff << 8) -#define PACKET3_COUNT_SHIFT 16 -#define PACKET3_COUNT_MASK (0x3fff << 16) -/* PACKET3 op code */ -#define PACKET3_NOP 0x10 -#define PACKET3_3D_DRAW_VBUF 0x28 -#define PACKET3_3D_DRAW_IMMD 0x29 -#define PACKET3_3D_DRAW_INDX 0x2A -#define PACKET3_3D_LOAD_VBPNTR 0x2F -#define PACKET3_INDX_BUFFER 0x33 -#define PACKET3_3D_DRAW_VBUF_2 0x34 -#define PACKET3_3D_DRAW_IMMD_2 0x35 -#define PACKET3_3D_DRAW_INDX_2 0x36 -#define PACKET3_BITBLT_MULTI 0x9B - -#define PACKET0(reg, n) (CP_PACKET0 | \ - REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ - REG_SET(PACKET0_COUNT, (n))) -#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) -#define PACKET3(op, n) (CP_PACKET3 | \ - REG_SET(PACKET3_IT_OPCODE, (op)) | \ - REG_SET(PACKET3_COUNT, (n))) - -#define PACKET_TYPE0 0 -#define PACKET_TYPE1 1 -#define PACKET_TYPE2 2 -#define PACKET_TYPE3 3 - -#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) -#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) -#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) -#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) -#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) - static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) { #if DRM_DEBUG_CODE @@ -890,6 +895,9 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) * ASICs macro. */ #define radeon_init(rdev) (rdev)->asic->init((rdev)) +#define radeon_fini(rdev) (rdev)->asic->fini((rdev)) +#define radeon_resume(rdev) (rdev)->asic->resume((rdev)) +#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) @@ -905,7 +913,11 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) +#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) +#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) +#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) +#define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev)) #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index c9cbd8a..e87bb91 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -60,6 +60,7 @@ int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); void r100_cp_fini(struct radeon_device *rdev); void r100_cp_disable(struct radeon_device *rdev); +void r100_cp_commit(struct radeon_device *rdev); void r100_ring_start(struct radeon_device *rdev); int r100_irq_set(struct radeon_device *rdev); int r100_irq_process(struct radeon_device *rdev); @@ -78,6 +79,9 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg, uint32_t offset, uint32_t obj_size); int r100_clear_surface_reg(struct radeon_device *rdev, int reg); void r100_bandwidth_update(struct radeon_device *rdev); +void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); +int r100_ib_test(struct radeon_device *rdev); +int r100_ring_test(struct radeon_device *rdev); static struct radeon_asic r100_asic = { .init = &r100_init, @@ -95,7 +99,11 @@ static struct radeon_asic r100_asic = { .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &r100_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &r100_irq_set, .irq_process = &r100_irq_process, .get_vblank_counter = &r100_get_vblank_counter, @@ -156,7 +164,11 @@ static struct radeon_asic r300_asic = { .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &r300_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &r100_irq_set, .irq_process = &r100_irq_process, .get_vblank_counter = &r100_get_vblank_counter, @@ -197,7 +209,11 @@ static struct radeon_asic r420_asic = { .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &r300_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &r100_irq_set, .irq_process = &r100_irq_process, .get_vblank_counter = &r100_get_vblank_counter, @@ -245,7 +261,11 @@ static struct radeon_asic rs400_asic = { .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &r300_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &r100_irq_set, .irq_process = &r100_irq_process, .get_vblank_counter = &r100_get_vblank_counter, @@ -298,7 +318,11 @@ static struct radeon_asic rs600_asic = { .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &r300_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &rs600_irq_set, .irq_process = &rs600_irq_process, .get_vblank_counter = &rs600_get_vblank_counter, @@ -341,7 +365,11 @@ static struct radeon_asic rs690_asic = { .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &r300_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &rs600_irq_set, .irq_process = &rs600_irq_process, .get_vblank_counter = &rs600_get_vblank_counter, @@ -391,7 +419,11 @@ static struct radeon_asic rv515_asic = { .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &rv515_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &rs600_irq_set, .irq_process = &rs600_irq_process, .get_vblank_counter = &rs600_get_vblank_counter, @@ -434,7 +466,11 @@ static struct radeon_asic r520_asic = { .cp_init = &r100_cp_init, .cp_fini = &r100_cp_fini, .cp_disable = &r100_cp_disable, + .cp_commit = &r100_cp_commit, .ring_start = &rv515_ring_start, + .ring_test = &r100_ring_test, + .ring_ib_execute = &r100_ring_ib_execute, + .ib_test = &r100_ib_test, .irq_set = &rs600_irq_set, .irq_process = &rs600_irq_process, .get_vblank_counter = &rs600_get_vblank_counter, @@ -453,9 +489,127 @@ static struct radeon_asic r520_asic = { }; /* - * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710 + * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 */ +int r600_init(struct radeon_device *rdev); +void r600_fini(struct radeon_device *rdev); +int r600_suspend(struct radeon_device *rdev); +int r600_resume(struct radeon_device *rdev); +int r600_wb_init(struct radeon_device *rdev); +void r600_wb_fini(struct radeon_device *rdev); +void r600_cp_commit(struct radeon_device *rdev); +void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); +int r600_cs_parse(struct radeon_cs_parser *p); +void r600_fence_ring_emit(struct radeon_device *rdev, + struct radeon_fence *fence); +int r600_copy_dma(struct radeon_device *rdev, + uint64_t src_offset, + uint64_t dst_offset, + unsigned num_pages, + struct radeon_fence *fence); +int r600_irq_process(struct radeon_device *rdev); +int r600_irq_set(struct radeon_device *rdev); +int r600_gpu_reset(struct radeon_device *rdev); +int r600_set_surface_reg(struct radeon_device *rdev, int reg, + uint32_t tiling_flags, uint32_t pitch, + uint32_t offset, uint32_t obj_size); +int r600_clear_surface_reg(struct radeon_device *rdev, int reg); +void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); +int r600_ib_test(struct radeon_device *rdev); +int r600_ring_test(struct radeon_device *rdev); +int r600_copy_blit(struct radeon_device *rdev, + uint64_t src_offset, uint64_t dst_offset, + unsigned num_pages, struct radeon_fence *fence); + +static struct radeon_asic r600_asic = { + .errata = NULL, + .init = &r600_init, + .fini = &r600_fini, + .suspend = &r600_suspend, + .resume = &r600_resume, + .cp_commit = &r600_cp_commit, + .vram_info = NULL, + .gpu_reset = &r600_gpu_reset, + .mc_init = NULL, + .mc_fini = NULL, + .wb_init = &r600_wb_init, + .wb_fini = &r600_wb_fini, + .gart_enable = NULL, + .gart_disable = NULL, + .gart_tlb_flush = &r600_pcie_gart_tlb_flush, + .gart_set_page = &rs600_gart_set_page, + .cp_init = NULL, + .cp_fini = NULL, + .cp_disable = NULL, + .ring_start = NULL, + .ring_test = &r600_ring_test, + .ring_ib_execute = &r600_ring_ib_execute, + .ib_test = &r600_ib_test, + .irq_set = &r600_irq_set, + .irq_process = &r600_irq_process, + .fence_ring_emit = &r600_fence_ring_emit, + .cs_parse = &r600_cs_parse, + .copy_blit = &r600_copy_blit, + .copy_dma = &r600_copy_blit, + .copy = NULL, + .set_engine_clock = &radeon_atom_set_engine_clock, + .set_memory_clock = &radeon_atom_set_memory_clock, + .set_pcie_lanes = NULL, + .set_clock_gating = &radeon_atom_set_clock_gating, + .set_surface_reg = r600_set_surface_reg, + .clear_surface_reg = r600_clear_surface_reg, + .bandwidth_update = &r520_bandwidth_update, +}; + +/* + * rv770,rv730,rv710,rv740 + */ +int rv770_init(struct radeon_device *rdev); +void rv770_fini(struct radeon_device *rdev); +int rv770_suspend(struct radeon_device *rdev); +int rv770_resume(struct radeon_device *rdev); +int rv770_gpu_reset(struct radeon_device *rdev); + +static struct radeon_asic rv770_asic = { + .errata = NULL, + .init = &rv770_init, + .fini = &rv770_fini, + .suspend = &rv770_suspend, + .resume = &rv770_resume, + .cp_commit = &r600_cp_commit, + .vram_info = NULL, + .gpu_reset = &rv770_gpu_reset, + .mc_init = NULL, + .mc_fini = NULL, + .wb_init = &r600_wb_init, + .wb_fini = &r600_wb_fini, + .gart_enable = NULL, + .gart_disable = NULL, + .gart_tlb_flush = &r600_pcie_gart_tlb_flush, + .gart_set_page = &rs600_gart_set_page, + .cp_init = NULL, + .cp_fini = NULL, + .cp_disable = NULL, + .ring_start = NULL, + .ring_test = &r600_ring_test, + .ring_ib_execute = &r600_ring_ib_execute, + .ib_test = &r600_ib_test, + .irq_set = &r600_irq_set, + .irq_process = &r600_irq_process, + .fence_ring_emit = &r600_fence_ring_emit, + .cs_parse = &r600_cs_parse, + .copy_blit = &r600_copy_blit, + .copy_dma = &r600_copy_blit, + .copy = NULL, + .set_engine_clock = &radeon_atom_set_engine_clock, + .set_memory_clock = &radeon_atom_set_memory_clock, + .set_pcie_lanes = NULL, + .set_clock_gating = &radeon_atom_set_clock_gating, + .set_surface_reg = r600_set_surface_reg, + .clear_surface_reg = r600_clear_surface_reg, + .bandwidth_update = &r520_bandwidth_update, +}; #endif diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index bba9b4b..a8fb392 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -370,10 +370,6 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) && record-> ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { - DRM_ERROR - ("record type %d\n", - record-> - ucRecordType); switch (record-> ucRecordType) { case ATOM_I2C_RECORD_TYPE: diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c index a37cbce..152eef1 100644 --- a/drivers/gpu/drm/radeon/radeon_clocks.c +++ b/drivers/gpu/drm/radeon/radeon_clocks.c @@ -102,10 +102,12 @@ void radeon_get_clock_info(struct drm_device *dev) p1pll->reference_div = 12; if (p2pll->reference_div < 2) p2pll->reference_div = 12; - if (spll->reference_div < 2) - spll->reference_div = - RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & - RADEON_M_SPLL_REF_DIV_MASK; + if (rdev->family < CHIP_RS600) { + if (spll->reference_div < 2) + spll->reference_div = + RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & + RADEON_M_SPLL_REF_DIV_MASK; + } if (mpll->reference_div < 2) mpll->reference_div = spll->reference_div; } else { diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 7693f7c..f2469c5 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -37,7 +37,7 @@ /* * Clear GPU surface registers. */ -static void radeon_surface_init(struct radeon_device *rdev) +void radeon_surface_init(struct radeon_device *rdev) { /* FIXME: check this out */ if (rdev->family < CHIP_R600) { @@ -56,7 +56,7 @@ static void radeon_surface_init(struct radeon_device *rdev) /* * GPU scratch registers helpers function. */ -static void radeon_scratch_init(struct radeon_device *rdev) +void radeon_scratch_init(struct radeon_device *rdev) { int i; @@ -156,16 +156,14 @@ int radeon_mc_setup(struct radeon_device *rdev) tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); rdev->mc.gtt_location = tmp; } - DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20); + DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", - rdev->mc.vram_location, - rdev->mc.vram_location + rdev->mc.mc_vram_size - 1); - if (rdev->mc.real_vram_size != rdev->mc.mc_vram_size) - DRM_INFO("radeon: VRAM less than aperture workaround enabled\n"); - DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20); + (unsigned)rdev->mc.vram_location, + (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); + DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", - rdev->mc.gtt_location, - rdev->mc.gtt_location + rdev->mc.gtt_size - 1); + (unsigned)rdev->mc.gtt_location, + (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); return 0; } @@ -205,6 +203,31 @@ static bool radeon_card_posted(struct radeon_device *rdev) } +int radeon_dummy_page_init(struct radeon_device *rdev) +{ + rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); + if (rdev->dummy_page.page == NULL) + return -ENOMEM; + rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, + 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + if (!rdev->dummy_page.addr) { + __free_page(rdev->dummy_page.page); + rdev->dummy_page.page = NULL; + return -ENOMEM; + } + return 0; +} + +void radeon_dummy_page_fini(struct radeon_device *rdev) +{ + if (rdev->dummy_page.page == NULL) + return; + pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, + PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + __free_page(rdev->dummy_page.page); + rdev->dummy_page.page = NULL; +} + /* * Registers accessors functions. @@ -323,9 +346,15 @@ int radeon_asic_init(struct radeon_device *rdev) case CHIP_RV635: case CHIP_RV670: case CHIP_RS780: + case CHIP_RS880: + rdev->asic = &r600_asic; + break; case CHIP_RV770: case CHIP_RV730: case CHIP_RV710: + case CHIP_RV740: + rdev->asic = &rv770_asic; + break; default: /* FIXME: not supported yet */ return -EINVAL; @@ -448,7 +477,7 @@ int radeon_device_init(struct radeon_device *rdev, struct pci_dev *pdev, uint32_t flags) { - int r, ret; + int r, ret = 0; int dma_bits; DRM_INFO("radeon: Initializing kernel modesetting.\n"); @@ -487,10 +516,6 @@ int radeon_device_init(struct radeon_device *rdev, if (r) { return r; } - r = radeon_init(rdev); - if (r) { - return r; - } /* set DMA mask + need_dma32 flags. * PCIE - can handle 40-bits. @@ -521,111 +546,118 @@ int radeon_device_init(struct radeon_device *rdev, DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); - /* Setup errata flags */ - radeon_errata(rdev); - /* Initialize scratch registers */ - radeon_scratch_init(rdev); - /* Initialize surface registers */ - radeon_surface_init(rdev); - - /* TODO: disable VGA need to use VGA request */ - /* BIOS*/ - if (!radeon_get_bios(rdev)) { - if (ASIC_IS_AVIVO(rdev)) - return -EINVAL; - } - if (rdev->is_atom_bios) { - r = radeon_atombios_init(rdev); + rdev->new_init_path = false; + r = radeon_init(rdev); + if (r) { + return r; + } + if (!rdev->new_init_path) { + /* Setup errata flags */ + radeon_errata(rdev); + /* Initialize scratch registers */ + radeon_scratch_init(rdev); + /* Initialize surface registers */ + radeon_surface_init(rdev); + + /* TODO: disable VGA need to use VGA request */ + /* BIOS*/ + if (!radeon_get_bios(rdev)) { + if (ASIC_IS_AVIVO(rdev)) + return -EINVAL; + } + if (rdev->is_atom_bios) { + r = radeon_atombios_init(rdev); + if (r) { + return r; + } + } else { + r = radeon_combios_init(rdev); + if (r) { + return r; + } + } + /* Reset gpu before posting otherwise ATOM will enter infinite loop */ + if (radeon_gpu_reset(rdev)) { + /* FIXME: what do we want to do here ? */ + } + /* check if cards are posted or not */ + if (!radeon_card_posted(rdev) && rdev->bios) { + DRM_INFO("GPU not posted. posting now...\n"); + if (rdev->is_atom_bios) { + atom_asic_init(rdev->mode_info.atom_context); + } else { + radeon_combios_asic_init(rdev->ddev); + } + } + /* Initialize clocks */ + r = radeon_clocks_init(rdev); if (r) { return r; } - } else { - r = radeon_combios_init(rdev); + /* Get vram informations */ + radeon_vram_info(rdev); + + /* Add an MTRR for the VRAM */ + rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, + MTRR_TYPE_WRCOMB, 1); + DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n", + (unsigned)(rdev->mc.mc_vram_size >> 20), + (unsigned)(rdev->mc.aper_size >> 20)); + DRM_INFO("RAM width %dbits %cDR\n", + rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); + /* Initialize memory controller (also test AGP) */ + r = radeon_mc_init(rdev); if (r) { return r; } - } - /* Reset gpu before posting otherwise ATOM will enter infinite loop */ - if (radeon_gpu_reset(rdev)) { - /* FIXME: what do we want to do here ? */ - } - /* check if cards are posted or not */ - if (!radeon_card_posted(rdev) && rdev->bios) { - DRM_INFO("GPU not posted. posting now...\n"); - if (rdev->is_atom_bios) { - atom_asic_init(rdev->mode_info.atom_context); - } else { - radeon_combios_asic_init(rdev->ddev); - } - } - /* Initialize clocks */ - r = radeon_clocks_init(rdev); - if (r) { - return r; - } - /* Get vram informations */ - radeon_vram_info(rdev); - - /* Add an MTRR for the VRAM */ - rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, - MTRR_TYPE_WRCOMB, 1); - DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n", - rdev->mc.real_vram_size >> 20, - (unsigned)rdev->mc.aper_size >> 20); - DRM_INFO("RAM width %dbits %cDR\n", - rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); - /* Initialize memory controller (also test AGP) */ - r = radeon_mc_init(rdev); - if (r) { - return r; - } - /* Fence driver */ - r = radeon_fence_driver_init(rdev); - if (r) { - return r; - } - r = radeon_irq_kms_init(rdev); - if (r) { - return r; - } - /* Memory manager */ - r = radeon_object_init(rdev); - if (r) { - return r; - } - /* Initialize GART (initialize after TTM so we can allocate - * memory through TTM but finalize after TTM) */ - r = radeon_gart_enable(rdev); - if (!r) { - r = radeon_gem_init(rdev); - } - - /* 1M ring buffer */ - if (!r) { - r = radeon_cp_init(rdev, 1024 * 1024); - } - if (!r) { - r = radeon_wb_init(rdev); + /* Fence driver */ + r = radeon_fence_driver_init(rdev); if (r) { - DRM_ERROR("radeon: failled initializing WB (%d).\n", r); return r; } - } - if (!r) { - r = radeon_ib_pool_init(rdev); + r = radeon_irq_kms_init(rdev); if (r) { - DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); return r; } - } - if (!r) { - r = radeon_ib_test(rdev); + /* Memory manager */ + r = radeon_object_init(rdev); if (r) { - DRM_ERROR("radeon: failled testing IB (%d).\n", r); return r; } + /* Initialize GART (initialize after TTM so we can allocate + * memory through TTM but finalize after TTM) */ + r = radeon_gart_enable(rdev); + if (!r) { + r = radeon_gem_init(rdev); + } + + /* 1M ring buffer */ + if (!r) { + r = radeon_cp_init(rdev, 1024 * 1024); + } + if (!r) { + r = radeon_wb_init(rdev); + if (r) { + DRM_ERROR("radeon: failled initializing WB (%d).\n", r); + return r; + } + } + if (!r) { + r = radeon_ib_pool_init(rdev); + if (r) { + DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); + return r; + } + } + if (!r) { + r = radeon_ib_test(rdev); + if (r) { + DRM_ERROR("radeon: failled testing IB (%d).\n", r); + return r; + } + } + ret = r; } - ret = r; r = radeon_modeset_init(rdev); if (r) { return r; @@ -651,26 +683,29 @@ void radeon_device_fini(struct radeon_device *rdev) rdev->shutdown = true; /* Order matter so becarefull if you rearrange anythings */ radeon_modeset_fini(rdev); - radeon_ib_pool_fini(rdev); - radeon_cp_fini(rdev); - radeon_wb_fini(rdev); - radeon_gem_fini(rdev); - radeon_object_fini(rdev); - /* mc_fini must be after object_fini */ - radeon_mc_fini(rdev); + if (!rdev->new_init_path) { + radeon_ib_pool_fini(rdev); + radeon_cp_fini(rdev); + radeon_wb_fini(rdev); + radeon_gem_fini(rdev); + radeon_mc_fini(rdev); #if __OS_HAS_AGP - radeon_agp_fini(rdev); + radeon_agp_fini(rdev); #endif - radeon_irq_kms_fini(rdev); - radeon_fence_driver_fini(rdev); - radeon_clocks_fini(rdev); - if (rdev->is_atom_bios) { - radeon_atombios_fini(rdev); + radeon_irq_kms_fini(rdev); + radeon_fence_driver_fini(rdev); + radeon_clocks_fini(rdev); + radeon_object_fini(rdev); + if (rdev->is_atom_bios) { + radeon_atombios_fini(rdev); + } else { + radeon_combios_fini(rdev); + } + kfree(rdev->bios); + rdev->bios = NULL; } else { - radeon_combios_fini(rdev); + radeon_fini(rdev); } - kfree(rdev->bios); - rdev->bios = NULL; iounmap(rdev->rmmio); rdev->rmmio = NULL; } @@ -708,9 +743,12 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) /* wait for gpu to finish processing current batch */ radeon_fence_wait_last(rdev); - radeon_cp_disable(rdev); - radeon_gart_disable(rdev); - + if (!rdev->new_init_path) { + radeon_cp_disable(rdev); + radeon_gart_disable(rdev); + } else { + radeon_suspend(rdev); + } /* evict remaining vram memory */ radeon_object_evict_vram(rdev); @@ -746,33 +784,37 @@ int radeon_resume_kms(struct drm_device *dev) if (radeon_gpu_reset(rdev)) { /* FIXME: what do we want to do here ? */ } - /* post card */ - if (rdev->is_atom_bios) { - atom_asic_init(rdev->mode_info.atom_context); + if (!rdev->new_init_path) { + /* post card */ + if (rdev->is_atom_bios) { + atom_asic_init(rdev->mode_info.atom_context); + } else { + radeon_combios_asic_init(rdev->ddev); + } + /* Initialize clocks */ + r = radeon_clocks_init(rdev); + if (r) { + release_console_sem(); + return r; + } + /* Enable IRQ */ + rdev->irq.sw_int = true; + radeon_irq_set(rdev); + /* Initialize GPU Memory Controller */ + r = radeon_mc_init(rdev); + if (r) { + goto out; + } + r = radeon_gart_enable(rdev); + if (r) { + goto out; + } + r = radeon_cp_init(rdev, rdev->cp.ring_size); + if (r) { + goto out; + } } else { - radeon_combios_asic_init(rdev->ddev); - } - /* Initialize clocks */ - r = radeon_clocks_init(rdev); - if (r) { - release_console_sem(); - return r; - } - /* Enable IRQ */ - rdev->irq.sw_int = true; - radeon_irq_set(rdev); - /* Initialize GPU Memory Controller */ - r = radeon_mc_init(rdev); - if (r) { - goto out; - } - r = radeon_gart_enable(rdev); - if (r) { - goto out; - } - r = radeon_cp_init(rdev, rdev->cp.ring_size); - if (r) { - goto out; + radeon_resume(rdev); } out: fb_set_suspend(rdev->fbdev_info, 0); diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index 40294a0..c7b1859 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -356,6 +356,12 @@ typedef struct drm_radeon_private { int r700_sc_hiz_tile_fifo_size; int r700_sc_earlyz_tile_fifo_fize; + struct mutex cs_mutex; + u32 cs_id_scnt; + u32 cs_id_wcnt; + /* r6xx/r7xx drm blit vertex buffer */ + struct drm_buf *blit_vb; + /* firmware */ const struct firmware *me_fw, *pfp_fw; } drm_radeon_private_t; @@ -396,6 +402,9 @@ static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, (off >= gart_start && off <= gart_end)); } +/* radeon_state.c */ +extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf); + /* radeon_cp.c */ extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); @@ -487,6 +496,22 @@ extern int r600_cp_dispatch_indirect(struct drm_device *dev, struct drm_buf *buf, int start, int end); extern int r600_page_table_init(struct drm_device *dev); extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); +extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); +extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv); +extern int r600_cp_dispatch_texture(struct drm_device *dev, + struct drm_file *file_priv, + drm_radeon_texture_t *tex, + drm_radeon_tex_image_t *image); +/* r600_blit.c */ +extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv); +extern void r600_done_blit_copy(struct drm_device *dev); +extern void r600_blit_copy(struct drm_device *dev, + uint64_t src_gpu_addr, uint64_t dst_gpu_addr, + int size_bytes); +extern void r600_blit_swap(struct drm_device *dev, + uint64_t src_gpu_addr, uint64_t dst_gpu_addr, + int sx, int sy, int dx, int dy, + int w, int h, int src_pitch, int dst_pitch, int cpp); /* Flags for stats.boxes */ @@ -1114,13 +1139,71 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00 -# define R600_IT_INDIRECT_BUFFER 0x00003200 -# define R600_IT_ME_INITIALIZE 0x00004400 +# define R600_IT_INDIRECT_BUFFER_END 0x00001700 +# define R600_IT_SET_PREDICATION 0x00002000 +# define R600_IT_REG_RMW 0x00002100 +# define R600_IT_COND_EXEC 0x00002200 +# define R600_IT_PRED_EXEC 0x00002300 +# define R600_IT_START_3D_CMDBUF 0x00002400 +# define R600_IT_DRAW_INDEX_2 0x00002700 +# define R600_IT_CONTEXT_CONTROL 0x00002800 +# define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 +# define R600_IT_INDEX_TYPE 0x00002A00 +# define R600_IT_DRAW_INDEX 0x00002B00 +# define R600_IT_DRAW_INDEX_AUTO 0x00002D00 +# define R600_IT_DRAW_INDEX_IMMD 0x00002E00 +# define R600_IT_NUM_INSTANCES 0x00002F00 +# define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 +# define R600_IT_INDIRECT_BUFFER_MP 0x00003800 +# define R600_IT_MEM_SEMAPHORE 0x00003900 +# define R600_IT_MPEG_INDEX 0x00003A00 +# define R600_IT_WAIT_REG_MEM 0x00003C00 +# define R600_IT_MEM_WRITE 0x00003D00 +# define R600_IT_INDIRECT_BUFFER 0x00003200 +# define R600_IT_CP_INTERRUPT 0x00004000 +# define R600_IT_SURFACE_SYNC 0x00004300 +# define R600_CB0_DEST_BASE_ENA (1 << 6) +# define R600_TC_ACTION_ENA (1 << 23) +# define R600_VC_ACTION_ENA (1 << 24) +# define R600_CB_ACTION_ENA (1 << 25) +# define R600_DB_ACTION_ENA (1 << 26) +# define R600_SH_ACTION_ENA (1 << 27) +# define R600_SMX_ACTION_ENA (1 << 28) +# define R600_IT_ME_INITIALIZE 0x00004400 # define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) -# define R600_IT_EVENT_WRITE 0x00004600 -# define R600_IT_SET_CONFIG_REG 0x00006800 -# define R600_SET_CONFIG_REG_OFFSET 0x00008000 -# define R600_SET_CONFIG_REG_END 0x0000ac00 +# define R600_IT_COND_WRITE 0x00004500 +# define R600_IT_EVENT_WRITE 0x00004600 +# define R600_IT_EVENT_WRITE_EOP 0x00004700 +# define R600_IT_ONE_REG_WRITE 0x00005700 +# define R600_IT_SET_CONFIG_REG 0x00006800 +# define R600_SET_CONFIG_REG_OFFSET 0x00008000 +# define R600_SET_CONFIG_REG_END 0x0000ac00 +# define R600_IT_SET_CONTEXT_REG 0x00006900 +# define R600_SET_CONTEXT_REG_OFFSET 0x00028000 +# define R600_SET_CONTEXT_REG_END 0x00029000 +# define R600_IT_SET_ALU_CONST 0x00006A00 +# define R600_SET_ALU_CONST_OFFSET 0x00030000 +# define R600_SET_ALU_CONST_END 0x00032000 +# define R600_IT_SET_BOOL_CONST 0x00006B00 +# define R600_SET_BOOL_CONST_OFFSET 0x0003e380 +# define R600_SET_BOOL_CONST_END 0x00040000 +# define R600_IT_SET_LOOP_CONST 0x00006C00 +# define R600_SET_LOOP_CONST_OFFSET 0x0003e200 +# define R600_SET_LOOP_CONST_END 0x0003e380 +# define R600_IT_SET_RESOURCE 0x00006D00 +# define R600_SET_RESOURCE_OFFSET 0x00038000 +# define R600_SET_RESOURCE_END 0x0003c000 +# define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0 +# define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1 +# define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2 +# define R600_SQ_TEX_VTX_VALID_BUFFER 0x3 +# define R600_IT_SET_SAMPLER 0x00006E00 +# define R600_SET_SAMPLER_OFFSET 0x0003c000 +# define R600_SET_SAMPLER_END 0x0003cff0 +# define R600_IT_SET_CTL_CONST 0x00006F00 +# define R600_SET_CTL_CONST_OFFSET 0x0003cff0 +# define R600_SET_CTL_CONST_END 0x0003e200 +# define R600_IT_SURFACE_BASE_UPDATE 0x00007300 #define RADEON_CP_PACKET_MASK 0xC0000000 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 @@ -1598,6 +1681,52 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); #define R600_CB_COLOR7_BASE 0x2805c #define R600_CB_COLOR7_FRAG 0x280fc +#define R600_CB_COLOR0_SIZE 0x28060 +#define R600_CB_COLOR0_VIEW 0x28080 +#define R600_CB_COLOR0_INFO 0x280a0 +#define R600_CB_COLOR0_TILE 0x280c0 +#define R600_CB_COLOR0_FRAG 0x280e0 +#define R600_CB_COLOR0_MASK 0x28100 + +#define AVIVO_D1MODE_VLINE_START_END 0x6538 +#define AVIVO_D2MODE_VLINE_START_END 0x6d38 +#define R600_CP_COHER_BASE 0x85f8 +#define R600_DB_DEPTH_BASE 0x2800c +#define R600_SQ_PGM_START_FS 0x28894 +#define R600_SQ_PGM_START_ES 0x28880 +#define R600_SQ_PGM_START_VS 0x28858 +#define R600_SQ_PGM_RESOURCES_VS 0x28868 +#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0 +#define R600_SQ_PGM_START_GS 0x2886c +#define R600_SQ_PGM_START_PS 0x28840 +#define R600_SQ_PGM_RESOURCES_PS 0x28850 +#define R600_SQ_PGM_EXPORTS_PS 0x28854 +#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc +#define R600_VGT_DMA_BASE 0x287e8 +#define R600_VGT_DMA_BASE_HI 0x287e4 +#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10 +#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14 +#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18 +#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c +#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44 +#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48 +#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c +#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50 +#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8 +#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8 +#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8 +#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08 +#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc +#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec +#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc +#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c + +#define R600_VGT_PRIMITIVE_TYPE 0x8958 + +#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030 +#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240 +#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204 + #define R600_TC_CNTL 0x9608 # define R600_TC_L2_SIZE(x) ((x) << 5) # define R600_L2_DISABLE_LATE_HIT (1 << 9) diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c index b4e48dd..506dd4d 100644 --- a/drivers/gpu/drm/radeon/radeon_fence.c +++ b/drivers/gpu/drm/radeon/radeon_fence.c @@ -53,9 +53,9 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) * away */ WREG32(rdev->fence_drv.scratch_reg, fence->seq); - } else { + } else radeon_fence_ring_emit(rdev, fence); - } + fence->emited = true; fence->timeout = jiffies + ((2000 * HZ) / 1000); list_del(&fence->list); @@ -168,7 +168,47 @@ bool radeon_fence_signaled(struct radeon_fence *fence) return signaled; } -int radeon_fence_wait(struct radeon_fence *fence, bool interruptible) +int r600_fence_wait(struct radeon_fence *fence, bool intr, bool lazy) +{ + struct radeon_device *rdev; + unsigned long cur_jiffies; + unsigned long timeout; + int ret = 0; + + cur_jiffies = jiffies; + timeout = HZ / 100; + + if (time_after(fence->timeout, cur_jiffies)) { + timeout = fence->timeout - cur_jiffies; + } + + rdev = fence->rdev; + + __set_current_state(intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); + + while (1) { + if (radeon_fence_signaled(fence)) + break; + + if (time_after_eq(jiffies, timeout)) { + ret = -EBUSY; + break; + } + + if (lazy) + schedule_timeout(1); + + if (intr && signal_pending(current)) { + ret = -ERESTART; + break; + } + } + __set_current_state(TASK_RUNNING); + return ret; +} + + +int radeon_fence_wait(struct radeon_fence *fence, bool intr) { struct radeon_device *rdev; unsigned long cur_jiffies; @@ -176,7 +216,6 @@ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible) bool expired = false; int r; - if (fence == NULL) { WARN(1, "Querying an invalid fence : %p !\n", fence); return 0; @@ -185,13 +224,18 @@ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible) if (radeon_fence_signaled(fence)) { return 0; } + + if (rdev->family >= CHIP_R600) + return r600_fence_wait(fence, intr, 0); + retry: cur_jiffies = jiffies; timeout = HZ / 100; if (time_after(fence->timeout, cur_jiffies)) { timeout = fence->timeout - cur_jiffies; } - if (interruptible) { + + if (intr) { r = wait_event_interruptible_timeout(rdev->fence_drv.queue, radeon_fence_signaled(fence), timeout); if (unlikely(r == -ERESTARTSYS)) { diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 28be2f1..21da871 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h @@ -3255,6 +3255,24 @@ #define RADEON_CP_RB_WPTR 0x0714 #define RADEON_CP_RB_RPTR_WR 0x071c +#define RADEON_SCRATCH_UMSK 0x0770 +#define RADEON_SCRATCH_ADDR 0x0774 + +#define R600_CP_RB_BASE 0xc100 +#define R600_CP_RB_CNTL 0xc104 +# define R600_RB_BUFSZ(x) ((x) << 0) +# define R600_RB_BLKSZ(x) ((x) << 8) +# define R600_RB_NO_UPDATE (1 << 27) +# define R600_RB_RPTR_WR_ENA (1 << 31) +#define R600_CP_RB_RPTR_WR 0xc108 +#define R600_CP_RB_RPTR_ADDR 0xc10c +#define R600_CP_RB_RPTR_ADDR_HI 0xc110 +#define R600_CP_RB_WPTR 0xc114 +#define R600_CP_RB_WPTR_ADDR 0xc118 +#define R600_CP_RB_WPTR_ADDR_HI 0xc11c +#define R600_CP_RB_RPTR 0x8700 +#define R600_CP_RB_WPTR_DELAY 0x8704 + #define RADEON_CP_IB_BASE 0x0738 #define RADEON_CP_IB_BUFSZ 0x073c diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index 60d1593..aa9837a 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c @@ -110,7 +110,6 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) return; } list_del(&tmp->list); - INIT_LIST_HEAD(&tmp->list); if (tmp->fence) { radeon_fence_unref(&tmp->fence); } @@ -119,19 +118,11 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) mutex_unlock(&rdev->ib_pool.mutex); } -static void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib) -{ - while ((ib->length_dw & rdev->cp.align_mask)) { - ib->ptr[ib->length_dw++] = PACKET2(0); - } -} - int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) { int r = 0; mutex_lock(&rdev->ib_pool.mutex); - radeon_ib_align(rdev, ib); if (!ib->length_dw || !rdev->cp.ready) { /* TODO: Nothings in the ib we should report. */ mutex_unlock(&rdev->ib_pool.mutex); @@ -145,9 +136,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) mutex_unlock(&rdev->ib_pool.mutex); return r; } - radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); - radeon_ring_write(rdev, ib->gpu_addr); - radeon_ring_write(rdev, ib->length_dw); + radeon_ring_ib_execute(rdev, ib); radeon_fence_emit(rdev, ib->fence); radeon_ring_unlock_commit(rdev); list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs); @@ -215,69 +204,16 @@ void radeon_ib_pool_fini(struct radeon_device *rdev) mutex_unlock(&rdev->ib_pool.mutex); } -int radeon_ib_test(struct radeon_device *rdev) -{ - struct radeon_ib *ib; - uint32_t scratch; - uint32_t tmp = 0; - unsigned i; - int r; - - r = radeon_scratch_get(rdev, &scratch); - if (r) { - DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); - return r; - } - WREG32(scratch, 0xCAFEDEAD); - r = radeon_ib_get(rdev, &ib); - if (r) { - return r; - } - ib->ptr[0] = PACKET0(scratch, 0); - ib->ptr[1] = 0xDEADBEEF; - ib->ptr[2] = PACKET2(0); - ib->ptr[3] = PACKET2(0); - ib->ptr[4] = PACKET2(0); - ib->ptr[5] = PACKET2(0); - ib->ptr[6] = PACKET2(0); - ib->ptr[7] = PACKET2(0); - ib->length_dw = 8; - r = radeon_ib_schedule(rdev, ib); - if (r) { - radeon_scratch_free(rdev, scratch); - radeon_ib_free(rdev, &ib); - return r; - } - r = radeon_fence_wait(ib->fence, false); - if (r) { - return r; - } - for (i = 0; i < rdev->usec_timeout; i++) { - tmp = RREG32(scratch); - if (tmp == 0xDEADBEEF) { - break; - } - DRM_UDELAY(1); - } - if (i < rdev->usec_timeout) { - DRM_INFO("ib test succeeded in %u usecs\n", i); - } else { - DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", - scratch, tmp); - r = -EINVAL; - } - radeon_scratch_free(rdev, scratch); - radeon_ib_free(rdev, &ib); - return r; -} - /* * Ring. */ void radeon_ring_free_size(struct radeon_device *rdev) { - rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); + if (rdev->family >= CHIP_R600) + rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); + else + rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); /* This works because ring_size is a power of 2 */ rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4)); rdev->cp.ring_free_dw -= rdev->cp.wptr; @@ -320,11 +256,10 @@ void radeon_ring_unlock_commit(struct radeon_device *rdev) count_dw_pad = (rdev->cp.align_mask + 1) - (rdev->cp.wptr & rdev->cp.align_mask); for (i = 0; i < count_dw_pad; i++) { - radeon_ring_write(rdev, PACKET2(0)); + radeon_ring_write(rdev, 2 << 30); } DRM_MEMORYBARRIER(); - WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); - (void)RREG32(RADEON_CP_RB_WPTR); + radeon_cp_commit(rdev); mutex_unlock(&rdev->cp.mutex); } @@ -334,46 +269,6 @@ void radeon_ring_unlock_undo(struct radeon_device *rdev) mutex_unlock(&rdev->cp.mutex); } -int radeon_ring_test(struct radeon_device *rdev) -{ - uint32_t scratch; - uint32_t tmp = 0; - unsigned i; - int r; - - r = radeon_scratch_get(rdev, &scratch); - if (r) { - DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); - return r; - } - WREG32(scratch, 0xCAFEDEAD); - r = radeon_ring_lock(rdev, 2); - if (r) { - DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); - radeon_scratch_free(rdev, scratch); - return r; - } - radeon_ring_write(rdev, PACKET0(scratch, 0)); - radeon_ring_write(rdev, 0xDEADBEEF); - radeon_ring_unlock_commit(rdev); - for (i = 0; i < rdev->usec_timeout; i++) { - tmp = RREG32(scratch); - if (tmp == 0xDEADBEEF) { - break; - } - DRM_UDELAY(1); - } - if (i < rdev->usec_timeout) { - DRM_INFO("ring test succeeded in %d usecs\n", i); - } else { - DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", - scratch, tmp); - r = -EINVAL; - } - radeon_scratch_free(rdev, scratch); - return r; -} - int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size) { int r; diff --git a/drivers/gpu/drm/radeon/radeon_share.h b/drivers/gpu/drm/radeon/radeon_share.h index 63a7735..5f9e358 100644 --- a/drivers/gpu/drm/radeon/radeon_share.h +++ b/drivers/gpu/drm/radeon/radeon_share.h @@ -28,12 +28,89 @@ #ifndef __RADEON_SHARE_H__ #define __RADEON_SHARE_H__ +/* Common */ +struct radeon_device; +struct radeon_cs_parser; +int radeon_clocks_init(struct radeon_device *rdev); +void radeon_clocks_fini(struct radeon_device *rdev); +void radeon_scratch_init(struct radeon_device *rdev); +void radeon_surface_init(struct radeon_device *rdev); +int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); + + +/* R100, RV100, RS100, RV200, RS200, R200, RV250, RS300, RV280 */ void r100_vram_init_sizes(struct radeon_device *rdev); + +/* R300, R350, RV350, RV380 */ +struct r300_asic { + const unsigned *reg_safe_bm; + unsigned reg_safe_bm_size; +}; + + +/* RS690, RS740 */ void rs690_line_buffer_adjust(struct radeon_device *rdev, struct drm_display_mode *mode1, struct drm_display_mode *mode2); + +/* RV515 */ void rv515_bandwidth_avivo_update(struct radeon_device *rdev); + +/* R600, RV610, RV630, RV620, RV635, RV670, RS780, RS880 */ +bool r600_card_posted(struct radeon_device *rdev); +void r600_cp_stop(struct radeon_device *rdev); +void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); +int r600_cp_resume(struct radeon_device *rdev); +int r600_count_pipe_bits(uint32_t val); +int r600_gart_clear_page(struct radeon_device *rdev, int i); +int r600_mc_wait_for_idle(struct radeon_device *rdev); +void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); +int r600_ib_test(struct radeon_device *rdev); +int r600_ring_test(struct radeon_device *rdev); +int r600_wb_init(struct radeon_device *rdev); +void r600_wb_fini(struct radeon_device *rdev); +void r600_scratch_init(struct radeon_device *rdev); +int r600_blit_init(struct radeon_device *rdev); +void r600_blit_fini(struct radeon_device *rdev); +int r600_cp_init_microcode(struct radeon_device *rdev); +struct r600_asic { + unsigned max_pipes; + unsigned max_tile_pipes; + unsigned max_simds; + unsigned max_backends; + unsigned max_gprs; + unsigned max_threads; + unsigned max_stack_entries; + unsigned max_hw_contexts; + unsigned max_gs_threads; + unsigned sx_max_export_size; + unsigned sx_max_export_pos_size; + unsigned sx_max_export_smx_size; + unsigned sq_num_cf_insts; +}; + +/* RV770, RV7300, RV710 */ +struct rv770_asic { + unsigned max_pipes; + unsigned max_tile_pipes; + unsigned max_simds; + unsigned max_backends; + unsigned max_gprs; + unsigned max_threads; + unsigned max_stack_entries; + unsigned max_hw_contexts; + unsigned max_gs_threads; + unsigned sx_max_export_size; + unsigned sx_max_export_pos_size; + unsigned sx_max_export_smx_size; + unsigned sq_num_cf_insts; + unsigned sx_num_of_sets; + unsigned sc_prim_fifo_size; + unsigned sc_hiz_tile_fifo_size; + unsigned sc_earlyz_tile_fifo_fize; +}; + #endif diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c index 2882f40..aad0c6f 100644 --- a/drivers/gpu/drm/radeon/radeon_state.c +++ b/drivers/gpu/drm/radeon/radeon_state.c @@ -1546,7 +1546,7 @@ static void radeon_cp_dispatch_vertex(struct drm_device * dev, } while (i < nbox); } -static void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf) +void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf) { drm_radeon_private_t *dev_priv = dev->dev_private; struct drm_radeon_master_private *master_priv = master->driver_priv; @@ -2213,7 +2213,10 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; - radeon_cp_dispatch_swap(dev, file_priv->master); + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) + r600_cp_dispatch_swap(dev, file_priv); + else + radeon_cp_dispatch_swap(dev, file_priv->master); sarea_priv->ctx_owner = 0; COMMIT_RING(); @@ -2412,7 +2415,10 @@ static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file RING_SPACE_TEST_WITH_RETURN(dev_priv); VB_AGE_TEST_WITH_RETURN(dev_priv); - ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image); + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) + ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image); + else + ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image); return ret; } @@ -2495,8 +2501,9 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end); } - if (indirect->discard) + if (indirect->discard) { radeon_cp_discard_buffer(dev, file_priv->master, buf); + } COMMIT_RING(); return 0; @@ -3227,7 +3234,8 @@ struct drm_ioctl_desc radeon_ioctls[] = { DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH), DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH), DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH), - DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH) + DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH), + DRM_IOCTL_DEF(DRM_RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH) }; int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index dc7a442..acd889c 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -376,9 +376,8 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, radeon_move_null(bo, new_mem); return 0; } - if (!rdev->cp.ready) { + if (!rdev->cp.ready || rdev->asic->copy == NULL) { /* use memcpy */ - DRM_ERROR("CP is not ready use memcpy.\n"); goto memcpy; } @@ -495,7 +494,7 @@ int radeon_ttm_init(struct radeon_device *rdev) return r; } DRM_INFO("radeon: %uM of VRAM memory ready\n", - rdev->mc.real_vram_size / (1024 * 1024)); + (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0, ((rdev->mc.gtt_size) >> PAGE_SHIFT)); if (r) { @@ -503,7 +502,7 @@ int radeon_ttm_init(struct radeon_device *rdev) return r; } DRM_INFO("radeon: %uM of GTT memory ready.\n", - rdev->mc.gtt_size / (1024 * 1024)); + (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; } diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c index b29affd..8c3ea7e 100644 --- a/drivers/gpu/drm/radeon/rs400.c +++ b/drivers/gpu/drm/radeon/rs400.c @@ -63,7 +63,7 @@ void rs400_gart_adjust_size(struct radeon_device *rdev) break; default: DRM_ERROR("Unable to use IGP GART size %uM\n", - rdev->mc.gtt_size >> 20); + (unsigned)(rdev->mc.gtt_size >> 20)); DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); DRM_ERROR("Forcing to 32M GART size\n"); rdev->mc.gtt_size = 32 * 1024 * 1024; diff --git a/drivers/gpu/drm/radeon/rs780.c b/drivers/gpu/drm/radeon/rs780.c deleted file mode 100644 index 0affcff..0000000 --- a/drivers/gpu/drm/radeon/rs780.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright 2008 Advanced Micro Devices, Inc. - * Copyright 2008 Red Hat Inc. - * Copyright 2009 Jerome Glisse. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Dave Airlie - * Alex Deucher - * Jerome Glisse - */ -#include "drmP.h" -#include "radeon_reg.h" -#include "radeon.h" - -/* rs780 depends on : */ -void rs600_mc_disable_clients(struct radeon_device *rdev); - -/* This files gather functions specifics to: - * rs780 - * - * Some of these functions might be used by newer ASICs. - */ -int rs780_mc_wait_for_idle(struct radeon_device *rdev); -void rs780_gpu_init(struct radeon_device *rdev); - - -/* - * MC - */ -int rs780_mc_init(struct radeon_device *rdev) -{ - rs780_gpu_init(rdev); - /* FIXME: implement */ - - rs600_mc_disable_clients(rdev); - if (rs780_mc_wait_for_idle(rdev)) { - printk(KERN_WARNING "Failed to wait MC idle while " - "programming pipes. Bad things might happen.\n"); - } - return 0; -} - -void rs780_mc_fini(struct radeon_device *rdev) -{ - /* FIXME: implement */ -} - - -/* - * Global GPU functions - */ -void rs780_errata(struct radeon_device *rdev) -{ - rdev->pll_errata = 0; -} - -int rs780_mc_wait_for_idle(struct radeon_device *rdev) -{ - /* FIXME: implement */ - return 0; -} - -void rs780_gpu_init(struct radeon_device *rdev) -{ - /* FIXME: implement */ -} - - -/* - * VRAM info - */ -void rs780_vram_get_type(struct radeon_device *rdev) -{ - /* FIXME: implement */ -} - -void rs780_vram_info(struct radeon_device *rdev) -{ - rs780_vram_get_type(rdev); - - /* FIXME: implement */ - /* Could aper size report 0 ? */ - rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); - rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); -} diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 97965c4..99e397f 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c @@ -27,7 +27,7 @@ */ #include #include "drmP.h" -#include "rv515r.h" +#include "rv515d.h" #include "radeon.h" #include "radeon_share.h" diff --git a/drivers/gpu/drm/radeon/rv515d.h b/drivers/gpu/drm/radeon/rv515d.h new file mode 100644 index 0000000..a65e17e --- /dev/null +++ b/drivers/gpu/drm/radeon/rv515d.h @@ -0,0 +1,220 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef __RV515D_H__ +#define __RV515D_H__ + +/* + * RV515 registers + */ +#define PCIE_INDEX 0x0030 +#define PCIE_DATA 0x0034 +#define MC_IND_INDEX 0x0070 +#define MC_IND_WR_EN (1 << 24) +#define MC_IND_DATA 0x0074 +#define RBBM_SOFT_RESET 0x00F0 +#define CONFIG_MEMSIZE 0x00F8 +#define HDP_FB_LOCATION 0x0134 +#define CP_CSQ_CNTL 0x0740 +#define CP_CSQ_MODE 0x0744 +#define CP_CSQ_ADDR 0x07F0 +#define CP_CSQ_DATA 0x07F4 +#define CP_CSQ_STAT 0x07F8 +#define CP_CSQ2_STAT 0x07FC +#define RBBM_STATUS 0x0E40 +#define DST_PIPE_CONFIG 0x170C +#define WAIT_UNTIL 0x1720 +#define WAIT_2D_IDLE (1 << 14) +#define WAIT_3D_IDLE (1 << 15) +#define WAIT_2D_IDLECLEAN (1 << 16) +#define WAIT_3D_IDLECLEAN (1 << 17) +#define ISYNC_CNTL 0x1724 +#define ISYNC_ANY2D_IDLE3D (1 << 0) +#define ISYNC_ANY3D_IDLE2D (1 << 1) +#define ISYNC_TRIG2D_IDLE3D (1 << 2) +#define ISYNC_TRIG3D_IDLE2D (1 << 3) +#define ISYNC_WAIT_IDLEGUI (1 << 4) +#define ISYNC_CPSCRATCH_IDLEGUI (1 << 5) +#define VAP_INDEX_OFFSET 0x208C +#define VAP_PVS_STATE_FLUSH_REG 0x2284 +#define GB_ENABLE 0x4008 +#define GB_MSPOS0 0x4010 +#define MS_X0_SHIFT 0 +#define MS_Y0_SHIFT 4 +#define MS_X1_SHIFT 8 +#define MS_Y1_SHIFT 12 +#define MS_X2_SHIFT 16 +#define MS_Y2_SHIFT 20 +#define MSBD0_Y_SHIFT 24 +#define MSBD0_X_SHIFT 28 +#define GB_MSPOS1 0x4014 +#define MS_X3_SHIFT 0 +#define MS_Y3_SHIFT 4 +#define MS_X4_SHIFT 8 +#define MS_Y4_SHIFT 12 +#define MS_X5_SHIFT 16 +#define MS_Y5_SHIFT 20 +#define MSBD1_SHIFT 24 +#define GB_TILE_CONFIG 0x4018 +#define ENABLE_TILING (1 << 0) +#define PIPE_COUNT_MASK 0x0000000E +#define PIPE_COUNT_SHIFT 1 +#define TILE_SIZE_8 (0 << 4) +#define TILE_SIZE_16 (1 << 4) +#define TILE_SIZE_32 (2 << 4) +#define SUBPIXEL_1_12 (0 << 16) +#define SUBPIXEL_1_16 (1 << 16) +#define GB_SELECT 0x401C +#define GB_AA_CONFIG 0x4020 +#define GB_PIPE_SELECT 0x402C +#define GA_ENHANCE 0x4274 +#define GA_DEADLOCK_CNTL (1 << 0) +#define GA_FASTSYNC_CNTL (1 << 1) +#define GA_POLY_MODE 0x4288 +#define FRONT_PTYPE_POINT (0 << 4) +#define FRONT_PTYPE_LINE (1 << 4) +#define FRONT_PTYPE_TRIANGE (2 << 4) +#define BACK_PTYPE_POINT (0 << 7) +#define BACK_PTYPE_LINE (1 << 7) +#define BACK_PTYPE_TRIANGE (2 << 7) +#define GA_ROUND_MODE 0x428C +#define GEOMETRY_ROUND_TRUNC (0 << 0) +#define GEOMETRY_ROUND_NEAREST (1 << 0) +#define COLOR_ROUND_TRUNC (0 << 2) +#define COLOR_ROUND_NEAREST (1 << 2) +#define SU_REG_DEST 0x42C8 +#define RB3D_DSTCACHE_CTLSTAT 0x4E4C +#define RB3D_DC_FLUSH (2 << 0) +#define RB3D_DC_FREE (2 << 2) +#define RB3D_DC_FINISH (1 << 4) +#define ZB_ZCACHE_CTLSTAT 0x4F18 +#define ZC_FLUSH (1 << 0) +#define ZC_FREE (1 << 1) +#define DC_LB_MEMORY_SPLIT 0x6520 +#define DC_LB_MEMORY_SPLIT_MASK 0x00000003 +#define DC_LB_MEMORY_SPLIT_SHIFT 0 +#define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 +#define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 +#define DC_LB_MEMORY_SPLIT_D1_ONLY 2 +#define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 +#define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) +#define DC_LB_DISP1_END_ADR_SHIFT 4 +#define DC_LB_DISP1_END_ADR_MASK 0x00007FF0 +#define D1MODE_PRIORITY_A_CNT 0x6548 +#define MODE_PRIORITY_MARK_MASK 0x00007FFF +#define MODE_PRIORITY_OFF (1 << 16) +#define MODE_PRIORITY_ALWAYS_ON (1 << 20) +#define MODE_PRIORITY_FORCE_MASK (1 << 24) +#define D1MODE_PRIORITY_B_CNT 0x654C +#define LB_MAX_REQ_OUTSTANDING 0x6D58 +#define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F +#define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 +#define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000 +#define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 +#define D2MODE_PRIORITY_A_CNT 0x6D48 +#define D2MODE_PRIORITY_B_CNT 0x6D4C + +/* ix[MC] registers */ +#define MC_FB_LOCATION 0x01 +#define MC_FB_START_MASK 0x0000FFFF +#define MC_FB_START_SHIFT 0 +#define MC_FB_TOP_MASK 0xFFFF0000 +#define MC_FB_TOP_SHIFT 16 +#define MC_AGP_LOCATION 0x02 +#define MC_AGP_START_MASK 0x0000FFFF +#define MC_AGP_START_SHIFT 0 +#define MC_AGP_TOP_MASK 0xFFFF0000 +#define MC_AGP_TOP_SHIFT 16 +#define MC_AGP_BASE 0x03 +#define MC_AGP_BASE_2 0x04 +#define MC_CNTL 0x5 +#define MEM_NUM_CHANNELS_MASK 0x00000003 +#define MC_STATUS 0x08 +#define MC_STATUS_IDLE (1 << 4) +#define MC_MISC_LAT_TIMER 0x09 +#define MC_CPR_INIT_LAT_MASK 0x0000000F +#define MC_VF_INIT_LAT_MASK 0x000000F0 +#define MC_DISP0R_INIT_LAT_MASK 0x00000F00 +#define MC_DISP0R_INIT_LAT_SHIFT 8 +#define MC_DISP1R_INIT_LAT_MASK 0x0000F000 +#define MC_DISP1R_INIT_LAT_SHIFT 12 +#define MC_FIXED_INIT_LAT_MASK 0x000F0000 +#define MC_E2R_INIT_LAT_MASK 0x00F00000 +#define SAME_PAGE_PRIO_MASK 0x0F000000 +#define MC_GLOBW_INIT_LAT_MASK 0xF0000000 + + +/* + * PM4 packet + */ +#define CP_PACKET0 0x00000000 +#define PACKET0_BASE_INDEX_SHIFT 0 +#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) +#define PACKET0_COUNT_SHIFT 16 +#define PACKET0_COUNT_MASK (0x3fff << 16) +#define CP_PACKET1 0x40000000 +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) +#define CP_PACKET3 0xC0000000 +#define PACKET3_IT_OPCODE_SHIFT 8 +#define PACKET3_IT_OPCODE_MASK (0xff << 8) +#define PACKET3_COUNT_SHIFT 16 +#define PACKET3_COUNT_MASK (0x3fff << 16) +/* PACKET3 op code */ +#define PACKET3_NOP 0x10 +#define PACKET3_3D_DRAW_VBUF 0x28 +#define PACKET3_3D_DRAW_IMMD 0x29 +#define PACKET3_3D_DRAW_INDX 0x2A +#define PACKET3_3D_LOAD_VBPNTR 0x2F +#define PACKET3_INDX_BUFFER 0x33 +#define PACKET3_3D_DRAW_VBUF_2 0x34 +#define PACKET3_3D_DRAW_IMMD_2 0x35 +#define PACKET3_3D_DRAW_INDX_2 0x36 +#define PACKET3_BITBLT_MULTI 0x9B + +#define PACKET0(reg, n) (CP_PACKET0 | \ + REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ + REG_SET(PACKET0_COUNT, (n))) +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) +#define PACKET3(op, n) (CP_PACKET3 | \ + REG_SET(PACKET3_IT_OPCODE, (op)) | \ + REG_SET(PACKET3_COUNT, (n))) + +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) +#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) + +#endif + diff --git a/drivers/gpu/drm/radeon/rv515r.h b/drivers/gpu/drm/radeon/rv515r.h deleted file mode 100644 index f3cf840..0000000 --- a/drivers/gpu/drm/radeon/rv515r.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright 2008 Advanced Micro Devices, Inc. - * Copyright 2008 Red Hat Inc. - * Copyright 2009 Jerome Glisse. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Dave Airlie - * Alex Deucher - * Jerome Glisse - */ -#ifndef RV515R_H -#define RV515R_H - -/* RV515 registers */ -#define PCIE_INDEX 0x0030 -#define PCIE_DATA 0x0034 -#define MC_IND_INDEX 0x0070 -#define MC_IND_WR_EN (1 << 24) -#define MC_IND_DATA 0x0074 -#define RBBM_SOFT_RESET 0x00F0 -#define CONFIG_MEMSIZE 0x00F8 -#define HDP_FB_LOCATION 0x0134 -#define CP_CSQ_CNTL 0x0740 -#define CP_CSQ_MODE 0x0744 -#define CP_CSQ_ADDR 0x07F0 -#define CP_CSQ_DATA 0x07F4 -#define CP_CSQ_STAT 0x07F8 -#define CP_CSQ2_STAT 0x07FC -#define RBBM_STATUS 0x0E40 -#define DST_PIPE_CONFIG 0x170C -#define WAIT_UNTIL 0x1720 -#define WAIT_2D_IDLE (1 << 14) -#define WAIT_3D_IDLE (1 << 15) -#define WAIT_2D_IDLECLEAN (1 << 16) -#define WAIT_3D_IDLECLEAN (1 << 17) -#define ISYNC_CNTL 0x1724 -#define ISYNC_ANY2D_IDLE3D (1 << 0) -#define ISYNC_ANY3D_IDLE2D (1 << 1) -#define ISYNC_TRIG2D_IDLE3D (1 << 2) -#define ISYNC_TRIG3D_IDLE2D (1 << 3) -#define ISYNC_WAIT_IDLEGUI (1 << 4) -#define ISYNC_CPSCRATCH_IDLEGUI (1 << 5) -#define VAP_INDEX_OFFSET 0x208C -#define VAP_PVS_STATE_FLUSH_REG 0x2284 -#define GB_ENABLE 0x4008 -#define GB_MSPOS0 0x4010 -#define MS_X0_SHIFT 0 -#define MS_Y0_SHIFT 4 -#define MS_X1_SHIFT 8 -#define MS_Y1_SHIFT 12 -#define MS_X2_SHIFT 16 -#define MS_Y2_SHIFT 20 -#define MSBD0_Y_SHIFT 24 -#define MSBD0_X_SHIFT 28 -#define GB_MSPOS1 0x4014 -#define MS_X3_SHIFT 0 -#define MS_Y3_SHIFT 4 -#define MS_X4_SHIFT 8 -#define MS_Y4_SHIFT 12 -#define MS_X5_SHIFT 16 -#define MS_Y5_SHIFT 20 -#define MSBD1_SHIFT 24 -#define GB_TILE_CONFIG 0x4018 -#define ENABLE_TILING (1 << 0) -#define PIPE_COUNT_MASK 0x0000000E -#define PIPE_COUNT_SHIFT 1 -#define TILE_SIZE_8 (0 << 4) -#define TILE_SIZE_16 (1 << 4) -#define TILE_SIZE_32 (2 << 4) -#define SUBPIXEL_1_12 (0 << 16) -#define SUBPIXEL_1_16 (1 << 16) -#define GB_SELECT 0x401C -#define GB_AA_CONFIG 0x4020 -#define GB_PIPE_SELECT 0x402C -#define GA_ENHANCE 0x4274 -#define GA_DEADLOCK_CNTL (1 << 0) -#define GA_FASTSYNC_CNTL (1 << 1) -#define GA_POLY_MODE 0x4288 -#define FRONT_PTYPE_POINT (0 << 4) -#define FRONT_PTYPE_LINE (1 << 4) -#define FRONT_PTYPE_TRIANGE (2 << 4) -#define BACK_PTYPE_POINT (0 << 7) -#define BACK_PTYPE_LINE (1 << 7) -#define BACK_PTYPE_TRIANGE (2 << 7) -#define GA_ROUND_MODE 0x428C -#define GEOMETRY_ROUND_TRUNC (0 << 0) -#define GEOMETRY_ROUND_NEAREST (1 << 0) -#define COLOR_ROUND_TRUNC (0 << 2) -#define COLOR_ROUND_NEAREST (1 << 2) -#define SU_REG_DEST 0x42C8 -#define RB3D_DSTCACHE_CTLSTAT 0x4E4C -#define RB3D_DC_FLUSH (2 << 0) -#define RB3D_DC_FREE (2 << 2) -#define RB3D_DC_FINISH (1 << 4) -#define ZB_ZCACHE_CTLSTAT 0x4F18 -#define ZC_FLUSH (1 << 0) -#define ZC_FREE (1 << 1) -#define DC_LB_MEMORY_SPLIT 0x6520 -#define DC_LB_MEMORY_SPLIT_MASK 0x00000003 -#define DC_LB_MEMORY_SPLIT_SHIFT 0 -#define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 -#define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 -#define DC_LB_MEMORY_SPLIT_D1_ONLY 2 -#define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 -#define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) -#define DC_LB_DISP1_END_ADR_SHIFT 4 -#define DC_LB_DISP1_END_ADR_MASK 0x00007FF0 -#define D1MODE_PRIORITY_A_CNT 0x6548 -#define MODE_PRIORITY_MARK_MASK 0x00007FFF -#define MODE_PRIORITY_OFF (1 << 16) -#define MODE_PRIORITY_ALWAYS_ON (1 << 20) -#define MODE_PRIORITY_FORCE_MASK (1 << 24) -#define D1MODE_PRIORITY_B_CNT 0x654C -#define LB_MAX_REQ_OUTSTANDING 0x6D58 -#define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F -#define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 -#define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000 -#define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 -#define D2MODE_PRIORITY_A_CNT 0x6D48 -#define D2MODE_PRIORITY_B_CNT 0x6D4C - -/* ix[MC] registers */ -#define MC_FB_LOCATION 0x01 -#define MC_FB_START_MASK 0x0000FFFF -#define MC_FB_START_SHIFT 0 -#define MC_FB_TOP_MASK 0xFFFF0000 -#define MC_FB_TOP_SHIFT 16 -#define MC_AGP_LOCATION 0x02 -#define MC_AGP_START_MASK 0x0000FFFF -#define MC_AGP_START_SHIFT 0 -#define MC_AGP_TOP_MASK 0xFFFF0000 -#define MC_AGP_TOP_SHIFT 16 -#define MC_AGP_BASE 0x03 -#define MC_AGP_BASE_2 0x04 -#define MC_CNTL 0x5 -#define MEM_NUM_CHANNELS_MASK 0x00000003 -#define MC_STATUS 0x08 -#define MC_STATUS_IDLE (1 << 4) -#define MC_MISC_LAT_TIMER 0x09 -#define MC_CPR_INIT_LAT_MASK 0x0000000F -#define MC_VF_INIT_LAT_MASK 0x000000F0 -#define MC_DISP0R_INIT_LAT_MASK 0x00000F00 -#define MC_DISP0R_INIT_LAT_SHIFT 8 -#define MC_DISP1R_INIT_LAT_MASK 0x0000F000 -#define MC_DISP1R_INIT_LAT_SHIFT 12 -#define MC_FIXED_INIT_LAT_MASK 0x000F0000 -#define MC_E2R_INIT_LAT_MASK 0x00F00000 -#define SAME_PAGE_PRIO_MASK 0x0F000000 -#define MC_GLOBW_INIT_LAT_MASK 0xF0000000 - - -#endif - diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 21d8ffd..57765f6 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -25,100 +25,975 @@ * Alex Deucher * Jerome Glisse */ +#include +#include #include "drmP.h" -#include "radeon_reg.h" #include "radeon.h" +#include "radeon_share.h" +#include "rv770d.h" +#include "avivod.h" +#include "atom.h" -/* rv770,rv730,rv710 depends on : */ -void rs600_mc_disable_clients(struct radeon_device *rdev); +#define R700_PFP_UCODE_SIZE 848 +#define R700_PM4_UCODE_SIZE 1360 -/* This files gather functions specifics to: - * rv770,rv730,rv710 - * - * Some of these functions might be used by newer ASICs. - */ -int rv770_mc_wait_for_idle(struct radeon_device *rdev); -void rv770_gpu_init(struct radeon_device *rdev); +static void rv770_gpu_init(struct radeon_device *rdev); +void rv770_fini(struct radeon_device *rdev); /* - * MC + * GART */ -int rv770_mc_init(struct radeon_device *rdev) +int rv770_pcie_gart_enable(struct radeon_device *rdev) { - uint32_t tmp; + u32 tmp; + int r, i; - rv770_gpu_init(rdev); + /* Initialize common gart structure */ + r = radeon_gart_init(rdev); + if (r) { + return r; + } + rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; + r = radeon_gart_table_vram_alloc(rdev); + if (r) { + return r; + } + for (i = 0; i < rdev->gart.num_gpu_pages; i++) + r600_gart_clear_page(rdev, i); + /* Setup L2 cache */ + WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | + ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | + EFFECTIVE_L2_QUEUE_SIZE(7)); + WREG32(VM_L2_CNTL2, 0); + WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); + /* Setup TLB control */ + tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | + SYSTEM_ACCESS_MODE_NOT_IN_SYS | + SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | + EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); + WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); + WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); + WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12); + WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); + WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); + WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, + (u32)(rdev->dummy_page.addr >> 12)); + for (i = 1; i < 7; i++) + WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); - /* setup the gart before changing location so we can ask to - * discard unmapped mc request - */ - /* FIXME: disable out of gart access */ - tmp = rdev->mc.gtt_location / 4096; - tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp); - WREG32(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp); - tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096; - tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp); - WREG32(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp); - - rs600_mc_disable_clients(rdev); - if (rv770_mc_wait_for_idle(rdev)) { - printk(KERN_WARNING "Failed to wait MC idle while " - "programming pipes. Bad things might happen.\n"); - } - - tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; - tmp = REG_SET(R700_MC_FB_TOP, tmp >> 24); - tmp |= REG_SET(R700_MC_FB_BASE, rdev->mc.vram_location >> 24); - WREG32(R700_MC_VM_FB_LOCATION, tmp); - tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; - tmp = REG_SET(R700_MC_AGP_TOP, tmp >> 22); - WREG32(R700_MC_VM_AGP_TOP, tmp); - tmp = REG_SET(R700_MC_AGP_BOT, rdev->mc.gtt_location >> 22); - WREG32(R700_MC_VM_AGP_BOT, tmp); + r600_pcie_gart_tlb_flush(rdev); + rdev->gart.ready = true; return 0; } -void rv770_mc_fini(struct radeon_device *rdev) +void rv770_pcie_gart_disable(struct radeon_device *rdev) { - /* FIXME: implement */ + u32 tmp; + int i; + + /* Clear ptes*/ + for (i = 0; i < rdev->gart.num_gpu_pages; i++) + r600_gart_clear_page(rdev, i); + r600_pcie_gart_tlb_flush(rdev); + /* Disable all tables */ + for (i = 0; i < 7; i++) + WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); + + /* Setup L2 cache */ + WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | + EFFECTIVE_L2_QUEUE_SIZE(7)); + WREG32(VM_L2_CNTL2, 0); + WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); + /* Setup TLB control */ + tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); + WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); + WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); } /* - * Global GPU functions + * MC */ -void rv770_errata(struct radeon_device *rdev) +static void rv770_mc_resume(struct radeon_device *rdev) { - rdev->pll_errata = 0; + u32 d1vga_control, d2vga_control; + u32 vga_render_control, vga_hdp_control; + u32 d1crtc_control, d2crtc_control; + u32 new_d1grph_primary, new_d1grph_secondary; + u32 new_d2grph_primary, new_d2grph_secondary; + u64 old_vram_start; + u32 tmp; + int i, j; + + /* Initialize HDP */ + for (i = 0, j = 0; i < 32; i++, j += 0x18) { + WREG32((0x2c14 + j), 0x00000000); + WREG32((0x2c18 + j), 0x00000000); + WREG32((0x2c1c + j), 0x00000000); + WREG32((0x2c20 + j), 0x00000000); + WREG32((0x2c24 + j), 0x00000000); + } + WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); + + d1vga_control = RREG32(D1VGA_CONTROL); + d2vga_control = RREG32(D2VGA_CONTROL); + vga_render_control = RREG32(VGA_RENDER_CONTROL); + vga_hdp_control = RREG32(VGA_HDP_CONTROL); + d1crtc_control = RREG32(D1CRTC_CONTROL); + d2crtc_control = RREG32(D2CRTC_CONTROL); + old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; + new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS); + new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS); + new_d1grph_primary += rdev->mc.vram_start - old_vram_start; + new_d1grph_secondary += rdev->mc.vram_start - old_vram_start; + new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS); + new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS); + new_d2grph_primary += rdev->mc.vram_start - old_vram_start; + new_d2grph_secondary += rdev->mc.vram_start - old_vram_start; + + /* Stop all video */ + WREG32(D1VGA_CONTROL, 0); + WREG32(D2VGA_CONTROL, 0); + WREG32(VGA_RENDER_CONTROL, 0); + WREG32(D1CRTC_UPDATE_LOCK, 1); + WREG32(D2CRTC_UPDATE_LOCK, 1); + WREG32(D1CRTC_CONTROL, 0); + WREG32(D2CRTC_CONTROL, 0); + WREG32(D1CRTC_UPDATE_LOCK, 0); + WREG32(D2CRTC_UPDATE_LOCK, 0); + + mdelay(1); + if (r600_mc_wait_for_idle(rdev)) { + printk(KERN_WARNING "[drm] MC not idle !\n"); + } + + /* Lockout access through VGA aperture*/ + WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); + + /* Update configuration */ + WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); + WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12); + WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); + tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16; + tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); + WREG32(MC_VM_FB_LOCATION, tmp); + WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); + WREG32(HDP_NONSURFACE_INFO, (2 << 7)); + WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); + if (rdev->flags & RADEON_IS_AGP) { + WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16); + WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); + WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); + } else { + WREG32(MC_VM_AGP_BASE, 0); + WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); + WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); + } + WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary); + WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary); + WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary); + WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary); + WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); + + /* Unlock host access */ + WREG32(VGA_HDP_CONTROL, vga_hdp_control); + + mdelay(1); + if (r600_mc_wait_for_idle(rdev)) { + printk(KERN_WARNING "[drm] MC not idle !\n"); + } + + /* Restore video state */ + WREG32(D1CRTC_UPDATE_LOCK, 1); + WREG32(D2CRTC_UPDATE_LOCK, 1); + WREG32(D1CRTC_CONTROL, d1crtc_control); + WREG32(D2CRTC_CONTROL, d2crtc_control); + WREG32(D1CRTC_UPDATE_LOCK, 0); + WREG32(D2CRTC_UPDATE_LOCK, 0); + WREG32(D1VGA_CONTROL, d1vga_control); + WREG32(D2VGA_CONTROL, d2vga_control); + WREG32(VGA_RENDER_CONTROL, vga_render_control); } -int rv770_mc_wait_for_idle(struct radeon_device *rdev) + +/* + * CP. + */ +void r700_cp_stop(struct radeon_device *rdev) { - /* FIXME: implement */ - return 0; + WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); } -void rv770_gpu_init(struct radeon_device *rdev) + +static int rv770_cp_load_microcode(struct radeon_device *rdev) { - /* FIXME: implement */ + const __be32 *fw_data; + int i; + + if (!rdev->me_fw || !rdev->pfp_fw) + return -EINVAL; + + r700_cp_stop(rdev); + WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); + + /* Reset cp */ + WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); + RREG32(GRBM_SOFT_RESET); + mdelay(15); + WREG32(GRBM_SOFT_RESET, 0); + + fw_data = (const __be32 *)rdev->pfp_fw->data; + WREG32(CP_PFP_UCODE_ADDR, 0); + for (i = 0; i < R700_PFP_UCODE_SIZE; i++) + WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); + WREG32(CP_PFP_UCODE_ADDR, 0); + + fw_data = (const __be32 *)rdev->me_fw->data; + WREG32(CP_ME_RAM_WADDR, 0); + for (i = 0; i < R700_PM4_UCODE_SIZE; i++) + WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); + + WREG32(CP_PFP_UCODE_ADDR, 0); + WREG32(CP_ME_RAM_WADDR, 0); + WREG32(CP_ME_RAM_RADDR, 0); + return 0; } /* - * VRAM info + * Core functions */ -void rv770_vram_get_type(struct radeon_device *rdev) +static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, + u32 num_backends, + u32 backend_disable_mask) { - /* FIXME: implement */ + u32 backend_map = 0; + u32 enabled_backends_mask; + u32 enabled_backends_count; + u32 cur_pipe; + u32 swizzle_pipe[R7XX_MAX_PIPES]; + u32 cur_backend; + u32 i; + + if (num_tile_pipes > R7XX_MAX_PIPES) + num_tile_pipes = R7XX_MAX_PIPES; + if (num_tile_pipes < 1) + num_tile_pipes = 1; + if (num_backends > R7XX_MAX_BACKENDS) + num_backends = R7XX_MAX_BACKENDS; + if (num_backends < 1) + num_backends = 1; + + enabled_backends_mask = 0; + enabled_backends_count = 0; + for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { + if (((backend_disable_mask >> i) & 1) == 0) { + enabled_backends_mask |= (1 << i); + ++enabled_backends_count; + } + if (enabled_backends_count == num_backends) + break; + } + + if (enabled_backends_count == 0) { + enabled_backends_mask = 1; + enabled_backends_count = 1; + } + + if (enabled_backends_count != num_backends) + num_backends = enabled_backends_count; + + memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); + switch (num_tile_pipes) { + case 1: + swizzle_pipe[0] = 0; + break; + case 2: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 1; + break; + case 3: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 1; + break; + case 4: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 3; + swizzle_pipe[3] = 1; + break; + case 5: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 1; + swizzle_pipe[4] = 3; + break; + case 6: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 5; + swizzle_pipe[4] = 3; + swizzle_pipe[5] = 1; + break; + case 7: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 6; + swizzle_pipe[4] = 3; + swizzle_pipe[5] = 1; + swizzle_pipe[6] = 5; + break; + case 8: + swizzle_pipe[0] = 0; + swizzle_pipe[1] = 2; + swizzle_pipe[2] = 4; + swizzle_pipe[3] = 6; + swizzle_pipe[4] = 3; + swizzle_pipe[5] = 1; + swizzle_pipe[6] = 7; + swizzle_pipe[7] = 5; + break; + } + + cur_backend = 0; + for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { + while (((1 << cur_backend) & enabled_backends_mask) == 0) + cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; + + backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); + + cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; + } + + return backend_map; } -void rv770_vram_info(struct radeon_device *rdev) +static void rv770_gpu_init(struct radeon_device *rdev) { - rv770_vram_get_type(rdev); + int i, j, num_qd_pipes; + u32 sx_debug_1; + u32 smx_dc_ctl0; + u32 num_gs_verts_per_thread; + u32 vgt_gs_per_es; + u32 gs_prim_buffer_depth = 0; + u32 sq_ms_fifo_sizes; + u32 sq_config; + u32 sq_thread_resource_mgmt; + u32 hdp_host_path_cntl; + u32 sq_dyn_gpr_size_simd_ab_0; + u32 backend_map; + u32 gb_tiling_config = 0; + u32 cc_rb_backend_disable = 0; + u32 cc_gc_shader_pipe_config = 0; + u32 mc_arb_ramcfg; + u32 db_debug4; - /* FIXME: implement */ + /* setup chip specs */ + switch (rdev->family) { + case CHIP_RV770: + rdev->config.rv770.max_pipes = 4; + rdev->config.rv770.max_tile_pipes = 8; + rdev->config.rv770.max_simds = 10; + rdev->config.rv770.max_backends = 4; + rdev->config.rv770.max_gprs = 256; + rdev->config.rv770.max_threads = 248; + rdev->config.rv770.max_stack_entries = 512; + rdev->config.rv770.max_hw_contexts = 8; + rdev->config.rv770.max_gs_threads = 16 * 2; + rdev->config.rv770.sx_max_export_size = 128; + rdev->config.rv770.sx_max_export_pos_size = 16; + rdev->config.rv770.sx_max_export_smx_size = 112; + rdev->config.rv770.sq_num_cf_insts = 2; + + rdev->config.rv770.sx_num_of_sets = 7; + rdev->config.rv770.sc_prim_fifo_size = 0xF9; + rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; + rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; + break; + case CHIP_RV730: + rdev->config.rv770.max_pipes = 2; + rdev->config.rv770.max_tile_pipes = 4; + rdev->config.rv770.max_simds = 8; + rdev->config.rv770.max_backends = 2; + rdev->config.rv770.max_gprs = 128; + rdev->config.rv770.max_threads = 248; + rdev->config.rv770.max_stack_entries = 256; + rdev->config.rv770.max_hw_contexts = 8; + rdev->config.rv770.max_gs_threads = 16 * 2; + rdev->config.rv770.sx_max_export_size = 256; + rdev->config.rv770.sx_max_export_pos_size = 32; + rdev->config.rv770.sx_max_export_smx_size = 224; + rdev->config.rv770.sq_num_cf_insts = 2; + + rdev->config.rv770.sx_num_of_sets = 7; + rdev->config.rv770.sc_prim_fifo_size = 0xf9; + rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; + rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; + if (rdev->config.rv770.sx_max_export_pos_size > 16) { + rdev->config.rv770.sx_max_export_pos_size -= 16; + rdev->config.rv770.sx_max_export_smx_size += 16; + } + break; + case CHIP_RV710: + rdev->config.rv770.max_pipes = 2; + rdev->config.rv770.max_tile_pipes = 2; + rdev->config.rv770.max_simds = 2; + rdev->config.rv770.max_backends = 1; + rdev->config.rv770.max_gprs = 256; + rdev->config.rv770.max_threads = 192; + rdev->config.rv770.max_stack_entries = 256; + rdev->config.rv770.max_hw_contexts = 4; + rdev->config.rv770.max_gs_threads = 8 * 2; + rdev->config.rv770.sx_max_export_size = 128; + rdev->config.rv770.sx_max_export_pos_size = 16; + rdev->config.rv770.sx_max_export_smx_size = 112; + rdev->config.rv770.sq_num_cf_insts = 1; + + rdev->config.rv770.sx_num_of_sets = 7; + rdev->config.rv770.sc_prim_fifo_size = 0x40; + rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; + rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; + break; + case CHIP_RV740: + rdev->config.rv770.max_pipes = 4; + rdev->config.rv770.max_tile_pipes = 4; + rdev->config.rv770.max_simds = 8; + rdev->config.rv770.max_backends = 4; + rdev->config.rv770.max_gprs = 256; + rdev->config.rv770.max_threads = 248; + rdev->config.rv770.max_stack_entries = 512; + rdev->config.rv770.max_hw_contexts = 8; + rdev->config.rv770.max_gs_threads = 16 * 2; + rdev->config.rv770.sx_max_export_size = 256; + rdev->config.rv770.sx_max_export_pos_size = 32; + rdev->config.rv770.sx_max_export_smx_size = 224; + rdev->config.rv770.sq_num_cf_insts = 2; + + rdev->config.rv770.sx_num_of_sets = 7; + rdev->config.rv770.sc_prim_fifo_size = 0x100; + rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; + rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; + + if (rdev->config.rv770.sx_max_export_pos_size > 16) { + rdev->config.rv770.sx_max_export_pos_size -= 16; + rdev->config.rv770.sx_max_export_smx_size += 16; + } + break; + default: + break; + } + + /* Initialize HDP */ + j = 0; + for (i = 0; i < 32; i++) { + WREG32((0x2c14 + j), 0x00000000); + WREG32((0x2c18 + j), 0x00000000); + WREG32((0x2c1c + j), 0x00000000); + WREG32((0x2c20 + j), 0x00000000); + WREG32((0x2c24 + j), 0x00000000); + j += 0x18; + } + + WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); + + /* setup tiling, simd, pipe config */ + mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); + + switch (rdev->config.rv770.max_tile_pipes) { + case 1: + gb_tiling_config |= PIPE_TILING(0); + break; + case 2: + gb_tiling_config |= PIPE_TILING(1); + break; + case 4: + gb_tiling_config |= PIPE_TILING(2); + break; + case 8: + gb_tiling_config |= PIPE_TILING(3); + break; + default: + break; + } + + if (rdev->family == CHIP_RV770) + gb_tiling_config |= BANK_TILING(1); + else + gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK); + + gb_tiling_config |= GROUP_SIZE(0); + + if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) { + gb_tiling_config |= ROW_TILING(3); + gb_tiling_config |= SAMPLE_SPLIT(3); + } else { + gb_tiling_config |= + ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); + gb_tiling_config |= + SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); + } + + gb_tiling_config |= BANK_SWAPS(1); + + backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes, + rdev->config.rv770.max_backends, + (0xff << rdev->config.rv770.max_backends) & 0xff); + gb_tiling_config |= BACKEND_MAP(backend_map); + + cc_gc_shader_pipe_config = + INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); + cc_gc_shader_pipe_config |= + INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); + + cc_rb_backend_disable = + BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); + + WREG32(GB_TILING_CONFIG, gb_tiling_config); + WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); + WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); + + WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); + WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); + WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); + + WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); + WREG32(CGTS_SYS_TCC_DISABLE, 0); + WREG32(CGTS_TCC_DISABLE, 0); + WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); + WREG32(CGTS_USER_TCC_DISABLE, 0); + + num_qd_pipes = + R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK); + WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); + WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); + + /* set HW defaults for 3D engine */ + WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | + ROQ_IB2_START(0x2b))); + + WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); + + WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | + SYNC_GRADIENT | + SYNC_WALKER | + SYNC_ALIGNER)); + + sx_debug_1 = RREG32(SX_DEBUG_1); + sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; + WREG32(SX_DEBUG_1, sx_debug_1); + + smx_dc_ctl0 = RREG32(SMX_DC_CTL0); + smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); + smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); + WREG32(SMX_DC_CTL0, smx_dc_ctl0); + + WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | + GS_FLUSH_CTL(4) | + ACK_FLUSH_CTL(3) | + SYNC_FLUSH_CTL)); + + if (rdev->family == CHIP_RV770) + WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f)); + else { + db_debug4 = RREG32(DB_DEBUG4); + db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; + WREG32(DB_DEBUG4, db_debug4); + } + + WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | + POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | + SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); + + WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | + SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | + SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); + + WREG32(PA_SC_MULTI_CHIP_CNTL, 0); + + WREG32(VGT_NUM_INSTANCES, 1); + + WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); + + WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); + + WREG32(CP_PERFMON_CNTL, 0); + + sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | + DONE_FIFO_HIWATER(0xe0) | + ALU_UPDATE_FIFO_HIWATER(0x8)); + switch (rdev->family) { + case CHIP_RV770: + sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); + break; + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + default: + sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); + break; + } + WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); + + /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT + * should be adjusted as needed by the 2D/3D drivers. This just sets default values + */ + sq_config = RREG32(SQ_CONFIG); + sq_config &= ~(PS_PRIO(3) | + VS_PRIO(3) | + GS_PRIO(3) | + ES_PRIO(3)); + sq_config |= (DX9_CONSTS | + VC_ENABLE | + EXPORT_SRC_C | + PS_PRIO(0) | + VS_PRIO(1) | + GS_PRIO(2) | + ES_PRIO(3)); + if (rdev->family == CHIP_RV710) + /* no vertex cache */ + sq_config &= ~VC_ENABLE; + + WREG32(SQ_CONFIG, sq_config); + + WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | + NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | + NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); + + WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | + NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); + + sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | + NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | + NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); + if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) + sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); + else + sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); + WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); + + WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | + NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); + + WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | + NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); + + sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | + SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | + SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | + SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); + + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); + WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); + + WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | + FORCE_EOV_MAX_REZ_CNT(255))); + + if (rdev->family == CHIP_RV710) + WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | + AUTO_INVLD_EN(ES_AND_GS_AUTO))); + else + WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | + AUTO_INVLD_EN(ES_AND_GS_AUTO))); + + switch (rdev->family) { + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV740: + gs_prim_buffer_depth = 384; + break; + case CHIP_RV710: + gs_prim_buffer_depth = 128; + break; + default: + break; + } + + num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; + vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; + /* Max value for this is 256 */ + if (vgt_gs_per_es > 256) + vgt_gs_per_es = 256; + + WREG32(VGT_ES_PER_GS, 128); + WREG32(VGT_GS_PER_ES, vgt_gs_per_es); + WREG32(VGT_GS_PER_VS, 2); + + /* more default values. 2D/3D driver should adjust as needed */ + WREG32(VGT_GS_VERTEX_REUSE, 16); + WREG32(PA_SC_LINE_STIPPLE_STATE, 0); + WREG32(VGT_STRMOUT_EN, 0); + WREG32(SX_MISC, 0); + WREG32(PA_SC_MODE_CNTL, 0); + WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); + WREG32(PA_SC_AA_CONFIG, 0); + WREG32(PA_SC_CLIPRECT_RULE, 0xffff); + WREG32(PA_SC_LINE_STIPPLE, 0); + WREG32(SPI_INPUT_Z, 0); + WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); + WREG32(CB_COLOR7_FRAG, 0); + + /* clear render buffer base addresses */ + WREG32(CB_COLOR0_BASE, 0); + WREG32(CB_COLOR1_BASE, 0); + WREG32(CB_COLOR2_BASE, 0); + WREG32(CB_COLOR3_BASE, 0); + WREG32(CB_COLOR4_BASE, 0); + WREG32(CB_COLOR5_BASE, 0); + WREG32(CB_COLOR6_BASE, 0); + WREG32(CB_COLOR7_BASE, 0); + + WREG32(TCP_CNTL, 0); + + hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); + WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); + + WREG32(PA_SC_MULTI_CHIP_CNTL, 0); + + WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | + NUM_CLIP_SEQ(3))); + +} + +int rv770_mc_init(struct radeon_device *rdev) +{ + fixed20_12 a; + u32 tmp; + int r; + + /* Get VRAM informations */ + /* FIXME: Don't know how to determine vram width, need to check + * vram_width usage + */ + rdev->mc.vram_width = 128; + rdev->mc.vram_is_ddr = true; /* Could aper size report 0 ? */ rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); + /* Setup GPU memory space */ + rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); + rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); + if (rdev->flags & RADEON_IS_AGP) { + r = radeon_agp_init(rdev); + if (r) + return r; + /* gtt_size is setup by radeon_agp_init */ + rdev->mc.gtt_location = rdev->mc.agp_base; + tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; + /* Try to put vram before or after AGP because we + * we want SYSTEM_APERTURE to cover both VRAM and + * AGP so that GPU can catch out of VRAM/AGP access + */ + if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { + /* Enought place before */ + rdev->mc.vram_location = rdev->mc.gtt_location - + rdev->mc.mc_vram_size; + } else if (tmp > rdev->mc.mc_vram_size) { + /* Enought place after */ + rdev->mc.vram_location = rdev->mc.gtt_location + + rdev->mc.gtt_size; + } else { + /* Try to setup VRAM then AGP might not + * not work on some card + */ + rdev->mc.vram_location = 0x00000000UL; + rdev->mc.gtt_location = rdev->mc.mc_vram_size; + } + } else { + rdev->mc.vram_location = 0x00000000UL; + rdev->mc.gtt_location = rdev->mc.mc_vram_size; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; + } + rdev->mc.vram_start = rdev->mc.vram_location; + rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size; + rdev->mc.gtt_start = rdev->mc.gtt_location; + rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size; + /* FIXME: we should enforce default clock in case GPU is not in + * default setup + */ + a.full = rfixed_const(100); + rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); + rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); + return 0; +} +int rv770_gpu_reset(struct radeon_device *rdev) +{ + /* FIXME: implement */ + return 0; +} + +int rv770_resume(struct radeon_device *rdev) +{ + int r; + + rv770_mc_resume(rdev); + r = rv770_pcie_gart_enable(rdev); + if (r) + return r; + rv770_gpu_init(rdev); + r = radeon_ring_init(rdev, rdev->cp.ring_size); + if (r) + return r; + r = rv770_cp_load_microcode(rdev); + if (r) + return r; + r = r600_cp_resume(rdev); + if (r) + return r; + r = r600_wb_init(rdev); + if (r) + return r; + return 0; +} + +int rv770_suspend(struct radeon_device *rdev) +{ + /* FIXME: we should wait for ring to be empty */ + r700_cp_stop(rdev); + return 0; +} + +/* Plan is to move initialization in that function and use + * helper function so that radeon_device_init pretty much + * do nothing more than calling asic specific function. This + * should also allow to remove a bunch of callback function + * like vram_info. + */ +int rv770_init(struct radeon_device *rdev) +{ + int r; + + rdev->new_init_path = true; + r = radeon_dummy_page_init(rdev); + if (r) + return r; + /* This don't do much */ + r = radeon_gem_init(rdev); + if (r) + return r; + /* Read BIOS */ + if (!radeon_get_bios(rdev)) { + if (ASIC_IS_AVIVO(rdev)) + return -EINVAL; + } + /* Must be an ATOMBIOS */ + if (!rdev->is_atom_bios) + return -EINVAL; + r = radeon_atombios_init(rdev); + if (r) + return r; + /* Post card if necessary */ + if (!r600_card_posted(rdev) && rdev->bios) { + DRM_INFO("GPU not posted. posting now...\n"); + atom_asic_init(rdev->mode_info.atom_context); + } + /* Initialize scratch registers */ + r600_scratch_init(rdev); + /* Initialize surface registers */ + radeon_surface_init(rdev); + r = radeon_clocks_init(rdev); + if (r) + return r; + /* Fence driver */ + r = radeon_fence_driver_init(rdev); + if (r) + return r; + r = rv770_mc_init(rdev); + if (r) { + if (rdev->flags & RADEON_IS_AGP) { + /* Retry with disabling AGP */ + rv770_fini(rdev); + rdev->flags &= ~RADEON_IS_AGP; + return rv770_init(rdev); + } + return r; + } + /* Memory manager */ + r = radeon_object_init(rdev); + if (r) + return r; + rdev->cp.ring_obj = NULL; + r600_ring_init(rdev, 1024 * 1024); + + if (!rdev->me_fw || !rdev->pfp_fw) { + r = r600_cp_init_microcode(rdev); + if (r) { + DRM_ERROR("Failed to load firmware!\n"); + return r; + } + } + + r = rv770_resume(rdev); + if (r) { + if (rdev->flags & RADEON_IS_AGP) { + /* Retry with disabling AGP */ + rv770_fini(rdev); + rdev->flags &= ~RADEON_IS_AGP; + return rv770_init(rdev); + } + return r; + } + r = r600_blit_init(rdev); + if (r) { + DRM_ERROR("radeon: failled blitter (%d).\n", r); + return r; + } + r = radeon_ib_pool_init(rdev); + if (r) { + DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); + return r; + } + r = radeon_ib_test(rdev); + if (r) { + DRM_ERROR("radeon: failled testing IB (%d).\n", r); + return r; + } + return 0; +} + +void rv770_fini(struct radeon_device *rdev) +{ + r600_blit_fini(rdev); + radeon_ring_fini(rdev); + rv770_pcie_gart_disable(rdev); + radeon_gart_table_vram_free(rdev); + radeon_gart_fini(rdev); + radeon_gem_fini(rdev); + radeon_fence_driver_fini(rdev); + radeon_clocks_fini(rdev); +#if __OS_HAS_AGP + if (rdev->flags & RADEON_IS_AGP) + radeon_agp_fini(rdev); +#endif + radeon_object_fini(rdev); + if (rdev->is_atom_bios) { + radeon_atombios_fini(rdev); + } else { + radeon_combios_fini(rdev); + } + kfree(rdev->bios); + rdev->bios = NULL; + radeon_dummy_page_fini(rdev); } diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h new file mode 100644 index 0000000..4b9c3d6 --- /dev/null +++ b/drivers/gpu/drm/radeon/rv770d.h @@ -0,0 +1,341 @@ +/* + * Copyright 2009 Advanced Micro Devices, Inc. + * Copyright 2009 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef RV770_H +#define RV770_H + +#define R7XX_MAX_SH_GPRS 256 +#define R7XX_MAX_TEMP_GPRS 16 +#define R7XX_MAX_SH_THREADS 256 +#define R7XX_MAX_SH_STACK_ENTRIES 4096 +#define R7XX_MAX_BACKENDS 8 +#define R7XX_MAX_BACKENDS_MASK 0xff +#define R7XX_MAX_SIMDS 16 +#define R7XX_MAX_SIMDS_MASK 0xffff +#define R7XX_MAX_PIPES 8 +#define R7XX_MAX_PIPES_MASK 0xff + +/* Registers */ +#define CB_COLOR0_BASE 0x28040 +#define CB_COLOR1_BASE 0x28044 +#define CB_COLOR2_BASE 0x28048 +#define CB_COLOR3_BASE 0x2804C +#define CB_COLOR4_BASE 0x28050 +#define CB_COLOR5_BASE 0x28054 +#define CB_COLOR6_BASE 0x28058 +#define CB_COLOR7_BASE 0x2805C +#define CB_COLOR7_FRAG 0x280FC + +#define CC_GC_SHADER_PIPE_CONFIG 0x8950 +#define CC_RB_BACKEND_DISABLE 0x98F4 +#define BACKEND_DISABLE(x) ((x) << 16) +#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 + +#define CGTS_SYS_TCC_DISABLE 0x3F90 +#define CGTS_TCC_DISABLE 0x9148 +#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 +#define CGTS_USER_TCC_DISABLE 0x914C + +#define CONFIG_MEMSIZE 0x5428 + +#define CP_ME_CNTL 0x86D8 +#define CP_ME_HALT (1<<28) +#define CP_PFP_HALT (1<<26) +#define CP_ME_RAM_DATA 0xC160 +#define CP_ME_RAM_RADDR 0xC158 +#define CP_ME_RAM_WADDR 0xC15C +#define CP_MEQ_THRESHOLDS 0x8764 +#define STQ_SPLIT(x) ((x) << 0) +#define CP_PERFMON_CNTL 0x87FC +#define CP_PFP_UCODE_ADDR 0xC150 +#define CP_PFP_UCODE_DATA 0xC154 +#define CP_QUEUE_THRESHOLDS 0x8760 +#define ROQ_IB1_START(x) ((x) << 0) +#define ROQ_IB2_START(x) ((x) << 8) +#define CP_RB_CNTL 0xC104 +#define RB_BUFSZ(x) ((x)<<0) +#define RB_BLKSZ(x) ((x)<<8) +#define RB_NO_UPDATE (1<<27) +#define RB_RPTR_WR_ENA (1<<31) +#define BUF_SWAP_32BIT (2 << 16) +#define CP_RB_RPTR 0x8700 +#define CP_RB_RPTR_ADDR 0xC10C +#define CP_RB_RPTR_ADDR_HI 0xC110 +#define CP_RB_RPTR_WR 0xC108 +#define CP_RB_WPTR 0xC114 +#define CP_RB_WPTR_ADDR 0xC118 +#define CP_RB_WPTR_ADDR_HI 0xC11C +#define CP_RB_WPTR_DELAY 0x8704 +#define CP_SEM_WAIT_TIMER 0x85BC + +#define DB_DEBUG3 0x98B0 +#define DB_CLK_OFF_DELAY(x) ((x) << 11) +#define DB_DEBUG4 0x9B8C +#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) + +#define DCP_TILING_CONFIG 0x6CA0 +#define PIPE_TILING(x) ((x) << 1) +#define BANK_TILING(x) ((x) << 4) +#define GROUP_SIZE(x) ((x) << 6) +#define ROW_TILING(x) ((x) << 8) +#define BANK_SWAPS(x) ((x) << 11) +#define SAMPLE_SPLIT(x) ((x) << 14) +#define BACKEND_MAP(x) ((x) << 16) + +#define GB_TILING_CONFIG 0x98F0 + +#define GC_USER_SHADER_PIPE_CONFIG 0x8954 +#define INACTIVE_QD_PIPES(x) ((x) << 8) +#define INACTIVE_QD_PIPES_MASK 0x0000FF00 +#define INACTIVE_SIMDS(x) ((x) << 16) +#define INACTIVE_SIMDS_MASK 0x00FF0000 + +#define GRBM_CNTL 0x8000 +#define GRBM_READ_TIMEOUT(x) ((x) << 0) +#define GRBM_SOFT_RESET 0x8020 +#define SOFT_RESET_CP (1<<0) +#define GRBM_STATUS 0x8010 +#define CMDFIFO_AVAIL_MASK 0x0000000F +#define GUI_ACTIVE (1<<31) +#define GRBM_STATUS2 0x8014 + +#define HDP_HOST_PATH_CNTL 0x2C00 +#define HDP_NONSURFACE_BASE 0x2C04 +#define HDP_NONSURFACE_INFO 0x2C08 +#define HDP_NONSURFACE_SIZE 0x2C0C +#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 +#define HDP_TILING_CONFIG 0x2F3C + +#define MC_ARB_RAMCFG 0x2760 +#define NOOFBANK_SHIFT 0 +#define NOOFBANK_MASK 0x00000003 +#define NOOFRANK_SHIFT 2 +#define NOOFRANK_MASK 0x00000004 +#define NOOFROWS_SHIFT 3 +#define NOOFROWS_MASK 0x00000038 +#define NOOFCOLS_SHIFT 6 +#define NOOFCOLS_MASK 0x000000C0 +#define CHANSIZE_SHIFT 8 +#define CHANSIZE_MASK 0x00000100 +#define BURSTLENGTH_SHIFT 9 +#define BURSTLENGTH_MASK 0x00000200 +#define MC_VM_AGP_TOP 0x2028 +#define MC_VM_AGP_BOT 0x202C +#define MC_VM_AGP_BASE 0x2030 +#define MC_VM_FB_LOCATION 0x2024 +#define MC_VM_MB_L1_TLB0_CNTL 0x2234 +#define MC_VM_MB_L1_TLB1_CNTL 0x2238 +#define MC_VM_MB_L1_TLB2_CNTL 0x223C +#define MC_VM_MB_L1_TLB3_CNTL 0x2240 +#define ENABLE_L1_TLB (1 << 0) +#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) +#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) +#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) +#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) +#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) +#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) +#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) +#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) +#define MC_VM_MD_L1_TLB0_CNTL 0x2654 +#define MC_VM_MD_L1_TLB1_CNTL 0x2658 +#define MC_VM_MD_L1_TLB2_CNTL 0x265C +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 + +#define PA_CL_ENHANCE 0x8A14 +#define CLIP_VTX_REORDER_ENA (1 << 0) +#define NUM_CLIP_SEQ(x) ((x) << 1) +#define PA_SC_AA_CONFIG 0x28C04 +#define PA_SC_CLIPRECT_RULE 0x2820C +#define PA_SC_EDGERULE 0x28230 +#define PA_SC_FIFO_SIZE 0x8BCC +#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) +#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) +#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 +#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) +#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) +#define PA_SC_LINE_STIPPLE 0x28A0C +#define PA_SC_LINE_STIPPLE_STATE 0x8B10 +#define PA_SC_MODE_CNTL 0x28A4C +#define PA_SC_MULTI_CHIP_CNTL 0x8B20 +#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) + +#define SCRATCH_REG0 0x8500 +#define SCRATCH_REG1 0x8504 +#define SCRATCH_REG2 0x8508 +#define SCRATCH_REG3 0x850C +#define SCRATCH_REG4 0x8510 +#define SCRATCH_REG5 0x8514 +#define SCRATCH_REG6 0x8518 +#define SCRATCH_REG7 0x851C +#define SCRATCH_UMSK 0x8540 +#define SCRATCH_ADDR 0x8544 + +#define SMX_DC_CTL0 0xA020 +#define USE_HASH_FUNCTION (1 << 0) +#define CACHE_DEPTH(x) ((x) << 1) +#define FLUSH_ALL_ON_EVENT (1 << 10) +#define STALL_ON_EVENT (1 << 11) +#define SMX_EVENT_CTL 0xA02C +#define ES_FLUSH_CTL(x) ((x) << 0) +#define GS_FLUSH_CTL(x) ((x) << 3) +#define ACK_FLUSH_CTL(x) ((x) << 6) +#define SYNC_FLUSH_CTL (1 << 8) + +#define SPI_CONFIG_CNTL 0x9100 +#define GPR_WRITE_PRIORITY(x) ((x) << 0) +#define DISABLE_INTERP_1 (1 << 5) +#define SPI_CONFIG_CNTL_1 0x913C +#define VTX_DONE_DELAY(x) ((x) << 0) +#define INTERP_ONE_PRIM_PER_ROW (1 << 4) +#define SPI_INPUT_Z 0x286D8 +#define SPI_PS_IN_CONTROL_0 0x286CC +#define NUM_INTERP(x) ((x)<<0) +#define POSITION_ENA (1<<8) +#define POSITION_CENTROID (1<<9) +#define POSITION_ADDR(x) ((x)<<10) +#define PARAM_GEN(x) ((x)<<15) +#define PARAM_GEN_ADDR(x) ((x)<<19) +#define BARYC_SAMPLE_CNTL(x) ((x)<<26) +#define PERSP_GRADIENT_ENA (1<<28) +#define LINEAR_GRADIENT_ENA (1<<29) +#define POSITION_SAMPLE (1<<30) +#define BARYC_AT_SAMPLE_ENA (1<<31) + +#define SQ_CONFIG 0x8C00 +#define VC_ENABLE (1 << 0) +#define EXPORT_SRC_C (1 << 1) +#define DX9_CONSTS (1 << 2) +#define ALU_INST_PREFER_VECTOR (1 << 3) +#define DX10_CLAMP (1 << 4) +#define CLAUSE_SEQ_PRIO(x) ((x) << 8) +#define PS_PRIO(x) ((x) << 24) +#define VS_PRIO(x) ((x) << 26) +#define GS_PRIO(x) ((x) << 28) +#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 +#define SIMDA_RING0(x) ((x)<<0) +#define SIMDA_RING1(x) ((x)<<8) +#define SIMDB_RING0(x) ((x)<<16) +#define SIMDB_RING1(x) ((x)<<24) +#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 +#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 +#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC +#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 +#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 +#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 +#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC +#define ES_PRIO(x) ((x) << 30) +#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 +#define NUM_PS_GPRS(x) ((x) << 0) +#define NUM_VS_GPRS(x) ((x) << 16) +#define DYN_GPR_ENABLE (1 << 27) +#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) +#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 +#define NUM_GS_GPRS(x) ((x) << 0) +#define NUM_ES_GPRS(x) ((x) << 16) +#define SQ_MS_FIFO_SIZES 0x8CF0 +#define CACHE_FIFO_SIZE(x) ((x) << 0) +#define FETCH_FIFO_HIWATER(x) ((x) << 8) +#define DONE_FIFO_HIWATER(x) ((x) << 16) +#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) +#define SQ_STACK_RESOURCE_MGMT_1 0x8C10 +#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) +#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) +#define SQ_STACK_RESOURCE_MGMT_2 0x8C14 +#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) +#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) +#define SQ_THREAD_RESOURCE_MGMT 0x8C0C +#define NUM_PS_THREADS(x) ((x) << 0) +#define NUM_VS_THREADS(x) ((x) << 8) +#define NUM_GS_THREADS(x) ((x) << 16) +#define NUM_ES_THREADS(x) ((x) << 24) + +#define SX_DEBUG_1 0x9058 +#define ENABLE_NEW_SMX_ADDRESS (1 << 16) +#define SX_EXPORT_BUFFER_SIZES 0x900C +#define COLOR_BUFFER_SIZE(x) ((x) << 0) +#define POSITION_BUFFER_SIZE(x) ((x) << 8) +#define SMX_BUFFER_SIZE(x) ((x) << 16) +#define SX_MISC 0x28350 + +#define TA_CNTL_AUX 0x9508 +#define DISABLE_CUBE_WRAP (1 << 0) +#define DISABLE_CUBE_ANISO (1 << 1) +#define SYNC_GRADIENT (1 << 24) +#define SYNC_WALKER (1 << 25) +#define SYNC_ALIGNER (1 << 26) +#define BILINEAR_PRECISION_6_BIT (0 << 31) +#define BILINEAR_PRECISION_8_BIT (1 << 31) + +#define TCP_CNTL 0x9610 + +#define VGT_CACHE_INVALIDATION 0x88C4 +#define CACHE_INVALIDATION(x) ((x)<<0) +#define VC_ONLY 0 +#define TC_ONLY 1 +#define VC_AND_TC 2 +#define AUTO_INVLD_EN(x) ((x) << 6) +#define NO_AUTO 0 +#define ES_AUTO 1 +#define GS_AUTO 2 +#define ES_AND_GS_AUTO 3 +#define VGT_ES_PER_GS 0x88CC +#define VGT_GS_PER_ES 0x88C8 +#define VGT_GS_PER_VS 0x88E8 +#define VGT_GS_VERTEX_REUSE 0x88D4 +#define VGT_NUM_INSTANCES 0x8974 +#define VGT_OUT_DEALLOC_CNTL 0x28C5C +#define DEALLOC_DIST_MASK 0x0000007F +#define VGT_STRMOUT_EN 0x28AB0 +#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 +#define VTX_REUSE_DEPTH_MASK 0x000000FF + +#define VM_CONTEXT0_CNTL 0x1410 +#define ENABLE_CONTEXT (1 << 0) +#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) +#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 +#define VM_L2_CNTL 0x1400 +#define ENABLE_L2_CACHE (1 << 0) +#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) +#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) +#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) +#define VM_L2_CNTL2 0x1404 +#define INVALIDATE_ALL_L1_TLBS (1 << 0) +#define INVALIDATE_L2_CACHE (1 << 1) +#define VM_L2_CNTL3 0x1408 +#define BANK_SELECT(x) ((x) << 0) +#define CACHE_UPDATE_MODE(x) ((x) << 6) +#define VM_L2_STATUS 0x140C +#define L2_BUSY (1 << 0) + +#define WAIT_UNTIL 0x8040 + +#endif -- cgit v0.10.2 From 6fcefd56f5060ca99ab03c9f2ad1f17c3a543ca1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 8 Sep 2009 11:08:32 +1000 Subject: drm/kms: fix kms helper license + Kconfig Allow the KMS module to work properly, and also rename it to KMS_HELPER so its clearer what its for. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 8c73091..d42cf54 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -18,12 +18,13 @@ menuconfig DRM details. You should also select and configure AGP (/dev/agpgart) support. -config DRM_MODE_HELPER +config DRM_KMS_HELPER tristate depends on DRM select FB + select FRAMEBUFFER_CONSOLE if !EMBEDDED help - FB and CRTC helpers for kms drivers. + FB and CRTC helpers for KMS drivers. config DRM_TTM tristate @@ -90,11 +91,10 @@ config DRM_I830 config DRM_I915 tristate "i915 driver" depends on AGP_INTEL - select DRM_MODE_HELPER + select DRM_KMS_HELPER select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT - select FRAMEBUFFER_CONSOLE if !EMBEDDED # i915 depends on ACPI_VIDEO when ACPI is enabled # but for select to work, need to select ACPI_VIDEO's dependencies, ick select VIDEO_OUTPUT_CONTROL if ACPI diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 7e96d74..3c8827a 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -15,9 +15,9 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \ drm-$(CONFIG_COMPAT) += drm_ioc32.o -drm_helper-y := drm_fb_helper.o drm_crtc_helper.o +drm_kms_helper-y := drm_fb_helper.o drm_crtc_helper.o -obj-$(CONFIG_DRM_MODE_HELPER) += drm_helper.o +obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o obj-$(CONFIG_DRM) += drm.o obj-$(CONFIG_DRM_TTM) += ttm/ diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 41086e9..8eee4a6 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -34,6 +34,10 @@ #include "drm_fb_helper.h" #include "drm_crtc_helper.h" +MODULE_AUTHOR("David Airlie, Jesse Barnes"); +MODULE_DESCRIPTION("DRM KMS helper"); +MODULE_LICENSE("GPL and additional rights"); + static LIST_HEAD(kernel_fb_helper_list); bool drm_fb_helper_force_kernel_mode(void) diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig index fdd9c89..3cc89b2 100644 --- a/drivers/gpu/drm/radeon/Kconfig +++ b/drivers/gpu/drm/radeon/Kconfig @@ -1,7 +1,7 @@ config DRM_RADEON_KMS bool "Enable modesetting on radeon by default" depends on DRM_RADEON - select DRM_MODE_HELPER + select DRM_KMS_HELPER select DRM_TTM help Choose this option if you want kernel modesetting enabled by default, -- cgit v0.10.2 From a0cdc6495bdd0ea12390b9edaf13c8cb653df109 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 8 Sep 2009 11:09:50 +1000 Subject: drm/kms/radeon: make kms default a runtime option This makes the kms/enable disable a runtime not a build time option. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index d42cf54..e4d971c 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -56,8 +56,9 @@ config DRM_RADEON select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT - select FRAMEBUFFER_CONSOLE if !EMBEDDED select FW_LOADER + select DRM_KMS_HELPER + select DRM_TTM help Choose this option if you have an ATI Radeon graphics card. There are both PCI and AGP versions. You don't need to choose this to diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig index 3cc89b2..5982321 100644 --- a/drivers/gpu/drm/radeon/Kconfig +++ b/drivers/gpu/drm/radeon/Kconfig @@ -1,8 +1,6 @@ config DRM_RADEON_KMS bool "Enable modesetting on radeon by default" depends on DRM_RADEON - select DRM_KMS_HELPER - select DRM_TTM help Choose this option if you want kernel modesetting enabled by default, and you have a new enough userspace to support this. Running old diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 14c3fe6..09a28923 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -3,8 +3,6 @@ # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. ccflags-y := -Iinclude/drm -radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ - radeon_irq.o r300_cmdbuf.o r600_cp.o hostprogs-y := mkregtable @@ -39,7 +37,10 @@ $(obj)/r300.o: $(obj)/r300_reg_safe.h $(obj)/rs600.o: $(obj)/rs600_reg_safe.h -radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \ +radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ + radeon_irq.o r300_cmdbuf.o r600_cp.o +# add KMS driver +radeon-y += radeon_device.o radeon_kms.o \ radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \ atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \ radeon_legacy_crtc.o radeon_legacy_encoders.o radeon_connectors.o \ diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 133e975..29f040a 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -38,7 +38,6 @@ #include -#if defined(CONFIG_DRM_RADEON_KMS) /* * KMS wrapper. */ @@ -77,11 +76,9 @@ int radeon_mmap(struct file *filp, struct vm_area_struct *vma); int radeon_debugfs_init(struct drm_minor *minor); void radeon_debugfs_cleanup(struct drm_minor *minor); #endif -#endif int radeon_no_wb; -#if defined(CONFIG_DRM_RADEON_KMS) int radeon_modeset = -1; int radeon_dynclks = -1; int radeon_r4xx_atom = 0; @@ -92,12 +89,10 @@ int radeon_benchmarking = 0; int radeon_testing = 0; int radeon_connector_table = 0; int radeon_tv = 1; -#endif MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); module_param_named(no_wb, radeon_no_wb, int, 0444); -#if defined(CONFIG_DRM_RADEON_KMS) MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); module_param_named(modeset, radeon_modeset, int, 0400); @@ -127,7 +122,6 @@ module_param_named(connector_table, radeon_connector_table, int, 0444); MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); module_param_named(tv, radeon_tv, int, 0444); -#endif static int radeon_suspend(struct drm_device *dev, pm_message_t state) { @@ -219,7 +213,6 @@ static struct drm_driver driver_old = { .patchlevel = DRIVER_PATCHLEVEL, }; -#if defined(CONFIG_DRM_RADEON_KMS) static struct drm_driver kms_driver; static int __devinit @@ -313,7 +306,6 @@ static struct drm_driver kms_driver = { .minor = KMS_DRIVER_MINOR, .patchlevel = KMS_DRIVER_PATCHLEVEL, }; -#endif static struct drm_driver *driver; @@ -321,7 +313,6 @@ static int __init radeon_init(void) { driver = &driver_old; driver->num_ioctls = radeon_max_ioctl; -#if defined(CONFIG_DRM_RADEON_KMS) #ifdef CONFIG_VGA_CONSOLE if (vgacon_text_force() && radeon_modeset == -1) { DRM_INFO("VGACON disable radeon kernel modesetting.\n"); @@ -332,8 +323,13 @@ static int __init radeon_init(void) #endif /* if enabled by default */ if (radeon_modeset == -1) { - DRM_INFO("radeon default to kernel modesetting.\n"); +#ifdef CONFIG_DRM_RADEON_KMS + DRM_INFO("radeon defaulting to kernel modesetting.\n"); radeon_modeset = 1; +#else + DRM_INFO("radeon defaulting to userspace modesetting.\n"); + radeon_modeset = 0; +#endif } if (radeon_modeset == 1) { DRM_INFO("radeon kernel modesetting enabled.\n"); @@ -343,7 +339,6 @@ static int __init radeon_init(void) } /* if the vga console setting is enabled still * let modprobe override it */ -#endif return drm_init(driver); } -- cgit v0.10.2 From f641e51e7469cc3a8115a3bd70b4526d566b1c60 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 8 Sep 2009 11:17:38 +1000 Subject: drm/radeon/kms: lower debugging on dpms events. Lower the debugging on encoders when getting DPMS events. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index 5c4ede7c..8a353ea 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c @@ -136,9 +136,9 @@ void radeon_encoder_set_active_device(struct drm_encoder *encoder) if (connector->encoder == encoder) { struct radeon_connector *radeon_connector = to_radeon_connector(connector); radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; - DRM_INFO("setting active device to %08x from %08x %08x for encoder %d\n", - radeon_encoder->active_device, radeon_encoder->devices, - radeon_connector->devices, encoder->encoder_type); + DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", + radeon_encoder->active_device, radeon_encoder->devices, + radeon_connector->devices, encoder->encoder_type); } } } @@ -878,9 +878,9 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) else devices = radeon_encoder->active_device; - DRM_INFO("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", - radeon_encoder->encoder_id, mode, radeon_encoder->devices, - radeon_encoder->active_device); + DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", + radeon_encoder->encoder_id, mode, radeon_encoder->devices, + radeon_encoder->active_device); switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_TMDS1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: @@ -1276,7 +1276,6 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder) { struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); - DRM_INFO("setting active device to 0 for encoder %d\n", encoder->encoder_type); radeon_encoder->active_device = 0; } -- cgit v0.10.2 From f1938cd6e900a85de64184e46d841efc9efd3484 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 8 Sep 2009 11:32:08 +1000 Subject: drm: include seq_file.h for debugfs builds. Fixes a warning seen on powerpc. Signed-off-by: Dave Airlie diff --git a/include/drm/drm_mm.h b/include/drm/drm_mm.h index bc5a87e..62329f9 100644 --- a/include/drm/drm_mm.h +++ b/include/drm/drm_mm.h @@ -37,6 +37,9 @@ * Generic range manager structs */ #include +#ifdef CONFIG_DEBUG_FS +#include +#endif struct drm_mm_node { struct list_head fl_entry; -- cgit v0.10.2 From ec2a4c3fdc8e82fe82a25d800e85c1ea06b74372 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 4 Aug 2009 11:43:41 +1000 Subject: drm/i915: get the bridge device once. The driver gets the bridge device in a number of places, upcoming vga arb code paths need the bridge device, however they need it in under a lock, and the pci lookup can allocate memory. So clean this code up before then and get the bridge once for the driver lifetime. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 91ef4c150..9909505 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -898,6 +898,18 @@ static int i915_set_status_page(struct drm_device *dev, void *data, return 0; } +static int i915_get_bridge_dev(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); + if (!dev_priv->bridge_dev) { + DRM_ERROR("bridge device not found\n"); + return -1; + } + return 0; +} + /** * i915_probe_agp - get AGP bootup configuration * @pdev: PCI device @@ -911,20 +923,13 @@ static int i915_set_status_page(struct drm_device *dev, void *data, static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, uint32_t *preallocated_size) { - struct pci_dev *bridge_dev; + struct drm_i915_private *dev_priv = dev->dev_private; u16 tmp = 0; unsigned long overhead; unsigned long stolen; - bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); - if (!bridge_dev) { - DRM_ERROR("bridge device not found\n"); - return -1; - } - /* Get the fb aperture size and "stolen" memory amount. */ - pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp); - pci_dev_put(bridge_dev); + pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp); *aperture_size = 1024 * 1024; *preallocated_size = 1024 * 1024; @@ -1176,11 +1181,16 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) base = drm_get_resource_start(dev, mmio_bar); size = drm_get_resource_len(dev, mmio_bar); + if (i915_get_bridge_dev(dev)) { + ret = -EIO; + goto free_priv; + } + dev_priv->regs = ioremap(base, size); if (!dev_priv->regs) { DRM_ERROR("failed to map registers\n"); ret = -EIO; - goto free_priv; + goto put_bridge; } dev_priv->mm.gtt_mapping = @@ -1292,6 +1302,8 @@ out_iomapfree: io_mapping_free(dev_priv->mm.gtt_mapping); out_rmmap: iounmap(dev_priv->regs); +put_bridge: + pci_dev_put(dev_priv->bridge_dev); free_priv: kfree(dev_priv); return ret; @@ -1335,6 +1347,7 @@ int i915_driver_unload(struct drm_device *dev) i915_gem_lastclose(dev); } + pci_dev_put(dev_priv->bridge_dev); kfree(dev->dev_private); return 0; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2d5bce6..77ed060 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -155,6 +155,7 @@ typedef struct drm_i915_private { void __iomem *regs; + struct pci_dev *bridge_dev; drm_i915_ring_buffer_t ring; drm_dma_handle_t *status_page_dmah; diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index e774a4a..200e398 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -94,23 +94,15 @@ static int intel_alloc_mchbar_resource(struct drm_device *dev) { - struct pci_dev *bridge_dev; drm_i915_private_t *dev_priv = dev->dev_private; int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; u32 temp_lo, temp_hi = 0; u64 mchbar_addr; int ret = 0; - bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); - if (!bridge_dev) { - DRM_DEBUG("no bridge dev?!\n"); - ret = -ENODEV; - goto out; - } - if (IS_I965G(dev)) - pci_read_config_dword(bridge_dev, reg + 4, &temp_hi); - pci_read_config_dword(bridge_dev, reg, &temp_lo); + pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); + pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); mchbar_addr = ((u64)temp_hi << 32) | temp_lo; /* If ACPI doesn't have it, assume we need to allocate it ourselves */ @@ -118,30 +110,28 @@ intel_alloc_mchbar_resource(struct drm_device *dev) if (mchbar_addr && pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { ret = 0; - goto out_put; + goto out; } #endif /* Get some space for it */ - ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res, + ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res, MCHBAR_SIZE, MCHBAR_SIZE, PCIBIOS_MIN_MEM, 0, pcibios_align_resource, - bridge_dev); + dev_priv->bridge_dev); if (ret) { DRM_DEBUG("failed bus alloc: %d\n", ret); dev_priv->mch_res.start = 0; - goto out_put; + goto out; } if (IS_I965G(dev)) - pci_write_config_dword(bridge_dev, reg + 4, + pci_write_config_dword(dev_priv->bridge_dev, reg + 4, upper_32_bits(dev_priv->mch_res.start)); - pci_write_config_dword(bridge_dev, reg, + pci_write_config_dword(dev_priv->bridge_dev, reg, lower_32_bits(dev_priv->mch_res.start)); -out_put: - pci_dev_put(bridge_dev); out: return ret; } @@ -150,44 +140,36 @@ out: static bool intel_setup_mchbar(struct drm_device *dev) { - struct pci_dev *bridge_dev; + drm_i915_private_t *dev_priv = dev->dev_private; int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; u32 temp; bool need_disable = false, enabled; - bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); - if (!bridge_dev) { - DRM_DEBUG("no bridge dev?!\n"); - goto out; - } - if (IS_I915G(dev) || IS_I915GM(dev)) { - pci_read_config_dword(bridge_dev, DEVEN_REG, &temp); + pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); enabled = !!(temp & DEVEN_MCHBAR_EN); } else { - pci_read_config_dword(bridge_dev, mchbar_reg, &temp); + pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); enabled = temp & 1; } /* If it's already enabled, don't have to do anything */ if (enabled) - goto out_put; + goto out; if (intel_alloc_mchbar_resource(dev)) - goto out_put; + goto out; need_disable = true; /* Space is allocated or reserved, so enable it. */ if (IS_I915G(dev) || IS_I915GM(dev)) { - pci_write_config_dword(bridge_dev, DEVEN_REG, + pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp | DEVEN_MCHBAR_EN); } else { - pci_read_config_dword(bridge_dev, mchbar_reg, &temp); - pci_write_config_dword(bridge_dev, mchbar_reg, temp | 1); + pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); + pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); } -out_put: - pci_dev_put(bridge_dev); out: return need_disable; } @@ -196,25 +178,18 @@ static void intel_teardown_mchbar(struct drm_device *dev, bool disable) { drm_i915_private_t *dev_priv = dev->dev_private; - struct pci_dev *bridge_dev; int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; u32 temp; - bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); - if (!bridge_dev) { - DRM_DEBUG("no bridge dev?!\n"); - return; - } - if (disable) { if (IS_I915G(dev) || IS_I915GM(dev)) { - pci_read_config_dword(bridge_dev, DEVEN_REG, &temp); + pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); temp &= ~DEVEN_MCHBAR_EN; - pci_write_config_dword(bridge_dev, DEVEN_REG, temp); + pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); } else { - pci_read_config_dword(bridge_dev, mchbar_reg, &temp); + pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); temp &= ~1; - pci_write_config_dword(bridge_dev, mchbar_reg, temp); + pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); } } -- cgit v0.10.2 From 1ecff1eb0b83efa85be5b54c958e831e37f993f3 Mon Sep 17 00:00:00 2001 From: Adam Jackson Date: Tue, 8 Sep 2009 11:48:40 +1000 Subject: drm: shut the EDID warnings up. These really aren't all that useful. taken from Fedora kernel. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index e2d5f51..90d76ba 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1011,7 +1011,6 @@ int drm_do_probe_ddc_edid(struct i2c_adapter *adapter, if (i2c_transfer(adapter, msgs, 2) == 2) return 0; - dev_info(&adapter->dev, "unable to read EDID block.\n"); return -1; } EXPORT_SYMBOL(drm_do_probe_ddc_edid); @@ -1024,8 +1023,6 @@ static int drm_ddc_read_edid(struct drm_connector *connector, ret = drm_do_probe_ddc_edid(adapter, buf, len); if (ret != 0) { - dev_info(&connector->dev->pdev->dev, "%s: no EDID data\n", - drm_get_connector_name(connector)); goto end; } if (!edid_is_valid((struct edid *)buf)) { -- cgit v0.10.2 From 620f37811dcc9e0f97ee79fbf8908fcc097deaee Mon Sep 17 00:00:00 2001 From: Adam Jackson Date: Tue, 8 Sep 2009 11:51:46 +1000 Subject: drm: prune modes when output is disconnected. When an output was disconnected, its mode list would remain. If you later plugged into a sink with no EDID (projector, etc), you'd inherit the mode list from the old sink, which is not what you want. taken from Fedora kernel Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index c9a50c7..ff447f1 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -95,8 +95,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, if (connector->status == connector_status_disconnected) { DRM_DEBUG_KMS("%s is disconnected\n", drm_get_connector_name(connector)); - /* TODO set EDID to NULL */ - return 0; + goto prune; } count = (*connector_funcs->get_modes)(connector); @@ -124,6 +123,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, mode); } +prune: drm_mode_prune_invalid(dev, &connector->modes, true); if (list_empty(&connector->modes)) -- cgit v0.10.2 From c746e205f2fb6f74b4a622382607f065eca5eb49 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 8 Sep 2009 14:38:45 +1000 Subject: drm/radeon/kms: don't allow ERESTART to hit userspace. the pre-r600 fence code returns ebusy if we get hit by a signal so we should continue to do that. Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c index 506dd4d..01a8963 100644 --- a/drivers/gpu/drm/radeon/radeon_fence.c +++ b/drivers/gpu/drm/radeon/radeon_fence.c @@ -199,7 +199,7 @@ int r600_fence_wait(struct radeon_fence *fence, bool intr, bool lazy) schedule_timeout(1); if (intr && signal_pending(current)) { - ret = -ERESTART; + ret = -ERESTARTSYS; break; } } @@ -225,8 +225,12 @@ int radeon_fence_wait(struct radeon_fence *fence, bool intr) return 0; } - if (rdev->family >= CHIP_R600) - return r600_fence_wait(fence, intr, 0); + if (rdev->family >= CHIP_R600) { + r = r600_fence_wait(fence, intr, 0); + if (r == -ERESTARTSYS) + return -EBUSY; + return r; + } retry: cur_jiffies = jiffies; -- cgit v0.10.2 From 60d15f551abdbc5fef70d85f55aac1e85950bf59 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 8 Sep 2009 14:22:45 -0400 Subject: drm/radeon/kms: re-apply 2007d633d639c896396e4c4b53b38068f3831307 Got accidently reverted by c93bb85b5cba3e3a06f2cad8e9bc5c23d3d10aac Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index 8a353ea..9ad2035 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c @@ -1400,8 +1400,14 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); - radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); + if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + radeon_encoder->rmx_type = RMX_FULL; + drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); + radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); + } else { + drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); + radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); + } drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); break; } -- cgit v0.10.2 From cecc6b63a5de547a345c491bb4c18c01a15984a4 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 8 Sep 2009 14:45:05 -0400 Subject: drm/radeon/r600: use fence->timeout directly Fixes fence timeouts on r6xx/r7xx. Noticed by taiu on IRC. Signed-off-by: Alex Deucher diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c index 01a8963..3beb26d 100644 --- a/drivers/gpu/drm/radeon/radeon_fence.c +++ b/drivers/gpu/drm/radeon/radeon_fence.c @@ -171,17 +171,8 @@ bool radeon_fence_signaled(struct radeon_fence *fence) int r600_fence_wait(struct radeon_fence *fence, bool intr, bool lazy) { struct radeon_device *rdev; - unsigned long cur_jiffies; - unsigned long timeout; int ret = 0; - cur_jiffies = jiffies; - timeout = HZ / 100; - - if (time_after(fence->timeout, cur_jiffies)) { - timeout = fence->timeout - cur_jiffies; - } - rdev = fence->rdev; __set_current_state(intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); @@ -190,7 +181,7 @@ int r600_fence_wait(struct radeon_fence *fence, bool intr, bool lazy) if (radeon_fence_signaled(fence)) break; - if (time_after_eq(jiffies, timeout)) { + if (time_after_eq(jiffies, fence->timeout)) { ret = -EBUSY; break; } -- cgit v0.10.2 From 1f27adc2f050836c12deb4d99afe507636537a0b Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:29:02 -0700 Subject: ioat: move definitions to dma.h Some of these defines may be useful outside of dma.c and the header is private so there are no namespace pollution concerns. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 648797e..16c0807 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -38,28 +38,14 @@ #include "registers.h" #include "hw.h" -#define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common) -#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) -#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) -#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx) - -#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) static int ioat_pending_level = 4; module_param(ioat_pending_level, int, 0644); MODULE_PARM_DESC(ioat_pending_level, "high-water mark for pushing ioat descriptors (default: 4)"); -#define RESET_DELAY msecs_to_jiffies(100) -#define WATCHDOG_DELAY round_jiffies(msecs_to_jiffies(2000)) static void ioat_dma_chan_reset_part2(struct work_struct *work); static void ioat_dma_chan_watchdog(struct work_struct *work); -/* - * workaround for IOAT ver.3.0 null descriptor issue - * (channel returns error when size is 0) - */ -#define NULL_DESC_BUFFER_SIZE 1 - /* internal functions */ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan); static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan); diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index e80e787..ccb400f 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -43,6 +43,22 @@ enum ioat_interrupt { #define IOAT_DMA_DCA_ANY_CPU ~0 #define IOAT_WATCHDOG_PERIOD (2 * HZ) +#define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common) +#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) +#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) +#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx) + +#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) + +#define RESET_DELAY msecs_to_jiffies(100) +#define WATCHDOG_DELAY round_jiffies(msecs_to_jiffies(2000)) + +/* + * workaround for IOAT ver.3.0 null descriptor issue + * (channel returns error when size is 0) + */ +#define NULL_DESC_BUFFER_SIZE 1 + /** * struct ioatdma_device - internal representation of a IOAT device -- cgit v0.10.2 From e6c0b69a43150c1a37cf342ce5faedf12583bf79 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:29:44 -0700 Subject: ioat: convert ioat_probe to pcim/devm The driver currently duplicates much of what these routines offer, so just use the common code. For example ->irq_mode tracks what interrupt mode was initialized, which duplicates the ->msix_enabled and ->msi_enabled handling in pcim_release. This also adds a check to the return value of dma_async_device_register, which can fail. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 16c0807..65f8b74 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -121,6 +121,7 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device) u32 xfercap; int i; struct ioat_dma_chan *ioat_chan; + struct device *dev = &device->pdev->dev; /* * IOAT ver.3 workarounds @@ -164,7 +165,7 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device) } #endif for (i = 0; i < device->common.chancnt; i++) { - ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL); + ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL); if (!ioat_chan) { device->common.chancnt = i; break; @@ -1450,7 +1451,11 @@ MODULE_PARM_DESC(ioat_interrupt_style, static int ioat_dma_setup_interrupts(struct ioatdma_device *device) { struct ioat_dma_chan *ioat_chan; - int err, i, j, msixcnt; + struct pci_dev *pdev = device->pdev; + struct device *dev = &pdev->dev; + struct msix_entry *msix; + int i, j, msixcnt; + int err = -EINVAL; u8 intrctrl = 0; if (!strcmp(ioat_interrupt_style, "msix")) @@ -1461,8 +1466,7 @@ static int ioat_dma_setup_interrupts(struct ioatdma_device *device) goto msi; if (!strcmp(ioat_interrupt_style, "intx")) goto intx; - dev_err(&device->pdev->dev, "invalid ioat_interrupt_style %s\n", - ioat_interrupt_style); + dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); goto err_no_irq; msix: @@ -1471,55 +1475,55 @@ msix: for (i = 0; i < msixcnt; i++) device->msix_entries[i].entry = i; - err = pci_enable_msix(device->pdev, device->msix_entries, msixcnt); + err = pci_enable_msix(pdev, device->msix_entries, msixcnt); if (err < 0) goto msi; if (err > 0) goto msix_single_vector; for (i = 0; i < msixcnt; i++) { + msix = &device->msix_entries[i]; ioat_chan = ioat_lookup_chan_by_index(device, i); - err = request_irq(device->msix_entries[i].vector, - ioat_dma_do_interrupt_msix, - 0, "ioat-msix", ioat_chan); + err = devm_request_irq(dev, msix->vector, + ioat_dma_do_interrupt_msix, 0, + "ioat-msix", ioat_chan); if (err) { for (j = 0; j < i; j++) { + msix = &device->msix_entries[j]; ioat_chan = ioat_lookup_chan_by_index(device, j); - free_irq(device->msix_entries[j].vector, - ioat_chan); + devm_free_irq(dev, msix->vector, ioat_chan); } goto msix_single_vector; } } intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; - device->irq_mode = msix_multi_vector; goto done; msix_single_vector: - device->msix_entries[0].entry = 0; - err = pci_enable_msix(device->pdev, device->msix_entries, 1); + msix = &device->msix_entries[0]; + msix->entry = 0; + err = pci_enable_msix(pdev, device->msix_entries, 1); if (err) goto msi; - err = request_irq(device->msix_entries[0].vector, ioat_dma_do_interrupt, - 0, "ioat-msix", device); + err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0, + "ioat-msix", device); if (err) { - pci_disable_msix(device->pdev); + pci_disable_msix(pdev); goto msi; } - device->irq_mode = msix_single_vector; goto done; msi: - err = pci_enable_msi(device->pdev); + err = pci_enable_msi(pdev); if (err) goto intx; - err = request_irq(device->pdev->irq, ioat_dma_do_interrupt, - 0, "ioat-msi", device); + err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, + "ioat-msi", device); if (err) { - pci_disable_msi(device->pdev); + pci_disable_msi(pdev); goto intx; } /* @@ -1527,21 +1531,17 @@ msi: */ if (device->version == IOAT_VER_1_2) { u32 dmactrl; - pci_read_config_dword(device->pdev, - IOAT_PCI_DMACTRL_OFFSET, &dmactrl); + pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl); dmactrl |= IOAT_PCI_DMACTRL_MSI_EN; - pci_write_config_dword(device->pdev, - IOAT_PCI_DMACTRL_OFFSET, dmactrl); + pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl); } - device->irq_mode = msi; goto done; intx: - err = request_irq(device->pdev->irq, ioat_dma_do_interrupt, - IRQF_SHARED, "ioat-intx", device); + err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, + IRQF_SHARED, "ioat-intx", device); if (err) goto err_no_irq; - device->irq_mode = intx; done: intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; @@ -1551,60 +1551,26 @@ done: err_no_irq: /* Disable all interrupt generation */ writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); - dev_err(&device->pdev->dev, "no usable interrupts\n"); - device->irq_mode = none; - return -1; + dev_err(dev, "no usable interrupts\n"); + return err; } -/** - * ioat_dma_remove_interrupts - remove whatever interrupts were set - * @device: ioat device - */ -static void ioat_dma_remove_interrupts(struct ioatdma_device *device) +static void ioat_disable_interrupts(struct ioatdma_device *device) { - struct ioat_dma_chan *ioat_chan; - int i; - /* Disable all interrupt generation */ writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); - - switch (device->irq_mode) { - case msix_multi_vector: - for (i = 0; i < device->common.chancnt; i++) { - ioat_chan = ioat_lookup_chan_by_index(device, i); - free_irq(device->msix_entries[i].vector, ioat_chan); - } - pci_disable_msix(device->pdev); - break; - case msix_single_vector: - free_irq(device->msix_entries[0].vector, device); - pci_disable_msix(device->pdev); - break; - case msi: - free_irq(device->pdev->irq, device); - pci_disable_msi(device->pdev); - break; - case intx: - free_irq(device->pdev->irq, device); - break; - case none: - dev_warn(&device->pdev->dev, - "call to %s without interrupts setup\n", __func__); - } - device->irq_mode = none; } struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, void __iomem *iobase) { int err; + struct device *dev = &pdev->dev; struct ioatdma_device *device; - device = kzalloc(sizeof(*device), GFP_KERNEL); - if (!device) { + device = devm_kzalloc(dev, sizeof(*device), GFP_KERNEL); + if (!device) err = -ENOMEM; - goto err_kzalloc; - } device->pdev = pdev; device->reg_base = iobase; device->version = readb(device->reg_base + IOAT_VER_OFFSET); @@ -1651,14 +1617,12 @@ struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, break; } - dev_err(&device->pdev->dev, - "Intel(R) I/OAT DMA Engine found," + dev_err(dev, "Intel(R) I/OAT DMA Engine found," " %d channels, device version 0x%02x, driver version %s\n", device->common.chancnt, device->version, IOAT_DMA_VERSION); if (!device->common.chancnt) { - dev_err(&device->pdev->dev, - "Intel(R) I/OAT DMA Engine problem found: " + dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: " "zero channels detected\n"); goto err_setup_interrupts; } @@ -1671,9 +1635,11 @@ struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, if (err) goto err_self_test; - ioat_set_tcp_copy_break(device); + err = dma_async_device_register(&device->common); + if (err) + goto err_self_test; - dma_async_device_register(&device->common); + ioat_set_tcp_copy_break(device); if (device->version != IOAT_VER_3_0) { INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog); @@ -1684,16 +1650,12 @@ struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, return device; err_self_test: - ioat_dma_remove_interrupts(device); + ioat_disable_interrupts(device); err_setup_interrupts: pci_pool_destroy(device->completion_pool); err_completion_pool: pci_pool_destroy(device->dma_pool); err_dma_pool: - kfree(device); -err_kzalloc: - dev_err(&pdev->dev, - "Intel(R) I/OAT DMA Engine initialization failed\n"); return NULL; } @@ -1705,23 +1667,17 @@ void ioat_dma_remove(struct ioatdma_device *device) if (device->version != IOAT_VER_3_0) cancel_delayed_work(&device->work); - ioat_dma_remove_interrupts(device); + ioat_disable_interrupts(device); dma_async_device_unregister(&device->common); pci_pool_destroy(device->dma_pool); pci_pool_destroy(device->completion_pool); - iounmap(device->reg_base); - pci_release_regions(device->pdev); - pci_disable_device(device->pdev); - list_for_each_entry_safe(chan, _chan, &device->common.channels, device_node) { ioat_chan = to_ioat_chan(chan); list_del(&chan->device_node); - kfree(ioat_chan); } - kfree(device); } diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index ccb400f..5e8d7cf 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -31,14 +31,6 @@ #define IOAT_DMA_VERSION "3.64" -enum ioat_interrupt { - none = 0, - msix_multi_vector = 1, - msix_single_vector = 2, - msi = 3, - intx = 4, -}; - #define IOAT_LOW_COMPLETION_MASK 0xffffffc0 #define IOAT_DMA_DCA_ANY_CPU ~0 #define IOAT_WATCHDOG_PERIOD (2 * HZ) @@ -59,7 +51,6 @@ enum ioat_interrupt { */ #define NULL_DESC_BUFFER_SIZE 1 - /** * struct ioatdma_device - internal representation of a IOAT device * @pdev: PCI-Express device @@ -67,7 +58,6 @@ enum ioat_interrupt { * @dma_pool: for allocating DMA descriptors * @common: embedded struct dma_device * @version: version of ioatdma device - * @irq_mode: which style irq to use * @msix_entries: irq handlers * @idx: per channel data */ @@ -79,7 +69,6 @@ struct ioatdma_device { struct pci_pool *completion_pool; struct dma_device common; u8 version; - enum ioat_interrupt irq_mode; struct delayed_work work; struct msix_entry msix_entries[4]; struct ioat_dma_chan *idx[4]; diff --git a/drivers/dma/ioat/hw.h b/drivers/dma/ioat/hw.h index afa57ee..1438fa5 100644 --- a/drivers/dma/ioat/hw.h +++ b/drivers/dma/ioat/hw.h @@ -23,6 +23,7 @@ /* PCI Configuration Space Values */ #define IOAT_PCI_VID 0x8086 +#define IOAT_MMIO_BAR 0 /* CB device ID's */ #define IOAT_PCI_DID_5000 0x1A38 diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c index d7948bf..982e38f 100644 --- a/drivers/dma/ioat/pci.c +++ b/drivers/dma/ioat/pci.c @@ -62,7 +62,6 @@ static struct pci_device_id ioat_pci_tbl[] = { struct ioat_device { struct pci_dev *pdev; - void __iomem *iobase; struct ioatdma_device *dma; struct dca_provider *dca; }; @@ -75,8 +74,10 @@ static int ioat_dca_enabled = 1; module_param(ioat_dca_enabled, int, 0644); MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); +#define DRV_NAME "ioatdma" + static struct pci_driver ioat_pci_driver = { - .name = "ioatdma", + .name = DRV_NAME, .id_table = ioat_pci_tbl, .probe = ioat_probe, .remove = __devexit_p(ioat_remove), @@ -85,47 +86,42 @@ static struct pci_driver ioat_pci_driver = { static int __devinit ioat_probe(struct pci_dev *pdev, const struct pci_device_id *id) { + void __iomem * const *iomap; void __iomem *iobase; + struct device *dev = &pdev->dev; struct ioat_device *device; - unsigned long mmio_start, mmio_len; int err; - err = pci_enable_device(pdev); + err = pcim_enable_device(pdev); if (err) - goto err_enable_device; + return err; - err = pci_request_regions(pdev, ioat_pci_driver.name); + err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME); if (err) - goto err_request_regions; + return err; + iomap = pcim_iomap_table(pdev); + if (!iomap) + return -ENOMEM; err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); if (err) err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); if (err) - goto err_set_dma_mask; + return err; err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); if (err) err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); if (err) - goto err_set_dma_mask; - - mmio_start = pci_resource_start(pdev, 0); - mmio_len = pci_resource_len(pdev, 0); - iobase = ioremap(mmio_start, mmio_len); - if (!iobase) { - err = -ENOMEM; - goto err_ioremap; - } + return err; + + device = devm_kzalloc(dev, sizeof(*device), GFP_KERNEL); + if (!device) + return -ENOMEM; - device = kzalloc(sizeof(*device), GFP_KERNEL); - if (!device) { - err = -ENOMEM; - goto err_kzalloc; - } device->pdev = pdev; pci_set_drvdata(pdev, device); - device->iobase = iobase; + iobase = iomap[IOAT_MMIO_BAR]; pci_set_master(pdev); @@ -146,28 +142,15 @@ static int __devinit ioat_probe(struct pci_dev *pdev, device->dca = ioat3_dca_init(pdev, iobase); break; default: - err = -ENODEV; - break; + return -ENODEV; } - if (!device->dma) - err = -ENODEV; - if (err) - goto err_version; + if (!device->dma) { + dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n"); + return -ENODEV; + } return 0; - -err_version: - kfree(device); -err_kzalloc: - iounmap(iobase); -err_ioremap: -err_set_dma_mask: - pci_release_regions(pdev); - pci_disable_device(pdev); -err_request_regions: -err_enable_device: - return err; } static void __devexit ioat_remove(struct pci_dev *pdev) @@ -185,8 +168,6 @@ static void __devexit ioat_remove(struct pci_dev *pdev) ioat_dma_remove(device->dma); device->dma = NULL; } - - kfree(device); } static int __init ioat_init_module(void) -- cgit v0.10.2 From bc3c70258526a635325f1f15138a96297879bc1a Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 28 Jul 2009 14:33:42 -0700 Subject: ioat: cleanup some long deref chains and 80 column collisions * reduce device->common. to dma-> in ioat_dma_{probe,remove,selftest} * ioat_lookup_chan_by_index to ioat_chan_by_index * multi-line function definitions * ioat_desc_sw.async_tx to ioat_desc_sw.txd * desc->txd. to tx-> in cleanup routine Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 65f8b74..462dae6 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -55,9 +55,8 @@ ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan); static struct ioat_desc_sw * ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan); -static inline struct ioat_dma_chan *ioat_lookup_chan_by_index( - struct ioatdma_device *device, - int index) +static inline struct ioat_dma_chan * +ioat_chan_by_index(struct ioatdma_device *device, int index) { return device->idx[index]; } @@ -87,7 +86,7 @@ static irqreturn_t ioat_dma_do_interrupt(int irq, void *data) attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); for_each_bit(bit, &attnstatus, BITS_PER_LONG) { - ioat_chan = ioat_lookup_chan_by_index(instance, bit); + ioat_chan = ioat_chan_by_index(instance, bit); tasklet_schedule(&ioat_chan->cleanup_task); } @@ -205,8 +204,8 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device) * descriptors to hw * @chan: DMA channel handle */ -static inline void __ioat1_dma_memcpy_issue_pending( - struct ioat_dma_chan *ioat_chan) +static inline void +__ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat_chan) { ioat_chan->pending = 0; writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET); @@ -223,8 +222,8 @@ static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan) } } -static inline void __ioat2_dma_memcpy_issue_pending( - struct ioat_dma_chan *ioat_chan) +static inline void +__ioat2_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat_chan) { ioat_chan->pending = 0; writew(ioat_chan->dmacount, @@ -279,18 +278,18 @@ static void ioat_dma_chan_reset_part2(struct work_struct *work) desc = to_ioat_desc(ioat_chan->used_desc.prev); switch (ioat_chan->device->version) { case IOAT_VER_1_2: - writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF, + writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->async_tx.phys) >> 32, + writel(((u64) desc->txd.phys) >> 32, ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); writeb(IOAT_CHANCMD_START, ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); break; case IOAT_VER_2_0: - writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF, + writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->async_tx.phys) >> 32, + writel(((u64) desc->txd.phys) >> 32, ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); /* tell the engine to go with what's left to be done */ @@ -299,7 +298,7 @@ static void ioat_dma_chan_reset_part2(struct work_struct *work) break; } - dev_err(&ioat_chan->device->pdev->dev, + dev_err(to_dev(ioat_chan), "chan%d reset - %d descs waiting, %d total desc\n", chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); @@ -322,7 +321,7 @@ static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan) chansts = (ioat_chan->completion_virt->low & IOAT_CHANSTS_DMA_TRANSFER_STATUS); if (chanerr) { - dev_err(&ioat_chan->device->pdev->dev, + dev_err(to_dev(ioat_chan), "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", chan_num(ioat_chan), chansts, chanerr); writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); @@ -367,7 +366,7 @@ static void ioat_dma_chan_watchdog(struct work_struct *work) unsigned long compl_desc_addr_hw; for (i = 0; i < device->common.chancnt; i++) { - ioat_chan = ioat_lookup_chan_by_index(device, i); + ioat_chan = ioat_chan_by_index(device, i); if (ioat_chan->device->version == IOAT_VER_1_2 /* have we started processing anything yet */ @@ -475,7 +474,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) len = first->len; src = first->src; dst = first->dst; - orig_flags = first->async_tx.flags; + orig_flags = first->txd.flags; new = first; spin_lock_bh(&ioat_chan->desc_lock); @@ -484,7 +483,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) do { copy = min_t(size_t, len, ioat_chan->xfercap); - async_tx_ack(&new->async_tx); + async_tx_ack(&new->txd); hw = new->hw; hw->size = copy; @@ -495,7 +494,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) /* chain together the physical address list for the HW */ wmb(); - prev->hw->next = (u64) new->async_tx.phys; + prev->hw->next = (u64) new->txd.phys; len -= copy; dst += copy; @@ -507,27 +506,26 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) } while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan))); if (!new) { - dev_err(&ioat_chan->device->pdev->dev, - "tx submit failed\n"); + dev_err(to_dev(ioat_chan), "tx submit failed\n"); spin_unlock_bh(&ioat_chan->desc_lock); return -ENOMEM; } hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS; - if (first->async_tx.callback) { + if (first->txd.callback) { hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN; if (first != new) { /* move callback into to last desc */ - new->async_tx.callback = first->async_tx.callback; - new->async_tx.callback_param - = first->async_tx.callback_param; - first->async_tx.callback = NULL; - first->async_tx.callback_param = NULL; + new->txd.callback = first->txd.callback; + new->txd.callback_param + = first->txd.callback_param; + first->txd.callback = NULL; + first->txd.callback_param = NULL; } } new->tx_cnt = desc_count; - new->async_tx.flags = orig_flags; /* client is in control of this ack */ + new->txd.flags = orig_flags; /* client is in control of this ack */ /* store the original values for use in later cleanup */ if (new != first) { @@ -541,11 +539,11 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) cookie++; if (cookie < 0) cookie = 1; - ioat_chan->common.cookie = new->async_tx.cookie = cookie; + ioat_chan->common.cookie = new->txd.cookie = cookie; /* write address into NextDescriptor field of last desc in chain */ to_ioat_desc(ioat_chan->used_desc.prev)->hw->next = - first->async_tx.phys; + first->txd.phys; list_splice_tail(&new_chain, &ioat_chan->used_desc); ioat_chan->dmacount += desc_count; @@ -574,7 +572,7 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) len = first->len; src = first->src; dst = first->dst; - orig_flags = first->async_tx.flags; + orig_flags = first->txd.flags; new = first; /* @@ -584,7 +582,7 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) do { copy = min_t(size_t, len, ioat_chan->xfercap); - async_tx_ack(&new->async_tx); + async_tx_ack(&new->txd); hw = new->hw; hw->size = copy; @@ -599,27 +597,26 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) } while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan))); if (!new) { - dev_err(&ioat_chan->device->pdev->dev, - "tx submit failed\n"); + dev_err(to_dev(ioat_chan), "tx submit failed\n"); spin_unlock_bh(&ioat_chan->desc_lock); return -ENOMEM; } hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS; - if (first->async_tx.callback) { + if (first->txd.callback) { hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN; if (first != new) { /* move callback into to last desc */ - new->async_tx.callback = first->async_tx.callback; - new->async_tx.callback_param - = first->async_tx.callback_param; - first->async_tx.callback = NULL; - first->async_tx.callback_param = NULL; + new->txd.callback = first->txd.callback; + new->txd.callback_param + = first->txd.callback_param; + first->txd.callback = NULL; + first->txd.callback_param = NULL; } } new->tx_cnt = desc_count; - new->async_tx.flags = orig_flags; /* client is in control of this ack */ + new->txd.flags = orig_flags; /* client is in control of this ack */ /* store the original values for use in later cleanup */ if (new != first) { @@ -633,7 +630,7 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) cookie++; if (cookie < 0) cookie = 1; - ioat_chan->common.cookie = new->async_tx.cookie = cookie; + ioat_chan->common.cookie = new->txd.cookie = cookie; ioat_chan->dmacount += desc_count; ioat_chan->pending += desc_count; @@ -649,9 +646,8 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) * @ioat_chan: the channel supplying the memory pool for the descriptors * @flags: allocation flags */ -static struct ioat_desc_sw *ioat_dma_alloc_descriptor( - struct ioat_dma_chan *ioat_chan, - gfp_t flags) +static struct ioat_desc_sw * +ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat_chan, gfp_t flags) { struct ioat_dma_descriptor *desc; struct ioat_desc_sw *desc_sw; @@ -670,19 +666,19 @@ static struct ioat_desc_sw *ioat_dma_alloc_descriptor( } memset(desc, 0, sizeof(*desc)); - dma_async_tx_descriptor_init(&desc_sw->async_tx, &ioat_chan->common); + dma_async_tx_descriptor_init(&desc_sw->txd, &ioat_chan->common); switch (ioat_chan->device->version) { case IOAT_VER_1_2: - desc_sw->async_tx.tx_submit = ioat1_tx_submit; + desc_sw->txd.tx_submit = ioat1_tx_submit; break; case IOAT_VER_2_0: case IOAT_VER_3_0: - desc_sw->async_tx.tx_submit = ioat2_tx_submit; + desc_sw->txd.tx_submit = ioat2_tx_submit; break; } desc_sw->hw = desc; - desc_sw->async_tx.phys = phys; + desc_sw->txd.phys = phys; return desc_sw; } @@ -712,9 +708,9 @@ static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan) /* circle link the hw descriptors */ desc = to_ioat_desc(ioat_chan->free_desc.next); - desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys; + desc->hw->next = to_ioat_desc(desc->node.next)->txd.phys; list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) { - desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys; + desc->hw->next = to_ioat_desc(desc->node.next)->txd.phys; } } @@ -743,8 +739,7 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan) chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); if (chanerr) { - dev_err(&ioat_chan->device->pdev->dev, - "CHANERR = %x, clearing\n", chanerr); + dev_err(to_dev(ioat_chan), "CHANERR = %x, clearing\n", chanerr); writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); } @@ -752,7 +747,7 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan) for (i = 0; i < ioat_initial_desc_count; i++) { desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL); if (!desc) { - dev_err(&ioat_chan->device->pdev->dev, + dev_err(to_dev(ioat_chan), "Only %d initial descriptors\n", i); break; } @@ -819,14 +814,14 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan) in_use_descs++; list_del(&desc->node); pci_pool_free(ioatdma_device->dma_pool, desc->hw, - desc->async_tx.phys); + desc->txd.phys); kfree(desc); } list_for_each_entry_safe(desc, _desc, &ioat_chan->free_desc, node) { list_del(&desc->node); pci_pool_free(ioatdma_device->dma_pool, desc->hw, - desc->async_tx.phys); + desc->txd.phys); kfree(desc); } break; @@ -836,12 +831,12 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan) ioat_chan->free_desc.next, node) { list_del(&desc->node); pci_pool_free(ioatdma_device->dma_pool, desc->hw, - desc->async_tx.phys); + desc->txd.phys); kfree(desc); } desc = to_ioat_desc(ioat_chan->free_desc.next); pci_pool_free(ioatdma_device->dma_pool, desc->hw, - desc->async_tx.phys); + desc->txd.phys); kfree(desc); INIT_LIST_HEAD(&ioat_chan->free_desc); INIT_LIST_HEAD(&ioat_chan->used_desc); @@ -855,8 +850,7 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan) /* one is ok since we left it on there on purpose */ if (in_use_descs > 1) - dev_err(&ioat_chan->device->pdev->dev, - "Freeing %d in use descriptors!\n", + dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n", in_use_descs - 1); ioat_chan->last_completion = ioat_chan->completion_addr = 0; @@ -889,8 +883,7 @@ ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) /* try to get another desc */ new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC); if (!new) { - dev_err(&ioat_chan->device->pdev->dev, - "alloc failed\n"); + dev_err(to_dev(ioat_chan), "alloc failed\n"); return NULL; } } @@ -936,16 +929,15 @@ ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) for (i = 16; i; i--) { desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC); if (!desc) { - dev_err(&ioat_chan->device->pdev->dev, - "alloc failed\n"); + dev_err(to_dev(ioat_chan), "alloc failed\n"); break; } list_add_tail(&desc->node, ioat_chan->used_desc.next); desc->hw->next - = to_ioat_desc(desc->node.next)->async_tx.phys; + = to_ioat_desc(desc->node.next)->txd.phys; to_ioat_desc(desc->node.prev)->hw->next - = desc->async_tx.phys; + = desc->txd.phys; ioat_chan->desccount++; } @@ -962,8 +954,8 @@ ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) return new; } -static struct ioat_desc_sw *ioat_dma_get_next_descriptor( - struct ioat_dma_chan *ioat_chan) +static struct ioat_desc_sw * +ioat_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) { if (!ioat_chan) return NULL; @@ -978,12 +970,9 @@ static struct ioat_desc_sw *ioat_dma_get_next_descriptor( return NULL; } -static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy( - struct dma_chan *chan, - dma_addr_t dma_dest, - dma_addr_t dma_src, - size_t len, - unsigned long flags) +static struct dma_async_tx_descriptor * +ioat1_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, + dma_addr_t dma_src, size_t len, unsigned long flags) { struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); struct ioat_desc_sw *new; @@ -996,22 +985,19 @@ static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy( new->len = len; new->dst = dma_dest; new->src = dma_src; - new->async_tx.flags = flags; - return &new->async_tx; + new->txd.flags = flags; + return &new->txd; } else { - dev_err(&ioat_chan->device->pdev->dev, + dev_err(to_dev(ioat_chan), "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n", chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); return NULL; } } -static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy( - struct dma_chan *chan, - dma_addr_t dma_dest, - dma_addr_t dma_src, - size_t len, - unsigned long flags) +static struct dma_async_tx_descriptor * +ioat2_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, + dma_addr_t dma_src, size_t len, unsigned long flags) { struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); struct ioat_desc_sw *new; @@ -1028,11 +1014,11 @@ static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy( new->len = len; new->dst = dma_dest; new->src = dma_src; - new->async_tx.flags = flags; - return &new->async_tx; + new->txd.flags = flags; + return &new->txd; } else { spin_unlock_bh(&ioat_chan->desc_lock); - dev_err(&ioat_chan->device->pdev->dev, + dev_err(to_dev(ioat_chan), "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n", chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); return NULL; @@ -1050,8 +1036,8 @@ static void ioat_dma_cleanup_tasklet(unsigned long data) static void ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc) { - if (!(desc->async_tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { - if (desc->async_tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) + if (!(desc->txd.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { + if (desc->txd.flags & DMA_COMPL_DEST_UNMAP_SINGLE) pci_unmap_single(ioat_chan->device->pdev, pci_unmap_addr(desc, dst), pci_unmap_len(desc, len), @@ -1063,8 +1049,8 @@ ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc) PCI_DMA_FROMDEVICE); } - if (!(desc->async_tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { - if (desc->async_tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) + if (!(desc->txd.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { + if (desc->txd.flags & DMA_COMPL_SRC_UNMAP_SINGLE) pci_unmap_single(ioat_chan->device->pdev, pci_unmap_addr(desc, src), pci_unmap_len(desc, len), @@ -1088,6 +1074,7 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) dma_cookie_t cookie = 0; unsigned long desc_phys; struct ioat_desc_sw *latest_desc; + struct dma_async_tx_descriptor *tx; prefetch(ioat_chan->completion_virt); @@ -1111,8 +1098,7 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) if ((ioat_chan->completion_virt->full & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) { - dev_err(&ioat_chan->device->pdev->dev, - "Channel halted, chanerr = %x\n", + dev_err(to_dev(ioat_chan), "Channel halted, chanerr = %x\n", readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET)); /* TODO do something to salvage the situation */ @@ -1145,38 +1131,38 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) case IOAT_VER_1_2: list_for_each_entry_safe(desc, _desc, &ioat_chan->used_desc, node) { - + tx = &desc->txd; /* * Incoming DMA requests may use multiple descriptors, * due to exceeding xfercap, perhaps. If so, only the * last one will have a cookie, and require unmapping. */ - if (desc->async_tx.cookie) { - cookie = desc->async_tx.cookie; + if (tx->cookie) { + cookie = tx->cookie; ioat_dma_unmap(ioat_chan, desc); - if (desc->async_tx.callback) { - desc->async_tx.callback(desc->async_tx.callback_param); - desc->async_tx.callback = NULL; + if (tx->callback) { + tx->callback(tx->callback_param); + tx->callback = NULL; } } - if (desc->async_tx.phys != phys_complete) { + if (tx->phys != phys_complete) { /* * a completed entry, but not the last, so clean * up if the client is done with the descriptor */ - if (async_tx_test_ack(&desc->async_tx)) { + if (async_tx_test_ack(tx)) { list_move_tail(&desc->node, &ioat_chan->free_desc); } else - desc->async_tx.cookie = 0; + tx->cookie = 0; } else { /* * last used desc. Do not remove, so we can * append from it, but don't look at it next * time, either */ - desc->async_tx.cookie = 0; + tx->cookie = 0; /* TODO check status bits? */ break; @@ -1191,10 +1177,11 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) /* work backwards to find latest finished desc */ desc = to_ioat_desc(ioat_chan->used_desc.next); + tx = &desc->txd; latest_desc = NULL; do { desc = to_ioat_desc(desc->node.prev); - desc_phys = (unsigned long)desc->async_tx.phys + desc_phys = (unsigned long)tx->phys & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; if (desc_phys == phys_complete) { latest_desc = desc; @@ -1203,19 +1190,18 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) } while (&desc->node != ioat_chan->used_desc.prev); if (latest_desc != NULL) { - /* work forwards to clear finished descriptors */ for (desc = to_ioat_desc(ioat_chan->used_desc.prev); &desc->node != latest_desc->node.next && &desc->node != ioat_chan->used_desc.next; desc = to_ioat_desc(desc->node.next)) { - if (desc->async_tx.cookie) { - cookie = desc->async_tx.cookie; - desc->async_tx.cookie = 0; + if (tx->cookie) { + cookie = tx->cookie; + tx->cookie = 0; ioat_dma_unmap(ioat_chan, desc); - if (desc->async_tx.callback) { - desc->async_tx.callback(desc->async_tx.callback_param); - desc->async_tx.callback = NULL; + if (tx->callback) { + tx->callback(tx->callback_param); + tx->callback = NULL; } } } @@ -1245,10 +1231,9 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) * @done: if not %NULL, updated with last completed transaction * @used: if not %NULL, updated with last used transaction */ -static enum dma_status ioat_dma_is_complete(struct dma_chan *chan, - dma_cookie_t cookie, - dma_cookie_t *done, - dma_cookie_t *used) +static enum dma_status +ioat_dma_is_complete(struct dma_chan *chan, dma_cookie_t cookie, + dma_cookie_t *done, dma_cookie_t *used) { struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); dma_cookie_t last_used; @@ -1290,7 +1275,7 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan) desc = ioat_dma_get_next_descriptor(ioat_chan); if (!desc) { - dev_err(&ioat_chan->device->pdev->dev, + dev_err(to_dev(ioat_chan), "Unable to start null desc - get next desc failed\n"); spin_unlock_bh(&ioat_chan->desc_lock); return; @@ -1303,15 +1288,15 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan) desc->hw->size = NULL_DESC_BUFFER_SIZE; desc->hw->src_addr = 0; desc->hw->dst_addr = 0; - async_tx_ack(&desc->async_tx); + async_tx_ack(&desc->txd); switch (ioat_chan->device->version) { case IOAT_VER_1_2: desc->hw->next = 0; list_add_tail(&desc->node, &ioat_chan->used_desc); - writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF, + writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->async_tx.phys) >> 32, + writel(((u64) desc->txd.phys) >> 32, ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); writeb(IOAT_CHANCMD_START, ioat_chan->reg_base @@ -1319,9 +1304,9 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan) break; case IOAT_VER_2_0: case IOAT_VER_3_0: - writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF, + writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->async_tx.phys) >> 32, + writel(((u64) desc->txd.phys) >> 32, ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); ioat_chan->dmacount++; @@ -1352,6 +1337,8 @@ static int ioat_dma_self_test(struct ioatdma_device *device) int i; u8 *src; u8 *dest; + struct dma_device *dma = &device->common; + struct device *dev = &device->pdev->dev; struct dma_chan *dma_chan; struct dma_async_tx_descriptor *tx; dma_addr_t dma_dest, dma_src; @@ -1375,26 +1362,21 @@ static int ioat_dma_self_test(struct ioatdma_device *device) src[i] = (u8)i; /* Start copy, using first DMA channel */ - dma_chan = container_of(device->common.channels.next, - struct dma_chan, + dma_chan = container_of(dma->channels.next, struct dma_chan, device_node); - if (device->common.device_alloc_chan_resources(dma_chan) < 1) { - dev_err(&device->pdev->dev, - "selftest cannot allocate chan resource\n"); + if (dma->device_alloc_chan_resources(dma_chan) < 1) { + dev_err(dev, "selftest cannot allocate chan resource\n"); err = -ENODEV; goto out; } - dma_src = dma_map_single(dma_chan->device->dev, src, IOAT_TEST_SIZE, - DMA_TO_DEVICE); - dma_dest = dma_map_single(dma_chan->device->dev, dest, IOAT_TEST_SIZE, - DMA_FROM_DEVICE); + dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); + dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE; tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src, IOAT_TEST_SIZE, flags); if (!tx) { - dev_err(&device->pdev->dev, - "Self-test prep failed, disabling\n"); + dev_err(dev, "Self-test prep failed, disabling\n"); err = -ENODEV; goto free_resources; } @@ -1405,32 +1387,29 @@ static int ioat_dma_self_test(struct ioatdma_device *device) tx->callback_param = &cmp; cookie = tx->tx_submit(tx); if (cookie < 0) { - dev_err(&device->pdev->dev, - "Self-test setup failed, disabling\n"); + dev_err(dev, "Self-test setup failed, disabling\n"); err = -ENODEV; goto free_resources; } - device->common.device_issue_pending(dma_chan); + dma->device_issue_pending(dma_chan); tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); if (tmo == 0 || - device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL) + dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { - dev_err(&device->pdev->dev, - "Self-test copy timed out, disabling\n"); + dev_err(dev, "Self-test copy timed out, disabling\n"); err = -ENODEV; goto free_resources; } if (memcmp(src, dest, IOAT_TEST_SIZE)) { - dev_err(&device->pdev->dev, - "Self-test copy failed compare, disabling\n"); + dev_err(dev, "Self-test copy failed compare, disabling\n"); err = -ENODEV; goto free_resources; } free_resources: - device->common.device_free_chan_resources(dma_chan); + dma->device_free_chan_resources(dma_chan); out: kfree(src); kfree(dest); @@ -1483,15 +1462,14 @@ msix: for (i = 0; i < msixcnt; i++) { msix = &device->msix_entries[i]; - ioat_chan = ioat_lookup_chan_by_index(device, i); + ioat_chan = ioat_chan_by_index(device, i); err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt_msix, 0, "ioat-msix", ioat_chan); if (err) { for (j = 0; j < i; j++) { msix = &device->msix_entries[j]; - ioat_chan = - ioat_lookup_chan_by_index(device, j); + ioat_chan = ioat_chan_by_index(device, j); devm_free_irq(dev, msix->vector, ioat_chan); } goto msix_single_vector; @@ -1561,12 +1539,13 @@ static void ioat_disable_interrupts(struct ioatdma_device *device) writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); } -struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, - void __iomem *iobase) +struct ioatdma_device * +ioat_dma_probe(struct pci_dev *pdev, void __iomem *iobase) { int err; struct device *dev = &pdev->dev; struct ioatdma_device *device; + struct dma_device *dma; device = devm_kzalloc(dev, sizeof(*device), GFP_KERNEL); if (!device) @@ -1574,6 +1553,7 @@ struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, device->pdev = pdev; device->reg_base = iobase; device->version = readb(device->reg_base + IOAT_VER_OFFSET); + dma = &device->common; /* DMA coherent memory pool for DMA descriptor allocations */ device->dma_pool = pci_pool_create("dma_desc_pool", pdev, @@ -1592,36 +1572,32 @@ struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, goto err_completion_pool; } - INIT_LIST_HEAD(&device->common.channels); + INIT_LIST_HEAD(&dma->channels); ioat_dma_enumerate_channels(device); - device->common.device_alloc_chan_resources = - ioat_dma_alloc_chan_resources; - device->common.device_free_chan_resources = - ioat_dma_free_chan_resources; - device->common.dev = &pdev->dev; + dma->device_alloc_chan_resources = ioat_dma_alloc_chan_resources; + dma->device_free_chan_resources = ioat_dma_free_chan_resources; + dma->dev = &pdev->dev; - dma_cap_set(DMA_MEMCPY, device->common.cap_mask); - device->common.device_is_tx_complete = ioat_dma_is_complete; + dma_cap_set(DMA_MEMCPY, dma->cap_mask); + dma->device_is_tx_complete = ioat_dma_is_complete; switch (device->version) { case IOAT_VER_1_2: - device->common.device_prep_dma_memcpy = ioat1_dma_prep_memcpy; - device->common.device_issue_pending = - ioat1_dma_memcpy_issue_pending; + dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy; + dma->device_issue_pending = ioat1_dma_memcpy_issue_pending; break; case IOAT_VER_2_0: case IOAT_VER_3_0: - device->common.device_prep_dma_memcpy = ioat2_dma_prep_memcpy; - device->common.device_issue_pending = - ioat2_dma_memcpy_issue_pending; + dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy; + dma->device_issue_pending = ioat2_dma_memcpy_issue_pending; break; } dev_err(dev, "Intel(R) I/OAT DMA Engine found," " %d channels, device version 0x%02x, driver version %s\n", - device->common.chancnt, device->version, IOAT_DMA_VERSION); + dma->chancnt, device->version, IOAT_DMA_VERSION); - if (!device->common.chancnt) { + if (!dma->chancnt) { dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: " "zero channels detected\n"); goto err_setup_interrupts; @@ -1635,7 +1611,7 @@ struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, if (err) goto err_self_test; - err = dma_async_device_register(&device->common); + err = dma_async_device_register(dma); if (err) goto err_self_test; @@ -1663,19 +1639,19 @@ void ioat_dma_remove(struct ioatdma_device *device) { struct dma_chan *chan, *_chan; struct ioat_dma_chan *ioat_chan; + struct dma_device *dma = &device->common; if (device->version != IOAT_VER_3_0) cancel_delayed_work(&device->work); ioat_disable_interrupts(device); - dma_async_device_unregister(&device->common); + dma_async_device_unregister(dma); pci_pool_destroy(device->dma_pool); pci_pool_destroy(device->completion_pool); - list_for_each_entry_safe(chan, _chan, - &device->common.channels, device_node) { + list_for_each_entry_safe(chan, _chan, &dma->channels, device_node) { ioat_chan = to_ioat_chan(chan); list_del(&chan->device_node); } diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index 5e8d7cf..c5eabae 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -38,7 +38,8 @@ #define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common) #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) -#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx) +#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd) +#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev) #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) @@ -123,7 +124,7 @@ struct ioat_dma_chan { * @node: this descriptor will either be on the free list, * or attached to a transaction list (async_tx.tx_list) * @tx_cnt: number of descriptors required to complete the transaction - * @async_tx: the generic software descriptor for all engines + * @txd: the generic software descriptor for all engines */ struct ioat_desc_sw { struct ioat_dma_descriptor *hw; @@ -132,7 +133,7 @@ struct ioat_desc_sw { size_t len; dma_addr_t src; dma_addr_t dst; - struct dma_async_tx_descriptor async_tx; + struct dma_async_tx_descriptor txd; }; static inline void ioat_set_tcp_copy_break(struct ioatdma_device *dev) -- cgit v0.10.2 From b31b78f1ab7806759622b703357e39a21f757281 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 28 Jul 2009 14:42:32 -0700 Subject: ioat: kill function prototype ifdef guards The only .c files that utilize these protected prototypes depend on CONFIG_INTEL_IOATDMA=y, so there is no value gained in providing empty prototypes. [ Impact: pure cleanup ] Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index c5eabae..6e27ddb 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -153,19 +153,10 @@ static inline void ioat_set_tcp_copy_break(struct ioatdma_device *dev) #endif } -#if defined(CONFIG_INTEL_IOATDMA) || defined(CONFIG_INTEL_IOATDMA_MODULE) struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, void __iomem *iobase); void ioat_dma_remove(struct ioatdma_device *device); struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase); -#else -#define ioat_dma_probe(pdev, iobase) NULL -#define ioat_dma_remove(device) do { } while (0) -#define ioat_dca_init(pdev, iobase) NULL -#define ioat2_dca_init(pdev, iobase) NULL -#define ioat3_dca_init(pdev, iobase) NULL -#endif - #endif /* IOATDMA_H */ -- cgit v0.10.2 From f2427e276ffec5ce599c6bc116e0927269a360ef Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 28 Jul 2009 14:42:38 -0700 Subject: ioat: split ioat_dma_probe into core/version-specific routines Towards the removal of ioatdma_device.version split the initialization path into distinct versions. This conversion: 1/ moves version specific probe code to version specific routines 2/ removes the need for ioat_device 3/ turns off the ioat1 msi quirk if the device is reinitialized for intx Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 462dae6..b750804 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -121,52 +121,21 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device) int i; struct ioat_dma_chan *ioat_chan; struct device *dev = &device->pdev->dev; + struct dma_device *dma = &device->common; - /* - * IOAT ver.3 workarounds - */ - if (device->version == IOAT_VER_3_0) { - u32 chan_err_mask; - u16 dev_id; - u32 dmauncerrsts; - - /* - * Write CHANERRMSK_INT with 3E07h to mask out the errors - * that can cause stability issues for IOAT ver.3 - */ - chan_err_mask = 0x3E07; - pci_write_config_dword(device->pdev, - IOAT_PCI_CHANERRMASK_INT_OFFSET, - chan_err_mask); - - /* - * Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit - * (workaround for spurious config parity error after restart) - */ - pci_read_config_word(device->pdev, - IOAT_PCI_DEVICE_ID_OFFSET, - &dev_id); - if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) { - dmauncerrsts = 0x10; - pci_write_config_dword(device->pdev, - IOAT_PCI_DMAUNCERRSTS_OFFSET, - dmauncerrsts); - } - } - - device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); + INIT_LIST_HEAD(&dma->channels); + dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL - if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) { - device->common.chancnt--; - } + if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) + dma->chancnt--; #endif - for (i = 0; i < device->common.chancnt; i++) { + for (i = 0; i < dma->chancnt; i++) { ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL); if (!ioat_chan) { - device->common.chancnt = i; + dma->chancnt = i; break; } @@ -175,28 +144,20 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device) ioat_chan->xfercap = xfercap; ioat_chan->desccount = 0; INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2); - if (ioat_chan->device->version == IOAT_VER_2_0) - writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | - IOAT_DMA_DCA_ANY_CPU, - ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); - else if (ioat_chan->device->version == IOAT_VER_3_0) - writel(IOAT_DMA_DCA_ANY_CPU, - ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); spin_lock_init(&ioat_chan->cleanup_lock); spin_lock_init(&ioat_chan->desc_lock); INIT_LIST_HEAD(&ioat_chan->free_desc); INIT_LIST_HEAD(&ioat_chan->used_desc); /* This should be made common somewhere in dmaengine.c */ ioat_chan->common.device = &device->common; - list_add_tail(&ioat_chan->common.device_node, - &device->common.channels); + list_add_tail(&ioat_chan->common.device_node, &dma->channels); device->idx[i] = ioat_chan; tasklet_init(&ioat_chan->cleanup_task, ioat_dma_cleanup_tasklet, (unsigned long) ioat_chan); tasklet_disable(&ioat_chan->cleanup_task); } - return device->common.chancnt; + return dma->chancnt; } /** @@ -1504,15 +1465,6 @@ msi: pci_disable_msi(pdev); goto intx; } - /* - * CB 1.2 devices need a bit set in configuration space to enable MSI - */ - if (device->version == IOAT_VER_1_2) { - u32 dmactrl; - pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl); - dmactrl |= IOAT_PCI_DMACTRL_MSI_EN; - pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl); - } goto done; intx: @@ -1522,6 +1474,8 @@ intx: goto err_no_irq; done: + if (device->intr_quirk) + device->intr_quirk(device); intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET); return 0; @@ -1539,21 +1493,12 @@ static void ioat_disable_interrupts(struct ioatdma_device *device) writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); } -struct ioatdma_device * -ioat_dma_probe(struct pci_dev *pdev, void __iomem *iobase) +static int ioat_probe(struct ioatdma_device *device) { - int err; + int err = -ENODEV; + struct dma_device *dma = &device->common; + struct pci_dev *pdev = device->pdev; struct device *dev = &pdev->dev; - struct ioatdma_device *device; - struct dma_device *dma; - - device = devm_kzalloc(dev, sizeof(*device), GFP_KERNEL); - if (!device) - err = -ENOMEM; - device->pdev = pdev; - device->reg_base = iobase; - device->version = readb(device->reg_base + IOAT_VER_OFFSET); - dma = &device->common; /* DMA coherent memory pool for DMA descriptor allocations */ device->dma_pool = pci_pool_create("dma_desc_pool", pdev, @@ -1572,26 +1517,13 @@ ioat_dma_probe(struct pci_dev *pdev, void __iomem *iobase) goto err_completion_pool; } - INIT_LIST_HEAD(&dma->channels); ioat_dma_enumerate_channels(device); + dma_cap_set(DMA_MEMCPY, dma->cap_mask); dma->device_alloc_chan_resources = ioat_dma_alloc_chan_resources; dma->device_free_chan_resources = ioat_dma_free_chan_resources; - dma->dev = &pdev->dev; - - dma_cap_set(DMA_MEMCPY, dma->cap_mask); dma->device_is_tx_complete = ioat_dma_is_complete; - switch (device->version) { - case IOAT_VER_1_2: - dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy; - dma->device_issue_pending = ioat1_dma_memcpy_issue_pending; - break; - case IOAT_VER_2_0: - case IOAT_VER_3_0: - dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy; - dma->device_issue_pending = ioat2_dma_memcpy_issue_pending; - break; - } + dma->dev = &pdev->dev; dev_err(dev, "Intel(R) I/OAT DMA Engine found," " %d channels, device version 0x%02x, driver version %s\n", @@ -1611,19 +1543,7 @@ ioat_dma_probe(struct pci_dev *pdev, void __iomem *iobase) if (err) goto err_self_test; - err = dma_async_device_register(dma); - if (err) - goto err_self_test; - - ioat_set_tcp_copy_break(device); - - if (device->version != IOAT_VER_3_0) { - INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog); - schedule_delayed_work(&device->work, - WATCHDOG_DELAY); - } - - return device; + return 0; err_self_test: ioat_disable_interrupts(device); @@ -1632,7 +1552,142 @@ err_setup_interrupts: err_completion_pool: pci_pool_destroy(device->dma_pool); err_dma_pool: - return NULL; + return err; +} + +static int ioat_register(struct ioatdma_device *device) +{ + int err = dma_async_device_register(&device->common); + + if (err) { + ioat_disable_interrupts(device); + pci_pool_destroy(device->completion_pool); + pci_pool_destroy(device->dma_pool); + } + + return err; +} + +/* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */ +static void ioat1_intr_quirk(struct ioatdma_device *device) +{ + struct pci_dev *pdev = device->pdev; + u32 dmactrl; + + pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl); + if (pdev->msi_enabled) + dmactrl |= IOAT_PCI_DMACTRL_MSI_EN; + else + dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN; + pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl); +} + +int ioat1_dma_probe(struct ioatdma_device *device, int dca) +{ + struct pci_dev *pdev = device->pdev; + struct dma_device *dma; + int err; + + device->intr_quirk = ioat1_intr_quirk; + dma = &device->common; + dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy; + dma->device_issue_pending = ioat1_dma_memcpy_issue_pending; + + err = ioat_probe(device); + if (err) + return err; + ioat_set_tcp_copy_break(4096); + err = ioat_register(device); + if (err) + return err; + if (dca) + device->dca = ioat_dca_init(pdev, device->reg_base); + + INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog); + schedule_delayed_work(&device->work, WATCHDOG_DELAY); + + return err; +} + +int ioat2_dma_probe(struct ioatdma_device *device, int dca) +{ + struct pci_dev *pdev = device->pdev; + struct dma_device *dma; + struct dma_chan *chan; + struct ioat_dma_chan *ioat_chan; + int err; + + dma = &device->common; + dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy; + dma->device_issue_pending = ioat2_dma_memcpy_issue_pending; + + err = ioat_probe(device); + if (err) + return err; + ioat_set_tcp_copy_break(2048); + + list_for_each_entry(chan, &dma->channels, device_node) { + ioat_chan = to_ioat_chan(chan); + writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU, + ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); + } + + err = ioat_register(device); + if (err) + return err; + if (dca) + device->dca = ioat2_dca_init(pdev, device->reg_base); + + INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog); + schedule_delayed_work(&device->work, WATCHDOG_DELAY); + + return err; +} + +int ioat3_dma_probe(struct ioatdma_device *device, int dca) +{ + struct pci_dev *pdev = device->pdev; + struct dma_device *dma; + struct dma_chan *chan; + struct ioat_dma_chan *ioat_chan; + int err; + u16 dev_id; + + dma = &device->common; + dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy; + dma->device_issue_pending = ioat2_dma_memcpy_issue_pending; + + /* -= IOAT ver.3 workarounds =- */ + /* Write CHANERRMSK_INT with 3E07h to mask out the errors + * that can cause stability issues for IOAT ver.3 + */ + pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07); + + /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit + * (workaround for spurious config parity error after restart) + */ + pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); + if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) + pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10); + + err = ioat_probe(device); + if (err) + return err; + ioat_set_tcp_copy_break(262144); + + list_for_each_entry(chan, &dma->channels, device_node) { + ioat_chan = to_ioat_chan(chan); + writel(IOAT_DMA_DCA_ANY_CPU, + ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); + } + + err = ioat_register(device); + if (err) + return err; + if (dca) + device->dca = ioat3_dca_init(pdev, device->reg_base); + + return err; } void ioat_dma_remove(struct ioatdma_device *device) diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index 6e27ddb..1226e35 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -61,6 +61,8 @@ * @version: version of ioatdma device * @msix_entries: irq handlers * @idx: per channel data + * @dca: direct cache access context + * @intr_quirk: interrupt setup quirk (for ioat_v1 devices) */ struct ioatdma_device { @@ -73,6 +75,8 @@ struct ioatdma_device { struct delayed_work work; struct msix_entry msix_entries[4]; struct ioat_dma_chan *idx[4]; + struct dca_provider *dca; + void (*intr_quirk)(struct ioatdma_device *device); }; /** @@ -136,25 +140,16 @@ struct ioat_desc_sw { struct dma_async_tx_descriptor txd; }; -static inline void ioat_set_tcp_copy_break(struct ioatdma_device *dev) +static inline void ioat_set_tcp_copy_break(unsigned long copybreak) { #ifdef CONFIG_NET_DMA - switch (dev->version) { - case IOAT_VER_1_2: - sysctl_tcp_dma_copybreak = 4096; - break; - case IOAT_VER_2_0: - sysctl_tcp_dma_copybreak = 2048; - break; - case IOAT_VER_3_0: - sysctl_tcp_dma_copybreak = 262144; - break; - } + sysctl_tcp_dma_copybreak = copybreak; #endif } -struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, - void __iomem *iobase); +int ioat1_dma_probe(struct ioatdma_device *dev, int dca); +int ioat2_dma_probe(struct ioatdma_device *dev, int dca); +int ioat3_dma_probe(struct ioatdma_device *dev, int dca); void ioat_dma_remove(struct ioatdma_device *device); struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c index 982e38f..55414d8 100644 --- a/drivers/dma/ioat/pci.c +++ b/drivers/dma/ioat/pci.c @@ -60,14 +60,8 @@ static struct pci_device_id ioat_pci_tbl[] = { { 0, } }; -struct ioat_device { - struct pci_dev *pdev; - struct ioatdma_device *dma; - struct dca_provider *dca; -}; - -static int __devinit ioat_probe(struct pci_dev *pdev, - const struct pci_device_id *id); +static int __devinit ioat_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *id); static void __devexit ioat_remove(struct pci_dev *pdev); static int ioat_dca_enabled = 1; @@ -79,17 +73,28 @@ MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)" static struct pci_driver ioat_pci_driver = { .name = DRV_NAME, .id_table = ioat_pci_tbl, - .probe = ioat_probe, + .probe = ioat_pci_probe, .remove = __devexit_p(ioat_remove), }; -static int __devinit ioat_probe(struct pci_dev *pdev, - const struct pci_device_id *id) +static struct ioatdma_device * +alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase) +{ + struct device *dev = &pdev->dev; + struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); + + if (!d) + return NULL; + d->pdev = pdev; + d->reg_base = iobase; + return d; +} + +static int __devinit ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { void __iomem * const *iomap; - void __iomem *iobase; struct device *dev = &pdev->dev; - struct ioat_device *device; + struct ioatdma_device *device; int err; err = pcim_enable_device(pdev); @@ -119,33 +124,24 @@ static int __devinit ioat_probe(struct pci_dev *pdev, if (!device) return -ENOMEM; - device->pdev = pdev; - pci_set_drvdata(pdev, device); - iobase = iomap[IOAT_MMIO_BAR]; - pci_set_master(pdev); - switch (readb(iobase + IOAT_VER_OFFSET)) { - case IOAT_VER_1_2: - device->dma = ioat_dma_probe(pdev, iobase); - if (device->dma && ioat_dca_enabled) - device->dca = ioat_dca_init(pdev, iobase); - break; - case IOAT_VER_2_0: - device->dma = ioat_dma_probe(pdev, iobase); - if (device->dma && ioat_dca_enabled) - device->dca = ioat2_dca_init(pdev, iobase); - break; - case IOAT_VER_3_0: - device->dma = ioat_dma_probe(pdev, iobase); - if (device->dma && ioat_dca_enabled) - device->dca = ioat3_dca_init(pdev, iobase); - break; - default: + device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]); + if (!device) + return -ENOMEM; + pci_set_drvdata(pdev, device); + + device->version = readb(device->reg_base + IOAT_VER_OFFSET); + if (device->version == IOAT_VER_1_2) + err = ioat1_dma_probe(device, ioat_dca_enabled); + else if (device->version == IOAT_VER_2_0) + err = ioat2_dma_probe(device, ioat_dca_enabled); + else if (device->version >= IOAT_VER_3_0) + err = ioat3_dma_probe(device, ioat_dca_enabled); + else return -ENODEV; - } - if (!device->dma) { + if (err) { dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n"); return -ENODEV; } @@ -155,7 +151,10 @@ static int __devinit ioat_probe(struct pci_dev *pdev, static void __devexit ioat_remove(struct pci_dev *pdev) { - struct ioat_device *device = pci_get_drvdata(pdev); + struct ioatdma_device *device = pci_get_drvdata(pdev); + + if (!device) + return; dev_err(&pdev->dev, "Removing dma and dca services\n"); if (device->dca) { @@ -163,11 +162,7 @@ static void __devexit ioat_remove(struct pci_dev *pdev) free_dca_provider(device->dca); device->dca = NULL; } - - if (device->dma) { - ioat_dma_remove(device->dma); - device->dma = NULL; - } + ioat_dma_remove(device); } static int __init ioat_init_module(void) -- cgit v0.10.2 From 77867fff033ea549096c49d863c564ad7d8be36f Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 28 Jul 2009 14:44:04 -0700 Subject: ioat: fix type mismatch for ->dmacount ->dmacount tracks the sequence number of active descriptors. It is written to the DMACOUNT register to update the channel's view of pending descriptors in the chain. The register is 16-bits so ->dmacount should be unsigned and 16-bit as well. Also modify ->desccount to maintain alignment. This was never a problem in practice because we never compared dmacount values, but this is a bug waiting to happen. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index 1226e35..9f0c853 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -102,8 +102,8 @@ struct ioat_dma_chan { struct delayed_work work; int pending; - int dmacount; - int desccount; + u16 dmacount; + u16 desccount; struct ioatdma_device *device; struct dma_chan common; -- cgit v0.10.2 From c7984f4e4e3af3bf8027d636283ea8658c7f80b9 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 28 Jul 2009 14:44:04 -0700 Subject: ioat: define descriptor control bit-field This cleans up a mess of and'ing and or'ing bit definitions, and allows simple assignments from the specified dma_ctrl_flags parameter. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index b750804..4840d48 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -472,9 +472,9 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) return -ENOMEM; } - hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS; + hw->ctl_f.compl_write = 1; if (first->txd.callback) { - hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN; + hw->ctl_f.int_en = 1; if (first != new) { /* move callback into to last desc */ new->txd.callback = first->txd.callback; @@ -563,9 +563,9 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) return -ENOMEM; } - hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS; + hw->ctl_f.compl_write = 1; if (first->txd.callback) { - hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN; + hw->ctl_f.int_en = 1; if (first != new) { /* move callback into to last desc */ new->txd.callback = first->txd.callback; @@ -878,7 +878,8 @@ ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) noop_desc = to_ioat_desc(ioat_chan->used_desc.next); /* set size to non-zero value (channel returns error when size is 0) */ noop_desc->hw->size = NULL_DESC_BUFFER_SIZE; - noop_desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL; + noop_desc->hw->ctl = 0; + noop_desc->hw->ctl_f.null = 1; noop_desc->hw->src_addr = 0; noop_desc->hw->dst_addr = 0; @@ -1230,6 +1231,7 @@ ioat_dma_is_complete(struct dma_chan *chan, dma_cookie_t cookie, static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan) { struct ioat_desc_sw *desc; + struct ioat_dma_descriptor *hw; spin_lock_bh(&ioat_chan->desc_lock); @@ -1242,17 +1244,19 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan) return; } - desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL - | IOAT_DMA_DESCRIPTOR_CTL_INT_GN - | IOAT_DMA_DESCRIPTOR_CTL_CP_STS; + hw = desc->hw; + hw->ctl = 0; + hw->ctl_f.null = 1; + hw->ctl_f.int_en = 1; + hw->ctl_f.compl_write = 1; /* set size to non-zero value (channel returns error when size is 0) */ - desc->hw->size = NULL_DESC_BUFFER_SIZE; - desc->hw->src_addr = 0; - desc->hw->dst_addr = 0; + hw->size = NULL_DESC_BUFFER_SIZE; + hw->src_addr = 0; + hw->dst_addr = 0; async_tx_ack(&desc->txd); switch (ioat_chan->device->version) { case IOAT_VER_1_2: - desc->hw->next = 0; + hw->next = 0; list_add_tail(&desc->node, &ioat_chan->used_desc); writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, diff --git a/drivers/dma/ioat/hw.h b/drivers/dma/ioat/hw.h index 1438fa5..e13f3ed4 100644 --- a/drivers/dma/ioat/hw.h +++ b/drivers/dma/ioat/hw.h @@ -40,7 +40,24 @@ struct ioat_dma_descriptor { uint32_t size; - uint32_t ctl; + union { + uint32_t ctl; + struct { + unsigned int int_en:1; + unsigned int src_snoop_dis:1; + unsigned int dest_snoop_dis:1; + unsigned int compl_write:1; + unsigned int fence:1; + unsigned int null:1; + unsigned int src_brk:1; + unsigned int dest_brk:1; + unsigned int bundle:1; + unsigned int dest_dca:1; + unsigned int hint:1; + unsigned int rsvd2:13; + unsigned int op:8; + } ctl_f; + }; uint64_t src_addr; uint64_t dst_addr; uint64_t next; @@ -49,23 +66,4 @@ struct ioat_dma_descriptor { uint64_t user1; uint64_t user2; }; - -#define IOAT_DMA_DESCRIPTOR_CTL_INT_GN 0x00000001 -#define IOAT_DMA_DESCRIPTOR_CTL_SRC_SN 0x00000002 -#define IOAT_DMA_DESCRIPTOR_CTL_DST_SN 0x00000004 -#define IOAT_DMA_DESCRIPTOR_CTL_CP_STS 0x00000008 -#define IOAT_DMA_DESCRIPTOR_CTL_FRAME 0x00000010 -#define IOAT_DMA_DESCRIPTOR_NUL 0x00000020 -#define IOAT_DMA_DESCRIPTOR_CTL_SP_BRK 0x00000040 -#define IOAT_DMA_DESCRIPTOR_CTL_DP_BRK 0x00000080 -#define IOAT_DMA_DESCRIPTOR_CTL_BNDL 0x00000100 -#define IOAT_DMA_DESCRIPTOR_CTL_DCA 0x00000200 -#define IOAT_DMA_DESCRIPTOR_CTL_BUFHINT 0x00000400 - -#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_CONTEXT 0xFF000000 -#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_DMA 0x00000000 - -#define IOAT_DMA_DESCRIPTOR_CTL_CONTEXT_DCA 0x00000001 -#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_MASK 0xFF000000 - #endif -- cgit v0.10.2 From a0587bcf3e64029a4da2a5666cad18df38db0d56 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 28 Jul 2009 14:44:04 -0700 Subject: ioat1: move descriptor allocation from submit to prep The async_tx api assumes that after a successful ->prep a subsequent ->submit will not fail due to a lack of resources. This also fixes a bug in the allocation failure case. Previously the descriptors allocated prior to the allocation failure would not be returned to the free list. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 4840d48..c4333be 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -420,95 +420,29 @@ static void ioat_dma_chan_watchdog(struct work_struct *work) static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) { struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan); - struct ioat_desc_sw *first = tx_to_ioat_desc(tx); - struct ioat_desc_sw *prev, *new; - struct ioat_dma_descriptor *hw; + struct ioat_desc_sw *desc = tx_to_ioat_desc(tx); + struct ioat_desc_sw *first; + struct ioat_desc_sw *chain_tail; dma_cookie_t cookie; - LIST_HEAD(new_chain); - u32 copy; - size_t len; - dma_addr_t src, dst; - unsigned long orig_flags; - unsigned int desc_count = 0; - - /* src and dest and len are stored in the initial descriptor */ - len = first->len; - src = first->src; - dst = first->dst; - orig_flags = first->txd.flags; - new = first; spin_lock_bh(&ioat_chan->desc_lock); - prev = to_ioat_desc(ioat_chan->used_desc.prev); - prefetch(prev->hw); - do { - copy = min_t(size_t, len, ioat_chan->xfercap); - - async_tx_ack(&new->txd); - - hw = new->hw; - hw->size = copy; - hw->ctl = 0; - hw->src_addr = src; - hw->dst_addr = dst; - hw->next = 0; - - /* chain together the physical address list for the HW */ - wmb(); - prev->hw->next = (u64) new->txd.phys; - - len -= copy; - dst += copy; - src += copy; - - list_add_tail(&new->node, &new_chain); - desc_count++; - prev = new; - } while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan))); - - if (!new) { - dev_err(to_dev(ioat_chan), "tx submit failed\n"); - spin_unlock_bh(&ioat_chan->desc_lock); - return -ENOMEM; - } - - hw->ctl_f.compl_write = 1; - if (first->txd.callback) { - hw->ctl_f.int_en = 1; - if (first != new) { - /* move callback into to last desc */ - new->txd.callback = first->txd.callback; - new->txd.callback_param - = first->txd.callback_param; - first->txd.callback = NULL; - first->txd.callback_param = NULL; - } - } - - new->tx_cnt = desc_count; - new->txd.flags = orig_flags; /* client is in control of this ack */ - - /* store the original values for use in later cleanup */ - if (new != first) { - new->src = first->src; - new->dst = first->dst; - new->len = first->len; - } - /* cookie incr and addition to used_list must be atomic */ cookie = ioat_chan->common.cookie; cookie++; if (cookie < 0) cookie = 1; - ioat_chan->common.cookie = new->txd.cookie = cookie; + ioat_chan->common.cookie = tx->cookie = cookie; /* write address into NextDescriptor field of last desc in chain */ - to_ioat_desc(ioat_chan->used_desc.prev)->hw->next = - first->txd.phys; - list_splice_tail(&new_chain, &ioat_chan->used_desc); - - ioat_chan->dmacount += desc_count; - ioat_chan->pending += desc_count; + first = to_ioat_desc(tx->tx_list.next); + chain_tail = to_ioat_desc(ioat_chan->used_desc.prev); + /* make descriptor updates globally visible before chaining */ + wmb(); + chain_tail->hw->next = first->txd.phys; + list_splice_tail_init(&tx->tx_list, &ioat_chan->used_desc); + + ioat_chan->dmacount += desc->tx_cnt; + ioat_chan->pending += desc->tx_cnt; if (ioat_chan->pending >= ioat_pending_level) __ioat1_dma_memcpy_issue_pending(ioat_chan); spin_unlock_bh(&ioat_chan->desc_lock); @@ -937,24 +871,66 @@ ioat1_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, size_t len, unsigned long flags) { struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); - struct ioat_desc_sw *new; + struct ioat_desc_sw *desc; + size_t copy; + LIST_HEAD(chain); + dma_addr_t src = dma_src; + dma_addr_t dest = dma_dest; + size_t total_len = len; + struct ioat_dma_descriptor *hw = NULL; + int tx_cnt = 0; spin_lock_bh(&ioat_chan->desc_lock); - new = ioat_dma_get_next_descriptor(ioat_chan); - spin_unlock_bh(&ioat_chan->desc_lock); + desc = ioat_dma_get_next_descriptor(ioat_chan); + do { + if (!desc) + break; - if (new) { - new->len = len; - new->dst = dma_dest; - new->src = dma_src; - new->txd.flags = flags; - return &new->txd; - } else { + tx_cnt++; + copy = min_t(size_t, len, ioat_chan->xfercap); + + hw = desc->hw; + hw->size = copy; + hw->ctl = 0; + hw->src_addr = src; + hw->dst_addr = dest; + + list_add_tail(&desc->node, &chain); + + len -= copy; + dest += copy; + src += copy; + if (len) { + struct ioat_desc_sw *next; + + async_tx_ack(&desc->txd); + next = ioat_dma_get_next_descriptor(ioat_chan); + hw->next = next ? next->txd.phys : 0; + desc = next; + } else + hw->next = 0; + } while (len); + + if (!desc) { dev_err(to_dev(ioat_chan), "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n", chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); + list_splice(&chain, &ioat_chan->free_desc); + spin_unlock_bh(&ioat_chan->desc_lock); return NULL; } + spin_unlock_bh(&ioat_chan->desc_lock); + + desc->txd.flags = flags; + desc->tx_cnt = tx_cnt; + desc->src = dma_src; + desc->dst = dma_dest; + desc->len = total_len; + list_splice(&chain, &desc->txd.tx_list); + hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); + hw->ctl_f.compl_write = 1; + + return &desc->txd; } static struct dma_async_tx_descriptor * -- cgit v0.10.2 From a6a39ca1badbeafc16941fcf2c1010c8c65c8ddc Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 28 Jul 2009 14:44:05 -0700 Subject: ioat: fix self test interrupts If a callback is to be attached to a descriptor the channel needs to know at ->prep time so it can set the interrupt enable bit. This is in preparation for moving descriptor ioat2 descriptor preparation from ->submit to ->prep. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index c4333be..cc5c557 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -1313,7 +1313,8 @@ static int ioat_dma_self_test(struct ioatdma_device *device) dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); - flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE; + flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE | + DMA_PREP_INTERRUPT; tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src, IOAT_TEST_SIZE, flags); if (!tx) { -- cgit v0.10.2 From dcbc853af6f0c056088e4df0794d9bf36184809e Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 28 Jul 2009 14:44:50 -0700 Subject: ioat: prepare the code for ioat[12]_dma_chan split Prepare the code for the conversion of the ioat2 linked-list-ring into a native ring buffer. After this conversion ioat2 channels will share less of the ioat1 infrastructure, but there will still be places where sharing is possible. struct ioat_chan_common is created to house the channel attributes that will remain common between ioat1 and ioat2 channels. For every routine that accesses both common and hardware specific fields the old unified 'ioat_chan' pointer is split into an 'ioat' and 'chan' pointer. Where 'chan' references common fields and 'ioat' the hardware/version specific. [ Impact: pure structure member movement/variable renames, no logic changes ] Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index cc5c557..2e81e0c 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -47,15 +47,15 @@ static void ioat_dma_chan_reset_part2(struct work_struct *work); static void ioat_dma_chan_watchdog(struct work_struct *work); /* internal functions */ -static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan); -static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan); +static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat); +static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat); static struct ioat_desc_sw * -ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan); +ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat); static struct ioat_desc_sw * -ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan); +ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat); -static inline struct ioat_dma_chan * +static inline struct ioat_chan_common * ioat_chan_by_index(struct ioatdma_device *device, int index) { return device->idx[index]; @@ -69,7 +69,7 @@ ioat_chan_by_index(struct ioatdma_device *device, int index) static irqreturn_t ioat_dma_do_interrupt(int irq, void *data) { struct ioatdma_device *instance = data; - struct ioat_dma_chan *ioat_chan; + struct ioat_chan_common *chan; unsigned long attnstatus; int bit; u8 intrctrl; @@ -86,8 +86,8 @@ static irqreturn_t ioat_dma_do_interrupt(int irq, void *data) attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); for_each_bit(bit, &attnstatus, BITS_PER_LONG) { - ioat_chan = ioat_chan_by_index(instance, bit); - tasklet_schedule(&ioat_chan->cleanup_task); + chan = ioat_chan_by_index(instance, bit); + tasklet_schedule(&chan->cleanup_task); } writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); @@ -101,9 +101,9 @@ static irqreturn_t ioat_dma_do_interrupt(int irq, void *data) */ static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) { - struct ioat_dma_chan *ioat_chan = data; + struct ioat_chan_common *chan = data; - tasklet_schedule(&ioat_chan->cleanup_task); + tasklet_schedule(&chan->cleanup_task); return IRQ_HANDLED; } @@ -119,7 +119,8 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device) u8 xfercap_scale; u32 xfercap; int i; - struct ioat_dma_chan *ioat_chan; + struct ioat_chan_common *chan; + struct ioat_dma_chan *ioat; struct device *dev = &device->pdev->dev; struct dma_device *dma = &device->common; @@ -133,29 +134,30 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device) dma->chancnt--; #endif for (i = 0; i < dma->chancnt; i++) { - ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL); - if (!ioat_chan) { + ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL); + if (!ioat) { dma->chancnt = i; break; } - ioat_chan->device = device; - ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1)); - ioat_chan->xfercap = xfercap; - ioat_chan->desccount = 0; - INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2); - spin_lock_init(&ioat_chan->cleanup_lock); - spin_lock_init(&ioat_chan->desc_lock); - INIT_LIST_HEAD(&ioat_chan->free_desc); - INIT_LIST_HEAD(&ioat_chan->used_desc); + chan = &ioat->base; + chan->device = device; + chan->reg_base = device->reg_base + (0x80 * (i + 1)); + ioat->xfercap = xfercap; + ioat->desccount = 0; + INIT_DELAYED_WORK(&chan->work, ioat_dma_chan_reset_part2); + spin_lock_init(&chan->cleanup_lock); + spin_lock_init(&ioat->desc_lock); + INIT_LIST_HEAD(&ioat->free_desc); + INIT_LIST_HEAD(&ioat->used_desc); /* This should be made common somewhere in dmaengine.c */ - ioat_chan->common.device = &device->common; - list_add_tail(&ioat_chan->common.device_node, &dma->channels); - device->idx[i] = ioat_chan; - tasklet_init(&ioat_chan->cleanup_task, + chan->common.device = &device->common; + list_add_tail(&chan->common.device_node, &dma->channels); + device->idx[i] = chan; + tasklet_init(&chan->cleanup_task, ioat_dma_cleanup_tasklet, - (unsigned long) ioat_chan); - tasklet_disable(&ioat_chan->cleanup_task); + (unsigned long) ioat); + tasklet_disable(&chan->cleanup_task); } return dma->chancnt; } @@ -166,39 +168,42 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device) * @chan: DMA channel handle */ static inline void -__ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat_chan) +__ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat) { - ioat_chan->pending = 0; - writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET); + void __iomem *reg_base = ioat->base.reg_base; + + ioat->pending = 0; + writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET); } static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan) { - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + struct ioat_dma_chan *ioat = to_ioat_chan(chan); - if (ioat_chan->pending > 0) { - spin_lock_bh(&ioat_chan->desc_lock); - __ioat1_dma_memcpy_issue_pending(ioat_chan); - spin_unlock_bh(&ioat_chan->desc_lock); + if (ioat->pending > 0) { + spin_lock_bh(&ioat->desc_lock); + __ioat1_dma_memcpy_issue_pending(ioat); + spin_unlock_bh(&ioat->desc_lock); } } static inline void -__ioat2_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat_chan) +__ioat2_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat) { - ioat_chan->pending = 0; - writew(ioat_chan->dmacount, - ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); + void __iomem *reg_base = ioat->base.reg_base; + + ioat->pending = 0; + writew(ioat->dmacount, reg_base + IOAT_CHAN_DMACOUNT_OFFSET); } static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan) { - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + struct ioat_dma_chan *ioat = to_ioat_chan(chan); - if (ioat_chan->pending > 0) { - spin_lock_bh(&ioat_chan->desc_lock); - __ioat2_dma_memcpy_issue_pending(ioat_chan); - spin_unlock_bh(&ioat_chan->desc_lock); + if (ioat->pending > 0) { + spin_lock_bh(&ioat->desc_lock); + __ioat2_dma_memcpy_issue_pending(ioat); + spin_unlock_bh(&ioat->desc_lock); } } @@ -208,84 +213,88 @@ static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan) */ static void ioat_dma_chan_reset_part2(struct work_struct *work) { - struct ioat_dma_chan *ioat_chan = - container_of(work, struct ioat_dma_chan, work.work); + struct ioat_chan_common *chan; + struct ioat_dma_chan *ioat; struct ioat_desc_sw *desc; - spin_lock_bh(&ioat_chan->cleanup_lock); - spin_lock_bh(&ioat_chan->desc_lock); + chan = container_of(work, struct ioat_chan_common, work.work); + ioat = container_of(chan, struct ioat_dma_chan, base); + spin_lock_bh(&chan->cleanup_lock); + spin_lock_bh(&ioat->desc_lock); - ioat_chan->completion_virt->low = 0; - ioat_chan->completion_virt->high = 0; - ioat_chan->pending = 0; + chan->completion_virt->low = 0; + chan->completion_virt->high = 0; + ioat->pending = 0; /* * count the descriptors waiting, and be sure to do it * right for both the CB1 line and the CB2 ring */ - ioat_chan->dmacount = 0; - if (ioat_chan->used_desc.prev) { - desc = to_ioat_desc(ioat_chan->used_desc.prev); + ioat->dmacount = 0; + if (ioat->used_desc.prev) { + desc = to_ioat_desc(ioat->used_desc.prev); do { - ioat_chan->dmacount++; + ioat->dmacount++; desc = to_ioat_desc(desc->node.next); - } while (&desc->node != ioat_chan->used_desc.next); + } while (&desc->node != ioat->used_desc.next); } /* * write the new starting descriptor address * this puts channel engine into ARMED state */ - desc = to_ioat_desc(ioat_chan->used_desc.prev); - switch (ioat_chan->device->version) { + desc = to_ioat_desc(ioat->used_desc.prev); + switch (chan->device->version) { case IOAT_VER_1_2: writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, - ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); + chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); writel(((u64) desc->txd.phys) >> 32, - ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); + chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); - writeb(IOAT_CHANCMD_START, ioat_chan->reg_base - + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); + writeb(IOAT_CHANCMD_START, chan->reg_base + + IOAT_CHANCMD_OFFSET(chan->device->version)); break; case IOAT_VER_2_0: writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, - ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); + chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); writel(((u64) desc->txd.phys) >> 32, - ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); + chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); /* tell the engine to go with what's left to be done */ - writew(ioat_chan->dmacount, - ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); + writew(ioat->dmacount, + chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); break; } - dev_err(to_dev(ioat_chan), + dev_err(to_dev(chan), "chan%d reset - %d descs waiting, %d total desc\n", - chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); + chan_num(chan), ioat->dmacount, ioat->desccount); - spin_unlock_bh(&ioat_chan->desc_lock); - spin_unlock_bh(&ioat_chan->cleanup_lock); + spin_unlock_bh(&ioat->desc_lock); + spin_unlock_bh(&chan->cleanup_lock); } /** * ioat_dma_reset_channel - restart a channel - * @ioat_chan: IOAT DMA channel handle + * @ioat: IOAT DMA channel handle */ -static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan) +static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat) { + struct ioat_chan_common *chan = &ioat->base; + void __iomem *reg_base = chan->reg_base; u32 chansts, chanerr; - if (!ioat_chan->used_desc.prev) + if (!ioat->used_desc.prev) return; - chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); - chansts = (ioat_chan->completion_virt->low + chanerr = readl(reg_base + IOAT_CHANERR_OFFSET); + chansts = (chan->completion_virt->low & IOAT_CHANSTS_DMA_TRANSFER_STATUS); if (chanerr) { - dev_err(to_dev(ioat_chan), + dev_err(to_dev(chan), "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", - chan_num(ioat_chan), chansts, chanerr); - writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); + chan_num(chan), chansts, chanerr); + writel(chanerr, reg_base + IOAT_CHANERR_OFFSET); } /* @@ -296,15 +305,14 @@ static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan) * while we're waiting. */ - spin_lock_bh(&ioat_chan->desc_lock); - ioat_chan->pending = INT_MIN; + spin_lock_bh(&ioat->desc_lock); + ioat->pending = INT_MIN; writeb(IOAT_CHANCMD_RESET, - ioat_chan->reg_base - + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); - spin_unlock_bh(&ioat_chan->desc_lock); + reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); + spin_unlock_bh(&ioat->desc_lock); /* schedule the 2nd half instead of sleeping a long time */ - schedule_delayed_work(&ioat_chan->work, RESET_DELAY); + schedule_delayed_work(&chan->work, RESET_DELAY); } /** @@ -314,7 +322,8 @@ static void ioat_dma_chan_watchdog(struct work_struct *work) { struct ioatdma_device *device = container_of(work, struct ioatdma_device, work.work); - struct ioat_dma_chan *ioat_chan; + struct ioat_dma_chan *ioat; + struct ioat_chan_common *chan; int i; union { @@ -327,23 +336,21 @@ static void ioat_dma_chan_watchdog(struct work_struct *work) unsigned long compl_desc_addr_hw; for (i = 0; i < device->common.chancnt; i++) { - ioat_chan = ioat_chan_by_index(device, i); + chan = ioat_chan_by_index(device, i); + ioat = container_of(chan, struct ioat_dma_chan, base); - if (ioat_chan->device->version == IOAT_VER_1_2 + if (chan->device->version == IOAT_VER_1_2 /* have we started processing anything yet */ - && ioat_chan->last_completion + && chan->last_completion /* have we completed any since last watchdog cycle? */ - && (ioat_chan->last_completion == - ioat_chan->watchdog_completion) + && (chan->last_completion == chan->watchdog_completion) /* has TCP stuck on one cookie since last watchdog? */ - && (ioat_chan->watchdog_tcp_cookie == - ioat_chan->watchdog_last_tcp_cookie) - && (ioat_chan->watchdog_tcp_cookie != - ioat_chan->completed_cookie) + && (chan->watchdog_tcp_cookie == chan->watchdog_last_tcp_cookie) + && (chan->watchdog_tcp_cookie != chan->completed_cookie) /* is there something in the chain to be processed? */ /* CB1 chain always has at least the last one processed */ - && (ioat_chan->used_desc.prev != ioat_chan->used_desc.next) - && ioat_chan->pending == 0) { + && (ioat->used_desc.prev != ioat->used_desc.next) + && ioat->pending == 0) { /* * check CHANSTS register for completed @@ -360,10 +367,10 @@ static void ioat_dma_chan_watchdog(struct work_struct *work) * try resetting the channel */ - completion_hw.low = readl(ioat_chan->reg_base + - IOAT_CHANSTS_OFFSET_LOW(ioat_chan->device->version)); - completion_hw.high = readl(ioat_chan->reg_base + - IOAT_CHANSTS_OFFSET_HIGH(ioat_chan->device->version)); + completion_hw.low = readl(chan->reg_base + + IOAT_CHANSTS_OFFSET_LOW(chan->device->version)); + completion_hw.high = readl(chan->reg_base + + IOAT_CHANSTS_OFFSET_HIGH(chan->device->version)); #if (BITS_PER_LONG == 64) compl_desc_addr_hw = completion_hw.full @@ -374,15 +381,15 @@ static void ioat_dma_chan_watchdog(struct work_struct *work) #endif if ((compl_desc_addr_hw != 0) - && (compl_desc_addr_hw != ioat_chan->watchdog_completion) - && (compl_desc_addr_hw != ioat_chan->last_compl_desc_addr_hw)) { - ioat_chan->last_compl_desc_addr_hw = compl_desc_addr_hw; - ioat_chan->completion_virt->low = completion_hw.low; - ioat_chan->completion_virt->high = completion_hw.high; + && (compl_desc_addr_hw != chan->watchdog_completion) + && (compl_desc_addr_hw != chan->last_compl_desc_addr_hw)) { + chan->last_compl_desc_addr_hw = compl_desc_addr_hw; + chan->completion_virt->low = completion_hw.low; + chan->completion_virt->high = completion_hw.high; } else { - ioat_dma_reset_channel(ioat_chan); - ioat_chan->watchdog_completion = 0; - ioat_chan->last_compl_desc_addr_hw = 0; + ioat_dma_reset_channel(ioat); + chan->watchdog_completion = 0; + chan->last_compl_desc_addr_hw = 0; } /* @@ -393,25 +400,22 @@ static void ioat_dma_chan_watchdog(struct work_struct *work) * else * try resetting the channel */ - } else if (ioat_chan->device->version == IOAT_VER_2_0 - && ioat_chan->used_desc.prev - && ioat_chan->last_completion - && ioat_chan->last_completion == ioat_chan->watchdog_completion) { + } else if (chan->device->version == IOAT_VER_2_0 + && ioat->used_desc.prev + && chan->last_completion + && chan->last_completion == chan->watchdog_completion) { - if (ioat_chan->pending < ioat_pending_level) - ioat2_dma_memcpy_issue_pending(&ioat_chan->common); + if (ioat->pending < ioat_pending_level) + ioat2_dma_memcpy_issue_pending(&chan->common); else { - ioat_dma_reset_channel(ioat_chan); - ioat_chan->watchdog_completion = 0; + ioat_dma_reset_channel(ioat); + chan->watchdog_completion = 0; } } else { - ioat_chan->last_compl_desc_addr_hw = 0; - ioat_chan->watchdog_completion - = ioat_chan->last_completion; + chan->last_compl_desc_addr_hw = 0; + chan->watchdog_completion = chan->last_completion; } - - ioat_chan->watchdog_last_tcp_cookie = - ioat_chan->watchdog_tcp_cookie; + chan->watchdog_last_tcp_cookie = chan->watchdog_tcp_cookie; } schedule_delayed_work(&device->work, WATCHDOG_DELAY); @@ -419,40 +423,42 @@ static void ioat_dma_chan_watchdog(struct work_struct *work) static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) { - struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan); + struct dma_chan *c = tx->chan; + struct ioat_dma_chan *ioat = to_ioat_chan(c); struct ioat_desc_sw *desc = tx_to_ioat_desc(tx); struct ioat_desc_sw *first; struct ioat_desc_sw *chain_tail; dma_cookie_t cookie; - spin_lock_bh(&ioat_chan->desc_lock); + spin_lock_bh(&ioat->desc_lock); /* cookie incr and addition to used_list must be atomic */ - cookie = ioat_chan->common.cookie; + cookie = c->cookie; cookie++; if (cookie < 0) cookie = 1; - ioat_chan->common.cookie = tx->cookie = cookie; + c->cookie = cookie; + tx->cookie = cookie; /* write address into NextDescriptor field of last desc in chain */ first = to_ioat_desc(tx->tx_list.next); - chain_tail = to_ioat_desc(ioat_chan->used_desc.prev); + chain_tail = to_ioat_desc(ioat->used_desc.prev); /* make descriptor updates globally visible before chaining */ wmb(); chain_tail->hw->next = first->txd.phys; - list_splice_tail_init(&tx->tx_list, &ioat_chan->used_desc); + list_splice_tail_init(&tx->tx_list, &ioat->used_desc); - ioat_chan->dmacount += desc->tx_cnt; - ioat_chan->pending += desc->tx_cnt; - if (ioat_chan->pending >= ioat_pending_level) - __ioat1_dma_memcpy_issue_pending(ioat_chan); - spin_unlock_bh(&ioat_chan->desc_lock); + ioat->dmacount += desc->tx_cnt; + ioat->pending += desc->tx_cnt; + if (ioat->pending >= ioat_pending_level) + __ioat1_dma_memcpy_issue_pending(ioat); + spin_unlock_bh(&ioat->desc_lock); return cookie; } static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) { - struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan); + struct ioat_dma_chan *ioat = to_ioat_chan(tx->chan); struct ioat_desc_sw *first = tx_to_ioat_desc(tx); struct ioat_desc_sw *new; struct ioat_dma_descriptor *hw; @@ -471,11 +477,11 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) new = first; /* - * ioat_chan->desc_lock is still in force in version 2 path + * ioat->desc_lock is still in force in version 2 path * it gets unlocked at end of this function */ do { - copy = min_t(size_t, len, ioat_chan->xfercap); + copy = min_t(size_t, len, ioat->xfercap); async_tx_ack(&new->txd); @@ -489,11 +495,11 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) dst += copy; src += copy; desc_count++; - } while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan))); + } while (len && (new = ioat2_dma_get_next_descriptor(ioat))); if (!new) { - dev_err(to_dev(ioat_chan), "tx submit failed\n"); - spin_unlock_bh(&ioat_chan->desc_lock); + dev_err(to_dev(&ioat->base), "tx submit failed\n"); + spin_unlock_bh(&ioat->desc_lock); return -ENOMEM; } @@ -521,35 +527,35 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) } /* cookie incr and addition to used_list must be atomic */ - cookie = ioat_chan->common.cookie; + cookie = ioat->base.common.cookie; cookie++; if (cookie < 0) cookie = 1; - ioat_chan->common.cookie = new->txd.cookie = cookie; + ioat->base.common.cookie = new->txd.cookie = cookie; - ioat_chan->dmacount += desc_count; - ioat_chan->pending += desc_count; - if (ioat_chan->pending >= ioat_pending_level) - __ioat2_dma_memcpy_issue_pending(ioat_chan); - spin_unlock_bh(&ioat_chan->desc_lock); + ioat->dmacount += desc_count; + ioat->pending += desc_count; + if (ioat->pending >= ioat_pending_level) + __ioat2_dma_memcpy_issue_pending(ioat); + spin_unlock_bh(&ioat->desc_lock); return cookie; } /** * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair - * @ioat_chan: the channel supplying the memory pool for the descriptors + * @ioat: the channel supplying the memory pool for the descriptors * @flags: allocation flags */ static struct ioat_desc_sw * -ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat_chan, gfp_t flags) +ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags) { struct ioat_dma_descriptor *desc; struct ioat_desc_sw *desc_sw; struct ioatdma_device *ioatdma_device; dma_addr_t phys; - ioatdma_device = to_ioatdma_device(ioat_chan->common.device); + ioatdma_device = ioat->base.device; desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys); if (unlikely(!desc)) return NULL; @@ -561,8 +567,8 @@ ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat_chan, gfp_t flags) } memset(desc, 0, sizeof(*desc)); - dma_async_tx_descriptor_init(&desc_sw->txd, &ioat_chan->common); - switch (ioat_chan->device->version) { + dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common); + switch (ioatdma_device->version) { case IOAT_VER_1_2: desc_sw->txd.tx_submit = ioat1_tx_submit; break; @@ -585,26 +591,26 @@ MODULE_PARM_DESC(ioat_initial_desc_count, /** * ioat2_dma_massage_chan_desc - link the descriptors into a circle - * @ioat_chan: the channel to be massaged + * @ioat: the channel to be massaged */ -static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan) +static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat) { struct ioat_desc_sw *desc, *_desc; /* setup used_desc */ - ioat_chan->used_desc.next = ioat_chan->free_desc.next; - ioat_chan->used_desc.prev = NULL; + ioat->used_desc.next = ioat->free_desc.next; + ioat->used_desc.prev = NULL; /* pull free_desc out of the circle so that every node is a hw * descriptor, but leave it pointing to the list */ - ioat_chan->free_desc.prev->next = ioat_chan->free_desc.next; - ioat_chan->free_desc.next->prev = ioat_chan->free_desc.prev; + ioat->free_desc.prev->next = ioat->free_desc.next; + ioat->free_desc.next->prev = ioat->free_desc.prev; /* circle link the hw descriptors */ - desc = to_ioat_desc(ioat_chan->free_desc.next); + desc = to_ioat_desc(ioat->free_desc.next); desc->hw->next = to_ioat_desc(desc->node.next)->txd.phys; - list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) { + list_for_each_entry_safe(desc, _desc, ioat->free_desc.next, node) { desc->hw->next = to_ioat_desc(desc->node.next)->txd.phys; } } @@ -613,9 +619,10 @@ static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan) * ioat_dma_alloc_chan_resources - returns the number of allocated descriptors * @chan: the channel to be filled out */ -static int ioat_dma_alloc_chan_resources(struct dma_chan *chan) +static int ioat_dma_alloc_chan_resources(struct dma_chan *c) { - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + struct ioat_dma_chan *ioat = to_ioat_chan(c); + struct ioat_chan_common *chan = &ioat->base; struct ioat_desc_sw *desc; u16 chanctrl; u32 chanerr; @@ -623,89 +630,87 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan) LIST_HEAD(tmp_list); /* have we already been set up? */ - if (!list_empty(&ioat_chan->free_desc)) - return ioat_chan->desccount; + if (!list_empty(&ioat->free_desc)) + return ioat->desccount; /* Setup register to interrupt and write completion status on error */ chanctrl = IOAT_CHANCTRL_ERR_INT_EN | IOAT_CHANCTRL_ANY_ERR_ABORT_EN | IOAT_CHANCTRL_ERR_COMPLETION_EN; - writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); + writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET); - chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); + chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); if (chanerr) { - dev_err(to_dev(ioat_chan), "CHANERR = %x, clearing\n", chanerr); - writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); + dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr); + writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); } /* Allocate descriptors */ for (i = 0; i < ioat_initial_desc_count; i++) { - desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL); + desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL); if (!desc) { - dev_err(to_dev(ioat_chan), - "Only %d initial descriptors\n", i); + dev_err(to_dev(chan), "Only %d initial descriptors\n", i); break; } list_add_tail(&desc->node, &tmp_list); } - spin_lock_bh(&ioat_chan->desc_lock); - ioat_chan->desccount = i; - list_splice(&tmp_list, &ioat_chan->free_desc); - if (ioat_chan->device->version != IOAT_VER_1_2) - ioat2_dma_massage_chan_desc(ioat_chan); - spin_unlock_bh(&ioat_chan->desc_lock); + spin_lock_bh(&ioat->desc_lock); + ioat->desccount = i; + list_splice(&tmp_list, &ioat->free_desc); + if (chan->device->version != IOAT_VER_1_2) + ioat2_dma_massage_chan_desc(ioat); + spin_unlock_bh(&ioat->desc_lock); /* allocate a completion writeback area */ /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ - ioat_chan->completion_virt = - pci_pool_alloc(ioat_chan->device->completion_pool, - GFP_KERNEL, - &ioat_chan->completion_addr); - memset(ioat_chan->completion_virt, 0, - sizeof(*ioat_chan->completion_virt)); - writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF, - ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); - writel(((u64) ioat_chan->completion_addr) >> 32, - ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); - - tasklet_enable(&ioat_chan->cleanup_task); - ioat_dma_start_null_desc(ioat_chan); /* give chain to dma device */ - return ioat_chan->desccount; + chan->completion_virt = pci_pool_alloc(chan->device->completion_pool, + GFP_KERNEL, + &chan->completion_addr); + memset(chan->completion_virt, 0, + sizeof(*chan->completion_virt)); + writel(((u64) chan->completion_addr) & 0x00000000FFFFFFFF, + chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); + writel(((u64) chan->completion_addr) >> 32, + chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); + + tasklet_enable(&chan->cleanup_task); + ioat_dma_start_null_desc(ioat); /* give chain to dma device */ + return ioat->desccount; } /** * ioat_dma_free_chan_resources - release all the descriptors * @chan: the channel to be cleaned */ -static void ioat_dma_free_chan_resources(struct dma_chan *chan) +static void ioat_dma_free_chan_resources(struct dma_chan *c) { - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); - struct ioatdma_device *ioatdma_device = to_ioatdma_device(chan->device); + struct ioat_dma_chan *ioat = to_ioat_chan(c); + struct ioat_chan_common *chan = &ioat->base; + struct ioatdma_device *ioatdma_device = chan->device; struct ioat_desc_sw *desc, *_desc; int in_use_descs = 0; /* Before freeing channel resources first check * if they have been previously allocated for this channel. */ - if (ioat_chan->desccount == 0) + if (ioat->desccount == 0) return; - tasklet_disable(&ioat_chan->cleanup_task); - ioat_dma_memcpy_cleanup(ioat_chan); + tasklet_disable(&chan->cleanup_task); + ioat_dma_memcpy_cleanup(ioat); /* Delay 100ms after reset to allow internal DMA logic to quiesce * before removing DMA descriptor resources. */ writeb(IOAT_CHANCMD_RESET, - ioat_chan->reg_base - + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); + chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); mdelay(100); - spin_lock_bh(&ioat_chan->desc_lock); - switch (ioat_chan->device->version) { + spin_lock_bh(&ioat->desc_lock); + switch (chan->device->version) { case IOAT_VER_1_2: list_for_each_entry_safe(desc, _desc, - &ioat_chan->used_desc, node) { + &ioat->used_desc, node) { in_use_descs++; list_del(&desc->node); pci_pool_free(ioatdma_device->dma_pool, desc->hw, @@ -713,7 +718,7 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan) kfree(desc); } list_for_each_entry_safe(desc, _desc, - &ioat_chan->free_desc, node) { + &ioat->free_desc, node) { list_del(&desc->node); pci_pool_free(ioatdma_device->dma_pool, desc->hw, desc->txd.phys); @@ -723,62 +728,61 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan) case IOAT_VER_2_0: case IOAT_VER_3_0: list_for_each_entry_safe(desc, _desc, - ioat_chan->free_desc.next, node) { + ioat->free_desc.next, node) { list_del(&desc->node); pci_pool_free(ioatdma_device->dma_pool, desc->hw, desc->txd.phys); kfree(desc); } - desc = to_ioat_desc(ioat_chan->free_desc.next); + desc = to_ioat_desc(ioat->free_desc.next); pci_pool_free(ioatdma_device->dma_pool, desc->hw, desc->txd.phys); kfree(desc); - INIT_LIST_HEAD(&ioat_chan->free_desc); - INIT_LIST_HEAD(&ioat_chan->used_desc); + INIT_LIST_HEAD(&ioat->free_desc); + INIT_LIST_HEAD(&ioat->used_desc); break; } - spin_unlock_bh(&ioat_chan->desc_lock); + spin_unlock_bh(&ioat->desc_lock); pci_pool_free(ioatdma_device->completion_pool, - ioat_chan->completion_virt, - ioat_chan->completion_addr); + chan->completion_virt, + chan->completion_addr); /* one is ok since we left it on there on purpose */ if (in_use_descs > 1) - dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n", + dev_err(to_dev(chan), "Freeing %d in use descriptors!\n", in_use_descs - 1); - ioat_chan->last_completion = ioat_chan->completion_addr = 0; - ioat_chan->pending = 0; - ioat_chan->dmacount = 0; - ioat_chan->desccount = 0; - ioat_chan->watchdog_completion = 0; - ioat_chan->last_compl_desc_addr_hw = 0; - ioat_chan->watchdog_tcp_cookie = - ioat_chan->watchdog_last_tcp_cookie = 0; + chan->last_completion = chan->completion_addr = 0; + chan->watchdog_completion = 0; + chan->last_compl_desc_addr_hw = 0; + chan->watchdog_tcp_cookie = chan->watchdog_last_tcp_cookie = 0; + ioat->pending = 0; + ioat->dmacount = 0; + ioat->desccount = 0; } /** - * ioat_dma_get_next_descriptor - return the next available descriptor - * @ioat_chan: IOAT DMA channel handle + * ioat1_dma_get_next_descriptor - return the next available descriptor + * @ioat: IOAT DMA channel handle * * Gets the next descriptor from the chain, and must be called with the * channel's desc_lock held. Allocates more descriptors if the channel * has run out. */ static struct ioat_desc_sw * -ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) +ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat) { struct ioat_desc_sw *new; - if (!list_empty(&ioat_chan->free_desc)) { - new = to_ioat_desc(ioat_chan->free_desc.next); + if (!list_empty(&ioat->free_desc)) { + new = to_ioat_desc(ioat->free_desc.next); list_del(&new->node); } else { /* try to get another desc */ - new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC); + new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC); if (!new) { - dev_err(to_dev(ioat_chan), "alloc failed\n"); + dev_err(to_dev(&ioat->base), "alloc failed\n"); return NULL; } } @@ -788,7 +792,7 @@ ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) } static struct ioat_desc_sw * -ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) +ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat) { struct ioat_desc_sw *new; @@ -801,15 +805,15 @@ ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) * linking in a new set of descriptors, since the device * has probably already read the pointer to it */ - if (ioat_chan->used_desc.prev && - ioat_chan->used_desc.next == ioat_chan->used_desc.prev->prev) { + if (ioat->used_desc.prev && + ioat->used_desc.next == ioat->used_desc.prev->prev) { struct ioat_desc_sw *desc; struct ioat_desc_sw *noop_desc; int i; /* set up the noop descriptor */ - noop_desc = to_ioat_desc(ioat_chan->used_desc.next); + noop_desc = to_ioat_desc(ioat->used_desc.next); /* set size to non-zero value (channel returns error when size is 0) */ noop_desc->hw->size = NULL_DESC_BUFFER_SIZE; noop_desc->hw->ctl = 0; @@ -817,60 +821,61 @@ ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) noop_desc->hw->src_addr = 0; noop_desc->hw->dst_addr = 0; - ioat_chan->used_desc.next = ioat_chan->used_desc.next->next; - ioat_chan->pending++; - ioat_chan->dmacount++; + ioat->used_desc.next = ioat->used_desc.next->next; + ioat->pending++; + ioat->dmacount++; /* try to get a few more descriptors */ for (i = 16; i; i--) { - desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC); + desc = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC); if (!desc) { - dev_err(to_dev(ioat_chan), "alloc failed\n"); + dev_err(to_dev(&ioat->base), + "alloc failed\n"); break; } - list_add_tail(&desc->node, ioat_chan->used_desc.next); + list_add_tail(&desc->node, ioat->used_desc.next); desc->hw->next = to_ioat_desc(desc->node.next)->txd.phys; to_ioat_desc(desc->node.prev)->hw->next = desc->txd.phys; - ioat_chan->desccount++; + ioat->desccount++; } - ioat_chan->used_desc.next = noop_desc->node.next; + ioat->used_desc.next = noop_desc->node.next; } - new = to_ioat_desc(ioat_chan->used_desc.next); + new = to_ioat_desc(ioat->used_desc.next); prefetch(new); - ioat_chan->used_desc.next = new->node.next; + ioat->used_desc.next = new->node.next; - if (ioat_chan->used_desc.prev == NULL) - ioat_chan->used_desc.prev = &new->node; + if (ioat->used_desc.prev == NULL) + ioat->used_desc.prev = &new->node; prefetch(new->hw); return new; } static struct ioat_desc_sw * -ioat_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan) +ioat_dma_get_next_descriptor(struct ioat_dma_chan *ioat) { - if (!ioat_chan) + if (!ioat) return NULL; - switch (ioat_chan->device->version) { + switch (ioat->base.device->version) { case IOAT_VER_1_2: - return ioat1_dma_get_next_descriptor(ioat_chan); + return ioat1_dma_get_next_descriptor(ioat); case IOAT_VER_2_0: case IOAT_VER_3_0: - return ioat2_dma_get_next_descriptor(ioat_chan); + return ioat2_dma_get_next_descriptor(ioat); } return NULL; } static struct dma_async_tx_descriptor * -ioat1_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, +ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, dma_addr_t dma_src, size_t len, unsigned long flags) { - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + struct ioat_dma_chan *ioat = to_ioat_chan(c); struct ioat_desc_sw *desc; size_t copy; LIST_HEAD(chain); @@ -880,14 +885,14 @@ ioat1_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, struct ioat_dma_descriptor *hw = NULL; int tx_cnt = 0; - spin_lock_bh(&ioat_chan->desc_lock); - desc = ioat_dma_get_next_descriptor(ioat_chan); + spin_lock_bh(&ioat->desc_lock); + desc = ioat_dma_get_next_descriptor(ioat); do { if (!desc) break; tx_cnt++; - copy = min_t(size_t, len, ioat_chan->xfercap); + copy = min_t(size_t, len, ioat->xfercap); hw = desc->hw; hw->size = copy; @@ -904,7 +909,7 @@ ioat1_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, struct ioat_desc_sw *next; async_tx_ack(&desc->txd); - next = ioat_dma_get_next_descriptor(ioat_chan); + next = ioat_dma_get_next_descriptor(ioat); hw->next = next ? next->txd.phys : 0; desc = next; } else @@ -912,14 +917,16 @@ ioat1_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, } while (len); if (!desc) { - dev_err(to_dev(ioat_chan), + struct ioat_chan_common *chan = &ioat->base; + + dev_err(to_dev(chan), "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n", - chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); - list_splice(&chain, &ioat_chan->free_desc); - spin_unlock_bh(&ioat_chan->desc_lock); + chan_num(chan), ioat->dmacount, ioat->desccount); + list_splice(&chain, &ioat->free_desc); + spin_unlock_bh(&ioat->desc_lock); return NULL; } - spin_unlock_bh(&ioat_chan->desc_lock); + spin_unlock_bh(&ioat->desc_lock); desc->txd.flags = flags; desc->tx_cnt = tx_cnt; @@ -934,17 +941,17 @@ ioat1_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, } static struct dma_async_tx_descriptor * -ioat2_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, +ioat2_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, dma_addr_t dma_src, size_t len, unsigned long flags) { - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + struct ioat_dma_chan *ioat = to_ioat_chan(c); struct ioat_desc_sw *new; - spin_lock_bh(&ioat_chan->desc_lock); - new = ioat2_dma_get_next_descriptor(ioat_chan); + spin_lock_bh(&ioat->desc_lock); + new = ioat2_dma_get_next_descriptor(ioat); /* - * leave ioat_chan->desc_lock set in ioat 2 path + * leave ioat->desc_lock set in ioat 2 path * it will get unlocked at end of tx_submit */ @@ -955,10 +962,12 @@ ioat2_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, new->txd.flags = flags; return &new->txd; } else { - spin_unlock_bh(&ioat_chan->desc_lock); - dev_err(to_dev(ioat_chan), + struct ioat_chan_common *chan = &ioat->base; + + spin_unlock_bh(&ioat->desc_lock); + dev_err(to_dev(chan), "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n", - chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount); + chan_num(chan), ioat->dmacount, ioat->desccount); return NULL; } } @@ -968,20 +977,20 @@ static void ioat_dma_cleanup_tasklet(unsigned long data) struct ioat_dma_chan *chan = (void *)data; ioat_dma_memcpy_cleanup(chan); writew(IOAT_CHANCTRL_INT_DISABLE, - chan->reg_base + IOAT_CHANCTRL_OFFSET); + chan->base.reg_base + IOAT_CHANCTRL_OFFSET); } static void -ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc) +ioat_dma_unmap(struct ioat_chan_common *chan, struct ioat_desc_sw *desc) { if (!(desc->txd.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { if (desc->txd.flags & DMA_COMPL_DEST_UNMAP_SINGLE) - pci_unmap_single(ioat_chan->device->pdev, + pci_unmap_single(chan->device->pdev, pci_unmap_addr(desc, dst), pci_unmap_len(desc, len), PCI_DMA_FROMDEVICE); else - pci_unmap_page(ioat_chan->device->pdev, + pci_unmap_page(chan->device->pdev, pci_unmap_addr(desc, dst), pci_unmap_len(desc, len), PCI_DMA_FROMDEVICE); @@ -989,12 +998,12 @@ ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc) if (!(desc->txd.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { if (desc->txd.flags & DMA_COMPL_SRC_UNMAP_SINGLE) - pci_unmap_single(ioat_chan->device->pdev, + pci_unmap_single(chan->device->pdev, pci_unmap_addr(desc, src), pci_unmap_len(desc, len), PCI_DMA_TODEVICE); else - pci_unmap_page(ioat_chan->device->pdev, + pci_unmap_page(chan->device->pdev, pci_unmap_addr(desc, src), pci_unmap_len(desc, len), PCI_DMA_TODEVICE); @@ -1005,8 +1014,9 @@ ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc) * ioat_dma_memcpy_cleanup - cleanup up finished descriptors * @chan: ioat channel to be cleaned up */ -static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) +static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat) { + struct ioat_chan_common *chan = &ioat->base; unsigned long phys_complete; struct ioat_desc_sw *desc, *_desc; dma_cookie_t cookie = 0; @@ -1014,9 +1024,9 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) struct ioat_desc_sw *latest_desc; struct dma_async_tx_descriptor *tx; - prefetch(ioat_chan->completion_virt); + prefetch(chan->completion_virt); - if (!spin_trylock_bh(&ioat_chan->cleanup_lock)) + if (!spin_trylock_bh(&chan->cleanup_lock)) return; /* The completion writeback can happen at any time, @@ -1026,49 +1036,47 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) #if (BITS_PER_LONG == 64) phys_complete = - ioat_chan->completion_virt->full + chan->completion_virt->full & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; #else - phys_complete = - ioat_chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK; + phys_complete = chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK; #endif - if ((ioat_chan->completion_virt->full + if ((chan->completion_virt->full & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) { - dev_err(to_dev(ioat_chan), "Channel halted, chanerr = %x\n", - readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET)); + dev_err(to_dev(chan), "Channel halted, chanerr = %x\n", + readl(chan->reg_base + IOAT_CHANERR_OFFSET)); /* TODO do something to salvage the situation */ } - if (phys_complete == ioat_chan->last_completion) { - spin_unlock_bh(&ioat_chan->cleanup_lock); + if (phys_complete == chan->last_completion) { + spin_unlock_bh(&chan->cleanup_lock); /* * perhaps we're stuck so hard that the watchdog can't go off? * try to catch it after 2 seconds */ - if (ioat_chan->device->version != IOAT_VER_3_0) { + if (chan->device->version != IOAT_VER_3_0) { if (time_after(jiffies, - ioat_chan->last_completion_time + HZ*WATCHDOG_DELAY)) { - ioat_dma_chan_watchdog(&(ioat_chan->device->work.work)); - ioat_chan->last_completion_time = jiffies; + chan->last_completion_time + HZ*WATCHDOG_DELAY)) { + ioat_dma_chan_watchdog(&(chan->device->work.work)); + chan->last_completion_time = jiffies; } } return; } - ioat_chan->last_completion_time = jiffies; + chan->last_completion_time = jiffies; cookie = 0; - if (!spin_trylock_bh(&ioat_chan->desc_lock)) { - spin_unlock_bh(&ioat_chan->cleanup_lock); + if (!spin_trylock_bh(&ioat->desc_lock)) { + spin_unlock_bh(&chan->cleanup_lock); return; } - switch (ioat_chan->device->version) { + switch (chan->device->version) { case IOAT_VER_1_2: - list_for_each_entry_safe(desc, _desc, - &ioat_chan->used_desc, node) { + list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { tx = &desc->txd; /* * Incoming DMA requests may use multiple descriptors, @@ -1077,7 +1085,7 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) */ if (tx->cookie) { cookie = tx->cookie; - ioat_dma_unmap(ioat_chan, desc); + ioat_dma_unmap(chan, desc); if (tx->callback) { tx->callback(tx->callback_param); tx->callback = NULL; @@ -1091,7 +1099,7 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) */ if (async_tx_test_ack(tx)) { list_move_tail(&desc->node, - &ioat_chan->free_desc); + &ioat->free_desc); } else tx->cookie = 0; } else { @@ -1110,11 +1118,11 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) case IOAT_VER_2_0: case IOAT_VER_3_0: /* has some other thread has already cleaned up? */ - if (ioat_chan->used_desc.prev == NULL) + if (ioat->used_desc.prev == NULL) break; /* work backwards to find latest finished desc */ - desc = to_ioat_desc(ioat_chan->used_desc.next); + desc = to_ioat_desc(ioat->used_desc.next); tx = &desc->txd; latest_desc = NULL; do { @@ -1125,18 +1133,18 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) latest_desc = desc; break; } - } while (&desc->node != ioat_chan->used_desc.prev); + } while (&desc->node != ioat->used_desc.prev); if (latest_desc != NULL) { /* work forwards to clear finished descriptors */ - for (desc = to_ioat_desc(ioat_chan->used_desc.prev); + for (desc = to_ioat_desc(ioat->used_desc.prev); &desc->node != latest_desc->node.next && - &desc->node != ioat_chan->used_desc.next; + &desc->node != ioat->used_desc.next; desc = to_ioat_desc(desc->node.next)) { if (tx->cookie) { cookie = tx->cookie; tx->cookie = 0; - ioat_dma_unmap(ioat_chan, desc); + ioat_dma_unmap(chan, desc); if (tx->callback) { tx->callback(tx->callback_param); tx->callback = NULL; @@ -1145,21 +1153,21 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) } /* move used.prev up beyond those that are finished */ - if (&desc->node == ioat_chan->used_desc.next) - ioat_chan->used_desc.prev = NULL; + if (&desc->node == ioat->used_desc.next) + ioat->used_desc.prev = NULL; else - ioat_chan->used_desc.prev = &desc->node; + ioat->used_desc.prev = &desc->node; } break; } - spin_unlock_bh(&ioat_chan->desc_lock); + spin_unlock_bh(&ioat->desc_lock); - ioat_chan->last_completion = phys_complete; + chan->last_completion = phys_complete; if (cookie != 0) - ioat_chan->completed_cookie = cookie; + chan->completed_cookie = cookie; - spin_unlock_bh(&ioat_chan->cleanup_lock); + spin_unlock_bh(&chan->cleanup_lock); } /** @@ -1170,17 +1178,18 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) * @used: if not %NULL, updated with last used transaction */ static enum dma_status -ioat_dma_is_complete(struct dma_chan *chan, dma_cookie_t cookie, +ioat_dma_is_complete(struct dma_chan *c, dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used) { - struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan); + struct ioat_dma_chan *ioat = to_ioat_chan(c); + struct ioat_chan_common *chan = &ioat->base; dma_cookie_t last_used; dma_cookie_t last_complete; enum dma_status ret; - last_used = chan->cookie; - last_complete = ioat_chan->completed_cookie; - ioat_chan->watchdog_tcp_cookie = cookie; + last_used = c->cookie; + last_complete = chan->completed_cookie; + chan->watchdog_tcp_cookie = cookie; if (done) *done = last_complete; @@ -1191,10 +1200,10 @@ ioat_dma_is_complete(struct dma_chan *chan, dma_cookie_t cookie, if (ret == DMA_SUCCESS) return ret; - ioat_dma_memcpy_cleanup(ioat_chan); + ioat_dma_memcpy_cleanup(ioat); - last_used = chan->cookie; - last_complete = ioat_chan->completed_cookie; + last_used = c->cookie; + last_complete = chan->completed_cookie; if (done) *done = last_complete; @@ -1204,19 +1213,20 @@ ioat_dma_is_complete(struct dma_chan *chan, dma_cookie_t cookie, return dma_async_is_complete(cookie, last_complete, last_used); } -static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan) +static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat) { + struct ioat_chan_common *chan = &ioat->base; struct ioat_desc_sw *desc; struct ioat_dma_descriptor *hw; - spin_lock_bh(&ioat_chan->desc_lock); + spin_lock_bh(&ioat->desc_lock); - desc = ioat_dma_get_next_descriptor(ioat_chan); + desc = ioat_dma_get_next_descriptor(ioat); if (!desc) { - dev_err(to_dev(ioat_chan), + dev_err(to_dev(chan), "Unable to start null desc - get next desc failed\n"); - spin_unlock_bh(&ioat_chan->desc_lock); + spin_unlock_bh(&ioat->desc_lock); return; } @@ -1230,31 +1240,31 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan) hw->src_addr = 0; hw->dst_addr = 0; async_tx_ack(&desc->txd); - switch (ioat_chan->device->version) { + switch (chan->device->version) { case IOAT_VER_1_2: hw->next = 0; - list_add_tail(&desc->node, &ioat_chan->used_desc); + list_add_tail(&desc->node, &ioat->used_desc); writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, - ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); + chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); writel(((u64) desc->txd.phys) >> 32, - ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); + chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); - writeb(IOAT_CHANCMD_START, ioat_chan->reg_base - + IOAT_CHANCMD_OFFSET(ioat_chan->device->version)); + writeb(IOAT_CHANCMD_START, chan->reg_base + + IOAT_CHANCMD_OFFSET(chan->device->version)); break; case IOAT_VER_2_0: case IOAT_VER_3_0: writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, - ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); + chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); writel(((u64) desc->txd.phys) >> 32, - ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); + chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); - ioat_chan->dmacount++; - __ioat2_dma_memcpy_issue_pending(ioat_chan); + ioat->dmacount++; + __ioat2_dma_memcpy_issue_pending(ioat); break; } - spin_unlock_bh(&ioat_chan->desc_lock); + spin_unlock_bh(&ioat->desc_lock); } /* @@ -1371,7 +1381,7 @@ MODULE_PARM_DESC(ioat_interrupt_style, */ static int ioat_dma_setup_interrupts(struct ioatdma_device *device) { - struct ioat_dma_chan *ioat_chan; + struct ioat_chan_common *chan; struct pci_dev *pdev = device->pdev; struct device *dev = &pdev->dev; struct msix_entry *msix; @@ -1404,15 +1414,15 @@ msix: for (i = 0; i < msixcnt; i++) { msix = &device->msix_entries[i]; - ioat_chan = ioat_chan_by_index(device, i); + chan = ioat_chan_by_index(device, i); err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt_msix, 0, - "ioat-msix", ioat_chan); + "ioat-msix", chan); if (err) { for (j = 0; j < i; j++) { msix = &device->msix_entries[j]; - ioat_chan = ioat_chan_by_index(device, j); - devm_free_irq(dev, msix->vector, ioat_chan); + chan = ioat_chan_by_index(device, j); + devm_free_irq(dev, msix->vector, chan); } goto msix_single_vector; } @@ -1594,8 +1604,8 @@ int ioat2_dma_probe(struct ioatdma_device *device, int dca) { struct pci_dev *pdev = device->pdev; struct dma_device *dma; - struct dma_chan *chan; - struct ioat_dma_chan *ioat_chan; + struct dma_chan *c; + struct ioat_chan_common *chan; int err; dma = &device->common; @@ -1607,10 +1617,10 @@ int ioat2_dma_probe(struct ioatdma_device *device, int dca) return err; ioat_set_tcp_copy_break(2048); - list_for_each_entry(chan, &dma->channels, device_node) { - ioat_chan = to_ioat_chan(chan); + list_for_each_entry(c, &dma->channels, device_node) { + chan = to_chan_common(c); writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU, - ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); + chan->reg_base + IOAT_DCACTRL_OFFSET); } err = ioat_register(device); @@ -1629,8 +1639,8 @@ int ioat3_dma_probe(struct ioatdma_device *device, int dca) { struct pci_dev *pdev = device->pdev; struct dma_device *dma; - struct dma_chan *chan; - struct ioat_dma_chan *ioat_chan; + struct dma_chan *c; + struct ioat_chan_common *chan; int err; u16 dev_id; @@ -1656,10 +1666,10 @@ int ioat3_dma_probe(struct ioatdma_device *device, int dca) return err; ioat_set_tcp_copy_break(262144); - list_for_each_entry(chan, &dma->channels, device_node) { - ioat_chan = to_ioat_chan(chan); + list_for_each_entry(c, &dma->channels, device_node) { + chan = to_chan_common(c); writel(IOAT_DMA_DCA_ANY_CPU, - ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); + chan->reg_base + IOAT_DCACTRL_OFFSET); } err = ioat_register(device); @@ -1673,8 +1683,6 @@ int ioat3_dma_probe(struct ioatdma_device *device, int dca) void ioat_dma_remove(struct ioatdma_device *device) { - struct dma_chan *chan, *_chan; - struct ioat_dma_chan *ioat_chan; struct dma_device *dma = &device->common; if (device->version != IOAT_VER_3_0) @@ -1687,9 +1695,6 @@ void ioat_dma_remove(struct ioatdma_device *device) pci_pool_destroy(device->dma_pool); pci_pool_destroy(device->completion_pool); - list_for_each_entry_safe(chan, _chan, &dma->channels, device_node) { - ioat_chan = to_ioat_chan(chan); - list_del(&chan->device_node); - } + INIT_LIST_HEAD(&dma->channels); } diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index 9f0c853..5b31db7 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -35,7 +35,6 @@ #define IOAT_DMA_DCA_ANY_CPU ~0 #define IOAT_WATCHDOG_PERIOD (2 * HZ) -#define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common) #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd) @@ -74,37 +73,24 @@ struct ioatdma_device { u8 version; struct delayed_work work; struct msix_entry msix_entries[4]; - struct ioat_dma_chan *idx[4]; + struct ioat_chan_common *idx[4]; struct dca_provider *dca; void (*intr_quirk)(struct ioatdma_device *device); }; -/** - * struct ioat_dma_chan - internal representation of a DMA channel - */ -struct ioat_dma_chan { - +struct ioat_chan_common { void __iomem *reg_base; - dma_cookie_t completed_cookie; unsigned long last_completion; unsigned long last_completion_time; - size_t xfercap; /* XFERCAP register value expanded out */ - spinlock_t cleanup_lock; - spinlock_t desc_lock; - struct list_head free_desc; - struct list_head used_desc; + dma_cookie_t completed_cookie; unsigned long watchdog_completion; int watchdog_tcp_cookie; u32 watchdog_last_tcp_cookie; struct delayed_work work; - int pending; - u16 dmacount; - u16 desccount; - struct ioatdma_device *device; struct dma_chan common; @@ -120,6 +106,35 @@ struct ioat_dma_chan { struct tasklet_struct cleanup_task; }; +/** + * struct ioat_dma_chan - internal representation of a DMA channel + */ +struct ioat_dma_chan { + struct ioat_chan_common base; + + size_t xfercap; /* XFERCAP register value expanded out */ + + spinlock_t desc_lock; + struct list_head free_desc; + struct list_head used_desc; + + int pending; + u16 dmacount; + u16 desccount; +}; + +static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c) +{ + return container_of(c, struct ioat_chan_common, common); +} + +static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c) +{ + struct ioat_chan_common *chan = to_chan_common(c); + + return container_of(chan, struct ioat_dma_chan, base); +} + /* wrapper around hardware descriptor format + additional software fields */ /** -- cgit v0.10.2 From 5cbafa65b92ee4f5b8ba915cddf94b91f186b989 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 26 Aug 2009 13:01:44 -0700 Subject: ioat2,3: convert to a true ring buffer Replace the current linked list munged into a ring with a native ring buffer implementation. The benefit of this approach is reduced overhead as many parameters can be derived from ring position with simple pointer comparisons and descriptor allocation/freeing becomes just a manipulation of head/tail pointers. It requires a contiguous allocation for the software descriptor information. Since this arrangement is significantly different from the ioat1 chain, move ioat2,3 support into its own file and header. Common routines are exported from driver/dma/ioat/dma.[ch]. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/Makefile b/drivers/dma/ioat/Makefile index 2ce3d3a..205a639 100644 --- a/drivers/dma/ioat/Makefile +++ b/drivers/dma/ioat/Makefile @@ -1,2 +1,2 @@ obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o -ioatdma-objs := pci.o dma.o dca.o +ioatdma-objs := pci.o dma.o dma_v2.o dca.o diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 2e81e0c..64b4d75 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -38,28 +38,14 @@ #include "registers.h" #include "hw.h" -static int ioat_pending_level = 4; +int ioat_pending_level = 4; module_param(ioat_pending_level, int, 0644); MODULE_PARM_DESC(ioat_pending_level, "high-water mark for pushing ioat descriptors (default: 4)"); -static void ioat_dma_chan_reset_part2(struct work_struct *work); -static void ioat_dma_chan_watchdog(struct work_struct *work); - /* internal functions */ -static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat); -static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat); - -static struct ioat_desc_sw * -ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat); -static struct ioat_desc_sw * -ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat); - -static inline struct ioat_chan_common * -ioat_chan_by_index(struct ioatdma_device *device, int index) -{ - return device->idx[index]; -} +static void ioat1_cleanup(struct ioat_dma_chan *ioat); +static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat); /** * ioat_dma_do_interrupt - handler used for single vector interrupt mode @@ -108,18 +94,38 @@ static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) return IRQ_HANDLED; } -static void ioat_dma_cleanup_tasklet(unsigned long data); +static void ioat1_cleanup_tasklet(unsigned long data); + +/* common channel initialization */ +void ioat_init_channel(struct ioatdma_device *device, + struct ioat_chan_common *chan, int idx, + work_func_t work_fn, void (*tasklet)(unsigned long), + unsigned long tasklet_data) +{ + struct dma_device *dma = &device->common; + + chan->device = device; + chan->reg_base = device->reg_base + (0x80 * (idx + 1)); + INIT_DELAYED_WORK(&chan->work, work_fn); + spin_lock_init(&chan->cleanup_lock); + chan->common.device = dma; + list_add_tail(&chan->common.device_node, &dma->channels); + device->idx[idx] = chan; + tasklet_init(&chan->cleanup_task, tasklet, tasklet_data); + tasklet_disable(&chan->cleanup_task); +} + +static void ioat1_reset_part2(struct work_struct *work); /** - * ioat_dma_enumerate_channels - find and initialize the device's channels + * ioat1_dma_enumerate_channels - find and initialize the device's channels * @device: the device to be enumerated */ -static int ioat_dma_enumerate_channels(struct ioatdma_device *device) +static int ioat1_enumerate_channels(struct ioatdma_device *device) { u8 xfercap_scale; u32 xfercap; int i; - struct ioat_chan_common *chan; struct ioat_dma_chan *ioat; struct device *dev = &device->pdev->dev; struct dma_device *dma = &device->common; @@ -135,31 +141,20 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device) #endif for (i = 0; i < dma->chancnt; i++) { ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL); - if (!ioat) { - dma->chancnt = i; + if (!ioat) break; - } - chan = &ioat->base; - chan->device = device; - chan->reg_base = device->reg_base + (0x80 * (i + 1)); + ioat_init_channel(device, &ioat->base, i, + ioat1_reset_part2, + ioat1_cleanup_tasklet, + (unsigned long) ioat); ioat->xfercap = xfercap; - ioat->desccount = 0; - INIT_DELAYED_WORK(&chan->work, ioat_dma_chan_reset_part2); - spin_lock_init(&chan->cleanup_lock); spin_lock_init(&ioat->desc_lock); INIT_LIST_HEAD(&ioat->free_desc); INIT_LIST_HEAD(&ioat->used_desc); - /* This should be made common somewhere in dmaengine.c */ - chan->common.device = &device->common; - list_add_tail(&chan->common.device_node, &dma->channels); - device->idx[i] = chan; - tasklet_init(&chan->cleanup_task, - ioat_dma_cleanup_tasklet, - (unsigned long) ioat); - tasklet_disable(&chan->cleanup_task); } - return dma->chancnt; + dma->chancnt = i; + return i; } /** @@ -187,35 +182,16 @@ static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan) } } -static inline void -__ioat2_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat) -{ - void __iomem *reg_base = ioat->base.reg_base; - - ioat->pending = 0; - writew(ioat->dmacount, reg_base + IOAT_CHAN_DMACOUNT_OFFSET); -} - -static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan) -{ - struct ioat_dma_chan *ioat = to_ioat_chan(chan); - - if (ioat->pending > 0) { - spin_lock_bh(&ioat->desc_lock); - __ioat2_dma_memcpy_issue_pending(ioat); - spin_unlock_bh(&ioat->desc_lock); - } -} - - /** - * ioat_dma_chan_reset_part2 - reinit the channel after a reset + * ioat1_reset_part2 - reinit the channel after a reset */ -static void ioat_dma_chan_reset_part2(struct work_struct *work) +static void ioat1_reset_part2(struct work_struct *work) { struct ioat_chan_common *chan; struct ioat_dma_chan *ioat; struct ioat_desc_sw *desc; + int dmacount; + bool start_null = false; chan = container_of(work, struct ioat_chan_common, work.work); ioat = container_of(chan, struct ioat_dma_chan, base); @@ -226,26 +202,22 @@ static void ioat_dma_chan_reset_part2(struct work_struct *work) chan->completion_virt->high = 0; ioat->pending = 0; - /* - * count the descriptors waiting, and be sure to do it - * right for both the CB1 line and the CB2 ring - */ - ioat->dmacount = 0; + /* count the descriptors waiting */ + dmacount = 0; if (ioat->used_desc.prev) { desc = to_ioat_desc(ioat->used_desc.prev); do { - ioat->dmacount++; + dmacount++; desc = to_ioat_desc(desc->node.next); } while (&desc->node != ioat->used_desc.next); } - /* - * write the new starting descriptor address - * this puts channel engine into ARMED state - */ - desc = to_ioat_desc(ioat->used_desc.prev); - switch (chan->device->version) { - case IOAT_VER_1_2: + if (dmacount) { + /* + * write the new starting descriptor address + * this puts channel engine into ARMED state + */ + desc = to_ioat_desc(ioat->used_desc.prev); writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); writel(((u64) desc->txd.phys) >> 32, @@ -253,32 +225,24 @@ static void ioat_dma_chan_reset_part2(struct work_struct *work) writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); - break; - case IOAT_VER_2_0: - writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, - chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->txd.phys) >> 32, - chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); - - /* tell the engine to go with what's left to be done */ - writew(ioat->dmacount, - chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); + } else + start_null = true; + spin_unlock_bh(&ioat->desc_lock); + spin_unlock_bh(&chan->cleanup_lock); - break; - } dev_err(to_dev(chan), "chan%d reset - %d descs waiting, %d total desc\n", - chan_num(chan), ioat->dmacount, ioat->desccount); + chan_num(chan), dmacount, ioat->desccount); - spin_unlock_bh(&ioat->desc_lock); - spin_unlock_bh(&chan->cleanup_lock); + if (start_null) + ioat1_dma_start_null_desc(ioat); } /** - * ioat_dma_reset_channel - restart a channel + * ioat1_reset_channel - restart a channel * @ioat: IOAT DMA channel handle */ -static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat) +static void ioat1_reset_channel(struct ioat_dma_chan *ioat) { struct ioat_chan_common *chan = &ioat->base; void __iomem *reg_base = chan->reg_base; @@ -316,9 +280,9 @@ static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat) } /** - * ioat_dma_chan_watchdog - watch for stuck channels + * ioat1_chan_watchdog - watch for stuck channels */ -static void ioat_dma_chan_watchdog(struct work_struct *work) +static void ioat1_chan_watchdog(struct work_struct *work) { struct ioatdma_device *device = container_of(work, struct ioatdma_device, work.work); @@ -339,16 +303,15 @@ static void ioat_dma_chan_watchdog(struct work_struct *work) chan = ioat_chan_by_index(device, i); ioat = container_of(chan, struct ioat_dma_chan, base); - if (chan->device->version == IOAT_VER_1_2 - /* have we started processing anything yet */ - && chan->last_completion - /* have we completed any since last watchdog cycle? */ + if (/* have we started processing anything yet */ + chan->last_completion + /* have we completed any since last watchdog cycle? */ && (chan->last_completion == chan->watchdog_completion) - /* has TCP stuck on one cookie since last watchdog? */ + /* has TCP stuck on one cookie since last watchdog? */ && (chan->watchdog_tcp_cookie == chan->watchdog_last_tcp_cookie) && (chan->watchdog_tcp_cookie != chan->completed_cookie) - /* is there something in the chain to be processed? */ - /* CB1 chain always has at least the last one processed */ + /* is there something in the chain to be processed? */ + /* CB1 chain always has at least the last one processed */ && (ioat->used_desc.prev != ioat->used_desc.next) && ioat->pending == 0) { @@ -387,34 +350,15 @@ static void ioat_dma_chan_watchdog(struct work_struct *work) chan->completion_virt->low = completion_hw.low; chan->completion_virt->high = completion_hw.high; } else { - ioat_dma_reset_channel(ioat); + ioat1_reset_channel(ioat); chan->watchdog_completion = 0; chan->last_compl_desc_addr_hw = 0; } - - /* - * for version 2.0 if there are descriptors yet to be processed - * and the last completed hasn't changed since the last watchdog - * if they haven't hit the pending level - * issue the pending to push them through - * else - * try resetting the channel - */ - } else if (chan->device->version == IOAT_VER_2_0 - && ioat->used_desc.prev - && chan->last_completion - && chan->last_completion == chan->watchdog_completion) { - - if (ioat->pending < ioat_pending_level) - ioat2_dma_memcpy_issue_pending(&chan->common); - else { - ioat_dma_reset_channel(ioat); - chan->watchdog_completion = 0; - } } else { chan->last_compl_desc_addr_hw = 0; chan->watchdog_completion = chan->last_completion; } + chan->watchdog_last_tcp_cookie = chan->watchdog_tcp_cookie; } @@ -447,7 +391,6 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) chain_tail->hw->next = first->txd.phys; list_splice_tail_init(&tx->tx_list, &ioat->used_desc); - ioat->dmacount += desc->tx_cnt; ioat->pending += desc->tx_cnt; if (ioat->pending >= ioat_pending_level) __ioat1_dma_memcpy_issue_pending(ioat); @@ -456,92 +399,6 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) return cookie; } -static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx) -{ - struct ioat_dma_chan *ioat = to_ioat_chan(tx->chan); - struct ioat_desc_sw *first = tx_to_ioat_desc(tx); - struct ioat_desc_sw *new; - struct ioat_dma_descriptor *hw; - dma_cookie_t cookie; - u32 copy; - size_t len; - dma_addr_t src, dst; - unsigned long orig_flags; - unsigned int desc_count = 0; - - /* src and dest and len are stored in the initial descriptor */ - len = first->len; - src = first->src; - dst = first->dst; - orig_flags = first->txd.flags; - new = first; - - /* - * ioat->desc_lock is still in force in version 2 path - * it gets unlocked at end of this function - */ - do { - copy = min_t(size_t, len, ioat->xfercap); - - async_tx_ack(&new->txd); - - hw = new->hw; - hw->size = copy; - hw->ctl = 0; - hw->src_addr = src; - hw->dst_addr = dst; - - len -= copy; - dst += copy; - src += copy; - desc_count++; - } while (len && (new = ioat2_dma_get_next_descriptor(ioat))); - - if (!new) { - dev_err(to_dev(&ioat->base), "tx submit failed\n"); - spin_unlock_bh(&ioat->desc_lock); - return -ENOMEM; - } - - hw->ctl_f.compl_write = 1; - if (first->txd.callback) { - hw->ctl_f.int_en = 1; - if (first != new) { - /* move callback into to last desc */ - new->txd.callback = first->txd.callback; - new->txd.callback_param - = first->txd.callback_param; - first->txd.callback = NULL; - first->txd.callback_param = NULL; - } - } - - new->tx_cnt = desc_count; - new->txd.flags = orig_flags; /* client is in control of this ack */ - - /* store the original values for use in later cleanup */ - if (new != first) { - new->src = first->src; - new->dst = first->dst; - new->len = first->len; - } - - /* cookie incr and addition to used_list must be atomic */ - cookie = ioat->base.common.cookie; - cookie++; - if (cookie < 0) - cookie = 1; - ioat->base.common.cookie = new->txd.cookie = cookie; - - ioat->dmacount += desc_count; - ioat->pending += desc_count; - if (ioat->pending >= ioat_pending_level) - __ioat2_dma_memcpy_issue_pending(ioat); - spin_unlock_bh(&ioat->desc_lock); - - return cookie; -} - /** * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair * @ioat: the channel supplying the memory pool for the descriptors @@ -567,17 +424,9 @@ ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags) } memset(desc, 0, sizeof(*desc)); - dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common); - switch (ioatdma_device->version) { - case IOAT_VER_1_2: - desc_sw->txd.tx_submit = ioat1_tx_submit; - break; - case IOAT_VER_2_0: - case IOAT_VER_3_0: - desc_sw->txd.tx_submit = ioat2_tx_submit; - break; - } + dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common); + desc_sw->txd.tx_submit = ioat1_tx_submit; desc_sw->hw = desc; desc_sw->txd.phys = phys; @@ -587,39 +436,12 @@ ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags) static int ioat_initial_desc_count = 256; module_param(ioat_initial_desc_count, int, 0644); MODULE_PARM_DESC(ioat_initial_desc_count, - "initial descriptors per channel (default: 256)"); - -/** - * ioat2_dma_massage_chan_desc - link the descriptors into a circle - * @ioat: the channel to be massaged - */ -static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat) -{ - struct ioat_desc_sw *desc, *_desc; - - /* setup used_desc */ - ioat->used_desc.next = ioat->free_desc.next; - ioat->used_desc.prev = NULL; - - /* pull free_desc out of the circle so that every node is a hw - * descriptor, but leave it pointing to the list - */ - ioat->free_desc.prev->next = ioat->free_desc.next; - ioat->free_desc.next->prev = ioat->free_desc.prev; - - /* circle link the hw descriptors */ - desc = to_ioat_desc(ioat->free_desc.next); - desc->hw->next = to_ioat_desc(desc->node.next)->txd.phys; - list_for_each_entry_safe(desc, _desc, ioat->free_desc.next, node) { - desc->hw->next = to_ioat_desc(desc->node.next)->txd.phys; - } -} - + "ioat1: initial descriptors per channel (default: 256)"); /** - * ioat_dma_alloc_chan_resources - returns the number of allocated descriptors + * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors * @chan: the channel to be filled out */ -static int ioat_dma_alloc_chan_resources(struct dma_chan *c) +static int ioat1_dma_alloc_chan_resources(struct dma_chan *c) { struct ioat_dma_chan *ioat = to_ioat_chan(c); struct ioat_chan_common *chan = &ioat->base; @@ -657,8 +479,6 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *c) spin_lock_bh(&ioat->desc_lock); ioat->desccount = i; list_splice(&tmp_list, &ioat->free_desc); - if (chan->device->version != IOAT_VER_1_2) - ioat2_dma_massage_chan_desc(ioat); spin_unlock_bh(&ioat->desc_lock); /* allocate a completion writeback area */ @@ -674,15 +494,15 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *c) chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); tasklet_enable(&chan->cleanup_task); - ioat_dma_start_null_desc(ioat); /* give chain to dma device */ + ioat1_dma_start_null_desc(ioat); /* give chain to dma device */ return ioat->desccount; } /** - * ioat_dma_free_chan_resources - release all the descriptors + * ioat1_dma_free_chan_resources - release all the descriptors * @chan: the channel to be cleaned */ -static void ioat_dma_free_chan_resources(struct dma_chan *c) +static void ioat1_dma_free_chan_resources(struct dma_chan *c) { struct ioat_dma_chan *ioat = to_ioat_chan(c); struct ioat_chan_common *chan = &ioat->base; @@ -697,7 +517,7 @@ static void ioat_dma_free_chan_resources(struct dma_chan *c) return; tasklet_disable(&chan->cleanup_task); - ioat_dma_memcpy_cleanup(ioat); + ioat1_cleanup(ioat); /* Delay 100ms after reset to allow internal DMA logic to quiesce * before removing DMA descriptor resources. @@ -707,40 +527,20 @@ static void ioat_dma_free_chan_resources(struct dma_chan *c) mdelay(100); spin_lock_bh(&ioat->desc_lock); - switch (chan->device->version) { - case IOAT_VER_1_2: - list_for_each_entry_safe(desc, _desc, - &ioat->used_desc, node) { - in_use_descs++; - list_del(&desc->node); - pci_pool_free(ioatdma_device->dma_pool, desc->hw, - desc->txd.phys); - kfree(desc); - } - list_for_each_entry_safe(desc, _desc, - &ioat->free_desc, node) { - list_del(&desc->node); - pci_pool_free(ioatdma_device->dma_pool, desc->hw, - desc->txd.phys); - kfree(desc); - } - break; - case IOAT_VER_2_0: - case IOAT_VER_3_0: - list_for_each_entry_safe(desc, _desc, - ioat->free_desc.next, node) { - list_del(&desc->node); - pci_pool_free(ioatdma_device->dma_pool, desc->hw, - desc->txd.phys); - kfree(desc); - } - desc = to_ioat_desc(ioat->free_desc.next); + list_for_each_entry_safe(desc, _desc, + &ioat->used_desc, node) { + in_use_descs++; + list_del(&desc->node); + pci_pool_free(ioatdma_device->dma_pool, desc->hw, + desc->txd.phys); + kfree(desc); + } + list_for_each_entry_safe(desc, _desc, + &ioat->free_desc, node) { + list_del(&desc->node); pci_pool_free(ioatdma_device->dma_pool, desc->hw, desc->txd.phys); kfree(desc); - INIT_LIST_HEAD(&ioat->free_desc); - INIT_LIST_HEAD(&ioat->used_desc); - break; } spin_unlock_bh(&ioat->desc_lock); @@ -758,7 +558,6 @@ static void ioat_dma_free_chan_resources(struct dma_chan *c) chan->last_compl_desc_addr_hw = 0; chan->watchdog_tcp_cookie = chan->watchdog_last_tcp_cookie = 0; ioat->pending = 0; - ioat->dmacount = 0; ioat->desccount = 0; } @@ -791,86 +590,6 @@ ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat) return new; } -static struct ioat_desc_sw * -ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat) -{ - struct ioat_desc_sw *new; - - /* - * used.prev points to where to start processing - * used.next points to next free descriptor - * if used.prev == NULL, there are none waiting to be processed - * if used.next == used.prev.prev, there is only one free descriptor, - * and we need to use it to as a noop descriptor before - * linking in a new set of descriptors, since the device - * has probably already read the pointer to it - */ - if (ioat->used_desc.prev && - ioat->used_desc.next == ioat->used_desc.prev->prev) { - - struct ioat_desc_sw *desc; - struct ioat_desc_sw *noop_desc; - int i; - - /* set up the noop descriptor */ - noop_desc = to_ioat_desc(ioat->used_desc.next); - /* set size to non-zero value (channel returns error when size is 0) */ - noop_desc->hw->size = NULL_DESC_BUFFER_SIZE; - noop_desc->hw->ctl = 0; - noop_desc->hw->ctl_f.null = 1; - noop_desc->hw->src_addr = 0; - noop_desc->hw->dst_addr = 0; - - ioat->used_desc.next = ioat->used_desc.next->next; - ioat->pending++; - ioat->dmacount++; - - /* try to get a few more descriptors */ - for (i = 16; i; i--) { - desc = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC); - if (!desc) { - dev_err(to_dev(&ioat->base), - "alloc failed\n"); - break; - } - list_add_tail(&desc->node, ioat->used_desc.next); - - desc->hw->next - = to_ioat_desc(desc->node.next)->txd.phys; - to_ioat_desc(desc->node.prev)->hw->next - = desc->txd.phys; - ioat->desccount++; - } - - ioat->used_desc.next = noop_desc->node.next; - } - new = to_ioat_desc(ioat->used_desc.next); - prefetch(new); - ioat->used_desc.next = new->node.next; - - if (ioat->used_desc.prev == NULL) - ioat->used_desc.prev = &new->node; - - prefetch(new->hw); - return new; -} - -static struct ioat_desc_sw * -ioat_dma_get_next_descriptor(struct ioat_dma_chan *ioat) -{ - if (!ioat) - return NULL; - - switch (ioat->base.device->version) { - case IOAT_VER_1_2: - return ioat1_dma_get_next_descriptor(ioat); - case IOAT_VER_2_0: - case IOAT_VER_3_0: - return ioat2_dma_get_next_descriptor(ioat); - } - return NULL; -} - static struct dma_async_tx_descriptor * ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, dma_addr_t dma_src, size_t len, unsigned long flags) @@ -886,7 +605,7 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, int tx_cnt = 0; spin_lock_bh(&ioat->desc_lock); - desc = ioat_dma_get_next_descriptor(ioat); + desc = ioat1_dma_get_next_descriptor(ioat); do { if (!desc) break; @@ -909,7 +628,7 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, struct ioat_desc_sw *next; async_tx_ack(&desc->txd); - next = ioat_dma_get_next_descriptor(ioat); + next = ioat1_dma_get_next_descriptor(ioat); hw->next = next ? next->txd.phys : 0; desc = next; } else @@ -920,8 +639,7 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, struct ioat_chan_common *chan = &ioat->base; dev_err(to_dev(chan), - "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n", - chan_num(chan), ioat->dmacount, ioat->desccount); + "chan%d - get_next_desc failed\n", chan_num(chan)); list_splice(&chain, &ioat->free_desc); spin_unlock_bh(&ioat->desc_lock); return NULL; @@ -940,94 +658,43 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, return &desc->txd; } -static struct dma_async_tx_descriptor * -ioat2_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, - dma_addr_t dma_src, size_t len, unsigned long flags) -{ - struct ioat_dma_chan *ioat = to_ioat_chan(c); - struct ioat_desc_sw *new; - - spin_lock_bh(&ioat->desc_lock); - new = ioat2_dma_get_next_descriptor(ioat); - - /* - * leave ioat->desc_lock set in ioat 2 path - * it will get unlocked at end of tx_submit - */ - - if (new) { - new->len = len; - new->dst = dma_dest; - new->src = dma_src; - new->txd.flags = flags; - return &new->txd; - } else { - struct ioat_chan_common *chan = &ioat->base; - - spin_unlock_bh(&ioat->desc_lock); - dev_err(to_dev(chan), - "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n", - chan_num(chan), ioat->dmacount, ioat->desccount); - return NULL; - } -} - -static void ioat_dma_cleanup_tasklet(unsigned long data) +static void ioat1_cleanup_tasklet(unsigned long data) { struct ioat_dma_chan *chan = (void *)data; - ioat_dma_memcpy_cleanup(chan); + ioat1_cleanup(chan); writew(IOAT_CHANCTRL_INT_DISABLE, chan->base.reg_base + IOAT_CHANCTRL_OFFSET); } -static void -ioat_dma_unmap(struct ioat_chan_common *chan, struct ioat_desc_sw *desc) +static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, + int direction, enum dma_ctrl_flags flags, bool dst) { - if (!(desc->txd.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { - if (desc->txd.flags & DMA_COMPL_DEST_UNMAP_SINGLE) - pci_unmap_single(chan->device->pdev, - pci_unmap_addr(desc, dst), - pci_unmap_len(desc, len), - PCI_DMA_FROMDEVICE); - else - pci_unmap_page(chan->device->pdev, - pci_unmap_addr(desc, dst), - pci_unmap_len(desc, len), - PCI_DMA_FROMDEVICE); - } - - if (!(desc->txd.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { - if (desc->txd.flags & DMA_COMPL_SRC_UNMAP_SINGLE) - pci_unmap_single(chan->device->pdev, - pci_unmap_addr(desc, src), - pci_unmap_len(desc, len), - PCI_DMA_TODEVICE); - else - pci_unmap_page(chan->device->pdev, - pci_unmap_addr(desc, src), - pci_unmap_len(desc, len), - PCI_DMA_TODEVICE); - } + if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) || + (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE))) + pci_unmap_single(pdev, addr, len, direction); + else + pci_unmap_page(pdev, addr, len, direction); } -/** - * ioat_dma_memcpy_cleanup - cleanup up finished descriptors - * @chan: ioat channel to be cleaned up - */ -static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat) + +void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, + size_t len, struct ioat_dma_descriptor *hw) { - struct ioat_chan_common *chan = &ioat->base; - unsigned long phys_complete; - struct ioat_desc_sw *desc, *_desc; - dma_cookie_t cookie = 0; - unsigned long desc_phys; - struct ioat_desc_sw *latest_desc; - struct dma_async_tx_descriptor *tx; + struct pci_dev *pdev = chan->device->pdev; + size_t offset = len - hw->size; - prefetch(chan->completion_virt); + if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) + ioat_unmap(pdev, hw->dst_addr - offset, len, + PCI_DMA_FROMDEVICE, flags, 1); - if (!spin_trylock_bh(&chan->cleanup_lock)) - return; + if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) + ioat_unmap(pdev, hw->src_addr - offset, len, + PCI_DMA_TODEVICE, flags, 0); +} + +unsigned long ioat_get_current_completion(struct ioat_chan_common *chan) +{ + unsigned long phys_complete; /* The completion writeback can happen at any time, so reads by the driver need to be atomic operations @@ -1051,18 +718,37 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat) /* TODO do something to salvage the situation */ } + return phys_complete; +} + +/** + * ioat1_cleanup - cleanup up finished descriptors + * @chan: ioat channel to be cleaned up + */ +static void ioat1_cleanup(struct ioat_dma_chan *ioat) +{ + struct ioat_chan_common *chan = &ioat->base; + unsigned long phys_complete; + struct ioat_desc_sw *desc, *_desc; + dma_cookie_t cookie = 0; + struct dma_async_tx_descriptor *tx; + + prefetch(chan->completion_virt); + + if (!spin_trylock_bh(&chan->cleanup_lock)) + return; + + phys_complete = ioat_get_current_completion(chan); if (phys_complete == chan->last_completion) { spin_unlock_bh(&chan->cleanup_lock); /* * perhaps we're stuck so hard that the watchdog can't go off? * try to catch it after 2 seconds */ - if (chan->device->version != IOAT_VER_3_0) { - if (time_after(jiffies, - chan->last_completion_time + HZ*WATCHDOG_DELAY)) { - ioat_dma_chan_watchdog(&(chan->device->work.work)); - chan->last_completion_time = jiffies; - } + if (time_after(jiffies, + chan->last_completion_time + HZ*WATCHDOG_DELAY)) { + ioat1_chan_watchdog(&(chan->device->work.work)); + chan->last_completion_time = jiffies; } return; } @@ -1074,91 +760,42 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat) return; } - switch (chan->device->version) { - case IOAT_VER_1_2: - list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { - tx = &desc->txd; - /* - * Incoming DMA requests may use multiple descriptors, - * due to exceeding xfercap, perhaps. If so, only the - * last one will have a cookie, and require unmapping. - */ - if (tx->cookie) { - cookie = tx->cookie; - ioat_dma_unmap(chan, desc); - if (tx->callback) { - tx->callback(tx->callback_param); - tx->callback = NULL; - } + list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { + tx = &desc->txd; + /* + * Incoming DMA requests may use multiple descriptors, + * due to exceeding xfercap, perhaps. If so, only the + * last one will have a cookie, and require unmapping. + */ + if (tx->cookie) { + cookie = tx->cookie; + ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw); + if (tx->callback) { + tx->callback(tx->callback_param); + tx->callback = NULL; } + } - if (tx->phys != phys_complete) { - /* - * a completed entry, but not the last, so clean - * up if the client is done with the descriptor - */ - if (async_tx_test_ack(tx)) { - list_move_tail(&desc->node, - &ioat->free_desc); - } else - tx->cookie = 0; - } else { - /* - * last used desc. Do not remove, so we can - * append from it, but don't look at it next - * time, either - */ + if (tx->phys != phys_complete) { + /* + * a completed entry, but not the last, so clean + * up if the client is done with the descriptor + */ + if (async_tx_test_ack(tx)) + list_move_tail(&desc->node, &ioat->free_desc); + else tx->cookie = 0; + } else { + /* + * last used desc. Do not remove, so we can + * append from it, but don't look at it next + * time, either + */ + tx->cookie = 0; - /* TODO check status bits? */ - break; - } - } - break; - case IOAT_VER_2_0: - case IOAT_VER_3_0: - /* has some other thread has already cleaned up? */ - if (ioat->used_desc.prev == NULL) + /* TODO check status bits? */ break; - - /* work backwards to find latest finished desc */ - desc = to_ioat_desc(ioat->used_desc.next); - tx = &desc->txd; - latest_desc = NULL; - do { - desc = to_ioat_desc(desc->node.prev); - desc_phys = (unsigned long)tx->phys - & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; - if (desc_phys == phys_complete) { - latest_desc = desc; - break; - } - } while (&desc->node != ioat->used_desc.prev); - - if (latest_desc != NULL) { - /* work forwards to clear finished descriptors */ - for (desc = to_ioat_desc(ioat->used_desc.prev); - &desc->node != latest_desc->node.next && - &desc->node != ioat->used_desc.next; - desc = to_ioat_desc(desc->node.next)) { - if (tx->cookie) { - cookie = tx->cookie; - tx->cookie = 0; - ioat_dma_unmap(chan, desc); - if (tx->callback) { - tx->callback(tx->callback_param); - tx->callback = NULL; - } - } - } - - /* move used.prev up beyond those that are finished */ - if (&desc->node == ioat->used_desc.next) - ioat->used_desc.prev = NULL; - else - ioat->used_desc.prev = &desc->node; } - break; } spin_unlock_bh(&ioat->desc_lock); @@ -1170,50 +807,21 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat) spin_unlock_bh(&chan->cleanup_lock); } -/** - * ioat_dma_is_complete - poll the status of a IOAT DMA transaction - * @chan: IOAT DMA channel handle - * @cookie: DMA transaction identifier - * @done: if not %NULL, updated with last completed transaction - * @used: if not %NULL, updated with last used transaction - */ static enum dma_status -ioat_dma_is_complete(struct dma_chan *c, dma_cookie_t cookie, - dma_cookie_t *done, dma_cookie_t *used) +ioat1_dma_is_complete(struct dma_chan *c, dma_cookie_t cookie, + dma_cookie_t *done, dma_cookie_t *used) { struct ioat_dma_chan *ioat = to_ioat_chan(c); - struct ioat_chan_common *chan = &ioat->base; - dma_cookie_t last_used; - dma_cookie_t last_complete; - enum dma_status ret; - - last_used = c->cookie; - last_complete = chan->completed_cookie; - chan->watchdog_tcp_cookie = cookie; - - if (done) - *done = last_complete; - if (used) - *used = last_used; - - ret = dma_async_is_complete(cookie, last_complete, last_used); - if (ret == DMA_SUCCESS) - return ret; - ioat_dma_memcpy_cleanup(ioat); + if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) + return DMA_SUCCESS; - last_used = c->cookie; - last_complete = chan->completed_cookie; + ioat1_cleanup(ioat); - if (done) - *done = last_complete; - if (used) - *used = last_used; - - return dma_async_is_complete(cookie, last_complete, last_used); + return ioat_is_complete(c, cookie, done, used); } -static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat) +static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat) { struct ioat_chan_common *chan = &ioat->base; struct ioat_desc_sw *desc; @@ -1221,7 +829,7 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat) spin_lock_bh(&ioat->desc_lock); - desc = ioat_dma_get_next_descriptor(ioat); + desc = ioat1_dma_get_next_descriptor(ioat); if (!desc) { dev_err(to_dev(chan), @@ -1240,30 +848,16 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat) hw->src_addr = 0; hw->dst_addr = 0; async_tx_ack(&desc->txd); - switch (chan->device->version) { - case IOAT_VER_1_2: - hw->next = 0; - list_add_tail(&desc->node, &ioat->used_desc); + hw->next = 0; + list_add_tail(&desc->node, &ioat->used_desc); - writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, - chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->txd.phys) >> 32, - chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); - - writeb(IOAT_CHANCMD_START, chan->reg_base - + IOAT_CHANCMD_OFFSET(chan->device->version)); - break; - case IOAT_VER_2_0: - case IOAT_VER_3_0: - writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, - chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->txd.phys) >> 32, - chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); + writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, + chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); + writel(((u64) desc->txd.phys) >> 32, + chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); - ioat->dmacount++; - __ioat2_dma_memcpy_issue_pending(ioat); - break; - } + writeb(IOAT_CHANCMD_START, chan->reg_base + + IOAT_CHANCMD_OFFSET(chan->device->version)); spin_unlock_bh(&ioat->desc_lock); } @@ -1484,7 +1078,7 @@ static void ioat_disable_interrupts(struct ioatdma_device *device) writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); } -static int ioat_probe(struct ioatdma_device *device) +int ioat_probe(struct ioatdma_device *device) { int err = -ENODEV; struct dma_device *dma = &device->common; @@ -1503,17 +1097,15 @@ static int ioat_probe(struct ioatdma_device *device) device->completion_pool = pci_pool_create("completion_pool", pdev, sizeof(u64), SMP_CACHE_BYTES, SMP_CACHE_BYTES); + if (!device->completion_pool) { err = -ENOMEM; goto err_completion_pool; } - ioat_dma_enumerate_channels(device); + device->enumerate_channels(device); dma_cap_set(DMA_MEMCPY, dma->cap_mask); - dma->device_alloc_chan_resources = ioat_dma_alloc_chan_resources; - dma->device_free_chan_resources = ioat_dma_free_chan_resources; - dma->device_is_tx_complete = ioat_dma_is_complete; dma->dev = &pdev->dev; dev_err(dev, "Intel(R) I/OAT DMA Engine found," @@ -1546,7 +1138,7 @@ err_dma_pool: return err; } -static int ioat_register(struct ioatdma_device *device) +int ioat_register(struct ioatdma_device *device) { int err = dma_async_device_register(&device->common); @@ -1580,9 +1172,13 @@ int ioat1_dma_probe(struct ioatdma_device *device, int dca) int err; device->intr_quirk = ioat1_intr_quirk; + device->enumerate_channels = ioat1_enumerate_channels; dma = &device->common; dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy; dma->device_issue_pending = ioat1_dma_memcpy_issue_pending; + dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources; + dma->device_free_chan_resources = ioat1_dma_free_chan_resources; + dma->device_is_tx_complete = ioat1_dma_is_complete; err = ioat_probe(device); if (err) @@ -1594,93 +1190,12 @@ int ioat1_dma_probe(struct ioatdma_device *device, int dca) if (dca) device->dca = ioat_dca_init(pdev, device->reg_base); - INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog); - schedule_delayed_work(&device->work, WATCHDOG_DELAY); - - return err; -} - -int ioat2_dma_probe(struct ioatdma_device *device, int dca) -{ - struct pci_dev *pdev = device->pdev; - struct dma_device *dma; - struct dma_chan *c; - struct ioat_chan_common *chan; - int err; - - dma = &device->common; - dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy; - dma->device_issue_pending = ioat2_dma_memcpy_issue_pending; - - err = ioat_probe(device); - if (err) - return err; - ioat_set_tcp_copy_break(2048); - - list_for_each_entry(c, &dma->channels, device_node) { - chan = to_chan_common(c); - writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU, - chan->reg_base + IOAT_DCACTRL_OFFSET); - } - - err = ioat_register(device); - if (err) - return err; - if (dca) - device->dca = ioat2_dca_init(pdev, device->reg_base); - - INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog); + INIT_DELAYED_WORK(&device->work, ioat1_chan_watchdog); schedule_delayed_work(&device->work, WATCHDOG_DELAY); return err; } -int ioat3_dma_probe(struct ioatdma_device *device, int dca) -{ - struct pci_dev *pdev = device->pdev; - struct dma_device *dma; - struct dma_chan *c; - struct ioat_chan_common *chan; - int err; - u16 dev_id; - - dma = &device->common; - dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy; - dma->device_issue_pending = ioat2_dma_memcpy_issue_pending; - - /* -= IOAT ver.3 workarounds =- */ - /* Write CHANERRMSK_INT with 3E07h to mask out the errors - * that can cause stability issues for IOAT ver.3 - */ - pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07); - - /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit - * (workaround for spurious config parity error after restart) - */ - pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); - if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) - pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10); - - err = ioat_probe(device); - if (err) - return err; - ioat_set_tcp_copy_break(262144); - - list_for_each_entry(c, &dma->channels, device_node) { - chan = to_chan_common(c); - writel(IOAT_DMA_DCA_ANY_CPU, - chan->reg_base + IOAT_DCACTRL_OFFSET); - } - - err = ioat_register(device); - if (err) - return err; - if (dca) - device->dca = ioat3_dca_init(pdev, device->reg_base); - - return err; -} - void ioat_dma_remove(struct ioatdma_device *device) { struct dma_device *dma = &device->common; @@ -1697,4 +1212,3 @@ void ioat_dma_remove(struct ioatdma_device *device) INIT_LIST_HEAD(&dma->channels); } - diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index 5b31db7..84065df 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -62,6 +62,7 @@ * @idx: per channel data * @dca: direct cache access context * @intr_quirk: interrupt setup quirk (for ioat_v1 devices) + * @enumerate_channels: hw version specific channel enumeration */ struct ioatdma_device { @@ -76,6 +77,7 @@ struct ioatdma_device { struct ioat_chan_common *idx[4]; struct dca_provider *dca; void (*intr_quirk)(struct ioatdma_device *device); + int (*enumerate_channels)(struct ioatdma_device *device); }; struct ioat_chan_common { @@ -106,6 +108,7 @@ struct ioat_chan_common { struct tasklet_struct cleanup_task; }; + /** * struct ioat_dma_chan - internal representation of a DMA channel */ @@ -119,7 +122,6 @@ struct ioat_dma_chan { struct list_head used_desc; int pending; - u16 dmacount; u16 desccount; }; @@ -135,6 +137,33 @@ static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c) return container_of(chan, struct ioat_dma_chan, base); } +/** + * ioat_is_complete - poll the status of an ioat transaction + * @c: channel handle + * @cookie: transaction identifier + * @done: if set, updated with last completed transaction + * @used: if set, updated with last used transaction + */ +static inline enum dma_status +ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie, + dma_cookie_t *done, dma_cookie_t *used) +{ + struct ioat_chan_common *chan = to_chan_common(c); + dma_cookie_t last_used; + dma_cookie_t last_complete; + + last_used = c->cookie; + last_complete = chan->completed_cookie; + chan->watchdog_tcp_cookie = cookie; + + if (done) + *done = last_complete; + if (used) + *used = last_used; + + return dma_async_is_complete(cookie, last_complete, last_used); +} + /* wrapper around hardware descriptor format + additional software fields */ /** @@ -162,11 +191,22 @@ static inline void ioat_set_tcp_copy_break(unsigned long copybreak) #endif } +static inline struct ioat_chan_common * +ioat_chan_by_index(struct ioatdma_device *device, int index) +{ + return device->idx[index]; +} + +int ioat_probe(struct ioatdma_device *device); +int ioat_register(struct ioatdma_device *device); int ioat1_dma_probe(struct ioatdma_device *dev, int dca); -int ioat2_dma_probe(struct ioatdma_device *dev, int dca); -int ioat3_dma_probe(struct ioatdma_device *dev, int dca); void ioat_dma_remove(struct ioatdma_device *device); struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); -struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); -struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase); +unsigned long ioat_get_current_completion(struct ioat_chan_common *chan); +void ioat_init_channel(struct ioatdma_device *device, + struct ioat_chan_common *chan, int idx, + work_func_t work_fn, void (*tasklet)(unsigned long), + unsigned long tasklet_data); +void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, + size_t len, struct ioat_dma_descriptor *hw); #endif /* IOATDMA_H */ diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c new file mode 100644 index 0000000..49ba1c7 --- /dev/null +++ b/drivers/dma/ioat/dma_v2.c @@ -0,0 +1,750 @@ +/* + * Intel I/OAT DMA Linux driver + * Copyright(c) 2004 - 2009 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + */ + +/* + * This driver supports an Intel I/OAT DMA engine (versions >= 2), which + * does asynchronous data movement and checksumming operations. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dma.h" +#include "dma_v2.h" +#include "registers.h" +#include "hw.h" + +static int ioat_ring_alloc_order = 8; +module_param(ioat_ring_alloc_order, int, 0644); +MODULE_PARM_DESC(ioat_ring_alloc_order, + "ioat2+: allocate 2^n descriptors per channel (default: n=8)"); + +static void __ioat2_issue_pending(struct ioat2_dma_chan *ioat) +{ + void * __iomem reg_base = ioat->base.reg_base; + + ioat->pending = 0; + ioat->dmacount += ioat2_ring_pending(ioat); + ioat->issued = ioat->head; + /* make descriptor updates globally visible before notifying channel */ + wmb(); + writew(ioat->dmacount, reg_base + IOAT_CHAN_DMACOUNT_OFFSET); + +} + +static void ioat2_issue_pending(struct dma_chan *chan) +{ + struct ioat2_dma_chan *ioat = to_ioat2_chan(chan); + + spin_lock_bh(&ioat->ring_lock); + if (ioat->pending == 1) + __ioat2_issue_pending(ioat); + spin_unlock_bh(&ioat->ring_lock); +} + +/** + * ioat2_update_pending - log pending descriptors + * @ioat: ioat2+ channel + * + * set pending to '1' unless pending is already set to '2', pending == 2 + * indicates that submission is temporarily blocked due to an in-flight + * reset. If we are already above the ioat_pending_level threshold then + * just issue pending. + * + * called with ring_lock held + */ +static void ioat2_update_pending(struct ioat2_dma_chan *ioat) +{ + if (unlikely(ioat->pending == 2)) + return; + else if (ioat2_ring_pending(ioat) > ioat_pending_level) + __ioat2_issue_pending(ioat); + else + ioat->pending = 1; +} + +static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat) +{ + void __iomem *reg_base = ioat->base.reg_base; + struct ioat_ring_ent *desc; + struct ioat_dma_descriptor *hw; + int idx; + + if (ioat2_ring_space(ioat) < 1) { + dev_err(to_dev(&ioat->base), + "Unable to start null desc - ring full\n"); + return; + } + + idx = ioat2_desc_alloc(ioat, 1); + desc = ioat2_get_ring_ent(ioat, idx); + + hw = desc->hw; + hw->ctl = 0; + hw->ctl_f.null = 1; + hw->ctl_f.int_en = 1; + hw->ctl_f.compl_write = 1; + /* set size to non-zero value (channel returns error when size is 0) */ + hw->size = NULL_DESC_BUFFER_SIZE; + hw->src_addr = 0; + hw->dst_addr = 0; + async_tx_ack(&desc->txd); + writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, + reg_base + IOAT2_CHAINADDR_OFFSET_LOW); + writel(((u64) desc->txd.phys) >> 32, + reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); + __ioat2_issue_pending(ioat); +} + +static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat) +{ + spin_lock_bh(&ioat->ring_lock); + __ioat2_start_null_desc(ioat); + spin_unlock_bh(&ioat->ring_lock); +} + +static void ioat2_cleanup(struct ioat2_dma_chan *ioat); + +/** + * ioat2_reset_part2 - reinit the channel after a reset + */ +static void ioat2_reset_part2(struct work_struct *work) +{ + struct ioat_chan_common *chan; + struct ioat2_dma_chan *ioat; + + chan = container_of(work, struct ioat_chan_common, work.work); + ioat = container_of(chan, struct ioat2_dma_chan, base); + + /* ensure that ->tail points to the stalled descriptor + * (ioat->pending is set to 2 at this point so no new + * descriptors will be issued while we perform this cleanup) + */ + ioat2_cleanup(ioat); + + spin_lock_bh(&chan->cleanup_lock); + spin_lock_bh(&ioat->ring_lock); + + /* set the tail to be re-issued */ + ioat->issued = ioat->tail; + ioat->dmacount = 0; + + if (ioat2_ring_pending(ioat)) { + struct ioat_ring_ent *desc; + + desc = ioat2_get_ring_ent(ioat, ioat->tail); + writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, + chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); + writel(((u64) desc->txd.phys) >> 32, + chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); + __ioat2_issue_pending(ioat); + } else + __ioat2_start_null_desc(ioat); + + spin_unlock_bh(&ioat->ring_lock); + spin_unlock_bh(&chan->cleanup_lock); + + dev_info(to_dev(chan), + "chan%d reset - %d descs waiting, %d total desc\n", + chan_num(chan), ioat->dmacount, 1 << ioat->alloc_order); +} + +/** + * ioat2_reset_channel - restart a channel + * @ioat: IOAT DMA channel handle + */ +static void ioat2_reset_channel(struct ioat2_dma_chan *ioat) +{ + u32 chansts, chanerr; + struct ioat_chan_common *chan = &ioat->base; + u16 active; + + spin_lock_bh(&ioat->ring_lock); + active = ioat2_ring_active(ioat); + spin_unlock_bh(&ioat->ring_lock); + if (!active) + return; + + chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); + chansts = (chan->completion_virt->low + & IOAT_CHANSTS_DMA_TRANSFER_STATUS); + if (chanerr) { + dev_err(to_dev(chan), + "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", + chan_num(chan), chansts, chanerr); + writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); + } + + spin_lock_bh(&ioat->ring_lock); + ioat->pending = 2; + writeb(IOAT_CHANCMD_RESET, + chan->reg_base + + IOAT_CHANCMD_OFFSET(chan->device->version)); + spin_unlock_bh(&ioat->ring_lock); + schedule_delayed_work(&chan->work, RESET_DELAY); +} + +/** + * ioat2_chan_watchdog - watch for stuck channels + */ +static void ioat2_chan_watchdog(struct work_struct *work) +{ + struct ioatdma_device *device = + container_of(work, struct ioatdma_device, work.work); + struct ioat2_dma_chan *ioat; + struct ioat_chan_common *chan; + u16 active; + int i; + + for (i = 0; i < device->common.chancnt; i++) { + chan = ioat_chan_by_index(device, i); + ioat = container_of(chan, struct ioat2_dma_chan, base); + + /* + * for version 2.0 if there are descriptors yet to be processed + * and the last completed hasn't changed since the last watchdog + * if they haven't hit the pending level + * issue the pending to push them through + * else + * try resetting the channel + */ + spin_lock_bh(&ioat->ring_lock); + active = ioat2_ring_active(ioat); + spin_unlock_bh(&ioat->ring_lock); + + if (active && + chan->last_completion && + chan->last_completion == chan->watchdog_completion) { + + if (ioat->pending == 1) + ioat2_issue_pending(&chan->common); + else { + ioat2_reset_channel(ioat); + chan->watchdog_completion = 0; + } + } else { + chan->last_compl_desc_addr_hw = 0; + chan->watchdog_completion = chan->last_completion; + } + chan->watchdog_last_tcp_cookie = chan->watchdog_tcp_cookie; + } + schedule_delayed_work(&device->work, WATCHDOG_DELAY); +} + +/** + * ioat2_cleanup - clean finished descriptors (advance tail pointer) + * @chan: ioat channel to be cleaned up + */ +static void ioat2_cleanup(struct ioat2_dma_chan *ioat) +{ + struct ioat_chan_common *chan = &ioat->base; + unsigned long phys_complete; + struct ioat_ring_ent *desc; + bool seen_current = false; + u16 active; + int i; + struct dma_async_tx_descriptor *tx; + + prefetch(chan->completion_virt); + + spin_lock_bh(&chan->cleanup_lock); + phys_complete = ioat_get_current_completion(chan); + if (phys_complete == chan->last_completion) { + spin_unlock_bh(&chan->cleanup_lock); + /* + * perhaps we're stuck so hard that the watchdog can't go off? + * try to catch it after WATCHDOG_DELAY seconds + */ + if (chan->device->version < IOAT_VER_3_0) { + unsigned long tmo; + + tmo = chan->last_completion_time + HZ*WATCHDOG_DELAY; + if (time_after(jiffies, tmo)) { + ioat2_chan_watchdog(&(chan->device->work.work)); + chan->last_completion_time = jiffies; + } + } + return; + } + chan->last_completion_time = jiffies; + + spin_lock_bh(&ioat->ring_lock); + + active = ioat2_ring_active(ioat); + for (i = 0; i < active && !seen_current; i++) { + prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1)); + desc = ioat2_get_ring_ent(ioat, ioat->tail + i); + tx = &desc->txd; + if (tx->cookie) { + ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw); + chan->completed_cookie = tx->cookie; + tx->cookie = 0; + if (tx->callback) { + tx->callback(tx->callback_param); + tx->callback = NULL; + } + } + + if (tx->phys == phys_complete) + seen_current = true; + } + ioat->tail += i; + BUG_ON(!seen_current); /* no active descs have written a completion? */ + spin_unlock_bh(&ioat->ring_lock); + + chan->last_completion = phys_complete; + + spin_unlock_bh(&chan->cleanup_lock); +} + +static void ioat2_cleanup_tasklet(unsigned long data) +{ + struct ioat2_dma_chan *ioat = (void *) data; + + ioat2_cleanup(ioat); + writew(IOAT_CHANCTRL_INT_DISABLE, + ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); +} + +/** + * ioat2_enumerate_channels - find and initialize the device's channels + * @device: the device to be enumerated + */ +static int ioat2_enumerate_channels(struct ioatdma_device *device) +{ + struct ioat2_dma_chan *ioat; + struct device *dev = &device->pdev->dev; + struct dma_device *dma = &device->common; + u8 xfercap_log; + int i; + + INIT_LIST_HEAD(&dma->channels); + dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); + xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET); + if (xfercap_log == 0) + return 0; + + /* FIXME which i/oat version is i7300? */ +#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL + if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) + dma->chancnt--; +#endif + for (i = 0; i < dma->chancnt; i++) { + ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL); + if (!ioat) + break; + + ioat_init_channel(device, &ioat->base, i, + ioat2_reset_part2, + ioat2_cleanup_tasklet, + (unsigned long) ioat); + ioat->xfercap_log = xfercap_log; + spin_lock_init(&ioat->ring_lock); + } + dma->chancnt = i; + return i; +} + +static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx) +{ + struct dma_chan *c = tx->chan; + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + dma_cookie_t cookie = c->cookie; + + cookie++; + if (cookie < 0) + cookie = 1; + tx->cookie = cookie; + c->cookie = cookie; + ioat2_update_pending(ioat); + spin_unlock_bh(&ioat->ring_lock); + + return cookie; +} + +static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan) +{ + struct ioat_dma_descriptor *hw; + struct ioat_ring_ent *desc; + struct ioatdma_device *dma; + dma_addr_t phys; + + dma = to_ioatdma_device(chan->device); + hw = pci_pool_alloc(dma->dma_pool, GFP_KERNEL, &phys); + if (!hw) + return NULL; + memset(hw, 0, sizeof(*hw)); + + desc = kzalloc(sizeof(*desc), GFP_KERNEL); + if (!desc) { + pci_pool_free(dma->dma_pool, hw, phys); + return NULL; + } + + dma_async_tx_descriptor_init(&desc->txd, chan); + desc->txd.tx_submit = ioat2_tx_submit_unlock; + desc->hw = hw; + desc->txd.phys = phys; + return desc; +} + +static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan) +{ + struct ioatdma_device *dma; + + dma = to_ioatdma_device(chan->device); + pci_pool_free(dma->dma_pool, desc->hw, desc->txd.phys); + kfree(desc); +} + +/* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring + * @chan: channel to be initialized + */ +static int ioat2_alloc_chan_resources(struct dma_chan *c) +{ + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + struct ioat_chan_common *chan = &ioat->base; + struct ioat_ring_ent **ring; + u16 chanctrl; + u32 chanerr; + int descs; + int i; + + /* have we already been set up? */ + if (ioat->ring) + return 1 << ioat->alloc_order; + + /* Setup register to interrupt and write completion status on error */ + chanctrl = IOAT_CHANCTRL_ERR_INT_EN | IOAT_CHANCTRL_ANY_ERR_ABORT_EN | + IOAT_CHANCTRL_ERR_COMPLETION_EN; + writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET); + + chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); + if (chanerr) { + dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr); + writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); + } + + /* allocate a completion writeback area */ + /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ + chan->completion_virt = pci_pool_alloc(chan->device->completion_pool, + GFP_KERNEL, + &chan->completion_addr); + if (!chan->completion_virt) + return -ENOMEM; + + memset(chan->completion_virt, 0, + sizeof(*chan->completion_virt)); + writel(((u64) chan->completion_addr) & 0x00000000FFFFFFFF, + chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); + writel(((u64) chan->completion_addr) >> 32, + chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); + + ioat->alloc_order = ioat_get_alloc_order(); + descs = 1 << ioat->alloc_order; + + /* allocate the array to hold the software ring */ + ring = kcalloc(descs, sizeof(*ring), GFP_KERNEL); + if (!ring) + return -ENOMEM; + for (i = 0; i < descs; i++) { + ring[i] = ioat2_alloc_ring_ent(c); + if (!ring[i]) { + while (i--) + ioat2_free_ring_ent(ring[i], c); + kfree(ring); + return -ENOMEM; + } + } + + /* link descs */ + for (i = 0; i < descs-1; i++) { + struct ioat_ring_ent *next = ring[i+1]; + struct ioat_dma_descriptor *hw = ring[i]->hw; + + hw->next = next->txd.phys; + } + ring[i]->hw->next = ring[0]->txd.phys; + + spin_lock_bh(&ioat->ring_lock); + ioat->ring = ring; + ioat->head = 0; + ioat->issued = 0; + ioat->tail = 0; + ioat->pending = 0; + spin_unlock_bh(&ioat->ring_lock); + + tasklet_enable(&chan->cleanup_task); + ioat2_start_null_desc(ioat); + + return descs; +} + +/** + * ioat2_alloc_and_lock - common descriptor alloc boilerplate for ioat2,3 ops + * @idx: gets starting descriptor index on successful allocation + * @ioat: ioat2,3 channel (ring) to operate on + * @num_descs: allocation length + */ +static int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs) +{ + struct ioat_chan_common *chan = &ioat->base; + + spin_lock_bh(&ioat->ring_lock); + if (unlikely(ioat2_ring_space(ioat) < num_descs)) { + if (printk_ratelimit()) + dev_dbg(to_dev(chan), + "%s: ring full! num_descs: %d (%x:%x:%x)\n", + __func__, num_descs, ioat->head, ioat->tail, + ioat->issued); + spin_unlock_bh(&ioat->ring_lock); + + /* do direct reclaim in the allocation failure case */ + ioat2_cleanup(ioat); + + return -ENOMEM; + } + + dev_dbg(to_dev(chan), "%s: num_descs: %d (%x:%x:%x)\n", + __func__, num_descs, ioat->head, ioat->tail, ioat->issued); + + *idx = ioat2_desc_alloc(ioat, num_descs); + return 0; /* with ioat->ring_lock held */ +} + +static struct dma_async_tx_descriptor * +ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, + dma_addr_t dma_src, size_t len, unsigned long flags) +{ + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + struct ioat_dma_descriptor *hw; + struct ioat_ring_ent *desc; + dma_addr_t dst = dma_dest; + dma_addr_t src = dma_src; + size_t total_len = len; + int num_descs; + u16 idx; + int i; + + num_descs = ioat2_xferlen_to_descs(ioat, len); + if (likely(num_descs) && + ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0) + /* pass */; + else + return NULL; + for (i = 0; i < num_descs; i++) { + size_t copy = min_t(size_t, len, 1 << ioat->xfercap_log); + + desc = ioat2_get_ring_ent(ioat, idx + i); + hw = desc->hw; + + hw->size = copy; + hw->ctl = 0; + hw->src_addr = src; + hw->dst_addr = dst; + + len -= copy; + dst += copy; + src += copy; + } + + desc->txd.flags = flags; + desc->len = total_len; + hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); + hw->ctl_f.compl_write = 1; + /* we leave the channel locked to ensure in order submission */ + + return &desc->txd; +} + +/** + * ioat2_free_chan_resources - release all the descriptors + * @chan: the channel to be cleaned + */ +static void ioat2_free_chan_resources(struct dma_chan *c) +{ + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + struct ioat_chan_common *chan = &ioat->base; + struct ioatdma_device *ioatdma_device = chan->device; + struct ioat_ring_ent *desc; + const u16 total_descs = 1 << ioat->alloc_order; + int descs; + int i; + + /* Before freeing channel resources first check + * if they have been previously allocated for this channel. + */ + if (!ioat->ring) + return; + + tasklet_disable(&chan->cleanup_task); + ioat2_cleanup(ioat); + + /* Delay 100ms after reset to allow internal DMA logic to quiesce + * before removing DMA descriptor resources. + */ + writeb(IOAT_CHANCMD_RESET, + chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); + mdelay(100); + + spin_lock_bh(&ioat->ring_lock); + descs = ioat2_ring_space(ioat); + for (i = 0; i < descs; i++) { + desc = ioat2_get_ring_ent(ioat, ioat->head + i); + ioat2_free_ring_ent(desc, c); + } + + if (descs < total_descs) + dev_err(to_dev(chan), "Freeing %d in use descriptors!\n", + total_descs - descs); + + for (i = 0; i < total_descs - descs; i++) { + desc = ioat2_get_ring_ent(ioat, ioat->tail + i); + ioat2_free_ring_ent(desc, c); + } + + kfree(ioat->ring); + ioat->ring = NULL; + ioat->alloc_order = 0; + pci_pool_free(ioatdma_device->completion_pool, + chan->completion_virt, + chan->completion_addr); + spin_unlock_bh(&ioat->ring_lock); + + chan->last_completion = 0; + chan->completion_addr = 0; + ioat->pending = 0; + ioat->dmacount = 0; + chan->watchdog_completion = 0; + chan->last_compl_desc_addr_hw = 0; + chan->watchdog_tcp_cookie = 0; + chan->watchdog_last_tcp_cookie = 0; +} + +static enum dma_status +ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie, + dma_cookie_t *done, dma_cookie_t *used) +{ + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + + if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) + return DMA_SUCCESS; + + ioat2_cleanup(ioat); + + return ioat_is_complete(c, cookie, done, used); +} + +int ioat2_dma_probe(struct ioatdma_device *device, int dca) +{ + struct pci_dev *pdev = device->pdev; + struct dma_device *dma; + struct dma_chan *c; + struct ioat_chan_common *chan; + int err; + + device->enumerate_channels = ioat2_enumerate_channels; + dma = &device->common; + dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; + dma->device_issue_pending = ioat2_issue_pending; + dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; + dma->device_free_chan_resources = ioat2_free_chan_resources; + dma->device_is_tx_complete = ioat2_is_complete; + + err = ioat_probe(device); + if (err) + return err; + ioat_set_tcp_copy_break(2048); + + list_for_each_entry(c, &dma->channels, device_node) { + chan = to_chan_common(c); + writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU, + chan->reg_base + IOAT_DCACTRL_OFFSET); + } + + err = ioat_register(device); + if (err) + return err; + if (dca) + device->dca = ioat2_dca_init(pdev, device->reg_base); + + INIT_DELAYED_WORK(&device->work, ioat2_chan_watchdog); + schedule_delayed_work(&device->work, WATCHDOG_DELAY); + + return err; +} + +int ioat3_dma_probe(struct ioatdma_device *device, int dca) +{ + struct pci_dev *pdev = device->pdev; + struct dma_device *dma; + struct dma_chan *c; + struct ioat_chan_common *chan; + int err; + u16 dev_id; + + device->enumerate_channels = ioat2_enumerate_channels; + dma = &device->common; + dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; + dma->device_issue_pending = ioat2_issue_pending; + dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; + dma->device_free_chan_resources = ioat2_free_chan_resources; + dma->device_is_tx_complete = ioat2_is_complete; + + /* -= IOAT ver.3 workarounds =- */ + /* Write CHANERRMSK_INT with 3E07h to mask out the errors + * that can cause stability issues for IOAT ver.3 + */ + pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07); + + /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit + * (workaround for spurious config parity error after restart) + */ + pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); + if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) + pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10); + + err = ioat_probe(device); + if (err) + return err; + ioat_set_tcp_copy_break(262144); + + list_for_each_entry(c, &dma->channels, device_node) { + chan = to_chan_common(c); + writel(IOAT_DMA_DCA_ANY_CPU, + chan->reg_base + IOAT_DCACTRL_OFFSET); + } + + err = ioat_register(device); + if (err) + return err; + if (dca) + device->dca = ioat3_dca_init(pdev, device->reg_base); + + return err; +} diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h new file mode 100644 index 0000000..94a553e --- /dev/null +++ b/drivers/dma/ioat/dma_v2.h @@ -0,0 +1,131 @@ +/* + * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * The full GNU General Public License is included in this distribution in the + * file called COPYING. + */ +#ifndef IOATDMA_V2_H +#define IOATDMA_V2_H + +#include +#include "dma.h" +#include "hw.h" + + +extern int ioat_pending_level; + +/* + * workaround for IOAT ver.3.0 null descriptor issue + * (channel returns error when size is 0) + */ +#define NULL_DESC_BUFFER_SIZE 1 + +#define IOAT_MAX_ORDER 16 +#define ioat_get_alloc_order() \ + (min(ioat_ring_alloc_order, IOAT_MAX_ORDER)) + +/* struct ioat2_dma_chan - ioat v2 / v3 channel attributes + * @base: common ioat channel parameters + * @xfercap_log; log2 of channel max transfer length (for fast division) + * @head: allocated index + * @issued: hardware notification point + * @tail: cleanup index + * @pending: lock free indicator for issued != head + * @dmacount: identical to 'head' except for occasionally resetting to zero + * @alloc_order: log2 of the number of allocated descriptors + * @ring: software ring buffer implementation of hardware ring + * @ring_lock: protects ring attributes + */ +struct ioat2_dma_chan { + struct ioat_chan_common base; + size_t xfercap_log; + u16 head; + u16 issued; + u16 tail; + u16 dmacount; + u16 alloc_order; + int pending; + struct ioat_ring_ent **ring; + spinlock_t ring_lock; +}; + +static inline struct ioat2_dma_chan *to_ioat2_chan(struct dma_chan *c) +{ + struct ioat_chan_common *chan = to_chan_common(c); + + return container_of(chan, struct ioat2_dma_chan, base); +} + +static inline u16 ioat2_ring_mask(struct ioat2_dma_chan *ioat) +{ + return (1 << ioat->alloc_order) - 1; +} + +/* count of descriptors in flight with the engine */ +static inline u16 ioat2_ring_active(struct ioat2_dma_chan *ioat) +{ + return (ioat->head - ioat->tail) & ioat2_ring_mask(ioat); +} + +/* count of descriptors pending submission to hardware */ +static inline u16 ioat2_ring_pending(struct ioat2_dma_chan *ioat) +{ + return (ioat->head - ioat->issued) & ioat2_ring_mask(ioat); +} + +static inline u16 ioat2_ring_space(struct ioat2_dma_chan *ioat) +{ + u16 num_descs = ioat2_ring_mask(ioat) + 1; + u16 active = ioat2_ring_active(ioat); + + BUG_ON(active > num_descs); + + return num_descs - active; +} + +/* assumes caller already checked space */ +static inline u16 ioat2_desc_alloc(struct ioat2_dma_chan *ioat, u16 len) +{ + ioat->head += len; + return ioat->head - len; +} + +static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len) +{ + u16 num_descs = len >> ioat->xfercap_log; + + num_descs += !!(len & ((1 << ioat->xfercap_log) - 1)); + return num_descs; +} + +struct ioat_ring_ent { + struct ioat_dma_descriptor *hw; + struct dma_async_tx_descriptor txd; + size_t len; +}; + +static inline struct ioat_ring_ent * +ioat2_get_ring_ent(struct ioat2_dma_chan *ioat, u16 idx) +{ + return ioat->ring[idx & ioat2_ring_mask(ioat)]; +} + +int ioat2_dma_probe(struct ioatdma_device *dev, int dca); +int ioat3_dma_probe(struct ioatdma_device *dev, int dca); +struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); +struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase); +#endif /* IOATDMA_V2_H */ diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c index 55414d8..c4e4322 100644 --- a/drivers/dma/ioat/pci.c +++ b/drivers/dma/ioat/pci.c @@ -31,6 +31,7 @@ #include #include #include "dma.h" +#include "dma_v2.h" #include "registers.h" #include "hw.h" -- cgit v0.10.2 From 38e12f64a165e83617c21dae3c15972fd8d639f5 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 12:00:46 -0700 Subject: ioat1: kill unused unmap parameters The unified ioat1/ioat2 ioat_dma_unmap() implementation derives the source and dest addresses from the unmap descriptor. There is no longer a need to track this information in struct ioat_desc_sw. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 64b4d75..696d4de 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -648,8 +648,6 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, desc->txd.flags = flags; desc->tx_cnt = tx_cnt; - desc->src = dma_src; - desc->dst = dma_dest; desc->len = total_len; list_splice(&chain, &desc->txd.tx_list); hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index 84065df..fa15e77 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -179,8 +179,6 @@ struct ioat_desc_sw { struct list_head node; int tx_cnt; size_t len; - dma_addr_t src; - dma_addr_t dst; struct dma_async_tx_descriptor txd; }; -- cgit v0.10.2 From 6df9183a153291a2585a8dfe67597fc18c201147 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 12:00:55 -0700 Subject: ioat: add some dev_dbg() calls Provide some output for debugging the driver. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 696d4de..edf4f5e 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -134,6 +134,7 @@ static int ioat1_enumerate_channels(struct ioatdma_device *device) dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); + dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap); #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) @@ -167,6 +168,8 @@ __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat) { void __iomem *reg_base = ioat->base.reg_base; + dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n", + __func__, ioat->pending); ioat->pending = 0; writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET); } @@ -251,6 +254,7 @@ static void ioat1_reset_channel(struct ioat_dma_chan *ioat) if (!ioat->used_desc.prev) return; + dev_dbg(to_dev(chan), "%s\n", __func__); chanerr = readl(reg_base + IOAT_CHANERR_OFFSET); chansts = (chan->completion_virt->low & IOAT_CHANSTS_DMA_TRANSFER_STATUS); @@ -382,6 +386,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) cookie = 1; c->cookie = cookie; tx->cookie = cookie; + dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie); /* write address into NextDescriptor field of last desc in chain */ first = to_ioat_desc(tx->tx_list.next); @@ -390,6 +395,8 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) wmb(); chain_tail->hw->next = first->txd.phys; list_splice_tail_init(&tx->tx_list, &ioat->used_desc); + dump_desc_dbg(ioat, chain_tail); + dump_desc_dbg(ioat, first); ioat->pending += desc->tx_cnt; if (ioat->pending >= ioat_pending_level) @@ -429,6 +436,7 @@ ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags) desc_sw->txd.tx_submit = ioat1_tx_submit; desc_sw->hw = desc; desc_sw->txd.phys = phys; + set_desc_id(desc_sw, -1); return desc_sw; } @@ -474,6 +482,7 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c) dev_err(to_dev(chan), "Only %d initial descriptors\n", i); break; } + set_desc_id(desc, i); list_add_tail(&desc->node, &tmp_list); } spin_lock_bh(&ioat->desc_lock); @@ -495,6 +504,8 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c) tasklet_enable(&chan->cleanup_task); ioat1_dma_start_null_desc(ioat); /* give chain to dma device */ + dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n", + __func__, ioat->desccount); return ioat->desccount; } @@ -527,8 +538,10 @@ static void ioat1_dma_free_chan_resources(struct dma_chan *c) mdelay(100); spin_lock_bh(&ioat->desc_lock); - list_for_each_entry_safe(desc, _desc, - &ioat->used_desc, node) { + list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { + dev_dbg(to_dev(chan), "%s: freeing %d from used list\n", + __func__, desc_id(desc)); + dump_desc_dbg(ioat, desc); in_use_descs++; list_del(&desc->node); pci_pool_free(ioatdma_device->dma_pool, desc->hw, @@ -585,7 +598,8 @@ ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat) return NULL; } } - + dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n", + __func__, desc_id(new)); prefetch(new->hw); return new; } @@ -630,6 +644,7 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, async_tx_ack(&desc->txd); next = ioat1_dma_get_next_descriptor(ioat); hw->next = next ? next->txd.phys : 0; + dump_desc_dbg(ioat, desc); desc = next; } else hw->next = 0; @@ -652,6 +667,7 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, list_splice(&chain, &desc->txd.tx_list); hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); hw->ctl_f.compl_write = 1; + dump_desc_dbg(ioat, desc); return &desc->txd; } @@ -707,6 +723,9 @@ unsigned long ioat_get_current_completion(struct ioat_chan_common *chan) phys_complete = chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK; #endif + dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__, + (unsigned long long) phys_complete); + if ((chan->completion_virt->full & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) { @@ -758,6 +777,8 @@ static void ioat1_cleanup(struct ioat_dma_chan *ioat) return; } + dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n", + __func__, phys_complete); list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { tx = &desc->txd; /* @@ -765,6 +786,7 @@ static void ioat1_cleanup(struct ioat_dma_chan *ioat) * due to exceeding xfercap, perhaps. If so, only the * last one will have a cookie, and require unmapping. */ + dump_desc_dbg(ioat, desc); if (tx->cookie) { cookie = tx->cookie; ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw); @@ -848,6 +870,7 @@ static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat) async_tx_ack(&desc->txd); hw->next = 0; list_add_tail(&desc->node, &ioat->used_desc); + dump_desc_dbg(ioat, desc); writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index fa15e77..9f9edc2c 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -173,6 +173,7 @@ ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie, * or attached to a transaction list (async_tx.tx_list) * @tx_cnt: number of descriptors required to complete the transaction * @txd: the generic software descriptor for all engines + * @id: identifier for debug */ struct ioat_desc_sw { struct ioat_dma_descriptor *hw; @@ -180,8 +181,35 @@ struct ioat_desc_sw { int tx_cnt; size_t len; struct dma_async_tx_descriptor txd; + #ifdef DEBUG + int id; + #endif }; +#ifdef DEBUG +#define set_desc_id(desc, i) ((desc)->id = (i)) +#define desc_id(desc) ((desc)->id) +#else +#define set_desc_id(desc, i) +#define desc_id(desc) (0) +#endif + +static inline void +__dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw, + struct dma_async_tx_descriptor *tx, int id) +{ + struct device *dev = to_dev(chan); + + dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x" + " ctl: %#x (op: %d int_en: %d compl: %d)\n", id, + (unsigned long long) tx->phys, + (unsigned long long) hw->next, tx->cookie, tx->flags, + hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write); +} + +#define dump_desc_dbg(c, d) \ + ({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; }) + static inline void ioat_set_tcp_copy_break(unsigned long copybreak) { #ifdef CONFIG_NET_DMA diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 49ba1c7..5888186 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -54,7 +54,9 @@ static void __ioat2_issue_pending(struct ioat2_dma_chan *ioat) /* make descriptor updates globally visible before notifying channel */ wmb(); writew(ioat->dmacount, reg_base + IOAT_CHAN_DMACOUNT_OFFSET); - + dev_dbg(to_dev(&ioat->base), + "%s: head: %#x tail: %#x issued: %#x count: %#x\n", + __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount); } static void ioat2_issue_pending(struct dma_chan *chan) @@ -101,6 +103,8 @@ static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat) return; } + dev_dbg(to_dev(&ioat->base), "%s: head: %#x tail: %#x issued: %#x\n", + __func__, ioat->head, ioat->tail, ioat->issued); idx = ioat2_desc_alloc(ioat, 1); desc = ioat2_get_ring_ent(ioat, idx); @@ -118,6 +122,7 @@ static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat) reg_base + IOAT2_CHAINADDR_OFFSET_LOW); writel(((u64) desc->txd.phys) >> 32, reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); + dump_desc_dbg(ioat, desc); __ioat2_issue_pending(ioat); } @@ -154,6 +159,10 @@ static void ioat2_reset_part2(struct work_struct *work) ioat->issued = ioat->tail; ioat->dmacount = 0; + dev_dbg(to_dev(&ioat->base), + "%s: head: %#x tail: %#x issued: %#x count: %#x\n", + __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount); + if (ioat2_ring_pending(ioat)) { struct ioat_ring_ent *desc; @@ -221,6 +230,8 @@ static void ioat2_chan_watchdog(struct work_struct *work) u16 active; int i; + dev_dbg(&device->pdev->dev, "%s\n", __func__); + for (i = 0; i < device->common.chancnt; i++) { chan = ioat_chan_by_index(device, i); ioat = container_of(chan, struct ioat2_dma_chan, base); @@ -295,11 +306,15 @@ static void ioat2_cleanup(struct ioat2_dma_chan *ioat) spin_lock_bh(&ioat->ring_lock); + dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n", + __func__, ioat->head, ioat->tail, ioat->issued); + active = ioat2_ring_active(ioat); for (i = 0; i < active && !seen_current; i++) { prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1)); desc = ioat2_get_ring_ent(ioat, ioat->tail + i); tx = &desc->txd; + dump_desc_dbg(ioat, desc); if (tx->cookie) { ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw); chan->completed_cookie = tx->cookie; @@ -348,6 +363,7 @@ static int ioat2_enumerate_channels(struct ioatdma_device *device) xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET); if (xfercap_log == 0) return 0; + dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log); /* FIXME which i/oat version is i7300? */ #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL @@ -381,6 +397,8 @@ static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx) cookie = 1; tx->cookie = cookie; c->cookie = cookie; + dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie); + ioat2_update_pending(ioat); spin_unlock_bh(&ioat->ring_lock); @@ -480,6 +498,7 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c) kfree(ring); return -ENOMEM; } + set_desc_id(ring[i], i); } /* link descs */ @@ -571,12 +590,14 @@ ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, len -= copy; dst += copy; src += copy; + dump_desc_dbg(ioat, desc); } desc->txd.flags = flags; desc->len = total_len; hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); hw->ctl_f.compl_write = 1; + dump_desc_dbg(ioat, desc); /* we leave the channel locked to ensure in order submission */ return &desc->txd; @@ -614,6 +635,7 @@ static void ioat2_free_chan_resources(struct dma_chan *c) spin_lock_bh(&ioat->ring_lock); descs = ioat2_ring_space(ioat); + dev_dbg(to_dev(chan), "freeing %d idle descriptors\n", descs); for (i = 0; i < descs; i++) { desc = ioat2_get_ring_ent(ioat, ioat->head + i); ioat2_free_ring_ent(desc, c); @@ -625,6 +647,7 @@ static void ioat2_free_chan_resources(struct dma_chan *c) for (i = 0; i < total_descs - descs; i++) { desc = ioat2_get_ring_ent(ioat, ioat->tail + i); + dump_desc_dbg(ioat, desc); ioat2_free_ring_ent(desc, c); } diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h index 94a553e..c72ccb5 100644 --- a/drivers/dma/ioat/dma_v2.h +++ b/drivers/dma/ioat/dma_v2.h @@ -116,6 +116,9 @@ struct ioat_ring_ent { struct ioat_dma_descriptor *hw; struct dma_async_tx_descriptor txd; size_t len; + #ifdef DEBUG + int id; + #endif }; static inline struct ioat_ring_ent * -- cgit v0.10.2 From 4fb9b9e8d55880523db550043dfb204696dd0422 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 12:01:04 -0700 Subject: ioat: cleanup completion status reads The cleanup path makes an effort to only perform an atomic read of the 64-bit completion address. However in the 32-bit case it does not matter if we read the upper-32 and lower-32 non-atomically because the upper-32 will always be zero. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index edf4f5e..08417ad 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -201,8 +201,7 @@ static void ioat1_reset_part2(struct work_struct *work) spin_lock_bh(&chan->cleanup_lock); spin_lock_bh(&ioat->desc_lock); - chan->completion_virt->low = 0; - chan->completion_virt->high = 0; + *chan->completion = 0; ioat->pending = 0; /* count the descriptors waiting */ @@ -256,8 +255,7 @@ static void ioat1_reset_channel(struct ioat_dma_chan *ioat) dev_dbg(to_dev(chan), "%s\n", __func__); chanerr = readl(reg_base + IOAT_CHANERR_OFFSET); - chansts = (chan->completion_virt->low - & IOAT_CHANSTS_DMA_TRANSFER_STATUS); + chansts = *chan->completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS; if (chanerr) { dev_err(to_dev(chan), "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", @@ -293,14 +291,8 @@ static void ioat1_chan_watchdog(struct work_struct *work) struct ioat_dma_chan *ioat; struct ioat_chan_common *chan; int i; - - union { - u64 full; - struct { - u32 low; - u32 high; - }; - } completion_hw; + u64 completion; + u32 completion_low; unsigned long compl_desc_addr_hw; for (i = 0; i < device->common.chancnt; i++) { @@ -334,25 +326,24 @@ static void ioat1_chan_watchdog(struct work_struct *work) * try resetting the channel */ - completion_hw.low = readl(chan->reg_base + + /* we need to read the low address first as this + * causes the chipset to latch the upper bits + * for the subsequent read + */ + completion_low = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(chan->device->version)); - completion_hw.high = readl(chan->reg_base + + completion = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(chan->device->version)); -#if (BITS_PER_LONG == 64) - compl_desc_addr_hw = - completion_hw.full - & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; -#else - compl_desc_addr_hw = - completion_hw.low & IOAT_LOW_COMPLETION_MASK; -#endif + completion <<= 32; + completion |= completion_low; + compl_desc_addr_hw = completion & + IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; if ((compl_desc_addr_hw != 0) && (compl_desc_addr_hw != chan->watchdog_completion) && (compl_desc_addr_hw != chan->last_compl_desc_addr_hw)) { chan->last_compl_desc_addr_hw = compl_desc_addr_hw; - chan->completion_virt->low = completion_hw.low; - chan->completion_virt->high = completion_hw.high; + *chan->completion = completion; } else { ioat1_reset_channel(ioat); chan->watchdog_completion = 0; @@ -492,14 +483,12 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c) /* allocate a completion writeback area */ /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ - chan->completion_virt = pci_pool_alloc(chan->device->completion_pool, - GFP_KERNEL, - &chan->completion_addr); - memset(chan->completion_virt, 0, - sizeof(*chan->completion_virt)); - writel(((u64) chan->completion_addr) & 0x00000000FFFFFFFF, + chan->completion = pci_pool_alloc(chan->device->completion_pool, + GFP_KERNEL, &chan->completion_dma); + memset(chan->completion, 0, sizeof(*chan->completion)); + writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF, chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); - writel(((u64) chan->completion_addr) >> 32, + writel(((u64) chan->completion_dma) >> 32, chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); tasklet_enable(&chan->cleanup_task); @@ -558,15 +547,16 @@ static void ioat1_dma_free_chan_resources(struct dma_chan *c) spin_unlock_bh(&ioat->desc_lock); pci_pool_free(ioatdma_device->completion_pool, - chan->completion_virt, - chan->completion_addr); + chan->completion, + chan->completion_dma); /* one is ok since we left it on there on purpose */ if (in_use_descs > 1) dev_err(to_dev(chan), "Freeing %d in use descriptors!\n", in_use_descs - 1); - chan->last_completion = chan->completion_addr = 0; + chan->last_completion = 0; + chan->completion_dma = 0; chan->watchdog_completion = 0; chan->last_compl_desc_addr_hw = 0; chan->watchdog_tcp_cookie = chan->watchdog_last_tcp_cookie = 0; @@ -709,25 +699,15 @@ void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, unsigned long ioat_get_current_completion(struct ioat_chan_common *chan) { unsigned long phys_complete; + u64 completion; - /* The completion writeback can happen at any time, - so reads by the driver need to be atomic operations - The descriptor physical addresses are limited to 32-bits - when the CPU can only do a 32-bit mov */ - -#if (BITS_PER_LONG == 64) - phys_complete = - chan->completion_virt->full - & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; -#else - phys_complete = chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK; -#endif + completion = *chan->completion; + phys_complete = completion & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__, (unsigned long long) phys_complete); - if ((chan->completion_virt->full - & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == + if ((completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) { dev_err(to_dev(chan), "Channel halted, chanerr = %x\n", readl(chan->reg_base + IOAT_CHANERR_OFFSET)); @@ -750,7 +730,7 @@ static void ioat1_cleanup(struct ioat_dma_chan *ioat) dma_cookie_t cookie = 0; struct dma_async_tx_descriptor *tx; - prefetch(chan->completion_virt); + prefetch(chan->completion); if (!spin_trylock_bh(&chan->cleanup_lock)) return; diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index 9f9edc2c..5fd6e2d 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -96,14 +96,8 @@ struct ioat_chan_common { struct ioatdma_device *device; struct dma_chan common; - dma_addr_t completion_addr; - union { - u64 full; /* HW completion writeback */ - struct { - u32 low; - u32 high; - }; - } *completion_virt; + dma_addr_t completion_dma; + u64 *completion; unsigned long last_compl_desc_addr_hw; struct tasklet_struct cleanup_task; }; diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 5888186..ca11342 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -200,8 +200,7 @@ static void ioat2_reset_channel(struct ioat2_dma_chan *ioat) return; chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); - chansts = (chan->completion_virt->low - & IOAT_CHANSTS_DMA_TRANSFER_STATUS); + chansts = *chan->completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS; if (chanerr) { dev_err(to_dev(chan), "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", @@ -281,7 +280,7 @@ static void ioat2_cleanup(struct ioat2_dma_chan *ioat) int i; struct dma_async_tx_descriptor *tx; - prefetch(chan->completion_virt); + prefetch(chan->completion); spin_lock_bh(&chan->cleanup_lock); phys_complete = ioat_get_current_completion(chan); @@ -470,17 +469,15 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c) /* allocate a completion writeback area */ /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ - chan->completion_virt = pci_pool_alloc(chan->device->completion_pool, - GFP_KERNEL, - &chan->completion_addr); - if (!chan->completion_virt) + chan->completion = pci_pool_alloc(chan->device->completion_pool, + GFP_KERNEL, &chan->completion_dma); + if (!chan->completion) return -ENOMEM; - memset(chan->completion_virt, 0, - sizeof(*chan->completion_virt)); - writel(((u64) chan->completion_addr) & 0x00000000FFFFFFFF, + memset(chan->completion, 0, sizeof(*chan->completion)); + writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF, chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); - writel(((u64) chan->completion_addr) >> 32, + writel(((u64) chan->completion_dma) >> 32, chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); ioat->alloc_order = ioat_get_alloc_order(); @@ -655,12 +652,12 @@ static void ioat2_free_chan_resources(struct dma_chan *c) ioat->ring = NULL; ioat->alloc_order = 0; pci_pool_free(ioatdma_device->completion_pool, - chan->completion_virt, - chan->completion_addr); + chan->completion, + chan->completion_dma); spin_unlock_bh(&ioat->ring_lock); chan->last_completion = 0; - chan->completion_addr = 0; + chan->completion_dma = 0; ioat->pending = 0; ioat->dmacount = 0; chan->watchdog_completion = 0; diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h index 49bc277..a83c733 100644 --- a/drivers/dma/ioat/registers.h +++ b/drivers/dma/ioat/registers.h @@ -94,10 +94,10 @@ #define IOAT2_CHANSTS_OFFSET_HIGH 0x0C #define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ ? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH) -#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR ~0x3F -#define IOAT_CHANSTS_SOFT_ERR 0x0000000000000010 -#define IOAT_CHANSTS_UNAFFILIATED_ERR 0x0000000000000008 -#define IOAT_CHANSTS_DMA_TRANSFER_STATUS 0x0000000000000007 +#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) +#define IOAT_CHANSTS_SOFT_ERR 0x10ULL +#define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL +#define IOAT_CHANSTS_DMA_TRANSFER_STATUS 0x7ULL #define IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE 0x0 #define IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE 0x1 #define IOAT_CHANSTS_DMA_TRANSFER_STATUS_SUSPENDED 0x2 -- cgit v0.10.2 From bb3207863014c7310593146f11fbc6573eab43c8 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 12:01:14 -0700 Subject: ioat: ignore reserved bits for chancnt and xfercap Don't trust that the reserved bits are always zero, also sanity check the returned value. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 08417ad..5173ba9 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -132,7 +132,14 @@ static int ioat1_enumerate_channels(struct ioatdma_device *device) INIT_LIST_HEAD(&dma->channels); dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); + dma->chancnt &= 0x1f; /* bits [4:0] valid */ + if (dma->chancnt > ARRAY_SIZE(device->idx)) { + dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", + dma->chancnt, ARRAY_SIZE(device->idx)); + dma->chancnt = ARRAY_SIZE(device->idx); + } xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); + xfercap_scale &= 0x1f; /* bits [4:0] valid */ xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap); diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index ca11342..137cf87 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -359,7 +359,14 @@ static int ioat2_enumerate_channels(struct ioatdma_device *device) INIT_LIST_HEAD(&dma->channels); dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); + dma->chancnt &= 0x1f; /* bits [4:0] valid */ + if (dma->chancnt > ARRAY_SIZE(device->idx)) { + dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", + dma->chancnt, ARRAY_SIZE(device->idx)); + dma->chancnt = ARRAY_SIZE(device->idx); + } xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET); + xfercap_log &= 0x1f; /* bits [4:0] valid */ if (xfercap_log == 0) return 0; dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log); -- cgit v0.10.2 From f6ab95b55735fa03cad8d0f966647e5df206e207 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 12:01:21 -0700 Subject: ioat: preserve chanctrl bits when re-arming interrupts The register write in ioat_dma_cleanup_tasklet is unfortunate in two ways: 1/ It clears the extra 'enable' bits that we set at alloc_chan_resources time 2/ It gives the impression that it disables interrupts when it is in fact re-arming interrupts [ Impact: fix, persist the value of the chanctrl register when re-arming ] Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 5173ba9..6dd0af1 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -452,7 +452,6 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c) struct ioat_dma_chan *ioat = to_ioat_chan(c); struct ioat_chan_common *chan = &ioat->base; struct ioat_desc_sw *desc; - u16 chanctrl; u32 chanerr; int i; LIST_HEAD(tmp_list); @@ -462,10 +461,7 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c) return ioat->desccount; /* Setup register to interrupt and write completion status on error */ - chanctrl = IOAT_CHANCTRL_ERR_INT_EN | - IOAT_CHANCTRL_ANY_ERR_ABORT_EN | - IOAT_CHANCTRL_ERR_COMPLETION_EN; - writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET); + writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET); chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); if (chanerr) { @@ -672,9 +668,9 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, static void ioat1_cleanup_tasklet(unsigned long data) { struct ioat_dma_chan *chan = (void *)data; + ioat1_cleanup(chan); - writew(IOAT_CHANCTRL_INT_DISABLE, - chan->base.reg_base + IOAT_CHANCTRL_OFFSET); + writew(IOAT_CHANCTRL_RUN, chan->base.reg_base + IOAT_CHANCTRL_OFFSET); } static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 137cf87..2f34f29 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -341,8 +341,7 @@ static void ioat2_cleanup_tasklet(unsigned long data) struct ioat2_dma_chan *ioat = (void *) data; ioat2_cleanup(ioat); - writew(IOAT_CHANCTRL_INT_DISABLE, - ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); + writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); } /** @@ -454,7 +453,6 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c) struct ioat2_dma_chan *ioat = to_ioat2_chan(c); struct ioat_chan_common *chan = &ioat->base; struct ioat_ring_ent **ring; - u16 chanctrl; u32 chanerr; int descs; int i; @@ -464,9 +462,7 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c) return 1 << ioat->alloc_order; /* Setup register to interrupt and write completion status on error */ - chanctrl = IOAT_CHANCTRL_ERR_INT_EN | IOAT_CHANCTRL_ANY_ERR_ABORT_EN | - IOAT_CHANCTRL_ERR_COMPLETION_EN; - writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET); + writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET); chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); if (chanerr) { diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h index a83c733..4380f6f 100644 --- a/drivers/dma/ioat/registers.h +++ b/drivers/dma/ioat/registers.h @@ -75,7 +75,11 @@ #define IOAT_CHANCTRL_ERR_INT_EN 0x0010 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 #define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 -#define IOAT_CHANCTRL_INT_DISABLE 0x0001 +#define IOAT_CHANCTRL_INT_REARM 0x0001 +#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ + IOAT_CHANCTRL_ERR_COMPLETION_EN |\ + IOAT_CHANCTRL_ANY_ERR_ABORT_EN |\ + IOAT_CHANCTRL_ERR_INT_EN) #define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */ #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ -- cgit v0.10.2 From 345d852391cf3fdc73f23a9ca522c6e7b5eb5a52 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 12:01:30 -0700 Subject: ioat: ___devinit annotate the initialization paths Mark all single use initialization routines with __devinit. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dca.c b/drivers/dma/ioat/dca.c index af1c762..69d0261 100644 --- a/drivers/dma/ioat/dca.c +++ b/drivers/dma/ioat/dca.c @@ -242,7 +242,8 @@ static struct dca_ops ioat_dca_ops = { }; -struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase) +struct dca_provider * __devinit +ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase) { struct dca_provider *dca; struct ioat_dca_priv *ioatdca; @@ -407,7 +408,8 @@ static int ioat2_dca_count_dca_slots(void __iomem *iobase, u16 dca_offset) return slots; } -struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase) +struct dca_provider * __devinit +ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase) { struct dca_provider *dca; struct ioat_dca_priv *ioatdca; @@ -602,7 +604,8 @@ static int ioat3_dca_count_dca_slots(void *iobase, u16 dca_offset) return slots; } -struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase) +struct dca_provider * __devinit +ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase) { struct dca_provider *dca; struct ioat_dca_priv *ioatdca; diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 6dd0af1..abc96c4 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -870,7 +870,7 @@ static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat) */ #define IOAT_TEST_SIZE 2000 -static void ioat_dma_test_callback(void *dma_async_param) +static void __devinit ioat_dma_test_callback(void *dma_async_param) { struct completion *cmp = dma_async_param; @@ -881,7 +881,7 @@ static void ioat_dma_test_callback(void *dma_async_param) * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. * @device: device to be tested */ -static int ioat_dma_self_test(struct ioatdma_device *device) +static int __devinit ioat_dma_self_test(struct ioatdma_device *device) { int i; u8 *src; @@ -1082,7 +1082,7 @@ static void ioat_disable_interrupts(struct ioatdma_device *device) writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); } -int ioat_probe(struct ioatdma_device *device) +int __devinit ioat_probe(struct ioatdma_device *device) { int err = -ENODEV; struct dma_device *dma = &device->common; @@ -1142,7 +1142,7 @@ err_dma_pool: return err; } -int ioat_register(struct ioatdma_device *device) +int __devinit ioat_register(struct ioatdma_device *device) { int err = dma_async_device_register(&device->common); @@ -1169,7 +1169,7 @@ static void ioat1_intr_quirk(struct ioatdma_device *device) pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl); } -int ioat1_dma_probe(struct ioatdma_device *device, int dca) +int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca) { struct pci_dev *pdev = device->pdev; struct dma_device *dma; @@ -1200,7 +1200,7 @@ int ioat1_dma_probe(struct ioatdma_device *device, int dca) return err; } -void ioat_dma_remove(struct ioatdma_device *device) +void __devexit ioat_dma_remove(struct ioatdma_device *device) { struct dma_device *dma = &device->common; diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index 5fd6e2d..e47083b 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -217,11 +217,12 @@ ioat_chan_by_index(struct ioatdma_device *device, int index) return device->idx[index]; } -int ioat_probe(struct ioatdma_device *device); -int ioat_register(struct ioatdma_device *device); -int ioat1_dma_probe(struct ioatdma_device *dev, int dca); -void ioat_dma_remove(struct ioatdma_device *device); -struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); +int __devinit ioat_probe(struct ioatdma_device *device); +int __devinit ioat_register(struct ioatdma_device *device); +int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca); +void __devexit ioat_dma_remove(struct ioatdma_device *device); +struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev, + void __iomem *iobase); unsigned long ioat_get_current_completion(struct ioat_chan_common *chan); void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *chan, int idx, diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 2f34f29..1aa2974 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -683,7 +683,7 @@ ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie, return ioat_is_complete(c, cookie, done, used); } -int ioat2_dma_probe(struct ioatdma_device *device, int dca) +int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca) { struct pci_dev *pdev = device->pdev; struct dma_device *dma; @@ -722,7 +722,7 @@ int ioat2_dma_probe(struct ioatdma_device *device, int dca) return err; } -int ioat3_dma_probe(struct ioatdma_device *device, int dca) +int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) { struct pci_dev *pdev = device->pdev; struct dma_device *dma; diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h index c72ccb5..bdde537 100644 --- a/drivers/dma/ioat/dma_v2.h +++ b/drivers/dma/ioat/dma_v2.h @@ -127,8 +127,8 @@ ioat2_get_ring_ent(struct ioat2_dma_chan *ioat, u16 idx) return ioat->ring[idx & ioat2_ring_mask(ioat)]; } -int ioat2_dma_probe(struct ioatdma_device *dev, int dca); -int ioat3_dma_probe(struct ioatdma_device *dev, int dca); -struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); -struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase); +int __devinit ioat2_dma_probe(struct ioatdma_device *dev, int dca); +int __devinit ioat3_dma_probe(struct ioatdma_device *dev, int dca); +struct dca_provider * __devinit ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); +struct dca_provider * __devinit ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase); #endif /* IOATDMA_V2_H */ -- cgit v0.10.2 From ad643f54c8514998333bc6c7b201fda2267496be Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 12:01:38 -0700 Subject: ioat1: trim ioat_dma_desc_sw Save 4 bytes per software descriptor by transmitting tx_cnt in an unused portion of the hardware descriptor. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index abc96c4..f59b6f4 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -396,7 +396,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) dump_desc_dbg(ioat, chain_tail); dump_desc_dbg(ioat, first); - ioat->pending += desc->tx_cnt; + ioat->pending += desc->hw->tx_cnt; if (ioat->pending >= ioat_pending_level) __ioat1_dma_memcpy_issue_pending(ioat); spin_unlock_bh(&ioat->desc_lock); @@ -655,11 +655,11 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, spin_unlock_bh(&ioat->desc_lock); desc->txd.flags = flags; - desc->tx_cnt = tx_cnt; desc->len = total_len; list_splice(&chain, &desc->txd.tx_list); hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); hw->ctl_f.compl_write = 1; + hw->tx_cnt = tx_cnt; dump_desc_dbg(ioat, desc); return &desc->txd; diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index e47083b..ec851cf 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -165,14 +165,12 @@ ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie, * @hw: hardware DMA descriptor * @node: this descriptor will either be on the free list, * or attached to a transaction list (async_tx.tx_list) - * @tx_cnt: number of descriptors required to complete the transaction * @txd: the generic software descriptor for all engines * @id: identifier for debug */ struct ioat_desc_sw { struct ioat_dma_descriptor *hw; struct list_head node; - int tx_cnt; size_t len; struct dma_async_tx_descriptor txd; #ifdef DEBUG diff --git a/drivers/dma/ioat/hw.h b/drivers/dma/ioat/hw.h index e13f3ed4..7481fb1 100644 --- a/drivers/dma/ioat/hw.h +++ b/drivers/dma/ioat/hw.h @@ -63,7 +63,11 @@ struct ioat_dma_descriptor { uint64_t next; uint64_t rsv1; uint64_t rsv2; - uint64_t user1; + /* store some driver data in an unused portion of the descriptor */ + union { + uint64_t user1; + uint64_t tx_cnt; + }; uint64_t user2; }; #endif -- cgit v0.10.2 From 09c8a5b85e5f1e74a19bdd7c85547429d51df1cd Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 12:01:49 -0700 Subject: ioat: switch watchdog and reset handler from workqueue to timer In order to support dynamic resizing of the descriptor ring or polling for a descriptor in the presence of a hung channel the reset handler needs to make progress while in a non-preemptible context. The current workqueue implementation precludes polling channel reset completion under spin_lock(). This conversion also allows us to return to opportunistic cleanup in the ioat2 case as the timer implementation guarantees at least one cleanup after every descriptor is submitted. This means the worst case completion latency becomes the timer frequency (for exceptional circumstances), but with the benefit of avoiding busy waiting when the lock is contended. Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index f59b6f4..17a518d 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -99,23 +99,26 @@ static void ioat1_cleanup_tasklet(unsigned long data); /* common channel initialization */ void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *chan, int idx, - work_func_t work_fn, void (*tasklet)(unsigned long), - unsigned long tasklet_data) + void (*timer_fn)(unsigned long), + void (*tasklet)(unsigned long), + unsigned long ioat) { struct dma_device *dma = &device->common; chan->device = device; chan->reg_base = device->reg_base + (0x80 * (idx + 1)); - INIT_DELAYED_WORK(&chan->work, work_fn); spin_lock_init(&chan->cleanup_lock); chan->common.device = dma; list_add_tail(&chan->common.device_node, &dma->channels); device->idx[idx] = chan; - tasklet_init(&chan->cleanup_task, tasklet, tasklet_data); + init_timer(&chan->timer); + chan->timer.function = timer_fn; + chan->timer.data = ioat; + tasklet_init(&chan->cleanup_task, tasklet, ioat); tasklet_disable(&chan->cleanup_task); } -static void ioat1_reset_part2(struct work_struct *work); +static void ioat1_timer_event(unsigned long data); /** * ioat1_dma_enumerate_channels - find and initialize the device's channels @@ -153,7 +156,7 @@ static int ioat1_enumerate_channels(struct ioatdma_device *device) break; ioat_init_channel(device, &ioat->base, i, - ioat1_reset_part2, + ioat1_timer_event, ioat1_cleanup_tasklet, (unsigned long) ioat); ioat->xfercap = xfercap; @@ -193,61 +196,6 @@ static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan) } /** - * ioat1_reset_part2 - reinit the channel after a reset - */ -static void ioat1_reset_part2(struct work_struct *work) -{ - struct ioat_chan_common *chan; - struct ioat_dma_chan *ioat; - struct ioat_desc_sw *desc; - int dmacount; - bool start_null = false; - - chan = container_of(work, struct ioat_chan_common, work.work); - ioat = container_of(chan, struct ioat_dma_chan, base); - spin_lock_bh(&chan->cleanup_lock); - spin_lock_bh(&ioat->desc_lock); - - *chan->completion = 0; - ioat->pending = 0; - - /* count the descriptors waiting */ - dmacount = 0; - if (ioat->used_desc.prev) { - desc = to_ioat_desc(ioat->used_desc.prev); - do { - dmacount++; - desc = to_ioat_desc(desc->node.next); - } while (&desc->node != ioat->used_desc.next); - } - - if (dmacount) { - /* - * write the new starting descriptor address - * this puts channel engine into ARMED state - */ - desc = to_ioat_desc(ioat->used_desc.prev); - writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, - chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->txd.phys) >> 32, - chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); - - writeb(IOAT_CHANCMD_START, chan->reg_base - + IOAT_CHANCMD_OFFSET(chan->device->version)); - } else - start_null = true; - spin_unlock_bh(&ioat->desc_lock); - spin_unlock_bh(&chan->cleanup_lock); - - dev_err(to_dev(chan), - "chan%d reset - %d descs waiting, %d total desc\n", - chan_num(chan), dmacount, ioat->desccount); - - if (start_null) - ioat1_dma_start_null_desc(ioat); -} - -/** * ioat1_reset_channel - restart a channel * @ioat: IOAT DMA channel handle */ @@ -257,12 +205,9 @@ static void ioat1_reset_channel(struct ioat_dma_chan *ioat) void __iomem *reg_base = chan->reg_base; u32 chansts, chanerr; - if (!ioat->used_desc.prev) - return; - - dev_dbg(to_dev(chan), "%s\n", __func__); + dev_warn(to_dev(chan), "reset\n"); chanerr = readl(reg_base + IOAT_CHANERR_OFFSET); - chansts = *chan->completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS; + chansts = *chan->completion & IOAT_CHANSTS_STATUS; if (chanerr) { dev_err(to_dev(chan), "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", @@ -278,93 +223,11 @@ static void ioat1_reset_channel(struct ioat_dma_chan *ioat) * while we're waiting. */ - spin_lock_bh(&ioat->desc_lock); ioat->pending = INT_MIN; writeb(IOAT_CHANCMD_RESET, reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); - spin_unlock_bh(&ioat->desc_lock); - - /* schedule the 2nd half instead of sleeping a long time */ - schedule_delayed_work(&chan->work, RESET_DELAY); -} - -/** - * ioat1_chan_watchdog - watch for stuck channels - */ -static void ioat1_chan_watchdog(struct work_struct *work) -{ - struct ioatdma_device *device = - container_of(work, struct ioatdma_device, work.work); - struct ioat_dma_chan *ioat; - struct ioat_chan_common *chan; - int i; - u64 completion; - u32 completion_low; - unsigned long compl_desc_addr_hw; - - for (i = 0; i < device->common.chancnt; i++) { - chan = ioat_chan_by_index(device, i); - ioat = container_of(chan, struct ioat_dma_chan, base); - - if (/* have we started processing anything yet */ - chan->last_completion - /* have we completed any since last watchdog cycle? */ - && (chan->last_completion == chan->watchdog_completion) - /* has TCP stuck on one cookie since last watchdog? */ - && (chan->watchdog_tcp_cookie == chan->watchdog_last_tcp_cookie) - && (chan->watchdog_tcp_cookie != chan->completed_cookie) - /* is there something in the chain to be processed? */ - /* CB1 chain always has at least the last one processed */ - && (ioat->used_desc.prev != ioat->used_desc.next) - && ioat->pending == 0) { - - /* - * check CHANSTS register for completed - * descriptor address. - * if it is different than completion writeback, - * it is not zero - * and it has changed since the last watchdog - * we can assume that channel - * is still working correctly - * and the problem is in completion writeback. - * update completion writeback - * with actual CHANSTS value - * else - * try resetting the channel - */ - - /* we need to read the low address first as this - * causes the chipset to latch the upper bits - * for the subsequent read - */ - completion_low = readl(chan->reg_base + - IOAT_CHANSTS_OFFSET_LOW(chan->device->version)); - completion = readl(chan->reg_base + - IOAT_CHANSTS_OFFSET_HIGH(chan->device->version)); - completion <<= 32; - completion |= completion_low; - compl_desc_addr_hw = completion & - IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; - - if ((compl_desc_addr_hw != 0) - && (compl_desc_addr_hw != chan->watchdog_completion) - && (compl_desc_addr_hw != chan->last_compl_desc_addr_hw)) { - chan->last_compl_desc_addr_hw = compl_desc_addr_hw; - *chan->completion = completion; - } else { - ioat1_reset_channel(ioat); - chan->watchdog_completion = 0; - chan->last_compl_desc_addr_hw = 0; - } - } else { - chan->last_compl_desc_addr_hw = 0; - chan->watchdog_completion = chan->last_completion; - } - - chan->watchdog_last_tcp_cookie = chan->watchdog_tcp_cookie; - } - - schedule_delayed_work(&device->work, WATCHDOG_DELAY); + set_bit(IOAT_RESET_PENDING, &chan->state); + mod_timer(&chan->timer, jiffies + RESET_DELAY); } static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) @@ -372,6 +235,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) struct dma_chan *c = tx->chan; struct ioat_dma_chan *ioat = to_ioat_chan(c); struct ioat_desc_sw *desc = tx_to_ioat_desc(tx); + struct ioat_chan_common *chan = &ioat->base; struct ioat_desc_sw *first; struct ioat_desc_sw *chain_tail; dma_cookie_t cookie; @@ -396,6 +260,9 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) dump_desc_dbg(ioat, chain_tail); dump_desc_dbg(ioat, first); + if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state)) + mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); + ioat->pending += desc->hw->tx_cnt; if (ioat->pending >= ioat_pending_level) __ioat1_dma_memcpy_issue_pending(ioat); @@ -520,6 +387,7 @@ static void ioat1_dma_free_chan_resources(struct dma_chan *c) return; tasklet_disable(&chan->cleanup_task); + del_timer_sync(&chan->timer); ioat1_cleanup(ioat); /* Delay 100ms after reset to allow internal DMA logic to quiesce @@ -560,9 +428,6 @@ static void ioat1_dma_free_chan_resources(struct dma_chan *c) chan->last_completion = 0; chan->completion_dma = 0; - chan->watchdog_completion = 0; - chan->last_compl_desc_addr_hw = 0; - chan->watchdog_tcp_cookie = chan->watchdog_last_tcp_cookie = 0; ioat->pending = 0; ioat->desccount = 0; } @@ -705,15 +570,15 @@ unsigned long ioat_get_current_completion(struct ioat_chan_common *chan) u64 completion; completion = *chan->completion; - phys_complete = completion & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; + phys_complete = ioat_chansts_to_addr(completion); dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__, (unsigned long long) phys_complete); - if ((completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == - IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) { + if (is_ioat_halted(completion)) { + u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); dev_err(to_dev(chan), "Channel halted, chanerr = %x\n", - readl(chan->reg_base + IOAT_CHANERR_OFFSET)); + chanerr); /* TODO do something to salvage the situation */ } @@ -721,48 +586,31 @@ unsigned long ioat_get_current_completion(struct ioat_chan_common *chan) return phys_complete; } -/** - * ioat1_cleanup - cleanup up finished descriptors - * @chan: ioat channel to be cleaned up - */ -static void ioat1_cleanup(struct ioat_dma_chan *ioat) +bool ioat_cleanup_preamble(struct ioat_chan_common *chan, + unsigned long *phys_complete) { - struct ioat_chan_common *chan = &ioat->base; - unsigned long phys_complete; - struct ioat_desc_sw *desc, *_desc; - dma_cookie_t cookie = 0; - struct dma_async_tx_descriptor *tx; - - prefetch(chan->completion); - - if (!spin_trylock_bh(&chan->cleanup_lock)) - return; + *phys_complete = ioat_get_current_completion(chan); + if (*phys_complete == chan->last_completion) + return false; + clear_bit(IOAT_COMPLETION_ACK, &chan->state); + mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); - phys_complete = ioat_get_current_completion(chan); - if (phys_complete == chan->last_completion) { - spin_unlock_bh(&chan->cleanup_lock); - /* - * perhaps we're stuck so hard that the watchdog can't go off? - * try to catch it after 2 seconds - */ - if (time_after(jiffies, - chan->last_completion_time + HZ*WATCHDOG_DELAY)) { - ioat1_chan_watchdog(&(chan->device->work.work)); - chan->last_completion_time = jiffies; - } - return; - } - chan->last_completion_time = jiffies; + return true; +} - cookie = 0; - if (!spin_trylock_bh(&ioat->desc_lock)) { - spin_unlock_bh(&chan->cleanup_lock); - return; - } +static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete) +{ + struct ioat_chan_common *chan = &ioat->base; + struct list_head *_desc, *n; + struct dma_async_tx_descriptor *tx; dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n", __func__, phys_complete); - list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { + list_for_each_safe(_desc, n, &ioat->used_desc) { + struct ioat_desc_sw *desc; + + prefetch(n); + desc = list_entry(_desc, typeof(*desc), node); tx = &desc->txd; /* * Incoming DMA requests may use multiple descriptors, @@ -771,7 +619,8 @@ static void ioat1_cleanup(struct ioat_dma_chan *ioat) */ dump_desc_dbg(ioat, desc); if (tx->cookie) { - cookie = tx->cookie; + chan->completed_cookie = tx->cookie; + tx->cookie = 0; ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw); if (tx->callback) { tx->callback(tx->callback_param); @@ -786,27 +635,110 @@ static void ioat1_cleanup(struct ioat_dma_chan *ioat) */ if (async_tx_test_ack(tx)) list_move_tail(&desc->node, &ioat->free_desc); - else - tx->cookie = 0; } else { /* * last used desc. Do not remove, so we can - * append from it, but don't look at it next - * time, either + * append from it. */ - tx->cookie = 0; + + /* if nothing else is pending, cancel the + * completion timeout + */ + if (n == &ioat->used_desc) { + dev_dbg(to_dev(chan), + "%s cancel completion timeout\n", + __func__); + clear_bit(IOAT_COMPLETION_PENDING, &chan->state); + } /* TODO check status bits? */ break; } } + chan->last_completion = phys_complete; +} + +/** + * ioat1_cleanup - cleanup up finished descriptors + * @chan: ioat channel to be cleaned up + * + * To prevent lock contention we defer cleanup when the locks are + * contended with a terminal timeout that forces cleanup and catches + * completion notification errors. + */ +static void ioat1_cleanup(struct ioat_dma_chan *ioat) +{ + struct ioat_chan_common *chan = &ioat->base; + unsigned long phys_complete; + + prefetch(chan->completion); + + if (!spin_trylock_bh(&chan->cleanup_lock)) + return; + + if (!ioat_cleanup_preamble(chan, &phys_complete)) { + spin_unlock_bh(&chan->cleanup_lock); + return; + } + + if (!spin_trylock_bh(&ioat->desc_lock)) { + spin_unlock_bh(&chan->cleanup_lock); + return; + } + + __cleanup(ioat, phys_complete); + spin_unlock_bh(&ioat->desc_lock); + spin_unlock_bh(&chan->cleanup_lock); +} - chan->last_completion = phys_complete; - if (cookie != 0) - chan->completed_cookie = cookie; +static void ioat1_timer_event(unsigned long data) +{ + struct ioat_dma_chan *ioat = (void *) data; + struct ioat_chan_common *chan = &ioat->base; + dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state); + + spin_lock_bh(&chan->cleanup_lock); + if (test_and_clear_bit(IOAT_RESET_PENDING, &chan->state)) { + struct ioat_desc_sw *desc; + + spin_lock_bh(&ioat->desc_lock); + + /* restart active descriptors */ + desc = to_ioat_desc(ioat->used_desc.prev); + ioat_set_chainaddr(ioat, desc->txd.phys); + ioat_start(chan); + + ioat->pending = 0; + set_bit(IOAT_COMPLETION_PENDING, &chan->state); + mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); + spin_unlock_bh(&ioat->desc_lock); + } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) { + unsigned long phys_complete; + + spin_lock_bh(&ioat->desc_lock); + /* if we haven't made progress and we have already + * acknowledged a pending completion once, then be more + * forceful with a restart + */ + if (ioat_cleanup_preamble(chan, &phys_complete)) + __cleanup(ioat, phys_complete); + else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) + ioat1_reset_channel(ioat); + else { + u64 status = ioat_chansts(chan); + + /* manually update the last completion address */ + if (ioat_chansts_to_addr(status) != 0) + *chan->completion = status; + + set_bit(IOAT_COMPLETION_ACK, &chan->state); + mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); + } + spin_unlock_bh(&ioat->desc_lock); + } spin_unlock_bh(&chan->cleanup_lock); } @@ -855,13 +787,8 @@ static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat) list_add_tail(&desc->node, &ioat->used_desc); dump_desc_dbg(ioat, desc); - writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, - chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->txd.phys) >> 32, - chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); - - writeb(IOAT_CHANCMD_START, chan->reg_base - + IOAT_CHANCMD_OFFSET(chan->device->version)); + ioat_set_chainaddr(ioat, desc->txd.phys); + ioat_start(chan); spin_unlock_bh(&ioat->desc_lock); } @@ -1194,9 +1121,6 @@ int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca) if (dca) device->dca = ioat_dca_init(pdev, device->reg_base); - INIT_DELAYED_WORK(&device->work, ioat1_chan_watchdog); - schedule_delayed_work(&device->work, WATCHDOG_DELAY); - return err; } @@ -1204,9 +1128,6 @@ void __devexit ioat_dma_remove(struct ioatdma_device *device) { struct dma_device *dma = &device->common; - if (device->version != IOAT_VER_3_0) - cancel_delayed_work(&device->work); - ioat_disable_interrupts(device); dma_async_device_unregister(dma); diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index ec851cf..dbfccac 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -23,6 +23,7 @@ #include #include "hw.h" +#include "registers.h" #include #include #include @@ -33,7 +34,6 @@ #define IOAT_LOW_COMPLETION_MASK 0xffffffc0 #define IOAT_DMA_DCA_ANY_CPU ~0 -#define IOAT_WATCHDOG_PERIOD (2 * HZ) #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common) #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node) @@ -42,9 +42,6 @@ #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80) -#define RESET_DELAY msecs_to_jiffies(100) -#define WATCHDOG_DELAY round_jiffies(msecs_to_jiffies(2000)) - /* * workaround for IOAT ver.3.0 null descriptor issue * (channel returns error when size is 0) @@ -72,7 +69,6 @@ struct ioatdma_device { struct pci_pool *completion_pool; struct dma_device common; u8 version; - struct delayed_work work; struct msix_entry msix_entries[4]; struct ioat_chan_common *idx[4]; struct dca_provider *dca; @@ -81,24 +77,21 @@ struct ioatdma_device { }; struct ioat_chan_common { + struct dma_chan common; void __iomem *reg_base; - unsigned long last_completion; - unsigned long last_completion_time; - spinlock_t cleanup_lock; dma_cookie_t completed_cookie; - unsigned long watchdog_completion; - int watchdog_tcp_cookie; - u32 watchdog_last_tcp_cookie; - struct delayed_work work; - + unsigned long state; + #define IOAT_COMPLETION_PENDING 0 + #define IOAT_COMPLETION_ACK 1 + #define IOAT_RESET_PENDING 2 + struct timer_list timer; + #define COMPLETION_TIMEOUT msecs_to_jiffies(100) + #define RESET_DELAY msecs_to_jiffies(100) struct ioatdma_device *device; - struct dma_chan common; - dma_addr_t completion_dma; u64 *completion; - unsigned long last_compl_desc_addr_hw; struct tasklet_struct cleanup_task; }; @@ -148,7 +141,6 @@ ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie, last_used = c->cookie; last_complete = chan->completed_cookie; - chan->watchdog_tcp_cookie = cookie; if (done) *done = last_complete; @@ -215,6 +207,85 @@ ioat_chan_by_index(struct ioatdma_device *device, int index) return device->idx[index]; } +static inline u64 ioat_chansts(struct ioat_chan_common *chan) +{ + u8 ver = chan->device->version; + u64 status; + u32 status_lo; + + /* We need to read the low address first as this causes the + * chipset to latch the upper bits for the subsequent read + */ + status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); + status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); + status <<= 32; + status |= status_lo; + + return status; +} + +static inline void ioat_start(struct ioat_chan_common *chan) +{ + u8 ver = chan->device->version; + + writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); +} + +static inline u64 ioat_chansts_to_addr(u64 status) +{ + return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; +} + +static inline u32 ioat_chanerr(struct ioat_chan_common *chan) +{ + return readl(chan->reg_base + IOAT_CHANERR_OFFSET); +} + +static inline void ioat_suspend(struct ioat_chan_common *chan) +{ + u8 ver = chan->device->version; + + writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); +} + +static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr) +{ + struct ioat_chan_common *chan = &ioat->base; + + writel(addr & 0x00000000FFFFFFFF, + chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); + writel(addr >> 32, + chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); +} + +static inline bool is_ioat_active(unsigned long status) +{ + return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE); +} + +static inline bool is_ioat_idle(unsigned long status) +{ + return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE); +} + +static inline bool is_ioat_halted(unsigned long status) +{ + return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED); +} + +static inline bool is_ioat_suspended(unsigned long status) +{ + return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED); +} + +/* channel was fatally programmed */ +static inline bool is_ioat_bug(unsigned long err) +{ + return !!(err & (IOAT_CHANERR_SRC_ADDR_ERR|IOAT_CHANERR_DEST_ADDR_ERR| + IOAT_CHANERR_NEXT_ADDR_ERR|IOAT_CHANERR_CONTROL_ERR| + IOAT_CHANERR_LENGTH_ERR)); +} + int __devinit ioat_probe(struct ioatdma_device *device); int __devinit ioat_register(struct ioatdma_device *device); int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca); @@ -224,8 +295,11 @@ struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev, unsigned long ioat_get_current_completion(struct ioat_chan_common *chan); void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *chan, int idx, - work_func_t work_fn, void (*tasklet)(unsigned long), - unsigned long tasklet_data); + void (*timer_fn)(unsigned long), + void (*tasklet)(unsigned long), + unsigned long ioat); void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, size_t len, struct ioat_dma_descriptor *hw); +bool ioat_cleanup_preamble(struct ioat_chan_common *chan, + unsigned long *phys_complete); #endif /* IOATDMA_H */ diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 1aa2974..72e59a0 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -49,7 +49,7 @@ static void __ioat2_issue_pending(struct ioat2_dma_chan *ioat) void * __iomem reg_base = ioat->base.reg_base; ioat->pending = 0; - ioat->dmacount += ioat2_ring_pending(ioat); + ioat->dmacount += ioat2_ring_pending(ioat);; ioat->issued = ioat->head; /* make descriptor updates globally visible before notifying channel */ wmb(); @@ -92,7 +92,6 @@ static void ioat2_update_pending(struct ioat2_dma_chan *ioat) static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat) { - void __iomem *reg_base = ioat->base.reg_base; struct ioat_ring_ent *desc; struct ioat_dma_descriptor *hw; int idx; @@ -118,10 +117,7 @@ static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat) hw->src_addr = 0; hw->dst_addr = 0; async_tx_ack(&desc->txd); - writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, - reg_base + IOAT2_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->txd.phys) >> 32, - reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); + ioat2_set_chainaddr(ioat, desc->txd.phys); dump_desc_dbg(ioat, desc); __ioat2_issue_pending(ioat); } @@ -133,177 +129,14 @@ static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat) spin_unlock_bh(&ioat->ring_lock); } -static void ioat2_cleanup(struct ioat2_dma_chan *ioat); - -/** - * ioat2_reset_part2 - reinit the channel after a reset - */ -static void ioat2_reset_part2(struct work_struct *work) -{ - struct ioat_chan_common *chan; - struct ioat2_dma_chan *ioat; - - chan = container_of(work, struct ioat_chan_common, work.work); - ioat = container_of(chan, struct ioat2_dma_chan, base); - - /* ensure that ->tail points to the stalled descriptor - * (ioat->pending is set to 2 at this point so no new - * descriptors will be issued while we perform this cleanup) - */ - ioat2_cleanup(ioat); - - spin_lock_bh(&chan->cleanup_lock); - spin_lock_bh(&ioat->ring_lock); - - /* set the tail to be re-issued */ - ioat->issued = ioat->tail; - ioat->dmacount = 0; - - dev_dbg(to_dev(&ioat->base), - "%s: head: %#x tail: %#x issued: %#x count: %#x\n", - __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount); - - if (ioat2_ring_pending(ioat)) { - struct ioat_ring_ent *desc; - - desc = ioat2_get_ring_ent(ioat, ioat->tail); - writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, - chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); - writel(((u64) desc->txd.phys) >> 32, - chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); - __ioat2_issue_pending(ioat); - } else - __ioat2_start_null_desc(ioat); - - spin_unlock_bh(&ioat->ring_lock); - spin_unlock_bh(&chan->cleanup_lock); - - dev_info(to_dev(chan), - "chan%d reset - %d descs waiting, %d total desc\n", - chan_num(chan), ioat->dmacount, 1 << ioat->alloc_order); -} - -/** - * ioat2_reset_channel - restart a channel - * @ioat: IOAT DMA channel handle - */ -static void ioat2_reset_channel(struct ioat2_dma_chan *ioat) +static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) { - u32 chansts, chanerr; struct ioat_chan_common *chan = &ioat->base; - u16 active; - - spin_lock_bh(&ioat->ring_lock); - active = ioat2_ring_active(ioat); - spin_unlock_bh(&ioat->ring_lock); - if (!active) - return; - - chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); - chansts = *chan->completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS; - if (chanerr) { - dev_err(to_dev(chan), - "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", - chan_num(chan), chansts, chanerr); - writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); - } - - spin_lock_bh(&ioat->ring_lock); - ioat->pending = 2; - writeb(IOAT_CHANCMD_RESET, - chan->reg_base - + IOAT_CHANCMD_OFFSET(chan->device->version)); - spin_unlock_bh(&ioat->ring_lock); - schedule_delayed_work(&chan->work, RESET_DELAY); -} - -/** - * ioat2_chan_watchdog - watch for stuck channels - */ -static void ioat2_chan_watchdog(struct work_struct *work) -{ - struct ioatdma_device *device = - container_of(work, struct ioatdma_device, work.work); - struct ioat2_dma_chan *ioat; - struct ioat_chan_common *chan; - u16 active; - int i; - - dev_dbg(&device->pdev->dev, "%s\n", __func__); - - for (i = 0; i < device->common.chancnt; i++) { - chan = ioat_chan_by_index(device, i); - ioat = container_of(chan, struct ioat2_dma_chan, base); - - /* - * for version 2.0 if there are descriptors yet to be processed - * and the last completed hasn't changed since the last watchdog - * if they haven't hit the pending level - * issue the pending to push them through - * else - * try resetting the channel - */ - spin_lock_bh(&ioat->ring_lock); - active = ioat2_ring_active(ioat); - spin_unlock_bh(&ioat->ring_lock); - - if (active && - chan->last_completion && - chan->last_completion == chan->watchdog_completion) { - - if (ioat->pending == 1) - ioat2_issue_pending(&chan->common); - else { - ioat2_reset_channel(ioat); - chan->watchdog_completion = 0; - } - } else { - chan->last_compl_desc_addr_hw = 0; - chan->watchdog_completion = chan->last_completion; - } - chan->watchdog_last_tcp_cookie = chan->watchdog_tcp_cookie; - } - schedule_delayed_work(&device->work, WATCHDOG_DELAY); -} - -/** - * ioat2_cleanup - clean finished descriptors (advance tail pointer) - * @chan: ioat channel to be cleaned up - */ -static void ioat2_cleanup(struct ioat2_dma_chan *ioat) -{ - struct ioat_chan_common *chan = &ioat->base; - unsigned long phys_complete; + struct dma_async_tx_descriptor *tx; struct ioat_ring_ent *desc; bool seen_current = false; u16 active; int i; - struct dma_async_tx_descriptor *tx; - - prefetch(chan->completion); - - spin_lock_bh(&chan->cleanup_lock); - phys_complete = ioat_get_current_completion(chan); - if (phys_complete == chan->last_completion) { - spin_unlock_bh(&chan->cleanup_lock); - /* - * perhaps we're stuck so hard that the watchdog can't go off? - * try to catch it after WATCHDOG_DELAY seconds - */ - if (chan->device->version < IOAT_VER_3_0) { - unsigned long tmo; - - tmo = chan->last_completion_time + HZ*WATCHDOG_DELAY; - if (time_after(jiffies, tmo)) { - ioat2_chan_watchdog(&(chan->device->work.work)); - chan->last_completion_time = jiffies; - } - } - return; - } - chan->last_completion_time = jiffies; - - spin_lock_bh(&ioat->ring_lock); dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n", __func__, ioat->head, ioat->tail, ioat->issued); @@ -329,10 +162,42 @@ static void ioat2_cleanup(struct ioat2_dma_chan *ioat) } ioat->tail += i; BUG_ON(!seen_current); /* no active descs have written a completion? */ - spin_unlock_bh(&ioat->ring_lock); chan->last_completion = phys_complete; + if (ioat->head == ioat->tail) { + dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", + __func__); + clear_bit(IOAT_COMPLETION_PENDING, &chan->state); + } +} + +/** + * ioat2_cleanup - clean finished descriptors (advance tail pointer) + * @chan: ioat channel to be cleaned up + */ +static void ioat2_cleanup(struct ioat2_dma_chan *ioat) +{ + struct ioat_chan_common *chan = &ioat->base; + unsigned long phys_complete; + prefetch(chan->completion); + + if (!spin_trylock_bh(&chan->cleanup_lock)) + return; + + if (!ioat_cleanup_preamble(chan, &phys_complete)) { + spin_unlock_bh(&chan->cleanup_lock); + return; + } + + if (!spin_trylock_bh(&ioat->ring_lock)) { + spin_unlock_bh(&chan->cleanup_lock); + return; + } + + __cleanup(ioat, phys_complete); + + spin_unlock_bh(&ioat->ring_lock); spin_unlock_bh(&chan->cleanup_lock); } @@ -344,6 +209,90 @@ static void ioat2_cleanup_tasklet(unsigned long data) writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); } +static void __restart_chan(struct ioat2_dma_chan *ioat) +{ + struct ioat_chan_common *chan = &ioat->base; + + /* set the tail to be re-issued */ + ioat->issued = ioat->tail; + ioat->dmacount = 0; + set_bit(IOAT_COMPLETION_PENDING, &chan->state); + mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); + + dev_dbg(to_dev(chan), + "%s: head: %#x tail: %#x issued: %#x count: %#x\n", + __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount); + + if (ioat2_ring_pending(ioat)) { + struct ioat_ring_ent *desc; + + desc = ioat2_get_ring_ent(ioat, ioat->tail); + ioat2_set_chainaddr(ioat, desc->txd.phys); + __ioat2_issue_pending(ioat); + } else + __ioat2_start_null_desc(ioat); +} + +static void ioat2_restart_channel(struct ioat2_dma_chan *ioat) +{ + struct ioat_chan_common *chan = &ioat->base; + unsigned long phys_complete; + u32 status; + + status = ioat_chansts(chan); + if (is_ioat_active(status) || is_ioat_idle(status)) + ioat_suspend(chan); + while (is_ioat_active(status) || is_ioat_idle(status)) { + status = ioat_chansts(chan); + cpu_relax(); + } + + if (ioat_cleanup_preamble(chan, &phys_complete)) + __cleanup(ioat, phys_complete); + + __restart_chan(ioat); +} + +static void ioat2_timer_event(unsigned long data) +{ + struct ioat2_dma_chan *ioat = (void *) data; + struct ioat_chan_common *chan = &ioat->base; + + spin_lock_bh(&chan->cleanup_lock); + if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) { + unsigned long phys_complete; + u64 status; + + spin_lock_bh(&ioat->ring_lock); + status = ioat_chansts(chan); + + /* when halted due to errors check for channel + * programming errors before advancing the completion state + */ + if (is_ioat_halted(status)) { + u32 chanerr; + + chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); + BUG_ON(is_ioat_bug(chanerr)); + } + + /* if we haven't made progress and we have already + * acknowledged a pending completion once, then be more + * forceful with a restart + */ + if (ioat_cleanup_preamble(chan, &phys_complete)) + __cleanup(ioat, phys_complete); + else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) + ioat2_restart_channel(ioat); + else { + set_bit(IOAT_COMPLETION_ACK, &chan->state); + mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); + } + spin_unlock_bh(&ioat->ring_lock); + } + spin_unlock_bh(&chan->cleanup_lock); +} + /** * ioat2_enumerate_channels - find and initialize the device's channels * @device: the device to be enumerated @@ -381,7 +330,7 @@ static int ioat2_enumerate_channels(struct ioatdma_device *device) break; ioat_init_channel(device, &ioat->base, i, - ioat2_reset_part2, + ioat2_timer_event, ioat2_cleanup_tasklet, (unsigned long) ioat); ioat->xfercap_log = xfercap_log; @@ -395,6 +344,7 @@ static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx) { struct dma_chan *c = tx->chan; struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + struct ioat_chan_common *chan = &ioat->base; dma_cookie_t cookie = c->cookie; cookie++; @@ -404,6 +354,8 @@ static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx) c->cookie = cookie; dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie); + if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state)) + mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); ioat2_update_pending(ioat); spin_unlock_bh(&ioat->ring_lock); @@ -543,9 +495,18 @@ static int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_d ioat->issued); spin_unlock_bh(&ioat->ring_lock); - /* do direct reclaim in the allocation failure case */ - ioat2_cleanup(ioat); - + /* progress reclaim in the allocation failure case we + * may be called under bh_disabled so we need to trigger + * the timer event directly + */ + spin_lock_bh(&chan->cleanup_lock); + if (jiffies > chan->timer.expires && + timer_pending(&chan->timer)) { + mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); + spin_unlock_bh(&chan->cleanup_lock); + ioat2_timer_event((unsigned long) ioat); + } else + spin_unlock_bh(&chan->cleanup_lock); return -ENOMEM; } @@ -624,6 +585,7 @@ static void ioat2_free_chan_resources(struct dma_chan *c) return; tasklet_disable(&chan->cleanup_task); + del_timer_sync(&chan->timer); ioat2_cleanup(ioat); /* Delay 100ms after reset to allow internal DMA logic to quiesce @@ -663,10 +625,6 @@ static void ioat2_free_chan_resources(struct dma_chan *c) chan->completion_dma = 0; ioat->pending = 0; ioat->dmacount = 0; - chan->watchdog_completion = 0; - chan->last_compl_desc_addr_hw = 0; - chan->watchdog_tcp_cookie = 0; - chan->watchdog_last_tcp_cookie = 0; } static enum dma_status @@ -716,9 +674,6 @@ int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca) if (dca) device->dca = ioat2_dca_init(pdev, device->reg_base); - INIT_DELAYED_WORK(&device->work, ioat2_chan_watchdog); - schedule_delayed_work(&device->work, WATCHDOG_DELAY); - return err; } diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h index bdde537..73b04a2 100644 --- a/drivers/dma/ioat/dma_v2.h +++ b/drivers/dma/ioat/dma_v2.h @@ -127,6 +127,16 @@ ioat2_get_ring_ent(struct ioat2_dma_chan *ioat, u16 idx) return ioat->ring[idx & ioat2_ring_mask(ioat)]; } +static inline void ioat2_set_chainaddr(struct ioat2_dma_chan *ioat, u64 addr) +{ + struct ioat_chan_common *chan = &ioat->base; + + writel(addr & 0x00000000FFFFFFFF, + chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); + writel(addr >> 32, + chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); +} + int __devinit ioat2_dma_probe(struct ioatdma_device *dev, int dca); int __devinit ioat3_dma_probe(struct ioatdma_device *dev, int dca); struct dca_provider * __devinit ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h index 4380f6f..e4334a1 100644 --- a/drivers/dma/ioat/registers.h +++ b/drivers/dma/ioat/registers.h @@ -101,11 +101,11 @@ #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) #define IOAT_CHANSTS_SOFT_ERR 0x10ULL #define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL -#define IOAT_CHANSTS_DMA_TRANSFER_STATUS 0x7ULL -#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE 0x0 -#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE 0x1 -#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_SUSPENDED 0x2 -#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED 0x3 +#define IOAT_CHANSTS_STATUS 0x7ULL +#define IOAT_CHANSTS_ACTIVE 0x0 +#define IOAT_CHANSTS_DONE 0x1 +#define IOAT_CHANSTS_SUSPENDED 0x2 +#define IOAT_CHANSTS_HALTED 0x3 @@ -208,18 +208,18 @@ #define IOAT_CDAR_OFFSET_HIGH 0x24 #define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */ -#define IOAT_CHANERR_DMA_TRANSFER_SRC_ADDR_ERR 0x0001 -#define IOAT_CHANERR_DMA_TRANSFER_DEST_ADDR_ERR 0x0002 -#define IOAT_CHANERR_NEXT_DESCRIPTOR_ADDR_ERR 0x0004 -#define IOAT_CHANERR_NEXT_DESCRIPTOR_ALIGNMENT_ERR 0x0008 +#define IOAT_CHANERR_SRC_ADDR_ERR 0x0001 +#define IOAT_CHANERR_DEST_ADDR_ERR 0x0002 +#define IOAT_CHANERR_NEXT_ADDR_ERR 0x0004 +#define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR 0x0008 #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010 #define IOAT_CHANERR_CHANCMD_ERR 0x0020 #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040 #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080 #define IOAT_CHANERR_READ_DATA_ERR 0x0100 #define IOAT_CHANERR_WRITE_DATA_ERR 0x0200 -#define IOAT_CHANERR_DESCRIPTOR_CONTROL_ERR 0x0400 -#define IOAT_CHANERR_DESCRIPTOR_LENGTH_ERR 0x0800 +#define IOAT_CHANERR_CONTROL_ERR 0x0400 +#define IOAT_CHANERR_LENGTH_ERR 0x0800 #define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000 #define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000 #define IOAT_CHANERR_SOFT_ERR 0x4000 diff --git a/drivers/idle/i7300_idle.c b/drivers/idle/i7300_idle.c index f2ec724..1f20a04 100644 --- a/drivers/idle/i7300_idle.c +++ b/drivers/idle/i7300_idle.c @@ -126,9 +126,9 @@ static void i7300_idle_ioat_stop(void) udelay(10); sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) & - IOAT_CHANSTS_DMA_TRANSFER_STATUS; + IOAT_CHANSTS_STATUS; - if (sts != IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE) + if (sts != IOAT_CHANSTS_ACTIVE) break; } @@ -160,9 +160,9 @@ static int __init i7300_idle_ioat_selftest(u8 *ctl, udelay(1000); chan_sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) & - IOAT_CHANSTS_DMA_TRANSFER_STATUS; + IOAT_CHANSTS_STATUS; - if (chan_sts != IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE) { + if (chan_sts != IOAT_CHANSTS_DONE) { /* Not complete, reset the channel */ writeb(IOAT_CHANCMD_RESET, ioat_chanbase + IOAT1_CHANCMD_OFFSET); @@ -288,9 +288,9 @@ static void __exit i7300_idle_ioat_exit(void) ioat_chanbase + IOAT1_CHANCMD_OFFSET); chan_sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) & - IOAT_CHANSTS_DMA_TRANSFER_STATUS; + IOAT_CHANSTS_STATUS; - if (chan_sts != IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE) { + if (chan_sts != IOAT_CHANSTS_ACTIVE) { writew(0, ioat_chanbase + IOAT_CHANCTRL_OFFSET); break; } @@ -298,14 +298,14 @@ static void __exit i7300_idle_ioat_exit(void) } chan_sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) & - IOAT_CHANSTS_DMA_TRANSFER_STATUS; + IOAT_CHANSTS_STATUS; /* * We tried to reset multiple times. If IO A/T channel is still active * flag an error and return without cleanup. Memory leak is better * than random corruption in that extreme error situation. */ - if (chan_sts == IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE) { + if (chan_sts == IOAT_CHANSTS_ACTIVE) { printk(KERN_ERR I7300_PRINT "Unable to stop IO A/T channels." " Not freeing resources\n"); return; -- cgit v0.10.2 From a309218acee8606f7e235da20cc826eb06d9b0f6 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 12:02:01 -0700 Subject: ioat2,3: dynamically resize descriptor ring Increment the allocation order of the descriptor ring every time we run out of descriptors up to a maximum of allocation order specified by the module parameter 'ioat_max_alloc_order'. After each idle period decrement the allocation order to a minimum order of 'ioat_ring_alloc_order' (i.e. the default ring size, tunable as a module parameter). Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index dbfccac..d9d6a7e 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -88,6 +88,7 @@ struct ioat_chan_common { #define IOAT_RESET_PENDING 2 struct timer_list timer; #define COMPLETION_TIMEOUT msecs_to_jiffies(100) + #define IDLE_TIMEOUT msecs_to_jiffies(2000) #define RESET_DELAY msecs_to_jiffies(100) struct ioatdma_device *device; dma_addr_t completion_dma; diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 72e59a0..460b773 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -43,6 +43,10 @@ static int ioat_ring_alloc_order = 8; module_param(ioat_ring_alloc_order, int, 0644); MODULE_PARM_DESC(ioat_ring_alloc_order, "ioat2+: allocate 2^n descriptors per channel (default: n=8)"); +static int ioat_ring_max_alloc_order = IOAT_MAX_ORDER; +module_param(ioat_ring_max_alloc_order, int, 0644); +MODULE_PARM_DESC(ioat_ring_max_alloc_order, + "ioat2+: upper limit for dynamic ring resizing (default: n=16)"); static void __ioat2_issue_pending(struct ioat2_dma_chan *ioat) { @@ -168,6 +172,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", __func__); clear_bit(IOAT_COMPLETION_PENDING, &chan->state); + mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); } } @@ -253,6 +258,8 @@ static void ioat2_restart_channel(struct ioat2_dma_chan *ioat) __restart_chan(ioat); } +static bool reshape_ring(struct ioat2_dma_chan *ioat, int order); + static void ioat2_timer_event(unsigned long data) { struct ioat2_dma_chan *ioat = (void *) data; @@ -289,6 +296,23 @@ static void ioat2_timer_event(unsigned long data) mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); } spin_unlock_bh(&ioat->ring_lock); + } else { + u16 active; + + /* if the ring is idle, empty, and oversized try to step + * down the size + */ + spin_lock_bh(&ioat->ring_lock); + active = ioat2_ring_active(ioat); + if (active == 0 && ioat->alloc_order > ioat_get_alloc_order()) + reshape_ring(ioat, ioat->alloc_order-1); + spin_unlock_bh(&ioat->ring_lock); + + /* keep shrinking until we get back to our minimum + * default size + */ + if (ioat->alloc_order > ioat_get_alloc_order()) + mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); } spin_unlock_bh(&chan->cleanup_lock); } @@ -362,7 +386,7 @@ static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx) return cookie; } -static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan) +static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan, gfp_t flags) { struct ioat_dma_descriptor *hw; struct ioat_ring_ent *desc; @@ -370,12 +394,12 @@ static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan) dma_addr_t phys; dma = to_ioatdma_device(chan->device); - hw = pci_pool_alloc(dma->dma_pool, GFP_KERNEL, &phys); + hw = pci_pool_alloc(dma->dma_pool, flags, &phys); if (!hw) return NULL; memset(hw, 0, sizeof(*hw)); - desc = kzalloc(sizeof(*desc), GFP_KERNEL); + desc = kzalloc(sizeof(*desc), flags); if (!desc) { pci_pool_free(dma->dma_pool, hw, phys); return NULL; @@ -397,6 +421,42 @@ static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *cha kfree(desc); } +static struct ioat_ring_ent **ioat2_alloc_ring(struct dma_chan *c, int order, gfp_t flags) +{ + struct ioat_ring_ent **ring; + int descs = 1 << order; + int i; + + if (order > ioat_get_max_alloc_order()) + return NULL; + + /* allocate the array to hold the software ring */ + ring = kcalloc(descs, sizeof(*ring), flags); + if (!ring) + return NULL; + for (i = 0; i < descs; i++) { + ring[i] = ioat2_alloc_ring_ent(c, flags); + if (!ring[i]) { + while (i--) + ioat2_free_ring_ent(ring[i], c); + kfree(ring); + return NULL; + } + set_desc_id(ring[i], i); + } + + /* link descs */ + for (i = 0; i < descs-1; i++) { + struct ioat_ring_ent *next = ring[i+1]; + struct ioat_dma_descriptor *hw = ring[i]->hw; + + hw->next = next->txd.phys; + } + ring[i]->hw->next = ring[0]->txd.phys; + + return ring; +} + /* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring * @chan: channel to be initialized */ @@ -406,8 +466,7 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c) struct ioat_chan_common *chan = &ioat->base; struct ioat_ring_ent **ring; u32 chanerr; - int descs; - int i; + int order; /* have we already been set up? */ if (ioat->ring) @@ -435,32 +494,10 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c) writel(((u64) chan->completion_dma) >> 32, chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); - ioat->alloc_order = ioat_get_alloc_order(); - descs = 1 << ioat->alloc_order; - - /* allocate the array to hold the software ring */ - ring = kcalloc(descs, sizeof(*ring), GFP_KERNEL); + order = ioat_get_alloc_order(); + ring = ioat2_alloc_ring(c, order, GFP_KERNEL); if (!ring) return -ENOMEM; - for (i = 0; i < descs; i++) { - ring[i] = ioat2_alloc_ring_ent(c); - if (!ring[i]) { - while (i--) - ioat2_free_ring_ent(ring[i], c); - kfree(ring); - return -ENOMEM; - } - set_desc_id(ring[i], i); - } - - /* link descs */ - for (i = 0; i < descs-1; i++) { - struct ioat_ring_ent *next = ring[i+1]; - struct ioat_dma_descriptor *hw = ring[i]->hw; - - hw->next = next->txd.phys; - } - ring[i]->hw->next = ring[0]->txd.phys; spin_lock_bh(&ioat->ring_lock); ioat->ring = ring; @@ -468,12 +505,120 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c) ioat->issued = 0; ioat->tail = 0; ioat->pending = 0; + ioat->alloc_order = order; spin_unlock_bh(&ioat->ring_lock); tasklet_enable(&chan->cleanup_task); ioat2_start_null_desc(ioat); - return descs; + return 1 << ioat->alloc_order; +} + +static bool reshape_ring(struct ioat2_dma_chan *ioat, int order) +{ + /* reshape differs from normal ring allocation in that we want + * to allocate a new software ring while only + * extending/truncating the hardware ring + */ + struct ioat_chan_common *chan = &ioat->base; + struct dma_chan *c = &chan->common; + const u16 curr_size = ioat2_ring_mask(ioat) + 1; + const u16 active = ioat2_ring_active(ioat); + const u16 new_size = 1 << order; + struct ioat_ring_ent **ring; + u16 i; + + if (order > ioat_get_max_alloc_order()) + return false; + + /* double check that we have at least 1 free descriptor */ + if (active == curr_size) + return false; + + /* when shrinking, verify that we can hold the current active + * set in the new ring + */ + if (active >= new_size) + return false; + + /* allocate the array to hold the software ring */ + ring = kcalloc(new_size, sizeof(*ring), GFP_NOWAIT); + if (!ring) + return false; + + /* allocate/trim descriptors as needed */ + if (new_size > curr_size) { + /* copy current descriptors to the new ring */ + for (i = 0; i < curr_size; i++) { + u16 curr_idx = (ioat->tail+i) & (curr_size-1); + u16 new_idx = (ioat->tail+i) & (new_size-1); + + ring[new_idx] = ioat->ring[curr_idx]; + set_desc_id(ring[new_idx], new_idx); + } + + /* add new descriptors to the ring */ + for (i = curr_size; i < new_size; i++) { + u16 new_idx = (ioat->tail+i) & (new_size-1); + + ring[new_idx] = ioat2_alloc_ring_ent(c, GFP_NOWAIT); + if (!ring[new_idx]) { + while (i--) { + u16 new_idx = (ioat->tail+i) & (new_size-1); + + ioat2_free_ring_ent(ring[new_idx], c); + } + kfree(ring); + return false; + } + set_desc_id(ring[new_idx], new_idx); + } + + /* hw link new descriptors */ + for (i = curr_size-1; i < new_size; i++) { + u16 new_idx = (ioat->tail+i) & (new_size-1); + struct ioat_ring_ent *next = ring[(new_idx+1) & (new_size-1)]; + struct ioat_dma_descriptor *hw = ring[new_idx]->hw; + + hw->next = next->txd.phys; + } + } else { + struct ioat_dma_descriptor *hw; + struct ioat_ring_ent *next; + + /* copy current descriptors to the new ring, dropping the + * removed descriptors + */ + for (i = 0; i < new_size; i++) { + u16 curr_idx = (ioat->tail+i) & (curr_size-1); + u16 new_idx = (ioat->tail+i) & (new_size-1); + + ring[new_idx] = ioat->ring[curr_idx]; + set_desc_id(ring[new_idx], new_idx); + } + + /* free deleted descriptors */ + for (i = new_size; i < curr_size; i++) { + struct ioat_ring_ent *ent; + + ent = ioat2_get_ring_ent(ioat, ioat->tail+i); + ioat2_free_ring_ent(ent, c); + } + + /* fix up hardware ring */ + hw = ring[(ioat->tail+new_size-1) & (new_size-1)]->hw; + next = ring[(ioat->tail+new_size) & (new_size-1)]; + hw->next = next->txd.phys; + } + + dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n", + __func__, new_size); + + kfree(ioat->ring); + ioat->ring = ring; + ioat->alloc_order = order; + + return true; } /** @@ -487,7 +632,15 @@ static int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_d struct ioat_chan_common *chan = &ioat->base; spin_lock_bh(&ioat->ring_lock); - if (unlikely(ioat2_ring_space(ioat) < num_descs)) { + /* never allow the last descriptor to be consumed, we need at + * least one free at all times to allow for on-the-fly ring + * resizing. + */ + while (unlikely(ioat2_ring_space(ioat) <= num_descs)) { + if (reshape_ring(ioat, ioat->alloc_order + 1) && + ioat2_ring_space(ioat) > num_descs) + break; + if (printk_ratelimit()) dev_dbg(to_dev(chan), "%s: ring full! num_descs: %d (%x:%x:%x)\n", diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h index 73b04a2..9baa3d6 100644 --- a/drivers/dma/ioat/dma_v2.h +++ b/drivers/dma/ioat/dma_v2.h @@ -37,6 +37,8 @@ extern int ioat_pending_level; #define IOAT_MAX_ORDER 16 #define ioat_get_alloc_order() \ (min(ioat_ring_alloc_order, IOAT_MAX_ORDER)) +#define ioat_get_max_alloc_order() \ + (min(ioat_ring_max_alloc_order, IOAT_MAX_ORDER)) /* struct ioat2_dma_chan - ioat v2 / v3 channel attributes * @base: common ioat channel parameters -- cgit v0.10.2 From 4b652f0db3be891c7b76b109c3b55003b920fc96 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 12:02:15 -0700 Subject: net_dma: poll for a descriptor after allocation failure Handle descriptor allocation failures by polling for a descriptor. The driver will force forward progress when polled. In the best case this polling interval will be the time it takes for one dma memcpy transaction to complete. In the worst case, channel hang, we will need to wait 100ms for the cleanup watchdog to fire (ioatdma driver). Signed-off-by: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/iovlock.c b/drivers/dma/iovlock.c index 9f6fe46..c0a272c7 100644 --- a/drivers/dma/iovlock.c +++ b/drivers/dma/iovlock.c @@ -183,6 +183,11 @@ dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, iov_byte_offset, kdata, copy); + /* poll for a descriptor slot */ + if (unlikely(dma_cookie < 0)) { + dma_async_issue_pending(chan); + continue; + } len -= copy; iov[iovec_idx].iov_len -= copy; @@ -248,6 +253,11 @@ dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, page, offset, copy); + /* poll for a descriptor slot */ + if (unlikely(dma_cookie < 0)) { + dma_async_issue_pending(chan); + continue; + } len -= copy; iov[iovec_idx].iov_len -= copy; -- cgit v0.10.2 From 0403e3827788d878163f9ef0541b748b0f88ca5d Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:42:50 -0700 Subject: dmaengine: add fence support Some engines optimize operation by reading ahead in the descriptor chain such that descriptor2 may start execution before descriptor1 completes. If descriptor2 depends on the result from descriptor1 then a fence is required (on descriptor2) to disable this optimization. The async_tx api could implicitly identify dependencies via the 'depend_tx' parameter, but that would constrain cases where the dependency chain only specifies a completion order rather than a data dependency. So, provide an ASYNC_TX_FENCE to explicitly identify data dependencies. Signed-off-by: Dan Williams diff --git a/crypto/async_tx/async_memcpy.c b/crypto/async_tx/async_memcpy.c index 98e15bd..b38cbb3 100644 --- a/crypto/async_tx/async_memcpy.c +++ b/crypto/async_tx/async_memcpy.c @@ -52,9 +52,12 @@ async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset, if (device) { dma_addr_t dma_dest, dma_src; - unsigned long dma_prep_flags; + unsigned long dma_prep_flags = 0; - dma_prep_flags = submit->cb_fn ? DMA_PREP_INTERRUPT : 0; + if (submit->cb_fn) + dma_prep_flags |= DMA_PREP_INTERRUPT; + if (submit->flags & ASYNC_TX_FENCE) + dma_prep_flags |= DMA_PREP_FENCE; dma_dest = dma_map_page(device->dev, dest, dest_offset, len, DMA_FROM_DEVICE); diff --git a/crypto/async_tx/async_memset.c b/crypto/async_tx/async_memset.c index b896a6e5..a374784 100644 --- a/crypto/async_tx/async_memset.c +++ b/crypto/async_tx/async_memset.c @@ -49,9 +49,12 @@ async_memset(struct page *dest, int val, unsigned int offset, size_t len, if (device) { dma_addr_t dma_dest; - unsigned long dma_prep_flags; + unsigned long dma_prep_flags = 0; - dma_prep_flags = submit->cb_fn ? DMA_PREP_INTERRUPT : 0; + if (submit->cb_fn) + dma_prep_flags |= DMA_PREP_INTERRUPT; + if (submit->flags & ASYNC_TX_FENCE) + dma_prep_flags |= DMA_PREP_FENCE; dma_dest = dma_map_page(device->dev, dest, offset, len, DMA_FROM_DEVICE); diff --git a/crypto/async_tx/async_pq.c b/crypto/async_tx/async_pq.c index 108b21e..a25e290 100644 --- a/crypto/async_tx/async_pq.c +++ b/crypto/async_tx/async_pq.c @@ -101,6 +101,7 @@ do_async_gen_syndrome(struct dma_chan *chan, struct page **blocks, */ if (src_cnt > pq_src_cnt) { submit->flags &= ~ASYNC_TX_ACK; + submit->flags |= ASYNC_TX_FENCE; dma_flags |= DMA_COMPL_SKIP_DEST_UNMAP; submit->cb_fn = NULL; submit->cb_param = NULL; @@ -111,6 +112,8 @@ do_async_gen_syndrome(struct dma_chan *chan, struct page **blocks, if (cb_fn_orig) dma_flags |= DMA_PREP_INTERRUPT; } + if (submit->flags & ASYNC_TX_FENCE) + dma_flags |= DMA_PREP_FENCE; /* Since we have clobbered the src_list we are committed * to doing this asynchronously. Drivers force forward @@ -282,6 +285,8 @@ async_syndrome_val(struct page **blocks, unsigned int offset, int disks, dma_flags |= DMA_PREP_PQ_DISABLE_P; if (!Q(blocks, disks)) dma_flags |= DMA_PREP_PQ_DISABLE_Q; + if (submit->flags & ASYNC_TX_FENCE) + dma_flags |= DMA_PREP_FENCE; for (i = 0; i < disks; i++) if (likely(blocks[i])) { BUG_ON(is_raid6_zero_block(blocks[i])); diff --git a/crypto/async_tx/async_raid6_recov.c b/crypto/async_tx/async_raid6_recov.c index 0c14d48..822a42d 100644 --- a/crypto/async_tx/async_raid6_recov.c +++ b/crypto/async_tx/async_raid6_recov.c @@ -44,6 +44,8 @@ async_sum_product(struct page *dest, struct page **srcs, unsigned char *coef, struct dma_async_tx_descriptor *tx; enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P; + if (submit->flags & ASYNC_TX_FENCE) + dma_flags |= DMA_PREP_FENCE; dma_dest[1] = dma_map_page(dev, dest, 0, len, DMA_BIDIRECTIONAL); dma_src[0] = dma_map_page(dev, srcs[0], 0, len, DMA_TO_DEVICE); dma_src[1] = dma_map_page(dev, srcs[1], 0, len, DMA_TO_DEVICE); @@ -89,6 +91,8 @@ async_mult(struct page *dest, struct page *src, u8 coef, size_t len, struct dma_async_tx_descriptor *tx; enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P; + if (submit->flags & ASYNC_TX_FENCE) + dma_flags |= DMA_PREP_FENCE; dma_dest[1] = dma_map_page(dev, dest, 0, len, DMA_BIDIRECTIONAL); dma_src[0] = dma_map_page(dev, src, 0, len, DMA_TO_DEVICE); tx = dma->device_prep_dma_pq(chan, dma_dest, dma_src, 1, &coef, @@ -138,7 +142,7 @@ __2data_recov_4(size_t bytes, int faila, int failb, struct page **blocks, srcs[1] = q; coef[0] = raid6_gfexi[failb-faila]; coef[1] = raid6_gfinv[raid6_gfexp[faila]^raid6_gfexp[failb]]; - init_async_submit(submit, 0, tx, NULL, NULL, scribble); + init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); tx = async_sum_product(b, srcs, coef, bytes, submit); /* Dy = P+Pxy+Dx */ @@ -188,23 +192,23 @@ __2data_recov_5(size_t bytes, int faila, int failb, struct page **blocks, dp = blocks[faila]; dq = blocks[failb]; - init_async_submit(submit, 0, tx, NULL, NULL, scribble); + init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); tx = async_memcpy(dp, g, 0, 0, bytes, submit); - init_async_submit(submit, 0, tx, NULL, NULL, scribble); + init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); tx = async_mult(dq, g, raid6_gfexp[good], bytes, submit); /* compute P + Pxy */ srcs[0] = dp; srcs[1] = p; - init_async_submit(submit, ASYNC_TX_XOR_DROP_DST, tx, NULL, NULL, - scribble); + init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx, + NULL, NULL, scribble); tx = async_xor(dp, srcs, 0, 2, bytes, submit); /* compute Q + Qxy */ srcs[0] = dq; srcs[1] = q; - init_async_submit(submit, ASYNC_TX_XOR_DROP_DST, tx, NULL, NULL, - scribble); + init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx, + NULL, NULL, scribble); tx = async_xor(dq, srcs, 0, 2, bytes, submit); /* Dx = A*(P+Pxy) + B*(Q+Qxy) */ @@ -212,7 +216,7 @@ __2data_recov_5(size_t bytes, int faila, int failb, struct page **blocks, srcs[1] = dq; coef[0] = raid6_gfexi[failb-faila]; coef[1] = raid6_gfinv[raid6_gfexp[faila]^raid6_gfexp[failb]]; - init_async_submit(submit, 0, tx, NULL, NULL, scribble); + init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); tx = async_sum_product(dq, srcs, coef, bytes, submit); /* Dy = P+Pxy+Dx */ @@ -252,7 +256,7 @@ __2data_recov_n(int disks, size_t bytes, int faila, int failb, blocks[failb] = (void *)raid6_empty_zero_page; blocks[disks-1] = dq; - init_async_submit(submit, 0, tx, NULL, NULL, scribble); + init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); tx = async_gen_syndrome(blocks, 0, disks, bytes, submit); /* Restore pointer table */ @@ -264,15 +268,15 @@ __2data_recov_n(int disks, size_t bytes, int faila, int failb, /* compute P + Pxy */ srcs[0] = dp; srcs[1] = p; - init_async_submit(submit, ASYNC_TX_XOR_DROP_DST, tx, NULL, NULL, - scribble); + init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx, + NULL, NULL, scribble); tx = async_xor(dp, srcs, 0, 2, bytes, submit); /* compute Q + Qxy */ srcs[0] = dq; srcs[1] = q; - init_async_submit(submit, ASYNC_TX_XOR_DROP_DST, tx, NULL, NULL, - scribble); + init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx, + NULL, NULL, scribble); tx = async_xor(dq, srcs, 0, 2, bytes, submit); /* Dx = A*(P+Pxy) + B*(Q+Qxy) */ @@ -280,7 +284,7 @@ __2data_recov_n(int disks, size_t bytes, int faila, int failb, srcs[1] = dq; coef[0] = raid6_gfexi[failb-faila]; coef[1] = raid6_gfinv[raid6_gfexp[faila]^raid6_gfexp[failb]]; - init_async_submit(submit, 0, tx, NULL, NULL, scribble); + init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); tx = async_sum_product(dq, srcs, coef, bytes, submit); /* Dy = P+Pxy+Dx */ @@ -407,13 +411,16 @@ async_raid6_datap_recov(int disks, size_t bytes, int faila, int good = faila == 0 ? 1 : 0; struct page *g = blocks[good]; - init_async_submit(submit, 0, tx, NULL, NULL, scribble); + init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, + scribble); tx = async_memcpy(p, g, 0, 0, bytes, submit); - init_async_submit(submit, 0, tx, NULL, NULL, scribble); + init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, + scribble); tx = async_mult(dq, g, raid6_gfexp[good], bytes, submit); } else { - init_async_submit(submit, 0, tx, NULL, NULL, scribble); + init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, + scribble); tx = async_gen_syndrome(blocks, 0, disks, bytes, submit); } @@ -426,11 +433,11 @@ async_raid6_datap_recov(int disks, size_t bytes, int faila, srcs[0] = dq; srcs[1] = q; - init_async_submit(submit, ASYNC_TX_XOR_DROP_DST, tx, NULL, NULL, - scribble); + init_async_submit(submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx, + NULL, NULL, scribble); tx = async_xor(dq, srcs, 0, 2, bytes, submit); - init_async_submit(submit, 0, tx, NULL, NULL, scribble); + init_async_submit(submit, ASYNC_TX_FENCE, tx, NULL, NULL, scribble); tx = async_mult(dq, dq, coef, bytes, submit); srcs[0] = p; diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index 56b5f98..db27987 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c @@ -69,6 +69,7 @@ do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, */ if (src_cnt > xor_src_cnt) { submit->flags &= ~ASYNC_TX_ACK; + submit->flags |= ASYNC_TX_FENCE; dma_flags = DMA_COMPL_SKIP_DEST_UNMAP; submit->cb_fn = NULL; submit->cb_param = NULL; @@ -78,7 +79,8 @@ do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, } if (submit->cb_fn) dma_flags |= DMA_PREP_INTERRUPT; - + if (submit->flags & ASYNC_TX_FENCE) + dma_flags |= DMA_PREP_FENCE; /* Since we have clobbered the src_list we are committed * to doing this asynchronously. Drivers force forward progress * in case they can not provide a descriptor @@ -264,12 +266,15 @@ async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, dma_src = (dma_addr_t *) src_list; if (dma_src && device && src_cnt <= device->max_xor) { - unsigned long dma_prep_flags; + unsigned long dma_prep_flags = 0; int i; pr_debug("%s: (async) len: %zu\n", __func__, len); - dma_prep_flags = submit->cb_fn ? DMA_PREP_INTERRUPT : 0; + if (submit->cb_fn) + dma_prep_flags |= DMA_PREP_INTERRUPT; + if (submit->flags & ASYNC_TX_FENCE) + dma_prep_flags |= DMA_PREP_FENCE; for (i = 0; i < src_cnt; i++) dma_src[i] = dma_map_page(device->dev, src_list[i], offset, len, DMA_TO_DEVICE); diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 0a5cf21..54ef8d7 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -502,13 +502,17 @@ async_copy_data(int frombio, struct bio *bio, struct page *page, int i; int page_offset; struct async_submit_ctl submit; + enum async_tx_flags flags = 0; if (bio->bi_sector >= sector) page_offset = (signed)(bio->bi_sector - sector) * 512; else page_offset = (signed)(sector - bio->bi_sector) * -512; - init_async_submit(&submit, 0, tx, NULL, NULL, NULL); + if (frombio) + flags |= ASYNC_TX_FENCE; + init_async_submit(&submit, flags, tx, NULL, NULL, NULL); + bio_for_each_segment(bvl, bio, i) { int len = bio_iovec_idx(bio, i)->bv_len; int clen; @@ -685,7 +689,7 @@ ops_run_compute5(struct stripe_head *sh, struct raid5_percpu *percpu) atomic_inc(&sh->count); - init_async_submit(&submit, ASYNC_TX_XOR_ZERO_DST, NULL, + init_async_submit(&submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_ZERO_DST, NULL, ops_complete_compute, sh, to_addr_conv(sh, percpu)); if (unlikely(count == 1)) tx = async_memcpy(xor_dest, xor_srcs[0], 0, 0, STRIPE_SIZE, &submit); @@ -763,7 +767,8 @@ ops_run_compute6_1(struct stripe_head *sh, struct raid5_percpu *percpu) count = set_syndrome_sources(blocks, sh); blocks[count] = NULL; /* regenerating p is not necessary */ BUG_ON(blocks[count+1] != dest); /* q should already be set */ - init_async_submit(&submit, 0, NULL, ops_complete_compute, sh, + init_async_submit(&submit, ASYNC_TX_FENCE, NULL, + ops_complete_compute, sh, to_addr_conv(sh, percpu)); tx = async_gen_syndrome(blocks, 0, count+2, STRIPE_SIZE, &submit); } else { @@ -775,8 +780,8 @@ ops_run_compute6_1(struct stripe_head *sh, struct raid5_percpu *percpu) blocks[count++] = sh->dev[i].page; } - init_async_submit(&submit, ASYNC_TX_XOR_ZERO_DST, NULL, - ops_complete_compute, sh, + init_async_submit(&submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_ZERO_DST, + NULL, ops_complete_compute, sh, to_addr_conv(sh, percpu)); tx = async_xor(dest, blocks, 0, count, STRIPE_SIZE, &submit); } @@ -837,8 +842,9 @@ ops_run_compute6_2(struct stripe_head *sh, struct raid5_percpu *percpu) /* Q disk is one of the missing disks */ if (faila == syndrome_disks) { /* Missing P+Q, just recompute */ - init_async_submit(&submit, 0, NULL, ops_complete_compute, - sh, to_addr_conv(sh, percpu)); + init_async_submit(&submit, ASYNC_TX_FENCE, NULL, + ops_complete_compute, sh, + to_addr_conv(sh, percpu)); return async_gen_syndrome(blocks, 0, count+2, STRIPE_SIZE, &submit); } else { @@ -859,21 +865,24 @@ ops_run_compute6_2(struct stripe_head *sh, struct raid5_percpu *percpu) blocks[count++] = sh->dev[i].page; } dest = sh->dev[data_target].page; - init_async_submit(&submit, ASYNC_TX_XOR_ZERO_DST, NULL, - NULL, NULL, to_addr_conv(sh, percpu)); + init_async_submit(&submit, + ASYNC_TX_FENCE|ASYNC_TX_XOR_ZERO_DST, + NULL, NULL, NULL, + to_addr_conv(sh, percpu)); tx = async_xor(dest, blocks, 0, count, STRIPE_SIZE, &submit); count = set_syndrome_sources(blocks, sh); - init_async_submit(&submit, 0, tx, ops_complete_compute, - sh, to_addr_conv(sh, percpu)); + init_async_submit(&submit, ASYNC_TX_FENCE, tx, + ops_complete_compute, sh, + to_addr_conv(sh, percpu)); return async_gen_syndrome(blocks, 0, count+2, STRIPE_SIZE, &submit); } } - init_async_submit(&submit, 0, NULL, ops_complete_compute, sh, - to_addr_conv(sh, percpu)); + init_async_submit(&submit, ASYNC_TX_FENCE, NULL, ops_complete_compute, + sh, to_addr_conv(sh, percpu)); if (failb == syndrome_disks) { /* We're missing D+P. */ return async_raid6_datap_recov(syndrome_disks+2, STRIPE_SIZE, @@ -916,7 +925,7 @@ ops_run_prexor(struct stripe_head *sh, struct raid5_percpu *percpu, xor_srcs[count++] = dev->page; } - init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST, tx, + init_async_submit(&submit, ASYNC_TX_FENCE|ASYNC_TX_XOR_DROP_DST, tx, ops_complete_prexor, sh, to_addr_conv(sh, percpu)); tx = async_xor(xor_dest, xor_srcs, 0, count, STRIPE_SIZE, &submit); diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index 866e61c..a1c486a 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h @@ -58,11 +58,14 @@ struct dma_chan_ref { * array. * @ASYNC_TX_ACK: immediately ack the descriptor, precludes setting up a * dependency chain + * @ASYNC_TX_FENCE: specify that the next operation in the dependency + * chain uses this operation's result as an input */ enum async_tx_flags { ASYNC_TX_XOR_ZERO_DST = (1 << 0), ASYNC_TX_XOR_DROP_DST = (1 << 1), ASYNC_TX_ACK = (1 << 2), + ASYNC_TX_FENCE = (1 << 3), }; /** diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 1012f1a..4d6c1c9 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -87,6 +87,8 @@ enum dma_transaction_type { * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as * sources that were the result of a previous operation, in the case of a PQ * operation it continues the calculation with new sources + * @DMA_PREP_FENCE - tell the driver that subsequent operations depend + * on the result of this operation */ enum dma_ctrl_flags { DMA_PREP_INTERRUPT = (1 << 0), @@ -98,6 +100,7 @@ enum dma_ctrl_flags { DMA_PREP_PQ_DISABLE_P = (1 << 6), DMA_PREP_PQ_DISABLE_Q = (1 << 7), DMA_PREP_CONTINUE = (1 << 8), + DMA_PREP_FENCE = (1 << 9), }; /** -- cgit v0.10.2 From 138f4c359d23d2ec38d18bd70dd9613ae515fe93 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:42:51 -0700 Subject: dmaengine, async_tx: add a "no channel switch" allocator Channel switching is problematic for some dmaengine drivers as the architecture precludes separating the ->prep from ->submit. In these cases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify the async_tx allocator to only return channels that support all of the required asynchronous operations. For example MD_RAID456=y selects support for asynchronous xor, xor validate, pq, pq validate, and memcpy. When ASYNC_TX_DISABLE_CHANNEL_SWITCH=y any channel with all these capabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to quickly locate compatible channels with the guarantee that dependency chains will remain on one channel. When ASYNC_TX_DISABLE_CHANNEL_SWITCH=n async_tx_find_channel() may select channels that lead to operation chains that need to cross channel boundaries using the async_tx channel switch capability. Signed-off-by: Dan Williams diff --git a/crypto/async_tx/async_tx.c b/crypto/async_tx/async_tx.c index 60615fe..f9cdf04 100644 --- a/crypto/async_tx/async_tx.c +++ b/crypto/async_tx/async_tx.c @@ -81,6 +81,10 @@ async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx, struct dma_device *device = chan->device; struct dma_async_tx_descriptor *intr_tx = (void *) ~0; + #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH + BUG(); + #endif + /* first check to see if we can still append to depend_tx */ spin_lock_bh(&depend_tx->lock); if (depend_tx->parent && depend_tx->chan == tx->chan) { diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 912a51b..ddcd979 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -17,11 +17,15 @@ if DMADEVICES comment "DMA Devices" +config ASYNC_TX_DISABLE_CHANNEL_SWITCH + bool + config INTEL_IOATDMA tristate "Intel I/OAT DMA support" depends on PCI && X86 select DMA_ENGINE select DCA + select ASYNC_TX_DISABLE_CHANNEL_SWITCH help Enable support for the Intel(R) I/OAT DMA engine present in recent Intel Xeon chipsets. diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 9659847..d5bc628 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -608,6 +608,40 @@ void dmaengine_put(void) } EXPORT_SYMBOL(dmaengine_put); +static bool device_has_all_tx_types(struct dma_device *device) +{ + /* A device that satisfies this test has channels that will never cause + * an async_tx channel switch event as all possible operation types can + * be handled. + */ + #ifdef CONFIG_ASYNC_TX_DMA + if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask)) + return false; + #endif + + #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE) + if (!dma_has_cap(DMA_MEMCPY, device->cap_mask)) + return false; + #endif + + #if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE) + if (!dma_has_cap(DMA_MEMSET, device->cap_mask)) + return false; + #endif + + #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE) + if (!dma_has_cap(DMA_XOR, device->cap_mask)) + return false; + #endif + + #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE) + if (!dma_has_cap(DMA_PQ, device->cap_mask)) + return false; + #endif + + return true; +} + static int get_dma_id(struct dma_device *device) { int rc; @@ -665,6 +699,12 @@ int dma_async_device_register(struct dma_device *device) BUG_ON(!device->device_issue_pending); BUG_ON(!device->dev); + /* note: this only matters in the + * CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH=y case + */ + if (device_has_all_tx_types(device)) + dma_cap_set(DMA_ASYNC_TX, device->cap_mask); + idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL); if (!idr_ref) return -ENOMEM; diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 4d6c1c9..86853ed 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -48,6 +48,9 @@ enum dma_status { /** * enum dma_transaction_type - DMA transaction types/indexes + * + * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is + * automatically set as dma devices are registered. */ enum dma_transaction_type { DMA_MEMCPY, @@ -61,6 +64,7 @@ enum dma_transaction_type { DMA_MEMCPY_CRC32C, DMA_INTERRUPT, DMA_PRIVATE, + DMA_ASYNC_TX, DMA_SLAVE, }; @@ -396,7 +400,11 @@ static inline void net_dmaengine_put(void) #ifdef CONFIG_ASYNC_TX_DMA #define async_dmaengine_get() dmaengine_get() #define async_dmaengine_put() dmaengine_put() +#ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH +#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) +#else #define async_dma_find_channel(type) dma_find_channel(type) +#endif /* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH */ #else static inline void async_dmaengine_get(void) { @@ -409,7 +417,7 @@ async_dma_find_channel(enum dma_transaction_type type) { return NULL; } -#endif +#endif /* CONFIG_ASYNC_TX_DMA */ dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest, void *src, size_t len); -- cgit v0.10.2 From 9308add6ea4fedeba37b0d7c4630a542bd34f214 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:42:52 -0700 Subject: dmaengine: cleanup unused transaction types No drivers currently implement these operation types, so they can be deleted. Signed-off-by: Dan Williams diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c index faaef95..5c147fb 100644 --- a/arch/arm/mach-iop13xx/setup.c +++ b/arch/arm/mach-iop13xx/setup.c @@ -477,10 +477,8 @@ void __init iop13xx_platform_init(void) plat_data = &iop13xx_adma_0_data; dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); dma_cap_set(DMA_XOR, plat_data->cap_mask); - dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); dma_cap_set(DMA_MEMSET, plat_data->cap_mask); - dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); break; case IOP13XX_INIT_ADMA_1: @@ -489,10 +487,8 @@ void __init iop13xx_platform_init(void) plat_data = &iop13xx_adma_1_data; dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); dma_cap_set(DMA_XOR, plat_data->cap_mask); - dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); dma_cap_set(DMA_MEMSET, plat_data->cap_mask); - dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); break; case IOP13XX_INIT_ADMA_2: @@ -501,13 +497,10 @@ void __init iop13xx_platform_init(void) plat_data = &iop13xx_adma_2_data; dma_cap_set(DMA_MEMCPY, plat_data->cap_mask); dma_cap_set(DMA_XOR, plat_data->cap_mask); - dma_cap_set(DMA_DUAL_XOR, plat_data->cap_mask); dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask); dma_cap_set(DMA_MEMSET, plat_data->cap_mask); - dma_cap_set(DMA_MEMCPY_CRC32C, plat_data->cap_mask); dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask); dma_cap_set(DMA_PQ, plat_data->cap_mask); - dma_cap_set(DMA_PQ_UPDATE, plat_data->cap_mask); dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask); break; } diff --git a/arch/arm/plat-iop/adma.c b/arch/arm/plat-iop/adma.c index da1dd0d..1ff6a37 100644 --- a/arch/arm/plat-iop/adma.c +++ b/arch/arm/plat-iop/adma.c @@ -179,7 +179,6 @@ static int __init iop3xx_adma_cap_init(void) dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask); #else dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask); - dma_cap_set(DMA_MEMCPY_CRC32C, iop3xx_dma_0_data.cap_mask); dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask); #endif @@ -188,7 +187,6 @@ static int __init iop3xx_adma_cap_init(void) dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask); #else dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask); - dma_cap_set(DMA_MEMCPY_CRC32C, iop3xx_dma_1_data.cap_mask); dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask); #endif diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index 4496bc6..cecb6d6 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c @@ -1256,15 +1256,12 @@ static int __devinit iop_adma_probe(struct platform_device *pdev) } dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: " - "( %s%s%s%s%s%s%s%s%s%s)\n", + "( %s%s%s%s%s%s%s)\n", dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "", - dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "", dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "", dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", - dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "", dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "", dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "", - dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "", dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 86853ed..db23fd5 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -56,12 +56,9 @@ enum dma_transaction_type { DMA_MEMCPY, DMA_XOR, DMA_PQ, - DMA_DUAL_XOR, - DMA_PQ_UPDATE, DMA_XOR_VAL, DMA_PQ_VAL, DMA_MEMSET, - DMA_MEMCPY_CRC32C, DMA_INTERRUPT, DMA_PRIVATE, DMA_ASYNC_TX, -- cgit v0.10.2 From 83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:42:53 -0700 Subject: dmaengine, async_tx: support alignment checks Some engines have transfer size and address alignment restrictions. Add a per-operation alignment property to struct dma_device that the async routines and dmatest can use to check alignment capabilities. Signed-off-by: Dan Williams diff --git a/crypto/async_tx/async_memcpy.c b/crypto/async_tx/async_memcpy.c index b38cbb3..0ec1fb6 100644 --- a/crypto/async_tx/async_memcpy.c +++ b/crypto/async_tx/async_memcpy.c @@ -50,7 +50,7 @@ async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset, struct dma_device *device = chan ? chan->device : NULL; struct dma_async_tx_descriptor *tx = NULL; - if (device) { + if (device && is_dma_copy_aligned(device, src_offset, dest_offset, len)) { dma_addr_t dma_dest, dma_src; unsigned long dma_prep_flags = 0; diff --git a/crypto/async_tx/async_memset.c b/crypto/async_tx/async_memset.c index a374784..58e4a87 100644 --- a/crypto/async_tx/async_memset.c +++ b/crypto/async_tx/async_memset.c @@ -47,7 +47,7 @@ async_memset(struct page *dest, int val, unsigned int offset, size_t len, struct dma_device *device = chan ? chan->device : NULL; struct dma_async_tx_descriptor *tx = NULL; - if (device) { + if (device && is_dma_fill_aligned(device, offset, 0, len)) { dma_addr_t dma_dest; unsigned long dma_prep_flags = 0; diff --git a/crypto/async_tx/async_pq.c b/crypto/async_tx/async_pq.c index a25e290..b88db6d 100644 --- a/crypto/async_tx/async_pq.c +++ b/crypto/async_tx/async_pq.c @@ -211,7 +211,8 @@ async_gen_syndrome(struct page **blocks, unsigned int offset, int disks, if (dma_src && device && (src_cnt <= dma_maxpq(device, 0) || - dma_maxpq(device, DMA_PREP_CONTINUE) > 0)) { + dma_maxpq(device, DMA_PREP_CONTINUE) > 0) && + is_dma_pq_aligned(device, offset, 0, len)) { /* run the p+q asynchronously */ pr_debug("%s: (async) disks: %d len: %zu\n", __func__, disks, len); @@ -274,7 +275,8 @@ async_syndrome_val(struct page **blocks, unsigned int offset, int disks, else if (sizeof(dma_addr_t) <= sizeof(struct page *)) dma_src = (dma_addr_t *) blocks; - if (dma_src && device && disks <= dma_maxpq(device, 0)) { + if (dma_src && device && disks <= dma_maxpq(device, 0) && + is_dma_pq_aligned(device, offset, 0, len)) { struct device *dev = device->dev; dma_addr_t *pq = &dma_src[disks-2]; int i; diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index db27987..b459a90 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c @@ -193,7 +193,7 @@ async_xor(struct page *dest, struct page **src_list, unsigned int offset, else if (sizeof(dma_addr_t) <= sizeof(struct page *)) dma_src = (dma_addr_t *) src_list; - if (dma_src && chan) { + if (dma_src && chan && is_dma_xor_aligned(chan->device, offset, 0, len)) { /* run the xor asynchronously */ pr_debug("%s (async): len: %zu\n", __func__, len); @@ -265,7 +265,8 @@ async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, else if (sizeof(dma_addr_t) <= sizeof(struct page *)) dma_src = (dma_addr_t *) src_list; - if (dma_src && device && src_cnt <= device->max_xor) { + if (dma_src && device && src_cnt <= device->max_xor && + is_dma_xor_aligned(device, offset, 0, len)) { unsigned long dma_prep_flags = 0; int i; diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c index 58e49e4..a3722a7 100644 --- a/drivers/dma/dmatest.c +++ b/drivers/dma/dmatest.c @@ -288,6 +288,7 @@ static int dmatest_func(void *data) dma_addr_t dma_dsts[dst_cnt]; struct completion cmp; unsigned long tmo = msecs_to_jiffies(3000); + u8 align = 0; total_tests++; @@ -295,6 +296,18 @@ static int dmatest_func(void *data) src_off = dmatest_random() % (test_buf_size - len + 1); dst_off = dmatest_random() % (test_buf_size - len + 1); + /* honor alignment restrictions */ + if (thread->type == DMA_MEMCPY) + align = dev->copy_align; + else if (thread->type == DMA_XOR) + align = dev->xor_align; + else if (thread->type == DMA_PQ) + align = dev->pq_align; + + len = (len >> align) << align; + src_off = (src_off >> align) << align; + dst_off = (dst_off >> align) << align; + dmatest_init_srcs(thread->srcs, src_off, len); dmatest_init_dsts(thread->dsts, dst_off, len); @@ -311,6 +324,7 @@ static int dmatest_func(void *data) DMA_BIDIRECTIONAL); } + if (thread->type == DMA_MEMCPY) tx = dev->device_prep_dma_memcpy(chan, dma_dsts[0] + dst_off, diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index db23fd5..835b9c7 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -245,6 +245,10 @@ struct dma_async_tx_descriptor { * @cap_mask: one or more dma_capability flags * @max_xor: maximum number of xor sources, 0 if no capability * @max_pq: maximum number of PQ sources and PQ-continue capability + * @copy_align: alignment shift for memcpy operations + * @xor_align: alignment shift for xor operations + * @pq_align: alignment shift for pq operations + * @fill_align: alignment shift for memset operations * @dev_id: unique device ID * @dev: struct device reference for dma mapping api * @device_alloc_chan_resources: allocate resources and return the @@ -271,6 +275,10 @@ struct dma_device { dma_cap_mask_t cap_mask; unsigned short max_xor; unsigned short max_pq; + u8 copy_align; + u8 xor_align; + u8 pq_align; + u8 fill_align; #define DMA_HAS_PQ_CONTINUE (1 << 15) int dev_id; @@ -314,6 +322,42 @@ struct dma_device { void (*device_issue_pending)(struct dma_chan *chan); }; +static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len) +{ + size_t mask; + + if (!align) + return true; + mask = (1 << align) - 1; + if (mask & (off1 | off2 | len)) + return false; + return true; +} + +static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, + size_t off2, size_t len) +{ + return dmaengine_check_align(dev->copy_align, off1, off2, len); +} + +static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, + size_t off2, size_t len) +{ + return dmaengine_check_align(dev->xor_align, off1, off2, len); +} + +static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, + size_t off2, size_t len) +{ + return dmaengine_check_align(dev->pq_align, off1, off2, len); +} + +static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, + size_t off2, size_t len) +{ + return dmaengine_check_align(dev->fill_align, off1, off2, len); +} + static inline void dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) { -- cgit v0.10.2 From 128f2d567f906d38b11d993d8d97b9b988848e26 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:42:53 -0700 Subject: ioat2+: add fence support In preparation for adding more operation types to the ioat3 path the driver needs to honor the DMA_PREP_FENCE flag. For example the async_tx api will hand xor->memcpy->xor chains to the driver with the 'fence' flag set on the first xor and the memcpy operation. This flag in turn sets the 'fence' flag in the descriptor control field telling the hardware that future descriptors in the chain depend on the result of the current descriptor, so wait for all writes to complete before starting the next operation. Note that ioat1 does not prefetch the descriptor chain, so does not require/support fenced operations. Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 460b773..568923c 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -710,6 +710,7 @@ ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, desc->txd.flags = flags; desc->len = total_len; hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); + hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); hw->ctl_f.compl_write = 1; dump_desc_dbg(ioat, desc); /* we leave the channel locked to ensure in order submission */ -- cgit v0.10.2 From 2aec048cdc4a5a81163a42a61df903f76a27e737 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:42:54 -0700 Subject: ioat3: hardware version 3.2 register / descriptor definitions ioat3.2 adds raid5 and raid6 offload capabilities. Signed-off-by: Tom Picard Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index d9d6a7e..0d94e78 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -155,7 +155,7 @@ ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie, /** * struct ioat_desc_sw - wrapper around hardware descriptor - * @hw: hardware DMA descriptor + * @hw: hardware DMA descriptor (for memcpy) * @node: this descriptor will either be on the free list, * or attached to a transaction list (async_tx.tx_list) * @txd: the generic software descriptor for all engines diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h index 9baa3d6..ed4bb82 100644 --- a/drivers/dma/ioat/dma_v2.h +++ b/drivers/dma/ioat/dma_v2.h @@ -114,8 +114,32 @@ static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len return num_descs; } +/** + * struct ioat_ring_ent - wrapper around hardware descriptor + * @hw: hardware DMA descriptor (for memcpy) + * @fill: hardware fill descriptor + * @xor: hardware xor descriptor + * @xor_ex: hardware xor extension descriptor + * @pq: hardware pq descriptor + * @pq_ex: hardware pq extension descriptor + * @pqu: hardware pq update descriptor + * @raw: hardware raw (un-typed) descriptor + * @txd: the generic software descriptor for all engines + * @len: total transaction length for unmap + * @id: identifier for debug + */ + struct ioat_ring_ent { - struct ioat_dma_descriptor *hw; + union { + struct ioat_dma_descriptor *hw; + struct ioat_fill_descriptor *fill; + struct ioat_xor_descriptor *xor; + struct ioat_xor_ext_descriptor *xor_ex; + struct ioat_pq_descriptor *pq; + struct ioat_pq_ext_descriptor *pq_ex; + struct ioat_pq_update_descriptor *pqu; + struct ioat_raw_descriptor *raw; + }; struct dma_async_tx_descriptor txd; size_t len; #ifdef DEBUG diff --git a/drivers/dma/ioat/hw.h b/drivers/dma/ioat/hw.h index 7481fb1..99afb12b 100644 --- a/drivers/dma/ioat/hw.h +++ b/drivers/dma/ioat/hw.h @@ -37,6 +37,7 @@ #define IOAT_VER_1_2 0x12 /* Version 1.2 */ #define IOAT_VER_2_0 0x20 /* Version 2.0 */ #define IOAT_VER_3_0 0x30 /* Version 3.0 */ +#define IOAT_VER_3_2 0x32 /* Version 3.2 */ struct ioat_dma_descriptor { uint32_t size; @@ -55,6 +56,7 @@ struct ioat_dma_descriptor { unsigned int dest_dca:1; unsigned int hint:1; unsigned int rsvd2:13; + #define IOAT_OP_COPY 0x00 unsigned int op:8; } ctl_f; }; @@ -70,4 +72,144 @@ struct ioat_dma_descriptor { }; uint64_t user2; }; + +struct ioat_fill_descriptor { + uint32_t size; + union { + uint32_t ctl; + struct { + unsigned int int_en:1; + unsigned int rsvd:1; + unsigned int dest_snoop_dis:1; + unsigned int compl_write:1; + unsigned int fence:1; + unsigned int rsvd2:2; + unsigned int dest_brk:1; + unsigned int bundle:1; + unsigned int rsvd4:15; + #define IOAT_OP_FILL 0x01 + unsigned int op:8; + } ctl_f; + }; + uint64_t src_data; + uint64_t dst_addr; + uint64_t next; + uint64_t rsv1; + uint64_t next_dst_addr; + uint64_t user1; + uint64_t user2; +}; + +struct ioat_xor_descriptor { + uint32_t size; + union { + uint32_t ctl; + struct { + unsigned int int_en:1; + unsigned int src_snoop_dis:1; + unsigned int dest_snoop_dis:1; + unsigned int compl_write:1; + unsigned int fence:1; + unsigned int src_cnt:3; + unsigned int bundle:1; + unsigned int dest_dca:1; + unsigned int hint:1; + unsigned int rsvd:13; + #define IOAT_OP_XOR 0x87 + #define IOAT_OP_XOR_VAL 0x88 + unsigned int op:8; + } ctl_f; + }; + uint64_t src_addr; + uint64_t dst_addr; + uint64_t next; + uint64_t src_addr2; + uint64_t src_addr3; + uint64_t src_addr4; + uint64_t src_addr5; +}; + +struct ioat_xor_ext_descriptor { + uint64_t src_addr6; + uint64_t src_addr7; + uint64_t src_addr8; + uint64_t next; + uint64_t rsvd[4]; +}; + +struct ioat_pq_descriptor { + uint32_t size; + union { + uint32_t ctl; + struct { + unsigned int int_en:1; + unsigned int src_snoop_dis:1; + unsigned int dest_snoop_dis:1; + unsigned int compl_write:1; + unsigned int fence:1; + unsigned int src_cnt:3; + unsigned int bundle:1; + unsigned int dest_dca:1; + unsigned int hint:1; + unsigned int p_disable:1; + unsigned int q_disable:1; + unsigned int rsvd:11; + #define IOAT_OP_PQ 0x89 + #define IOAT_OP_PQ_VAL 0x8a + unsigned int op:8; + } ctl_f; + }; + uint64_t src_addr; + uint64_t p_addr; + uint64_t next; + uint64_t src_addr2; + uint64_t src_addr3; + uint8_t coef[8]; + uint64_t q_addr; +}; + +struct ioat_pq_ext_descriptor { + uint64_t src_addr4; + uint64_t src_addr5; + uint64_t src_addr6; + uint64_t next; + uint64_t src_addr7; + uint64_t src_addr8; + uint64_t rsvd[2]; +}; + +struct ioat_pq_update_descriptor { + uint32_t size; + union { + uint32_t ctl; + struct { + unsigned int int_en:1; + unsigned int src_snoop_dis:1; + unsigned int dest_snoop_dis:1; + unsigned int compl_write:1; + unsigned int fence:1; + unsigned int src_cnt:3; + unsigned int bundle:1; + unsigned int dest_dca:1; + unsigned int hint:1; + unsigned int p_disable:1; + unsigned int q_disable:1; + unsigned int rsvd:3; + unsigned int coef:8; + #define IOAT_OP_PQ_UP 0x8b + unsigned int op:8; + } ctl_f; + }; + uint64_t src_addr; + uint64_t p_addr; + uint64_t next; + uint64_t src_addr2; + uint64_t p_src; + uint64_t q_src; + uint64_t q_addr; +}; + +struct ioat_raw_descriptor { + uint64_t field[8]; +}; #endif diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h index e4334a1..85d04b8c 100644 --- a/drivers/dma/ioat/registers.h +++ b/drivers/dma/ioat/registers.h @@ -64,6 +64,20 @@ #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ #define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001 +#define IOAT_DEVICE_MMIO_RESTRICTED 0x0002 +#define IOAT_DEVICE_MEMORY_BYPASS 0x0004 +#define IOAT_DEVICE_ADDRESS_REMAPPING 0x0008 + +#define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */ +#define IOAT_CAP_PAGE_BREAK 0x00000001 +#define IOAT_CAP_CRC 0x00000002 +#define IOAT_CAP_SKIP_MARKER 0x00000004 +#define IOAT_CAP_DCA 0x00000010 +#define IOAT_CAP_CRC_MOVE 0x00000020 +#define IOAT_CAP_FILL_BLOCK 0x00000040 +#define IOAT_CAP_APIC 0x00000080 +#define IOAT_CAP_XOR 0x00000100 +#define IOAT_CAP_PQ 0x00000200 #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ @@ -224,6 +238,9 @@ #define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000 #define IOAT_CHANERR_SOFT_ERR 0x4000 #define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000 +#define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000 +#define IOAT_CHANERR_XOR_Q_ERR 0x20000 +#define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000 #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ -- cgit v0.10.2 From bf40a6869c9198bdf56fe173961feb89e9f0d961 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:42:55 -0700 Subject: ioat3: split ioat3 support to its own file, add memset Up until this point the driver for Intel(R) QuickData Technology engines, specification versions 2 and 3, were mostly identical save for a few quirks. Version 3.2 hardware adds many new capabilities (like raid offload support) requiring some infrastructure that is not relevant for v2. For better code organization of the new funcionality move v3 and v3.2 support to its own file dma_v3.c, and export some routines from the base files (dma.c and dma_v2.c) that can be reused directly. The first new capability included in this code reorganization is support for v3.2 memset operations. Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/Makefile b/drivers/dma/ioat/Makefile index 205a639..8997d3f 100644 --- a/drivers/dma/ioat/Makefile +++ b/drivers/dma/ioat/Makefile @@ -1,2 +1,2 @@ obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o -ioatdma-objs := pci.o dma.o dma_v2.o dca.o +ioatdma-objs := pci.o dma.o dma_v2.o dma_v3.o dca.o diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 17a518d..70262c0 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -538,17 +538,6 @@ static void ioat1_cleanup_tasklet(unsigned long data) writew(IOAT_CHANCTRL_RUN, chan->base.reg_base + IOAT_CHANCTRL_OFFSET); } -static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, - int direction, enum dma_ctrl_flags flags, bool dst) -{ - if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) || - (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE))) - pci_unmap_single(pdev, addr, len, direction); - else - pci_unmap_page(pdev, addr, len, direction); -} - - void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, size_t len, struct ioat_dma_descriptor *hw) { diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index 0d94e78..c6d58bf 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -60,6 +60,10 @@ * @dca: direct cache access context * @intr_quirk: interrupt setup quirk (for ioat_v1 devices) * @enumerate_channels: hw version specific channel enumeration + * @cleanup_tasklet: select between the v2 and v3 cleanup routines + * @timer_fn: select between the v2 and v3 timer watchdog routines + * + * Note: the v3 cleanup routine supports raid operations */ struct ioatdma_device { @@ -74,6 +78,8 @@ struct ioatdma_device { struct dca_provider *dca; void (*intr_quirk)(struct ioatdma_device *device); int (*enumerate_channels)(struct ioatdma_device *device); + void (*cleanup_tasklet)(unsigned long data); + void (*timer_fn)(unsigned long data); }; struct ioat_chan_common { @@ -287,6 +293,16 @@ static inline bool is_ioat_bug(unsigned long err) IOAT_CHANERR_LENGTH_ERR)); } +static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, + int direction, enum dma_ctrl_flags flags, bool dst) +{ + if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) || + (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE))) + pci_unmap_single(pdev, addr, len, direction); + else + pci_unmap_page(pdev, addr, len, direction); +} + int __devinit ioat_probe(struct ioatdma_device *device); int __devinit ioat_register(struct ioatdma_device *device); int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca); diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 568923c..7492e91 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -39,7 +39,7 @@ #include "registers.h" #include "hw.h" -static int ioat_ring_alloc_order = 8; +int ioat_ring_alloc_order = 8; module_param(ioat_ring_alloc_order, int, 0644); MODULE_PARM_DESC(ioat_ring_alloc_order, "ioat2+: allocate 2^n descriptors per channel (default: n=8)"); @@ -63,7 +63,7 @@ static void __ioat2_issue_pending(struct ioat2_dma_chan *ioat) __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount); } -static void ioat2_issue_pending(struct dma_chan *chan) +void ioat2_issue_pending(struct dma_chan *chan) { struct ioat2_dma_chan *ioat = to_ioat2_chan(chan); @@ -214,7 +214,7 @@ static void ioat2_cleanup_tasklet(unsigned long data) writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); } -static void __restart_chan(struct ioat2_dma_chan *ioat) +void __ioat2_restart_chan(struct ioat2_dma_chan *ioat) { struct ioat_chan_common *chan = &ioat->base; @@ -255,11 +255,9 @@ static void ioat2_restart_channel(struct ioat2_dma_chan *ioat) if (ioat_cleanup_preamble(chan, &phys_complete)) __cleanup(ioat, phys_complete); - __restart_chan(ioat); + __ioat2_restart_chan(ioat); } -static bool reshape_ring(struct ioat2_dma_chan *ioat, int order); - static void ioat2_timer_event(unsigned long data) { struct ioat2_dma_chan *ioat = (void *) data; @@ -321,7 +319,7 @@ static void ioat2_timer_event(unsigned long data) * ioat2_enumerate_channels - find and initialize the device's channels * @device: the device to be enumerated */ -static int ioat2_enumerate_channels(struct ioatdma_device *device) +int ioat2_enumerate_channels(struct ioatdma_device *device) { struct ioat2_dma_chan *ioat; struct device *dev = &device->pdev->dev; @@ -354,8 +352,8 @@ static int ioat2_enumerate_channels(struct ioatdma_device *device) break; ioat_init_channel(device, &ioat->base, i, - ioat2_timer_event, - ioat2_cleanup_tasklet, + device->timer_fn, + device->cleanup_tasklet, (unsigned long) ioat); ioat->xfercap_log = xfercap_log; spin_lock_init(&ioat->ring_lock); @@ -460,7 +458,7 @@ static struct ioat_ring_ent **ioat2_alloc_ring(struct dma_chan *c, int order, gf /* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring * @chan: channel to be initialized */ -static int ioat2_alloc_chan_resources(struct dma_chan *c) +int ioat2_alloc_chan_resources(struct dma_chan *c) { struct ioat2_dma_chan *ioat = to_ioat2_chan(c); struct ioat_chan_common *chan = &ioat->base; @@ -514,7 +512,7 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c) return 1 << ioat->alloc_order; } -static bool reshape_ring(struct ioat2_dma_chan *ioat, int order) +bool reshape_ring(struct ioat2_dma_chan *ioat, int order) { /* reshape differs from normal ring allocation in that we want * to allocate a new software ring while only @@ -627,7 +625,7 @@ static bool reshape_ring(struct ioat2_dma_chan *ioat, int order) * @ioat: ioat2,3 channel (ring) to operate on * @num_descs: allocation length */ -static int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs) +int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs) { struct ioat_chan_common *chan = &ioat->base; @@ -655,9 +653,11 @@ static int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_d spin_lock_bh(&chan->cleanup_lock); if (jiffies > chan->timer.expires && timer_pending(&chan->timer)) { + struct ioatdma_device *device = chan->device; + mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); spin_unlock_bh(&chan->cleanup_lock); - ioat2_timer_event((unsigned long) ioat); + device->timer_fn((unsigned long) ioat); } else spin_unlock_bh(&chan->cleanup_lock); return -ENOMEM; @@ -670,7 +670,7 @@ static int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_d return 0; /* with ioat->ring_lock held */ } -static struct dma_async_tx_descriptor * +struct dma_async_tx_descriptor * ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, dma_addr_t dma_src, size_t len, unsigned long flags) { @@ -722,11 +722,11 @@ ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, * ioat2_free_chan_resources - release all the descriptors * @chan: the channel to be cleaned */ -static void ioat2_free_chan_resources(struct dma_chan *c) +void ioat2_free_chan_resources(struct dma_chan *c) { struct ioat2_dma_chan *ioat = to_ioat2_chan(c); struct ioat_chan_common *chan = &ioat->base; - struct ioatdma_device *ioatdma_device = chan->device; + struct ioatdma_device *device = chan->device; struct ioat_ring_ent *desc; const u16 total_descs = 1 << ioat->alloc_order; int descs; @@ -740,7 +740,7 @@ static void ioat2_free_chan_resources(struct dma_chan *c) tasklet_disable(&chan->cleanup_task); del_timer_sync(&chan->timer); - ioat2_cleanup(ioat); + device->cleanup_tasklet((unsigned long) ioat); /* Delay 100ms after reset to allow internal DMA logic to quiesce * before removing DMA descriptor resources. @@ -770,8 +770,7 @@ static void ioat2_free_chan_resources(struct dma_chan *c) kfree(ioat->ring); ioat->ring = NULL; ioat->alloc_order = 0; - pci_pool_free(ioatdma_device->completion_pool, - chan->completion, + pci_pool_free(device->completion_pool, chan->completion, chan->completion_dma); spin_unlock_bh(&ioat->ring_lock); @@ -781,16 +780,17 @@ static void ioat2_free_chan_resources(struct dma_chan *c) ioat->dmacount = 0; } -static enum dma_status +enum dma_status ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used) { struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + struct ioatdma_device *device = ioat->base.device; if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) return DMA_SUCCESS; - ioat2_cleanup(ioat); + device->cleanup_tasklet((unsigned long) ioat); return ioat_is_complete(c, cookie, done, used); } @@ -804,6 +804,8 @@ int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca) int err; device->enumerate_channels = ioat2_enumerate_channels; + device->cleanup_tasklet = ioat2_cleanup_tasklet; + device->timer_fn = ioat2_timer_event; dma = &device->common; dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; dma->device_issue_pending = ioat2_issue_pending; @@ -830,53 +832,3 @@ int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca) return err; } - -int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) -{ - struct pci_dev *pdev = device->pdev; - struct dma_device *dma; - struct dma_chan *c; - struct ioat_chan_common *chan; - int err; - u16 dev_id; - - device->enumerate_channels = ioat2_enumerate_channels; - dma = &device->common; - dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; - dma->device_issue_pending = ioat2_issue_pending; - dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; - dma->device_free_chan_resources = ioat2_free_chan_resources; - dma->device_is_tx_complete = ioat2_is_complete; - - /* -= IOAT ver.3 workarounds =- */ - /* Write CHANERRMSK_INT with 3E07h to mask out the errors - * that can cause stability issues for IOAT ver.3 - */ - pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07); - - /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit - * (workaround for spurious config parity error after restart) - */ - pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); - if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) - pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10); - - err = ioat_probe(device); - if (err) - return err; - ioat_set_tcp_copy_break(262144); - - list_for_each_entry(c, &dma->channels, device_node) { - chan = to_chan_common(c); - writel(IOAT_DMA_DCA_ANY_CPU, - chan->reg_base + IOAT_DCACTRL_OFFSET); - } - - err = ioat_register(device); - if (err) - return err; - if (dca) - device->dca = ioat3_dca_init(pdev, device->reg_base); - - return err; -} diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h index ed4bb82..bde57dd 100644 --- a/drivers/dma/ioat/dma_v2.h +++ b/drivers/dma/ioat/dma_v2.h @@ -27,6 +27,7 @@ extern int ioat_pending_level; +extern int ioat_ring_alloc_order; /* * workaround for IOAT ver.3.0 null descriptor issue @@ -167,4 +168,16 @@ int __devinit ioat2_dma_probe(struct ioatdma_device *dev, int dca); int __devinit ioat3_dma_probe(struct ioatdma_device *dev, int dca); struct dca_provider * __devinit ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); struct dca_provider * __devinit ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase); +int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs); +int ioat2_enumerate_channels(struct ioatdma_device *device); +struct dma_async_tx_descriptor * +ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, + dma_addr_t dma_src, size_t len, unsigned long flags); +void ioat2_issue_pending(struct dma_chan *chan); +int ioat2_alloc_chan_resources(struct dma_chan *c); +void ioat2_free_chan_resources(struct dma_chan *c); +enum dma_status ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie, + dma_cookie_t *done, dma_cookie_t *used); +void __ioat2_restart_chan(struct ioat2_dma_chan *ioat); +bool reshape_ring(struct ioat2_dma_chan *ioat, int order); #endif /* IOATDMA_V2_H */ diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c new file mode 100644 index 0000000..b223d66 --- /dev/null +++ b/drivers/dma/ioat/dma_v3.c @@ -0,0 +1,367 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + * BSD LICENSE + * + * Copyright(c) 2004-2009 Intel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Support routines for v3+ hardware + */ + +#include +#include +#include +#include "registers.h" +#include "hw.h" +#include "dma.h" +#include "dma_v2.h" + +static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, + struct ioat_ring_ent *desc) +{ + struct ioat_chan_common *chan = &ioat->base; + struct pci_dev *pdev = chan->device->pdev; + size_t len = desc->len; + size_t offset = len - desc->hw->size; + struct dma_async_tx_descriptor *tx = &desc->txd; + enum dma_ctrl_flags flags = tx->flags; + + switch (desc->hw->ctl_f.op) { + case IOAT_OP_COPY: + ioat_dma_unmap(chan, flags, len, desc->hw); + break; + case IOAT_OP_FILL: { + struct ioat_fill_descriptor *hw = desc->fill; + + if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) + ioat_unmap(pdev, hw->dst_addr - offset, len, + PCI_DMA_FROMDEVICE, flags, 1); + break; + } + default: + dev_err(&pdev->dev, "%s: unknown op type: %#x\n", + __func__, desc->hw->ctl_f.op); + } +} + + +static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) +{ + struct ioat_chan_common *chan = &ioat->base; + struct ioat_ring_ent *desc; + bool seen_current = false; + u16 active; + int i; + + dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n", + __func__, ioat->head, ioat->tail, ioat->issued); + + active = ioat2_ring_active(ioat); + for (i = 0; i < active && !seen_current; i++) { + struct dma_async_tx_descriptor *tx; + + prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1)); + desc = ioat2_get_ring_ent(ioat, ioat->tail + i); + dump_desc_dbg(ioat, desc); + tx = &desc->txd; + if (tx->cookie) { + chan->completed_cookie = tx->cookie; + ioat3_dma_unmap(ioat, desc); + tx->cookie = 0; + if (tx->callback) { + tx->callback(tx->callback_param); + tx->callback = NULL; + } + } + + if (tx->phys == phys_complete) + seen_current = true; + } + ioat->tail += i; + BUG_ON(!seen_current); /* no active descs have written a completion? */ + chan->last_completion = phys_complete; + if (ioat->head == ioat->tail) { + dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", + __func__); + clear_bit(IOAT_COMPLETION_PENDING, &chan->state); + mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); + } +} + +static void ioat3_cleanup(struct ioat2_dma_chan *ioat) +{ + struct ioat_chan_common *chan = &ioat->base; + unsigned long phys_complete; + + prefetch(chan->completion); + + if (!spin_trylock_bh(&chan->cleanup_lock)) + return; + + if (!ioat_cleanup_preamble(chan, &phys_complete)) { + spin_unlock_bh(&chan->cleanup_lock); + return; + } + + if (!spin_trylock_bh(&ioat->ring_lock)) { + spin_unlock_bh(&chan->cleanup_lock); + return; + } + + __cleanup(ioat, phys_complete); + + spin_unlock_bh(&ioat->ring_lock); + spin_unlock_bh(&chan->cleanup_lock); +} + +static void ioat3_cleanup_tasklet(unsigned long data) +{ + struct ioat2_dma_chan *ioat = (void *) data; + + ioat3_cleanup(ioat); + writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); +} + +static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) +{ + struct ioat_chan_common *chan = &ioat->base; + unsigned long phys_complete; + u32 status; + + status = ioat_chansts(chan); + if (is_ioat_active(status) || is_ioat_idle(status)) + ioat_suspend(chan); + while (is_ioat_active(status) || is_ioat_idle(status)) { + status = ioat_chansts(chan); + cpu_relax(); + } + + if (ioat_cleanup_preamble(chan, &phys_complete)) + __cleanup(ioat, phys_complete); + + __ioat2_restart_chan(ioat); +} + +static void ioat3_timer_event(unsigned long data) +{ + struct ioat2_dma_chan *ioat = (void *) data; + struct ioat_chan_common *chan = &ioat->base; + + spin_lock_bh(&chan->cleanup_lock); + if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) { + unsigned long phys_complete; + u64 status; + + spin_lock_bh(&ioat->ring_lock); + status = ioat_chansts(chan); + + /* when halted due to errors check for channel + * programming errors before advancing the completion state + */ + if (is_ioat_halted(status)) { + u32 chanerr; + + chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); + BUG_ON(is_ioat_bug(chanerr)); + } + + /* if we haven't made progress and we have already + * acknowledged a pending completion once, then be more + * forceful with a restart + */ + if (ioat_cleanup_preamble(chan, &phys_complete)) + __cleanup(ioat, phys_complete); + else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) + ioat3_restart_channel(ioat); + else { + set_bit(IOAT_COMPLETION_ACK, &chan->state); + mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); + } + spin_unlock_bh(&ioat->ring_lock); + } else { + u16 active; + + /* if the ring is idle, empty, and oversized try to step + * down the size + */ + spin_lock_bh(&ioat->ring_lock); + active = ioat2_ring_active(ioat); + if (active == 0 && ioat->alloc_order > ioat_get_alloc_order()) + reshape_ring(ioat, ioat->alloc_order-1); + spin_unlock_bh(&ioat->ring_lock); + + /* keep shrinking until we get back to our minimum + * default size + */ + if (ioat->alloc_order > ioat_get_alloc_order()) + mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); + } + spin_unlock_bh(&chan->cleanup_lock); +} + +static enum dma_status +ioat3_is_complete(struct dma_chan *c, dma_cookie_t cookie, + dma_cookie_t *done, dma_cookie_t *used) +{ + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + + if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) + return DMA_SUCCESS; + + ioat3_cleanup(ioat); + + return ioat_is_complete(c, cookie, done, used); +} + +static struct dma_async_tx_descriptor * +ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value, + size_t len, unsigned long flags) +{ + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + struct ioat_ring_ent *desc; + size_t total_len = len; + struct ioat_fill_descriptor *fill; + int num_descs; + u64 src_data = (0x0101010101010101ULL) * (value & 0xff); + u16 idx; + int i; + + num_descs = ioat2_xferlen_to_descs(ioat, len); + if (likely(num_descs) && + ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0) + /* pass */; + else + return NULL; + for (i = 0; i < num_descs; i++) { + size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); + + desc = ioat2_get_ring_ent(ioat, idx + i); + fill = desc->fill; + + fill->size = xfer_size; + fill->src_data = src_data; + fill->dst_addr = dest; + fill->ctl = 0; + fill->ctl_f.op = IOAT_OP_FILL; + + len -= xfer_size; + dest += xfer_size; + dump_desc_dbg(ioat, desc); + } + + desc->txd.flags = flags; + desc->len = total_len; + fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); + fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE); + fill->ctl_f.compl_write = 1; + dump_desc_dbg(ioat, desc); + + /* we leave the channel locked to ensure in order submission */ + return &desc->txd; +} + +int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) +{ + struct pci_dev *pdev = device->pdev; + struct dma_device *dma; + struct dma_chan *c; + struct ioat_chan_common *chan; + int err; + u16 dev_id; + u32 cap; + + device->enumerate_channels = ioat2_enumerate_channels; + device->cleanup_tasklet = ioat3_cleanup_tasklet; + device->timer_fn = ioat3_timer_event; + dma = &device->common; + dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; + dma->device_issue_pending = ioat2_issue_pending; + dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; + dma->device_free_chan_resources = ioat2_free_chan_resources; + dma->device_is_tx_complete = ioat3_is_complete; + cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET); + if (cap & IOAT_CAP_FILL_BLOCK) { + dma_cap_set(DMA_MEMSET, dma->cap_mask); + dma->device_prep_dma_memset = ioat3_prep_memset_lock; + } + + /* -= IOAT ver.3 workarounds =- */ + /* Write CHANERRMSK_INT with 3E07h to mask out the errors + * that can cause stability issues for IOAT ver.3 + */ + pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07); + + /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit + * (workaround for spurious config parity error after restart) + */ + pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); + if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) + pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10); + + err = ioat_probe(device); + if (err) + return err; + ioat_set_tcp_copy_break(262144); + + list_for_each_entry(c, &dma->channels, device_node) { + chan = to_chan_common(c); + writel(IOAT_DMA_DCA_ANY_CPU, + chan->reg_base + IOAT_DCACTRL_OFFSET); + } + + err = ioat_register(device); + if (err) + return err; + if (dca) + device->dca = ioat3_dca_init(pdev, device->reg_base); + + return 0; +} diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c index c4e4322..0f3ec6e 100644 --- a/drivers/dma/ioat/pci.c +++ b/drivers/dma/ioat/pci.c @@ -36,7 +36,7 @@ #include "hw.h" MODULE_VERSION(IOAT_DMA_VERSION); -MODULE_LICENSE("GPL"); +MODULE_LICENSE("Dual BSD/GPL"); MODULE_AUTHOR("Intel Corporation"); static struct pci_device_id ioat_pci_tbl[] = { -- cgit v0.10.2 From 5669e31c5a4874f1634bc0ffba268a6e2fa0cdd2 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:42:56 -0700 Subject: ioat: add 'ioat' sysfs attributes Export driver attributes for diagnostic purposes: 'ring_size': total number of descriptors available to the engine 'ring_active': number of descriptors in-flight 'capabilities': supported operation types for this channel 'version': Intel(R) QuickData specfication revision This also allows some chattiness to be removed from the driver startup as this information is now available via sysfs. Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 70262c0..cb08f81 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -263,6 +263,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state)) mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); + ioat->active += desc->hw->tx_cnt; ioat->pending += desc->hw->tx_cnt; if (ioat->pending >= ioat_pending_level) __ioat1_dma_memcpy_issue_pending(ioat); @@ -611,6 +612,7 @@ static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete) chan->completed_cookie = tx->cookie; tx->cookie = 0; ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw); + ioat->active -= desc->hw->tx_cnt; if (tx->callback) { tx->callback(tx->callback_param); tx->callback = NULL; @@ -1028,13 +1030,8 @@ int __devinit ioat_probe(struct ioatdma_device *device) dma_cap_set(DMA_MEMCPY, dma->cap_mask); dma->dev = &pdev->dev; - dev_err(dev, "Intel(R) I/OAT DMA Engine found," - " %d channels, device version 0x%02x, driver version %s\n", - dma->chancnt, device->version, IOAT_DMA_VERSION); - if (!dma->chancnt) { - dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: " - "zero channels detected\n"); + dev_err(dev, "zero channels detected\n"); goto err_setup_interrupts; } @@ -1085,6 +1082,113 @@ static void ioat1_intr_quirk(struct ioatdma_device *device) pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl); } +static ssize_t ring_size_show(struct dma_chan *c, char *page) +{ + struct ioat_dma_chan *ioat = to_ioat_chan(c); + + return sprintf(page, "%d\n", ioat->desccount); +} +static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size); + +static ssize_t ring_active_show(struct dma_chan *c, char *page) +{ + struct ioat_dma_chan *ioat = to_ioat_chan(c); + + return sprintf(page, "%d\n", ioat->active); +} +static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active); + +static ssize_t cap_show(struct dma_chan *c, char *page) +{ + struct dma_device *dma = c->device; + + return sprintf(page, "copy%s%s%s%s%s%s\n", + dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "", + dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "", + dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "", + dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "", + dma_has_cap(DMA_MEMSET, dma->cap_mask) ? " fill" : "", + dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : ""); + +} +struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap); + +static ssize_t version_show(struct dma_chan *c, char *page) +{ + struct dma_device *dma = c->device; + struct ioatdma_device *device = to_ioatdma_device(dma); + + return sprintf(page, "%d.%d\n", + device->version >> 4, device->version & 0xf); +} +struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version); + +static struct attribute *ioat1_attrs[] = { + &ring_size_attr.attr, + &ring_active_attr.attr, + &ioat_cap_attr.attr, + &ioat_version_attr.attr, + NULL, +}; + +static ssize_t +ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page) +{ + struct ioat_sysfs_entry *entry; + struct ioat_chan_common *chan; + + entry = container_of(attr, struct ioat_sysfs_entry, attr); + chan = container_of(kobj, struct ioat_chan_common, kobj); + + if (!entry->show) + return -EIO; + return entry->show(&chan->common, page); +} + +struct sysfs_ops ioat_sysfs_ops = { + .show = ioat_attr_show, +}; + +static struct kobj_type ioat1_ktype = { + .sysfs_ops = &ioat_sysfs_ops, + .default_attrs = ioat1_attrs, +}; + +void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type) +{ + struct dma_device *dma = &device->common; + struct dma_chan *c; + + list_for_each_entry(c, &dma->channels, device_node) { + struct ioat_chan_common *chan = to_chan_common(c); + struct kobject *parent = &c->dev->device.kobj; + int err; + + err = kobject_init_and_add(&chan->kobj, type, parent, "quickdata"); + if (err) { + dev_warn(to_dev(chan), + "sysfs init error (%d), continuing...\n", err); + kobject_put(&chan->kobj); + set_bit(IOAT_KOBJ_INIT_FAIL, &chan->state); + } + } +} + +void ioat_kobject_del(struct ioatdma_device *device) +{ + struct dma_device *dma = &device->common; + struct dma_chan *c; + + list_for_each_entry(c, &dma->channels, device_node) { + struct ioat_chan_common *chan = to_chan_common(c); + + if (!test_bit(IOAT_KOBJ_INIT_FAIL, &chan->state)) { + kobject_del(&chan->kobj); + kobject_put(&chan->kobj); + } + } +} + int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca) { struct pci_dev *pdev = device->pdev; @@ -1107,6 +1211,8 @@ int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca) err = ioat_register(device); if (err) return err; + ioat_kobject_add(device, &ioat1_ktype); + if (dca) device->dca = ioat_dca_init(pdev, device->reg_base); @@ -1119,6 +1225,8 @@ void __devexit ioat_dma_remove(struct ioatdma_device *device) ioat_disable_interrupts(device); + ioat_kobject_del(device); + dma_async_device_unregister(dma); pci_pool_destroy(device->dma_pool); diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index c6d58bf..c2939b2 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -92,6 +92,7 @@ struct ioat_chan_common { #define IOAT_COMPLETION_PENDING 0 #define IOAT_COMPLETION_ACK 1 #define IOAT_RESET_PENDING 2 + #define IOAT_KOBJ_INIT_FAIL 3 struct timer_list timer; #define COMPLETION_TIMEOUT msecs_to_jiffies(100) #define IDLE_TIMEOUT msecs_to_jiffies(2000) @@ -100,8 +101,13 @@ struct ioat_chan_common { dma_addr_t completion_dma; u64 *completion; struct tasklet_struct cleanup_task; + struct kobject kobj; }; +struct ioat_sysfs_entry { + struct attribute attr; + ssize_t (*show)(struct dma_chan *, char *); +}; /** * struct ioat_dma_chan - internal representation of a DMA channel @@ -117,6 +123,7 @@ struct ioat_dma_chan { int pending; u16 desccount; + u16 active; }; static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c) @@ -319,4 +326,9 @@ void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, size_t len, struct ioat_dma_descriptor *hw); bool ioat_cleanup_preamble(struct ioat_chan_common *chan, unsigned long *phys_complete); +void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type); +void ioat_kobject_del(struct ioatdma_device *device); +extern struct sysfs_ops ioat_sysfs_ops; +extern struct ioat_sysfs_entry ioat_version_attr; +extern struct ioat_sysfs_entry ioat_cap_attr; #endif /* IOATDMA_H */ diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 7492e91..80ce32d 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -795,6 +795,36 @@ ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie, return ioat_is_complete(c, cookie, done, used); } +static ssize_t ring_size_show(struct dma_chan *c, char *page) +{ + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + + return sprintf(page, "%d\n", (1 << ioat->alloc_order) & ~1); +} +static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size); + +static ssize_t ring_active_show(struct dma_chan *c, char *page) +{ + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + + /* ...taken outside the lock, no need to be precise */ + return sprintf(page, "%d\n", ioat2_ring_active(ioat)); +} +static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active); + +static struct attribute *ioat2_attrs[] = { + &ring_size_attr.attr, + &ring_active_attr.attr, + &ioat_cap_attr.attr, + &ioat_version_attr.attr, + NULL, +}; + +struct kobj_type ioat2_ktype = { + .sysfs_ops = &ioat_sysfs_ops, + .default_attrs = ioat2_attrs, +}; + int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca) { struct pci_dev *pdev = device->pdev; @@ -827,6 +857,9 @@ int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca) err = ioat_register(device); if (err) return err; + + ioat_kobject_add(device, &ioat2_ktype); + if (dca) device->dca = ioat2_dca_init(pdev, device->reg_base); diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h index bde57dd..fa030f8 100644 --- a/drivers/dma/ioat/dma_v2.h +++ b/drivers/dma/ioat/dma_v2.h @@ -180,4 +180,5 @@ enum dma_status ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used); void __ioat2_restart_chan(struct ioat2_dma_chan *ioat); bool reshape_ring(struct ioat2_dma_chan *ioat, int order); +extern struct kobj_type ioat2_ktype; #endif /* IOATDMA_V2_H */ diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index b223d66..22af78e 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -360,6 +360,9 @@ int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) err = ioat_register(device); if (err) return err; + + ioat_kobject_add(device, &ioat2_ktype); + if (dca) device->dca = ioat3_dca_init(pdev, device->reg_base); diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c index 0f3ec6e..626a508 100644 --- a/drivers/dma/ioat/pci.c +++ b/drivers/dma/ioat/pci.c @@ -168,6 +168,9 @@ static void __devexit ioat_remove(struct pci_dev *pdev) static int __init ioat_init_module(void) { + pr_info("%s: Intel(R) QuickData Technology Driver %s\n", + DRV_NAME, IOAT_DMA_VERSION); + return pci_register_driver(&ioat_pci_driver); } module_init(ioat_init_module); -- cgit v0.10.2 From e61dacaeb3918cd00cd642e8fb0828324ac59819 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:42:57 -0700 Subject: ioat3: enable dca for completion writes Tag completion writes for direct cache access to reduce the latency of checking for descriptor completions. Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index 22af78e..0913d11 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -167,7 +167,8 @@ static void ioat3_cleanup_tasklet(unsigned long data) struct ioat2_dma_chan *ioat = (void *) data; ioat3_cleanup(ioat); - writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); + writew(IOAT_CHANCTRL_RUN | IOAT3_CHANCTRL_COMPL_DCA_EN, + ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); } static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h index 85d04b8c..97d26ea 100644 --- a/drivers/dma/ioat/registers.h +++ b/drivers/dma/ioat/registers.h @@ -84,6 +84,7 @@ /* DMA Channel Registers */ #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */ #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 +#define IOAT3_CHANCTRL_COMPL_DCA_EN 0x0200 #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 #define IOAT_CHANCTRL_ERR_INT_EN 0x0010 -- cgit v0.10.2 From b094ad3be564e7cc59cca4ff0256550d3a55dd3b Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:42:57 -0700 Subject: ioat3: xor support ioat3.2 adds xor offload support for up to 8 sources. It can also perform an xor-zero-sum operation to validate whether all given sources sum to zero, without writing to a destination. Xor descriptors differ from memcpy in that one operation may require multiple descriptors depending on the number of sources. When the number of sources exceeds 5 an extended descriptor is needed. These descriptors need to be accounted for when updating the DMA_COUNT register. Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 80ce32d..ee295d4 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -48,7 +48,7 @@ module_param(ioat_ring_max_alloc_order, int, 0644); MODULE_PARM_DESC(ioat_ring_max_alloc_order, "ioat2+: upper limit for dynamic ring resizing (default: n=16)"); -static void __ioat2_issue_pending(struct ioat2_dma_chan *ioat) +void __ioat2_issue_pending(struct ioat2_dma_chan *ioat) { void * __iomem reg_base = ioat->base.reg_base; diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h index fa030f8..e23027d 100644 --- a/drivers/dma/ioat/dma_v2.h +++ b/drivers/dma/ioat/dma_v2.h @@ -127,6 +127,7 @@ static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len * @raw: hardware raw (un-typed) descriptor * @txd: the generic software descriptor for all engines * @len: total transaction length for unmap + * @result: asynchronous result of validate operations * @id: identifier for debug */ @@ -143,6 +144,7 @@ struct ioat_ring_ent { }; struct dma_async_tx_descriptor txd; size_t len; + enum sum_check_flags *result; #ifdef DEBUG int id; #endif @@ -180,5 +182,6 @@ enum dma_status ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used); void __ioat2_restart_chan(struct ioat2_dma_chan *ioat); bool reshape_ring(struct ioat2_dma_chan *ioat, int order); +void __ioat2_issue_pending(struct ioat2_dma_chan *ioat); extern struct kobj_type ioat2_ktype; #endif /* IOATDMA_V2_H */ diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index 0913d11..957c205 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -64,8 +64,33 @@ #include "dma.h" #include "dma_v2.h" +/* ioat hardware assumes at least two sources for raid operations */ +#define src_cnt_to_sw(x) ((x) + 2) +#define src_cnt_to_hw(x) ((x) - 2) + +/* provide a lookup table for setting the source address in the base or + * extended descriptor of an xor descriptor + */ +static const u8 xor_idx_to_desc __read_mostly = 0xd0; +static const u8 xor_idx_to_field[] __read_mostly = { 1, 4, 5, 6, 7, 0, 1, 2 }; + +static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx) +{ + struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; + + return raw->field[xor_idx_to_field[idx]]; +} + +static void xor_set_src(struct ioat_raw_descriptor *descs[2], + dma_addr_t addr, u32 offset, int idx) +{ + struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; + + raw->field[xor_idx_to_field[idx]] = addr + offset; +} + static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, - struct ioat_ring_ent *desc) + struct ioat_ring_ent *desc, int idx) { struct ioat_chan_common *chan = &ioat->base; struct pci_dev *pdev = chan->device->pdev; @@ -86,13 +111,71 @@ static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, PCI_DMA_FROMDEVICE, flags, 1); break; } + case IOAT_OP_XOR_VAL: + case IOAT_OP_XOR: { + struct ioat_xor_descriptor *xor = desc->xor; + struct ioat_ring_ent *ext; + struct ioat_xor_ext_descriptor *xor_ex = NULL; + int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt); + struct ioat_raw_descriptor *descs[2]; + int i; + + if (src_cnt > 5) { + ext = ioat2_get_ring_ent(ioat, idx + 1); + xor_ex = ext->xor_ex; + } + + if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { + descs[0] = (struct ioat_raw_descriptor *) xor; + descs[1] = (struct ioat_raw_descriptor *) xor_ex; + for (i = 0; i < src_cnt; i++) { + dma_addr_t src = xor_get_src(descs, i); + + ioat_unmap(pdev, src - offset, len, + PCI_DMA_TODEVICE, flags, 0); + } + + /* dest is a source in xor validate operations */ + if (xor->ctl_f.op == IOAT_OP_XOR_VAL) { + ioat_unmap(pdev, xor->dst_addr - offset, len, + PCI_DMA_TODEVICE, flags, 1); + break; + } + } + + if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) + ioat_unmap(pdev, xor->dst_addr - offset, len, + PCI_DMA_FROMDEVICE, flags, 1); + break; + } default: dev_err(&pdev->dev, "%s: unknown op type: %#x\n", __func__, desc->hw->ctl_f.op); } } +static bool desc_has_ext(struct ioat_ring_ent *desc) +{ + struct ioat_dma_descriptor *hw = desc->hw; + + if (hw->ctl_f.op == IOAT_OP_XOR || + hw->ctl_f.op == IOAT_OP_XOR_VAL) { + struct ioat_xor_descriptor *xor = desc->xor; + if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) + return true; + } + + return false; +} + +/** + * __cleanup - reclaim used descriptors + * @ioat: channel (ring) to clean + * + * The difference from the dma_v2.c __cleanup() is that this routine + * handles extended descriptors and dma-unmapping raid operations. + */ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) { struct ioat_chan_common *chan = &ioat->base; @@ -114,7 +197,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) tx = &desc->txd; if (tx->cookie) { chan->completed_cookie = tx->cookie; - ioat3_dma_unmap(ioat, desc); + ioat3_dma_unmap(ioat, desc, ioat->tail + i); tx->cookie = 0; if (tx->callback) { tx->callback(tx->callback_param); @@ -124,6 +207,12 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) if (tx->phys == phys_complete) seen_current = true; + + /* skip extended descriptors */ + if (desc_has_ext(desc)) { + BUG_ON(i + 1 >= active); + i++; + } } ioat->tail += i; BUG_ON(!seen_current); /* no active descs have written a completion? */ @@ -309,6 +398,121 @@ ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value, return &desc->txd; } +static struct dma_async_tx_descriptor * +__ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result, + dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt, + size_t len, unsigned long flags) +{ + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + struct ioat_ring_ent *compl_desc; + struct ioat_ring_ent *desc; + struct ioat_ring_ent *ext; + size_t total_len = len; + struct ioat_xor_descriptor *xor; + struct ioat_xor_ext_descriptor *xor_ex = NULL; + struct ioat_dma_descriptor *hw; + u32 offset = 0; + int num_descs; + int with_ext; + int i; + u16 idx; + u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR; + + BUG_ON(src_cnt < 2); + + num_descs = ioat2_xferlen_to_descs(ioat, len); + /* we need 2x the number of descriptors to cover greater than 5 + * sources + */ + if (src_cnt > 5) { + with_ext = 1; + num_descs *= 2; + } else + with_ext = 0; + + /* completion writes from the raid engine may pass completion + * writes from the legacy engine, so we need one extra null + * (legacy) descriptor to ensure all completion writes arrive in + * order. + */ + if (likely(num_descs) && + ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0) + /* pass */; + else + return NULL; + for (i = 0; i < num_descs; i += 1 + with_ext) { + struct ioat_raw_descriptor *descs[2]; + size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); + int s; + + desc = ioat2_get_ring_ent(ioat, idx + i); + xor = desc->xor; + + /* save a branch by unconditionally retrieving the + * extended descriptor xor_set_src() knows to not write + * to it in the single descriptor case + */ + ext = ioat2_get_ring_ent(ioat, idx + i + 1); + xor_ex = ext->xor_ex; + + descs[0] = (struct ioat_raw_descriptor *) xor; + descs[1] = (struct ioat_raw_descriptor *) xor_ex; + for (s = 0; s < src_cnt; s++) + xor_set_src(descs, src[s], offset, s); + xor->size = xfer_size; + xor->dst_addr = dest + offset; + xor->ctl = 0; + xor->ctl_f.op = op; + xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt); + + len -= xfer_size; + offset += xfer_size; + dump_desc_dbg(ioat, desc); + } + + /* last xor descriptor carries the unmap parameters and fence bit */ + desc->txd.flags = flags; + desc->len = total_len; + if (result) + desc->result = result; + xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE); + + /* completion descriptor carries interrupt bit */ + compl_desc = ioat2_get_ring_ent(ioat, idx + i); + compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; + hw = compl_desc->hw; + hw->ctl = 0; + hw->ctl_f.null = 1; + hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); + hw->ctl_f.compl_write = 1; + hw->size = NULL_DESC_BUFFER_SIZE; + dump_desc_dbg(ioat, compl_desc); + + /* we leave the channel locked to ensure in order submission */ + return &desc->txd; +} + +static struct dma_async_tx_descriptor * +ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, + unsigned int src_cnt, size_t len, unsigned long flags) +{ + return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags); +} + +struct dma_async_tx_descriptor * +ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, + unsigned int src_cnt, size_t len, + enum sum_check_flags *result, unsigned long flags) +{ + /* the cleanup routine only sets bits on validate failure, it + * does not clear bits on validate success... so clear it here + */ + *result = 0; + + return __ioat3_prep_xor_lock(chan, result, src[0], &src[1], + src_cnt - 1, len, flags); +} + int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) { struct pci_dev *pdev = device->pdev; @@ -333,6 +537,16 @@ int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) dma_cap_set(DMA_MEMSET, dma->cap_mask); dma->device_prep_dma_memset = ioat3_prep_memset_lock; } + if (cap & IOAT_CAP_XOR) { + dma->max_xor = 8; + dma->xor_align = 2; + + dma_cap_set(DMA_XOR, dma->cap_mask); + dma->device_prep_dma_xor = ioat3_prep_xor; + + dma_cap_set(DMA_XOR_VAL, dma->cap_mask); + dma->device_prep_dma_xor_val = ioat3_prep_xor_val; + } /* -= IOAT ver.3 workarounds =- */ /* Write CHANERRMSK_INT with 3E07h to mask out the errors diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h index 97d26ea..63038e1 100644 --- a/drivers/dma/ioat/registers.h +++ b/drivers/dma/ioat/registers.h @@ -243,6 +243,8 @@ #define IOAT_CHANERR_XOR_Q_ERR 0x20000 #define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000 +#define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR) + #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ #endif /* _IOAT_REGISTERS_H_ */ -- cgit v0.10.2 From 9de6fc717bdc574cf5faf9d46ce0f9d6265c7952 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:42:58 -0700 Subject: ioat3: xor self test This adds a hardware specific self test to be called from ioat_probe. In the ioat3 case we will have tests for all the different raid operations, while ioat1 and ioat2 will continue to just test memcpy. Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index cb08f81..32a757b 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -799,7 +799,7 @@ static void __devinit ioat_dma_test_callback(void *dma_async_param) * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. * @device: device to be tested */ -static int __devinit ioat_dma_self_test(struct ioatdma_device *device) +int __devinit ioat_dma_self_test(struct ioatdma_device *device) { int i; u8 *src; @@ -1039,7 +1039,7 @@ int __devinit ioat_probe(struct ioatdma_device *device) if (err) goto err_setup_interrupts; - err = ioat_dma_self_test(device); + err = device->self_test(device); if (err) goto err_self_test; @@ -1197,6 +1197,7 @@ int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca) device->intr_quirk = ioat1_intr_quirk; device->enumerate_channels = ioat1_enumerate_channels; + device->self_test = ioat_dma_self_test; dma = &device->common; dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy; dma->device_issue_pending = ioat1_dma_memcpy_issue_pending; diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index c2939b2..0e37e42 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -62,10 +62,10 @@ * @enumerate_channels: hw version specific channel enumeration * @cleanup_tasklet: select between the v2 and v3 cleanup routines * @timer_fn: select between the v2 and v3 timer watchdog routines + * @self_test: hardware version specific self test for each supported op type * * Note: the v3 cleanup routine supports raid operations */ - struct ioatdma_device { struct pci_dev *pdev; void __iomem *reg_base; @@ -80,6 +80,7 @@ struct ioatdma_device { int (*enumerate_channels)(struct ioatdma_device *device); void (*cleanup_tasklet)(unsigned long data); void (*timer_fn)(unsigned long data); + int (*self_test)(struct ioatdma_device *device); }; struct ioat_chan_common { @@ -313,6 +314,7 @@ static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, int __devinit ioat_probe(struct ioatdma_device *device); int __devinit ioat_register(struct ioatdma_device *device); int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca); +int __devinit ioat_dma_self_test(struct ioatdma_device *device); void __devexit ioat_dma_remove(struct ioatdma_device *device); struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index ee295d4..12c64e1 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -836,6 +836,7 @@ int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca) device->enumerate_channels = ioat2_enumerate_channels; device->cleanup_tasklet = ioat2_cleanup_tasklet; device->timer_fn = ioat2_timer_event; + device->self_test = ioat_dma_self_test; dma = &device->common; dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; dma->device_issue_pending = ioat2_issue_pending; diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index 957c205..927c08b 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -513,6 +513,280 @@ ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, src_cnt - 1, len, flags); } +static void __devinit ioat3_dma_test_callback(void *dma_async_param) +{ + struct completion *cmp = dma_async_param; + + complete(cmp); +} + +#define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ +static int __devinit ioat_xor_val_self_test(struct ioatdma_device *device) +{ + int i, src_idx; + struct page *dest; + struct page *xor_srcs[IOAT_NUM_SRC_TEST]; + struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; + dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; + dma_addr_t dma_addr, dest_dma; + struct dma_async_tx_descriptor *tx; + struct dma_chan *dma_chan; + dma_cookie_t cookie; + u8 cmp_byte = 0; + u32 cmp_word; + u32 xor_val_result; + int err = 0; + struct completion cmp; + unsigned long tmo; + struct device *dev = &device->pdev->dev; + struct dma_device *dma = &device->common; + + dev_dbg(dev, "%s\n", __func__); + + if (!dma_has_cap(DMA_XOR, dma->cap_mask)) + return 0; + + for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { + xor_srcs[src_idx] = alloc_page(GFP_KERNEL); + if (!xor_srcs[src_idx]) { + while (src_idx--) + __free_page(xor_srcs[src_idx]); + return -ENOMEM; + } + } + + dest = alloc_page(GFP_KERNEL); + if (!dest) { + while (src_idx--) + __free_page(xor_srcs[src_idx]); + return -ENOMEM; + } + + /* Fill in src buffers */ + for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { + u8 *ptr = page_address(xor_srcs[src_idx]); + for (i = 0; i < PAGE_SIZE; i++) + ptr[i] = (1 << src_idx); + } + + for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) + cmp_byte ^= (u8) (1 << src_idx); + + cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | + (cmp_byte << 8) | cmp_byte; + + memset(page_address(dest), 0, PAGE_SIZE); + + dma_chan = container_of(dma->channels.next, struct dma_chan, + device_node); + if (dma->device_alloc_chan_resources(dma_chan) < 1) { + err = -ENODEV; + goto out; + } + + /* test xor */ + dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); + for (i = 0; i < IOAT_NUM_SRC_TEST; i++) + dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, + DMA_TO_DEVICE); + tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, + IOAT_NUM_SRC_TEST, PAGE_SIZE, + DMA_PREP_INTERRUPT); + + if (!tx) { + dev_err(dev, "Self-test xor prep failed\n"); + err = -ENODEV; + goto free_resources; + } + + async_tx_ack(tx); + init_completion(&cmp); + tx->callback = ioat3_dma_test_callback; + tx->callback_param = &cmp; + cookie = tx->tx_submit(tx); + if (cookie < 0) { + dev_err(dev, "Self-test xor setup failed\n"); + err = -ENODEV; + goto free_resources; + } + dma->device_issue_pending(dma_chan); + + tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); + + if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { + dev_err(dev, "Self-test xor timed out\n"); + err = -ENODEV; + goto free_resources; + } + + dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); + for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { + u32 *ptr = page_address(dest); + if (ptr[i] != cmp_word) { + dev_err(dev, "Self-test xor failed compare\n"); + err = -ENODEV; + goto free_resources; + } + } + dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_TO_DEVICE); + + /* skip validate if the capability is not present */ + if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) + goto free_resources; + + /* validate the sources with the destintation page */ + for (i = 0; i < IOAT_NUM_SRC_TEST; i++) + xor_val_srcs[i] = xor_srcs[i]; + xor_val_srcs[i] = dest; + + xor_val_result = 1; + + for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) + dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, + DMA_TO_DEVICE); + tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, + IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, + &xor_val_result, DMA_PREP_INTERRUPT); + if (!tx) { + dev_err(dev, "Self-test zero prep failed\n"); + err = -ENODEV; + goto free_resources; + } + + async_tx_ack(tx); + init_completion(&cmp); + tx->callback = ioat3_dma_test_callback; + tx->callback_param = &cmp; + cookie = tx->tx_submit(tx); + if (cookie < 0) { + dev_err(dev, "Self-test zero setup failed\n"); + err = -ENODEV; + goto free_resources; + } + dma->device_issue_pending(dma_chan); + + tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); + + if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { + dev_err(dev, "Self-test validate timed out\n"); + err = -ENODEV; + goto free_resources; + } + + if (xor_val_result != 0) { + dev_err(dev, "Self-test validate failed compare\n"); + err = -ENODEV; + goto free_resources; + } + + /* skip memset if the capability is not present */ + if (!dma_has_cap(DMA_MEMSET, dma_chan->device->cap_mask)) + goto free_resources; + + /* test memset */ + dma_addr = dma_map_page(dev, dest, 0, + PAGE_SIZE, DMA_FROM_DEVICE); + tx = dma->device_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, + DMA_PREP_INTERRUPT); + if (!tx) { + dev_err(dev, "Self-test memset prep failed\n"); + err = -ENODEV; + goto free_resources; + } + + async_tx_ack(tx); + init_completion(&cmp); + tx->callback = ioat3_dma_test_callback; + tx->callback_param = &cmp; + cookie = tx->tx_submit(tx); + if (cookie < 0) { + dev_err(dev, "Self-test memset setup failed\n"); + err = -ENODEV; + goto free_resources; + } + dma->device_issue_pending(dma_chan); + + tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); + + if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { + dev_err(dev, "Self-test memset timed out\n"); + err = -ENODEV; + goto free_resources; + } + + for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) { + u32 *ptr = page_address(dest); + if (ptr[i]) { + dev_err(dev, "Self-test memset failed compare\n"); + err = -ENODEV; + goto free_resources; + } + } + + /* test for non-zero parity sum */ + xor_val_result = 0; + for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) + dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, + DMA_TO_DEVICE); + tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, + IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, + &xor_val_result, DMA_PREP_INTERRUPT); + if (!tx) { + dev_err(dev, "Self-test 2nd zero prep failed\n"); + err = -ENODEV; + goto free_resources; + } + + async_tx_ack(tx); + init_completion(&cmp); + tx->callback = ioat3_dma_test_callback; + tx->callback_param = &cmp; + cookie = tx->tx_submit(tx); + if (cookie < 0) { + dev_err(dev, "Self-test 2nd zero setup failed\n"); + err = -ENODEV; + goto free_resources; + } + dma->device_issue_pending(dma_chan); + + tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); + + if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { + dev_err(dev, "Self-test 2nd validate timed out\n"); + err = -ENODEV; + goto free_resources; + } + + if (xor_val_result != SUM_CHECK_P_RESULT) { + dev_err(dev, "Self-test validate failed compare\n"); + err = -ENODEV; + goto free_resources; + } + +free_resources: + dma->device_free_chan_resources(dma_chan); +out: + src_idx = IOAT_NUM_SRC_TEST; + while (src_idx--) + __free_page(xor_srcs[src_idx]); + __free_page(dest); + return err; +} + +static int __devinit ioat3_dma_self_test(struct ioatdma_device *device) +{ + int rc = ioat_dma_self_test(device); + + if (rc) + return rc; + + rc = ioat_xor_val_self_test(device); + if (rc) + return rc; + + return 0; +} + int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) { struct pci_dev *pdev = device->pdev; @@ -526,6 +800,7 @@ int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) device->enumerate_channels = ioat2_enumerate_channels; device->cleanup_tasklet = ioat3_cleanup_tasklet; device->timer_fn = ioat3_timer_event; + device->self_test = ioat3_dma_self_test; dma = &device->common; dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; dma->device_issue_pending = ioat2_issue_pending; -- cgit v0.10.2 From d69d235b7da2778891640ee95efcd68075978904 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:42:59 -0700 Subject: ioat3: pq support ioat3.2 adds support for raid6 syndrome generation (xor sum of galois field multiplication products) using up to 8 sources. It can also perform an pq-zero-sum operation to validate whether the syndrome for a given set of sources matches a previously computed syndrome. Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index 927c08b..ca2af0f 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -69,10 +69,12 @@ #define src_cnt_to_hw(x) ((x) - 2) /* provide a lookup table for setting the source address in the base or - * extended descriptor of an xor descriptor + * extended descriptor of an xor or pq descriptor */ static const u8 xor_idx_to_desc __read_mostly = 0xd0; static const u8 xor_idx_to_field[] __read_mostly = { 1, 4, 5, 6, 7, 0, 1, 2 }; +static const u8 pq_idx_to_desc __read_mostly = 0xf8; +static const u8 pq_idx_to_field[] __read_mostly = { 1, 4, 5, 0, 1, 2, 4, 5 }; static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx) { @@ -89,6 +91,23 @@ static void xor_set_src(struct ioat_raw_descriptor *descs[2], raw->field[xor_idx_to_field[idx]] = addr + offset; } +static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx) +{ + struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; + + return raw->field[pq_idx_to_field[idx]]; +} + +static void pq_set_src(struct ioat_raw_descriptor *descs[2], + dma_addr_t addr, u32 offset, u8 coef, int idx) +{ + struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0]; + struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; + + raw->field[pq_idx_to_field[idx]] = addr + offset; + pq->coef[idx] = coef; +} + static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, int idx) { @@ -148,6 +167,58 @@ static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, PCI_DMA_FROMDEVICE, flags, 1); break; } + case IOAT_OP_PQ_VAL: + case IOAT_OP_PQ: { + struct ioat_pq_descriptor *pq = desc->pq; + struct ioat_ring_ent *ext; + struct ioat_pq_ext_descriptor *pq_ex = NULL; + int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); + struct ioat_raw_descriptor *descs[2]; + int i; + + if (src_cnt > 3) { + ext = ioat2_get_ring_ent(ioat, idx + 1); + pq_ex = ext->pq_ex; + } + + /* in the 'continue' case don't unmap the dests as sources */ + if (dmaf_p_disabled_continue(flags)) + src_cnt--; + else if (dmaf_continue(flags)) + src_cnt -= 3; + + if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { + descs[0] = (struct ioat_raw_descriptor *) pq; + descs[1] = (struct ioat_raw_descriptor *) pq_ex; + for (i = 0; i < src_cnt; i++) { + dma_addr_t src = pq_get_src(descs, i); + + ioat_unmap(pdev, src - offset, len, + PCI_DMA_TODEVICE, flags, 0); + } + + /* the dests are sources in pq validate operations */ + if (pq->ctl_f.op == IOAT_OP_XOR_VAL) { + if (!(flags & DMA_PREP_PQ_DISABLE_P)) + ioat_unmap(pdev, pq->p_addr - offset, + len, PCI_DMA_TODEVICE, flags, 0); + if (!(flags & DMA_PREP_PQ_DISABLE_Q)) + ioat_unmap(pdev, pq->q_addr - offset, + len, PCI_DMA_TODEVICE, flags, 0); + break; + } + } + + if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { + if (!(flags & DMA_PREP_PQ_DISABLE_P)) + ioat_unmap(pdev, pq->p_addr - offset, len, + PCI_DMA_BIDIRECTIONAL, flags, 1); + if (!(flags & DMA_PREP_PQ_DISABLE_Q)) + ioat_unmap(pdev, pq->q_addr - offset, len, + PCI_DMA_BIDIRECTIONAL, flags, 1); + } + break; + } default: dev_err(&pdev->dev, "%s: unknown op type: %#x\n", __func__, desc->hw->ctl_f.op); @@ -164,6 +235,12 @@ static bool desc_has_ext(struct ioat_ring_ent *desc) if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) return true; + } else if (hw->ctl_f.op == IOAT_OP_PQ || + hw->ctl_f.op == IOAT_OP_PQ_VAL) { + struct ioat_pq_descriptor *pq = desc->pq; + + if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) + return true; } return false; @@ -513,6 +590,182 @@ ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, src_cnt - 1, len, flags); } +static void +dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext) +{ + struct device *dev = to_dev(&ioat->base); + struct ioat_pq_descriptor *pq = desc->pq; + struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL; + struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex }; + int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); + int i; + + dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" + " sz: %#x ctl: %#x (op: %d int: %d compl: %d pq: '%s%s' src_cnt: %d)\n", + desc_id(desc), (unsigned long long) desc->txd.phys, + (unsigned long long) (pq_ex ? pq_ex->next : pq->next), + desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en, + pq->ctl_f.compl_write, + pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", + pq->ctl_f.src_cnt); + for (i = 0; i < src_cnt; i++) + dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, + (unsigned long long) pq_get_src(descs, i), pq->coef[i]); + dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); + dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); +} + +static struct dma_async_tx_descriptor * +__ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result, + const dma_addr_t *dst, const dma_addr_t *src, + unsigned int src_cnt, const unsigned char *scf, + size_t len, unsigned long flags) +{ + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + struct ioat_chan_common *chan = &ioat->base; + struct ioat_ring_ent *compl_desc; + struct ioat_ring_ent *desc; + struct ioat_ring_ent *ext; + size_t total_len = len; + struct ioat_pq_descriptor *pq; + struct ioat_pq_ext_descriptor *pq_ex = NULL; + struct ioat_dma_descriptor *hw; + u32 offset = 0; + int num_descs; + int with_ext; + int i, s; + u16 idx; + u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ; + + dev_dbg(to_dev(chan), "%s\n", __func__); + /* the engine requires at least two sources (we provide + * at least 1 implied source in the DMA_PREP_CONTINUE case) + */ + BUG_ON(src_cnt + dmaf_continue(flags) < 2); + + num_descs = ioat2_xferlen_to_descs(ioat, len); + /* we need 2x the number of descriptors to cover greater than 3 + * sources + */ + if (src_cnt > 3 || flags & DMA_PREP_CONTINUE) { + with_ext = 1; + num_descs *= 2; + } else + with_ext = 0; + + /* completion writes from the raid engine may pass completion + * writes from the legacy engine, so we need one extra null + * (legacy) descriptor to ensure all completion writes arrive in + * order. + */ + if (likely(num_descs) && + ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0) + /* pass */; + else + return NULL; + for (i = 0; i < num_descs; i += 1 + with_ext) { + struct ioat_raw_descriptor *descs[2]; + size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); + + desc = ioat2_get_ring_ent(ioat, idx + i); + pq = desc->pq; + + /* save a branch by unconditionally retrieving the + * extended descriptor pq_set_src() knows to not write + * to it in the single descriptor case + */ + ext = ioat2_get_ring_ent(ioat, idx + i + with_ext); + pq_ex = ext->pq_ex; + + descs[0] = (struct ioat_raw_descriptor *) pq; + descs[1] = (struct ioat_raw_descriptor *) pq_ex; + + for (s = 0; s < src_cnt; s++) + pq_set_src(descs, src[s], offset, scf[s], s); + + /* see the comment for dma_maxpq in include/linux/dmaengine.h */ + if (dmaf_p_disabled_continue(flags)) + pq_set_src(descs, dst[1], offset, 1, s++); + else if (dmaf_continue(flags)) { + pq_set_src(descs, dst[0], offset, 0, s++); + pq_set_src(descs, dst[1], offset, 1, s++); + pq_set_src(descs, dst[1], offset, 0, s++); + } + pq->size = xfer_size; + pq->p_addr = dst[0] + offset; + pq->q_addr = dst[1] + offset; + pq->ctl = 0; + pq->ctl_f.op = op; + pq->ctl_f.src_cnt = src_cnt_to_hw(s); + pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); + pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); + + len -= xfer_size; + offset += xfer_size; + } + + /* last pq descriptor carries the unmap parameters and fence bit */ + desc->txd.flags = flags; + desc->len = total_len; + if (result) + desc->result = result; + pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); + dump_pq_desc_dbg(ioat, desc, ext); + + /* completion descriptor carries interrupt bit */ + compl_desc = ioat2_get_ring_ent(ioat, idx + i); + compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; + hw = compl_desc->hw; + hw->ctl = 0; + hw->ctl_f.null = 1; + hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); + hw->ctl_f.compl_write = 1; + hw->size = NULL_DESC_BUFFER_SIZE; + dump_desc_dbg(ioat, compl_desc); + + /* we leave the channel locked to ensure in order submission */ + return &desc->txd; +} + +static struct dma_async_tx_descriptor * +ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, + unsigned int src_cnt, const unsigned char *scf, size_t len, + unsigned long flags) +{ + /* handle the single source multiply case from the raid6 + * recovery path + */ + if (unlikely((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1)) { + dma_addr_t single_source[2]; + unsigned char single_source_coef[2]; + + BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q); + single_source[0] = src[0]; + single_source[1] = src[0]; + single_source_coef[0] = scf[0]; + single_source_coef[1] = 0; + + return __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2, + single_source_coef, len, flags); + } else + return __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, scf, + len, flags); +} + +struct dma_async_tx_descriptor * +ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, + unsigned int src_cnt, const unsigned char *scf, size_t len, + enum sum_check_flags *pqres, unsigned long flags) +{ + /* the cleanup routine only sets bits on validate failure, it + * does not clear bits on validate success... so clear it here + */ + *pqres = 0; + + return __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len, + flags); +} + static void __devinit ioat3_dma_test_callback(void *dma_async_param) { struct completion *cmp = dma_async_param; @@ -822,6 +1075,16 @@ int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) dma_cap_set(DMA_XOR_VAL, dma->cap_mask); dma->device_prep_dma_xor_val = ioat3_prep_xor_val; } + if (cap & IOAT_CAP_PQ) { + dma_set_maxpq(dma, 8, 0); + dma->pq_align = 2; + + dma_cap_set(DMA_PQ, dma->cap_mask); + dma->device_prep_dma_pq = ioat3_prep_pq; + + dma_cap_set(DMA_PQ_VAL, dma->cap_mask); + dma->device_prep_dma_pq_val = ioat3_prep_pq_val; + } /* -= IOAT ver.3 workarounds =- */ /* Write CHANERRMSK_INT with 3E07h to mask out the errors -- cgit v0.10.2 From ae786624c27411c1d38823f640b39f3d97412d5a Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:43:00 -0700 Subject: ioat3: support xor via pq descriptors If a platform advertises pq capabilities, but not xor, then use ioat3_prep_pqxor and ioat3_prep_pqxor_val to simulate xor support. Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index ca2af0f..bb57491 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -766,6 +766,44 @@ ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, flags); } +static struct dma_async_tx_descriptor * +ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, + unsigned int src_cnt, size_t len, unsigned long flags) +{ + unsigned char scf[src_cnt]; + dma_addr_t pq[2]; + + memset(scf, 0, src_cnt); + flags |= DMA_PREP_PQ_DISABLE_Q; + pq[0] = dst; + pq[1] = ~0; + + return __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len, + flags); +} + +struct dma_async_tx_descriptor * +ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, + unsigned int src_cnt, size_t len, + enum sum_check_flags *result, unsigned long flags) +{ + unsigned char scf[src_cnt]; + dma_addr_t pq[2]; + + /* the cleanup routine only sets bits on validate failure, it + * does not clear bits on validate success... so clear it here + */ + *result = 0; + + memset(scf, 0, src_cnt); + flags |= DMA_PREP_PQ_DISABLE_Q; + pq[0] = src[0]; + pq[1] = ~0; + + return __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, scf, + len, flags); +} + static void __devinit ioat3_dma_test_callback(void *dma_async_param) { struct completion *cmp = dma_async_param; @@ -1084,6 +1122,17 @@ int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) dma_cap_set(DMA_PQ_VAL, dma->cap_mask); dma->device_prep_dma_pq_val = ioat3_prep_pq_val; + + if (!(cap & IOAT_CAP_XOR)) { + dma->max_xor = 8; + dma->xor_align = 2; + + dma_cap_set(DMA_XOR, dma->cap_mask); + dma->device_prep_dma_xor = ioat3_prep_pqxor; + + dma_cap_set(DMA_XOR_VAL, dma->cap_mask); + dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val; + } } /* -= IOAT ver.3 workarounds =- */ -- cgit v0.10.2 From 58c8649e0e25de511c4a66ce3fa38891e2ec4e9e Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:43:00 -0700 Subject: ioat3: interrupt descriptor support The async_tx api uses the DMA_INTERRUPT operation type to terminate a chain of issued operations with a callback routine. Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index bb57491..ff4afdc 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -120,7 +120,8 @@ static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, switch (desc->hw->ctl_f.op) { case IOAT_OP_COPY: - ioat_dma_unmap(chan, flags, len, desc->hw); + if (!desc->hw->ctl_f.null) /* skip 'interrupt' ops */ + ioat_dma_unmap(chan, flags, len, desc->hw); break; case IOAT_OP_FILL: { struct ioat_fill_descriptor *hw = desc->fill; @@ -804,6 +805,38 @@ ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, len, flags); } +static struct dma_async_tx_descriptor * +ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags) +{ + struct ioat2_dma_chan *ioat = to_ioat2_chan(c); + struct ioat_ring_ent *desc; + struct ioat_dma_descriptor *hw; + u16 idx; + + if (ioat2_alloc_and_lock(&idx, ioat, 1) == 0) + desc = ioat2_get_ring_ent(ioat, idx); + else + return NULL; + + hw = desc->hw; + hw->ctl = 0; + hw->ctl_f.null = 1; + hw->ctl_f.int_en = 1; + hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); + hw->ctl_f.compl_write = 1; + hw->size = NULL_DESC_BUFFER_SIZE; + hw->src_addr = 0; + hw->dst_addr = 0; + + desc->txd.flags = flags; + desc->len = 1; + + dump_desc_dbg(ioat, desc); + + /* we leave the channel locked to ensure in order submission */ + return &desc->txd; +} + static void __devinit ioat3_dma_test_callback(void *dma_async_param) { struct completion *cmp = dma_async_param; @@ -1098,6 +1131,10 @@ int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; dma->device_free_chan_resources = ioat2_free_chan_resources; dma->device_is_tx_complete = ioat3_is_complete; + + dma_cap_set(DMA_INTERRUPT, dma->cap_mask); + dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock; + cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET); if (cap & IOAT_CAP_FILL_BLOCK) { dma_cap_set(DMA_MEMSET, dma->cap_mask); -- cgit v0.10.2 From b265b11fc1a0bd6ae5a7fde12e374583a52ab326 Mon Sep 17 00:00:00 2001 From: Tom Picard Date: Tue, 8 Sep 2009 17:43:01 -0700 Subject: ioat3: ioat3.2 pci ids for Jasper Forest Jasper Forest introduces raid offload support via ioat3.2 support. When raid offload is enabled two (out of 8 channels) will report raid5/raid6 offload capabilities. The remaining channels will only report ioat3.0 capabilities (memcpy). Signed-off-by: Tom Picard Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c index 626a508..6c1aac5 100644 --- a/drivers/dma/ioat/pci.c +++ b/drivers/dma/ioat/pci.c @@ -58,6 +58,19 @@ static struct pci_device_id ioat_pci_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, + + /* I/OAT v3.2 platforms */ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, + { 0, } }; diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 0f71812..2b4b8ce 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2529,6 +2529,16 @@ #define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e #define PCI_DEVICE_ID_INTEL_IOAT_CNB 0x360b #define PCI_DEVICE_ID_INTEL_FBD_CNB 0x360c +#define PCI_DEVICE_ID_INTEL_IOAT_JSF0 0x3710 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF1 0x3711 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF2 0x3712 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF3 0x3713 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF4 0x3714 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF5 0x3715 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF6 0x3716 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF7 0x3717 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF8 0x3718 +#define PCI_DEVICE_ID_INTEL_IOAT_JSF9 0x3719 #define PCI_DEVICE_ID_INTEL_ICH10_0 0x3a14 #define PCI_DEVICE_ID_INTEL_ICH10_1 0x3a16 #define PCI_DEVICE_ID_INTEL_ICH10_2 0x3a18 -- cgit v0.10.2 From e3232714d465c42ac631929b990f5e35e2d8a955 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:43:02 -0700 Subject: ioat3: segregate raid engines The cleanup routine for the raid cases imposes extra checks for handling raid descriptors and extended descriptors. If the channel does not support raid it can avoid this extra overhead by using the ioat2 cleanup path. Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 12c64e1..7bbbd83 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -206,7 +206,7 @@ static void ioat2_cleanup(struct ioat2_dma_chan *ioat) spin_unlock_bh(&chan->cleanup_lock); } -static void ioat2_cleanup_tasklet(unsigned long data) +void ioat2_cleanup_tasklet(unsigned long data) { struct ioat2_dma_chan *ioat = (void *) data; @@ -258,7 +258,7 @@ static void ioat2_restart_channel(struct ioat2_dma_chan *ioat) __ioat2_restart_chan(ioat); } -static void ioat2_timer_event(unsigned long data) +void ioat2_timer_event(unsigned long data) { struct ioat2_dma_chan *ioat = (void *) data; struct ioat_chan_common *chan = &ioat->base; diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h index e23027d..246e646 100644 --- a/drivers/dma/ioat/dma_v2.h +++ b/drivers/dma/ioat/dma_v2.h @@ -183,5 +183,7 @@ enum dma_status ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie, void __ioat2_restart_chan(struct ioat2_dma_chan *ioat); bool reshape_ring(struct ioat2_dma_chan *ioat, int order); void __ioat2_issue_pending(struct ioat2_dma_chan *ioat); +void ioat2_cleanup_tasklet(unsigned long data); +void ioat2_timer_event(unsigned long data); extern struct kobj_type ioat2_ktype; #endif /* IOATDMA_V2_H */ diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c index ff4afdc..3686ddd 100644 --- a/drivers/dma/ioat/dma_v3.c +++ b/drivers/dma/ioat/dma_v3.c @@ -1117,30 +1117,25 @@ int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) struct dma_device *dma; struct dma_chan *c; struct ioat_chan_common *chan; + bool is_raid_device = false; int err; u16 dev_id; u32 cap; device->enumerate_channels = ioat2_enumerate_channels; - device->cleanup_tasklet = ioat3_cleanup_tasklet; - device->timer_fn = ioat3_timer_event; device->self_test = ioat3_dma_self_test; dma = &device->common; dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; dma->device_issue_pending = ioat2_issue_pending; dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; dma->device_free_chan_resources = ioat2_free_chan_resources; - dma->device_is_tx_complete = ioat3_is_complete; dma_cap_set(DMA_INTERRUPT, dma->cap_mask); dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock; cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET); - if (cap & IOAT_CAP_FILL_BLOCK) { - dma_cap_set(DMA_MEMSET, dma->cap_mask); - dma->device_prep_dma_memset = ioat3_prep_memset_lock; - } if (cap & IOAT_CAP_XOR) { + is_raid_device = true; dma->max_xor = 8; dma->xor_align = 2; @@ -1151,6 +1146,7 @@ int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) dma->device_prep_dma_xor_val = ioat3_prep_xor_val; } if (cap & IOAT_CAP_PQ) { + is_raid_device = true; dma_set_maxpq(dma, 8, 0); dma->pq_align = 2; @@ -1171,6 +1167,21 @@ int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val; } } + if (is_raid_device && (cap & IOAT_CAP_FILL_BLOCK)) { + dma_cap_set(DMA_MEMSET, dma->cap_mask); + dma->device_prep_dma_memset = ioat3_prep_memset_lock; + } + + + if (is_raid_device) { + dma->device_is_tx_complete = ioat3_is_complete; + device->cleanup_tasklet = ioat3_cleanup_tasklet; + device->timer_fn = ioat3_timer_event; + } else { + dma->device_is_tx_complete = ioat2_is_complete; + device->cleanup_tasklet = ioat2_cleanup_tasklet; + device->timer_fn = ioat2_timer_event; + } /* -= IOAT ver.3 workarounds =- */ /* Write CHANERRMSK_INT with 3E07h to mask out the errors -- cgit v0.10.2 From 6506cbca6b5b36d682bd39afcbf3f575c81dddb6 Mon Sep 17 00:00:00 2001 From: Roland Dreier Date: Tue, 8 Sep 2009 17:43:03 -0700 Subject: Add MODULE_DEVICE_TABLE() so ioatdma module is autoloaded The ioatdma module is missing aliases for the PCI devices it supports, so it is not autoloaded on boot. Add a MODULE_DEVICE_TABLE() to get these aliases. Signed-off-by: Roland Dreier Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c index 6c1aac5..3b2f40e 100644 --- a/drivers/dma/ioat/pci.c +++ b/drivers/dma/ioat/pci.c @@ -73,6 +73,7 @@ static struct pci_device_id ioat_pci_tbl[] = { { 0, } }; +MODULE_DEVICE_TABLE(pci, ioat_pci_tbl); static int __devinit ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); -- cgit v0.10.2 From a6417dd58d6832f123f36c6f22c63ec1ab62ce1c Mon Sep 17 00:00:00 2001 From: Roland Dreier Date: Tue, 8 Sep 2009 17:43:03 -0700 Subject: I/OAT: Convert to PCI_VDEVICE() Trivial cleanup to make the PCI ID table easier to read. [dan.j.williams@intel.com: extended to v3.2 devices] Signed-off-by: Roland Dreier Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c index 3b2f40e..b77d3a2 100644 --- a/drivers/dma/ioat/pci.c +++ b/drivers/dma/ioat/pci.c @@ -41,35 +41,35 @@ MODULE_AUTHOR("Intel Corporation"); static struct pci_device_id ioat_pci_tbl[] = { /* I/OAT v1 platforms */ - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_CNB) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SCNB) }, - { PCI_DEVICE(PCI_VENDOR_ID_UNISYS, PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_CNB) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SCNB) }, + { PCI_VDEVICE(UNISYS, PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR) }, /* I/OAT v2 platforms */ - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB) }, /* I/OAT v3 platforms */ - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) }, /* I/OAT v3.2 platforms */ - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) }, { 0, } }; -- cgit v0.10.2 From e0bd0f8cb09cf3ccac1425f0f3a6705106c4d65c Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:53:02 -0700 Subject: dw_dmac: implement a private tx_list Drop dw_dmac's use of tx_list from struct dma_async_tx_descriptor in preparation for removal of this field. Cc: Haavard Skinnemoen Signed-off-by: Dan Williams diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c index 98c9a84..514ef7d 100644 --- a/drivers/dma/dw_dmac.c +++ b/drivers/dma/dw_dmac.c @@ -116,7 +116,7 @@ static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc) { struct dw_desc *child; - list_for_each_entry(child, &desc->txd.tx_list, desc_node) + list_for_each_entry(child, &desc->tx_list, desc_node) dma_sync_single_for_cpu(chan2parent(&dwc->chan), child->txd.phys, sizeof(child->lli), DMA_TO_DEVICE); @@ -137,11 +137,11 @@ static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) dwc_sync_desc_for_cpu(dwc, desc); spin_lock_bh(&dwc->lock); - list_for_each_entry(child, &desc->txd.tx_list, desc_node) + list_for_each_entry(child, &desc->tx_list, desc_node) dev_vdbg(chan2dev(&dwc->chan), "moving child desc %p to freelist\n", child); - list_splice_init(&desc->txd.tx_list, &dwc->free_list); + list_splice_init(&desc->tx_list, &dwc->free_list); dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); list_add(&desc->desc_node, &dwc->free_list); spin_unlock_bh(&dwc->lock); @@ -209,7 +209,7 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc) param = txd->callback_param; dwc_sync_desc_for_cpu(dwc, desc); - list_splice_init(&txd->tx_list, &dwc->free_list); + list_splice_init(&desc->tx_list, &dwc->free_list); list_move(&desc->desc_node, &dwc->free_list); /* @@ -289,7 +289,7 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) /* This one is currently in progress */ return; - list_for_each_entry(child, &desc->txd.tx_list, desc_node) + list_for_each_entry(child, &desc->tx_list, desc_node) if (child->lli.llp == llp) /* Currently in progress */ return; @@ -356,7 +356,7 @@ static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) dev_printk(KERN_CRIT, chan2dev(&dwc->chan), " cookie: %d\n", bad_desc->txd.cookie); dwc_dump_lli(dwc, &bad_desc->lli); - list_for_each_entry(child, &bad_desc->txd.tx_list, desc_node) + list_for_each_entry(child, &bad_desc->tx_list, desc_node) dwc_dump_lli(dwc, &child->lli); /* Pretend the descriptor completed successfully */ @@ -608,7 +608,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, prev->txd.phys, sizeof(prev->lli), DMA_TO_DEVICE); list_add_tail(&desc->desc_node, - &first->txd.tx_list); + &first->tx_list); } prev = desc; } @@ -700,7 +700,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, sizeof(prev->lli), DMA_TO_DEVICE); list_add_tail(&desc->desc_node, - &first->txd.tx_list); + &first->tx_list); } prev = desc; total_len += len; @@ -746,7 +746,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, sizeof(prev->lli), DMA_TO_DEVICE); list_add_tail(&desc->desc_node, - &first->txd.tx_list); + &first->tx_list); } prev = desc; total_len += len; @@ -902,6 +902,7 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan) break; } + INIT_LIST_HEAD(&desc->tx_list); dma_async_tx_descriptor_init(&desc->txd, chan); desc->txd.tx_submit = dwc_tx_submit; desc->txd.flags = DMA_CTRL_ACK; diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h index 13a5807..d9a939f 100644 --- a/drivers/dma/dw_dmac_regs.h +++ b/drivers/dma/dw_dmac_regs.h @@ -217,6 +217,7 @@ struct dw_desc { /* THEN values for driver housekeeping */ struct list_head desc_node; + struct list_head tx_list; struct dma_async_tx_descriptor txd; size_t len; }; -- cgit v0.10.2 From eda34234578fd822c950fd06b5c5ff7ac08b3001 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:53:02 -0700 Subject: fsldma: implement a private tx_list Drop fsldma's use of tx_list from struct dma_async_tx_descriptor in preparation for removal of this field. Cc: Li Yang Signed-off-by: Dan Williams diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index ef87a89..73dd748 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -326,7 +326,8 @@ static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable) static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) { struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan); - struct fsl_desc_sw *desc; + struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); + struct fsl_desc_sw *child; unsigned long flags; dma_cookie_t cookie; @@ -334,7 +335,7 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) spin_lock_irqsave(&fsl_chan->desc_lock, flags); cookie = fsl_chan->common.cookie; - list_for_each_entry(desc, &tx->tx_list, node) { + list_for_each_entry(child, &desc->tx_list, node) { cookie++; if (cookie < 0) cookie = 1; @@ -343,8 +344,8 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) } fsl_chan->common.cookie = cookie; - append_ld_queue(fsl_chan, tx_to_fsl_desc(tx)); - list_splice_init(&tx->tx_list, fsl_chan->ld_queue.prev); + append_ld_queue(fsl_chan, desc); + list_splice_init(&desc->tx_list, fsl_chan->ld_queue.prev); spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); @@ -366,6 +367,7 @@ static struct fsl_desc_sw *fsl_dma_alloc_descriptor( desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc); if (desc_sw) { memset(desc_sw, 0, sizeof(struct fsl_desc_sw)); + INIT_LIST_HEAD(&desc_sw->tx_list); dma_async_tx_descriptor_init(&desc_sw->async_tx, &fsl_chan->common); desc_sw->async_tx.tx_submit = fsl_dma_tx_submit; @@ -455,7 +457,7 @@ fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags) new->async_tx.flags = flags; /* Insert the link descriptor to the LD ring */ - list_add_tail(&new->node, &new->async_tx.tx_list); + list_add_tail(&new->node, &new->tx_list); /* Set End-of-link to the last link descriptor of new list*/ set_ld_eol(fsl_chan, new); @@ -513,7 +515,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( dma_dest += copy; /* Insert the link descriptor to the LD ring */ - list_add_tail(&new->node, &first->async_tx.tx_list); + list_add_tail(&new->node, &first->tx_list); } while (len); new->async_tx.flags = flags; /* client is in control of this ack */ @@ -528,7 +530,7 @@ fail: if (!first) return NULL; - list = &first->async_tx.tx_list; + list = &first->tx_list; list_for_each_entry_safe_reverse(new, prev, list, node) { list_del(&new->node); dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys); diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index dc7f268..4493afe 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -90,6 +90,7 @@ struct fsl_dma_ld_hw { struct fsl_desc_sw { struct fsl_dma_ld_hw hw; struct list_head node; + struct list_head tx_list; struct dma_async_tx_descriptor async_tx; struct list_head *ld; void *priv; -- cgit v0.10.2 From 308136d1abcb2d759bac40ed4f5d42ac4af59d8b Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:53:02 -0700 Subject: iop-adma: implement a private tx_list Drop iop-adma's use of tx_list from struct dma_async_tx_descriptor in preparation for removal of this field. Signed-off-by: Dan Williams diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h index 385c6e8..95dc133 100644 --- a/arch/arm/include/asm/hardware/iop_adma.h +++ b/arch/arm/include/asm/hardware/iop_adma.h @@ -86,6 +86,7 @@ struct iop_adma_chan { * @idx: pool index * @unmap_src_cnt: number of xor sources * @unmap_len: transaction bytecount + * @tx_list: list of descriptors that are associated with one operation * @async_tx: support for the async_tx api * @group_list: list of slots that make up a multi-descriptor transaction * for example transfer lengths larger than the supported hw max @@ -102,6 +103,7 @@ struct iop_adma_desc_slot { u16 idx; u16 unmap_src_cnt; size_t unmap_len; + struct list_head tx_list; struct dma_async_tx_descriptor async_tx; union { u32 *xor_check_result; diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index 2f05226..9f6c16f 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c @@ -370,7 +370,7 @@ retry: } alloc_tail->group_head = alloc_start; alloc_tail->async_tx.cookie = -EBUSY; - list_splice(&chain, &alloc_tail->async_tx.tx_list); + list_splice(&chain, &alloc_tail->tx_list); iop_chan->last_used = last_used; iop_desc_clear_next_desc(alloc_start); iop_desc_clear_next_desc(alloc_tail); @@ -429,7 +429,7 @@ iop_adma_tx_submit(struct dma_async_tx_descriptor *tx) old_chain_tail = list_entry(iop_chan->chain.prev, struct iop_adma_desc_slot, chain_node); - list_splice_init(&sw_desc->async_tx.tx_list, + list_splice_init(&sw_desc->tx_list, &old_chain_tail->chain_node); /* fix up the hardware chain */ @@ -496,6 +496,7 @@ static int iop_adma_alloc_chan_resources(struct dma_chan *chan) dma_async_tx_descriptor_init(&slot->async_tx, chan); slot->async_tx.tx_submit = iop_adma_tx_submit; + INIT_LIST_HEAD(&slot->tx_list); INIT_LIST_HEAD(&slot->chain_node); INIT_LIST_HEAD(&slot->slot_node); hw_desc = (char *) iop_chan->device->dma_desc_pool; @@ -1296,7 +1297,7 @@ static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan) if (sw_desc) { grp_start = sw_desc->group_head; - list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain); + list_splice_init(&sw_desc->tx_list, &iop_chan->chain); async_tx_ack(&sw_desc->async_tx); iop_desc_init_memcpy(grp_start, 0); iop_desc_set_byte_count(grp_start, iop_chan, 0); @@ -1352,7 +1353,7 @@ static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan) sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); if (sw_desc) { grp_start = sw_desc->group_head; - list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain); + list_splice_init(&sw_desc->tx_list, &iop_chan->chain); async_tx_ack(&sw_desc->async_tx); iop_desc_init_null_xor(grp_start, 2, 0); iop_desc_set_byte_count(grp_start, iop_chan, 0); -- cgit v0.10.2 From ea25968a32a621b02c3715d6b649f0c6ef53c24e Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:53:02 -0700 Subject: ioat: implement a private tx_list Drop ioatdma's use of tx_list from struct dma_async_tx_descriptor in preparation for removal of this field. Cc: Maciej Sosnowski Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 17a518d..21527b8 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -251,12 +251,12 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie); /* write address into NextDescriptor field of last desc in chain */ - first = to_ioat_desc(tx->tx_list.next); + first = to_ioat_desc(desc->tx_list.next); chain_tail = to_ioat_desc(ioat->used_desc.prev); /* make descriptor updates globally visible before chaining */ wmb(); chain_tail->hw->next = first->txd.phys; - list_splice_tail_init(&tx->tx_list, &ioat->used_desc); + list_splice_tail_init(&desc->tx_list, &ioat->used_desc); dump_desc_dbg(ioat, chain_tail); dump_desc_dbg(ioat, first); @@ -297,6 +297,7 @@ ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags) memset(desc, 0, sizeof(*desc)); + INIT_LIST_HEAD(&desc_sw->tx_list); dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common); desc_sw->txd.tx_submit = ioat1_tx_submit; desc_sw->hw = desc; @@ -521,7 +522,7 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, desc->txd.flags = flags; desc->len = total_len; - list_splice(&chain, &desc->txd.tx_list); + list_splice(&chain, &desc->tx_list); hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); hw->ctl_f.compl_write = 1; hw->tx_cnt = tx_cnt; diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index d9d6a7e..8966fa5 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -157,7 +157,7 @@ ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie, * struct ioat_desc_sw - wrapper around hardware descriptor * @hw: hardware DMA descriptor * @node: this descriptor will either be on the free list, - * or attached to a transaction list (async_tx.tx_list) + * or attached to a transaction list (tx_list) * @txd: the generic software descriptor for all engines * @id: identifier for debug */ @@ -165,6 +165,7 @@ struct ioat_desc_sw { struct ioat_dma_descriptor *hw; struct list_head node; size_t len; + struct list_head tx_list; struct dma_async_tx_descriptor txd; #ifdef DEBUG int id; -- cgit v0.10.2 From 64203b67274680e95e0c2eec935a22fc94e9ecb5 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:53:03 -0700 Subject: mv_xor: implement a private tx_list Drop mv_xor's use of tx_list from struct dma_async_tx_descriptor in preparation for removal of this field. Cc: Saeed Bishara Signed-off-by: Dan Williams diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index 3f23eab..466ab10 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -517,7 +517,7 @@ retry: } alloc_tail->group_head = alloc_start; alloc_tail->async_tx.cookie = -EBUSY; - list_splice(&chain, &alloc_tail->async_tx.tx_list); + list_splice(&chain, &alloc_tail->tx_list); mv_chan->last_used = last_used; mv_desc_clear_next_desc(alloc_start); mv_desc_clear_next_desc(alloc_tail); @@ -565,14 +565,14 @@ mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) cookie = mv_desc_assign_cookie(mv_chan, sw_desc); if (list_empty(&mv_chan->chain)) - list_splice_init(&sw_desc->async_tx.tx_list, &mv_chan->chain); + list_splice_init(&sw_desc->tx_list, &mv_chan->chain); else { new_hw_chain = 0; old_chain_tail = list_entry(mv_chan->chain.prev, struct mv_xor_desc_slot, chain_node); - list_splice_init(&grp_start->async_tx.tx_list, + list_splice_init(&grp_start->tx_list, &old_chain_tail->chain_node); if (!mv_can_chain(grp_start)) @@ -632,6 +632,7 @@ static int mv_xor_alloc_chan_resources(struct dma_chan *chan) slot->async_tx.tx_submit = mv_xor_tx_submit; INIT_LIST_HEAD(&slot->chain_node); INIT_LIST_HEAD(&slot->slot_node); + INIT_LIST_HEAD(&slot->tx_list); hw_desc = (char *) mv_chan->device->dma_desc_pool; slot->async_tx.phys = (dma_addr_t) &hw_desc[idx * MV_XOR_SLOT_SIZE]; diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h index 06cafe1e..977b592 100644 --- a/drivers/dma/mv_xor.h +++ b/drivers/dma/mv_xor.h @@ -126,9 +126,8 @@ struct mv_xor_chan { * @idx: pool index * @unmap_src_cnt: number of xor sources * @unmap_len: transaction bytecount + * @tx_list: list of slots that make up a multi-descriptor transaction * @async_tx: support for the async_tx api - * @group_list: list of slots that make up a multi-descriptor transaction - * for example transfer lengths larger than the supported hw max * @xor_check_result: result of zero sum * @crc32_result: result crc calculation */ @@ -145,6 +144,7 @@ struct mv_xor_desc_slot { u16 unmap_src_cnt; u32 value; size_t unmap_len; + struct list_head tx_list; struct dma_async_tx_descriptor async_tx; union { u32 *xor_check_result; -- cgit v0.10.2 From 285a3c71640ad7101b7237b8fbaa4ead22c6551c Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:53:03 -0700 Subject: at_hdmac: implement a private tx_list Drop at_hdmac's use of tx_list from struct dma_async_tx_descriptor in preparation for removal of this field. Cc: Nicolas Ferre Signed-off-by: Dan Williams diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index 9a1e5fb..da4e8b7 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -87,6 +87,7 @@ static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); if (desc) { memset(desc, 0, sizeof(struct at_desc)); + INIT_LIST_HEAD(&desc->tx_list); dma_async_tx_descriptor_init(&desc->txd, chan); /* txd.flags will be overwritten in prep functions */ desc->txd.flags = DMA_CTRL_ACK; @@ -150,11 +151,11 @@ static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) struct at_desc *child; spin_lock_bh(&atchan->lock); - list_for_each_entry(child, &desc->txd.tx_list, desc_node) + list_for_each_entry(child, &desc->tx_list, desc_node) dev_vdbg(chan2dev(&atchan->chan_common), "moving child desc %p to freelist\n", child); - list_splice_init(&desc->txd.tx_list, &atchan->free_list); + list_splice_init(&desc->tx_list, &atchan->free_list); dev_vdbg(chan2dev(&atchan->chan_common), "moving desc %p to freelist\n", desc); list_add(&desc->desc_node, &atchan->free_list); @@ -247,7 +248,7 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) param = txd->callback_param; /* move children to free_list */ - list_splice_init(&txd->tx_list, &atchan->free_list); + list_splice_init(&desc->tx_list, &atchan->free_list); /* move myself to free_list */ list_move(&desc->desc_node, &atchan->free_list); @@ -334,7 +335,7 @@ static void atc_cleanup_descriptors(struct at_dma_chan *atchan) /* This one is currently in progress */ return; - list_for_each_entry(child, &desc->txd.tx_list, desc_node) + list_for_each_entry(child, &desc->tx_list, desc_node) if (!(child->lli.ctrla & ATC_DONE)) /* Currently in progress */ return; @@ -407,7 +408,7 @@ static void atc_handle_error(struct at_dma_chan *atchan) dev_crit(chan2dev(&atchan->chan_common), " cookie: %d\n", bad_desc->txd.cookie); atc_dump_lli(atchan, &bad_desc->lli); - list_for_each_entry(child, &bad_desc->txd.tx_list, desc_node) + list_for_each_entry(child, &bad_desc->tx_list, desc_node) atc_dump_lli(atchan, &child->lli); /* Pretend the descriptor completed successfully */ @@ -587,7 +588,7 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, prev->lli.dscr = desc->txd.phys; /* insert the link descriptor to the LD ring */ list_add_tail(&desc->desc_node, - &first->txd.tx_list); + &first->tx_list); } prev = desc; } @@ -687,7 +688,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, prev->lli.dscr = desc->txd.phys; /* insert the link descriptor to the LD ring */ list_add_tail(&desc->desc_node, - &first->txd.tx_list); + &first->tx_list); } prev = desc; total_len += len; @@ -729,7 +730,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, prev->lli.dscr = desc->txd.phys; /* insert the link descriptor to the LD ring */ list_add_tail(&desc->desc_node, - &first->txd.tx_list); + &first->tx_list); } prev = desc; total_len += len; diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h index 4c972af..495457e 100644 --- a/drivers/dma/at_hdmac_regs.h +++ b/drivers/dma/at_hdmac_regs.h @@ -165,6 +165,7 @@ struct at_desc { struct at_lli lli; /* THEN values for driver housekeeping */ + struct list_head tx_list; struct dma_async_tx_descriptor txd; struct list_head desc_node; size_t len; -- cgit v0.10.2 From 1979b186b80449ac6574d97c254b694c8a99b703 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:53:03 -0700 Subject: txx9dmac: implement a private tx_list Drop txx9dmac's use of tx_list from struct dma_async_tx_descriptor in preparation for removal of this field. Cc: Atsushi Nemoto Signed-off-by: Dan Williams diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c index 88dab52..197c7bc 100644 --- a/drivers/dma/txx9dmac.c +++ b/drivers/dma/txx9dmac.c @@ -180,9 +180,8 @@ static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc) static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc) { - if (!list_empty(&desc->txd.tx_list)) - desc = list_entry(desc->txd.tx_list.prev, - struct txx9dmac_desc, desc_node); + if (!list_empty(&desc->tx_list)) + desc = list_entry(desc->tx_list.prev, typeof(*desc), desc_node); return desc; } @@ -197,6 +196,7 @@ static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc, desc = kzalloc(sizeof(*desc), flags); if (!desc) return NULL; + INIT_LIST_HEAD(&desc->tx_list); dma_async_tx_descriptor_init(&desc->txd, &dc->chan); desc->txd.tx_submit = txx9dmac_tx_submit; /* txd.flags will be overwritten in prep funcs */ @@ -245,7 +245,7 @@ static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc, struct txx9dmac_dev *ddev = dc->ddev; struct txx9dmac_desc *child; - list_for_each_entry(child, &desc->txd.tx_list, desc_node) + list_for_each_entry(child, &desc->tx_list, desc_node) dma_sync_single_for_cpu(chan2parent(&dc->chan), child->txd.phys, ddev->descsize, DMA_TO_DEVICE); @@ -267,11 +267,11 @@ static void txx9dmac_desc_put(struct txx9dmac_chan *dc, txx9dmac_sync_desc_for_cpu(dc, desc); spin_lock_bh(&dc->lock); - list_for_each_entry(child, &desc->txd.tx_list, desc_node) + list_for_each_entry(child, &desc->tx_list, desc_node) dev_vdbg(chan2dev(&dc->chan), "moving child desc %p to freelist\n", child); - list_splice_init(&desc->txd.tx_list, &dc->free_list); + list_splice_init(&desc->tx_list, &dc->free_list); dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n", desc); list_add(&desc->desc_node, &dc->free_list); @@ -429,7 +429,7 @@ txx9dmac_descriptor_complete(struct txx9dmac_chan *dc, param = txd->callback_param; txx9dmac_sync_desc_for_cpu(dc, desc); - list_splice_init(&txd->tx_list, &dc->free_list); + list_splice_init(&desc->tx_list, &dc->free_list); list_move(&desc->desc_node, &dc->free_list); if (!ds) { @@ -571,7 +571,7 @@ static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr) "Bad descriptor submitted for DMA! (cookie: %d)\n", bad_desc->txd.cookie); txx9dmac_dump_desc(dc, &bad_desc->hwdesc); - list_for_each_entry(child, &bad_desc->txd.tx_list, desc_node) + list_for_each_entry(child, &bad_desc->tx_list, desc_node) txx9dmac_dump_desc(dc, &child->hwdesc); /* Pretend the descriptor completed successfully */ txx9dmac_descriptor_complete(dc, bad_desc); @@ -613,7 +613,7 @@ static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc) return; } - list_for_each_entry(child, &desc->txd.tx_list, desc_node) + list_for_each_entry(child, &desc->tx_list, desc_node) if (desc_read_CHAR(dc, child) == chain) { /* Currently in progress */ if (csr & TXX9_DMA_CSR_ABCHC) @@ -823,8 +823,7 @@ txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, dma_sync_single_for_device(chan2parent(&dc->chan), prev->txd.phys, ddev->descsize, DMA_TO_DEVICE); - list_add_tail(&desc->desc_node, - &first->txd.tx_list); + list_add_tail(&desc->desc_node, &first->tx_list); } prev = desc; } @@ -919,8 +918,7 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, prev->txd.phys, ddev->descsize, DMA_TO_DEVICE); - list_add_tail(&desc->desc_node, - &first->txd.tx_list); + list_add_tail(&desc->desc_node, &first->tx_list); } prev = desc; } diff --git a/drivers/dma/txx9dmac.h b/drivers/dma/txx9dmac.h index c907ff0..365d423 100644 --- a/drivers/dma/txx9dmac.h +++ b/drivers/dma/txx9dmac.h @@ -231,6 +231,7 @@ struct txx9dmac_desc { /* THEN values for driver housekeeping */ struct list_head desc_node ____cacheline_aligned; + struct list_head tx_list; struct dma_async_tx_descriptor txd; size_t len; }; -- cgit v0.10.2 From 0803172778901e24a75ab074798d98c2b7411559 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:53:04 -0700 Subject: dmaengine: kill tx_list The tx_list attribute of struct dma_async_tx_descriptor is common to most, but not all dma driver implementations. None of the upper level code (dmaengine/async_tx) uses it, so allow drivers to implement it locally if they need it. This saves sizeof(struct list_head) bytes for drivers that do not manage descriptors with a linked list (e.g.: ioatdma v2,3). Signed-off-by: Dan Williams diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 5a87384..562d182 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -933,7 +933,6 @@ void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, { tx->chan = chan; spin_lock_init(&tx->lock); - INIT_LIST_HEAD(&tx->tx_list); } EXPORT_SYMBOL(dma_async_tx_descriptor_init); diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index ffefba8..f114bc7 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -180,8 +180,6 @@ typedef void (*dma_async_tx_callback)(void *dma_async_param); * @flags: flags to augment operation preparation, control completion, and * communicate status * @phys: physical address of the descriptor - * @tx_list: driver common field for operations that require multiple - * descriptors * @chan: target channel for this operation * @tx_submit: set the prepared descriptor(s) to be executed by the engine * @callback: routine to call after this operation is complete @@ -195,7 +193,6 @@ struct dma_async_tx_descriptor { dma_cookie_t cookie; enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ dma_addr_t phys; - struct list_head tx_list; struct dma_chan *chan; dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); dma_async_tx_callback callback; -- cgit v0.10.2 From 162b96e63e518aa6ff029ce23de12d7f027483bf Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 17:53:04 -0700 Subject: ioat2,3: cacheline align software descriptor allocations All the necessary fields for handling an ioat2,3 ring entry can fit into one cacheline. Move ->len prior to ->txd in struct ioat_ring_ent, and move allocation of these entries to a hw-cache-aligned kmem cache to reduce the number of cachelines dirtied for descriptor management. Signed-off-by: Dan Williams diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 460b773..fa3d6db 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -399,11 +399,12 @@ static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan, gfp_t f return NULL; memset(hw, 0, sizeof(*hw)); - desc = kzalloc(sizeof(*desc), flags); + desc = kmem_cache_alloc(ioat2_cache, flags); if (!desc) { pci_pool_free(dma->dma_pool, hw, phys); return NULL; } + memset(desc, 0, sizeof(*desc)); dma_async_tx_descriptor_init(&desc->txd, chan); desc->txd.tx_submit = ioat2_tx_submit_unlock; @@ -418,7 +419,7 @@ static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *cha dma = to_ioatdma_device(chan->device); pci_pool_free(dma->dma_pool, desc->hw, desc->txd.phys); - kfree(desc); + kmem_cache_free(ioat2_cache, desc); } static struct ioat_ring_ent **ioat2_alloc_ring(struct dma_chan *c, int order, gfp_t flags) diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h index 9baa3d6..ac00adc 100644 --- a/drivers/dma/ioat/dma_v2.h +++ b/drivers/dma/ioat/dma_v2.h @@ -116,8 +116,8 @@ static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len struct ioat_ring_ent { struct ioat_dma_descriptor *hw; - struct dma_async_tx_descriptor txd; size_t len; + struct dma_async_tx_descriptor txd; #ifdef DEBUG int id; #endif @@ -143,4 +143,5 @@ int __devinit ioat2_dma_probe(struct ioatdma_device *dev, int dca); int __devinit ioat3_dma_probe(struct ioatdma_device *dev, int dca); struct dca_provider * __devinit ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); struct dca_provider * __devinit ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase); +extern struct kmem_cache *ioat2_cache; #endif /* IOATDMA_V2_H */ diff --git a/drivers/dma/ioat/pci.c b/drivers/dma/ioat/pci.c index c4e4322..61086c6 100644 --- a/drivers/dma/ioat/pci.c +++ b/drivers/dma/ioat/pci.c @@ -69,6 +69,8 @@ static int ioat_dca_enabled = 1; module_param(ioat_dca_enabled, int, 0644); MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)"); +struct kmem_cache *ioat2_cache; + #define DRV_NAME "ioatdma" static struct pci_driver ioat_pci_driver = { @@ -168,12 +170,24 @@ static void __devexit ioat_remove(struct pci_dev *pdev) static int __init ioat_init_module(void) { - return pci_register_driver(&ioat_pci_driver); + int err; + + ioat2_cache = kmem_cache_create("ioat2", sizeof(struct ioat_ring_ent), + 0, SLAB_HWCACHE_ALIGN, NULL); + if (!ioat2_cache) + return -ENOMEM; + + err = pci_register_driver(&ioat_pci_driver); + if (err) + kmem_cache_destroy(ioat2_cache); + + return err; } module_init(ioat_init_module); static void __exit ioat_exit_module(void) { pci_unregister_driver(&ioat_pci_driver); + kmem_cache_destroy(ioat2_cache); } module_exit(ioat_exit_module); -- cgit v0.10.2 From e6c7ecb64e08ef346cb7062b4a5421f00bc602bd Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Tue, 8 Sep 2009 17:53:04 -0700 Subject: fsldma: split apart external pause and request count features When using the Freescale DMA controller in external control mode, both the request count and external pause bits need to be setup correctly. This was being done with the same function. The 83xx controller lacks the external pause feature, but has a similar feature called external start. This feature requires that the request count bits be setup correctly. Split the function into two parts, to make it possible to use the external start feature on the 83xx controller. Signed-off-by: Ira W. Snyder Signed-off-by: Dan Williams diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 73dd748..7a0cb60 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -280,28 +280,40 @@ static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size) } /** - * fsl_chan_toggle_ext_pause - Toggle channel external pause status + * fsl_chan_set_request_count - Set DMA Request Count for external control * @fsl_chan : Freescale DMA channel - * @size : Pause control size, 0 for disable external pause control. - * The maximum is 1024. + * @size : Number of bytes to transfer in a single request + * + * The Freescale DMA channel can be controlled by the external signal DREQ#. + * The DMA request count is how many bytes are allowed to transfer before + * pausing the channel, after which a new assertion of DREQ# resumes channel + * operation. * - * The Freescale DMA channel can be controlled by the external - * signal DREQ#. The pause control size is how many bytes are allowed - * to transfer before pausing the channel, after which a new assertion - * of DREQ# resumes channel operation. + * A size of 0 disables external pause control. The maximum size is 1024. */ -static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size) +static void fsl_chan_set_request_count(struct fsl_dma_chan *fsl_chan, int size) { - if (size > 1024) - return; + BUG_ON(size > 1024); + DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, + DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) + | ((__ilog2(size) << 24) & 0x0f000000), + 32); +} - if (size) { - DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, - DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) - | ((__ilog2(size) << 24) & 0x0f000000), - 32); +/** + * fsl_chan_toggle_ext_pause - Toggle channel external pause status + * @fsl_chan : Freescale DMA channel + * @enable : 0 is disabled, 1 is enabled. + * + * The Freescale DMA channel can be controlled by the external signal DREQ#. + * The DMA Request Count feature should be used in addition to this feature + * to set the number of bytes to transfer before pausing the channel. + */ +static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int enable) +{ + if (enable) fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; - } else + else fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; } @@ -885,6 +897,7 @@ static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev, new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start; new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size; new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size; + new_fsl_chan->set_request_count = fsl_chan_set_request_count; } spin_lock_init(&new_fsl_chan->desc_lock); diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index 4493afe..0df14cb 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -144,10 +144,11 @@ struct fsl_dma_chan { struct tasklet_struct tasklet; u32 feature; - void (*toggle_ext_pause)(struct fsl_dma_chan *fsl_chan, int size); + void (*toggle_ext_pause)(struct fsl_dma_chan *fsl_chan, int enable); void (*toggle_ext_start)(struct fsl_dma_chan *fsl_chan, int enable); void (*set_src_loop_size)(struct fsl_dma_chan *fsl_chan, int size); void (*set_dest_loop_size)(struct fsl_dma_chan *fsl_chan, int size); + void (*set_request_count)(struct fsl_dma_chan *fsl_chan, int size); }; #define to_fsl_chan(chan) container_of(chan, struct fsl_dma_chan, common) -- cgit v0.10.2 From bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7d Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Tue, 8 Sep 2009 17:53:04 -0700 Subject: fsldma: Add DMA_SLAVE support Use the DMA_SLAVE capability of the DMAEngine API to copy/from a scatterlist into an arbitrary list of hardware address/length pairs. This allows a single DMA transaction to copy data from several different devices into a scatterlist at the same time. This also adds support to enable some controller-specific features such as external start and external pause for a DMA transaction. [dan.j.williams@intel.com: rebased on tx_list movement] Signed-off-by: Ira W. Snyder Acked-by: Li Yang Acked-by: Kumar Gala Signed-off-by: Dan Williams diff --git a/arch/powerpc/include/asm/fsldma.h b/arch/powerpc/include/asm/fsldma.h new file mode 100644 index 0000000..a67aeed --- /dev/null +++ b/arch/powerpc/include/asm/fsldma.h @@ -0,0 +1,136 @@ +/* + * Freescale MPC83XX / MPC85XX DMA Controller + * + * Copyright (c) 2009 Ira W. Snyder + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __ARCH_POWERPC_ASM_FSLDMA_H__ +#define __ARCH_POWERPC_ASM_FSLDMA_H__ + +#include + +/* + * Definitions for the Freescale DMA controller's DMA_SLAVE implemention + * + * The Freescale DMA_SLAVE implementation was designed to handle many-to-many + * transfers. An example usage would be an accelerated copy between two + * scatterlists. Another example use would be an accelerated copy from + * multiple non-contiguous device buffers into a single scatterlist. + * + * A DMA_SLAVE transaction is defined by a struct fsl_dma_slave. This + * structure contains a list of hardware addresses that should be copied + * to/from the scatterlist passed into device_prep_slave_sg(). The structure + * also has some fields to enable hardware-specific features. + */ + +/** + * struct fsl_dma_hw_addr + * @entry: linked list entry + * @address: the hardware address + * @length: length to transfer + * + * Holds a single physical hardware address / length pair for use + * with the DMAEngine DMA_SLAVE API. + */ +struct fsl_dma_hw_addr { + struct list_head entry; + + dma_addr_t address; + size_t length; +}; + +/** + * struct fsl_dma_slave + * @addresses: a linked list of struct fsl_dma_hw_addr structures + * @request_count: value for DMA request count + * @src_loop_size: setup and enable constant source-address DMA transfers + * @dst_loop_size: setup and enable constant destination address DMA transfers + * @external_start: enable externally started DMA transfers + * @external_pause: enable externally paused DMA transfers + * + * Holds a list of address / length pairs for use with the DMAEngine + * DMA_SLAVE API implementation for the Freescale DMA controller. + */ +struct fsl_dma_slave { + + /* List of hardware address/length pairs */ + struct list_head addresses; + + /* Support for extra controller features */ + unsigned int request_count; + unsigned int src_loop_size; + unsigned int dst_loop_size; + bool external_start; + bool external_pause; +}; + +/** + * fsl_dma_slave_append - add an address/length pair to a struct fsl_dma_slave + * @slave: the &struct fsl_dma_slave to add to + * @address: the hardware address to add + * @length: the length of bytes to transfer from @address + * + * Add a hardware address/length pair to a struct fsl_dma_slave. Returns 0 on + * success, -ERRNO otherwise. + */ +static inline int fsl_dma_slave_append(struct fsl_dma_slave *slave, + dma_addr_t address, size_t length) +{ + struct fsl_dma_hw_addr *addr; + + addr = kzalloc(sizeof(*addr), GFP_ATOMIC); + if (!addr) + return -ENOMEM; + + INIT_LIST_HEAD(&addr->entry); + addr->address = address; + addr->length = length; + + list_add_tail(&addr->entry, &slave->addresses); + return 0; +} + +/** + * fsl_dma_slave_free - free a struct fsl_dma_slave + * @slave: the struct fsl_dma_slave to free + * + * Free a struct fsl_dma_slave and all associated address/length pairs + */ +static inline void fsl_dma_slave_free(struct fsl_dma_slave *slave) +{ + struct fsl_dma_hw_addr *addr, *tmp; + + if (slave) { + list_for_each_entry_safe(addr, tmp, &slave->addresses, entry) { + list_del(&addr->entry); + kfree(addr); + } + + kfree(slave); + } +} + +/** + * fsl_dma_slave_alloc - allocate a struct fsl_dma_slave + * @gfp: the flags to pass to kmalloc when allocating this structure + * + * Allocate a struct fsl_dma_slave for use by the DMA_SLAVE API. Returns a new + * struct fsl_dma_slave on success, or NULL on failure. + */ +static inline struct fsl_dma_slave *fsl_dma_slave_alloc(gfp_t gfp) +{ + struct fsl_dma_slave *slave; + + slave = kzalloc(sizeof(*slave), gfp); + if (!slave) + return NULL; + + INIT_LIST_HEAD(&slave->addresses); + return slave; +} + +#endif /* __ARCH_POWERPC_ASM_FSLDMA_H__ */ diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 7a0cb60..296f9e7 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -34,6 +34,7 @@ #include #include +#include #include "fsldma.h" static void dma_init(struct fsl_dma_chan *fsl_chan) @@ -552,6 +553,229 @@ fail: } /** + * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction + * @chan: DMA channel + * @sgl: scatterlist to transfer to/from + * @sg_len: number of entries in @scatterlist + * @direction: DMA direction + * @flags: DMAEngine flags + * + * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the + * DMA_SLAVE API, this gets the device-specific information from the + * chan->private variable. + */ +static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( + struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, + enum dma_data_direction direction, unsigned long flags) +{ + struct fsl_dma_chan *fsl_chan; + struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; + struct fsl_dma_slave *slave; + struct list_head *tx_list; + size_t copy; + + int i; + struct scatterlist *sg; + size_t sg_used; + size_t hw_used; + struct fsl_dma_hw_addr *hw; + dma_addr_t dma_dst, dma_src; + + if (!chan) + return NULL; + + if (!chan->private) + return NULL; + + fsl_chan = to_fsl_chan(chan); + slave = chan->private; + + if (list_empty(&slave->addresses)) + return NULL; + + hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry); + hw_used = 0; + + /* + * Build the hardware transaction to copy from the scatterlist to + * the hardware, or from the hardware to the scatterlist + * + * If you are copying from the hardware to the scatterlist and it + * takes two hardware entries to fill an entire page, then both + * hardware entries will be coalesced into the same page + * + * If you are copying from the scatterlist to the hardware and a + * single page can fill two hardware entries, then the data will + * be read out of the page into the first hardware entry, and so on + */ + for_each_sg(sgl, sg, sg_len, i) { + sg_used = 0; + + /* Loop until the entire scatterlist entry is used */ + while (sg_used < sg_dma_len(sg)) { + + /* + * If we've used up the current hardware address/length + * pair, we need to load a new one + * + * This is done in a while loop so that descriptors with + * length == 0 will be skipped + */ + while (hw_used >= hw->length) { + + /* + * If the current hardware entry is the last + * entry in the list, we're finished + */ + if (list_is_last(&hw->entry, &slave->addresses)) + goto finished; + + /* Get the next hardware address/length pair */ + hw = list_entry(hw->entry.next, + struct fsl_dma_hw_addr, entry); + hw_used = 0; + } + + /* Allocate the link descriptor from DMA pool */ + new = fsl_dma_alloc_descriptor(fsl_chan); + if (!new) { + dev_err(fsl_chan->dev, "No free memory for " + "link descriptor\n"); + goto fail; + } +#ifdef FSL_DMA_LD_DEBUG + dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new); +#endif + + /* + * Calculate the maximum number of bytes to transfer, + * making sure it is less than the DMA controller limit + */ + copy = min_t(size_t, sg_dma_len(sg) - sg_used, + hw->length - hw_used); + copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT); + + /* + * DMA_FROM_DEVICE + * from the hardware to the scatterlist + * + * DMA_TO_DEVICE + * from the scatterlist to the hardware + */ + if (direction == DMA_FROM_DEVICE) { + dma_src = hw->address + hw_used; + dma_dst = sg_dma_address(sg) + sg_used; + } else { + dma_src = sg_dma_address(sg) + sg_used; + dma_dst = hw->address + hw_used; + } + + /* Fill in the descriptor */ + set_desc_cnt(fsl_chan, &new->hw, copy); + set_desc_src(fsl_chan, &new->hw, dma_src); + set_desc_dest(fsl_chan, &new->hw, dma_dst); + + /* + * If this is not the first descriptor, chain the + * current descriptor after the previous descriptor + */ + if (!first) { + first = new; + } else { + set_desc_next(fsl_chan, &prev->hw, + new->async_tx.phys); + } + + new->async_tx.cookie = 0; + async_tx_ack(&new->async_tx); + + prev = new; + sg_used += copy; + hw_used += copy; + + /* Insert the link descriptor into the LD ring */ + list_add_tail(&new->node, &first->tx_list); + } + } + +finished: + + /* All of the hardware address/length pairs had length == 0 */ + if (!first || !new) + return NULL; + + new->async_tx.flags = flags; + new->async_tx.cookie = -EBUSY; + + /* Set End-of-link to the last link descriptor of new list */ + set_ld_eol(fsl_chan, new); + + /* Enable extra controller features */ + if (fsl_chan->set_src_loop_size) + fsl_chan->set_src_loop_size(fsl_chan, slave->src_loop_size); + + if (fsl_chan->set_dest_loop_size) + fsl_chan->set_dest_loop_size(fsl_chan, slave->dst_loop_size); + + if (fsl_chan->toggle_ext_start) + fsl_chan->toggle_ext_start(fsl_chan, slave->external_start); + + if (fsl_chan->toggle_ext_pause) + fsl_chan->toggle_ext_pause(fsl_chan, slave->external_pause); + + if (fsl_chan->set_request_count) + fsl_chan->set_request_count(fsl_chan, slave->request_count); + + return &first->async_tx; + +fail: + /* If first was not set, then we failed to allocate the very first + * descriptor, and we're done */ + if (!first) + return NULL; + + /* + * First is set, so all of the descriptors we allocated have been added + * to first->tx_list, INCLUDING "first" itself. Therefore we + * must traverse the list backwards freeing each descriptor in turn + * + * We're re-using variables for the loop, oh well + */ + tx_list = &first->tx_list; + list_for_each_entry_safe_reverse(new, prev, tx_list, node) { + list_del_init(&new->node); + dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys); + } + + return NULL; +} + +static void fsl_dma_device_terminate_all(struct dma_chan *chan) +{ + struct fsl_dma_chan *fsl_chan; + struct fsl_desc_sw *desc, *tmp; + unsigned long flags; + + if (!chan) + return; + + fsl_chan = to_fsl_chan(chan); + + /* Halt the DMA engine */ + dma_halt(fsl_chan); + + spin_lock_irqsave(&fsl_chan->desc_lock, flags); + + /* Remove and free all of the descriptors in the LD queue */ + list_for_each_entry_safe(desc, tmp, &fsl_chan->ld_queue, node) { + list_del(&desc->node); + dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); + } + + spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); +} + +/** * fsl_dma_update_completed_cookie - Update the completed cookie. * @fsl_chan : Freescale DMA channel */ @@ -977,12 +1201,15 @@ static int __devinit of_fsl_dma_probe(struct of_device *dev, dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); + dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; fdev->common.device_is_tx_complete = fsl_dma_is_complete; fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; + fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; + fdev->common.device_terminate_all = fsl_dma_device_terminate_all; fdev->common.dev = &dev->dev; fdev->irq = irq_of_parse_and_map(dev->node, 0); -- cgit v0.10.2 From 657a77fa7284d8ae28dfa48f1dc5d919bf5b2843 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Tue, 8 Sep 2009 17:53:05 -0700 Subject: dmaengine: Move all map_sg/unmap_sg for slave channel to its client Dan Williams wrote: ... DMA-slave clients request specific channels and know the hardware details at a low level, so it should not be too high an expectation to push dma mapping responsibility to the client. Also this patch includes DMA_COMPL_{SRC,DEST}_UNMAP_SINGLE support for dw_dmac driver. Acked-by: Maciej Sosnowski Acked-by: Nicolas Ferre Signed-off-by: Atsushi Nemoto Signed-off-by: Dan Williams diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index da4e8b7..0aeb578 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -253,25 +253,28 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) list_move(&desc->desc_node, &atchan->free_list); /* unmap dma addresses */ - if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { - if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) - dma_unmap_single(chan2parent(&atchan->chan_common), - desc->lli.daddr, - desc->len, DMA_FROM_DEVICE); - else - dma_unmap_page(chan2parent(&atchan->chan_common), - desc->lli.daddr, - desc->len, DMA_FROM_DEVICE); - } - if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { - if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) - dma_unmap_single(chan2parent(&atchan->chan_common), - desc->lli.saddr, - desc->len, DMA_TO_DEVICE); - else - dma_unmap_page(chan2parent(&atchan->chan_common), - desc->lli.saddr, - desc->len, DMA_TO_DEVICE); + if (!atchan->chan_common.private) { + struct device *parent = chan2parent(&atchan->chan_common); + if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { + if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) + dma_unmap_single(parent, + desc->lli.daddr, + desc->len, DMA_FROM_DEVICE); + else + dma_unmap_page(parent, + desc->lli.daddr, + desc->len, DMA_FROM_DEVICE); + } + if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { + if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) + dma_unmap_single(parent, + desc->lli.saddr, + desc->len, DMA_TO_DEVICE); + else + dma_unmap_page(parent, + desc->lli.saddr, + desc->len, DMA_TO_DEVICE); + } } /* @@ -647,8 +650,6 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, reg_width = atslave->reg_width; - sg_len = dma_map_sg(chan2parent(chan), sgl, sg_len, direction); - ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla; ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN; diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c index 514ef7d..8fb7482 100644 --- a/drivers/dma/dw_dmac.c +++ b/drivers/dma/dw_dmac.c @@ -212,16 +212,25 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc) list_splice_init(&desc->tx_list, &dwc->free_list); list_move(&desc->desc_node, &dwc->free_list); - /* - * We use dma_unmap_page() regardless of how the buffers were - * mapped before they were submitted... - */ - if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) - dma_unmap_page(chan2parent(&dwc->chan), desc->lli.dar, - desc->len, DMA_FROM_DEVICE); - if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) - dma_unmap_page(chan2parent(&dwc->chan), desc->lli.sar, - desc->len, DMA_TO_DEVICE); + if (!dwc->chan.private) { + struct device *parent = chan2parent(&dwc->chan); + if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { + if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) + dma_unmap_single(parent, desc->lli.dar, + desc->len, DMA_FROM_DEVICE); + else + dma_unmap_page(parent, desc->lli.dar, + desc->len, DMA_FROM_DEVICE); + } + if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { + if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) + dma_unmap_single(parent, desc->lli.sar, + desc->len, DMA_TO_DEVICE); + else + dma_unmap_page(parent, desc->lli.sar, + desc->len, DMA_TO_DEVICE); + } + } /* * The API requires that no submissions are done from a @@ -658,8 +667,6 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, reg_width = dws->reg_width; prev = first = NULL; - sg_len = dma_map_sg(chan2parent(chan), sgl, sg_len, direction); - switch (direction) { case DMA_TO_DEVICE: ctllo = (DWC_DEFAULT_CTLLO diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c index 7b603e4..5e10d36 100644 --- a/drivers/mmc/host/atmel-mci.c +++ b/drivers/mmc/host/atmel-mci.c @@ -576,6 +576,7 @@ atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) struct scatterlist *sg; unsigned int i; enum dma_data_direction direction; + unsigned int sglen; /* * We don't do DMA on "complex" transfers, i.e. with @@ -605,11 +606,14 @@ atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) else direction = DMA_TO_DEVICE; + sglen = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, direction); + if (sglen != data->sg_len) + goto unmap_exit; desc = chan->device->device_prep_slave_sg(chan, data->sg, data->sg_len, direction, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); if (!desc) - return -ENOMEM; + goto unmap_exit; host->dma.data_desc = desc; desc->callback = atmci_dma_complete; @@ -620,6 +624,9 @@ atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) chan->device->device_issue_pending(chan); return 0; +unmap_exit: + dma_unmap_sg(&host->pdev->dev, data->sg, sglen, direction); + return -ENOMEM; } #else /* CONFIG_MMC_ATMELMCI_DMA */ -- cgit v0.10.2 From d8902adcc1a9fd484c8cb5e575152e32192c1ff8 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 7 Sep 2009 03:26:23 +0000 Subject: dmaengine: sh: Add Support SuperH DMA Engine driver This supported all DMA channels, and it was tested in SH7722, SH7780, SH7785 and SH7763. This can not use with SH DMA API. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Matt Fleming Acked-by: Maciej Sosnowski Acked-by: Paul Mundt Signed-off-by: Dan Williams diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig index 63e9dd3..f935a7e 100644 --- a/arch/sh/drivers/dma/Kconfig +++ b/arch/sh/drivers/dma/Kconfig @@ -1,12 +1,9 @@ menu "DMA support" -config SH_DMA_API - bool config SH_DMA bool "SuperH on-chip DMA controller (DMAC) support" depends on CPU_SH3 || CPU_SH4 - select SH_DMA_API default n config SH_DMA_IRQ_MULTI @@ -19,6 +16,15 @@ config SH_DMA_IRQ_MULTI CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || \ CPU_SUBTYPE_SH7760 +config SH_DMA_API + depends on SH_DMA + bool "SuperH DMA API support" + default n + help + SH_DMA_API always enabled DMA API of used SuperH. + If you want to use DMA ENGINE, you must not enable this. + Please enable DMA_ENGINE and SH_DMAE. + config NR_ONCHIP_DMA_CHANNELS int depends on SH_DMA diff --git a/arch/sh/drivers/dma/Makefile b/arch/sh/drivers/dma/Makefile index c606813..d88c948 100644 --- a/arch/sh/drivers/dma/Makefile +++ b/arch/sh/drivers/dma/Makefile @@ -2,8 +2,7 @@ # Makefile for the SuperH DMA specific kernel interface routines under Linux. # -obj-$(CONFIG_SH_DMA_API) += dma-api.o dma-sysfs.o -obj-$(CONFIG_SH_DMA) += dma-sh.o +obj-$(CONFIG_SH_DMA_API) += dma-sh.o dma-api.o dma-sysfs.o obj-$(CONFIG_PVR2_DMA) += dma-pvr2.o obj-$(CONFIG_G2_DMA) += dma-g2.o obj-$(CONFIG_SH_DMABRG) += dmabrg.o diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h index 0c8f8e1..89bdac5 100644 --- a/arch/sh/include/asm/dma-sh.h +++ b/arch/sh/include/asm/dma-sh.h @@ -115,4 +115,17 @@ static u32 dma_base_addr[] __maybe_unused = { #define CHCR 0x0C #define DMAOR 0x40 +/* + * for dma engine + * + * SuperH DMA mode + */ +#define SHDMA_MIX_IRQ (1 << 1) +#define SHDMA_DMAOR1 (1 << 2) +#define SHDMA_DMAE1 (1 << 3) + +struct sh_dmae_pdata { + unsigned int mode; +}; + #endif /* __DMA_SH_H */ diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index fe1f3717..3230a78 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -101,6 +101,14 @@ config TXX9_DMAC Support the TXx9 SoC internal DMA controller. This can be integrated in chips such as the Toshiba TX4927/38/39. +config SH_DMAE + tristate "Renesas SuperH DMAC support" + depends on SUPERH && SH_DMA + depends on !SH_DMA_API + select DMA_ENGINE + help + Enable support for the Renesas SuperH DMA controllers. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 8f115e9..eca71ba 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_DW_DMAC) += dw_dmac.o obj-$(CONFIG_AT_HDMAC) += at_hdmac.o obj-$(CONFIG_MX3_IPU) += ipu/ obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o +obj-$(CONFIG_SH_DMAE) += shdma.o diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c new file mode 100644 index 0000000..b3b065c4 --- /dev/null +++ b/drivers/dma/shdma.c @@ -0,0 +1,786 @@ +/* + * Renesas SuperH DMA Engine support + * + * base is drivers/dma/flsdma.c + * + * Copyright (C) 2009 Nobuhiro Iwamatsu + * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. + * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * - DMA of SuperH does not have Hardware DMA chain mode. + * - MAX DMA size is 16MB. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "shdma.h" + +/* DMA descriptor control */ +#define DESC_LAST (-1) +#define DESC_COMP (1) +#define DESC_NCOMP (0) + +#define NR_DESCS_PER_CHANNEL 32 +/* + * Define the default configuration for dual address memory-memory transfer. + * The 0x400 value represents auto-request, external->external. + * + * And this driver set 4byte burst mode. + * If you want to change mode, you need to change RS_DEFAULT of value. + * (ex 1byte burst mode -> (RS_DUAL & ~TS_32) + */ +#define RS_DEFAULT (RS_DUAL) + +#define SH_DMAC_CHAN_BASE(id) (dma_base_addr[id]) +static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) +{ + ctrl_outl(data, (SH_DMAC_CHAN_BASE(sh_dc->id) + reg)); +} + +static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) +{ + return ctrl_inl((SH_DMAC_CHAN_BASE(sh_dc->id) + reg)); +} + +static void dmae_init(struct sh_dmae_chan *sh_chan) +{ + u32 chcr = RS_DEFAULT; /* default is DUAL mode */ + sh_dmae_writel(sh_chan, chcr, CHCR); +} + +/* + * Reset DMA controller + * + * SH7780 has two DMAOR register + */ +static void sh_dmae_ctl_stop(int id) +{ + unsigned short dmaor = dmaor_read_reg(id); + + dmaor &= ~(DMAOR_NMIF | DMAOR_AE); + dmaor_write_reg(id, dmaor); +} + +static int sh_dmae_rst(int id) +{ + unsigned short dmaor; + + sh_dmae_ctl_stop(id); + dmaor = (dmaor_read_reg(id)|DMAOR_INIT); + + dmaor_write_reg(id, dmaor); + if ((dmaor_read_reg(id) & (DMAOR_AE | DMAOR_NMIF))) { + pr_warning(KERN_ERR "dma-sh: Can't initialize DMAOR.\n"); + return -EINVAL; + } + return 0; +} + +static int dmae_is_idle(struct sh_dmae_chan *sh_chan) +{ + u32 chcr = sh_dmae_readl(sh_chan, CHCR); + if (chcr & CHCR_DE) { + if (!(chcr & CHCR_TE)) + return -EBUSY; /* working */ + } + return 0; /* waiting */ +} + +static inline unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan) +{ + u32 chcr = sh_dmae_readl(sh_chan, CHCR); + return ts_shift[(chcr & CHCR_TS_MASK) >> CHCR_TS_SHIFT]; +} + +static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs hw) +{ + sh_dmae_writel(sh_chan, hw.sar, SAR); + sh_dmae_writel(sh_chan, hw.dar, DAR); + sh_dmae_writel(sh_chan, + (hw.tcr >> calc_xmit_shift(sh_chan)), TCR); +} + +static void dmae_start(struct sh_dmae_chan *sh_chan) +{ + u32 chcr = sh_dmae_readl(sh_chan, CHCR); + + chcr |= (CHCR_DE|CHCR_IE); + sh_dmae_writel(sh_chan, chcr, CHCR); +} + +static void dmae_halt(struct sh_dmae_chan *sh_chan) +{ + u32 chcr = sh_dmae_readl(sh_chan, CHCR); + + chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); + sh_dmae_writel(sh_chan, chcr, CHCR); +} + +static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) +{ + int ret = dmae_is_idle(sh_chan); + /* When DMA was working, can not set data to CHCR */ + if (ret) + return ret; + + sh_dmae_writel(sh_chan, val, CHCR); + return 0; +} + +#define DMARS1_ADDR 0x04 +#define DMARS2_ADDR 0x08 +#define DMARS_SHIFT 8 +#define DMARS_CHAN_MSK 0x01 +static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) +{ + u32 addr; + int shift = 0; + int ret = dmae_is_idle(sh_chan); + if (ret) + return ret; + + if (sh_chan->id & DMARS_CHAN_MSK) + shift = DMARS_SHIFT; + + switch (sh_chan->id) { + /* DMARS0 */ + case 0: + case 1: + addr = SH_DMARS_BASE; + break; + /* DMARS1 */ + case 2: + case 3: + addr = (SH_DMARS_BASE + DMARS1_ADDR); + break; + /* DMARS2 */ + case 4: + case 5: + addr = (SH_DMARS_BASE + DMARS2_ADDR); + break; + default: + return -EINVAL; + } + + ctrl_outw((val << shift) | + (ctrl_inw(addr) & (shift ? 0xFF00 : 0x00FF)), + addr); + + return 0; +} + +static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct sh_desc *desc = tx_to_sh_desc(tx); + struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan); + dma_cookie_t cookie; + + spin_lock_bh(&sh_chan->desc_lock); + + cookie = sh_chan->common.cookie; + cookie++; + if (cookie < 0) + cookie = 1; + + /* If desc only in the case of 1 */ + if (desc->async_tx.cookie != -EBUSY) + desc->async_tx.cookie = cookie; + sh_chan->common.cookie = desc->async_tx.cookie; + + list_splice_init(&desc->tx_list, sh_chan->ld_queue.prev); + + spin_unlock_bh(&sh_chan->desc_lock); + + return cookie; +} + +static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan) +{ + struct sh_desc *desc, *_desc, *ret = NULL; + + spin_lock_bh(&sh_chan->desc_lock); + list_for_each_entry_safe(desc, _desc, &sh_chan->ld_free, node) { + if (async_tx_test_ack(&desc->async_tx)) { + list_del(&desc->node); + ret = desc; + break; + } + } + spin_unlock_bh(&sh_chan->desc_lock); + + return ret; +} + +static void sh_dmae_put_desc(struct sh_dmae_chan *sh_chan, struct sh_desc *desc) +{ + if (desc) { + spin_lock_bh(&sh_chan->desc_lock); + + list_splice_init(&desc->tx_list, &sh_chan->ld_free); + list_add(&desc->node, &sh_chan->ld_free); + + spin_unlock_bh(&sh_chan->desc_lock); + } +} + +static int sh_dmae_alloc_chan_resources(struct dma_chan *chan) +{ + struct sh_dmae_chan *sh_chan = to_sh_chan(chan); + struct sh_desc *desc; + + spin_lock_bh(&sh_chan->desc_lock); + while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) { + spin_unlock_bh(&sh_chan->desc_lock); + desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL); + if (!desc) { + spin_lock_bh(&sh_chan->desc_lock); + break; + } + dma_async_tx_descriptor_init(&desc->async_tx, + &sh_chan->common); + desc->async_tx.tx_submit = sh_dmae_tx_submit; + desc->async_tx.flags = DMA_CTRL_ACK; + INIT_LIST_HEAD(&desc->tx_list); + sh_dmae_put_desc(sh_chan, desc); + + spin_lock_bh(&sh_chan->desc_lock); + sh_chan->descs_allocated++; + } + spin_unlock_bh(&sh_chan->desc_lock); + + return sh_chan->descs_allocated; +} + +/* + * sh_dma_free_chan_resources - Free all resources of the channel. + */ +static void sh_dmae_free_chan_resources(struct dma_chan *chan) +{ + struct sh_dmae_chan *sh_chan = to_sh_chan(chan); + struct sh_desc *desc, *_desc; + LIST_HEAD(list); + + BUG_ON(!list_empty(&sh_chan->ld_queue)); + spin_lock_bh(&sh_chan->desc_lock); + + list_splice_init(&sh_chan->ld_free, &list); + sh_chan->descs_allocated = 0; + + spin_unlock_bh(&sh_chan->desc_lock); + + list_for_each_entry_safe(desc, _desc, &list, node) + kfree(desc); +} + +static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy( + struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, + size_t len, unsigned long flags) +{ + struct sh_dmae_chan *sh_chan; + struct sh_desc *first = NULL, *prev = NULL, *new; + size_t copy_size; + + if (!chan) + return NULL; + + if (!len) + return NULL; + + sh_chan = to_sh_chan(chan); + + do { + /* Allocate the link descriptor from DMA pool */ + new = sh_dmae_get_desc(sh_chan); + if (!new) { + dev_err(sh_chan->dev, + "No free memory for link descriptor\n"); + goto err_get_desc; + } + + copy_size = min(len, (size_t)SH_DMA_TCR_MAX); + + new->hw.sar = dma_src; + new->hw.dar = dma_dest; + new->hw.tcr = copy_size; + if (!first) + first = new; + + new->mark = DESC_NCOMP; + async_tx_ack(&new->async_tx); + + prev = new; + len -= copy_size; + dma_src += copy_size; + dma_dest += copy_size; + /* Insert the link descriptor to the LD ring */ + list_add_tail(&new->node, &first->tx_list); + } while (len); + + new->async_tx.flags = flags; /* client is in control of this ack */ + new->async_tx.cookie = -EBUSY; /* Last desc */ + + return &first->async_tx; + +err_get_desc: + sh_dmae_put_desc(sh_chan, first); + return NULL; + +} + +/* + * sh_chan_ld_cleanup - Clean up link descriptors + * + * This function clean up the ld_queue of DMA channel. + */ +static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan) +{ + struct sh_desc *desc, *_desc; + + spin_lock_bh(&sh_chan->desc_lock); + list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) { + dma_async_tx_callback callback; + void *callback_param; + + /* non send data */ + if (desc->mark == DESC_NCOMP) + break; + + /* send data sesc */ + callback = desc->async_tx.callback; + callback_param = desc->async_tx.callback_param; + + /* Remove from ld_queue list */ + list_splice_init(&desc->tx_list, &sh_chan->ld_free); + + dev_dbg(sh_chan->dev, "link descriptor %p will be recycle.\n", + desc); + + list_move(&desc->node, &sh_chan->ld_free); + /* Run the link descriptor callback function */ + if (callback) { + spin_unlock_bh(&sh_chan->desc_lock); + dev_dbg(sh_chan->dev, "link descriptor %p callback\n", + desc); + callback(callback_param); + spin_lock_bh(&sh_chan->desc_lock); + } + } + spin_unlock_bh(&sh_chan->desc_lock); +} + +static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan) +{ + struct list_head *ld_node; + struct sh_dmae_regs hw; + + /* DMA work check */ + if (dmae_is_idle(sh_chan)) + return; + + /* Find the first un-transfer desciptor */ + for (ld_node = sh_chan->ld_queue.next; + (ld_node != &sh_chan->ld_queue) + && (to_sh_desc(ld_node)->mark == DESC_COMP); + ld_node = ld_node->next) + cpu_relax(); + + if (ld_node != &sh_chan->ld_queue) { + /* Get the ld start address from ld_queue */ + hw = to_sh_desc(ld_node)->hw; + dmae_set_reg(sh_chan, hw); + dmae_start(sh_chan); + } +} + +static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan) +{ + struct sh_dmae_chan *sh_chan = to_sh_chan(chan); + sh_chan_xfer_ld_queue(sh_chan); +} + +static enum dma_status sh_dmae_is_complete(struct dma_chan *chan, + dma_cookie_t cookie, + dma_cookie_t *done, + dma_cookie_t *used) +{ + struct sh_dmae_chan *sh_chan = to_sh_chan(chan); + dma_cookie_t last_used; + dma_cookie_t last_complete; + + sh_dmae_chan_ld_cleanup(sh_chan); + + last_used = chan->cookie; + last_complete = sh_chan->completed_cookie; + if (last_complete == -EBUSY) + last_complete = last_used; + + if (done) + *done = last_complete; + + if (used) + *used = last_used; + + return dma_async_is_complete(cookie, last_complete, last_used); +} + +static irqreturn_t sh_dmae_interrupt(int irq, void *data) +{ + irqreturn_t ret = IRQ_NONE; + struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data; + u32 chcr = sh_dmae_readl(sh_chan, CHCR); + + if (chcr & CHCR_TE) { + /* DMA stop */ + dmae_halt(sh_chan); + + ret = IRQ_HANDLED; + tasklet_schedule(&sh_chan->tasklet); + } + + return ret; +} + +#if defined(CONFIG_CPU_SH4) +static irqreturn_t sh_dmae_err(int irq, void *data) +{ + int err = 0; + struct sh_dmae_device *shdev = (struct sh_dmae_device *)data; + + /* IRQ Multi */ + if (shdev->pdata.mode & SHDMA_MIX_IRQ) { + int cnt = 0; + switch (irq) { +#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ) + case DMTE6_IRQ: + cnt++; +#endif + case DMTE0_IRQ: + if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) { + disable_irq(irq); + return IRQ_HANDLED; + } + default: + return IRQ_NONE; + } + } else { + /* reset dma controller */ + err = sh_dmae_rst(0); + if (err) + return err; + if (shdev->pdata.mode & SHDMA_DMAOR1) { + err = sh_dmae_rst(1); + if (err) + return err; + } + disable_irq(irq); + return IRQ_HANDLED; + } +} +#endif + +static void dmae_do_tasklet(unsigned long data) +{ + struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data; + struct sh_desc *desc, *_desc, *cur_desc = NULL; + u32 sar_buf = sh_dmae_readl(sh_chan, SAR); + list_for_each_entry_safe(desc, _desc, + &sh_chan->ld_queue, node) { + if ((desc->hw.sar + desc->hw.tcr) == sar_buf) { + cur_desc = desc; + break; + } + } + + if (cur_desc) { + switch (cur_desc->async_tx.cookie) { + case 0: /* other desc data */ + break; + case -EBUSY: /* last desc */ + sh_chan->completed_cookie = + cur_desc->async_tx.cookie; + break; + default: /* first desc ( 0 < )*/ + sh_chan->completed_cookie = + cur_desc->async_tx.cookie - 1; + break; + } + cur_desc->mark = DESC_COMP; + } + /* Next desc */ + sh_chan_xfer_ld_queue(sh_chan); + sh_dmae_chan_ld_cleanup(sh_chan); +} + +static unsigned int get_dmae_irq(unsigned int id) +{ + unsigned int irq = 0; + if (id < ARRAY_SIZE(dmte_irq_map)) + irq = dmte_irq_map[id]; + return irq; +} + +static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id) +{ + int err; + unsigned int irq = get_dmae_irq(id); + unsigned long irqflags = IRQF_DISABLED; + struct sh_dmae_chan *new_sh_chan; + + /* alloc channel */ + new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL); + if (!new_sh_chan) { + dev_err(shdev->common.dev, "No free memory for allocating " + "dma channels!\n"); + return -ENOMEM; + } + + new_sh_chan->dev = shdev->common.dev; + new_sh_chan->id = id; + + /* Init DMA tasklet */ + tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet, + (unsigned long)new_sh_chan); + + /* Init the channel */ + dmae_init(new_sh_chan); + + spin_lock_init(&new_sh_chan->desc_lock); + + /* Init descripter manage list */ + INIT_LIST_HEAD(&new_sh_chan->ld_queue); + INIT_LIST_HEAD(&new_sh_chan->ld_free); + + /* copy struct dma_device */ + new_sh_chan->common.device = &shdev->common; + + /* Add the channel to DMA device channel list */ + list_add_tail(&new_sh_chan->common.device_node, + &shdev->common.channels); + shdev->common.chancnt++; + + if (shdev->pdata.mode & SHDMA_MIX_IRQ) { + irqflags = IRQF_SHARED; +#if defined(DMTE6_IRQ) + if (irq >= DMTE6_IRQ) + irq = DMTE6_IRQ; + else +#endif + irq = DMTE0_IRQ; + } + + snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id), + "sh-dmae%d", new_sh_chan->id); + + /* set up channel irq */ + err = request_irq(irq, &sh_dmae_interrupt, + irqflags, new_sh_chan->dev_id, new_sh_chan); + if (err) { + dev_err(shdev->common.dev, "DMA channel %d request_irq error " + "with return %d\n", id, err); + goto err_no_irq; + } + + /* CHCR register control function */ + new_sh_chan->set_chcr = dmae_set_chcr; + /* DMARS register control function */ + new_sh_chan->set_dmars = dmae_set_dmars; + + shdev->chan[id] = new_sh_chan; + return 0; + +err_no_irq: + /* remove from dmaengine device node */ + list_del(&new_sh_chan->common.device_node); + kfree(new_sh_chan); + return err; +} + +static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) +{ + int i; + + for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) { + if (shdev->chan[i]) { + struct sh_dmae_chan *shchan = shdev->chan[i]; + if (!(shdev->pdata.mode & SHDMA_MIX_IRQ)) + free_irq(dmte_irq_map[i], shchan); + + list_del(&shchan->common.device_node); + kfree(shchan); + shdev->chan[i] = NULL; + } + } + shdev->common.chancnt = 0; +} + +static int __init sh_dmae_probe(struct platform_device *pdev) +{ + int err = 0, cnt, ecnt; + unsigned long irqflags = IRQF_DISABLED; +#if defined(CONFIG_CPU_SH4) + int eirq[] = { DMAE0_IRQ, +#if defined(DMAE1_IRQ) + DMAE1_IRQ +#endif + }; +#endif + struct sh_dmae_device *shdev; + + shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL); + if (!shdev) { + dev_err(&pdev->dev, "No enough memory\n"); + err = -ENOMEM; + goto shdev_err; + } + + /* get platform data */ + if (!pdev->dev.platform_data) + goto shdev_err; + + /* platform data */ + memcpy(&shdev->pdata, pdev->dev.platform_data, + sizeof(struct sh_dmae_pdata)); + + /* reset dma controller */ + err = sh_dmae_rst(0); + if (err) + goto rst_err; + + /* SH7780/85/23 has DMAOR1 */ + if (shdev->pdata.mode & SHDMA_DMAOR1) { + err = sh_dmae_rst(1); + if (err) + goto rst_err; + } + + INIT_LIST_HEAD(&shdev->common.channels); + + dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask); + shdev->common.device_alloc_chan_resources + = sh_dmae_alloc_chan_resources; + shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources; + shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy; + shdev->common.device_is_tx_complete = sh_dmae_is_complete; + shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending; + shdev->common.dev = &pdev->dev; + +#if defined(CONFIG_CPU_SH4) + /* Non Mix IRQ mode SH7722/SH7730 etc... */ + if (shdev->pdata.mode & SHDMA_MIX_IRQ) { + irqflags = IRQF_SHARED; + eirq[0] = DMTE0_IRQ; +#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ) + eirq[1] = DMTE6_IRQ; +#endif + } + + for (ecnt = 0 ; ecnt < ARRAY_SIZE(eirq); ecnt++) { + err = request_irq(eirq[ecnt], sh_dmae_err, + irqflags, "DMAC Address Error", shdev); + if (err) { + dev_err(&pdev->dev, "DMA device request_irq" + "error (irq %d) with return %d\n", + eirq[ecnt], err); + goto eirq_err; + } + } +#endif /* CONFIG_CPU_SH4 */ + + /* Create DMA Channel */ + for (cnt = 0 ; cnt < MAX_DMA_CHANNELS ; cnt++) { + err = sh_dmae_chan_probe(shdev, cnt); + if (err) + goto chan_probe_err; + } + + platform_set_drvdata(pdev, shdev); + dma_async_device_register(&shdev->common); + + return err; + +chan_probe_err: + sh_dmae_chan_remove(shdev); + +eirq_err: + for (ecnt-- ; ecnt >= 0; ecnt--) + free_irq(eirq[ecnt], shdev); + +rst_err: + kfree(shdev); + +shdev_err: + return err; +} + +static int __exit sh_dmae_remove(struct platform_device *pdev) +{ + struct sh_dmae_device *shdev = platform_get_drvdata(pdev); + + dma_async_device_unregister(&shdev->common); + + if (shdev->pdata.mode & SHDMA_MIX_IRQ) { + free_irq(DMTE0_IRQ, shdev); +#if defined(DMTE6_IRQ) + free_irq(DMTE6_IRQ, shdev); +#endif + } + + /* channel data remove */ + sh_dmae_chan_remove(shdev); + + if (!(shdev->pdata.mode & SHDMA_MIX_IRQ)) { + free_irq(DMAE0_IRQ, shdev); +#if defined(DMAE1_IRQ) + free_irq(DMAE1_IRQ, shdev); +#endif + } + kfree(shdev); + + return 0; +} + +static void sh_dmae_shutdown(struct platform_device *pdev) +{ + struct sh_dmae_device *shdev = platform_get_drvdata(pdev); + sh_dmae_ctl_stop(0); + if (shdev->pdata.mode & SHDMA_DMAOR1) + sh_dmae_ctl_stop(1); +} + +static struct platform_driver sh_dmae_driver = { + .remove = __exit_p(sh_dmae_remove), + .shutdown = sh_dmae_shutdown, + .driver = { + .name = "sh-dma-engine", + }, +}; + +static int __init sh_dmae_init(void) +{ + return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe); +} +module_init(sh_dmae_init); + +static void __exit sh_dmae_exit(void) +{ + platform_driver_unregister(&sh_dmae_driver); +} +module_exit(sh_dmae_exit); + +MODULE_AUTHOR("Nobuhiro Iwamatsu "); +MODULE_DESCRIPTION("Renesas SH DMA Engine driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/shdma.h b/drivers/dma/shdma.h new file mode 100644 index 0000000..2b4bc15 --- /dev/null +++ b/drivers/dma/shdma.h @@ -0,0 +1,64 @@ +/* + * Renesas SuperH DMA Engine support + * + * Copyright (C) 2009 Nobuhiro Iwamatsu + * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __DMA_SHDMA_H +#define __DMA_SHDMA_H + +#include +#include +#include + +#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */ + +struct sh_dmae_regs { + u32 sar; /* SAR / source address */ + u32 dar; /* DAR / destination address */ + u32 tcr; /* TCR / transfer count */ +}; + +struct sh_desc { + struct list_head tx_list; + struct sh_dmae_regs hw; + struct list_head node; + struct dma_async_tx_descriptor async_tx; + int mark; +}; + +struct sh_dmae_chan { + dma_cookie_t completed_cookie; /* The maximum cookie completed */ + spinlock_t desc_lock; /* Descriptor operation lock */ + struct list_head ld_queue; /* Link descriptors queue */ + struct list_head ld_free; /* Link descriptors free */ + struct dma_chan common; /* DMA common channel */ + struct device *dev; /* Channel device */ + struct tasklet_struct tasklet; /* Tasklet */ + int descs_allocated; /* desc count */ + int id; /* Raw id of this channel */ + char dev_id[16]; /* unique name per DMAC of channel */ + + /* Set chcr */ + int (*set_chcr)(struct sh_dmae_chan *sh_chan, u32 regs); + /* Set DMA resource */ + int (*set_dmars)(struct sh_dmae_chan *sh_chan, u16 res); +}; + +struct sh_dmae_device { + struct dma_device common; + struct sh_dmae_chan *chan[MAX_DMA_CHANNELS]; + struct sh_dmae_pdata pdata; +}; + +#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common) +#define to_sh_desc(lh) container_of(lh, struct sh_desc, node) +#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx) + +#endif /* __DMA_SHDMA_H */ -- cgit v0.10.2 From 9a8de639f35ca3951b910d5e3a2f92f4cf3afc8f Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 8 Sep 2009 15:06:10 -0700 Subject: async_tx: remove HIGHMEM64G restriction This restriction prevented ASYNC_TX_DMA from being enabled on platform configurations where DMA address conversion could not be performed in place on the stack. Since commit 04ce9ab3 ("async_xor: permit callers to pass in a 'dma/page scribble' region") the async_tx api now either uses a caller provided 'scribble' buffer, or performs the conversion in place when sizeof(dma_addr_t) <= sizeof(struct page *). Signed-off-by: Dan Williams diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 3230a78..5903a88 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -128,7 +128,7 @@ config NET_DMA config ASYNC_TX_DMA bool "Async_tx: Offload support for the async_tx api" - depends on DMA_ENGINE && !HIGHMEM64G + depends on DMA_ENGINE help This allows the async_tx api to take advantage of offload engines for memcpy, memset, xor, and raid6 p+q operations. If your platform has -- cgit v0.10.2 From 307a042416dfc2216251a85b79e8578b65fdc0e7 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Thu, 3 Sep 2009 09:55:40 +0800 Subject: ACPICA: Fix extraneous warning if _DSM returns a package _DSM can return any type of object, so validation on the return type cannot be performed. ACPICA BZ 802. http://www.acpica.org/bugzilla/show_bug.cgi?id=802 Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/nspredef.c b/drivers/acpi/acpica/nspredef.c index 8314e6a..f8427af 100644 --- a/drivers/acpi/acpica/nspredef.c +++ b/drivers/acpi/acpica/nspredef.c @@ -193,11 +193,15 @@ acpi_ns_check_predefined_names(struct acpi_namespace_node *node, } /* - * We have a return value, but if one wasn't expected, just exit, this is + * 1) We have a return value, but if one wasn't expected, just exit, this is * not a problem. For example, if the "Implicit Return" feature is * enabled, methods will always return a value. + * + * 2) If the return value can be of any type, then we cannot perform any + * validation, exit. */ - if (!predefined->info.expected_btypes) { + if ((!predefined->info.expected_btypes) || + (predefined->info.expected_btypes == ACPI_RTYPE_ALL)) { goto cleanup; } -- cgit v0.10.2 From e678902ee899f6b0ab48166b410cdc9f1c27a350 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Thu, 3 Sep 2009 09:58:14 +0800 Subject: ACPICA: Remove error message for Store(Localx,Localx) We silently ignore this construct for Windows compatibility ACPICA BZ 785. http://www.acpica.org/bugzilla/show_bug.cgi?id=785 Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/dsmthdat.c b/drivers/acpi/acpica/dsmthdat.c index 22b1a3c..7d077bb 100644 --- a/drivers/acpi/acpica/dsmthdat.c +++ b/drivers/acpi/acpica/dsmthdat.c @@ -433,10 +433,10 @@ acpi_ds_method_data_get_value(u8 type, case ACPI_REFCLASS_LOCAL: - ACPI_ERROR((AE_INFO, - "Uninitialized Local[%d] at node %p", - index, node)); - + /* + * No error message for this case, will be trapped again later to + * detect and ignore cases of Store(local_x,local_x) + */ return_ACPI_STATUS(AE_AML_UNINITIALIZED_LOCAL); default: -- cgit v0.10.2 From e3fe0913b8e732ae636cf23afca76cf2c30718e5 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Thu, 3 Sep 2009 10:03:37 +0800 Subject: ACPICA: Fix memory leak for ill-formed Package objects Fixes a possible memory leak in the interpreter for package objects if the package initializer list is longer than the defined size of the package. This apparently can only happen if the BIOS changes the package size on the fly (seen in a _PSS object), as both iASL and the other compiler do not allow this. The interpreter will truncate the package to the defined size (and issue an error message), but can leave the extra objects undeleted if they have been pre-created during the argument processing (such is the case if the package consists of a number of sub-packages as in the _PSS.) ACPICA BZ 805. http://www.acpica.org/bugzilla/show_bug.cgi?id=805 Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/dsobject.c b/drivers/acpi/acpica/dsobject.c index 02e6caa..507e1f0 100644 --- a/drivers/acpi/acpica/dsobject.c +++ b/drivers/acpi/acpica/dsobject.c @@ -482,14 +482,27 @@ acpi_ds_build_internal_package_obj(struct acpi_walk_state *walk_state, if (arg) { /* * num_elements was exhausted, but there are remaining elements in the - * package_list. + * package_list. Truncate the package to num_elements. * * Note: technically, this is an error, from ACPI spec: "It is an error * for NumElements to be less than the number of elements in the - * PackageList". However, for now, we just print an error message and - * no exception is returned. + * PackageList". However, we just print an error message and + * no exception is returned. This provides Windows compatibility. Some + * BIOSs will alter the num_elements on the fly, creating this type + * of ill-formed package object. */ while (arg) { + /* + * We must delete any package elements that were created earlier + * and are not going to be used because of the package truncation. + */ + if (arg->common.node) { + acpi_ut_remove_reference(ACPI_CAST_PTR + (union + acpi_operand_object, + arg->common.node)); + arg->common.node = NULL; + } /* Find out how many elements there really are */ @@ -498,7 +511,7 @@ acpi_ds_build_internal_package_obj(struct acpi_walk_state *walk_state, } ACPI_WARNING((AE_INFO, - "Package List length (%X) larger than NumElements count (%X), truncated\n", + "Package List length (0x%X) larger than NumElements count (0x%X), truncated\n", i, element_count)); } else if (i < element_count) { /* @@ -506,7 +519,7 @@ acpi_ds_build_internal_package_obj(struct acpi_walk_state *walk_state, * Note: this is not an error, the package is padded out with NULLs. */ ACPI_DEBUG_PRINT((ACPI_DB_INFO, - "Package List length (%X) smaller than NumElements count (%X), padded with null elements\n", + "Package List length (0x%X) smaller than NumElements count (0x%X), padded with null elements\n", i, element_count)); } -- cgit v0.10.2 From eb752552464dbb7a99f8a975ec3b9355893cedd4 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Thu, 3 Sep 2009 10:05:08 +0800 Subject: ACPICA: Update _OSI with new Windows OS strings Added strings for Windows server 2008, Windows Vista SP1, Windows 7, and Windows server 2008 R2. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/aclocal.h b/drivers/acpi/acpica/aclocal.h index ff6689e..81e64f4 100644 --- a/drivers/acpi/acpica/aclocal.h +++ b/drivers/acpi/acpica/aclocal.h @@ -898,6 +898,9 @@ struct acpi_bit_register_info { #define ACPI_OSI_WIN_XP_SP2 0x05 #define ACPI_OSI_WINSRV_2003_SP1 0x06 #define ACPI_OSI_WIN_VISTA 0x07 +#define ACPI_OSI_WINSRV_2008 0x08 +#define ACPI_OSI_WIN_VISTA_SP1 0x09 +#define ACPI_OSI_WIN_7 0x0A #define ACPI_ALWAYS_ILLEGAL 0x00 diff --git a/drivers/acpi/acpica/uteval.c b/drivers/acpi/acpica/uteval.c index 5503307..5d54e36 100644 --- a/drivers/acpi/acpica/uteval.c +++ b/drivers/acpi/acpica/uteval.c @@ -69,6 +69,9 @@ static struct acpi_interface_info acpi_interfaces_supported[] = { {"Windows 2001 SP2", ACPI_OSI_WIN_XP_SP2}, /* Windows XP SP2 */ {"Windows 2001.1 SP1", ACPI_OSI_WINSRV_2003_SP1}, /* Windows Server 2003 SP1 - Added 03/2006 */ {"Windows 2006", ACPI_OSI_WIN_VISTA}, /* Windows Vista - Added 03/2006 */ + {"Windows 2006.1", ACPI_OSI_WINSRV_2008}, /* Windows Server 2008 - Added 09/2009 */ + {"Windows 2006 SP1", ACPI_OSI_WIN_VISTA_SP1}, /* Windows Vista SP1 - Added 09/2009 */ + {"Windows 2009", ACPI_OSI_WIN_7}, /* Windows 7 and Server 2008 R2 - Added 09/2009 */ /* Feature Group Strings */ -- cgit v0.10.2 From 9e64155eb1b6ab78980db58cfd21385fa5f6b024 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Thu, 3 Sep 2009 10:21:03 +0800 Subject: ACPICA: Windows compatibility: autoexecute root _INI method Add support for execution of an _INI method at the namespace root. Although not defined in the ACPI specification, this support was added to Windows around the Vista timeframe. It is added here for Windows compatibility. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/drivers/acpi/acpica/nsinit.c b/drivers/acpi/acpica/nsinit.c index 2adfcf3..1d5b360 100644 --- a/drivers/acpi/acpica/nsinit.c +++ b/drivers/acpi/acpica/nsinit.c @@ -170,6 +170,21 @@ acpi_status acpi_ns_initialize_devices(void) goto error_exit; } + /* + * Execute the "global" _INI method that may appear at the root. This + * support is provided for Windows compatibility (Vista+) and is not + * part of the ACPI specification. + */ + info.evaluate_info->prefix_node = acpi_gbl_root_node; + info.evaluate_info->pathname = METHOD_NAME__INI; + info.evaluate_info->parameters = NULL; + info.evaluate_info->flags = ACPI_IGNORE_RETURN_VALUE; + + status = acpi_ns_evaluate(info.evaluate_info); + if (ACPI_SUCCESS(status)) { + info.num_INI++; + } + /* Walk namespace to execute all _INIs on present devices */ status = acpi_ns_walk_namespace(ACPI_TYPE_ANY, ACPI_ROOT_OBJECT, -- cgit v0.10.2 From c9766237afa92e8d7f27bbcd4964f1b43fa0bce8 Mon Sep 17 00:00:00 2001 From: Bob Moore Date: Fri, 4 Sep 2009 08:56:17 +0800 Subject: ACPICA: Update version to 20090903. Version 20090903. Signed-off-by: Bob Moore Signed-off-by: Lin Ming Signed-off-by: Len Brown diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index f3b358b..e723b0f 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -47,7 +47,7 @@ /* Current ACPICA subsystem version in YYYYMMDD format */ -#define ACPI_CA_VERSION 0x20090730 +#define ACPI_CA_VERSION 0x20090903 #include "actypes.h" #include "actbl.h" -- cgit v0.10.2 From 38d8a95621b20ed7868e232a35a26ee61bdcae6f Mon Sep 17 00:00:00 2001 From: Fabian Henze Date: Tue, 8 Sep 2009 00:59:58 +0800 Subject: agp/intel: Add B43 chipset support Signed-off-by: Fabian Henze [Fix reversed HB & IG ids for B43] Signed-off-by: Zhenyu Wang Signed-off-by: Eric Anholt diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index c585577..c172917 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c @@ -36,6 +36,8 @@ #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 +#define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40 +#define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00 @@ -81,6 +83,7 @@ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB) @@ -1216,6 +1219,7 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) case PCI_DEVICE_ID_INTEL_Q45_HB: case PCI_DEVICE_ID_INTEL_G45_HB: case PCI_DEVICE_ID_INTEL_G41_HB: + case PCI_DEVICE_ID_INTEL_B43_HB: case PCI_DEVICE_ID_INTEL_IGDNG_D_HB: case PCI_DEVICE_ID_INTEL_IGDNG_M_HB: case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB: @@ -2192,6 +2196,8 @@ static const struct intel_driver_description { "Q45/Q43", NULL, &intel_i965_driver }, { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, "G45/G43", NULL, &intel_i965_driver }, + { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0, + "B43", NULL, &intel_i965_driver }, { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, "G41", NULL, &intel_i965_driver }, { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0, @@ -2401,6 +2407,7 @@ static struct pci_device_id agp_intel_pci_table[] = { ID(PCI_DEVICE_ID_INTEL_Q45_HB), ID(PCI_DEVICE_ID_INTEL_G45_HB), ID(PCI_DEVICE_ID_INTEL_G41_HB), + ID(PCI_DEVICE_ID_INTEL_B43_HB), ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB), ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB), ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB), -- cgit v0.10.2 From 7839c5d5519b6d9e2ccf3cdbf1c39e3817ad0835 Mon Sep 17 00:00:00 2001 From: Fabian Henze Date: Tue, 8 Sep 2009 00:59:59 +0800 Subject: drm/i915: add B43 chipset support Signed-off-by: Fabian Henze Signed-off-by: Zhenyu Wang Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 77ed060..e5f20e4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -863,6 +863,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); (dev)->pci_device == 0x2E12 || \ (dev)->pci_device == 0x2E22 || \ (dev)->pci_device == 0x2E32 || \ + (dev)->pci_device == 0x2E42 || \ (dev)->pci_device == 0x0042 || \ (dev)->pci_device == 0x0046) @@ -875,6 +876,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); (dev)->pci_device == 0x2E12 || \ (dev)->pci_device == 0x2E22 || \ (dev)->pci_device == 0x2E32 || \ + (dev)->pci_device == 0x2E42 || \ IS_GM45(dev)) #define IS_IGDG(dev) ((dev)->pci_device == 0xa001) diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h index 8535084..3f6e545 100644 --- a/include/drm/drm_pciids.h +++ b/include/drm/drm_pciids.h @@ -552,6 +552,7 @@ {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0x8086, 0x2e32, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2e42, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0x8086, 0xa001, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0x8086, 0xa011, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0x8086, 0x35e8, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ -- cgit v0.10.2 From 5323fd042f89164927ee8c311f0a975e8c846412 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 9 Sep 2009 11:50:45 -0700 Subject: drm/i915: Zap mmaps of objects before unbinding them from the GTT. Otherwise, some other userland writing into its buffer may race to land writes either after the CPU thinks it's got a coherent view, or after its GTT entries have been redirected to point at the scratch page. Either result is unpleasant. Signed-off-by: Eric Anholt diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 954fb69..f3758f9 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1915,6 +1915,12 @@ i915_gem_object_unbind(struct drm_gem_object *obj) return -EINVAL; } + /* blow away mappings if mapped through GTT */ + i915_gem_release_mmap(obj); + + if (obj_priv->fence_reg != I915_FENCE_REG_NONE) + i915_gem_clear_fence_reg(obj); + /* Move the object to the CPU domain to ensure that * any possible CPU writes while it's not in the GTT * are flushed when we go to remap it. This will @@ -1928,20 +1934,14 @@ i915_gem_object_unbind(struct drm_gem_object *obj) return ret; } + BUG_ON(obj_priv->active); + if (obj_priv->agp_mem != NULL) { drm_unbind_agp(obj_priv->agp_mem); drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); obj_priv->agp_mem = NULL; } - BUG_ON(obj_priv->active); - - /* blow away mappings if mapped through GTT */ - i915_gem_release_mmap(obj); - - if (obj_priv->fence_reg != I915_FENCE_REG_NONE) - i915_gem_clear_fence_reg(obj); - i915_gem_object_put_pages(obj); if (obj_priv->gtt_space) { -- cgit v0.10.2 From 5d93b135fc051be3740cbe55729fc7b86a7069d7 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 9 Sep 2009 16:09:36 -0400 Subject: drm/radeon/r600: fix legacy blit code ARRAY_SIZE is number of elements not bytes. Fix ring counts accordingly, also make a few functions static. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c index c51402e..dde2ccb 100644 --- a/drivers/gpu/drm/radeon/r600_blit.c +++ b/drivers/gpu/drm/radeon/r600_blit.c @@ -126,7 +126,7 @@ set_shaders(struct drm_device *dev) { drm_radeon_private_t *dev_priv = dev->dev_private; u64 gpu_addr; - int shader_size, i; + int i; u32 *vs, *ps; uint32_t sq_pgm_resources; RING_LOCALS; @@ -136,11 +136,9 @@ set_shaders(struct drm_device *dev) vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset); ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256); - shader_size = r6xx_vs_size; - for (i = 0; i < shader_size; i++) + for (i = 0; i < r6xx_vs_size; i++) vs[i] = r6xx_vs[i]; - shader_size = r6xx_ps_size; - for (i = 0; i < shader_size; i++) + for (i = 0; i < r6xx_ps_size; i++) ps[i] = r6xx_ps[i]; dev_priv->blit_vb->used = 512; @@ -309,7 +307,7 @@ draw_auto(drm_radeon_private_t *dev_priv) static inline void set_default_state(drm_radeon_private_t *dev_priv) { - int default_state_dw, i; + int i; u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; @@ -462,14 +460,12 @@ set_default_state(drm_radeon_private_t *dev_priv) R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries)); if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { - default_state_dw = r7xx_default_size * 4; - BEGIN_RING(default_state_dw + 10); - for (i = 0; i < default_state_dw; i++) + BEGIN_RING(r7xx_default_size + 10); + for (i = 0; i < r7xx_default_size; i++) OUT_RING(r7xx_default_state[i]); } else { - default_state_dw = r6xx_default_size * 4; - BEGIN_RING(default_state_dw + 10); - for (i = 0; i < default_state_dw; i++) + BEGIN_RING(r6xx_default_size + 10); + for (i = 0; i < r6xx_default_size; i++) OUT_RING(r6xx_default_state[i]); } OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); @@ -512,7 +508,7 @@ static inline uint32_t i2f(uint32_t input) } -int r600_nomm_get_vb(struct drm_device *dev) +static inline int r600_nomm_get_vb(struct drm_device *dev) { drm_radeon_private_t *dev_priv = dev->dev_private; dev_priv->blit_vb = radeon_freelist_get(dev); @@ -523,7 +519,7 @@ int r600_nomm_get_vb(struct drm_device *dev) return 0; } -void r600_nomm_put_vb(struct drm_device *dev) +static inline void r600_nomm_put_vb(struct drm_device *dev) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -531,7 +527,7 @@ void r600_nomm_put_vb(struct drm_device *dev) radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb); } -void *r600_nomm_get_vb_ptr(struct drm_device *dev) +static inline void *r600_nomm_get_vb_ptr(struct drm_device *dev) { drm_radeon_private_t *dev_priv = dev->dev_private; return (((char *)dev->agp_buffer_map->handle + @@ -781,8 +777,7 @@ r600_blit_swap(struct drm_device *dev, u64 vb_addr; u32 *vb; - vb = (u32 *) ((char *)dev->agp_buffer_map->handle + - dev_priv->blit_vb->offset + dev_priv->blit_vb->used); + vb = r600_nomm_get_vb_ptr(dev); if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) { -- cgit v0.10.2 From 45600232b3dbb97817c9e15de848c742901893e1 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 9 Sep 2009 22:23:45 +0200 Subject: drm/radeon/kms: wait for cp idle before stopping it. If we stop CP and that it's still processing thing GPU hang might happen, this patch wait for CP idle (the wait can timeout) so we can avoid shutting down CP at bad time. This is especialy usefull when reseting the GPU as it seems GPU reset fails to properly reset CP when the CP wasn't stop after being idle. Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 5708c07..938a693 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -487,6 +487,21 @@ int r100_copy_blit(struct radeon_device *rdev, /* * CP */ +static int r100_cp_wait_for_idle(struct radeon_device *rdev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < rdev->usec_timeout; i++) { + tmp = RREG32(R_000E40_RBBM_STATUS); + if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { + return 0; + } + udelay(1); + } + return -1; +} + void r100_ring_start(struct radeon_device *rdev) { int r; @@ -715,6 +730,9 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) void r100_cp_fini(struct radeon_device *rdev) { + if (r100_cp_wait_for_idle(rdev)) { + DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); + } /* Disable ring */ rdev->cp.ready = false; WREG32(RADEON_CP_CSQ_CNTL, 0); diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h index 6da7d92..1d951ab 100644 --- a/drivers/gpu/drm/radeon/r100d.h +++ b/drivers/gpu/drm/radeon/r100d.h @@ -73,4 +73,64 @@ #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) +/* Registers */ +#define R_000E40_RBBM_STATUS 0x000E40 +#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) +#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) +#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 +#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) +#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) +#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF +#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) +#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) +#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF +#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) +#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) +#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF +#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) +#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) +#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF +#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) +#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) +#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF +#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) +#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) +#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF +#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) +#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) +#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF +#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) +#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) +#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF +#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) +#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) +#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF +#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) +#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) +#define C_000E40_E2_BUSY 0xFFFDFFFF +#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) +#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) +#define C_000E40_RB2D_BUSY 0xFFFBFFFF +#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) +#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) +#define C_000E40_RB3D_BUSY 0xFFF7FFFF +#define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20) +#define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1) +#define C_000E40_SE_BUSY 0xFFEFFFFF +#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) +#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) +#define C_000E40_RE_BUSY 0xFFDFFFFF +#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) +#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) +#define C_000E40_TAM_BUSY 0xFFBFFFFF +#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) +#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) +#define C_000E40_TDM_BUSY 0xFF7FFFFF +#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) +#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) +#define C_000E40_PB_BUSY 0xFEFFFFFF +#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) +#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) +#define C_000E40_GUI_ACTIVE 0x7FFFFFFF + #endif -- cgit v0.10.2 From a18d7ea15356679f58c2fafe2957786c5f7f9201 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 9 Sep 2009 22:23:27 +0200 Subject: drm/radeon/kms: call r100_cp_disable rather than duplicating code. r100_cp_fini was duplicating code of r100_cp_disable, call r100_cp_disable instead. Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 938a693..4e1c551 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -734,8 +734,7 @@ void r100_cp_fini(struct radeon_device *rdev) DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); } /* Disable ring */ - rdev->cp.ready = false; - WREG32(RADEON_CP_CSQ_CNTL, 0); + r100_cp_disable(rdev); radeon_ring_fini(rdev); DRM_INFO("radeon: cp finalized\n"); } diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 3299733..24574bc 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -933,4 +933,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) +/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ +void r100_cp_disable(struct radeon_device *rdev); + #endif -- cgit v0.10.2 From 905b68223be18937159a29b354e6a332952ff952 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 9 Sep 2009 22:24:20 +0200 Subject: drm/radeon/kms: add R4XX mc register access helper. Atombios will use the mc register access helper and R4XX hw have a bigger mc range than R3XX so add R4XX specific mc register access helper. Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index 97426a6..96303f0 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c @@ -29,6 +29,7 @@ #include "drmP.h" #include "radeon_reg.h" #include "radeon.h" +#include "r420d.h" /* r420,r423,rv410 depends on : */ void r100_pci_gart_disable(struct radeon_device *rdev); @@ -232,3 +233,19 @@ int r420_debugfs_pipes_info_init(struct radeon_device *rdev) return 0; #endif } + +u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) +{ + u32 r; + + WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); + r = RREG32(R_0001FC_MC_IND_DATA); + return r; +} + +void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | + S_0001F8_MC_IND_WR_EN(1)); + WREG32(R_0001FC_MC_IND_DATA, v); +} diff --git a/drivers/gpu/drm/radeon/r420d.h b/drivers/gpu/drm/radeon/r420d.h new file mode 100644 index 0000000..8b946c1 --- /dev/null +++ b/drivers/gpu/drm/radeon/r420d.h @@ -0,0 +1,43 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef R420D_H +#define R420D_H + +#define R_0001F8_MC_IND_INDEX 0x0001F8 +#define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) +#define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) +#define C_0001F8_MC_IND_ADDR 0xFFFFFF80 +#define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) +#define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) +#define C_0001F8_MC_IND_WR_EN 0xFFFFFEFF +#define R_0001FC_MC_IND_DATA 0x0001FC +#define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0001FC_MC_IND_DATA 0x00000000 + +#endif diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 24574bc..fa84c77 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -936,4 +936,8 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ void r100_cp_disable(struct radeon_device *rdev); +/* r420,r423,rv410 */ +u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); +void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); + #endif diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index f2469c5..05e1af0 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -266,6 +266,10 @@ void radeon_register_accessor_init(struct radeon_device *rdev) rdev->pll_rreg = &r100_pll_rreg; rdev->pll_wreg = &r100_pll_wreg; } + if (rdev->family >= CHIP_R420) { + rdev->mc_rreg = &r420_mc_rreg; + rdev->mc_wreg = &r420_mc_wreg; + } if (rdev->family >= CHIP_RV515) { rdev->mc_rreg = &rv515_mc_rreg; rdev->mc_wreg = &rv515_mc_wreg; -- cgit v0.10.2 From e3c3efc243462d67ba9fa7f67620dcbc4597bf0a Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Thu, 27 Aug 2009 16:34:19 +0300 Subject: UBIFS: add inode size debugging check Add one more check to UBIFS - a check that makes sure that there are no data nodes beyond inode size. And few commantaries fixes along the line. Signed-off-by: Artem Bityutskiy Reviewed-by: Adrian Hunter diff --git a/fs/ubifs/debug.h b/fs/ubifs/debug.h index c1cd73b..fe2c927 100644 --- a/fs/ubifs/debug.h +++ b/fs/ubifs/debug.h @@ -321,6 +321,8 @@ void dbg_check_heap(struct ubifs_info *c, struct ubifs_lpt_heap *heap, int cat, int dbg_check_lprops(struct ubifs_info *c); int dbg_check_lpt_nodes(struct ubifs_info *c, struct ubifs_cnode *cnode, int row, int col); +int dbg_check_inode_size(struct ubifs_info *c, const struct inode *inode, + loff_t size); /* Force the use of in-the-gaps method for testing */ @@ -460,6 +462,7 @@ void dbg_debugfs_exit_fs(struct ubifs_info *c); #define dbg_check_heap(c, heap, cat, add_pos) ({}) #define dbg_check_lprops(c) 0 #define dbg_check_lpt_nodes(c, cnode, row, col) 0 +#define dbg_check_inode_size(c, inode, size) 0 #define dbg_force_in_the_gaps_enabled 0 #define dbg_force_in_the_gaps() 0 #define dbg_failure_mode 0 diff --git a/fs/ubifs/key.h b/fs/ubifs/key.h index 919af84..0f530c6 100644 --- a/fs/ubifs/key.h +++ b/fs/ubifs/key.h @@ -278,6 +278,18 @@ static inline void data_key_init(const struct ubifs_info *c, } /** + * highest_data_key - get the highest possible data key for an inode. + * @c: UBIFS file-system description object + * @key: key to initialize + * @inum: inode number + */ +static inline void highest_data_key(const struct ubifs_info *c, + union ubifs_key *key, ino_t inum) +{ + data_key_init(c, key, inum, UBIFS_S_KEY_BLOCK_MASK); +} + +/** * trun_key_init - initialize truncation node key. * @c: UBIFS file-system description object * @key: key to initialize @@ -518,4 +530,5 @@ static inline unsigned long long key_max_inode_size(const struct ubifs_info *c) return 0; } } + #endif /* !__UBIFS_KEY_H__ */ diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index b541bd7..7e2b3d4 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -317,6 +317,8 @@ static int ubifs_write_inode(struct inode *inode, int wait) if (err) ubifs_err("can't write inode %lu, error %d", inode->i_ino, err); + else + err = dbg_check_inode_size(c, inode, ui->ui_size); } ui->dirty = 0; diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c index f249f7b..e5b1a7d 100644 --- a/fs/ubifs/tnc.c +++ b/fs/ubifs/tnc.c @@ -1159,8 +1159,8 @@ static struct ubifs_znode *dirty_cow_bottom_up(struct ubifs_info *c, * o exact match, i.e. the found zero-level znode contains key @key, then %1 * is returned and slot number of the matched branch is stored in @n; * o not exact match, which means that zero-level znode does not contain - * @key, then %0 is returned and slot number of the closed branch is stored - * in @n; + * @key, then %0 is returned and slot number of the closest branch is stored + * in @n; * o @key is so small that it is even less than the lowest key of the * leftmost zero-level node, then %0 is returned and %0 is stored in @n. * @@ -1433,7 +1433,7 @@ static int maybe_leb_gced(struct ubifs_info *c, int lnum, int gc_seq1) * @lnum: LEB number is returned here * @offs: offset is returned here * - * This function look up and reads node with key @key. The caller has to make + * This function looks up and reads node with key @key. The caller has to make * sure the @node buffer is large enough to fit the node. Returns zero in case * of success, %-ENOENT if the node was not found, and a negative error code in * case of failure. The node location can be returned in @lnum and @offs. @@ -3268,3 +3268,73 @@ out_unlock: mutex_unlock(&c->tnc_mutex); return err; } + +#ifdef CONFIG_UBIFS_FS_DEBUG + +/** + * dbg_check_inode_size - check if inode size is correct. + * @c: UBIFS file-system description object + * @inum: inode number + * @size: inode size + * + * This function makes sure that the inode size (@size) is correct and it does + * not have any pages beyond @size. Returns zero if the inode is OK, %-EINVAL + * if it has a data page beyond @size, and other negative error code in case of + * other errors. + */ +int dbg_check_inode_size(struct ubifs_info *c, const struct inode *inode, + loff_t size) +{ + int err, n; + union ubifs_key from_key, to_key, *key; + struct ubifs_znode *znode; + unsigned int block; + + if (!S_ISREG(inode->i_mode)) + return 0; + if (!(ubifs_chk_flags & UBIFS_CHK_GEN)) + return 0; + + block = (size + UBIFS_BLOCK_SIZE - 1) >> UBIFS_BLOCK_SHIFT; + data_key_init(c, &from_key, inode->i_ino, block); + highest_data_key(c, &to_key, inode->i_ino); + + mutex_lock(&c->tnc_mutex); + err = ubifs_lookup_level0(c, &from_key, &znode, &n); + if (err < 0) + goto out_unlock; + + if (err) { + err = -EINVAL; + key = &from_key; + goto out_dump; + } + + err = tnc_next(c, &znode, &n); + if (err == -ENOENT) { + err = 0; + goto out_unlock; + } + if (err < 0) + goto out_unlock; + + ubifs_assert(err == 0); + key = &znode->zbranch[n].key; + if (!key_in_range(c, key, &from_key, &to_key)) + goto out_unlock; + +out_dump: + block = key_block(c, key); + ubifs_err("inode %lu has size %lld, but there are data at offset %lld " + "(data key %s)", (unsigned long)inode->i_ino, size, + ((loff_t)block) << UBIFS_BLOCK_SHIFT, DBGKEY(key)); + dbg_dump_inode(c, inode); + dbg_dump_stack(); + err = -EINVAL; + +out_unlock: + mutex_unlock(&c->tnc_mutex); + return err; +} + +#endif /* CONFIG_UBIFS_FS_DEBUG */ -- cgit v0.10.2 From a513c184d99fe10e7b20771ef86f5f807769318f Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Wed, 9 Sep 2009 22:23:07 +0200 Subject: drm/radeon/kms: Don't try to process irq when we are unloading If module is being unloaded we should not try to handle irq especialy we should not call into drm helper or we could hard hang the computer free_irq will call the irq handler to make sure we behave properly. Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 4e1c551..4dd5ca5 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -319,6 +319,9 @@ int r100_irq_process(struct radeon_device *rdev) if (!status) { return IRQ_NONE; } + if (rdev->shutdown) { + return IRQ_NONE; + } while (status) { /* SW interrupt */ if (status & RADEON_SW_INT_TEST) { -- cgit v0.10.2 From 119e20dc149581db3064661b2e659f308f97b663 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 10 Sep 2009 02:53:50 -0400 Subject: drm/radeon/kms/r600: fix blit support select the correct max number of bytes per blit based on whether the size is multiple of 4 bytes. This determines whether we can use 8 or 32 bit pixels for the blit. airlied: also merged the IB padding patch + correcting the VS offset for context Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c index 5755647..bbb0d61 100644 --- a/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c @@ -129,6 +129,7 @@ set_shaders(struct radeon_device *rdev) radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); radeon_ring_write(rdev, 0); + gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); } @@ -248,6 +249,7 @@ set_default_state(struct radeon_device *rdev) int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; u64 gpu_addr; + int dwords; switch (rdev->family) { case CHIP_R600: @@ -394,11 +396,12 @@ set_default_state(struct radeon_device *rdev) NUM_ES_STACK_ENTRIES(num_es_stack_entries)); /* emit an IB pointing at default state */ + dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf; gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); - radeon_ring_write(rdev, (rdev->r600_blit.state_len / 4)); + radeon_ring_write(rdev, dwords); radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); @@ -441,17 +444,25 @@ static inline uint32_t i2f(uint32_t input) int r600_blit_init(struct radeon_device *rdev) { u32 obj_size; - int r; + int r, dwords; void *ptr; + u32 packet2s[16]; + int num_packet2s = 0; rdev->r600_blit.state_offset = 0; if (rdev->family >= CHIP_RV770) - rdev->r600_blit.state_len = r7xx_default_size * 4; + rdev->r600_blit.state_len = r7xx_default_size; else - rdev->r600_blit.state_len = r6xx_default_size * 4; + rdev->r600_blit.state_len = r6xx_default_size; + + dwords = rdev->r600_blit.state_len; + while (dwords & 0xf) { + packet2s[num_packet2s++] = PACKET2(0); + dwords++; + } - obj_size = rdev->r600_blit.state_len; + obj_size = dwords * 4; obj_size = ALIGN(obj_size, 256); rdev->r600_blit.vs_offset = obj_size; @@ -488,9 +499,15 @@ int r600_blit_init(struct radeon_device *rdev) } if (rdev->family >= CHIP_RV770) - memcpy_toio(ptr + rdev->r600_blit.state_offset, r7xx_default_state, rdev->r600_blit.state_len); + memcpy_toio(ptr + rdev->r600_blit.state_offset, + r7xx_default_state, rdev->r600_blit.state_len * 4); else - memcpy_toio(ptr + rdev->r600_blit.state_offset, r6xx_default_state, rdev->r600_blit.state_len); + memcpy_toio(ptr + rdev->r600_blit.state_offset, + r6xx_default_state, rdev->r600_blit.state_len * 4); + if (num_packet2s) + memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), + packet2s, num_packet2s * 4); + memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4); memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); @@ -532,7 +549,13 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) { int r; int ring_size; - const int max_size = 8192*8192; + int max_size; + + /* 8 bpp vs 32 bpp for xfer unit */ + if (size_bytes & 3) + max_size = 8192*8192; + else + max_size = 8192*8192*4; r = r600_vb_ib_get(rdev); WARN_ON(r); -- cgit v0.10.2 From 348709bad348d2fd013e1529b4cf5f220717c328 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Tue, 25 Aug 2009 15:00:55 +0300 Subject: UBIFS: do not print scary error messages needlessly At the moment UBIFS print large and scary error messages and flash dumps in case of nearly any corruption, even if it is a recoverable corruption. For example, if the master node is corrupted, ubifs_scan() prints error dumps, then UBIFS recovers just fine and goes on. This patch makes UBIFS print scary error messages only in real cases, which are not recoverable. It adds 'quiet' argument to the 'ubifs_scan()' function, so the caller may ask 'ubi_scan()' not to print error messages if the caller is able to do recovery. Signed-off-by: Artem Bityutskiy Reviewed-by: Adrian Hunter diff --git a/fs/ubifs/debug.c b/fs/ubifs/debug.c index ce2cd83..8183ee0 100644 --- a/fs/ubifs/debug.c +++ b/fs/ubifs/debug.c @@ -724,7 +724,7 @@ void dbg_dump_leb(const struct ubifs_info *c, int lnum) printk(KERN_DEBUG "(pid %d) start dumping LEB %d\n", current->pid, lnum); - sleb = ubifs_scan(c, lnum, 0, c->dbg->buf); + sleb = ubifs_scan(c, lnum, 0, c->dbg->buf, 0); if (IS_ERR(sleb)) { ubifs_err("scan error %d", (int)PTR_ERR(sleb)); return; diff --git a/fs/ubifs/gc.c b/fs/ubifs/gc.c index f0f5f15..618c270 100644 --- a/fs/ubifs/gc.c +++ b/fs/ubifs/gc.c @@ -529,7 +529,7 @@ int ubifs_garbage_collect_leb(struct ubifs_info *c, struct ubifs_lprops *lp) * We scan the entire LEB even though we only really need to scan up to * (c->leb_size - lp->free). */ - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 0); if (IS_ERR(sleb)) return PTR_ERR(sleb); diff --git a/fs/ubifs/log.c b/fs/ubifs/log.c index 56e3377..60dcf6c 100644 --- a/fs/ubifs/log.c +++ b/fs/ubifs/log.c @@ -695,7 +695,7 @@ int ubifs_consolidate_log(struct ubifs_info *c) lnum = c->ltail_lnum; write_lnum = lnum; while (1) { - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 0); if (IS_ERR(sleb)) { err = PTR_ERR(sleb); goto out_free; diff --git a/fs/ubifs/lprops.c b/fs/ubifs/lprops.c index 4cdd284..00f19b4 100644 --- a/fs/ubifs/lprops.c +++ b/fs/ubifs/lprops.c @@ -1096,7 +1096,7 @@ static int scan_check_cb(struct ubifs_info *c, } } - sleb = ubifs_scan(c, lnum, 0, c->dbg->buf); + sleb = ubifs_scan(c, lnum, 0, c->dbg->buf, 0); if (IS_ERR(sleb)) { /* * After an unclean unmount, empty and freeable LEBs diff --git a/fs/ubifs/master.c b/fs/ubifs/master.c index a88f338..6f95a16 100644 --- a/fs/ubifs/master.c +++ b/fs/ubifs/master.c @@ -40,7 +40,7 @@ static int scan_for_master(struct ubifs_info *c) lnum = UBIFS_MST_LNUM; - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 1); if (IS_ERR(sleb)) return PTR_ERR(sleb); nodes_cnt = sleb->nodes_cnt; @@ -56,7 +56,7 @@ static int scan_for_master(struct ubifs_info *c) lnum += 1; - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 1); if (IS_ERR(sleb)) return PTR_ERR(sleb); if (sleb->nodes_cnt != nodes_cnt) diff --git a/fs/ubifs/orphan.c b/fs/ubifs/orphan.c index 152a7b3..3119af3 100644 --- a/fs/ubifs/orphan.c +++ b/fs/ubifs/orphan.c @@ -670,7 +670,7 @@ static int kill_orphans(struct ubifs_info *c) struct ubifs_scan_leb *sleb; dbg_rcvry("LEB %d", lnum); - sleb = ubifs_scan(c, lnum, 0, c->sbuf); + sleb = ubifs_scan(c, lnum, 0, c->sbuf, 1); if (IS_ERR(sleb)) { sleb = ubifs_recover_leb(c, lnum, 0, c->sbuf, 0); if (IS_ERR(sleb)) { @@ -899,7 +899,7 @@ static int dbg_scan_orphans(struct ubifs_info *c, struct check_info *ci) for (lnum = c->orph_first; lnum <= c->orph_last; lnum++) { struct ubifs_scan_leb *sleb; - sleb = ubifs_scan(c, lnum, 0, c->dbg->buf); + sleb = ubifs_scan(c, lnum, 0, c->dbg->buf, 0); if (IS_ERR(sleb)) { err = PTR_ERR(sleb); break; diff --git a/fs/ubifs/recovery.c b/fs/ubifs/recovery.c index e5f6cf8..f94ddf7 100644 --- a/fs/ubifs/recovery.c +++ b/fs/ubifs/recovery.c @@ -286,7 +286,7 @@ int ubifs_recover_master_node(struct ubifs_info *c) mst = mst2; } - dbg_rcvry("recovered master node from LEB %d", + ubifs_msg("recovered master node from LEB %d", (mst == mst1 ? UBIFS_MST_LNUM : UBIFS_MST_LNUM + 1)); memcpy(c->mst_node, mst, UBIFS_MST_NODE_SZ); @@ -790,7 +790,7 @@ struct ubifs_scan_leb *ubifs_recover_log_leb(struct ubifs_info *c, int lnum, * We can only recover at the end of the log, so check that the * next log LEB is empty or out of date. */ - sleb = ubifs_scan(c, next_lnum, 0, sbuf); + sleb = ubifs_scan(c, next_lnum, 0, sbuf, 0); if (IS_ERR(sleb)) return sleb; if (sleb->nodes_cnt) { diff --git a/fs/ubifs/replay.c b/fs/ubifs/replay.c index 2970500..5c2d6d7 100644 --- a/fs/ubifs/replay.c +++ b/fs/ubifs/replay.c @@ -506,7 +506,7 @@ static int replay_bud(struct ubifs_info *c, int lnum, int offs, int jhead, if (c->need_recovery) sleb = ubifs_recover_leb(c, lnum, offs, c->sbuf, jhead != GCHD); else - sleb = ubifs_scan(c, lnum, offs, c->sbuf); + sleb = ubifs_scan(c, lnum, offs, c->sbuf, 0); if (IS_ERR(sleb)) return PTR_ERR(sleb); @@ -836,8 +836,8 @@ static int replay_log_leb(struct ubifs_info *c, int lnum, int offs, void *sbuf) const struct ubifs_cs_node *node; dbg_mnt("replay log LEB %d:%d", lnum, offs); - sleb = ubifs_scan(c, lnum, offs, sbuf); - if (IS_ERR(sleb) ) { + sleb = ubifs_scan(c, lnum, offs, sbuf, c->need_recovery); + if (IS_ERR(sleb)) { if (PTR_ERR(sleb) != -EUCLEAN || !c->need_recovery) return PTR_ERR(sleb); sleb = ubifs_recover_log_leb(c, lnum, offs, sbuf); diff --git a/fs/ubifs/scan.c b/fs/ubifs/scan.c index 892ebfe..96c5253 100644 --- a/fs/ubifs/scan.c +++ b/fs/ubifs/scan.c @@ -108,10 +108,9 @@ int ubifs_scan_a_node(const struct ubifs_info *c, void *buf, int len, int lnum, /* Make the node pads to 8-byte boundary */ if ((node_len + pad_len) & 7) { - if (!quiet) { + if (!quiet) dbg_err("bad padding length %d - %d", offs, offs + node_len + pad_len); - } return SCANNED_A_BAD_PAD_NODE; } @@ -253,15 +252,19 @@ void ubifs_scanned_corruption(const struct ubifs_info *c, int lnum, int offs, * @c: UBIFS file-system description object * @lnum: logical eraseblock number * @offs: offset to start at (usually zero) - * @sbuf: scan buffer (must be c->leb_size) + * @sbuf: scan buffer (must be of @c->leb_size bytes in size) + * @quiet: print no messages * * This function scans LEB number @lnum and returns complete information about * its contents. Returns the scaned information in case of success and, * %-EUCLEAN if the LEB neads recovery, and other negative error codes in case * of failure. + * + * If @quiet is non-zero, this function does not print large and scary + * error messages and flash dumps in case of errors. */ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, - int offs, void *sbuf) + int offs, void *sbuf, int quiet) { void *buf = sbuf + offs; int err, len = c->leb_size - offs; @@ -280,7 +283,7 @@ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, cond_resched(); - ret = ubifs_scan_a_node(c, buf, len, lnum, offs, 0); + ret = ubifs_scan_a_node(c, buf, len, lnum, offs, quiet); if (ret > 0) { /* Padding bytes or a valid padding node */ offs += ret; @@ -320,7 +323,9 @@ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, } if (offs % c->min_io_size) { - ubifs_err("empty space starts at non-aligned offset %d", offs); + if (!quiet) + ubifs_err("empty space starts at non-aligned offset %d", + offs); goto corrupted;; } @@ -331,18 +336,25 @@ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, break; for (; len; offs++, buf++, len--) if (*(uint8_t *)buf != 0xff) { - ubifs_err("corrupt empty space at LEB %d:%d", - lnum, offs); + if (!quiet) + ubifs_err("corrupt empty space at LEB %d:%d", + lnum, offs); goto corrupted; } return sleb; corrupted: - ubifs_scanned_corruption(c, lnum, offs, buf); + if (!quiet) { + ubifs_scanned_corruption(c, lnum, offs, buf); + ubifs_err("LEB %d scanning failed", lnum); + } err = -EUCLEAN; + ubifs_scan_destroy(sleb); + return ERR_PTR(err); + error: - ubifs_err("LEB %d scanning failed", lnum); + ubifs_err("LEB %d scanning failed, error %d", lnum, err); ubifs_scan_destroy(sleb); return ERR_PTR(err); } diff --git a/fs/ubifs/tnc_commit.c b/fs/ubifs/tnc_commit.c index fde8d12..53288e5 100644 --- a/fs/ubifs/tnc_commit.c +++ b/fs/ubifs/tnc_commit.c @@ -245,7 +245,7 @@ static int layout_leb_in_gaps(struct ubifs_info *c, int *p) * it is more comprehensive and less efficient than is needed for this * purpose. */ - sleb = ubifs_scan(c, lnum, 0, c->ileb_buf); + sleb = ubifs_scan(c, lnum, 0, c->ileb_buf, 0); c->ileb_len = 0; if (IS_ERR(sleb)) return PTR_ERR(sleb); diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index a293490..9782e7c 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -1451,7 +1451,7 @@ int ubifs_sync_wbufs_by_inode(struct ubifs_info *c, struct inode *inode); /* scan.c */ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum, - int offs, void *sbuf); + int offs, void *sbuf, int quiet); void ubifs_scan_destroy(struct ubifs_scan_leb *sleb); int ubifs_scan_a_node(const struct ubifs_info *c, void *buf, int len, int lnum, int offs, int quiet); -- cgit v0.10.2 From 0dcd18e4073454daf591e7127247e32ec942b4f3 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Tue, 25 Aug 2009 16:22:53 +0300 Subject: UBIFS: check ubifs_scan error codes better The 'ubifs_scan()' function returns -EUCLEAN if something is corrupted and recovery is needed, otherwise it returns other error codes. However, in few places UBIFS does not check the error codes and runs recovery. This patch changes this behavior and makes UBIFS start recovery only on -EUCLEAN errors. Signed-off-by: Artem Bityutskiy Reviewed-by: Adrian Hunter diff --git a/fs/ubifs/master.c b/fs/ubifs/master.c index 6f95a16..28beaee 100644 --- a/fs/ubifs/master.c +++ b/fs/ubifs/master.c @@ -29,7 +29,8 @@ * @c: UBIFS file-system description object * * This function scans the master node LEBs and search for the latest master - * node. Returns zero in case of success and a negative error code in case of + * node. Returns zero in case of success, %-EUCLEAN if there master area is + * corrupted and requires recovery, and a negative error code in case of * failure. */ static int scan_for_master(struct ubifs_info *c) @@ -48,7 +49,7 @@ static int scan_for_master(struct ubifs_info *c) snod = list_entry(sleb->nodes.prev, struct ubifs_scan_node, list); if (snod->type != UBIFS_MST_NODE) - goto out; + goto out_dump; memcpy(c->mst_node, snod->node, snod->len); offs = snod->offs; } @@ -65,7 +66,7 @@ static int scan_for_master(struct ubifs_info *c) goto out; snod = list_entry(sleb->nodes.prev, struct ubifs_scan_node, list); if (snod->type != UBIFS_MST_NODE) - goto out; + goto out_dump; if (snod->offs != offs) goto out; if (memcmp((void *)c->mst_node + UBIFS_CH_SZ, @@ -78,6 +79,12 @@ static int scan_for_master(struct ubifs_info *c) out: ubifs_scan_destroy(sleb); + return -EUCLEAN; + +out_dump: + ubifs_err("unexpected node type %d master LEB %d:%d", + snod->type, lnum, snod->offs); + ubifs_scan_destroy(sleb); return -EINVAL; } @@ -256,7 +263,8 @@ int ubifs_read_master(struct ubifs_info *c) err = scan_for_master(c); if (err) { - err = ubifs_recover_master_node(c); + if (err == -EUCLEAN) + err = ubifs_recover_master_node(c); if (err) /* * Note, we do not free 'c->mst_node' here because the diff --git a/fs/ubifs/orphan.c b/fs/ubifs/orphan.c index 3119af3..82009c7 100644 --- a/fs/ubifs/orphan.c +++ b/fs/ubifs/orphan.c @@ -672,7 +672,8 @@ static int kill_orphans(struct ubifs_info *c) dbg_rcvry("LEB %d", lnum); sleb = ubifs_scan(c, lnum, 0, c->sbuf, 1); if (IS_ERR(sleb)) { - sleb = ubifs_recover_leb(c, lnum, 0, c->sbuf, 0); + if (PTR_ERR(sleb) == -EUCLEAN) + sleb = ubifs_recover_leb(c, lnum, 0, c->sbuf, 0); if (IS_ERR(sleb)) { err = PTR_ERR(sleb); break; -- cgit v0.10.2 From 873a64c762f0c52cdf95dcee59bd416bbf9688e6 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Tue, 1 Sep 2009 17:06:43 +0300 Subject: UBIFS: amend commentaries This patch amends and nicifies commentaries in file.c, as well as fixes some spelling problems. Signed-off-by: Artem Bityutskiy diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c index 6d34dc7..2e6481a 100644 --- a/fs/ubifs/file.c +++ b/fs/ubifs/file.c @@ -21,34 +21,32 @@ */ /* - * This file implements VFS file and inode operations of regular files, device + * This file implements VFS file and inode operations for regular files, device * nodes and symlinks as well as address space operations. * - * UBIFS uses 2 page flags: PG_private and PG_checked. PG_private is set if the - * page is dirty and is used for budgeting purposes - dirty pages should not be - * budgeted. The PG_checked flag is set if full budgeting is required for the - * page e.g., when it corresponds to a file hole or it is just beyond the file - * size. The budgeting is done in 'ubifs_write_begin()', because it is OK to - * fail in this function, and the budget is released in 'ubifs_write_end()'. So - * the PG_private and PG_checked flags carry the information about how the page - * was budgeted, to make it possible to release the budget properly. + * UBIFS uses 2 page flags: @PG_private and @PG_checked. @PG_private is set if + * the page is dirty and is used for optimization purposes - dirty pages are + * not budgeted so the flag shows that 'ubifs_write_end()' should not release + * the budget for this page. The @PG_checked flag is set if full budgeting is + * required for the page e.g., when it corresponds to a file hole or it is + * beyond the file size. The budgeting is done in 'ubifs_write_begin()', because + * it is OK to fail in this function, and the budget is released in + * 'ubifs_write_end()'. So the @PG_private and @PG_checked flags carry + * information about how the page was budgeted, to make it possible to release + * the budget properly. * - * A thing to keep in mind: inode's 'i_mutex' is locked in most VFS operations - * we implement. However, this is not true for '->writepage()', which might be - * called with 'i_mutex' unlocked. For example, when pdflush is performing - * write-back, it calls 'writepage()' with unlocked 'i_mutex', although the - * inode has 'I_LOCK' flag in this case. At "normal" work-paths 'i_mutex' is - * locked in '->writepage', e.g. in "sys_write -> alloc_pages -> direct reclaim - * path'. So, in '->writepage()' we are only guaranteed that the page is - * locked. + * A thing to keep in mind: inode @i_mutex is locked in most VFS operations we + * implement. However, this is not true for 'ubifs_writepage()', which may be + * called with @i_mutex unlocked. For example, when pdflush is doing background + * write-back, it calls 'ubifs_writepage()' with unlocked @i_mutex. At "normal" + * work-paths the @i_mutex is locked in 'ubifs_writepage()', e.g. in the + * "sys_write -> alloc_pages -> direct reclaim path". So, in 'ubifs_writepage()' + * we are only guaranteed that the page is locked. * - * Similarly, 'i_mutex' does not have to be locked in readpage(), e.g., - * readahead path does not have it locked ("sys_read -> generic_file_aio_read - * -> ondemand_readahead -> readpage"). In case of readahead, 'I_LOCK' flag is - * not set as well. However, UBIFS disables readahead. - * - * This, for example means that there might be 2 concurrent '->writepage()' - * calls for the same inode, but different inode dirty pages. + * Similarly, @i_mutex is not always locked in 'ubifs_readpage()', e.g., the + * read-ahead path does not lock it ("sys_read -> generic_file_aio_read -> + * ondemand_readahead -> readpage"). In case of readahead, @I_LOCK flag is not + * set as well. However, UBIFS disables readahead. */ #include "ubifs.h" @@ -449,9 +447,9 @@ static int ubifs_write_begin(struct file *file, struct address_space *mapping, /* * We change whole page so no need to load it. But we * have to set the @PG_checked flag to make the further - * code the page is new. This might be not true, but it - * is better to budget more that to read the page from - * the media. + * code know that the page is new. This might be not + * true, but it is better to budget more than to read + * the page from the media. */ SetPageChecked(page); skipped_read = 1; @@ -497,8 +495,8 @@ static int ubifs_write_begin(struct file *file, struct address_space *mapping, } /* - * Whee, we aquired budgeting quickly - without involving - * garbage-collection, committing or forceing write-back. We return + * Whee, we acquired budgeting quickly - without involving + * garbage-collection, committing or forcing write-back. We return * with @ui->ui_mutex locked if we are appending pages, and unlocked * otherwise. This is an optimization (slightly hacky though). */ @@ -562,7 +560,7 @@ static int ubifs_write_end(struct file *file, struct address_space *mapping, /* * Return 0 to force VFS to repeat the whole operation, or the - * error code if 'do_readpage()' failes. + * error code if 'do_readpage()' fails. */ copied = do_readpage(page); goto out; @@ -1175,11 +1173,11 @@ static int do_truncation(struct ubifs_info *c, struct inode *inode, ui->ui_size = inode->i_size; /* Truncation changes inode [mc]time */ inode->i_mtime = inode->i_ctime = ubifs_current_time(inode); - /* The other attributes may be changed at the same time as well */ + /* Other attributes may be changed at the same time as well */ do_attr_changes(inode, attr); - err = ubifs_jnl_truncate(c, inode, old_size, new_size); mutex_unlock(&ui->ui_mutex); + out_budg: if (budgeted) ubifs_release_budget(c, &req); -- cgit v0.10.2 From ee297936a7ed7e8477a200eb9c6de13150adbf0c Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 7 Aug 2009 15:51:12 +0200 Subject: [ARM] pxa: remove left-over struct clk *other field from struct clk Its removal was omitted when all its uses were removed in 8c3abc7d... "[ARM] pxa: convert to clkdev and match clocks by struct device where possible" Signed-off-by: Philipp Zabel Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h index 5599bce..978a366 100644 --- a/arch/arm/mach-pxa/clock.h +++ b/arch/arm/mach-pxa/clock.h @@ -12,7 +12,6 @@ struct clk { unsigned int cken; unsigned int delay; unsigned int enabled; - struct clk *other; }; #define INIT_CLKREG(_clk,_devname,_conname) \ -- cgit v0.10.2 From 9304d008d6ba41ff52ef6eae44337398e83b4436 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 31 Aug 2009 20:16:54 +0800 Subject: [ARM] pxa: remove duplicate mfp definition in mach Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/include/mach/mfp.h b/arch/arm/mach-pxa/include/mach/mfp.h index 4821850..271e249 100644 --- a/arch/arm/mach-pxa/include/mach/mfp.h +++ b/arch/arm/mach-pxa/include/mach/mfp.h @@ -16,305 +16,6 @@ #ifndef __ASM_ARCH_MFP_H #define __ASM_ARCH_MFP_H -#define mfp_to_gpio(m) ((m) % 128) - -/* list of all the configurable MFP pins */ -enum { - MFP_PIN_INVALID = -1, - - MFP_PIN_GPIO0 = 0, - MFP_PIN_GPIO1, - MFP_PIN_GPIO2, - MFP_PIN_GPIO3, - MFP_PIN_GPIO4, - MFP_PIN_GPIO5, - MFP_PIN_GPIO6, - MFP_PIN_GPIO7, - MFP_PIN_GPIO8, - MFP_PIN_GPIO9, - MFP_PIN_GPIO10, - MFP_PIN_GPIO11, - MFP_PIN_GPIO12, - MFP_PIN_GPIO13, - MFP_PIN_GPIO14, - MFP_PIN_GPIO15, - MFP_PIN_GPIO16, - MFP_PIN_GPIO17, - MFP_PIN_GPIO18, - MFP_PIN_GPIO19, - MFP_PIN_GPIO20, - MFP_PIN_GPIO21, - MFP_PIN_GPIO22, - MFP_PIN_GPIO23, - MFP_PIN_GPIO24, - MFP_PIN_GPIO25, - MFP_PIN_GPIO26, - MFP_PIN_GPIO27, - MFP_PIN_GPIO28, - MFP_PIN_GPIO29, - MFP_PIN_GPIO30, - MFP_PIN_GPIO31, - MFP_PIN_GPIO32, - MFP_PIN_GPIO33, - MFP_PIN_GPIO34, - MFP_PIN_GPIO35, - MFP_PIN_GPIO36, - MFP_PIN_GPIO37, - MFP_PIN_GPIO38, - MFP_PIN_GPIO39, - MFP_PIN_GPIO40, - MFP_PIN_GPIO41, - MFP_PIN_GPIO42, - MFP_PIN_GPIO43, - MFP_PIN_GPIO44, - MFP_PIN_GPIO45, - MFP_PIN_GPIO46, - MFP_PIN_GPIO47, - MFP_PIN_GPIO48, - MFP_PIN_GPIO49, - MFP_PIN_GPIO50, - MFP_PIN_GPIO51, - MFP_PIN_GPIO52, - MFP_PIN_GPIO53, - MFP_PIN_GPIO54, - MFP_PIN_GPIO55, - MFP_PIN_GPIO56, - MFP_PIN_GPIO57, - MFP_PIN_GPIO58, - MFP_PIN_GPIO59, - MFP_PIN_GPIO60, - MFP_PIN_GPIO61, - MFP_PIN_GPIO62, - MFP_PIN_GPIO63, - MFP_PIN_GPIO64, - MFP_PIN_GPIO65, - MFP_PIN_GPIO66, - MFP_PIN_GPIO67, - MFP_PIN_GPIO68, - MFP_PIN_GPIO69, - MFP_PIN_GPIO70, - MFP_PIN_GPIO71, - MFP_PIN_GPIO72, - MFP_PIN_GPIO73, - MFP_PIN_GPIO74, - MFP_PIN_GPIO75, - MFP_PIN_GPIO76, - MFP_PIN_GPIO77, - MFP_PIN_GPIO78, - MFP_PIN_GPIO79, - MFP_PIN_GPIO80, - MFP_PIN_GPIO81, - MFP_PIN_GPIO82, - MFP_PIN_GPIO83, - MFP_PIN_GPIO84, - MFP_PIN_GPIO85, - MFP_PIN_GPIO86, - MFP_PIN_GPIO87, - MFP_PIN_GPIO88, - MFP_PIN_GPIO89, - MFP_PIN_GPIO90, - MFP_PIN_GPIO91, - MFP_PIN_GPIO92, - MFP_PIN_GPIO93, - MFP_PIN_GPIO94, - MFP_PIN_GPIO95, - MFP_PIN_GPIO96, - MFP_PIN_GPIO97, - MFP_PIN_GPIO98, - MFP_PIN_GPIO99, - MFP_PIN_GPIO100, - MFP_PIN_GPIO101, - MFP_PIN_GPIO102, - MFP_PIN_GPIO103, - MFP_PIN_GPIO104, - MFP_PIN_GPIO105, - MFP_PIN_GPIO106, - MFP_PIN_GPIO107, - MFP_PIN_GPIO108, - MFP_PIN_GPIO109, - MFP_PIN_GPIO110, - MFP_PIN_GPIO111, - MFP_PIN_GPIO112, - MFP_PIN_GPIO113, - MFP_PIN_GPIO114, - MFP_PIN_GPIO115, - MFP_PIN_GPIO116, - MFP_PIN_GPIO117, - MFP_PIN_GPIO118, - MFP_PIN_GPIO119, - MFP_PIN_GPIO120, - MFP_PIN_GPIO121, - MFP_PIN_GPIO122, - MFP_PIN_GPIO123, - MFP_PIN_GPIO124, - MFP_PIN_GPIO125, - MFP_PIN_GPIO126, - MFP_PIN_GPIO127, - MFP_PIN_GPIO0_2, - MFP_PIN_GPIO1_2, - MFP_PIN_GPIO2_2, - MFP_PIN_GPIO3_2, - MFP_PIN_GPIO4_2, - MFP_PIN_GPIO5_2, - MFP_PIN_GPIO6_2, - MFP_PIN_GPIO7_2, - MFP_PIN_GPIO8_2, - MFP_PIN_GPIO9_2, - MFP_PIN_GPIO10_2, - MFP_PIN_GPIO11_2, - MFP_PIN_GPIO12_2, - MFP_PIN_GPIO13_2, - MFP_PIN_GPIO14_2, - MFP_PIN_GPIO15_2, - MFP_PIN_GPIO16_2, - MFP_PIN_GPIO17_2, - - MFP_PIN_ULPI_STP, - MFP_PIN_ULPI_NXT, - MFP_PIN_ULPI_DIR, - - MFP_PIN_nXCVREN, - MFP_PIN_DF_CLE_nOE, - MFP_PIN_DF_nADV1_ALE, - MFP_PIN_DF_SCLK_E, - MFP_PIN_DF_SCLK_S, - MFP_PIN_nBE0, - MFP_PIN_nBE1, - MFP_PIN_DF_nADV2_ALE, - MFP_PIN_DF_INT_RnB, - MFP_PIN_DF_nCS0, - MFP_PIN_DF_nCS1, - MFP_PIN_nLUA, - MFP_PIN_nLLA, - MFP_PIN_DF_nWE, - MFP_PIN_DF_ALE_nWE, - MFP_PIN_DF_nRE_nOE, - MFP_PIN_DF_ADDR0, - MFP_PIN_DF_ADDR1, - MFP_PIN_DF_ADDR2, - MFP_PIN_DF_ADDR3, - MFP_PIN_DF_IO0, - MFP_PIN_DF_IO1, - MFP_PIN_DF_IO2, - MFP_PIN_DF_IO3, - MFP_PIN_DF_IO4, - MFP_PIN_DF_IO5, - MFP_PIN_DF_IO6, - MFP_PIN_DF_IO7, - MFP_PIN_DF_IO8, - MFP_PIN_DF_IO9, - MFP_PIN_DF_IO10, - MFP_PIN_DF_IO11, - MFP_PIN_DF_IO12, - MFP_PIN_DF_IO13, - MFP_PIN_DF_IO14, - MFP_PIN_DF_IO15, - - /* additional pins on PXA930 */ - MFP_PIN_GSIM_UIO, - MFP_PIN_GSIM_UCLK, - MFP_PIN_GSIM_UDET, - MFP_PIN_GSIM_nURST, - MFP_PIN_PMIC_INT, - MFP_PIN_RDY, - - MFP_PIN_MAX, -}; - -/* - * a possible MFP configuration is represented by a 32-bit integer - * - * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) - * bit 10..12 - Alternate Function Selection - * bit 13..15 - Drive Strength - * bit 16..18 - Low Power Mode State - * bit 19..20 - Low Power Mode Edge Detection - * bit 21..22 - Run Mode Pull State - * - * to facilitate the definition, the following macros are provided - * - * MFP_CFG_DEFAULT - default MFP configuration value, with - * alternate function = 0, - * drive strength = fast 3mA (MFP_DS03X) - * low power mode = default - * edge detection = none - * - * MFP_CFG - default MFPR value with alternate function - * MFP_CFG_DRV - default MFPR value with alternate function and - * pin drive strength - * MFP_CFG_LPM - default MFPR value with alternate function and - * low power mode - * MFP_CFG_X - default MFPR value with alternate function, - * pin drive strength and low power mode - */ - -typedef unsigned long mfp_cfg_t; - -#define MFP_PIN(x) ((x) & 0x3ff) - -#define MFP_AF0 (0x0 << 10) -#define MFP_AF1 (0x1 << 10) -#define MFP_AF2 (0x2 << 10) -#define MFP_AF3 (0x3 << 10) -#define MFP_AF4 (0x4 << 10) -#define MFP_AF5 (0x5 << 10) -#define MFP_AF6 (0x6 << 10) -#define MFP_AF7 (0x7 << 10) -#define MFP_AF_MASK (0x7 << 10) -#define MFP_AF(x) (((x) >> 10) & 0x7) - -#define MFP_DS01X (0x0 << 13) -#define MFP_DS02X (0x1 << 13) -#define MFP_DS03X (0x2 << 13) -#define MFP_DS04X (0x3 << 13) -#define MFP_DS06X (0x4 << 13) -#define MFP_DS08X (0x5 << 13) -#define MFP_DS10X (0x6 << 13) -#define MFP_DS13X (0x7 << 13) -#define MFP_DS_MASK (0x7 << 13) -#define MFP_DS(x) (((x) >> 13) & 0x7) - -#define MFP_LPM_DEFAULT (0x0 << 16) -#define MFP_LPM_DRIVE_LOW (0x1 << 16) -#define MFP_LPM_DRIVE_HIGH (0x2 << 16) -#define MFP_LPM_PULL_LOW (0x3 << 16) -#define MFP_LPM_PULL_HIGH (0x4 << 16) -#define MFP_LPM_FLOAT (0x5 << 16) -#define MFP_LPM_INPUT (0x6 << 16) -#define MFP_LPM_STATE_MASK (0x7 << 16) -#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7) - -#define MFP_LPM_EDGE_NONE (0x0 << 19) -#define MFP_LPM_EDGE_RISE (0x1 << 19) -#define MFP_LPM_EDGE_FALL (0x2 << 19) -#define MFP_LPM_EDGE_BOTH (0x3 << 19) -#define MFP_LPM_EDGE_MASK (0x3 << 19) -#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3) - -#define MFP_PULL_NONE (0x0 << 21) -#define MFP_PULL_LOW (0x1 << 21) -#define MFP_PULL_HIGH (0x2 << 21) -#define MFP_PULL_BOTH (0x3 << 21) -#define MFP_PULL_MASK (0x3 << 21) -#define MFP_PULL(x) (((x) >> 21) & 0x3) - -#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\ - MFP_LPM_EDGE_NONE | MFP_PULL_NONE) - -#define MFP_CFG(pin, af) \ - ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af)) - -#define MFP_CFG_DRV(pin, af, drv) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv)) - -#define MFP_CFG_LPM(pin, af, lpm) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm)) - -#define MFP_CFG_X(pin, af, drv, lpm) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) +#include #endif /* __ASM_ARCH_MFP_H */ -- cgit v0.10.2 From fb60870f630f926d2299b6ebd31fc94714dcd734 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Tue, 11 Aug 2009 14:39:09 +0200 Subject: [ARM] pxa: add MFP_PULL_FLOAT There is currently an uncovered case for MFP configuration on PXAs which is selected by setting the PULL_SEL bit but none of the PULL{UP,DOWN}_EN bits. This case is needed to explicitly let pins float, even if the selected alternate function would default to a configuration with a pull resistor enabled. Signed-off-by: Daniel Mack Signed-off-by: Eric Miao diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h index 6401946..08ad665 100644 --- a/arch/arm/plat-pxa/include/plat/mfp.h +++ b/arch/arm/plat-pxa/include/plat/mfp.h @@ -325,8 +325,9 @@ typedef unsigned long mfp_cfg_t; #define MFP_PULL_LOW (0x1 << 21) #define MFP_PULL_HIGH (0x2 << 21) #define MFP_PULL_BOTH (0x3 << 21) -#define MFP_PULL_MASK (0x3 << 21) -#define MFP_PULL(x) (((x) >> 21) & 0x3) +#define MFP_PULL_FLOAT (0x4 << 21) +#define MFP_PULL_MASK (0x7 << 21) +#define MFP_PULL(x) (((x) >> 21) & 0x7) #define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\ MFP_LPM_EDGE_NONE | MFP_PULL_NONE) diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c index e716c62..9405d03 100644 --- a/arch/arm/plat-pxa/mfp.c +++ b/arch/arm/plat-pxa/mfp.c @@ -77,11 +77,13 @@ * MFPR_PULL_LOW 1 0 1 * MFPR_PULL_HIGH 1 1 0 * MFPR_PULL_BOTH 1 1 1 + * MFPR_PULL_FLOAT 1 0 0 */ #define MFPR_PULL_NONE (0) #define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN) #define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN) #define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN) +#define MFPR_PULL_FLOAT (MFPR_PULL_SEL) /* mfp_spin_lock is used to ensure that MFP register configuration * (most likely a read-modify-write operation) is atomic, and that @@ -116,6 +118,7 @@ static const unsigned long mfpr_pull[] = { MFPR_PULL_LOW, MFPR_PULL_HIGH, MFPR_PULL_BOTH, + MFPR_PULL_FLOAT, }; /* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */ -- cgit v0.10.2 From 063936df925f54a32649490f828af9af66ef8c8e Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 17 Jun 2009 13:57:40 +0800 Subject: [ARM] pxa: support mfp of pxa935 Add and initialize the mfp setting of pxa935 chip. Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c index 7113174..0642920 100644 --- a/arch/arm/mach-pxa/pxa930.c +++ b/arch/arm/mach-pxa/pxa930.c @@ -176,13 +176,30 @@ static struct mfp_addr_map pxa930_mfp_addr_map[] __initdata = { MFP_ADDR_END, }; +static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = { + MFP_ADDR(GPIO159, 0x0524), + MFP_ADDR(GPIO163, 0x0534), + MFP_ADDR(GPIO167, 0x0544), + MFP_ADDR(GPIO168, 0x0548), + MFP_ADDR(GPIO169, 0x054c), + MFP_ADDR(GPIO170, 0x0550), + MFP_ADDR(GPIO171, 0x0554), + MFP_ADDR(GPIO172, 0x0558), + MFP_ADDR(GPIO173, 0x055c), + + MFP_ADDR_END, +}; + static int __init pxa930_init(void) { - if (cpu_is_pxa930()) { + if (cpu_is_pxa930() || cpu_is_pxa935()) { mfp_init_base(io_p2v(MFPR_BASE)); mfp_init_addr(pxa930_mfp_addr_map); } + if (cpu_is_pxa935()) + mfp_init_addr(pxa935_mfp_addr_map); + return 0; } diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h index 08ad665..22086e6 100644 --- a/arch/arm/plat-pxa/include/plat/mfp.h +++ b/arch/arm/plat-pxa/include/plat/mfp.h @@ -150,6 +150,74 @@ enum { MFP_PIN_GPIO125, MFP_PIN_GPIO126, MFP_PIN_GPIO127, + + MFP_PIN_GPIO128, + MFP_PIN_GPIO129, + MFP_PIN_GPIO130, + MFP_PIN_GPIO131, + MFP_PIN_GPIO132, + MFP_PIN_GPIO133, + MFP_PIN_GPIO134, + MFP_PIN_GPIO135, + MFP_PIN_GPIO136, + MFP_PIN_GPIO137, + MFP_PIN_GPIO138, + MFP_PIN_GPIO139, + MFP_PIN_GPIO140, + MFP_PIN_GPIO141, + MFP_PIN_GPIO142, + MFP_PIN_GPIO143, + MFP_PIN_GPIO144, + MFP_PIN_GPIO145, + MFP_PIN_GPIO146, + MFP_PIN_GPIO147, + MFP_PIN_GPIO148, + MFP_PIN_GPIO149, + MFP_PIN_GPIO150, + MFP_PIN_GPIO151, + MFP_PIN_GPIO152, + MFP_PIN_GPIO153, + MFP_PIN_GPIO154, + MFP_PIN_GPIO155, + MFP_PIN_GPIO156, + MFP_PIN_GPIO157, + MFP_PIN_GPIO158, + MFP_PIN_GPIO159, + MFP_PIN_GPIO160, + MFP_PIN_GPIO161, + MFP_PIN_GPIO162, + MFP_PIN_GPIO163, + MFP_PIN_GPIO164, + MFP_PIN_GPIO165, + MFP_PIN_GPIO166, + MFP_PIN_GPIO167, + MFP_PIN_GPIO168, + MFP_PIN_GPIO169, + MFP_PIN_GPIO170, + MFP_PIN_GPIO171, + MFP_PIN_GPIO172, + MFP_PIN_GPIO173, + MFP_PIN_GPIO174, + MFP_PIN_GPIO175, + MFP_PIN_GPIO176, + MFP_PIN_GPIO177, + MFP_PIN_GPIO178, + MFP_PIN_GPIO179, + MFP_PIN_GPIO180, + MFP_PIN_GPIO181, + MFP_PIN_GPIO182, + MFP_PIN_GPIO183, + MFP_PIN_GPIO184, + MFP_PIN_GPIO185, + MFP_PIN_GPIO186, + MFP_PIN_GPIO187, + MFP_PIN_GPIO188, + MFP_PIN_GPIO189, + MFP_PIN_GPIO190, + MFP_PIN_GPIO191, + + MFP_PIN_GPIO255 = 255, + MFP_PIN_GPIO0_2, MFP_PIN_GPIO1_2, MFP_PIN_GPIO2_2, -- cgit v0.10.2 From 9db95cb6c430b3d9b8abbd5870e0d1e69b884ba0 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 31 Aug 2009 17:23:44 +0800 Subject: [ARM] pxa: expand irq support for PXA93x and PXA950 PXA93x/950 has additional 64 GPIOs, each is a secondary interrupt source for IRQ_GPIO_2_x, extend PXA_GPIO_IRQ_{BASE,NUM}. PXA93x/950 specific IRQ definitions are added as well. Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index 6a1d959..abd2c2c 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -68,6 +68,7 @@ #ifdef CONFIG_PXA3xx #define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */ #define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ +#define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */ #define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ #define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ #define IRQ_GRPHICS PXA_IRQ(39) /* Graphics Controller */ @@ -81,8 +82,31 @@ #define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ #endif -#define PXA_GPIO_IRQ_BASE PXA_IRQ(64) -#define PXA_GPIO_IRQ_NUM (128) +#ifdef CONFIG_CPU_PXA935 +#define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */ +#define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */ + +#define IRQ_MMC3_PXA935 PXA_IRQ(72) /* MMC3 Controller (PXA935) */ +#define IRQ_MMC4_PXA935 PXA_IRQ(73) /* MMC4 Controller (PXA935) */ +#define IRQ_MMC5_PXA935 PXA_IRQ(74) /* MMC5 Controller (PXA935) */ + +#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ +#endif + +#ifdef CONFIG_CPU_PXA930 +#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */ +#define IRQ_ACIPC0 PXA_IRQ(5) +#define IRQ_ACIPC1 PXA_IRQ(40) +#define IRQ_ACIPC2 PXA_IRQ(19) +#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball */ +#endif + +#ifdef CONFIG_CPU_PXA950 +#define IRQ_GC500 PXA_IRQ(70) /* Graphics Controller (PXA950) */ +#endif + +#define PXA_GPIO_IRQ_BASE PXA_IRQ(96) +#define PXA_GPIO_IRQ_NUM (192) #define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) #define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) -- cgit v0.10.2 From 337c1db645bce3f5a832129c4a803dc157ac7e9a Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 21 Aug 2009 16:10:41 +0800 Subject: [ARM] pxa: update cpu_is_xsc3() to include Marvell CPUID CPU id is changed in Marvell chip. So update the code in cpu_is_xsc3(). Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index b3e656c..7c6e208 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -73,7 +73,10 @@ static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) #else static inline int cpu_is_xsc3(void) { - if ((read_cpuid_id() & 0xffffe000) == 0x69056000) + unsigned int id; + id = read_cpuid_id() & 0xffffe000; + /* It covers both Intel ID and Marvell ID */ + if ((id == 0x69056000) || (id == 0x56056000)) return 1; return 0; -- cgit v0.10.2 From 4646dd2795e793f97b7fd40206567bf72e6cdf21 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 26 Aug 2009 10:32:00 +0800 Subject: [ARM] pxa: add cpu_is_pxa950() and Kconfig options Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 89c992b..626cecb 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -21,6 +21,11 @@ config CPU_PXA930 config CPU_PXA935 bool "PXA935 (codename Tavor-P65)" + select CPU_PXA930 + +config CPU_PXA950 + bool "PXA950 (codename Tavor-PV2)" + select CPU_PXA930 endmenu diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index 16ab795..aa3d9f7 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -197,6 +197,16 @@ #define __cpu_is_pxa935(id) (0) #endif +#ifdef CONFIG_CPU_PXA950 +#define __cpu_is_pxa950(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + id == 0x697; \ + }) +#else +#define __cpu_is_pxa950(id) (0) +#endif + #define cpu_is_pxa210() \ ({ \ __cpu_is_pxa210(read_cpuid_id()); \ @@ -249,6 +259,13 @@ __cpu_is_pxa935(id); \ }) +#define cpu_is_pxa950() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa950(id); \ + }) + + /* * CPUID Core Generation Bit * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x -- cgit v0.10.2 From 6ba39282bb3ee486a142ee3fd61196d329622ed9 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 19 Aug 2009 19:30:24 +0800 Subject: [ARM] pxa: add more registers in interrupt controller Add priority registers and new registers of pxa935. Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h index ad23e74..68464ce 100644 --- a/arch/arm/mach-pxa/include/mach/regs-intc.h +++ b/arch/arm/mach-pxa/include/mach/regs-intc.h @@ -13,6 +13,7 @@ #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ +#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */ #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ @@ -20,4 +21,14 @@ #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ +#define ICIP3 __REG(0x40D00130) /* Interrupt Controller IRQ Pending Register 3 */ +#define ICMR3 __REG(0x40D00134) /* Interrupt Controller Mask Register 3 */ +#define ICLR3 __REG(0x40D00138) /* Interrupt Controller Level Register 3 */ +#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */ +#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */ + +#define IPR(x) __REG(0x40D0001C + (x < 32 ? (x << 2) \ + : (x < 64 ? (0x94 + ((x - 32) << 2)) \ + : (0x128 + ((x - 64) << 2))))) + #endif /* __ASM_MACH_REGS_INTC_H */ -- cgit v0.10.2 From d2c37068429b29d6549cf3486fc84b836689e122 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 19 Aug 2009 19:49:31 +0800 Subject: [ARM] pxa: initialize default interrupt priority and use ICHP for IRQ handling Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S index f6b4bf3..2418806 100644 --- a/arch/arm/mach-pxa/include/mach/entry-macro.S +++ b/arch/arm/mach-pxa/include/mach/entry-macro.S @@ -24,34 +24,27 @@ mov \tmp, \tmp, lsr #13 and \tmp, \tmp, #0x7 @ Core G cmp \tmp, #1 - bhi 1004f + bhi 1002f + @ Core Generation 1 (PXA25x) mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000 add \base, \base, #0x00d00000 ldr \irqstat, [\base, #0] @ ICIP ldr \irqnr, [\base, #4] @ ICMR - b 1002f -1004: - mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2 - mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2 ands \irqnr, \irqstat, \irqnr - beq 1003f + beq 1001f rsb \irqstat, \irqnr, #0 and \irqstat, \irqstat, \irqnr clz \irqnr, \irqstat - rsb \irqnr, \irqnr, #31 - add \irqnr, \irqnr, #(32 + PXA_IRQ(0)) + rsb \irqnr, \irqnr, #(31 + PXA_IRQ(0)) b 1001f -1003: - mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP - mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR 1002: - ands \irqnr, \irqstat, \irqnr + @ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx) + mrc p6, 0, \irqstat, c5, c0, 0 @ ICHP + tst \irqstat, #0x80000000 beq 1001f - rsb \irqstat, \irqnr, #0 - and \irqstat, \irqstat, \irqnr - clz \irqnr, \irqstat - rsb \irqnr, \irqnr, #(31 + PXA_IRQ(0)) + bic \irqstat, \irqstat, #0x80000000 + mov \irqnr, \irqstat, lsr #16 1001: .endm diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index f6e0300..d694ce2 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -120,7 +120,7 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn) void __init pxa_init_irq(int irq_nr, set_wake_t fn) { - int irq; + int irq, i; pxa_internal_irq_nr = irq_nr; @@ -129,6 +129,12 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */ } + /* initialize interrupt priority */ + if (cpu_is_pxa27x() || cpu_is_pxa3xx()) { + for (i = 0; i < irq_nr; i++) + IPR(i) = i | (1 << 31); + } + /* only unmasked interrupts kick us out of idle */ ICCR = 1; -- cgit v0.10.2 From f0f04f0840e41411895056bece50bfbd5dfc81cc Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 9 Jul 2009 19:04:48 +0200 Subject: [ARM] pxa: add clock definition for graphics controller Signed-off-by: Daniel Mack Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index 7d1a059..e91d63c 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -208,7 +208,7 @@ #define CKEN_MVED 43 /* < MVED clock enable */ /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ -#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */ -#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */ +#define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */ +#define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */ #endif /* __ASM_ARCH_PXA3XX_REGS_H */ diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c index 4ba6d21..f4af6e2b 100644 --- a/arch/arm/mach-pxa/pxa300.c +++ b/arch/arm/mach-pxa/pxa300.c @@ -84,9 +84,11 @@ static struct mfp_addr_map pxa310_mfp_addr_map[] __initdata = { }; static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0); +static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0); static struct clk_lookup common_clkregs[] = { INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL), }; static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0); diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c index 8b3d97e..c7373e7 100644 --- a/arch/arm/mach-pxa/pxa320.c +++ b/arch/arm/mach-pxa/pxa320.c @@ -78,9 +78,11 @@ static struct mfp_addr_map pxa320_mfp_addr_map[] __initdata = { }; static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0); +static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0); static struct clk_lookup pxa320_clkregs[] = { INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL), }; static int __init pxa320_init(void) -- cgit v0.10.2 From 1ff2c33e197f0a65e4641b2dbac1a8c85f5204dd Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 9 Jul 2009 19:04:49 +0200 Subject: [ARM] pxa: add device definition for graphics controller Signed-off-by: Daniel Mack Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index ecc08f3..46fabe1c 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -935,6 +935,33 @@ void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info) { pxa_register_device(&pxa3xx_device_nand, info); } + +static struct resource pxa3xx_resources_gcu[] = { + { + .start = 0x54000000, + .end = 0x54000fff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_GCU, + .end = IRQ_GCU, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32); + +struct platform_device pxa3xx_device_gcu = { + .name = "pxa3xx-gcu", + .id = -1, + .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu), + .resource = pxa3xx_resources_gcu, + .dev = { + .dma_mask = &pxa3xx_gcu_dmamask, + .coherent_dma_mask = 0xffffffff, + }, +}; + #endif /* CONFIG_PXA3xx */ /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1. diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index ecc24a4..93817d9 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h @@ -35,4 +35,6 @@ extern struct platform_device pxa27x_device_pwm1; extern struct platform_device pxa3xx_device_nand; extern struct platform_device pxa3xx_device_i2c_power; +extern struct platform_device pxa3xx_device_gcu; + void __init pxa_register_device(struct platform_device *dev, void *data); -- cgit v0.10.2 From 17e513ec79f9524f737f367a1efe97489aff9546 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 9 Jul 2009 19:04:50 +0200 Subject: [ARM] pxa: rename GCU IRQ for consistency For consistency reasons, rename IRQ_GRPHICS to IRQ_GCU. Signed-off-by: Daniel Mack Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index abd2c2c..7af0de4 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -71,7 +71,7 @@ #define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */ #define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ #define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ -#define IRQ_GRPHICS PXA_IRQ(39) /* Graphics Controller */ +#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller */ #define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ #define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ #define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ -- cgit v0.10.2 From d7c46ddde3fc51e81b094f4cfdbf9097386d3044 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 4 Sep 2009 17:37:17 +0800 Subject: [ARM] pxa: update dependancy of pxa i2c module PXA I2C module is also used in Marvell PXA168 and PXA910 series. Update the module dependancy of PXA I2C. Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 8206442..834a034 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -460,8 +460,8 @@ config I2C_PNX will be called i2c-pnx. config I2C_PXA - tristate "Intel PXA2XX I2C adapter (EXPERIMENTAL)" - depends on EXPERIMENTAL && ARCH_PXA + tristate "Intel PXA2XX I2C adapter" + depends on ARCH_PXA || ARCH_MMP help If you have devices in the PXA I2C bus, say yes to this option. This driver can also be built as a module. If so, the module -- cgit v0.10.2 From 36714c935a5d4125c6ccd013484de725dc09b387 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 1 Jul 2009 14:17:16 +0800 Subject: [ARM] pxa: merge {zylonite,littleton}_defconfig into pxa3xx_defconfig Merge zylonite_defconfig and littleton_defconfig into pxa3xx_defconfig. Since they're similar platform and servicing for same SoC family. Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao diff --git a/arch/arm/configs/littleton_defconfig b/arch/arm/configs/littleton_defconfig deleted file mode 100644 index 1db4969..0000000 --- a/arch/arm/configs/littleton_defconfig +++ /dev/null @@ -1,783 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.24-rc5 -# Fri Dec 21 11:06:19 2007 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_MMU=y -# CONFIG_NO_IOPORT is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ZONE_DMA=y -CONFIG_ARCH_MTD_XIP=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CGROUPS is not set -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_FAIR_USER_SCHED=y -# CONFIG_FAIR_CGROUP_SCHED is not set -CONFIG_SYSFS_DEPRECATED=y -# CONFIG_RELAY is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -# CONFIG_EMBEDDED is not set -CONFIG_UID16=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_ANON_INODES=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_KMOD is not set -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set -# CONFIG_BLK_DEV_BSG is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" - -# -# System Type -# -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_PNX4008 is not set -CONFIG_ARCH_PXA=y -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_OMAP is not set - -# -# Intel PXA2xx/PXA3xx Implementations -# - -# -# Supported PXA3xx Processor Variants -# -CONFIG_CPU_PXA300=y -CONFIG_CPU_PXA310=y -# CONFIG_CPU_PXA320 is not set -# CONFIG_ARCH_LUBBOCK is not set -# CONFIG_MACH_LOGICPD_PXA270 is not set -# CONFIG_MACH_MAINSTONE is not set -# CONFIG_ARCH_PXA_IDP is not set -# CONFIG_PXA_SHARPSL is not set -# CONFIG_MACH_TRIZEPS4 is not set -# CONFIG_MACH_EM_X270 is not set -# CONFIG_MACH_ZYLONITE is not set -CONFIG_MACH_LITTLETON=y -# CONFIG_MACH_ARMCORE is not set -CONFIG_PXA3xx=y -CONFIG_PXA_SSP=y - -# -# Boot options -# - -# -# Power management -# - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_XSC3=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5T=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_IO_36=y - -# -# Processor Features -# -# CONFIG_ARM_THUMB is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -# CONFIG_OUTER_CACHE is not set -CONFIG_IWMMXT=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_PREEMPT=y -CONFIG_HZ=100 -CONFIG_AEABI=y -CONFIG_OABI_COMPAT=y -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y -CONFIG_VIRT_TO_BUS=y -CONFIG_ALIGNMENT_TRAP=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=64M" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Frequency scaling -# -# CONFIG_CPU_FREQ is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set -# CONFIG_FPE_FASTFPE is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -# CONFIG_PM is not set -CONFIG_SUSPEND_UP_POSSIBLE=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_STANDALONE is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -CONFIG_FW_LOADER=y -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set -# CONFIG_PARPORT is not set -# CONFIG_BLK_DEV is not set -# CONFIG_MISC_DEVICES is not set -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -CONFIG_SMC91X=y -# CONFIG_DM9000 is not set -# CONFIG_SMC911X is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_B44 is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_NVRAM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_WATCHDOG is not set - -# -# Sonics Silicon Backplane -# -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_SM501 is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_SYS_FOPS is not set -CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -CONFIG_FB_PXA=y -# CONFIG_FB_PXA_PARAMETERS is not set -# CONFIG_FB_MBX is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -CONFIG_FONTS=y -# CONFIG_FONT_8x8 is not set -CONFIG_FONT_8x16=y -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_10x18 is not set -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LOGO_LINUX_CLUT224=y - -# -# Sound -# -# CONFIG_SOUND is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_MMC is not set -# CONFIG_NEW_LEDS is not set -CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_INOTIFY is not set -# CONFIG_QUOTA is not set -# CONFIG_DNOTIFY is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_DIRECTIO=y -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_BIND34 is not set -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_NLS is not set -# CONFIG_DLM is not set -# CONFIG_INSTRUMENTATION is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_MAGIC_SYSRQ=y -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -CONFIG_SCHED_DEBUG=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -CONFIG_FRAME_POINTER=y -CONFIG_FORCED_INLINING=y -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_SAMPLES is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -CONFIG_DEBUG_LL=y -# CONFIG_DEBUG_ICEDCC is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_MANAGER=y -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_ECB is not set -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_XTS is not set -# CONFIG_CRYPTO_CRYPTD is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_TEST is not set -# CONFIG_CRYPTO_AUTHENC is not set -CONFIG_CRYPTO_HW=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig new file mode 100644 index 0000000..733b851 --- /dev/null +++ b/arch/arm/configs/pxa3xx_defconfig @@ -0,0 +1,1332 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31-rc1 +# Mon Jul 13 22:48:49 2009 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +# CONFIG_CLASSIC_RCU is not set +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Intel PXA2xx/PXA3xx Implementations +# + +# +# Supported PXA3xx Processor Variants +# +CONFIG_CPU_PXA300=y +CONFIG_CPU_PXA310=y +CONFIG_CPU_PXA320=y +CONFIG_CPU_PXA930=y +CONFIG_CPU_PXA935=y +# CONFIG_ARCH_GUMSTIX is not set +# CONFIG_MACH_INTELMOTE2 is not set +# CONFIG_MACH_STARGATE2 is not set +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_LOGICPD_PXA270 is not set +# CONFIG_MACH_MAINSTONE is not set +# CONFIG_MACH_MP900C is not set +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_PXA_SHARPSL is not set +# CONFIG_ARCH_VIPER is not set +# CONFIG_ARCH_PXA_ESERIES is not set +# CONFIG_TRIZEPS_PXA is not set +# CONFIG_MACH_H5000 is not set +# CONFIG_MACH_EM_X270 is not set +# CONFIG_MACH_EXEDA is not set +# CONFIG_MACH_COLIBRI is not set +# CONFIG_MACH_COLIBRI300 is not set +# CONFIG_MACH_COLIBRI320 is not set +CONFIG_MACH_ZYLONITE=y +CONFIG_MACH_LITTLETON=y +CONFIG_MACH_TAVOREVB=y +CONFIG_MACH_SAAR=y +# CONFIG_MACH_ARMCORE is not set +# CONFIG_MACH_CM_X300 is not set +# CONFIG_MACH_H4700 is not set +# CONFIG_MACH_MAGICIAN is not set +# CONFIG_MACH_HIMALAYA is not set +# CONFIG_MACH_MIOA701 is not set +# CONFIG_MACH_PCM027 is not set +# CONFIG_ARCH_PXA_PALM is not set +# CONFIG_MACH_CSB726 is not set +# CONFIG_PXA_EZX is not set +CONFIG_PXA3xx=y +CONFIG_PXA_SSP=y +CONFIG_PXA_HAVE_BOARD_IRQS=y +CONFIG_PLAT_PXA=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSC3=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_IO_36=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_XSC3L2=y +CONFIG_IWMMXT=y +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=64M debug" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_H1900 is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_SHARPSL is not set +CONFIG_MTD_NAND_PXA3xx=y +CONFIG_MTD_NAND_PXA3xx_BUILTIN=y +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_ONENAND=y +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +CONFIG_MTD_ONENAND_GENERIC=y +# CONFIG_MTD_ONENAND_OTP is not set +# CONFIG_MTD_ONENAND_2X_PROGRAM is not set +# CONFIG_MTD_ONENAND_SIM is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_SMC91X=y +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_LM8323 is not set +CONFIG_KEYBOARD_PXA27x=y +CONFIG_KEYBOARD_PXA930_ROTARY=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +CONFIG_MOUSE_PXA930_TRKBALL=y +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +CONFIG_TOUCHSCREEN_DA9034=y +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_HELPER_AUTO is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_PXA=y +# CONFIG_I2C_PXA_SLAVE is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_PXA2XX=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCF857X=y + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +CONFIG_GPIO_MAX7301=y +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_DEBUG=y +CONFIG_PDA_POWER=y +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_BQ27x00 is not set +CONFIG_BATTERY_DA9030=y +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +CONFIG_PMIC_DA903X=y +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_PXA=y +# CONFIG_FB_PXA_OVERLAY is not set +# CONFIG_FB_PXA_SMARTPANEL is not set +# CONFIG_FB_PXA_PARAMETERS is not set +# CONFIG_FB_MBX is not set +# CONFIG_FB_W100 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI9320 is not set +CONFIG_LCD_TDO24M=y +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_DA903X=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +# CONFIG_FONT_8x16 is not set +CONFIG_FONT_6x11=y +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_PXA=y +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_PCA955X is not set +CONFIG_LEDS_DA903X=m +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_BD2802 is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +CONFIG_REGULATOR_DA903X=y +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_FS_WBUF_VERIFY=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_KMEMCHECK is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/zylonite_defconfig b/arch/arm/configs/zylonite_defconfig deleted file mode 100644 index 7949d04..0000000 --- a/arch/arm/configs/zylonite_defconfig +++ /dev/null @@ -1,736 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.23 -# Tue Oct 23 13:33:20 2007 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_MMU=y -# CONFIG_NO_IOPORT is not set -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ZONE_DMA=y -CONFIG_ARCH_MTD_XIP=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=18 -# CONFIG_CGROUPS is not set -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_FAIR_USER_SCHED=y -# CONFIG_FAIR_CGROUP_SCHED is not set -CONFIG_SYSFS_DEPRECATED=y -# CONFIG_RELAY is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -# CONFIG_EMBEDDED is not set -CONFIG_UID16=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_ANON_INODES=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_KMOD is not set -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set -# CONFIG_BLK_DEV_BSG is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" - -# -# System Type -# -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_PNX4008 is not set -CONFIG_ARCH_PXA=y -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_OMAP is not set - -# -# Intel PXA2xx/PXA3xx Implementations -# - -# -# Supported PXA3xx Processor Variants -# -CONFIG_CPU_PXA300=y -CONFIG_CPU_PXA310=y -CONFIG_CPU_PXA320=y -# CONFIG_ARCH_LUBBOCK is not set -# CONFIG_MACH_LOGICPD_PXA270 is not set -# CONFIG_MACH_MAINSTONE is not set -# CONFIG_ARCH_PXA_IDP is not set -# CONFIG_PXA_SHARPSL is not set -# CONFIG_MACH_TRIZEPS4 is not set -# CONFIG_MACH_EM_X270 is not set -CONFIG_MACH_ZYLONITE=y -# CONFIG_MACH_ARMCORE is not set -CONFIG_PXA3xx=y - -# -# Boot options -# - -# -# Power management -# - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_XSC3=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5T=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_IO_36=y - -# -# Processor Features -# -# CONFIG_ARM_THUMB is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -# CONFIG_OUTER_CACHE is not set -CONFIG_IWMMXT=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -# CONFIG_TICK_ONESHOT is not set -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -# CONFIG_PREEMPT is not set -CONFIG_HZ=100 -CONFIG_AEABI=y -CONFIG_OABI_COMPAT=y -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y -CONFIG_VIRT_TO_BUS=y -CONFIG_ALIGNMENT_TRAP=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfs/rootfs/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS0,38400 mem=64M debug" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set -# CONFIG_FPE_FASTFPE is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -# CONFIG_PM is not set -CONFIG_SUSPEND_UP_POSSIBLE=y - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set -# CONFIG_PARPORT is not set -# CONFIG_BLK_DEV is not set -# CONFIG_MISC_DEVICES is not set -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -CONFIG_SMC91X=y -# CONFIG_DM9000 is not set -# CONFIG_SMC911X is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_B44 is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_NVRAM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set - -# -# Sonics Silicon Backplane -# -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_SM501 is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_SYS_FOPS is not set -CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -CONFIG_FB_PXA=y -# CONFIG_FB_PXA_PARAMETERS is not set -# CONFIG_FB_MBX is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -CONFIG_FONTS=y -# CONFIG_FONT_8x8 is not set -# CONFIG_FONT_8x16 is not set -CONFIG_FONT_6x11=y -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_10x18 is not set -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LOGO_LINUX_CLUT224=y - -# -# Sound -# -# CONFIG_SOUND is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_MMC is not set -# CONFIG_NEW_LEDS is not set -CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_INOTIFY is not set -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_DIRECTIO=y -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_BIND34 is not set -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_NLS is not set -# CONFIG_DLM is not set -# CONFIG_INSTRUMENTATION is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_SLUB_DEBUG_ON is not set -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_FRAME_POINTER=y -# CONFIG_SAMPLES is not set -CONFIG_DEBUG_USER=y - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_MANAGER=y -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_ECB is not set -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_XTS is not set -# CONFIG_CRYPTO_CRYPTD is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_TEST is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_HW is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -- cgit v0.10.2 From 43c6342b1562cc27d8ba1240220cb887ad0e36f0 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sat, 8 Aug 2009 23:07:20 +0200 Subject: [ARM] pxa/dma: cosmetic move of EXPORT_SYMBOL under their functions Signed-off-by: Robert Jarzmik Signed-off-by: Eric Miao diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c index 70aeee4..897663d 100644 --- a/arch/arm/plat-pxa/dma.c +++ b/arch/arm/plat-pxa/dma.c @@ -71,6 +71,7 @@ int pxa_request_dma (char *name, pxa_dma_prio prio, local_irq_restore(flags); return i; } +EXPORT_SYMBOL(pxa_request_dma); void pxa_free_dma (int dma_ch) { @@ -88,6 +89,7 @@ void pxa_free_dma (int dma_ch) dma_channels[dma_ch].name = NULL; local_irq_restore(flags); } +EXPORT_SYMBOL(pxa_free_dma); static irqreturn_t dma_irq_handler(int irq, void *dev_id) { @@ -139,6 +141,3 @@ int __init pxa_init_dma(int irq, int num_ch) num_dma_channels = num_ch; return 0; } - -EXPORT_SYMBOL(pxa_request_dma); -EXPORT_SYMBOL(pxa_free_dma); -- cgit v0.10.2 From d46f5e4a20867da84d12a35407cf7dcc8713c9cc Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sat, 8 Aug 2009 23:07:21 +0200 Subject: [ARM] pxa/dma: optimize irq handler loop Reduce loop for dma irq handler callbacks to the minimum required. Since V1: included suggestion from Nicolas Pitre to improve even further the loop. Signed-off-by: Robert Jarzmik Signed-off-by: Eric Miao diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c index 897663d..56b51cf 100644 --- a/arch/arm/plat-pxa/dma.c +++ b/arch/arm/plat-pxa/dma.c @@ -94,20 +94,21 @@ EXPORT_SYMBOL(pxa_free_dma); static irqreturn_t dma_irq_handler(int irq, void *dev_id) { int i, dint = DINT; - - for (i = 0; i < num_dma_channels; i++) { - if (dint & (1 << i)) { - struct dma_channel *channel = &dma_channels[i]; - if (channel->name && channel->irq_handler) { - channel->irq_handler(i, channel->data); - } else { - /* - * IRQ for an unregistered DMA channel: - * let's clear the interrupts and disable it. - */ - printk (KERN_WARNING "spurious IRQ for DMA channel %d\n", i); - DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; - } + struct dma_channel *channel; + + while (dint) { + i = __ffs(dint); + dint &= (dint - 1); + channel = &dma_channels[i]; + if (channel->name && channel->irq_handler) { + channel->irq_handler(i, channel->data); + } else { + /* + * IRQ for an unregistered DMA channel: + * let's clear the interrupts and disable it. + */ + printk (KERN_WARNING "spurious IRQ for DMA channel %d\n", i); + DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; } } return IRQ_HANDLED; -- cgit v0.10.2 From d294948c2ce4e1c85f452154469752cc9b8e876d Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sat, 8 Aug 2009 23:07:22 +0200 Subject: [ARM] pxa/dma: add debugfs entries Add some debug information for PXA DMA : - descriptors queued - channels state - global state -- Since V1: reverted to old register access (no more dma_readl() or dma_writel()). Signed-off-by: Robert Jarzmik Signed-off-by: Eric Miao diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c index 56b51cf..2975798 100644 --- a/arch/arm/plat-pxa/dma.c +++ b/arch/arm/plat-pxa/dma.c @@ -17,22 +17,266 @@ #include #include #include +#include #include #include +#include #include #include +#define DMA_DEBUG_NAME "pxa_dma" +#define DMA_MAX_REQUESTERS 64 + struct dma_channel { char *name; pxa_dma_prio prio; void (*irq_handler)(int, void *); void *data; + spinlock_t lock; }; static struct dma_channel *dma_channels; static int num_dma_channels; +/* + * Debug fs + */ +#ifdef CONFIG_DEBUG_FS +#include +#include +#include + +static struct dentry *dbgfs_root, *dbgfs_state, **dbgfs_chan; + +static int dbg_show_requester_chan(struct seq_file *s, void *p) +{ + int pos = 0; + int chan = (int)s->private; + int i; + u32 drcmr; + + pos += seq_printf(s, "DMA channel %d requesters list :\n", chan); + for (i = 0; i < DMA_MAX_REQUESTERS; i++) { + drcmr = DRCMR(i); + if ((drcmr & DRCMR_CHLNUM) == chan) + pos += seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i, + !!(drcmr & DRCMR_MAPVLD)); + } + return pos; +} + +static inline int dbg_burst_from_dcmd(u32 dcmd) +{ + int burst = (dcmd >> 16) & 0x3; + + return burst ? 4 << burst : 0; +} + +static int is_phys_valid(unsigned long addr) +{ + return pfn_valid(__phys_to_pfn(addr)); +} + +#define DCSR_STR(flag) (dcsr & DCSR_##flag ? #flag" " : "") +#define DCMD_STR(flag) (dcmd & DCMD_##flag ? #flag" " : "") + +static int dbg_show_descriptors(struct seq_file *s, void *p) +{ + int pos = 0; + int chan = (int)s->private; + int i, max_show = 20, burst, width; + u32 dcmd; + unsigned long phys_desc; + struct pxa_dma_desc *desc; + unsigned long flags; + + spin_lock_irqsave(&dma_channels[chan].lock, flags); + phys_desc = DDADR(chan); + + pos += seq_printf(s, "DMA channel %d descriptors :\n", chan); + pos += seq_printf(s, "[%03d] First descriptor unknown\n", 0); + for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) { + desc = phys_to_virt(phys_desc); + dcmd = desc->dcmd; + burst = dbg_burst_from_dcmd(dcmd); + width = (1 << ((dcmd >> 14) & 0x3)) >> 1; + + pos += seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n", + i, phys_desc, desc); + pos += seq_printf(s, "\tDDADR = %08x\n", desc->ddadr); + pos += seq_printf(s, "\tDSADR = %08x\n", desc->dsadr); + pos += seq_printf(s, "\tDTADR = %08x\n", desc->dtadr); + pos += seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d" + " width=%d len=%d)\n", + dcmd, + DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR), + DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG), + DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN), + DCMD_STR(ENDIAN), burst, width, + dcmd & DCMD_LENGTH); + phys_desc = desc->ddadr; + } + if (i == max_show) + pos += seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n", + i, phys_desc); + else + pos += seq_printf(s, "[%03d] Desc at %08lx is %s\n", + i, phys_desc, phys_desc == DDADR_STOP ? + "DDADR_STOP" : "invalid"); + + spin_unlock_irqrestore(&dma_channels[chan].lock, flags); + return pos; +} + +static int dbg_show_chan_state(struct seq_file *s, void *p) +{ + int pos = 0; + int chan = (int)s->private; + u32 dcsr, dcmd; + int burst, width; + static char *str_prio[] = { "high", "normal", "low" }; + + dcsr = DCSR(chan); + dcmd = DCMD(chan); + burst = dbg_burst_from_dcmd(dcmd); + width = (1 << ((dcmd >> 14) & 0x3)) >> 1; + + pos += seq_printf(s, "DMA channel %d\n", chan); + pos += seq_printf(s, "\tPriority : %s\n", + str_prio[dma_channels[chan].prio]); + pos += seq_printf(s, "\tUnaligned transfer bit: %s\n", + DALGN & (1 << chan) ? "yes" : "no"); + pos += seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", + dcsr, DCSR_STR(RUN), DCSR_STR(NODESC), + DCSR_STR(STOPIRQEN), DCSR_STR(EORIRQEN), + DCSR_STR(EORJMPEN), DCSR_STR(EORSTOPEN), + DCSR_STR(SETCMPST), DCSR_STR(CLRCMPST), + DCSR_STR(CMPST), DCSR_STR(EORINTR), DCSR_STR(REQPEND), + DCSR_STR(STOPSTATE), DCSR_STR(ENDINTR), + DCSR_STR(STARTINTR), DCSR_STR(BUSERR)); + + pos += seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d" + " len=%d)\n", + dcmd, + DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR), + DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG), + DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN), + DCMD_STR(ENDIAN), burst, width, dcmd & DCMD_LENGTH); + pos += seq_printf(s, "\tDSADR = %08x\n", DSADR(chan)); + pos += seq_printf(s, "\tDTADR = %08x\n", DTADR(chan)); + pos += seq_printf(s, "\tDDADR = %08x\n", DDADR(chan)); + return pos; +} + +static int dbg_show_state(struct seq_file *s, void *p) +{ + int pos = 0; + + /* basic device status */ + pos += seq_printf(s, "DMA engine status\n"); + pos += seq_printf(s, "\tChannel number: %d\n", num_dma_channels); + + return pos; +} + +#define DBGFS_FUNC_DECL(name) \ +static int dbg_open_##name(struct inode *inode, struct file *file) \ +{ \ + return single_open(file, dbg_show_##name, inode->i_private); \ +} \ +static const struct file_operations dbg_fops_##name = { \ + .owner = THIS_MODULE, \ + .open = dbg_open_##name, \ + .llseek = seq_lseek, \ + .read = seq_read, \ + .release = single_release, \ +} + +DBGFS_FUNC_DECL(state); +DBGFS_FUNC_DECL(chan_state); +DBGFS_FUNC_DECL(descriptors); +DBGFS_FUNC_DECL(requester_chan); + +static struct dentry *pxa_dma_dbg_alloc_chan(int ch, struct dentry *chandir) +{ + char chan_name[11]; + struct dentry *chan, *chan_state = NULL, *chan_descr = NULL; + struct dentry *chan_reqs = NULL; + void *dt; + + scnprintf(chan_name, sizeof(chan_name), "%d", ch); + chan = debugfs_create_dir(chan_name, chandir); + dt = (void *)ch; + + if (chan) + chan_state = debugfs_create_file("state", 0400, chan, dt, + &dbg_fops_chan_state); + if (chan_state) + chan_descr = debugfs_create_file("descriptors", 0400, chan, dt, + &dbg_fops_descriptors); + if (chan_descr) + chan_reqs = debugfs_create_file("requesters", 0400, chan, dt, + &dbg_fops_requester_chan); + if (!chan_reqs) + goto err_state; + + return chan; + +err_state: + debugfs_remove_recursive(chan); + return NULL; +} + +static void pxa_dma_init_debugfs(void) +{ + int i; + struct dentry *chandir; + + dbgfs_root = debugfs_create_dir(DMA_DEBUG_NAME, NULL); + if (IS_ERR(dbgfs_root) || !dbgfs_root) + goto err_root; + + dbgfs_state = debugfs_create_file("state", 0400, dbgfs_root, NULL, + &dbg_fops_state); + if (!dbgfs_state) + goto err_state; + + dbgfs_chan = kmalloc(sizeof(*dbgfs_state) * num_dma_channels, + GFP_KERNEL); + if (!dbgfs_state) + goto err_alloc; + + chandir = debugfs_create_dir("channels", dbgfs_root); + if (!chandir) + goto err_chandir; + + for (i = 0; i < num_dma_channels; i++) { + dbgfs_chan[i] = pxa_dma_dbg_alloc_chan(i, chandir); + if (!dbgfs_chan[i]) + goto err_chans; + } + + return; +err_chans: +err_chandir: + kfree(dbgfs_chan); +err_alloc: +err_state: + debugfs_remove_recursive(dbgfs_root); +err_root: + pr_err("pxa_dma: debugfs is not available\n"); +} + +static void __exit pxa_dma_cleanup_debugfs(void) +{ + debugfs_remove_recursive(dbgfs_root); +} +#else +static inline void pxa_dma_init_debugfs(void) {} +static inline void pxa_dma_cleanup_debugfs(void) {} +#endif + int pxa_request_dma (char *name, pxa_dma_prio prio, void (*irq_handler)(int, void *), void *data) @@ -130,6 +374,7 @@ int __init pxa_init_dma(int irq, int num_ch) for (i = 0; i < num_ch; i++) { DCSR(i) = 0; dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW); + spin_lock_init(&dma_channels[i].lock); } ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL); @@ -138,7 +383,9 @@ int __init pxa_init_dma(int irq, int num_ch) kfree(dma_channels); return ret; } - num_dma_channels = num_ch; + + pxa_dma_init_debugfs(); + return 0; } -- cgit v0.10.2 From 53eff4175f1eb25f97425b1526774fecb81444d4 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Mon, 22 Jun 2009 21:08:04 +0200 Subject: [ARM] pxafb: use resource_size() function Cleanup only, no function change. Signed-off-by: Daniel Mack Signed-off-by: Eric Miao diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index 6506117..0a30100 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c @@ -2091,14 +2091,14 @@ static int __devinit pxafb_probe(struct platform_device *dev) goto failed_fbi; } - r = request_mem_region(r->start, r->end - r->start + 1, dev->name); + r = request_mem_region(r->start, resource_size(r), dev->name); if (r == NULL) { dev_err(&dev->dev, "failed to request I/O memory\n"); ret = -EBUSY; goto failed_fbi; } - fbi->mmio_base = ioremap(r->start, r->end - r->start + 1); + fbi->mmio_base = ioremap(r->start, resource_size(r)); if (fbi->mmio_base == NULL) { dev_err(&dev->dev, "failed to map I/O memory\n"); ret = -EBUSY; @@ -2197,7 +2197,7 @@ failed_free_dma: failed_free_io: iounmap(fbi->mmio_base); failed_free_res: - release_mem_region(r->start, r->end - r->start + 1); + release_mem_region(r->start, resource_size(r)); failed_fbi: clk_put(fbi->clk); platform_set_drvdata(dev, NULL); @@ -2237,7 +2237,7 @@ static int __devexit pxafb_remove(struct platform_device *dev) iounmap(fbi->mmio_base); r = platform_get_resource(dev, IORESOURCE_MEM, 0); - release_mem_region(r->start, r->end - r->start + 1); + release_mem_region(r->start, resource_size(r)); clk_put(fbi->clk); kfree(fbi); -- cgit v0.10.2 From b405db6c015fe8e4c9d8199a0355bb16d95d7049 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 23 Jun 2009 23:21:03 +0200 Subject: [ARM] pxamci: add simple gpio controls The MMC block needs 3 external datas to work : - is the MMC card put in "read-only mode" ? - is a MMC card inserted or removed ? - enable power towards the MMC card Several platforms provide these controls through gpios. Expand the platform_data to request and use these gpios is set up by board code. Signed-off-by: Robert Jarzmik Acked-by: Pierre.Ossman Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/include/mach/mmc.h b/arch/arm/mach-pxa/include/mach/mmc.h index 6d1304c..02a69dc 100644 --- a/arch/arm/mach-pxa/include/mach/mmc.h +++ b/arch/arm/mach-pxa/include/mach/mmc.h @@ -14,6 +14,11 @@ struct pxamci_platform_data { int (*get_ro)(struct device *); void (*setpower)(struct device *, unsigned int); void (*exit)(struct device *, void *); + int gpio_card_detect; /* gpio detecting card insertion */ + int gpio_card_ro; /* gpio detecting read only toggle */ + bool gpio_card_ro_invert; /* gpio ro is inverted */ + int gpio_power; /* gpio powering up MMC bus */ + bool gpio_power_invert; /* gpio power is inverted */ }; extern void pxa_set_mci_info(struct pxamci_platform_data *info); diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c index e55ac79..972efa8 100644 --- a/drivers/mmc/host/pxamci.c +++ b/drivers/mmc/host/pxamci.c @@ -28,6 +28,7 @@ #include #include #include +#include #include @@ -96,10 +97,18 @@ static inline void pxamci_init_ocr(struct pxamci_host *host) static inline void pxamci_set_power(struct pxamci_host *host, unsigned int vdd) { + int on; + #ifdef CONFIG_REGULATOR if (host->vcc) mmc_regulator_set_ocr(host->vcc, vdd); #endif + if (!host->vcc && host->pdata && + gpio_is_valid(host->pdata->gpio_power)) { + on = ((1 << vdd) & host->pdata->ocr_mask); + gpio_set_value(host->pdata->gpio_power, + !!on ^ host->pdata->gpio_power_invert); + } if (!host->vcc && host->pdata && host->pdata->setpower) host->pdata->setpower(mmc_dev(host->mmc), vdd); } @@ -421,6 +430,12 @@ static int pxamci_get_ro(struct mmc_host *mmc) { struct pxamci_host *host = mmc_priv(mmc); + if (host->pdata && gpio_is_valid(host->pdata->gpio_card_ro)) { + if (host->pdata->gpio_card_ro_invert) + return !gpio_get_value(host->pdata->gpio_card_ro); + else + return gpio_get_value(host->pdata->gpio_card_ro); + } if (host->pdata && host->pdata->get_ro) return !!host->pdata->get_ro(mmc_dev(mmc)); /* @@ -534,7 +549,7 @@ static int pxamci_probe(struct platform_device *pdev) struct mmc_host *mmc; struct pxamci_host *host = NULL; struct resource *r, *dmarx, *dmatx; - int ret, irq; + int ret, irq, gpio_cd = -1, gpio_ro = -1, gpio_power = -1; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); @@ -661,13 +676,63 @@ static int pxamci_probe(struct platform_device *pdev) } host->dma_drcmrtx = dmatx->start; + if (host->pdata) { + gpio_cd = host->pdata->gpio_card_detect; + gpio_ro = host->pdata->gpio_card_ro; + gpio_power = host->pdata->gpio_power; + } + if (gpio_is_valid(gpio_power)) { + ret = gpio_request(gpio_power, "mmc card power"); + if (ret) { + dev_err(&pdev->dev, "Failed requesting gpio_power %d\n", gpio_power); + goto out; + } + gpio_direction_output(gpio_power, + host->pdata->gpio_power_invert); + } + if (gpio_is_valid(gpio_ro)) { + ret = gpio_request(gpio_ro, "mmc card read only"); + if (ret) { + dev_err(&pdev->dev, "Failed requesting gpio_ro %d\n", gpio_power); + goto err_gpio_ro; + } + gpio_direction_input(gpio_ro); + } + if (gpio_is_valid(gpio_cd)) { + ret = gpio_request(gpio_cd, "mmc card detect"); + if (ret) { + dev_err(&pdev->dev, "Failed requesting gpio_cd %d\n", gpio_power); + goto err_gpio_cd; + } + gpio_direction_input(gpio_cd); + + ret = request_irq(gpio_to_irq(gpio_cd), pxamci_detect_irq, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "mmc card detect", mmc); + if (ret) { + dev_err(&pdev->dev, "failed to request card detect IRQ\n"); + goto err_request_irq; + } + } + if (host->pdata && host->pdata->init) host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc); + if (gpio_is_valid(gpio_power) && host->pdata->setpower) + dev_warn(&pdev->dev, "gpio_power and setpower() both defined\n"); + if (gpio_is_valid(gpio_ro) && host->pdata->get_ro) + dev_warn(&pdev->dev, "gpio_ro and get_ro() both defined\n"); + mmc_add_host(mmc); return 0; +err_request_irq: + gpio_free(gpio_cd); +err_gpio_cd: + gpio_free(gpio_ro); +err_gpio_ro: + gpio_free(gpio_power); out: if (host) { if (host->dma >= 0) @@ -688,12 +753,26 @@ static int pxamci_probe(struct platform_device *pdev) static int pxamci_remove(struct platform_device *pdev) { struct mmc_host *mmc = platform_get_drvdata(pdev); + int gpio_cd = -1, gpio_ro = -1, gpio_power = -1; platform_set_drvdata(pdev, NULL); if (mmc) { struct pxamci_host *host = mmc_priv(mmc); + if (host->pdata) { + gpio_cd = host->pdata->gpio_card_detect; + gpio_ro = host->pdata->gpio_card_ro; + gpio_power = host->pdata->gpio_power; + } + if (gpio_is_valid(gpio_cd)) { + free_irq(gpio_to_irq(gpio_cd), mmc); + gpio_free(gpio_cd); + } + if (gpio_is_valid(gpio_ro)) + gpio_free(gpio_ro); + if (gpio_is_valid(gpio_power)) + gpio_free(gpio_power); if (host->vcc) regulator_put(host->vcc); -- cgit v0.10.2 From 7a648256b20c493c99757fe1d248daf7954647bc Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Mon, 6 Jul 2009 22:16:42 +0200 Subject: [ARM] pxa: factor pxamci gpio handling Several boards use always the same pattern with pxamci : request gpio, request irq for that gpio to detect MMC card insertion, request gpio for read-only mode detection, etc ... Now that pxamci provides platform_data to describe simple gpio management of the MMC external controls, use it. Signed-off-by: Robert Jarzmik Acked-by: Mike Rapoport Acked-by: Philipp Zabel Acked-by: Dmitry Eremin-Solenikov Cc: rpurdie@rpsys.net Cc: drwyrm@gmail.com Cc: sakoman@gmail.com Cc: marek.vasut@gmail.com Cc: s.hauer@pengutronix.de Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index 1d2cec2..5929218 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c @@ -271,56 +271,12 @@ static inline void cmx270_init_ohci(void) {} #endif #if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE) -static int cmx270_mci_init(struct device *dev, - irq_handler_t cmx270_detect_int, - void *data) -{ - int err; - - err = gpio_request(GPIO105_MMC_POWER, "MMC/SD power"); - if (err) { - dev_warn(dev, "power gpio unavailable\n"); - return err; - } - - gpio_direction_output(GPIO105_MMC_POWER, 0); - - err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "MMC card detect", data); - if (err) { - gpio_free(GPIO105_MMC_POWER); - dev_err(dev, "cmx270_mci_init: MMC/SD: can't" - " request MMC card detect IRQ\n"); - } - - return err; -} - -static void cmx270_mci_setpower(struct device *dev, unsigned int vdd) -{ - struct pxamci_platform_data *p_d = dev->platform_data; - - if ((1 << vdd) & p_d->ocr_mask) { - dev_dbg(dev, "power on\n"); - gpio_set_value(GPIO105_MMC_POWER, 0); - } else { - gpio_set_value(GPIO105_MMC_POWER, 1); - dev_dbg(dev, "power off\n"); - } -} - -static void cmx270_mci_exit(struct device *dev, void *data) -{ - free_irq(CMX270_MMC_IRQ, data); - gpio_free(GPIO105_MMC_POWER); -} - static struct pxamci_platform_data cmx270_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .init = cmx270_mci_init, - .setpower = cmx270_mci_setpower, - .exit = cmx270_mci_exit, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .gpio_card_detect = GPIO83_MMC_IRQ, + .gpio_card_ro = -1, + .gpio_power = GPIO105_MMC_POWER, + .gpio_power_invert = 1, }; static void __init cmx270_init_mmc(void) diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 465da26..aac2cda 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -306,68 +306,21 @@ static void cm_x300_mci_exit(struct device *dev, void *data) } static struct pxamci_platform_data cm_x300_mci_platform_data = { - .detect_delay = 20, - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .init = cm_x300_mci_init, - .exit = cm_x300_mci_exit, + .detect_delay = 20, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .init = cm_x300_mci_init, + .exit = cm_x300_mci_exit, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, }; -static int cm_x300_mci2_ro(struct device *dev) -{ - return gpio_get_value(GPIO85_MMC2_WP); -} - -static int cm_x300_mci2_init(struct device *dev, - irq_handler_t cm_x300_detect_int, - void *data) -{ - int err; - - /* - * setup GPIO for CM-X300 MMC controller - */ - err = gpio_request(GPIO82_MMC2_IRQ, "mmc card detect"); - if (err) - goto err_request_cd; - gpio_direction_input(GPIO82_MMC2_IRQ); - - err = gpio_request(GPIO85_MMC2_WP, "mmc write protect"); - if (err) - goto err_request_wp; - gpio_direction_input(GPIO85_MMC2_WP); - - err = request_irq(CM_X300_MMC2_IRQ, cm_x300_detect_int, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "MMC card detect", data); - if (err) { - printk(KERN_ERR "%s: MMC/SD/SDIO: " - "can't request card detect IRQ\n", __func__); - goto err_request_irq; - } - - return 0; - -err_request_irq: - gpio_free(GPIO85_MMC2_WP); -err_request_wp: - gpio_free(GPIO82_MMC2_IRQ); -err_request_cd: - return err; -} - -static void cm_x300_mci2_exit(struct device *dev, void *data) -{ - free_irq(CM_X300_MMC2_IRQ, data); - gpio_free(GPIO82_MMC2_IRQ); - gpio_free(GPIO85_MMC2_WP); -} - static struct pxamci_platform_data cm_x300_mci2_platform_data = { - .detect_delay = 20, - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .init = cm_x300_mci2_init, - .exit = cm_x300_mci2_exit, - .get_ro = cm_x300_mci2_ro, + .detect_delay = 20, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .gpio_card_detect = GPIO82_MMC2_IRQ, + .gpio_card_ro = GPIO85_MMC2_WP, + .gpio_power = -1, }; static void __init cm_x300_init_mmc(void) diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index ea34e34..2c846bb 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c @@ -95,10 +95,13 @@ static void colibri_pxa3xx_mci_exit(struct device *dev, void *data) } static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = { - .detect_delay = 20, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .init = colibri_pxa3xx_mci_init, - .exit = colibri_pxa3xx_mci_exit, + .detect_delay = 20, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .init = colibri_pxa3xx_mci_init, + .exit = colibri_pxa3xx_mci_exit, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, }; void __init colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin) diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 5363e1a..39a9458 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -307,77 +307,11 @@ static struct platform_device corgiled_device = { * The card detect interrupt isn't debounced so we delay it by 250ms * to give the card a chance to fully insert/eject. */ -static struct pxamci_platform_data corgi_mci_platform_data; - -static int corgi_mci_init(struct device *dev, irq_handler_t corgi_detect_int, void *data) -{ - int err; - - err = gpio_request(CORGI_GPIO_nSD_DETECT, "nSD_DETECT"); - if (err) - goto err_out; - - err = gpio_request(CORGI_GPIO_nSD_WP, "nSD_WP"); - if (err) - goto err_free_1; - - err = gpio_request(CORGI_GPIO_SD_PWR, "SD_PWR"); - if (err) - goto err_free_2; - - gpio_direction_input(CORGI_GPIO_nSD_DETECT); - gpio_direction_input(CORGI_GPIO_nSD_WP); - gpio_direction_output(CORGI_GPIO_SD_PWR, 0); - - corgi_mci_platform_data.detect_delay = msecs_to_jiffies(250); - - err = request_irq(CORGI_IRQ_GPIO_nSD_DETECT, corgi_detect_int, - IRQF_DISABLED | IRQF_TRIGGER_RISING | - IRQF_TRIGGER_FALLING, - "MMC card detect", data); - if (err) { - pr_err("%s: MMC/SD: can't request MMC card detect IRQ\n", - __func__); - goto err_free_3; - } - return 0; - -err_free_3: - gpio_free(CORGI_GPIO_SD_PWR); -err_free_2: - gpio_free(CORGI_GPIO_nSD_WP); -err_free_1: - gpio_free(CORGI_GPIO_nSD_DETECT); -err_out: - return err; -} - -static void corgi_mci_setpower(struct device *dev, unsigned int vdd) -{ - struct pxamci_platform_data* p_d = dev->platform_data; - - gpio_set_value(CORGI_GPIO_SD_PWR, ((1 << vdd) & p_d->ocr_mask)); -} - -static int corgi_mci_get_ro(struct device *dev) -{ - return gpio_get_value(CORGI_GPIO_nSD_WP); -} - -static void corgi_mci_exit(struct device *dev, void *data) -{ - free_irq(CORGI_IRQ_GPIO_nSD_DETECT, data); - gpio_free(CORGI_GPIO_SD_PWR); - gpio_free(CORGI_GPIO_nSD_WP); - gpio_free(CORGI_GPIO_nSD_DETECT); -} - static struct pxamci_platform_data corgi_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .init = corgi_mci_init, - .get_ro = corgi_mci_get_ro, - .setpower = corgi_mci_setpower, - .exit = corgi_mci_exit, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .gpio_card_detect = -1, + .gpio_card_ro = CORGI_GPIO_nSD_WP, + .gpio_power = CORGI_GPIO_SD_PWR, }; @@ -636,6 +570,7 @@ static void __init corgi_init(void) corgi_init_spi(); pxa_set_udc_info(&udc_info); + corgi_mci_platform_data.detect_delay = msecs_to_jiffies(250); pxa_set_mci_info(&corgi_mci_platform_data); pxa_set_ficp_info(&corgi_ficp_platform_data); pxa_set_i2c_info(NULL); diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index 7d3e1b4..79141f8 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c @@ -130,61 +130,17 @@ static struct pxamci_platform_data csb726_mci_data; static int csb726_mci_init(struct device *dev, irq_handler_t detect, void *data) { - int err; - csb726_mci_data.detect_delay = msecs_to_jiffies(500); - - err = gpio_request(CSB726_GPIO_MMC_DETECT, "MMC detect"); - if (err) - goto err_det_req; - - err = gpio_direction_input(CSB726_GPIO_MMC_DETECT); - if (err) - goto err_det_dir; - - err = gpio_request(CSB726_GPIO_MMC_RO, "MMC ro"); - if (err) - goto err_ro_req; - - err = gpio_direction_input(CSB726_GPIO_MMC_RO); - if (err) - goto err_ro_dir; - - err = request_irq(gpio_to_irq(CSB726_GPIO_MMC_DETECT), detect, - IRQF_DISABLED, "MMC card detect", data); - if (err) - goto err_irq; - return 0; - -err_irq: -err_ro_dir: - gpio_free(CSB726_GPIO_MMC_RO); -err_ro_req: -err_det_dir: - gpio_free(CSB726_GPIO_MMC_DETECT); -err_det_req: - return err; -} - -static int csb726_mci_get_ro(struct device *dev) -{ - return gpio_get_value(CSB726_GPIO_MMC_RO); -} - -static void csb726_mci_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(CSB726_GPIO_MMC_DETECT), data); - gpio_free(CSB726_GPIO_MMC_RO); - gpio_free(CSB726_GPIO_MMC_DETECT); } static struct pxamci_platform_data csb726_mci = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .init = csb726_mci_init, - .get_ro = csb726_mci_get_ro, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .init = csb726_mci_init, /* FIXME setpower */ - .exit = csb726_mci_exit, + .gpio_card_detect = CSB726_GPIO_MMC_DETECT, + .gpio_card_ro = CSB726_GPIO_MMC_RO, + .gpio_power = -1, }; static struct pxaohci_platform_data csb726_ohci_platform_data = { diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 9cd0946..e0121f4 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -646,13 +646,16 @@ static int em_x270_mci_get_ro(struct device *dev) } static struct pxamci_platform_data em_x270_mci_platform_data = { - .ocr_mask = MMC_VDD_20_21|MMC_VDD_21_22|MMC_VDD_22_23| - MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27| - MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30| - MMC_VDD_30_31|MMC_VDD_31_32, - .init = em_x270_mci_init, - .setpower = em_x270_mci_setpower, - .exit = em_x270_mci_exit, + .ocr_mask = MMC_VDD_20_21|MMC_VDD_21_22|MMC_VDD_22_23| + MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27| + MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30| + MMC_VDD_30_31|MMC_VDD_31_32, + .init = em_x270_mci_init, + .setpower = em_x270_mci_setpower, + .exit = em_x270_mci_exit, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, }; static void __init em_x270_init_mmc(void) diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index ca9912e..1708c01 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c @@ -88,7 +88,10 @@ static struct platform_device *devices[] __initdata = { #ifdef CONFIG_MMC_PXA static struct pxamci_platform_data gumstix_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, }; static void __init gumstix_mmc_init(void) diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index b6243b5..b6486ef 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -168,7 +168,10 @@ static struct pxafb_mach_info sharp_lm8v31 = { }; static struct pxamci_platform_data idp_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, }; static void __init idp_init(void) diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c index 961807d..2a4945d 100644 --- a/arch/arm/mach-pxa/imote2.c +++ b/arch/arm/mach-pxa/imote2.c @@ -389,6 +389,9 @@ static int imote2_mci_get_ro(struct device *dev) static struct pxamci_platform_data imote2_mci_platform_data = { .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* default anyway */ .get_ro = imote2_mci_get_ro, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, }; static struct mtd_partition imote2flash_partitions[] = { diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index f04c833..1785cc9 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -482,11 +482,14 @@ static void lubbock_mci_exit(struct device *dev, void *data) } static struct pxamci_platform_data lubbock_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .detect_delay = 1, - .init = lubbock_mci_init, - .get_ro = lubbock_mci_get_ro, - .exit = lubbock_mci_exit, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .detect_delay = 1, + .init = lubbock_mci_init, + .get_ro = lubbock_mci_get_ro, + .exit = lubbock_mci_exit, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, }; static void lubbock_irda_transceiver_mode(struct device *dev, int mode) diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index ca39669..0daba43 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -651,55 +651,24 @@ static struct platform_device bq24022 = { static int magician_mci_init(struct device *dev, irq_handler_t detect_irq, void *data) { - int err; - - err = request_irq(IRQ_MAGICIAN_SD, detect_irq, + return request_irq(IRQ_MAGICIAN_SD, detect_irq, IRQF_DISABLED | IRQF_SAMPLE_RANDOM, - "MMC card detect", data); - if (err) - goto err_request_irq; - err = gpio_request(EGPIO_MAGICIAN_SD_POWER, "SD_POWER"); - if (err) - goto err_request_power; - err = gpio_request(EGPIO_MAGICIAN_nSD_READONLY, "nSD_READONLY"); - if (err) - goto err_request_readonly; - - return 0; - -err_request_readonly: - gpio_free(EGPIO_MAGICIAN_SD_POWER); -err_request_power: - free_irq(IRQ_MAGICIAN_SD, data); -err_request_irq: - return err; -} - -static void magician_mci_setpower(struct device *dev, unsigned int vdd) -{ - struct pxamci_platform_data *pdata = dev->platform_data; - - gpio_set_value(EGPIO_MAGICIAN_SD_POWER, (1 << vdd) & pdata->ocr_mask); -} - -static int magician_mci_get_ro(struct device *dev) -{ - return (!gpio_get_value(EGPIO_MAGICIAN_nSD_READONLY)); + "mmc card detect", data); } static void magician_mci_exit(struct device *dev, void *data) { - gpio_free(EGPIO_MAGICIAN_nSD_READONLY); - gpio_free(EGPIO_MAGICIAN_SD_POWER); free_irq(IRQ_MAGICIAN_SD, data); } static struct pxamci_platform_data magician_mci_info = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .init = magician_mci_init, - .get_ro = magician_mci_get_ro, - .setpower = magician_mci_setpower, - .exit = magician_mci_exit, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .init = magician_mci_init, + .exit = magician_mci_exit, + .gpio_card_detect = -1, + .gpio_card_ro = EGPIO_MAGICIAN_nSD_READONLY, + .gpio_card_ro_invert = 1, + .gpio_power = EGPIO_MAGICIAN_SD_POWER, }; diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index f4dabf0..f7dc230 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -450,10 +450,13 @@ static void mainstone_mci_exit(struct device *dev, void *data) } static struct pxamci_platform_data mainstone_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .init = mainstone_mci_init, - .setpower = mainstone_mci_setpower, - .exit = mainstone_mci_exit, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .init = mainstone_mci_init, + .setpower = mainstone_mci_setpower, + .exit = mainstone_mci_exit, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, }; static void mainstone_irda_transceiver_mode(struct device *dev, int mode) diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 2d28132..a8122ec 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -434,72 +434,15 @@ struct gpio_vbus_mach_info gpio_vbus_data = { /* * SDIO/MMC Card controller */ -static void mci_setpower(struct device *dev, unsigned int vdd) -{ - struct pxamci_platform_data *p_d = dev->platform_data; - - if ((1 << vdd) & p_d->ocr_mask) - gpio_set_value(GPIO91_SDIO_EN, 1); /* enable SDIO power */ - else - gpio_set_value(GPIO91_SDIO_EN, 0); /* disable SDIO power */ -} - -static int mci_get_ro(struct device *dev) -{ - return gpio_get_value(GPIO78_SDIO_RO); -} - -struct gpio_ress mci_gpios[] = { - MIO_GPIO_IN(GPIO78_SDIO_RO, "SDIO readonly detect"), - MIO_GPIO_IN(GPIO15_SDIO_INSERT, "SDIO insertion detect"), - MIO_GPIO_OUT(GPIO91_SDIO_EN, 0, "SDIO power enable") -}; - -static void mci_exit(struct device *dev, void *data) -{ - mio_gpio_free(ARRAY_AND_SIZE(mci_gpios)); - free_irq(gpio_to_irq(GPIO15_SDIO_INSERT), data); -} - -static struct pxamci_platform_data mioa701_mci_info; - /** * The card detect interrupt isn't debounced so we delay it by 250ms * to give the card a chance to fully insert/eject. */ -static int mci_init(struct device *dev, irq_handler_t detect_int, void *data) -{ - int rc; - int irq = gpio_to_irq(GPIO15_SDIO_INSERT); - - rc = mio_gpio_request(ARRAY_AND_SIZE(mci_gpios)); - if (rc) - goto err_gpio; - /* enable RE/FE interrupt on card insertion and removal */ - rc = request_irq(irq, detect_int, - IRQF_DISABLED | IRQF_TRIGGER_RISING | - IRQF_TRIGGER_FALLING, - "MMC card detect", data); - if (rc) - goto err_irq; - - mioa701_mci_info.detect_delay = msecs_to_jiffies(250); - return 0; - -err_irq: - dev_err(dev, "mioa701_mci_init: MMC/SD:" - " can't request MMC card detect IRQ\n"); - mio_gpio_free(ARRAY_AND_SIZE(mci_gpios)); -err_gpio: - return rc; -} - static struct pxamci_platform_data mioa701_mci_info = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .init = mci_init, - .get_ro = mci_get_ro, - .setpower = mci_setpower, - .exit = mci_exit, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_card_detect = GPIO15_SDIO_INSERT, + .gpio_card_ro = GPIO78_SDIO_RO, + .gpio_power = GPIO91_SDIO_EN, }; /* FlashRAM */ @@ -841,7 +784,7 @@ static void mioa701_restart(char c, const char *cmd) static struct gpio_ress global_gpios[] = { MIO_GPIO_OUT(GPIO9_CHARGE_EN, 1, "Charger enable"), MIO_GPIO_OUT(GPIO18_POWEROFF, 0, "Power Off"), - MIO_GPIO_OUT(GPIO87_LCD_POWER, 0, "LCD Power") + MIO_GPIO_OUT(GPIO87_LCD_POWER, 0, "LCD Power"), }; static void __init mioa701_machine_init(void) @@ -855,6 +798,7 @@ static void __init mioa701_machine_init(void) mio_gpio_request(ARRAY_AND_SIZE(global_gpios)); bootstrap_init(); set_pxa_fb_info(&mioa701_pxafb_info); + mioa701_mci_info.detect_delay = msecs_to_jiffies(250); pxa_set_mci_info(&mioa701_mci_info); pxa_set_keypad_info(&mioa701_keypad_info); wm97xx_bat_set_pdata(&mioa701_battery_data); diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index 169fcc1..4457491 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -143,83 +143,11 @@ static unsigned long palmld_pin_config[] __initdata = { /****************************************************************************** * SD/MMC card controller ******************************************************************************/ -static int palmld_mci_init(struct device *dev, irq_handler_t palmld_detect_int, - void *data) -{ - int err = 0; - - /* Setup an interrupt for detecting card insert/remove events */ - err = gpio_request(GPIO_NR_PALMLD_SD_DETECT_N, "SD IRQ"); - if (err) - goto err; - err = gpio_direction_input(GPIO_NR_PALMLD_SD_DETECT_N); - if (err) - goto err2; - err = request_irq(gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N), - palmld_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, - "SD/MMC card detect", data); - if (err) { - printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n", - __func__); - goto err2; - } - - err = gpio_request(GPIO_NR_PALMLD_SD_POWER, "SD_POWER"); - if (err) - goto err3; - err = gpio_direction_output(GPIO_NR_PALMLD_SD_POWER, 0); - if (err) - goto err4; - - err = gpio_request(GPIO_NR_PALMLD_SD_READONLY, "SD_READONLY"); - if (err) - goto err4; - err = gpio_direction_input(GPIO_NR_PALMLD_SD_READONLY); - if (err) - goto err5; - - printk(KERN_DEBUG "%s: irq registered\n", __func__); - - return 0; - -err5: - gpio_free(GPIO_NR_PALMLD_SD_READONLY); -err4: - gpio_free(GPIO_NR_PALMLD_SD_POWER); -err3: - free_irq(gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N), data); -err2: - gpio_free(GPIO_NR_PALMLD_SD_DETECT_N); -err: - return err; -} - -static void palmld_mci_exit(struct device *dev, void *data) -{ - gpio_free(GPIO_NR_PALMLD_SD_READONLY); - gpio_free(GPIO_NR_PALMLD_SD_POWER); - free_irq(gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N), data); - gpio_free(GPIO_NR_PALMLD_SD_DETECT_N); -} - -static void palmld_mci_power(struct device *dev, unsigned int vdd) -{ - struct pxamci_platform_data *p_d = dev->platform_data; - gpio_set_value(GPIO_NR_PALMLD_SD_POWER, p_d->ocr_mask & (1 << vdd)); -} - -static int palmld_mci_get_ro(struct device *dev) -{ - return gpio_get_value(GPIO_NR_PALMLD_SD_READONLY); -} - static struct pxamci_platform_data palmld_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .setpower = palmld_mci_power, - .get_ro = palmld_mci_get_ro, - .init = palmld_mci_init, - .exit = palmld_mci_exit, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_card_detect = GPIO_NR_PALMLD_SD_DETECT_N, + .gpio_card_ro = GPIO_NR_PALMLD_SD_READONLY, + .gpio_power = GPIO_NR_PALMLD_SD_POWER, }; /****************************************************************************** diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 33f726f..42d0528 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c @@ -124,83 +124,11 @@ static unsigned long palmt5_pin_config[] __initdata = { /****************************************************************************** * SD/MMC card controller ******************************************************************************/ -static int palmt5_mci_init(struct device *dev, irq_handler_t palmt5_detect_int, - void *data) -{ - int err = 0; - - /* Setup an interrupt for detecting card insert/remove events */ - err = gpio_request(GPIO_NR_PALMT5_SD_DETECT_N, "SD IRQ"); - if (err) - goto err; - err = gpio_direction_input(GPIO_NR_PALMT5_SD_DETECT_N); - if (err) - goto err2; - err = request_irq(gpio_to_irq(GPIO_NR_PALMT5_SD_DETECT_N), - palmt5_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, - "SD/MMC card detect", data); - if (err) { - printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n", - __func__); - goto err2; - } - - err = gpio_request(GPIO_NR_PALMT5_SD_POWER, "SD_POWER"); - if (err) - goto err3; - err = gpio_direction_output(GPIO_NR_PALMT5_SD_POWER, 0); - if (err) - goto err4; - - err = gpio_request(GPIO_NR_PALMT5_SD_READONLY, "SD_READONLY"); - if (err) - goto err4; - err = gpio_direction_input(GPIO_NR_PALMT5_SD_READONLY); - if (err) - goto err5; - - printk(KERN_DEBUG "%s: irq registered\n", __func__); - - return 0; - -err5: - gpio_free(GPIO_NR_PALMT5_SD_READONLY); -err4: - gpio_free(GPIO_NR_PALMT5_SD_POWER); -err3: - free_irq(gpio_to_irq(GPIO_NR_PALMT5_SD_DETECT_N), data); -err2: - gpio_free(GPIO_NR_PALMT5_SD_DETECT_N); -err: - return err; -} - -static void palmt5_mci_exit(struct device *dev, void *data) -{ - gpio_free(GPIO_NR_PALMT5_SD_READONLY); - gpio_free(GPIO_NR_PALMT5_SD_POWER); - free_irq(IRQ_GPIO_PALMT5_SD_DETECT_N, data); - gpio_free(GPIO_NR_PALMT5_SD_DETECT_N); -} - -static void palmt5_mci_power(struct device *dev, unsigned int vdd) -{ - struct pxamci_platform_data *p_d = dev->platform_data; - gpio_set_value(GPIO_NR_PALMT5_SD_POWER, p_d->ocr_mask & (1 << vdd)); -} - -static int palmt5_mci_get_ro(struct device *dev) -{ - return gpio_get_value(GPIO_NR_PALMT5_SD_READONLY); -} - static struct pxamci_platform_data palmt5_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .setpower = palmt5_mci_power, - .get_ro = palmt5_mci_get_ro, - .init = palmt5_mci_init, - .exit = palmt5_mci_exit, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_card_detect = GPIO_NR_PALMT5_SD_DETECT_N, + .gpio_card_ro = GPIO_NR_PALMT5_SD_READONLY, + .gpio_power = GPIO_NR_PALMT5_SD_POWER, }; /****************************************************************************** diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index d823b09..d9ef76c 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -117,83 +117,11 @@ static unsigned long palmte2_pin_config[] __initdata = { /****************************************************************************** * SD/MMC card controller ******************************************************************************/ -static int palmte2_mci_init(struct device *dev, - irq_handler_t palmte2_detect_int, void *data) -{ - int err = 0; - - /* Setup an interrupt for detecting card insert/remove events */ - err = gpio_request(GPIO_NR_PALMTE2_SD_DETECT_N, "SD IRQ"); - if (err) - goto err; - err = gpio_direction_input(GPIO_NR_PALMTE2_SD_DETECT_N); - if (err) - goto err2; - err = request_irq(gpio_to_irq(GPIO_NR_PALMTE2_SD_DETECT_N), - palmte2_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, - "SD/MMC card detect", data); - if (err) { - printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n", - __func__); - goto err2; - } - - err = gpio_request(GPIO_NR_PALMTE2_SD_POWER, "SD_POWER"); - if (err) - goto err3; - err = gpio_direction_output(GPIO_NR_PALMTE2_SD_POWER, 0); - if (err) - goto err4; - - err = gpio_request(GPIO_NR_PALMTE2_SD_READONLY, "SD_READONLY"); - if (err) - goto err4; - err = gpio_direction_input(GPIO_NR_PALMTE2_SD_READONLY); - if (err) - goto err5; - - printk(KERN_DEBUG "%s: irq registered\n", __func__); - - return 0; - -err5: - gpio_free(GPIO_NR_PALMTE2_SD_READONLY); -err4: - gpio_free(GPIO_NR_PALMTE2_SD_POWER); -err3: - free_irq(gpio_to_irq(GPIO_NR_PALMTE2_SD_DETECT_N), data); -err2: - gpio_free(GPIO_NR_PALMTE2_SD_DETECT_N); -err: - return err; -} - -static void palmte2_mci_exit(struct device *dev, void *data) -{ - gpio_free(GPIO_NR_PALMTE2_SD_READONLY); - gpio_free(GPIO_NR_PALMTE2_SD_POWER); - free_irq(gpio_to_irq(GPIO_NR_PALMTE2_SD_DETECT_N), data); - gpio_free(GPIO_NR_PALMTE2_SD_DETECT_N); -} - -static void palmte2_mci_power(struct device *dev, unsigned int vdd) -{ - struct pxamci_platform_data *p_d = dev->platform_data; - gpio_set_value(GPIO_NR_PALMTE2_SD_POWER, p_d->ocr_mask & (1 << vdd)); -} - -static int palmte2_mci_get_ro(struct device *dev) -{ - return gpio_get_value(GPIO_NR_PALMTE2_SD_READONLY); -} - static struct pxamci_platform_data palmte2_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .setpower = palmte2_mci_power, - .get_ro = palmte2_mci_get_ro, - .init = palmte2_mci_init, - .exit = palmte2_mci_exit, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_card_detect = GPIO_NR_PALMTE2_SD_DETECT_N, + .gpio_card_ro = GPIO_NR_PALMTE2_SD_READONLY, + .gpio_power = GPIO_NR_PALMTE2_SD_POWER, }; /****************************************************************************** diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index 83d0208..4a9ca71 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -140,83 +140,11 @@ static unsigned long palmtx_pin_config[] __initdata = { /****************************************************************************** * SD/MMC card controller ******************************************************************************/ -static int palmtx_mci_init(struct device *dev, irq_handler_t palmtx_detect_int, - void *data) -{ - int err = 0; - - /* Setup an interrupt for detecting card insert/remove events */ - err = gpio_request(GPIO_NR_PALMTX_SD_DETECT_N, "SD IRQ"); - if (err) - goto err; - err = gpio_direction_input(GPIO_NR_PALMTX_SD_DETECT_N); - if (err) - goto err2; - err = request_irq(gpio_to_irq(GPIO_NR_PALMTX_SD_DETECT_N), - palmtx_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, - "SD/MMC card detect", data); - if (err) { - printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n", - __func__); - goto err2; - } - - err = gpio_request(GPIO_NR_PALMTX_SD_POWER, "SD_POWER"); - if (err) - goto err3; - err = gpio_direction_output(GPIO_NR_PALMTX_SD_POWER, 0); - if (err) - goto err4; - - err = gpio_request(GPIO_NR_PALMTX_SD_READONLY, "SD_READONLY"); - if (err) - goto err4; - err = gpio_direction_input(GPIO_NR_PALMTX_SD_READONLY); - if (err) - goto err5; - - printk(KERN_DEBUG "%s: irq registered\n", __func__); - - return 0; - -err5: - gpio_free(GPIO_NR_PALMTX_SD_READONLY); -err4: - gpio_free(GPIO_NR_PALMTX_SD_POWER); -err3: - free_irq(gpio_to_irq(GPIO_NR_PALMTX_SD_DETECT_N), data); -err2: - gpio_free(GPIO_NR_PALMTX_SD_DETECT_N); -err: - return err; -} - -static void palmtx_mci_exit(struct device *dev, void *data) -{ - gpio_free(GPIO_NR_PALMTX_SD_READONLY); - gpio_free(GPIO_NR_PALMTX_SD_POWER); - free_irq(gpio_to_irq(GPIO_NR_PALMTX_SD_DETECT_N), data); - gpio_free(GPIO_NR_PALMTX_SD_DETECT_N); -} - -static void palmtx_mci_power(struct device *dev, unsigned int vdd) -{ - struct pxamci_platform_data *p_d = dev->platform_data; - gpio_set_value(GPIO_NR_PALMTX_SD_POWER, p_d->ocr_mask & (1 << vdd)); -} - -static int palmtx_mci_get_ro(struct device *dev) -{ - return gpio_get_value(GPIO_NR_PALMTX_SD_READONLY); -} - static struct pxamci_platform_data palmtx_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .setpower = palmtx_mci_power, - .get_ro = palmtx_mci_get_ro, - .init = palmtx_mci_init, - .exit = palmtx_mci_exit, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_card_detect = GPIO_NR_PALMTX_SD_DETECT_N, + .gpio_card_ro = GPIO_NR_PALMTX_SD_READONLY, + .gpio_power = GPIO_NR_PALMTX_SD_POWER, }; /****************************************************************************** diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index c3645aa..d8fa53c 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -129,88 +129,14 @@ static unsigned long palmz72_pin_config[] __initdata = { /****************************************************************************** * SD/MMC card controller ******************************************************************************/ -static int palmz72_mci_init(struct device *dev, - irq_handler_t palmz72_detect_int, void *data) -{ - int err = 0; - - /* Setup an interrupt for detecting card insert/remove events */ - err = gpio_request(GPIO_NR_PALMZ72_SD_DETECT_N, "SD IRQ"); - if (err) - goto err; - err = gpio_direction_input(GPIO_NR_PALMZ72_SD_DETECT_N); - if (err) - goto err2; - err = request_irq(gpio_to_irq(GPIO_NR_PALMZ72_SD_DETECT_N), - palmz72_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, - "SD/MMC card detect", data); - if (err) { - printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n", - __func__); - goto err2; - } - - /* SD_POWER is not actually power, but it is more like chip - * select, i.e. it is inverted */ - - err = gpio_request(GPIO_NR_PALMZ72_SD_POWER_N, "SD_POWER"); - if (err) - goto err3; - err = gpio_direction_output(GPIO_NR_PALMZ72_SD_POWER_N, 0); - if (err) - goto err4; - err = gpio_request(GPIO_NR_PALMZ72_SD_RO, "SD_RO"); - if (err) - goto err4; - err = gpio_direction_input(GPIO_NR_PALMZ72_SD_RO); - if (err) - goto err5; - - printk(KERN_DEBUG "%s: irq registered\n", __func__); - - return 0; - -err5: - gpio_free(GPIO_NR_PALMZ72_SD_RO); -err4: - gpio_free(GPIO_NR_PALMZ72_SD_POWER_N); -err3: - free_irq(gpio_to_irq(GPIO_NR_PALMZ72_SD_DETECT_N), data); -err2: - gpio_free(GPIO_NR_PALMZ72_SD_DETECT_N); -err: - return err; -} - -static void palmz72_mci_exit(struct device *dev, void *data) -{ - gpio_free(GPIO_NR_PALMZ72_SD_POWER_N); - free_irq(gpio_to_irq(GPIO_NR_PALMZ72_SD_DETECT_N), data); - gpio_free(GPIO_NR_PALMZ72_SD_DETECT_N); - gpio_free(GPIO_NR_PALMZ72_SD_RO); -} - -static void palmz72_mci_power(struct device *dev, unsigned int vdd) -{ - struct pxamci_platform_data *p_d = dev->platform_data; - if (p_d->ocr_mask & (1 << vdd)) - gpio_set_value(GPIO_NR_PALMZ72_SD_POWER_N, 0); - else - gpio_set_value(GPIO_NR_PALMZ72_SD_POWER_N, 1); -} - -static int palmz72_mci_ro(struct device *dev) -{ - return gpio_get_value(GPIO_NR_PALMZ72_SD_RO); -} - +/* SD_POWER is not actually power, but it is more like chip + * select, i.e. it is inverted */ static struct pxamci_platform_data palmz72_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .setpower = palmz72_mci_power, - .get_ro = palmz72_mci_ro, - .init = palmz72_mci_init, - .exit = palmz72_mci_exit, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_card_detect = GPIO_NR_PALMZ72_SD_DETECT_N, + .gpio_card_ro = GPIO_NR_PALMZ72_SD_RO, + .gpio_power = GPIO_NR_PALMZ72_SD_POWER_N, + .gpio_power_invert = 1, }; /****************************************************************************** diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 01791d7..e211633 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -321,11 +321,14 @@ static void pcm990_mci_exit(struct device *dev, void *data) #define MSECS_PER_JIFFY (1000/HZ) static struct pxamci_platform_data pcm990_mci_platform_data = { - .detect_delay = 250 / MSECS_PER_JIFFY, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .init = pcm990_mci_init, - .setpower = pcm990_mci_setpower, - .exit = pcm990_mci_exit, + .detect_delay = 250 / MSECS_PER_JIFFY, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .init = pcm990_mci_init, + .setpower = pcm990_mci_setpower, + .exit = pcm990_mci_exit, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, }; static struct pxaohci_platform_data pcm990_ohci_platform_data = { diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 9352d4a..333b1dc 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -245,20 +245,10 @@ static inline void poodle_init_spi(void) {} * The card detect interrupt isn't debounced so we delay it by 250ms * to give the card a chance to fully insert/eject. */ -static struct pxamci_platform_data poodle_mci_platform_data; - static int poodle_mci_init(struct device *dev, irq_handler_t poodle_detect_int, void *data) { int err; - err = gpio_request(POODLE_GPIO_nSD_DETECT, "nSD_DETECT"); - if (err) - goto err_out; - - err = gpio_request(POODLE_GPIO_nSD_WP, "nSD_WP"); - if (err) - goto err_free_1; - err = gpio_request(POODLE_GPIO_SD_PWR, "SD_PWR"); if (err) goto err_free_2; @@ -267,34 +257,14 @@ static int poodle_mci_init(struct device *dev, irq_handler_t poodle_detect_int, if (err) goto err_free_3; - gpio_direction_input(POODLE_GPIO_nSD_DETECT); - gpio_direction_input(POODLE_GPIO_nSD_WP); - gpio_direction_output(POODLE_GPIO_SD_PWR, 0); gpio_direction_output(POODLE_GPIO_SD_PWR1, 0); - poodle_mci_platform_data.detect_delay = msecs_to_jiffies(250); - - err = request_irq(POODLE_IRQ_GPIO_nSD_DETECT, poodle_detect_int, - IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "MMC card detect", data); - if (err) { - pr_err("%s: MMC/SD: can't request MMC card detect IRQ\n", - __func__); - goto err_free_4; - } - return 0; -err_free_4: - gpio_free(POODLE_GPIO_SD_PWR1); err_free_3: gpio_free(POODLE_GPIO_SD_PWR); err_free_2: - gpio_free(POODLE_GPIO_nSD_WP); -err_free_1: - gpio_free(POODLE_GPIO_nSD_DETECT); -err_out: return err; } @@ -312,28 +282,20 @@ static void poodle_mci_setpower(struct device *dev, unsigned int vdd) } } -static int poodle_mci_get_ro(struct device *dev) -{ - return !!gpio_get_value(POODLE_GPIO_nSD_WP); - return GPLR(POODLE_GPIO_nSD_WP) & GPIO_bit(POODLE_GPIO_nSD_WP); -} - - static void poodle_mci_exit(struct device *dev, void *data) { - free_irq(POODLE_IRQ_GPIO_nSD_DETECT, data); gpio_free(POODLE_GPIO_SD_PWR1); gpio_free(POODLE_GPIO_SD_PWR); - gpio_free(POODLE_GPIO_nSD_WP); - gpio_free(POODLE_GPIO_nSD_DETECT); } static struct pxamci_platform_data poodle_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .init = poodle_mci_init, - .get_ro = poodle_mci_get_ro, - .setpower = poodle_mci_setpower, - .exit = poodle_mci_exit, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .init = poodle_mci_init, + .setpower = poodle_mci_setpower, + .exit = poodle_mci_exit, + .gpio_card_detect = POODLE_IRQ_GPIO_nSD_DETECT, + .gpio_card_ro = POODLE_GPIO_nSD_WP, + .gpio_power = -1, }; @@ -521,6 +483,7 @@ static void __init poodle_init(void) set_pxa_fb_parent(&poodle_locomo_device.dev); set_pxa_fb_info(&poodle_fb_info); pxa_set_udc_info(&udc_info); + poodle_mci_platform_data.detect_delay = msecs_to_jiffies(250); pxa_set_mci_info(&poodle_mci_platform_data); pxa_set_ficp_info(&poodle_ficp_platform_data); pxa_set_i2c_info(NULL); diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index dda310f..da85327 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -378,45 +378,6 @@ static inline void spitz_init_spi(void) {} * The card detect interrupt isn't debounced so we delay it by 250ms * to give the card a chance to fully insert/eject. */ - -static struct pxamci_platform_data spitz_mci_platform_data; - -static int spitz_mci_init(struct device *dev, irq_handler_t spitz_detect_int, void *data) -{ - int err; - - err = gpio_request(SPITZ_GPIO_nSD_DETECT, "nSD_DETECT"); - if (err) - goto err_out; - - err = gpio_request(SPITZ_GPIO_nSD_WP, "nSD_WP"); - if (err) - goto err_free_1; - - gpio_direction_input(SPITZ_GPIO_nSD_DETECT); - gpio_direction_input(SPITZ_GPIO_nSD_WP); - - spitz_mci_platform_data.detect_delay = msecs_to_jiffies(250); - - err = request_irq(SPITZ_IRQ_GPIO_nSD_DETECT, spitz_detect_int, - IRQF_DISABLED | IRQF_TRIGGER_RISING | - IRQF_TRIGGER_FALLING, - "MMC card detect", data); - if (err) { - pr_err("%s: MMC/SD: can't request MMC card detect IRQ\n", - __func__); - goto err_free_2; - } - return 0; - -err_free_2: - gpio_free(SPITZ_GPIO_nSD_WP); -err_free_1: - gpio_free(SPITZ_GPIO_nSD_DETECT); -err_out: - return err; -} - static void spitz_mci_setpower(struct device *dev, unsigned int vdd) { struct pxamci_platform_data* p_d = dev->platform_data; @@ -427,24 +388,12 @@ static void spitz_mci_setpower(struct device *dev, unsigned int vdd) spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0000); } -static int spitz_mci_get_ro(struct device *dev) -{ - return gpio_get_value(SPITZ_GPIO_nSD_WP); -} - -static void spitz_mci_exit(struct device *dev, void *data) -{ - free_irq(SPITZ_IRQ_GPIO_nSD_DETECT, data); - gpio_free(SPITZ_GPIO_nSD_WP); - gpio_free(SPITZ_GPIO_nSD_DETECT); -} - static struct pxamci_platform_data spitz_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .init = spitz_mci_init, - .get_ro = spitz_mci_get_ro, - .setpower = spitz_mci_setpower, - .exit = spitz_mci_exit, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .setpower = spitz_mci_setpower, + .gpio_card_detect = SPITZ_GPIO_nSD_DETECT, + .gpio_card_ro = SPITZ_GPIO_nSD_WP, + .gpio_power = -1, }; @@ -695,6 +644,7 @@ static void __init common_init(void) spitz_init_spi(); platform_add_devices(devices, ARRAY_SIZE(devices)); + spitz_mci_platform_data.detect_delay = msecs_to_jiffies(250); pxa_set_mci_info(&spitz_mci_platform_data); pxa_set_ohci_info(&spitz_ohci_platform_data); pxa_set_ficp_info(&spitz_ficp_platform_data); diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 117ad59..b56cc56 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -247,49 +247,10 @@ static struct pxa2xx_udc_mach_info udc_info __initdata = { /* * MMC/SD Device */ -static struct pxamci_platform_data tosa_mci_platform_data; - static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void *data) { int err; - tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250); - - err = gpio_request(TOSA_GPIO_nSD_DETECT, "MMC/SD card detect"); - if (err) { - printk(KERN_ERR "tosa_mci_init: can't request nSD_DETECT gpio\n"); - goto err_gpio_detect; - } - err = gpio_direction_input(TOSA_GPIO_nSD_DETECT); - if (err) - goto err_gpio_detect_dir; - - err = request_irq(TOSA_IRQ_GPIO_nSD_DETECT, tosa_detect_int, - IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "MMC/SD card detect", data); - if (err) { - printk(KERN_ERR "tosa_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); - goto err_irq; - } - - err = gpio_request(TOSA_GPIO_SD_WP, "SD Write Protect"); - if (err) { - printk(KERN_ERR "tosa_mci_init: can't request SD_WP gpio\n"); - goto err_gpio_wp; - } - err = gpio_direction_input(TOSA_GPIO_SD_WP); - if (err) - goto err_gpio_wp_dir; - - err = gpio_request(TOSA_GPIO_PWR_ON, "SD Power"); - if (err) { - printk(KERN_ERR "tosa_mci_init: can't request SD_PWR gpio\n"); - goto err_gpio_pwr; - } - err = gpio_direction_output(TOSA_GPIO_PWR_ON, 0); - if (err) - goto err_gpio_pwr_dir; - err = gpio_request(TOSA_GPIO_nSD_INT, "SD Int"); if (err) { printk(KERN_ERR "tosa_mci_init: can't request SD_PWR gpio\n"); @@ -304,51 +265,21 @@ static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void err_gpio_int_dir: gpio_free(TOSA_GPIO_nSD_INT); err_gpio_int: -err_gpio_pwr_dir: - gpio_free(TOSA_GPIO_PWR_ON); -err_gpio_pwr: -err_gpio_wp_dir: - gpio_free(TOSA_GPIO_SD_WP); -err_gpio_wp: - free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data); -err_irq: -err_gpio_detect_dir: - gpio_free(TOSA_GPIO_nSD_DETECT); -err_gpio_detect: return err; } -static void tosa_mci_setpower(struct device *dev, unsigned int vdd) -{ - struct pxamci_platform_data* p_d = dev->platform_data; - - if (( 1 << vdd) & p_d->ocr_mask) { - gpio_set_value(TOSA_GPIO_PWR_ON, 1); - } else { - gpio_set_value(TOSA_GPIO_PWR_ON, 0); - } -} - -static int tosa_mci_get_ro(struct device *dev) -{ - return gpio_get_value(TOSA_GPIO_SD_WP); -} - static void tosa_mci_exit(struct device *dev, void *data) { gpio_free(TOSA_GPIO_nSD_INT); - gpio_free(TOSA_GPIO_PWR_ON); - gpio_free(TOSA_GPIO_SD_WP); - free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data); - gpio_free(TOSA_GPIO_nSD_DETECT); } static struct pxamci_platform_data tosa_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .init = tosa_mci_init, - .get_ro = tosa_mci_get_ro, - .setpower = tosa_mci_setpower, - .exit = tosa_mci_exit, + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .init = tosa_mci_init, + .exit = tosa_mci_exit, + .gpio_card_detect = TOSA_GPIO_nSD_DETECT, + .gpio_card_ro = TOSA_GPIO_SD_WP, + .gpio_power = TOSA_GPIO_PWR_ON, }; /* @@ -910,6 +841,7 @@ static void __init tosa_init(void) dummy = gpiochip_reserve(TOSA_SCOOP_JC_GPIO_BASE, 12); dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16); + tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250); pxa_set_mci_info(&tosa_mci_platform_data); pxa_set_udc_info(&udc_info); pxa_set_ficp_info(&tosa_ficp_platform_data); diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 825f540..3229986 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -367,6 +367,9 @@ static struct pxamci_platform_data trizeps4_mci_platform_data = { .exit = trizeps4_mci_exit, .get_ro = NULL, /* write-protection not supported */ .setpower = NULL, /* power-switching not supported */ + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, }; /**************************************************************************** diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 218d200..09784d3 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -290,6 +290,9 @@ static struct pxamci_platform_data zylonite_mci_platform_data = { .init = zylonite_mci_init, .exit = zylonite_mci_exit, .get_ro = zylonite_mci_ro, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, }; static struct pxamci_platform_data zylonite_mci2_platform_data = { -- cgit v0.10.2 From 70f6d3e8a6670d1cccab5e206315b935eb62a08e Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Mon, 13 Jul 2009 22:57:56 +0800 Subject: [ARM] pxa/littleton: update littleton to use the new gpio_card_detect for mmc Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 55b3788..1384895 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -265,45 +265,12 @@ static inline void littleton_init_keypad(void) {} #endif #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) -static int littleton_mci_init(struct device *dev, - irq_handler_t littleton_detect_int, void *data) -{ - int err, gpio_cd = GPIO_MMC1_CARD_DETECT; - - err = gpio_request(gpio_cd, "mmc card detect"); - if (err) - goto err_request_cd; - - gpio_direction_input(gpio_cd); - - err = request_irq(gpio_to_irq(gpio_cd), littleton_detect_int, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "mmc card detect", data); - if (err) { - dev_err(dev, "failed to request card detect IRQ\n"); - goto err_request_irq; - } - return 0; - -err_request_irq: - gpio_free(gpio_cd); -err_request_cd: - return err; -} - -static void littleton_mci_exit(struct device *dev, void *data) -{ - int gpio_cd = GPIO_MMC1_CARD_DETECT; - - free_irq(gpio_to_irq(gpio_cd), data); - gpio_free(gpio_cd); -} - static struct pxamci_platform_data littleton_mci_platform_data = { - .detect_delay = 20, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .init = littleton_mci_init, - .exit = littleton_mci_exit, + .detect_delay = 20, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_card_detect = GPIO_MMC1_CARD_DETECT, + .gpio_card_ro = -1, + .gpio_power = -1, }; static void __init littleton_init_mmc(void) -- cgit v0.10.2 From 0d95c1fa5661b11cf7777af2613563cc3c683d8d Mon Sep 17 00:00:00 2001 From: Daniel Ribeiro Date: Tue, 23 Jun 2009 12:39:25 -0300 Subject: [ARM] pxa/ezx: set IRQ_BOARD_END for EZX Signed-off-by: Daniel Ribeiro Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 626cecb..32e44b3 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -463,6 +463,7 @@ config PXA_EZX select PXA27x select IWMMXT select HAVE_PWM + select PXA_HAVE_BOARD_IRQS config MACH_EZX_A780 bool "Motorola EZX A780" diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index 7af0de4..567204c 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -129,6 +129,8 @@ #define IRQ_BOARD_END (IRQ_BOARD_START + 70) #elif defined(CONFIG_MACH_ZYLONITE) #define IRQ_BOARD_END (IRQ_BOARD_START + 32) +#elif defined(CONFIG_PXA_EZX) +#define IRQ_BOARD_END (IRQ_BOARD_START + 23) #else #define IRQ_BOARD_END (IRQ_BOARD_START + 16) #endif -- cgit v0.10.2 From 53740df16f42163255031d24d99ba207a9ac81a9 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Wed, 17 Jun 2009 10:32:54 +0200 Subject: [ARM] pxa/colibri: add NAND config for Colibri PXA3xx boards NAND feature will be enabled when the appropriate config option is set. Signed-off-by: Daniel Mack Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c index 7c9c34c..37c239c 100644 --- a/arch/arm/mach-pxa/colibri-pxa300.c +++ b/arch/arm/mach-pxa/colibri-pxa300.c @@ -172,6 +172,7 @@ void __init colibri_pxa300_init(void) { colibri_pxa300_init_eth(); colibri_pxa300_init_ohci(); + colibri_pxa3xx_init_nand(); colibri_pxa300_init_lcd(); colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO)); colibri_pxa310_init_ac97(); diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c index a18d37b..458c1a1 100644 --- a/arch/arm/mach-pxa/colibri-pxa320.c +++ b/arch/arm/mach-pxa/colibri-pxa320.c @@ -168,6 +168,7 @@ void __init colibri_pxa320_init(void) { colibri_pxa320_init_eth(); colibri_pxa320_init_ohci(); + colibri_pxa3xx_init_nand(); colibri_pxa320_init_lcd(); colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO)); colibri_pxa320_init_ac97(); diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index 2c846bb..efebaf4 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "generic.h" #include "devices.h" @@ -157,3 +158,43 @@ void __init colibri_pxa3xx_init_lcd(int bl_pin) } #endif +#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE) +static struct mtd_partition colibri_nand_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "reserved", + .offset = MTDPART_OFS_APPEND, + .size = SZ_1M, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "fs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct pxa3xx_nand_platform_data colibri_nand_info = { + .enable_arbiter = 1, + .keep_config = 1, + .parts = colibri_nand_partitions, + .nr_parts = ARRAY_SIZE(colibri_nand_partitions), +}; + +void __init colibri_pxa3xx_init_nand(void) +{ + pxa3xx_set_nand_info(&colibri_nand_info); +} +#endif + diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h index a88d7ca..811743c 100644 --- a/arch/arm/mach-pxa/include/mach/colibri.h +++ b/arch/arm/mach-pxa/include/mach/colibri.h @@ -23,6 +23,12 @@ static inline void colibri_pxa3xx_init_lcd(int bl_pin) {} extern void colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data); #endif +#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE) +extern void colibri_pxa3xx_init_nand(void); +#else +static inline void colibri_pxa3xx_init_nand(void) {} +#endif + /* physical memory regions */ #define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ -- cgit v0.10.2 From ecc85e166fbec0378215aab13925b0e980a48d1e Mon Sep 17 00:00:00 2001 From: Alex Roman Date: Fri, 3 Jul 2009 14:58:59 +0800 Subject: [ARM] pxa/colibri: add UART MFP configuration for the PXA320 module This patch configures the MFP pads for UART1, UART2, UART3 for the Toradex Colibri PXA320 module. Previously they were just not configured resulting in just the first UART working because it was the only one that was configured by the bootloader (Toradex EBOOT in our case). This patch is against vanilla 2.6.30 and has been tested with the Toradex Orchid carrier board (all three UARTs were functional). Signed-off-by: Alex Roman Acked-by: Daniel Mack Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c index 458c1a1..4945728 100644 --- a/arch/arm/mach-pxa/colibri-pxa320.c +++ b/arch/arm/mach-pxa/colibri-pxa320.c @@ -164,6 +164,37 @@ static inline void __init colibri_pxa320_init_ac97(void) static inline void colibri_pxa320_init_ac97(void) {} #endif +/* + * The following configuration is verified to work with the Toradex Orchid + * carrier board + */ +static mfp_cfg_t colibri_pxa320_uart_pin_config[] __initdata = { + /* UART 1 configuration (may be set by bootloader) */ + GPIO99_UART1_CTS, + GPIO104_UART1_RTS, + GPIO97_UART1_RXD, + GPIO98_UART1_TXD, + GPIO101_UART1_DTR, + GPIO103_UART1_DSR, + GPIO100_UART1_DCD, + GPIO102_UART1_RI, + + /* UART 2 configuration */ + GPIO109_UART2_CTS, + GPIO112_UART2_RTS, + GPIO110_UART2_RXD, + GPIO111_UART2_TXD, + + /* UART 3 configuration */ + GPIO30_UART3_RXD, + GPIO31_UART3_TXD, +}; + +static void __init colibri_pxa320_init_uart(void) +{ + pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_uart_pin_config)); +} + void __init colibri_pxa320_init(void) { colibri_pxa320_init_eth(); @@ -174,6 +205,7 @@ void __init colibri_pxa320_init(void) colibri_pxa320_init_ac97(); colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config), mfp_to_gpio(MFP_PIN_GPIO28)); + colibri_pxa320_init_uart(); } MACHINE_START(COLIBRI320, "Toradex Colibri PXA320") -- cgit v0.10.2 From 4a3d3abe91963d7b3e562e70fc6c5c9d3f76fb30 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 13 May 2009 11:33:43 +0200 Subject: [ARM] pxa/pcm990: convert pcm990 to soc-camera as platform-device Signed-off-by: Guennadi Liakhovetski Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index e211633..bbda570 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -430,25 +430,56 @@ static void pcm990_camera_free_bus(struct soc_camera_link *link) gpio_bus_switch = -EINVAL; } -static struct soc_camera_link iclink = { - .bus_id = 0, /* Must match with the camera ID above */ - .query_bus_param = pcm990_camera_query_bus_param, - .set_bus_param = pcm990_camera_set_bus_param, - .free_bus = pcm990_camera_free_bus, -}; - /* Board I2C devices. */ static struct i2c_board_info __initdata pcm990_i2c_devices[] = { { /* Must initialize before the camera(s) */ I2C_BOARD_INFO("pca9536", 0x41), .platform_data = &pca9536_data, - }, { + }, +}; + +static struct i2c_board_info pcm990_camera_i2c[] = { + { I2C_BOARD_INFO("mt9v022", 0x48), - .platform_data = &iclink, /* With extender */ }, { I2C_BOARD_INFO("mt9m001", 0x5d), - .platform_data = &iclink, /* With extender */ + }, +}; + +static struct soc_camera_link iclink[] = { + { + .bus_id = 0, /* Must match with the camera ID */ + .board_info = &pcm990_camera_i2c[0], + .i2c_adapter_id = 0, + .query_bus_param = pcm990_camera_query_bus_param, + .set_bus_param = pcm990_camera_set_bus_param, + .free_bus = pcm990_camera_free_bus, + .module_name = "mt9v022", + }, { + .bus_id = 0, /* Must match with the camera ID */ + .board_info = &pcm990_camera_i2c[1], + .i2c_adapter_id = 0, + .query_bus_param = pcm990_camera_query_bus_param, + .set_bus_param = pcm990_camera_set_bus_param, + .free_bus = pcm990_camera_free_bus, + .module_name = "mt9m001", + }, +}; + +static struct platform_device pcm990_camera[] = { + { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &iclink[0], + }, + }, { + .name = "soc-camera-pdrv", + .id = 1, + .dev = { + .platform_data = &iclink[1], + }, }, }; #endif /* CONFIG_VIDEO_PXA27x ||CONFIG_VIDEO_PXA27x_MODULE */ @@ -504,6 +535,9 @@ void __init pcm990_baseboard_init(void) pxa_set_camera_info(&pcm990_pxacamera_platform_data); i2c_register_board_info(0, ARRAY_AND_SIZE(pcm990_i2c_devices)); + + platform_device_register(&pcm990_camera[0]); + platform_device_register(&pcm990_camera[1]); #endif printk(KERN_INFO "PCM-990 Evaluation baseboard initialized\n"); -- cgit v0.10.2 From a48c24a696f0d93c49f913b7818e9819612b1f4e Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 24 Apr 2009 18:40:27 +0200 Subject: [ARM] pxa/mioa701: convert mioa701 to the new platform-device soc-camera interface Signed-off-by: Guennadi Liakhovetski Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index a8122ec..3cab452 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -708,19 +708,20 @@ static struct i2c_board_info __initdata mioa701_pi2c_devices[] = { }, }; -static struct soc_camera_link iclink = { - .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */ -}; - /* Board I2C devices. */ static struct i2c_board_info __initdata mioa701_i2c_devices[] = { { - /* Must initialize before the camera(s) */ I2C_BOARD_INFO("mt9m111", 0x5d), - .platform_data = &iclink, }, }; +static struct soc_camera_link iclink = { + .bus_id = 0, /* Match id in pxa27x_device_camera in device.c */ + .board_info = &mioa701_i2c_devices[0], + .i2c_adapter_id = 0, + .module_name = "mt9m111", +}; + struct i2c_pxa_platform_data i2c_pdata = { .fast_mode = 1, }; @@ -754,6 +755,7 @@ MIO_SIMPLE_DEV(pxa2xx_pcm, "pxa2xx-pcm", NULL) MIO_SIMPLE_DEV(mioa701_sound, "mioa701-wm9713", NULL) MIO_SIMPLE_DEV(mioa701_board, "mioa701-board", NULL) MIO_SIMPLE_DEV(gpio_vbus, "gpio-vbus", &gpio_vbus_data); +MIO_SIMPLE_DEV(mioa701_camera, "soc-camera-pdrv",&iclink); static struct platform_device *devices[] __initdata = { &mioa701_gpio_keys, @@ -764,6 +766,7 @@ static struct platform_device *devices[] __initdata = { &power_dev, &strataflash, &gpio_vbus, + &mioa701_camera, &mioa701_board, }; @@ -813,7 +816,6 @@ static void __init mioa701_machine_init(void) pxa_set_i2c_info(&i2c_pdata); pxa27x_set_i2c_power_info(NULL); pxa_set_camera_info(&mioa701_pxacamera_platform_data); - i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices)); } static void mioa701_machine_exit(void) -- cgit v0.10.2 From 489db6a662af5ca1b6574bae2d974017346bb983 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 12 May 2009 18:12:29 +0200 Subject: [ARM] pxa/em-x270: convert em-x270 to soc-camera as platform-device Signed-off-by: Guennadi Liakhovetski Acked-by: Mike Rapoport Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index e0121f4..2ed1dfe 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -1025,22 +1025,32 @@ static int em_x270_sensor_power(struct device *dev, int on) return 0; } -static struct soc_camera_link iclink = { - .bus_id = 0, - .power = em_x270_sensor_power, -}; - static struct i2c_board_info em_x270_i2c_cam_info[] = { { I2C_BOARD_INFO("mt9m111", 0x48), + }, +}; + +static struct soc_camera_link iclink = { + .bus_id = 0, + .power = em_x270_sensor_power, + .board_info = &em_x270_i2c_cam_info[0], + .i2c_adapter_id = 0, + .module_name = "mt9m111", +}; + +static struct platform_device em_x270_camera = { + .name = "soc-camera-pdrv", + .id = -1, + .dev = { .platform_data = &iclink, }, }; static void __init em_x270_init_camera(void) { - i2c_register_board_info(0, ARRAY_AND_SIZE(em_x270_i2c_cam_info)); pxa_set_camera_info(&em_x270_camera_platform_data); + platform_device_register(&em_x270_camera); } #else static inline void em_x270_init_camera(void) {} -- cgit v0.10.2 From 9cf97b1beeb8596b1e923642e3f2af949fc68082 Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Sun, 26 Jul 2009 13:48:39 +0300 Subject: [ARM] pxa/em-x270: remove debug leftovers Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 2ed1dfe..8614cab 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -1258,7 +1258,6 @@ static void __init em_x270_init_i2c(void) static void __init em_x270_module_init(void) { - pr_info("%s\n", __func__); pxa2xx_mfp_config(ARRAY_AND_SIZE(em_x270_pin_config)); mmc_cd = GPIO13_MMC_CD; @@ -1270,7 +1269,6 @@ static void __init em_x270_module_init(void) static void __init em_x270_exeda_init(void) { - pr_info("%s\n", __func__); pxa2xx_mfp_config(ARRAY_AND_SIZE(exeda_pin_config)); mmc_cd = GPIO114_MMC_CD; -- cgit v0.10.2 From 100a1d250d3806caa97b08d04cb558372c8e8097 Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Sun, 26 Jul 2009 13:48:40 +0300 Subject: [ARM] pxa/em-x270: add vcc_core regulator Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 8614cab..aec7f42 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -1116,6 +1116,7 @@ REGULATOR_CONSUMER(ldo5, NULL, "vcc cam"); REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio"); REGULATOR_CONSUMER(ldo12, NULL, "vcc usb"); REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs"); +REGULATOR_CONSUMER(buck2, NULL, "vcc_core"); #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \ static struct regulator_init_data _ldo##_data = { \ @@ -1138,6 +1139,7 @@ REGULATOR_INIT(ldo10, 2000000, 3200000, REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE); REGULATOR_INIT(ldo12, 3000000, 3000000, REGULATOR_CHANGE_STATUS); REGULATOR_INIT(ldo19, 3200000, 3200000, REGULATOR_CHANGE_STATUS); +REGULATOR_INIT(buck2, 1000000, 1650000, REGULATOR_CHANGE_VOLTAGE); struct led_info em_x270_led_info = { .name = "em-x270:orange", @@ -1207,6 +1209,8 @@ struct da903x_subdev_info em_x270_da9030_subdevs[] = { DA9030_LDO(12), DA9030_LDO(19), + DA9030_SUBDEV(regulator, BUCK2, &buck2_data), + DA9030_SUBDEV(led, LED_PC, &em_x270_led_info), DA9030_SUBDEV(backlight, WLED, &em_x270_led_info), DA9030_SUBDEV(battery, BAT, &em_x270_batterty_info), -- cgit v0.10.2 From a2099e49f4f8728b0c0301a4e3eb650644ee9206 Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Mon, 3 Aug 2009 12:07:52 +0300 Subject: [ARM] pxa/cm-x270: add libertas device registration v2 changes: - use gpio_to_irq instead of IRQ_GPIO - check gpio_direction_output return value to be on the safe side :) Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index 5929218..eea78b6 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c @@ -13,13 +13,18 @@ #include #include #include +#include #include #include